base.c 79 KB

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  1. /*-
  2. * Copyright (c) 2002-2005 Sam Leffler, Errno Consulting
  3. * Copyright (c) 2004-2005 Atheros Communications, Inc.
  4. * Copyright (c) 2006 Devicescape Software, Inc.
  5. * Copyright (c) 2007 Jiri Slaby <jirislaby@gmail.com>
  6. * Copyright (c) 2007 Luis R. Rodriguez <mcgrof@winlab.rutgers.edu>
  7. *
  8. * All rights reserved.
  9. *
  10. * Redistribution and use in source and binary forms, with or without
  11. * modification, are permitted provided that the following conditions
  12. * are met:
  13. * 1. Redistributions of source code must retain the above copyright
  14. * notice, this list of conditions and the following disclaimer,
  15. * without modification.
  16. * 2. Redistributions in binary form must reproduce at minimum a disclaimer
  17. * similar to the "NO WARRANTY" disclaimer below ("Disclaimer") and any
  18. * redistribution must be conditioned upon including a substantially
  19. * similar Disclaimer requirement for further binary redistribution.
  20. * 3. Neither the names of the above-listed copyright holders nor the names
  21. * of any contributors may be used to endorse or promote products derived
  22. * from this software without specific prior written permission.
  23. *
  24. * Alternatively, this software may be distributed under the terms of the
  25. * GNU General Public License ("GPL") version 2 as published by the Free
  26. * Software Foundation.
  27. *
  28. * NO WARRANTY
  29. * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  30. * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  31. * LIMITED TO, THE IMPLIED WARRANTIES OF NONINFRINGEMENT, MERCHANTIBILITY
  32. * AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL
  33. * THE COPYRIGHT HOLDERS OR CONTRIBUTORS BE LIABLE FOR SPECIAL, EXEMPLARY,
  34. * OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
  35. * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
  36. * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER
  37. * IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
  38. * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
  39. * THE POSSIBILITY OF SUCH DAMAGES.
  40. *
  41. */
  42. #include <linux/module.h>
  43. #include <linux/delay.h>
  44. #include <linux/dma-mapping.h>
  45. #include <linux/hardirq.h>
  46. #include <linux/if.h>
  47. #include <linux/io.h>
  48. #include <linux/netdevice.h>
  49. #include <linux/cache.h>
  50. #include <linux/ethtool.h>
  51. #include <linux/uaccess.h>
  52. #include <linux/slab.h>
  53. #include <linux/etherdevice.h>
  54. #include <net/ieee80211_radiotap.h>
  55. #include <asm/unaligned.h>
  56. #include "base.h"
  57. #include "reg.h"
  58. #include "debug.h"
  59. #include "ani.h"
  60. #define CREATE_TRACE_POINTS
  61. #include "trace.h"
  62. int ath5k_modparam_nohwcrypt;
  63. module_param_named(nohwcrypt, ath5k_modparam_nohwcrypt, bool, S_IRUGO);
  64. MODULE_PARM_DESC(nohwcrypt, "Disable hardware encryption.");
  65. static int modparam_all_channels;
  66. module_param_named(all_channels, modparam_all_channels, bool, S_IRUGO);
  67. MODULE_PARM_DESC(all_channels, "Expose all channels the device can use.");
  68. static int modparam_fastchanswitch;
  69. module_param_named(fastchanswitch, modparam_fastchanswitch, bool, S_IRUGO);
  70. MODULE_PARM_DESC(fastchanswitch, "Enable fast channel switching for AR2413/AR5413 radios.");
  71. /* Module info */
  72. MODULE_AUTHOR("Jiri Slaby");
  73. MODULE_AUTHOR("Nick Kossifidis");
  74. MODULE_DESCRIPTION("Support for 5xxx series of Atheros 802.11 wireless LAN cards.");
  75. MODULE_SUPPORTED_DEVICE("Atheros 5xxx WLAN cards");
  76. MODULE_LICENSE("Dual BSD/GPL");
  77. static int ath5k_init(struct ieee80211_hw *hw);
  78. static int ath5k_reset(struct ath5k_hw *ah, struct ieee80211_channel *chan,
  79. bool skip_pcu);
  80. /* Known SREVs */
  81. static const struct ath5k_srev_name srev_names[] = {
  82. #ifdef CONFIG_ATHEROS_AR231X
  83. { "5312", AR5K_VERSION_MAC, AR5K_SREV_AR5312_R2 },
  84. { "5312", AR5K_VERSION_MAC, AR5K_SREV_AR5312_R7 },
  85. { "2313", AR5K_VERSION_MAC, AR5K_SREV_AR2313_R8 },
  86. { "2315", AR5K_VERSION_MAC, AR5K_SREV_AR2315_R6 },
  87. { "2315", AR5K_VERSION_MAC, AR5K_SREV_AR2315_R7 },
  88. { "2317", AR5K_VERSION_MAC, AR5K_SREV_AR2317_R1 },
  89. { "2317", AR5K_VERSION_MAC, AR5K_SREV_AR2317_R2 },
  90. #else
  91. { "5210", AR5K_VERSION_MAC, AR5K_SREV_AR5210 },
  92. { "5311", AR5K_VERSION_MAC, AR5K_SREV_AR5311 },
  93. { "5311A", AR5K_VERSION_MAC, AR5K_SREV_AR5311A },
  94. { "5311B", AR5K_VERSION_MAC, AR5K_SREV_AR5311B },
  95. { "5211", AR5K_VERSION_MAC, AR5K_SREV_AR5211 },
  96. { "5212", AR5K_VERSION_MAC, AR5K_SREV_AR5212 },
  97. { "5213", AR5K_VERSION_MAC, AR5K_SREV_AR5213 },
  98. { "5213A", AR5K_VERSION_MAC, AR5K_SREV_AR5213A },
  99. { "2413", AR5K_VERSION_MAC, AR5K_SREV_AR2413 },
  100. { "2414", AR5K_VERSION_MAC, AR5K_SREV_AR2414 },
  101. { "5424", AR5K_VERSION_MAC, AR5K_SREV_AR5424 },
  102. { "5413", AR5K_VERSION_MAC, AR5K_SREV_AR5413 },
  103. { "5414", AR5K_VERSION_MAC, AR5K_SREV_AR5414 },
  104. { "2415", AR5K_VERSION_MAC, AR5K_SREV_AR2415 },
  105. { "5416", AR5K_VERSION_MAC, AR5K_SREV_AR5416 },
  106. { "5418", AR5K_VERSION_MAC, AR5K_SREV_AR5418 },
  107. { "2425", AR5K_VERSION_MAC, AR5K_SREV_AR2425 },
  108. { "2417", AR5K_VERSION_MAC, AR5K_SREV_AR2417 },
  109. #endif
  110. { "xxxxx", AR5K_VERSION_MAC, AR5K_SREV_UNKNOWN },
  111. { "5110", AR5K_VERSION_RAD, AR5K_SREV_RAD_5110 },
  112. { "5111", AR5K_VERSION_RAD, AR5K_SREV_RAD_5111 },
  113. { "5111A", AR5K_VERSION_RAD, AR5K_SREV_RAD_5111A },
  114. { "2111", AR5K_VERSION_RAD, AR5K_SREV_RAD_2111 },
  115. { "5112", AR5K_VERSION_RAD, AR5K_SREV_RAD_5112 },
  116. { "5112A", AR5K_VERSION_RAD, AR5K_SREV_RAD_5112A },
  117. { "5112B", AR5K_VERSION_RAD, AR5K_SREV_RAD_5112B },
  118. { "2112", AR5K_VERSION_RAD, AR5K_SREV_RAD_2112 },
  119. { "2112A", AR5K_VERSION_RAD, AR5K_SREV_RAD_2112A },
  120. { "2112B", AR5K_VERSION_RAD, AR5K_SREV_RAD_2112B },
  121. { "2413", AR5K_VERSION_RAD, AR5K_SREV_RAD_2413 },
  122. { "5413", AR5K_VERSION_RAD, AR5K_SREV_RAD_5413 },
  123. { "5424", AR5K_VERSION_RAD, AR5K_SREV_RAD_5424 },
  124. { "5133", AR5K_VERSION_RAD, AR5K_SREV_RAD_5133 },
  125. #ifdef CONFIG_ATHEROS_AR231X
  126. { "2316", AR5K_VERSION_RAD, AR5K_SREV_RAD_2316 },
  127. { "2317", AR5K_VERSION_RAD, AR5K_SREV_RAD_2317 },
  128. #endif
  129. { "xxxxx", AR5K_VERSION_RAD, AR5K_SREV_UNKNOWN },
  130. };
  131. static const struct ieee80211_rate ath5k_rates[] = {
  132. { .bitrate = 10,
  133. .hw_value = ATH5K_RATE_CODE_1M, },
  134. { .bitrate = 20,
  135. .hw_value = ATH5K_RATE_CODE_2M,
  136. .hw_value_short = ATH5K_RATE_CODE_2M | AR5K_SET_SHORT_PREAMBLE,
  137. .flags = IEEE80211_RATE_SHORT_PREAMBLE },
  138. { .bitrate = 55,
  139. .hw_value = ATH5K_RATE_CODE_5_5M,
  140. .hw_value_short = ATH5K_RATE_CODE_5_5M | AR5K_SET_SHORT_PREAMBLE,
  141. .flags = IEEE80211_RATE_SHORT_PREAMBLE },
  142. { .bitrate = 110,
  143. .hw_value = ATH5K_RATE_CODE_11M,
  144. .hw_value_short = ATH5K_RATE_CODE_11M | AR5K_SET_SHORT_PREAMBLE,
  145. .flags = IEEE80211_RATE_SHORT_PREAMBLE },
  146. { .bitrate = 60,
  147. .hw_value = ATH5K_RATE_CODE_6M,
  148. .flags = 0 },
  149. { .bitrate = 90,
  150. .hw_value = ATH5K_RATE_CODE_9M,
  151. .flags = 0 },
  152. { .bitrate = 120,
  153. .hw_value = ATH5K_RATE_CODE_12M,
  154. .flags = 0 },
  155. { .bitrate = 180,
  156. .hw_value = ATH5K_RATE_CODE_18M,
  157. .flags = 0 },
  158. { .bitrate = 240,
  159. .hw_value = ATH5K_RATE_CODE_24M,
  160. .flags = 0 },
  161. { .bitrate = 360,
  162. .hw_value = ATH5K_RATE_CODE_36M,
  163. .flags = 0 },
  164. { .bitrate = 480,
  165. .hw_value = ATH5K_RATE_CODE_48M,
  166. .flags = 0 },
  167. { .bitrate = 540,
  168. .hw_value = ATH5K_RATE_CODE_54M,
  169. .flags = 0 },
  170. /* XR missing */
  171. };
  172. static inline u64 ath5k_extend_tsf(struct ath5k_hw *ah, u32 rstamp)
  173. {
  174. u64 tsf = ath5k_hw_get_tsf64(ah);
  175. if ((tsf & 0x7fff) < rstamp)
  176. tsf -= 0x8000;
  177. return (tsf & ~0x7fff) | rstamp;
  178. }
  179. const char *
  180. ath5k_chip_name(enum ath5k_srev_type type, u_int16_t val)
  181. {
  182. const char *name = "xxxxx";
  183. unsigned int i;
  184. for (i = 0; i < ARRAY_SIZE(srev_names); i++) {
  185. if (srev_names[i].sr_type != type)
  186. continue;
  187. if ((val & 0xf0) == srev_names[i].sr_val)
  188. name = srev_names[i].sr_name;
  189. if ((val & 0xff) == srev_names[i].sr_val) {
  190. name = srev_names[i].sr_name;
  191. break;
  192. }
  193. }
  194. return name;
  195. }
  196. static unsigned int ath5k_ioread32(void *hw_priv, u32 reg_offset)
  197. {
  198. struct ath5k_hw *ah = (struct ath5k_hw *) hw_priv;
  199. return ath5k_hw_reg_read(ah, reg_offset);
  200. }
  201. static void ath5k_iowrite32(void *hw_priv, u32 val, u32 reg_offset)
  202. {
  203. struct ath5k_hw *ah = (struct ath5k_hw *) hw_priv;
  204. ath5k_hw_reg_write(ah, val, reg_offset);
  205. }
  206. static const struct ath_ops ath5k_common_ops = {
  207. .read = ath5k_ioread32,
  208. .write = ath5k_iowrite32,
  209. };
  210. /***********************\
  211. * Driver Initialization *
  212. \***********************/
  213. static int ath5k_reg_notifier(struct wiphy *wiphy, struct regulatory_request *request)
  214. {
  215. struct ieee80211_hw *hw = wiphy_to_ieee80211_hw(wiphy);
  216. struct ath5k_hw *ah = hw->priv;
  217. struct ath_regulatory *regulatory = ath5k_hw_regulatory(ah);
  218. return ath_reg_notifier_apply(wiphy, request, regulatory);
  219. }
  220. /********************\
  221. * Channel/mode setup *
  222. \********************/
  223. /*
  224. * Returns true for the channel numbers used without all_channels modparam.
  225. */
  226. static bool ath5k_is_standard_channel(short chan, enum ieee80211_band band)
  227. {
  228. if (band == IEEE80211_BAND_2GHZ && chan <= 14)
  229. return true;
  230. return /* UNII 1,2 */
  231. (((chan & 3) == 0 && chan >= 36 && chan <= 64) ||
  232. /* midband */
  233. ((chan & 3) == 0 && chan >= 100 && chan <= 140) ||
  234. /* UNII-3 */
  235. ((chan & 3) == 1 && chan >= 149 && chan <= 165) ||
  236. /* 802.11j 5.030-5.080 GHz (20MHz) */
  237. (chan == 8 || chan == 12 || chan == 16) ||
  238. /* 802.11j 4.9GHz (20MHz) */
  239. (chan == 184 || chan == 188 || chan == 192 || chan == 196));
  240. }
  241. static unsigned int
  242. ath5k_setup_channels(struct ath5k_hw *ah, struct ieee80211_channel *channels,
  243. unsigned int mode, unsigned int max)
  244. {
  245. unsigned int count, size, chfreq, freq, ch;
  246. enum ieee80211_band band;
  247. switch (mode) {
  248. case AR5K_MODE_11A:
  249. /* 1..220, but 2GHz frequencies are filtered by check_channel */
  250. size = 220;
  251. chfreq = CHANNEL_5GHZ;
  252. band = IEEE80211_BAND_5GHZ;
  253. break;
  254. case AR5K_MODE_11B:
  255. case AR5K_MODE_11G:
  256. size = 26;
  257. chfreq = CHANNEL_2GHZ;
  258. band = IEEE80211_BAND_2GHZ;
  259. break;
  260. default:
  261. ATH5K_WARN(ah, "bad mode, not copying channels\n");
  262. return 0;
  263. }
  264. count = 0;
  265. for (ch = 1; ch <= size && count < max; ch++) {
  266. freq = ieee80211_channel_to_frequency(ch, band);
  267. if (freq == 0) /* mapping failed - not a standard channel */
  268. continue;
  269. /* Check if channel is supported by the chipset */
  270. if (!ath5k_channel_ok(ah, freq, chfreq))
  271. continue;
  272. if (!modparam_all_channels &&
  273. !ath5k_is_standard_channel(ch, band))
  274. continue;
  275. /* Write channel info and increment counter */
  276. channels[count].center_freq = freq;
  277. channels[count].band = band;
  278. switch (mode) {
  279. case AR5K_MODE_11A:
  280. case AR5K_MODE_11G:
  281. channels[count].hw_value = chfreq | CHANNEL_OFDM;
  282. break;
  283. case AR5K_MODE_11B:
  284. channels[count].hw_value = CHANNEL_B;
  285. }
  286. count++;
  287. }
  288. return count;
  289. }
  290. static void
  291. ath5k_setup_rate_idx(struct ath5k_hw *ah, struct ieee80211_supported_band *b)
  292. {
  293. u8 i;
  294. for (i = 0; i < AR5K_MAX_RATES; i++)
  295. ah->rate_idx[b->band][i] = -1;
  296. for (i = 0; i < b->n_bitrates; i++) {
  297. ah->rate_idx[b->band][b->bitrates[i].hw_value] = i;
  298. if (b->bitrates[i].hw_value_short)
  299. ah->rate_idx[b->band][b->bitrates[i].hw_value_short] = i;
  300. }
  301. }
  302. static int
  303. ath5k_setup_bands(struct ieee80211_hw *hw)
  304. {
  305. struct ath5k_hw *ah = hw->priv;
  306. struct ieee80211_supported_band *sband;
  307. int max_c, count_c = 0;
  308. int i;
  309. BUILD_BUG_ON(ARRAY_SIZE(ah->sbands) < IEEE80211_NUM_BANDS);
  310. max_c = ARRAY_SIZE(ah->channels);
  311. /* 2GHz band */
  312. sband = &ah->sbands[IEEE80211_BAND_2GHZ];
  313. sband->band = IEEE80211_BAND_2GHZ;
  314. sband->bitrates = &ah->rates[IEEE80211_BAND_2GHZ][0];
  315. if (test_bit(AR5K_MODE_11G, ah->ah_capabilities.cap_mode)) {
  316. /* G mode */
  317. memcpy(sband->bitrates, &ath5k_rates[0],
  318. sizeof(struct ieee80211_rate) * 12);
  319. sband->n_bitrates = 12;
  320. sband->channels = ah->channels;
  321. sband->n_channels = ath5k_setup_channels(ah, sband->channels,
  322. AR5K_MODE_11G, max_c);
  323. hw->wiphy->bands[IEEE80211_BAND_2GHZ] = sband;
  324. count_c = sband->n_channels;
  325. max_c -= count_c;
  326. } else if (test_bit(AR5K_MODE_11B, ah->ah_capabilities.cap_mode)) {
  327. /* B mode */
  328. memcpy(sband->bitrates, &ath5k_rates[0],
  329. sizeof(struct ieee80211_rate) * 4);
  330. sband->n_bitrates = 4;
  331. /* 5211 only supports B rates and uses 4bit rate codes
  332. * (e.g normally we have 0x1B for 1M, but on 5211 we have 0x0B)
  333. * fix them up here:
  334. */
  335. if (ah->ah_version == AR5K_AR5211) {
  336. for (i = 0; i < 4; i++) {
  337. sband->bitrates[i].hw_value =
  338. sband->bitrates[i].hw_value & 0xF;
  339. sband->bitrates[i].hw_value_short =
  340. sband->bitrates[i].hw_value_short & 0xF;
  341. }
  342. }
  343. sband->channels = ah->channels;
  344. sband->n_channels = ath5k_setup_channels(ah, sband->channels,
  345. AR5K_MODE_11B, max_c);
  346. hw->wiphy->bands[IEEE80211_BAND_2GHZ] = sband;
  347. count_c = sband->n_channels;
  348. max_c -= count_c;
  349. }
  350. ath5k_setup_rate_idx(ah, sband);
  351. /* 5GHz band, A mode */
  352. if (test_bit(AR5K_MODE_11A, ah->ah_capabilities.cap_mode)) {
  353. sband = &ah->sbands[IEEE80211_BAND_5GHZ];
  354. sband->band = IEEE80211_BAND_5GHZ;
  355. sband->bitrates = &ah->rates[IEEE80211_BAND_5GHZ][0];
  356. memcpy(sband->bitrates, &ath5k_rates[4],
  357. sizeof(struct ieee80211_rate) * 8);
  358. sband->n_bitrates = 8;
  359. sband->channels = &ah->channels[count_c];
  360. sband->n_channels = ath5k_setup_channels(ah, sband->channels,
  361. AR5K_MODE_11A, max_c);
  362. hw->wiphy->bands[IEEE80211_BAND_5GHZ] = sband;
  363. }
  364. ath5k_setup_rate_idx(ah, sband);
  365. ath5k_debug_dump_bands(ah);
  366. return 0;
  367. }
  368. /*
  369. * Set/change channels. We always reset the chip.
  370. * To accomplish this we must first cleanup any pending DMA,
  371. * then restart stuff after a la ath5k_init.
  372. *
  373. * Called with ah->lock.
  374. */
  375. int
  376. ath5k_chan_set(struct ath5k_hw *ah, struct ieee80211_channel *chan)
  377. {
  378. ATH5K_DBG(ah, ATH5K_DEBUG_RESET,
  379. "channel set, resetting (%u -> %u MHz)\n",
  380. ah->curchan->center_freq, chan->center_freq);
  381. /*
  382. * To switch channels clear any pending DMA operations;
  383. * wait long enough for the RX fifo to drain, reset the
  384. * hardware at the new frequency, and then re-enable
  385. * the relevant bits of the h/w.
  386. */
  387. return ath5k_reset(ah, chan, true);
  388. }
  389. void ath5k_vif_iter(void *data, u8 *mac, struct ieee80211_vif *vif)
  390. {
  391. struct ath5k_vif_iter_data *iter_data = data;
  392. int i;
  393. struct ath5k_vif *avf = (void *)vif->drv_priv;
  394. if (iter_data->hw_macaddr)
  395. for (i = 0; i < ETH_ALEN; i++)
  396. iter_data->mask[i] &=
  397. ~(iter_data->hw_macaddr[i] ^ mac[i]);
  398. if (!iter_data->found_active) {
  399. iter_data->found_active = true;
  400. memcpy(iter_data->active_mac, mac, ETH_ALEN);
  401. }
  402. if (iter_data->need_set_hw_addr && iter_data->hw_macaddr)
  403. if (compare_ether_addr(iter_data->hw_macaddr, mac) == 0)
  404. iter_data->need_set_hw_addr = false;
  405. if (!iter_data->any_assoc) {
  406. if (avf->assoc)
  407. iter_data->any_assoc = true;
  408. }
  409. /* Calculate combined mode - when APs are active, operate in AP mode.
  410. * Otherwise use the mode of the new interface. This can currently
  411. * only deal with combinations of APs and STAs. Only one ad-hoc
  412. * interfaces is allowed.
  413. */
  414. if (avf->opmode == NL80211_IFTYPE_AP)
  415. iter_data->opmode = NL80211_IFTYPE_AP;
  416. else {
  417. if (avf->opmode == NL80211_IFTYPE_STATION)
  418. iter_data->n_stas++;
  419. if (iter_data->opmode == NL80211_IFTYPE_UNSPECIFIED)
  420. iter_data->opmode = avf->opmode;
  421. }
  422. }
  423. void
  424. ath5k_update_bssid_mask_and_opmode(struct ath5k_hw *ah,
  425. struct ieee80211_vif *vif)
  426. {
  427. struct ath_common *common = ath5k_hw_common(ah);
  428. struct ath5k_vif_iter_data iter_data;
  429. u32 rfilt;
  430. /*
  431. * Use the hardware MAC address as reference, the hardware uses it
  432. * together with the BSSID mask when matching addresses.
  433. */
  434. iter_data.hw_macaddr = common->macaddr;
  435. memset(&iter_data.mask, 0xff, ETH_ALEN);
  436. iter_data.found_active = false;
  437. iter_data.need_set_hw_addr = true;
  438. iter_data.opmode = NL80211_IFTYPE_UNSPECIFIED;
  439. iter_data.n_stas = 0;
  440. if (vif)
  441. ath5k_vif_iter(&iter_data, vif->addr, vif);
  442. /* Get list of all active MAC addresses */
  443. ieee80211_iterate_active_interfaces_atomic(ah->hw, ath5k_vif_iter,
  444. &iter_data);
  445. memcpy(ah->bssidmask, iter_data.mask, ETH_ALEN);
  446. ah->opmode = iter_data.opmode;
  447. if (ah->opmode == NL80211_IFTYPE_UNSPECIFIED)
  448. /* Nothing active, default to station mode */
  449. ah->opmode = NL80211_IFTYPE_STATION;
  450. ath5k_hw_set_opmode(ah, ah->opmode);
  451. ATH5K_DBG(ah, ATH5K_DEBUG_MODE, "mode setup opmode %d (%s)\n",
  452. ah->opmode, ath_opmode_to_string(ah->opmode));
  453. if (iter_data.need_set_hw_addr && iter_data.found_active)
  454. ath5k_hw_set_lladdr(ah, iter_data.active_mac);
  455. if (ath5k_hw_hasbssidmask(ah))
  456. ath5k_hw_set_bssid_mask(ah, ah->bssidmask);
  457. /* Set up RX Filter */
  458. if (iter_data.n_stas > 1) {
  459. /* If you have multiple STA interfaces connected to
  460. * different APs, ARPs are not received (most of the time?)
  461. * Enabling PROMISC appears to fix that problem.
  462. */
  463. ah->filter_flags |= AR5K_RX_FILTER_PROM;
  464. }
  465. rfilt = ah->filter_flags;
  466. ath5k_hw_set_rx_filter(ah, rfilt);
  467. ATH5K_DBG(ah, ATH5K_DEBUG_MODE, "RX filter 0x%x\n", rfilt);
  468. }
  469. static inline int
  470. ath5k_hw_to_driver_rix(struct ath5k_hw *ah, int hw_rix)
  471. {
  472. int rix;
  473. /* return base rate on errors */
  474. if (WARN(hw_rix < 0 || hw_rix >= AR5K_MAX_RATES,
  475. "hw_rix out of bounds: %x\n", hw_rix))
  476. return 0;
  477. rix = ah->rate_idx[ah->curchan->band][hw_rix];
  478. if (WARN(rix < 0, "invalid hw_rix: %x\n", hw_rix))
  479. rix = 0;
  480. return rix;
  481. }
  482. /***************\
  483. * Buffers setup *
  484. \***************/
  485. static
  486. struct sk_buff *ath5k_rx_skb_alloc(struct ath5k_hw *ah, dma_addr_t *skb_addr)
  487. {
  488. struct ath_common *common = ath5k_hw_common(ah);
  489. struct sk_buff *skb;
  490. /*
  491. * Allocate buffer with headroom_needed space for the
  492. * fake physical layer header at the start.
  493. */
  494. skb = ath_rxbuf_alloc(common,
  495. common->rx_bufsize,
  496. GFP_ATOMIC);
  497. if (!skb) {
  498. ATH5K_ERR(ah, "can't alloc skbuff of size %u\n",
  499. common->rx_bufsize);
  500. return NULL;
  501. }
  502. *skb_addr = dma_map_single(ah->dev,
  503. skb->data, common->rx_bufsize,
  504. DMA_FROM_DEVICE);
  505. if (unlikely(dma_mapping_error(ah->dev, *skb_addr))) {
  506. ATH5K_ERR(ah, "%s: DMA mapping failed\n", __func__);
  507. dev_kfree_skb(skb);
  508. return NULL;
  509. }
  510. return skb;
  511. }
  512. static int
  513. ath5k_rxbuf_setup(struct ath5k_hw *ah, struct ath5k_buf *bf)
  514. {
  515. struct sk_buff *skb = bf->skb;
  516. struct ath5k_desc *ds;
  517. int ret;
  518. if (!skb) {
  519. skb = ath5k_rx_skb_alloc(ah, &bf->skbaddr);
  520. if (!skb)
  521. return -ENOMEM;
  522. bf->skb = skb;
  523. }
  524. /*
  525. * Setup descriptors. For receive we always terminate
  526. * the descriptor list with a self-linked entry so we'll
  527. * not get overrun under high load (as can happen with a
  528. * 5212 when ANI processing enables PHY error frames).
  529. *
  530. * To ensure the last descriptor is self-linked we create
  531. * each descriptor as self-linked and add it to the end. As
  532. * each additional descriptor is added the previous self-linked
  533. * entry is "fixed" naturally. This should be safe even
  534. * if DMA is happening. When processing RX interrupts we
  535. * never remove/process the last, self-linked, entry on the
  536. * descriptor list. This ensures the hardware always has
  537. * someplace to write a new frame.
  538. */
  539. ds = bf->desc;
  540. ds->ds_link = bf->daddr; /* link to self */
  541. ds->ds_data = bf->skbaddr;
  542. ret = ath5k_hw_setup_rx_desc(ah, ds, ah->common.rx_bufsize, 0);
  543. if (ret) {
  544. ATH5K_ERR(ah, "%s: could not setup RX desc\n", __func__);
  545. return ret;
  546. }
  547. if (ah->rxlink != NULL)
  548. *ah->rxlink = bf->daddr;
  549. ah->rxlink = &ds->ds_link;
  550. return 0;
  551. }
  552. static enum ath5k_pkt_type get_hw_packet_type(struct sk_buff *skb)
  553. {
  554. struct ieee80211_hdr *hdr;
  555. enum ath5k_pkt_type htype;
  556. __le16 fc;
  557. hdr = (struct ieee80211_hdr *)skb->data;
  558. fc = hdr->frame_control;
  559. if (ieee80211_is_beacon(fc))
  560. htype = AR5K_PKT_TYPE_BEACON;
  561. else if (ieee80211_is_probe_resp(fc))
  562. htype = AR5K_PKT_TYPE_PROBE_RESP;
  563. else if (ieee80211_is_atim(fc))
  564. htype = AR5K_PKT_TYPE_ATIM;
  565. else if (ieee80211_is_pspoll(fc))
  566. htype = AR5K_PKT_TYPE_PSPOLL;
  567. else
  568. htype = AR5K_PKT_TYPE_NORMAL;
  569. return htype;
  570. }
  571. static int
  572. ath5k_txbuf_setup(struct ath5k_hw *ah, struct ath5k_buf *bf,
  573. struct ath5k_txq *txq, int padsize)
  574. {
  575. struct ath5k_desc *ds = bf->desc;
  576. struct sk_buff *skb = bf->skb;
  577. struct ieee80211_tx_info *info = IEEE80211_SKB_CB(skb);
  578. unsigned int pktlen, flags, keyidx = AR5K_TXKEYIX_INVALID;
  579. struct ieee80211_rate *rate;
  580. unsigned int mrr_rate[3], mrr_tries[3];
  581. int i, ret;
  582. u16 hw_rate;
  583. u16 cts_rate = 0;
  584. u16 duration = 0;
  585. u8 rc_flags;
  586. flags = AR5K_TXDESC_INTREQ | AR5K_TXDESC_CLRDMASK;
  587. /* XXX endianness */
  588. bf->skbaddr = dma_map_single(ah->dev, skb->data, skb->len,
  589. DMA_TO_DEVICE);
  590. rate = ieee80211_get_tx_rate(ah->hw, info);
  591. if (!rate) {
  592. ret = -EINVAL;
  593. goto err_unmap;
  594. }
  595. if (info->flags & IEEE80211_TX_CTL_NO_ACK)
  596. flags |= AR5K_TXDESC_NOACK;
  597. rc_flags = info->control.rates[0].flags;
  598. hw_rate = (rc_flags & IEEE80211_TX_RC_USE_SHORT_PREAMBLE) ?
  599. rate->hw_value_short : rate->hw_value;
  600. pktlen = skb->len;
  601. /* FIXME: If we are in g mode and rate is a CCK rate
  602. * subtract ah->ah_txpower.txp_cck_ofdm_pwr_delta
  603. * from tx power (value is in dB units already) */
  604. if (info->control.hw_key) {
  605. keyidx = info->control.hw_key->hw_key_idx;
  606. pktlen += info->control.hw_key->icv_len;
  607. }
  608. if (rc_flags & IEEE80211_TX_RC_USE_RTS_CTS) {
  609. flags |= AR5K_TXDESC_RTSENA;
  610. cts_rate = ieee80211_get_rts_cts_rate(ah->hw, info)->hw_value;
  611. duration = le16_to_cpu(ieee80211_rts_duration(ah->hw,
  612. info->control.vif, pktlen, info));
  613. }
  614. if (rc_flags & IEEE80211_TX_RC_USE_CTS_PROTECT) {
  615. flags |= AR5K_TXDESC_CTSENA;
  616. cts_rate = ieee80211_get_rts_cts_rate(ah->hw, info)->hw_value;
  617. duration = le16_to_cpu(ieee80211_ctstoself_duration(ah->hw,
  618. info->control.vif, pktlen, info));
  619. }
  620. ret = ah->ah_setup_tx_desc(ah, ds, pktlen,
  621. ieee80211_get_hdrlen_from_skb(skb), padsize,
  622. get_hw_packet_type(skb),
  623. (ah->power_level * 2),
  624. hw_rate,
  625. info->control.rates[0].count, keyidx, ah->ah_tx_ant, flags,
  626. cts_rate, duration);
  627. if (ret)
  628. goto err_unmap;
  629. memset(mrr_rate, 0, sizeof(mrr_rate));
  630. memset(mrr_tries, 0, sizeof(mrr_tries));
  631. for (i = 0; i < 3; i++) {
  632. rate = ieee80211_get_alt_retry_rate(ah->hw, info, i);
  633. if (!rate)
  634. break;
  635. mrr_rate[i] = rate->hw_value;
  636. mrr_tries[i] = info->control.rates[i + 1].count;
  637. }
  638. ath5k_hw_setup_mrr_tx_desc(ah, ds,
  639. mrr_rate[0], mrr_tries[0],
  640. mrr_rate[1], mrr_tries[1],
  641. mrr_rate[2], mrr_tries[2]);
  642. ds->ds_link = 0;
  643. ds->ds_data = bf->skbaddr;
  644. spin_lock_bh(&txq->lock);
  645. list_add_tail(&bf->list, &txq->q);
  646. txq->txq_len++;
  647. if (txq->link == NULL) /* is this first packet? */
  648. ath5k_hw_set_txdp(ah, txq->qnum, bf->daddr);
  649. else /* no, so only link it */
  650. *txq->link = bf->daddr;
  651. txq->link = &ds->ds_link;
  652. ath5k_hw_start_tx_dma(ah, txq->qnum);
  653. mmiowb();
  654. spin_unlock_bh(&txq->lock);
  655. return 0;
  656. err_unmap:
  657. dma_unmap_single(ah->dev, bf->skbaddr, skb->len, DMA_TO_DEVICE);
  658. return ret;
  659. }
  660. /*******************\
  661. * Descriptors setup *
  662. \*******************/
  663. static int
  664. ath5k_desc_alloc(struct ath5k_hw *ah)
  665. {
  666. struct ath5k_desc *ds;
  667. struct ath5k_buf *bf;
  668. dma_addr_t da;
  669. unsigned int i;
  670. int ret;
  671. /* allocate descriptors */
  672. ah->desc_len = sizeof(struct ath5k_desc) *
  673. (ATH_TXBUF + ATH_RXBUF + ATH_BCBUF + 1);
  674. ah->desc = dma_alloc_coherent(ah->dev, ah->desc_len,
  675. &ah->desc_daddr, GFP_KERNEL);
  676. if (ah->desc == NULL) {
  677. ATH5K_ERR(ah, "can't allocate descriptors\n");
  678. ret = -ENOMEM;
  679. goto err;
  680. }
  681. ds = ah->desc;
  682. da = ah->desc_daddr;
  683. ATH5K_DBG(ah, ATH5K_DEBUG_ANY, "DMA map: %p (%zu) -> %llx\n",
  684. ds, ah->desc_len, (unsigned long long)ah->desc_daddr);
  685. bf = kcalloc(1 + ATH_TXBUF + ATH_RXBUF + ATH_BCBUF,
  686. sizeof(struct ath5k_buf), GFP_KERNEL);
  687. if (bf == NULL) {
  688. ATH5K_ERR(ah, "can't allocate bufptr\n");
  689. ret = -ENOMEM;
  690. goto err_free;
  691. }
  692. ah->bufptr = bf;
  693. INIT_LIST_HEAD(&ah->rxbuf);
  694. for (i = 0; i < ATH_RXBUF; i++, bf++, ds++, da += sizeof(*ds)) {
  695. bf->desc = ds;
  696. bf->daddr = da;
  697. list_add_tail(&bf->list, &ah->rxbuf);
  698. }
  699. INIT_LIST_HEAD(&ah->txbuf);
  700. ah->txbuf_len = ATH_TXBUF;
  701. for (i = 0; i < ATH_TXBUF; i++, bf++, ds++, da += sizeof(*ds)) {
  702. bf->desc = ds;
  703. bf->daddr = da;
  704. list_add_tail(&bf->list, &ah->txbuf);
  705. }
  706. /* beacon buffers */
  707. INIT_LIST_HEAD(&ah->bcbuf);
  708. for (i = 0; i < ATH_BCBUF; i++, bf++, ds++, da += sizeof(*ds)) {
  709. bf->desc = ds;
  710. bf->daddr = da;
  711. list_add_tail(&bf->list, &ah->bcbuf);
  712. }
  713. return 0;
  714. err_free:
  715. dma_free_coherent(ah->dev, ah->desc_len, ah->desc, ah->desc_daddr);
  716. err:
  717. ah->desc = NULL;
  718. return ret;
  719. }
  720. void
  721. ath5k_txbuf_free_skb(struct ath5k_hw *ah, struct ath5k_buf *bf)
  722. {
  723. BUG_ON(!bf);
  724. if (!bf->skb)
  725. return;
  726. dma_unmap_single(ah->dev, bf->skbaddr, bf->skb->len,
  727. DMA_TO_DEVICE);
  728. dev_kfree_skb_any(bf->skb);
  729. bf->skb = NULL;
  730. bf->skbaddr = 0;
  731. bf->desc->ds_data = 0;
  732. }
  733. void
  734. ath5k_rxbuf_free_skb(struct ath5k_hw *ah, struct ath5k_buf *bf)
  735. {
  736. struct ath_common *common = ath5k_hw_common(ah);
  737. BUG_ON(!bf);
  738. if (!bf->skb)
  739. return;
  740. dma_unmap_single(ah->dev, bf->skbaddr, common->rx_bufsize,
  741. DMA_FROM_DEVICE);
  742. dev_kfree_skb_any(bf->skb);
  743. bf->skb = NULL;
  744. bf->skbaddr = 0;
  745. bf->desc->ds_data = 0;
  746. }
  747. static void
  748. ath5k_desc_free(struct ath5k_hw *ah)
  749. {
  750. struct ath5k_buf *bf;
  751. list_for_each_entry(bf, &ah->txbuf, list)
  752. ath5k_txbuf_free_skb(ah, bf);
  753. list_for_each_entry(bf, &ah->rxbuf, list)
  754. ath5k_rxbuf_free_skb(ah, bf);
  755. list_for_each_entry(bf, &ah->bcbuf, list)
  756. ath5k_txbuf_free_skb(ah, bf);
  757. /* Free memory associated with all descriptors */
  758. dma_free_coherent(ah->dev, ah->desc_len, ah->desc, ah->desc_daddr);
  759. ah->desc = NULL;
  760. ah->desc_daddr = 0;
  761. kfree(ah->bufptr);
  762. ah->bufptr = NULL;
  763. }
  764. /**************\
  765. * Queues setup *
  766. \**************/
  767. static struct ath5k_txq *
  768. ath5k_txq_setup(struct ath5k_hw *ah,
  769. int qtype, int subtype)
  770. {
  771. struct ath5k_txq *txq;
  772. struct ath5k_txq_info qi = {
  773. .tqi_subtype = subtype,
  774. /* XXX: default values not correct for B and XR channels,
  775. * but who cares? */
  776. .tqi_aifs = AR5K_TUNE_AIFS,
  777. .tqi_cw_min = AR5K_TUNE_CWMIN,
  778. .tqi_cw_max = AR5K_TUNE_CWMAX
  779. };
  780. int qnum;
  781. /*
  782. * Enable interrupts only for EOL and DESC conditions.
  783. * We mark tx descriptors to receive a DESC interrupt
  784. * when a tx queue gets deep; otherwise we wait for the
  785. * EOL to reap descriptors. Note that this is done to
  786. * reduce interrupt load and this only defers reaping
  787. * descriptors, never transmitting frames. Aside from
  788. * reducing interrupts this also permits more concurrency.
  789. * The only potential downside is if the tx queue backs
  790. * up in which case the top half of the kernel may backup
  791. * due to a lack of tx descriptors.
  792. */
  793. qi.tqi_flags = AR5K_TXQ_FLAG_TXEOLINT_ENABLE |
  794. AR5K_TXQ_FLAG_TXDESCINT_ENABLE;
  795. qnum = ath5k_hw_setup_tx_queue(ah, qtype, &qi);
  796. if (qnum < 0) {
  797. /*
  798. * NB: don't print a message, this happens
  799. * normally on parts with too few tx queues
  800. */
  801. return ERR_PTR(qnum);
  802. }
  803. if (qnum >= ARRAY_SIZE(ah->txqs)) {
  804. ATH5K_ERR(ah, "hw qnum %u out of range, max %tu!\n",
  805. qnum, ARRAY_SIZE(ah->txqs));
  806. ath5k_hw_release_tx_queue(ah, qnum);
  807. return ERR_PTR(-EINVAL);
  808. }
  809. txq = &ah->txqs[qnum];
  810. if (!txq->setup) {
  811. txq->qnum = qnum;
  812. txq->link = NULL;
  813. INIT_LIST_HEAD(&txq->q);
  814. spin_lock_init(&txq->lock);
  815. txq->setup = true;
  816. txq->txq_len = 0;
  817. txq->txq_max = ATH5K_TXQ_LEN_MAX;
  818. txq->txq_poll_mark = false;
  819. txq->txq_stuck = 0;
  820. }
  821. return &ah->txqs[qnum];
  822. }
  823. static int
  824. ath5k_beaconq_setup(struct ath5k_hw *ah)
  825. {
  826. struct ath5k_txq_info qi = {
  827. /* XXX: default values not correct for B and XR channels,
  828. * but who cares? */
  829. .tqi_aifs = AR5K_TUNE_AIFS,
  830. .tqi_cw_min = AR5K_TUNE_CWMIN,
  831. .tqi_cw_max = AR5K_TUNE_CWMAX,
  832. /* NB: for dynamic turbo, don't enable any other interrupts */
  833. .tqi_flags = AR5K_TXQ_FLAG_TXDESCINT_ENABLE
  834. };
  835. return ath5k_hw_setup_tx_queue(ah, AR5K_TX_QUEUE_BEACON, &qi);
  836. }
  837. static int
  838. ath5k_beaconq_config(struct ath5k_hw *ah)
  839. {
  840. struct ath5k_txq_info qi;
  841. int ret;
  842. ret = ath5k_hw_get_tx_queueprops(ah, ah->bhalq, &qi);
  843. if (ret)
  844. goto err;
  845. if (ah->opmode == NL80211_IFTYPE_AP ||
  846. ah->opmode == NL80211_IFTYPE_MESH_POINT) {
  847. /*
  848. * Always burst out beacon and CAB traffic
  849. * (aifs = cwmin = cwmax = 0)
  850. */
  851. qi.tqi_aifs = 0;
  852. qi.tqi_cw_min = 0;
  853. qi.tqi_cw_max = 0;
  854. } else if (ah->opmode == NL80211_IFTYPE_ADHOC) {
  855. /*
  856. * Adhoc mode; backoff between 0 and (2 * cw_min).
  857. */
  858. qi.tqi_aifs = 0;
  859. qi.tqi_cw_min = 0;
  860. qi.tqi_cw_max = 2 * AR5K_TUNE_CWMIN;
  861. }
  862. ATH5K_DBG(ah, ATH5K_DEBUG_BEACON,
  863. "beacon queueprops tqi_aifs:%d tqi_cw_min:%d tqi_cw_max:%d\n",
  864. qi.tqi_aifs, qi.tqi_cw_min, qi.tqi_cw_max);
  865. ret = ath5k_hw_set_tx_queueprops(ah, ah->bhalq, &qi);
  866. if (ret) {
  867. ATH5K_ERR(ah, "%s: unable to update parameters for beacon "
  868. "hardware queue!\n", __func__);
  869. goto err;
  870. }
  871. ret = ath5k_hw_reset_tx_queue(ah, ah->bhalq); /* push to h/w */
  872. if (ret)
  873. goto err;
  874. /* reconfigure cabq with ready time to 80% of beacon_interval */
  875. ret = ath5k_hw_get_tx_queueprops(ah, AR5K_TX_QUEUE_ID_CAB, &qi);
  876. if (ret)
  877. goto err;
  878. qi.tqi_ready_time = (ah->bintval * 80) / 100;
  879. ret = ath5k_hw_set_tx_queueprops(ah, AR5K_TX_QUEUE_ID_CAB, &qi);
  880. if (ret)
  881. goto err;
  882. ret = ath5k_hw_reset_tx_queue(ah, AR5K_TX_QUEUE_ID_CAB);
  883. err:
  884. return ret;
  885. }
  886. /**
  887. * ath5k_drain_tx_buffs - Empty tx buffers
  888. *
  889. * @ah The &struct ath5k_hw
  890. *
  891. * Empty tx buffers from all queues in preparation
  892. * of a reset or during shutdown.
  893. *
  894. * NB: this assumes output has been stopped and
  895. * we do not need to block ath5k_tx_tasklet
  896. */
  897. static void
  898. ath5k_drain_tx_buffs(struct ath5k_hw *ah)
  899. {
  900. struct ath5k_txq *txq;
  901. struct ath5k_buf *bf, *bf0;
  902. int i;
  903. for (i = 0; i < ARRAY_SIZE(ah->txqs); i++) {
  904. if (ah->txqs[i].setup) {
  905. txq = &ah->txqs[i];
  906. spin_lock_bh(&txq->lock);
  907. list_for_each_entry_safe(bf, bf0, &txq->q, list) {
  908. ath5k_debug_printtxbuf(ah, bf);
  909. ath5k_txbuf_free_skb(ah, bf);
  910. spin_lock_bh(&ah->txbuflock);
  911. list_move_tail(&bf->list, &ah->txbuf);
  912. ah->txbuf_len++;
  913. txq->txq_len--;
  914. spin_unlock_bh(&ah->txbuflock);
  915. }
  916. txq->link = NULL;
  917. txq->txq_poll_mark = false;
  918. spin_unlock_bh(&txq->lock);
  919. }
  920. }
  921. }
  922. static void
  923. ath5k_txq_release(struct ath5k_hw *ah)
  924. {
  925. struct ath5k_txq *txq = ah->txqs;
  926. unsigned int i;
  927. for (i = 0; i < ARRAY_SIZE(ah->txqs); i++, txq++)
  928. if (txq->setup) {
  929. ath5k_hw_release_tx_queue(ah, txq->qnum);
  930. txq->setup = false;
  931. }
  932. }
  933. /*************\
  934. * RX Handling *
  935. \*************/
  936. /*
  937. * Enable the receive h/w following a reset.
  938. */
  939. static int
  940. ath5k_rx_start(struct ath5k_hw *ah)
  941. {
  942. struct ath_common *common = ath5k_hw_common(ah);
  943. struct ath5k_buf *bf;
  944. int ret;
  945. common->rx_bufsize = roundup(IEEE80211_MAX_FRAME_LEN, common->cachelsz);
  946. ATH5K_DBG(ah, ATH5K_DEBUG_RESET, "cachelsz %u rx_bufsize %u\n",
  947. common->cachelsz, common->rx_bufsize);
  948. spin_lock_bh(&ah->rxbuflock);
  949. ah->rxlink = NULL;
  950. list_for_each_entry(bf, &ah->rxbuf, list) {
  951. ret = ath5k_rxbuf_setup(ah, bf);
  952. if (ret != 0) {
  953. spin_unlock_bh(&ah->rxbuflock);
  954. goto err;
  955. }
  956. }
  957. bf = list_first_entry(&ah->rxbuf, struct ath5k_buf, list);
  958. ath5k_hw_set_rxdp(ah, bf->daddr);
  959. spin_unlock_bh(&ah->rxbuflock);
  960. ath5k_hw_start_rx_dma(ah); /* enable recv descriptors */
  961. ath5k_update_bssid_mask_and_opmode(ah, NULL); /* set filters, etc. */
  962. ath5k_hw_start_rx_pcu(ah); /* re-enable PCU/DMA engine */
  963. return 0;
  964. err:
  965. return ret;
  966. }
  967. /*
  968. * Disable the receive logic on PCU (DRU)
  969. * In preparation for a shutdown.
  970. *
  971. * Note: Doesn't stop rx DMA, ath5k_hw_dma_stop
  972. * does.
  973. */
  974. static void
  975. ath5k_rx_stop(struct ath5k_hw *ah)
  976. {
  977. ath5k_hw_set_rx_filter(ah, 0); /* clear recv filter */
  978. ath5k_hw_stop_rx_pcu(ah); /* disable PCU */
  979. ath5k_debug_printrxbuffs(ah);
  980. }
  981. static unsigned int
  982. ath5k_rx_decrypted(struct ath5k_hw *ah, struct sk_buff *skb,
  983. struct ath5k_rx_status *rs)
  984. {
  985. struct ath_common *common = ath5k_hw_common(ah);
  986. struct ieee80211_hdr *hdr = (void *)skb->data;
  987. unsigned int keyix, hlen;
  988. if (!(rs->rs_status & AR5K_RXERR_DECRYPT) &&
  989. rs->rs_keyix != AR5K_RXKEYIX_INVALID)
  990. return RX_FLAG_DECRYPTED;
  991. /* Apparently when a default key is used to decrypt the packet
  992. the hw does not set the index used to decrypt. In such cases
  993. get the index from the packet. */
  994. hlen = ieee80211_hdrlen(hdr->frame_control);
  995. if (ieee80211_has_protected(hdr->frame_control) &&
  996. !(rs->rs_status & AR5K_RXERR_DECRYPT) &&
  997. skb->len >= hlen + 4) {
  998. keyix = skb->data[hlen + 3] >> 6;
  999. if (test_bit(keyix, common->keymap))
  1000. return RX_FLAG_DECRYPTED;
  1001. }
  1002. return 0;
  1003. }
  1004. static void
  1005. ath5k_check_ibss_tsf(struct ath5k_hw *ah, struct sk_buff *skb,
  1006. struct ieee80211_rx_status *rxs)
  1007. {
  1008. struct ath_common *common = ath5k_hw_common(ah);
  1009. u64 tsf, bc_tstamp;
  1010. u32 hw_tu;
  1011. struct ieee80211_mgmt *mgmt = (struct ieee80211_mgmt *)skb->data;
  1012. if (ieee80211_is_beacon(mgmt->frame_control) &&
  1013. le16_to_cpu(mgmt->u.beacon.capab_info) & WLAN_CAPABILITY_IBSS &&
  1014. memcmp(mgmt->bssid, common->curbssid, ETH_ALEN) == 0) {
  1015. /*
  1016. * Received an IBSS beacon with the same BSSID. Hardware *must*
  1017. * have updated the local TSF. We have to work around various
  1018. * hardware bugs, though...
  1019. */
  1020. tsf = ath5k_hw_get_tsf64(ah);
  1021. bc_tstamp = le64_to_cpu(mgmt->u.beacon.timestamp);
  1022. hw_tu = TSF_TO_TU(tsf);
  1023. ATH5K_DBG_UNLIMIT(ah, ATH5K_DEBUG_BEACON,
  1024. "beacon %llx mactime %llx (diff %lld) tsf now %llx\n",
  1025. (unsigned long long)bc_tstamp,
  1026. (unsigned long long)rxs->mactime,
  1027. (unsigned long long)(rxs->mactime - bc_tstamp),
  1028. (unsigned long long)tsf);
  1029. /*
  1030. * Sometimes the HW will give us a wrong tstamp in the rx
  1031. * status, causing the timestamp extension to go wrong.
  1032. * (This seems to happen especially with beacon frames bigger
  1033. * than 78 byte (incl. FCS))
  1034. * But we know that the receive timestamp must be later than the
  1035. * timestamp of the beacon since HW must have synced to that.
  1036. *
  1037. * NOTE: here we assume mactime to be after the frame was
  1038. * received, not like mac80211 which defines it at the start.
  1039. */
  1040. if (bc_tstamp > rxs->mactime) {
  1041. ATH5K_DBG_UNLIMIT(ah, ATH5K_DEBUG_BEACON,
  1042. "fixing mactime from %llx to %llx\n",
  1043. (unsigned long long)rxs->mactime,
  1044. (unsigned long long)tsf);
  1045. rxs->mactime = tsf;
  1046. }
  1047. /*
  1048. * Local TSF might have moved higher than our beacon timers,
  1049. * in that case we have to update them to continue sending
  1050. * beacons. This also takes care of synchronizing beacon sending
  1051. * times with other stations.
  1052. */
  1053. if (hw_tu >= ah->nexttbtt)
  1054. ath5k_beacon_update_timers(ah, bc_tstamp);
  1055. /* Check if the beacon timers are still correct, because a TSF
  1056. * update might have created a window between them - for a
  1057. * longer description see the comment of this function: */
  1058. if (!ath5k_hw_check_beacon_timers(ah, ah->bintval)) {
  1059. ath5k_beacon_update_timers(ah, bc_tstamp);
  1060. ATH5K_DBG_UNLIMIT(ah, ATH5K_DEBUG_BEACON,
  1061. "fixed beacon timers after beacon receive\n");
  1062. }
  1063. }
  1064. }
  1065. static void
  1066. ath5k_update_beacon_rssi(struct ath5k_hw *ah, struct sk_buff *skb, int rssi)
  1067. {
  1068. struct ieee80211_mgmt *mgmt = (struct ieee80211_mgmt *)skb->data;
  1069. struct ath_common *common = ath5k_hw_common(ah);
  1070. /* only beacons from our BSSID */
  1071. if (!ieee80211_is_beacon(mgmt->frame_control) ||
  1072. memcmp(mgmt->bssid, common->curbssid, ETH_ALEN) != 0)
  1073. return;
  1074. ewma_add(&ah->ah_beacon_rssi_avg, rssi);
  1075. /* in IBSS mode we should keep RSSI statistics per neighbour */
  1076. /* le16_to_cpu(mgmt->u.beacon.capab_info) & WLAN_CAPABILITY_IBSS */
  1077. }
  1078. /*
  1079. * Compute padding position. skb must contain an IEEE 802.11 frame
  1080. */
  1081. static int ath5k_common_padpos(struct sk_buff *skb)
  1082. {
  1083. struct ieee80211_hdr *hdr = (struct ieee80211_hdr *)skb->data;
  1084. __le16 frame_control = hdr->frame_control;
  1085. int padpos = 24;
  1086. if (ieee80211_has_a4(frame_control))
  1087. padpos += ETH_ALEN;
  1088. if (ieee80211_is_data_qos(frame_control))
  1089. padpos += IEEE80211_QOS_CTL_LEN;
  1090. return padpos;
  1091. }
  1092. /*
  1093. * This function expects an 802.11 frame and returns the number of
  1094. * bytes added, or -1 if we don't have enough header room.
  1095. */
  1096. static int ath5k_add_padding(struct sk_buff *skb)
  1097. {
  1098. int padpos = ath5k_common_padpos(skb);
  1099. int padsize = padpos & 3;
  1100. if (padsize && skb->len > padpos) {
  1101. if (skb_headroom(skb) < padsize)
  1102. return -1;
  1103. skb_push(skb, padsize);
  1104. memmove(skb->data, skb->data + padsize, padpos);
  1105. return padsize;
  1106. }
  1107. return 0;
  1108. }
  1109. /*
  1110. * The MAC header is padded to have 32-bit boundary if the
  1111. * packet payload is non-zero. The general calculation for
  1112. * padsize would take into account odd header lengths:
  1113. * padsize = 4 - (hdrlen & 3); however, since only
  1114. * even-length headers are used, padding can only be 0 or 2
  1115. * bytes and we can optimize this a bit. We must not try to
  1116. * remove padding from short control frames that do not have a
  1117. * payload.
  1118. *
  1119. * This function expects an 802.11 frame and returns the number of
  1120. * bytes removed.
  1121. */
  1122. static int ath5k_remove_padding(struct sk_buff *skb)
  1123. {
  1124. int padpos = ath5k_common_padpos(skb);
  1125. int padsize = padpos & 3;
  1126. if (padsize && skb->len >= padpos + padsize) {
  1127. memmove(skb->data + padsize, skb->data, padpos);
  1128. skb_pull(skb, padsize);
  1129. return padsize;
  1130. }
  1131. return 0;
  1132. }
  1133. static void
  1134. ath5k_receive_frame(struct ath5k_hw *ah, struct sk_buff *skb,
  1135. struct ath5k_rx_status *rs)
  1136. {
  1137. struct ieee80211_rx_status *rxs;
  1138. ath5k_remove_padding(skb);
  1139. rxs = IEEE80211_SKB_RXCB(skb);
  1140. rxs->flag = 0;
  1141. if (unlikely(rs->rs_status & AR5K_RXERR_MIC))
  1142. rxs->flag |= RX_FLAG_MMIC_ERROR;
  1143. /*
  1144. * always extend the mac timestamp, since this information is
  1145. * also needed for proper IBSS merging.
  1146. *
  1147. * XXX: it might be too late to do it here, since rs_tstamp is
  1148. * 15bit only. that means TSF extension has to be done within
  1149. * 32768usec (about 32ms). it might be necessary to move this to
  1150. * the interrupt handler, like it is done in madwifi.
  1151. *
  1152. * Unfortunately we don't know when the hardware takes the rx
  1153. * timestamp (beginning of phy frame, data frame, end of rx?).
  1154. * The only thing we know is that it is hardware specific...
  1155. * On AR5213 it seems the rx timestamp is at the end of the
  1156. * frame, but I'm not sure.
  1157. *
  1158. * NOTE: mac80211 defines mactime at the beginning of the first
  1159. * data symbol. Since we don't have any time references it's
  1160. * impossible to comply to that. This affects IBSS merge only
  1161. * right now, so it's not too bad...
  1162. */
  1163. rxs->mactime = ath5k_extend_tsf(ah, rs->rs_tstamp);
  1164. rxs->flag |= RX_FLAG_MACTIME_MPDU;
  1165. rxs->freq = ah->curchan->center_freq;
  1166. rxs->band = ah->curchan->band;
  1167. rxs->signal = ah->ah_noise_floor + rs->rs_rssi;
  1168. rxs->antenna = rs->rs_antenna;
  1169. if (rs->rs_antenna > 0 && rs->rs_antenna < 5)
  1170. ah->stats.antenna_rx[rs->rs_antenna]++;
  1171. else
  1172. ah->stats.antenna_rx[0]++; /* invalid */
  1173. rxs->rate_idx = ath5k_hw_to_driver_rix(ah, rs->rs_rate);
  1174. rxs->flag |= ath5k_rx_decrypted(ah, skb, rs);
  1175. if (rxs->rate_idx >= 0 && rs->rs_rate ==
  1176. ah->sbands[ah->curchan->band].bitrates[rxs->rate_idx].hw_value_short)
  1177. rxs->flag |= RX_FLAG_SHORTPRE;
  1178. trace_ath5k_rx(ah, skb);
  1179. ath5k_update_beacon_rssi(ah, skb, rs->rs_rssi);
  1180. /* check beacons in IBSS mode */
  1181. if (ah->opmode == NL80211_IFTYPE_ADHOC)
  1182. ath5k_check_ibss_tsf(ah, skb, rxs);
  1183. ieee80211_rx(ah->hw, skb);
  1184. }
  1185. /** ath5k_frame_receive_ok() - Do we want to receive this frame or not?
  1186. *
  1187. * Check if we want to further process this frame or not. Also update
  1188. * statistics. Return true if we want this frame, false if not.
  1189. */
  1190. static bool
  1191. ath5k_receive_frame_ok(struct ath5k_hw *ah, struct ath5k_rx_status *rs)
  1192. {
  1193. ah->stats.rx_all_count++;
  1194. ah->stats.rx_bytes_count += rs->rs_datalen;
  1195. if (unlikely(rs->rs_status)) {
  1196. if (rs->rs_status & AR5K_RXERR_CRC)
  1197. ah->stats.rxerr_crc++;
  1198. if (rs->rs_status & AR5K_RXERR_FIFO)
  1199. ah->stats.rxerr_fifo++;
  1200. if (rs->rs_status & AR5K_RXERR_PHY) {
  1201. ah->stats.rxerr_phy++;
  1202. if (rs->rs_phyerr > 0 && rs->rs_phyerr < 32)
  1203. ah->stats.rxerr_phy_code[rs->rs_phyerr]++;
  1204. return false;
  1205. }
  1206. if (rs->rs_status & AR5K_RXERR_DECRYPT) {
  1207. /*
  1208. * Decrypt error. If the error occurred
  1209. * because there was no hardware key, then
  1210. * let the frame through so the upper layers
  1211. * can process it. This is necessary for 5210
  1212. * parts which have no way to setup a ``clear''
  1213. * key cache entry.
  1214. *
  1215. * XXX do key cache faulting
  1216. */
  1217. ah->stats.rxerr_decrypt++;
  1218. if (rs->rs_keyix == AR5K_RXKEYIX_INVALID &&
  1219. !(rs->rs_status & AR5K_RXERR_CRC))
  1220. return true;
  1221. }
  1222. if (rs->rs_status & AR5K_RXERR_MIC) {
  1223. ah->stats.rxerr_mic++;
  1224. return true;
  1225. }
  1226. /* reject any frames with non-crypto errors */
  1227. if (rs->rs_status & ~(AR5K_RXERR_DECRYPT))
  1228. return false;
  1229. }
  1230. if (unlikely(rs->rs_more)) {
  1231. ah->stats.rxerr_jumbo++;
  1232. return false;
  1233. }
  1234. return true;
  1235. }
  1236. static void
  1237. ath5k_set_current_imask(struct ath5k_hw *ah)
  1238. {
  1239. enum ath5k_int imask;
  1240. unsigned long flags;
  1241. spin_lock_irqsave(&ah->irqlock, flags);
  1242. imask = ah->imask;
  1243. if (ah->rx_pending)
  1244. imask &= ~AR5K_INT_RX_ALL;
  1245. if (ah->tx_pending)
  1246. imask &= ~AR5K_INT_TX_ALL;
  1247. ath5k_hw_set_imr(ah, imask);
  1248. spin_unlock_irqrestore(&ah->irqlock, flags);
  1249. }
  1250. static void
  1251. ath5k_tasklet_rx(unsigned long data)
  1252. {
  1253. struct ath5k_rx_status rs = {};
  1254. struct sk_buff *skb, *next_skb;
  1255. dma_addr_t next_skb_addr;
  1256. struct ath5k_hw *ah = (void *)data;
  1257. struct ath_common *common = ath5k_hw_common(ah);
  1258. struct ath5k_buf *bf;
  1259. struct ath5k_desc *ds;
  1260. int ret;
  1261. spin_lock(&ah->rxbuflock);
  1262. if (list_empty(&ah->rxbuf)) {
  1263. ATH5K_WARN(ah, "empty rx buf pool\n");
  1264. goto unlock;
  1265. }
  1266. do {
  1267. bf = list_first_entry(&ah->rxbuf, struct ath5k_buf, list);
  1268. BUG_ON(bf->skb == NULL);
  1269. skb = bf->skb;
  1270. ds = bf->desc;
  1271. /* bail if HW is still using self-linked descriptor */
  1272. if (ath5k_hw_get_rxdp(ah) == bf->daddr)
  1273. break;
  1274. ret = ah->ah_proc_rx_desc(ah, ds, &rs);
  1275. if (unlikely(ret == -EINPROGRESS))
  1276. break;
  1277. else if (unlikely(ret)) {
  1278. ATH5K_ERR(ah, "error in processing rx descriptor\n");
  1279. ah->stats.rxerr_proc++;
  1280. break;
  1281. }
  1282. if (ath5k_receive_frame_ok(ah, &rs)) {
  1283. next_skb = ath5k_rx_skb_alloc(ah, &next_skb_addr);
  1284. /*
  1285. * If we can't replace bf->skb with a new skb under
  1286. * memory pressure, just skip this packet
  1287. */
  1288. if (!next_skb)
  1289. goto next;
  1290. dma_unmap_single(ah->dev, bf->skbaddr,
  1291. common->rx_bufsize,
  1292. DMA_FROM_DEVICE);
  1293. skb_put(skb, rs.rs_datalen);
  1294. ath5k_receive_frame(ah, skb, &rs);
  1295. bf->skb = next_skb;
  1296. bf->skbaddr = next_skb_addr;
  1297. }
  1298. next:
  1299. list_move_tail(&bf->list, &ah->rxbuf);
  1300. } while (ath5k_rxbuf_setup(ah, bf) == 0);
  1301. unlock:
  1302. spin_unlock(&ah->rxbuflock);
  1303. ah->rx_pending = false;
  1304. ath5k_set_current_imask(ah);
  1305. }
  1306. /*************\
  1307. * TX Handling *
  1308. \*************/
  1309. void
  1310. ath5k_tx_queue(struct ieee80211_hw *hw, struct sk_buff *skb,
  1311. struct ath5k_txq *txq)
  1312. {
  1313. struct ath5k_hw *ah = hw->priv;
  1314. struct ath5k_buf *bf;
  1315. unsigned long flags;
  1316. int padsize;
  1317. trace_ath5k_tx(ah, skb, txq);
  1318. /*
  1319. * The hardware expects the header padded to 4 byte boundaries.
  1320. * If this is not the case, we add the padding after the header.
  1321. */
  1322. padsize = ath5k_add_padding(skb);
  1323. if (padsize < 0) {
  1324. ATH5K_ERR(ah, "tx hdrlen not %%4: not enough"
  1325. " headroom to pad");
  1326. goto drop_packet;
  1327. }
  1328. if (txq->txq_len >= txq->txq_max &&
  1329. txq->qnum <= AR5K_TX_QUEUE_ID_DATA_MAX)
  1330. ieee80211_stop_queue(hw, txq->qnum);
  1331. spin_lock_irqsave(&ah->txbuflock, flags);
  1332. if (list_empty(&ah->txbuf)) {
  1333. ATH5K_ERR(ah, "no further txbuf available, dropping packet\n");
  1334. spin_unlock_irqrestore(&ah->txbuflock, flags);
  1335. ieee80211_stop_queues(hw);
  1336. goto drop_packet;
  1337. }
  1338. bf = list_first_entry(&ah->txbuf, struct ath5k_buf, list);
  1339. list_del(&bf->list);
  1340. ah->txbuf_len--;
  1341. if (list_empty(&ah->txbuf))
  1342. ieee80211_stop_queues(hw);
  1343. spin_unlock_irqrestore(&ah->txbuflock, flags);
  1344. bf->skb = skb;
  1345. if (ath5k_txbuf_setup(ah, bf, txq, padsize)) {
  1346. bf->skb = NULL;
  1347. spin_lock_irqsave(&ah->txbuflock, flags);
  1348. list_add_tail(&bf->list, &ah->txbuf);
  1349. ah->txbuf_len++;
  1350. spin_unlock_irqrestore(&ah->txbuflock, flags);
  1351. goto drop_packet;
  1352. }
  1353. return;
  1354. drop_packet:
  1355. dev_kfree_skb_any(skb);
  1356. }
  1357. static void
  1358. ath5k_tx_frame_completed(struct ath5k_hw *ah, struct sk_buff *skb,
  1359. struct ath5k_txq *txq, struct ath5k_tx_status *ts)
  1360. {
  1361. struct ieee80211_tx_info *info;
  1362. u8 tries[3];
  1363. int i;
  1364. ah->stats.tx_all_count++;
  1365. ah->stats.tx_bytes_count += skb->len;
  1366. info = IEEE80211_SKB_CB(skb);
  1367. tries[0] = info->status.rates[0].count;
  1368. tries[1] = info->status.rates[1].count;
  1369. tries[2] = info->status.rates[2].count;
  1370. ieee80211_tx_info_clear_status(info);
  1371. for (i = 0; i < ts->ts_final_idx; i++) {
  1372. struct ieee80211_tx_rate *r =
  1373. &info->status.rates[i];
  1374. r->count = tries[i];
  1375. }
  1376. info->status.rates[ts->ts_final_idx].count = ts->ts_final_retry;
  1377. info->status.rates[ts->ts_final_idx + 1].idx = -1;
  1378. if (unlikely(ts->ts_status)) {
  1379. ah->stats.ack_fail++;
  1380. if (ts->ts_status & AR5K_TXERR_FILT) {
  1381. info->flags |= IEEE80211_TX_STAT_TX_FILTERED;
  1382. ah->stats.txerr_filt++;
  1383. }
  1384. if (ts->ts_status & AR5K_TXERR_XRETRY)
  1385. ah->stats.txerr_retry++;
  1386. if (ts->ts_status & AR5K_TXERR_FIFO)
  1387. ah->stats.txerr_fifo++;
  1388. } else {
  1389. info->flags |= IEEE80211_TX_STAT_ACK;
  1390. info->status.ack_signal = ts->ts_rssi;
  1391. /* count the successful attempt as well */
  1392. info->status.rates[ts->ts_final_idx].count++;
  1393. }
  1394. /*
  1395. * Remove MAC header padding before giving the frame
  1396. * back to mac80211.
  1397. */
  1398. ath5k_remove_padding(skb);
  1399. if (ts->ts_antenna > 0 && ts->ts_antenna < 5)
  1400. ah->stats.antenna_tx[ts->ts_antenna]++;
  1401. else
  1402. ah->stats.antenna_tx[0]++; /* invalid */
  1403. trace_ath5k_tx_complete(ah, skb, txq, ts);
  1404. ieee80211_tx_status(ah->hw, skb);
  1405. }
  1406. static void
  1407. ath5k_tx_processq(struct ath5k_hw *ah, struct ath5k_txq *txq)
  1408. {
  1409. struct ath5k_tx_status ts = {};
  1410. struct ath5k_buf *bf, *bf0;
  1411. struct ath5k_desc *ds;
  1412. struct sk_buff *skb;
  1413. int ret;
  1414. spin_lock(&txq->lock);
  1415. list_for_each_entry_safe(bf, bf0, &txq->q, list) {
  1416. txq->txq_poll_mark = false;
  1417. /* skb might already have been processed last time. */
  1418. if (bf->skb != NULL) {
  1419. ds = bf->desc;
  1420. ret = ah->ah_proc_tx_desc(ah, ds, &ts);
  1421. if (unlikely(ret == -EINPROGRESS))
  1422. break;
  1423. else if (unlikely(ret)) {
  1424. ATH5K_ERR(ah,
  1425. "error %d while processing "
  1426. "queue %u\n", ret, txq->qnum);
  1427. break;
  1428. }
  1429. skb = bf->skb;
  1430. bf->skb = NULL;
  1431. dma_unmap_single(ah->dev, bf->skbaddr, skb->len,
  1432. DMA_TO_DEVICE);
  1433. ath5k_tx_frame_completed(ah, skb, txq, &ts);
  1434. }
  1435. /*
  1436. * It's possible that the hardware can say the buffer is
  1437. * completed when it hasn't yet loaded the ds_link from
  1438. * host memory and moved on.
  1439. * Always keep the last descriptor to avoid HW races...
  1440. */
  1441. if (ath5k_hw_get_txdp(ah, txq->qnum) != bf->daddr) {
  1442. spin_lock(&ah->txbuflock);
  1443. list_move_tail(&bf->list, &ah->txbuf);
  1444. ah->txbuf_len++;
  1445. txq->txq_len--;
  1446. spin_unlock(&ah->txbuflock);
  1447. }
  1448. }
  1449. spin_unlock(&txq->lock);
  1450. if (txq->txq_len < ATH5K_TXQ_LEN_LOW && txq->qnum < 4)
  1451. ieee80211_wake_queue(ah->hw, txq->qnum);
  1452. }
  1453. static void
  1454. ath5k_tasklet_tx(unsigned long data)
  1455. {
  1456. int i;
  1457. struct ath5k_hw *ah = (void *)data;
  1458. for (i = 0; i < AR5K_NUM_TX_QUEUES; i++)
  1459. if (ah->txqs[i].setup && (ah->ah_txq_isr & BIT(i)))
  1460. ath5k_tx_processq(ah, &ah->txqs[i]);
  1461. ah->tx_pending = false;
  1462. ath5k_set_current_imask(ah);
  1463. }
  1464. /*****************\
  1465. * Beacon handling *
  1466. \*****************/
  1467. /*
  1468. * Setup the beacon frame for transmit.
  1469. */
  1470. static int
  1471. ath5k_beacon_setup(struct ath5k_hw *ah, struct ath5k_buf *bf)
  1472. {
  1473. struct sk_buff *skb = bf->skb;
  1474. struct ieee80211_tx_info *info = IEEE80211_SKB_CB(skb);
  1475. struct ath5k_desc *ds;
  1476. int ret = 0;
  1477. u8 antenna;
  1478. u32 flags;
  1479. const int padsize = 0;
  1480. bf->skbaddr = dma_map_single(ah->dev, skb->data, skb->len,
  1481. DMA_TO_DEVICE);
  1482. ATH5K_DBG(ah, ATH5K_DEBUG_BEACON, "skb %p [data %p len %u] "
  1483. "skbaddr %llx\n", skb, skb->data, skb->len,
  1484. (unsigned long long)bf->skbaddr);
  1485. if (dma_mapping_error(ah->dev, bf->skbaddr)) {
  1486. ATH5K_ERR(ah, "beacon DMA mapping failed\n");
  1487. dev_kfree_skb_any(skb);
  1488. bf->skb = NULL;
  1489. return -EIO;
  1490. }
  1491. ds = bf->desc;
  1492. antenna = ah->ah_tx_ant;
  1493. flags = AR5K_TXDESC_NOACK;
  1494. if (ah->opmode == NL80211_IFTYPE_ADHOC && ath5k_hw_hasveol(ah)) {
  1495. ds->ds_link = bf->daddr; /* self-linked */
  1496. flags |= AR5K_TXDESC_VEOL;
  1497. } else
  1498. ds->ds_link = 0;
  1499. /*
  1500. * If we use multiple antennas on AP and use
  1501. * the Sectored AP scenario, switch antenna every
  1502. * 4 beacons to make sure everybody hears our AP.
  1503. * When a client tries to associate, hw will keep
  1504. * track of the tx antenna to be used for this client
  1505. * automatically, based on ACKed packets.
  1506. *
  1507. * Note: AP still listens and transmits RTS on the
  1508. * default antenna which is supposed to be an omni.
  1509. *
  1510. * Note2: On sectored scenarios it's possible to have
  1511. * multiple antennas (1 omni -- the default -- and 14
  1512. * sectors), so if we choose to actually support this
  1513. * mode, we need to allow the user to set how many antennas
  1514. * we have and tweak the code below to send beacons
  1515. * on all of them.
  1516. */
  1517. if (ah->ah_ant_mode == AR5K_ANTMODE_SECTOR_AP)
  1518. antenna = ah->bsent & 4 ? 2 : 1;
  1519. /* FIXME: If we are in g mode and rate is a CCK rate
  1520. * subtract ah->ah_txpower.txp_cck_ofdm_pwr_delta
  1521. * from tx power (value is in dB units already) */
  1522. ds->ds_data = bf->skbaddr;
  1523. ret = ah->ah_setup_tx_desc(ah, ds, skb->len,
  1524. ieee80211_get_hdrlen_from_skb(skb), padsize,
  1525. AR5K_PKT_TYPE_BEACON, (ah->power_level * 2),
  1526. ieee80211_get_tx_rate(ah->hw, info)->hw_value,
  1527. 1, AR5K_TXKEYIX_INVALID,
  1528. antenna, flags, 0, 0);
  1529. if (ret)
  1530. goto err_unmap;
  1531. return 0;
  1532. err_unmap:
  1533. dma_unmap_single(ah->dev, bf->skbaddr, skb->len, DMA_TO_DEVICE);
  1534. return ret;
  1535. }
  1536. /*
  1537. * Updates the beacon that is sent by ath5k_beacon_send. For adhoc,
  1538. * this is called only once at config_bss time, for AP we do it every
  1539. * SWBA interrupt so that the TIM will reflect buffered frames.
  1540. *
  1541. * Called with the beacon lock.
  1542. */
  1543. int
  1544. ath5k_beacon_update(struct ieee80211_hw *hw, struct ieee80211_vif *vif)
  1545. {
  1546. int ret;
  1547. struct ath5k_hw *ah = hw->priv;
  1548. struct ath5k_vif *avf = (void *)vif->drv_priv;
  1549. struct sk_buff *skb;
  1550. if (WARN_ON(!vif)) {
  1551. ret = -EINVAL;
  1552. goto out;
  1553. }
  1554. skb = ieee80211_beacon_get(hw, vif);
  1555. if (!skb) {
  1556. ret = -ENOMEM;
  1557. goto out;
  1558. }
  1559. ath5k_txbuf_free_skb(ah, avf->bbuf);
  1560. avf->bbuf->skb = skb;
  1561. ret = ath5k_beacon_setup(ah, avf->bbuf);
  1562. out:
  1563. return ret;
  1564. }
  1565. /*
  1566. * Transmit a beacon frame at SWBA. Dynamic updates to the
  1567. * frame contents are done as needed and the slot time is
  1568. * also adjusted based on current state.
  1569. *
  1570. * This is called from software irq context (beacontq tasklets)
  1571. * or user context from ath5k_beacon_config.
  1572. */
  1573. static void
  1574. ath5k_beacon_send(struct ath5k_hw *ah)
  1575. {
  1576. struct ieee80211_vif *vif;
  1577. struct ath5k_vif *avf;
  1578. struct ath5k_buf *bf;
  1579. struct sk_buff *skb;
  1580. int err;
  1581. ATH5K_DBG_UNLIMIT(ah, ATH5K_DEBUG_BEACON, "in beacon_send\n");
  1582. /*
  1583. * Check if the previous beacon has gone out. If
  1584. * not, don't don't try to post another: skip this
  1585. * period and wait for the next. Missed beacons
  1586. * indicate a problem and should not occur. If we
  1587. * miss too many consecutive beacons reset the device.
  1588. */
  1589. if (unlikely(ath5k_hw_num_tx_pending(ah, ah->bhalq) != 0)) {
  1590. ah->bmisscount++;
  1591. ATH5K_DBG(ah, ATH5K_DEBUG_BEACON,
  1592. "missed %u consecutive beacons\n", ah->bmisscount);
  1593. if (ah->bmisscount > 10) { /* NB: 10 is a guess */
  1594. ATH5K_DBG(ah, ATH5K_DEBUG_BEACON,
  1595. "stuck beacon time (%u missed)\n",
  1596. ah->bmisscount);
  1597. ATH5K_DBG(ah, ATH5K_DEBUG_RESET,
  1598. "stuck beacon, resetting\n");
  1599. ieee80211_queue_work(ah->hw, &ah->reset_work);
  1600. }
  1601. return;
  1602. }
  1603. if (unlikely(ah->bmisscount != 0)) {
  1604. ATH5K_DBG(ah, ATH5K_DEBUG_BEACON,
  1605. "resume beacon xmit after %u misses\n",
  1606. ah->bmisscount);
  1607. ah->bmisscount = 0;
  1608. }
  1609. if ((ah->opmode == NL80211_IFTYPE_AP && ah->num_ap_vifs > 1) ||
  1610. ah->opmode == NL80211_IFTYPE_MESH_POINT) {
  1611. u64 tsf = ath5k_hw_get_tsf64(ah);
  1612. u32 tsftu = TSF_TO_TU(tsf);
  1613. int slot = ((tsftu % ah->bintval) * ATH_BCBUF) / ah->bintval;
  1614. vif = ah->bslot[(slot + 1) % ATH_BCBUF];
  1615. ATH5K_DBG(ah, ATH5K_DEBUG_BEACON,
  1616. "tsf %llx tsftu %x intval %u slot %u vif %p\n",
  1617. (unsigned long long)tsf, tsftu, ah->bintval, slot, vif);
  1618. } else /* only one interface */
  1619. vif = ah->bslot[0];
  1620. if (!vif)
  1621. return;
  1622. avf = (void *)vif->drv_priv;
  1623. bf = avf->bbuf;
  1624. /*
  1625. * Stop any current dma and put the new frame on the queue.
  1626. * This should never fail since we check above that no frames
  1627. * are still pending on the queue.
  1628. */
  1629. if (unlikely(ath5k_hw_stop_beacon_queue(ah, ah->bhalq))) {
  1630. ATH5K_WARN(ah, "beacon queue %u didn't start/stop ?\n", ah->bhalq);
  1631. /* NB: hw still stops DMA, so proceed */
  1632. }
  1633. /* refresh the beacon for AP or MESH mode */
  1634. if (ah->opmode == NL80211_IFTYPE_AP ||
  1635. ah->opmode == NL80211_IFTYPE_MESH_POINT) {
  1636. err = ath5k_beacon_update(ah->hw, vif);
  1637. if (err)
  1638. return;
  1639. }
  1640. if (unlikely(bf->skb == NULL || ah->opmode == NL80211_IFTYPE_STATION ||
  1641. ah->opmode == NL80211_IFTYPE_MONITOR)) {
  1642. ATH5K_WARN(ah, "bf=%p bf_skb=%p\n", bf, bf->skb);
  1643. return;
  1644. }
  1645. trace_ath5k_tx(ah, bf->skb, &ah->txqs[ah->bhalq]);
  1646. ath5k_hw_set_txdp(ah, ah->bhalq, bf->daddr);
  1647. ath5k_hw_start_tx_dma(ah, ah->bhalq);
  1648. ATH5K_DBG(ah, ATH5K_DEBUG_BEACON, "TXDP[%u] = %llx (%p)\n",
  1649. ah->bhalq, (unsigned long long)bf->daddr, bf->desc);
  1650. skb = ieee80211_get_buffered_bc(ah->hw, vif);
  1651. while (skb) {
  1652. ath5k_tx_queue(ah->hw, skb, ah->cabq);
  1653. if (ah->cabq->txq_len >= ah->cabq->txq_max)
  1654. break;
  1655. skb = ieee80211_get_buffered_bc(ah->hw, vif);
  1656. }
  1657. ah->bsent++;
  1658. }
  1659. /**
  1660. * ath5k_beacon_update_timers - update beacon timers
  1661. *
  1662. * @ah: struct ath5k_hw pointer we are operating on
  1663. * @bc_tsf: the timestamp of the beacon. 0 to reset the TSF. -1 to perform a
  1664. * beacon timer update based on the current HW TSF.
  1665. *
  1666. * Calculate the next target beacon transmit time (TBTT) based on the timestamp
  1667. * of a received beacon or the current local hardware TSF and write it to the
  1668. * beacon timer registers.
  1669. *
  1670. * This is called in a variety of situations, e.g. when a beacon is received,
  1671. * when a TSF update has been detected, but also when an new IBSS is created or
  1672. * when we otherwise know we have to update the timers, but we keep it in this
  1673. * function to have it all together in one place.
  1674. */
  1675. void
  1676. ath5k_beacon_update_timers(struct ath5k_hw *ah, u64 bc_tsf)
  1677. {
  1678. u32 nexttbtt, intval, hw_tu, bc_tu;
  1679. u64 hw_tsf;
  1680. intval = ah->bintval & AR5K_BEACON_PERIOD;
  1681. if (ah->opmode == NL80211_IFTYPE_AP && ah->num_ap_vifs > 1) {
  1682. intval /= ATH_BCBUF; /* staggered multi-bss beacons */
  1683. if (intval < 15)
  1684. ATH5K_WARN(ah, "intval %u is too low, min 15\n",
  1685. intval);
  1686. }
  1687. if (WARN_ON(!intval))
  1688. return;
  1689. /* beacon TSF converted to TU */
  1690. bc_tu = TSF_TO_TU(bc_tsf);
  1691. /* current TSF converted to TU */
  1692. hw_tsf = ath5k_hw_get_tsf64(ah);
  1693. hw_tu = TSF_TO_TU(hw_tsf);
  1694. #define FUDGE (AR5K_TUNE_SW_BEACON_RESP + 3)
  1695. /* We use FUDGE to make sure the next TBTT is ahead of the current TU.
  1696. * Since we later subtract AR5K_TUNE_SW_BEACON_RESP (10) in the timer
  1697. * configuration we need to make sure it is bigger than that. */
  1698. if (bc_tsf == -1) {
  1699. /*
  1700. * no beacons received, called internally.
  1701. * just need to refresh timers based on HW TSF.
  1702. */
  1703. nexttbtt = roundup(hw_tu + FUDGE, intval);
  1704. } else if (bc_tsf == 0) {
  1705. /*
  1706. * no beacon received, probably called by ath5k_reset_tsf().
  1707. * reset TSF to start with 0.
  1708. */
  1709. nexttbtt = intval;
  1710. intval |= AR5K_BEACON_RESET_TSF;
  1711. } else if (bc_tsf > hw_tsf) {
  1712. /*
  1713. * beacon received, SW merge happened but HW TSF not yet updated.
  1714. * not possible to reconfigure timers yet, but next time we
  1715. * receive a beacon with the same BSSID, the hardware will
  1716. * automatically update the TSF and then we need to reconfigure
  1717. * the timers.
  1718. */
  1719. ATH5K_DBG_UNLIMIT(ah, ATH5K_DEBUG_BEACON,
  1720. "need to wait for HW TSF sync\n");
  1721. return;
  1722. } else {
  1723. /*
  1724. * most important case for beacon synchronization between STA.
  1725. *
  1726. * beacon received and HW TSF has been already updated by HW.
  1727. * update next TBTT based on the TSF of the beacon, but make
  1728. * sure it is ahead of our local TSF timer.
  1729. */
  1730. nexttbtt = bc_tu + roundup(hw_tu + FUDGE - bc_tu, intval);
  1731. }
  1732. #undef FUDGE
  1733. ah->nexttbtt = nexttbtt;
  1734. intval |= AR5K_BEACON_ENA;
  1735. ath5k_hw_init_beacon(ah, nexttbtt, intval);
  1736. /*
  1737. * debugging output last in order to preserve the time critical aspect
  1738. * of this function
  1739. */
  1740. if (bc_tsf == -1)
  1741. ATH5K_DBG_UNLIMIT(ah, ATH5K_DEBUG_BEACON,
  1742. "reconfigured timers based on HW TSF\n");
  1743. else if (bc_tsf == 0)
  1744. ATH5K_DBG_UNLIMIT(ah, ATH5K_DEBUG_BEACON,
  1745. "reset HW TSF and timers\n");
  1746. else
  1747. ATH5K_DBG_UNLIMIT(ah, ATH5K_DEBUG_BEACON,
  1748. "updated timers based on beacon TSF\n");
  1749. ATH5K_DBG_UNLIMIT(ah, ATH5K_DEBUG_BEACON,
  1750. "bc_tsf %llx hw_tsf %llx bc_tu %u hw_tu %u nexttbtt %u\n",
  1751. (unsigned long long) bc_tsf,
  1752. (unsigned long long) hw_tsf, bc_tu, hw_tu, nexttbtt);
  1753. ATH5K_DBG_UNLIMIT(ah, ATH5K_DEBUG_BEACON, "intval %u %s %s\n",
  1754. intval & AR5K_BEACON_PERIOD,
  1755. intval & AR5K_BEACON_ENA ? "AR5K_BEACON_ENA" : "",
  1756. intval & AR5K_BEACON_RESET_TSF ? "AR5K_BEACON_RESET_TSF" : "");
  1757. }
  1758. /**
  1759. * ath5k_beacon_config - Configure the beacon queues and interrupts
  1760. *
  1761. * @ah: struct ath5k_hw pointer we are operating on
  1762. *
  1763. * In IBSS mode we use a self-linked tx descriptor if possible. We enable SWBA
  1764. * interrupts to detect TSF updates only.
  1765. */
  1766. void
  1767. ath5k_beacon_config(struct ath5k_hw *ah)
  1768. {
  1769. unsigned long flags;
  1770. spin_lock_irqsave(&ah->block, flags);
  1771. ah->bmisscount = 0;
  1772. ah->imask &= ~(AR5K_INT_BMISS | AR5K_INT_SWBA);
  1773. if (ah->enable_beacon) {
  1774. /*
  1775. * In IBSS mode we use a self-linked tx descriptor and let the
  1776. * hardware send the beacons automatically. We have to load it
  1777. * only once here.
  1778. * We use the SWBA interrupt only to keep track of the beacon
  1779. * timers in order to detect automatic TSF updates.
  1780. */
  1781. ath5k_beaconq_config(ah);
  1782. ah->imask |= AR5K_INT_SWBA;
  1783. if (ah->opmode == NL80211_IFTYPE_ADHOC) {
  1784. if (ath5k_hw_hasveol(ah))
  1785. ath5k_beacon_send(ah);
  1786. } else
  1787. ath5k_beacon_update_timers(ah, -1);
  1788. } else {
  1789. ath5k_hw_stop_beacon_queue(ah, ah->bhalq);
  1790. }
  1791. ath5k_hw_set_imr(ah, ah->imask);
  1792. mmiowb();
  1793. spin_unlock_irqrestore(&ah->block, flags);
  1794. }
  1795. static void ath5k_tasklet_beacon(unsigned long data)
  1796. {
  1797. struct ath5k_hw *ah = (struct ath5k_hw *) data;
  1798. /*
  1799. * Software beacon alert--time to send a beacon.
  1800. *
  1801. * In IBSS mode we use this interrupt just to
  1802. * keep track of the next TBTT (target beacon
  1803. * transmission time) in order to detect whether
  1804. * automatic TSF updates happened.
  1805. */
  1806. if (ah->opmode == NL80211_IFTYPE_ADHOC) {
  1807. /* XXX: only if VEOL supported */
  1808. u64 tsf = ath5k_hw_get_tsf64(ah);
  1809. ah->nexttbtt += ah->bintval;
  1810. ATH5K_DBG(ah, ATH5K_DEBUG_BEACON,
  1811. "SWBA nexttbtt: %x hw_tu: %x "
  1812. "TSF: %llx\n",
  1813. ah->nexttbtt,
  1814. TSF_TO_TU(tsf),
  1815. (unsigned long long) tsf);
  1816. } else {
  1817. spin_lock(&ah->block);
  1818. ath5k_beacon_send(ah);
  1819. spin_unlock(&ah->block);
  1820. }
  1821. }
  1822. /********************\
  1823. * Interrupt handling *
  1824. \********************/
  1825. static void
  1826. ath5k_intr_calibration_poll(struct ath5k_hw *ah)
  1827. {
  1828. if (time_is_before_eq_jiffies(ah->ah_cal_next_ani) &&
  1829. !(ah->ah_cal_mask & AR5K_CALIBRATION_FULL)) {
  1830. /* run ANI only when full calibration is not active */
  1831. ah->ah_cal_next_ani = jiffies +
  1832. msecs_to_jiffies(ATH5K_TUNE_CALIBRATION_INTERVAL_ANI);
  1833. tasklet_schedule(&ah->ani_tasklet);
  1834. } else if (time_is_before_eq_jiffies(ah->ah_cal_next_full)) {
  1835. ah->ah_cal_next_full = jiffies +
  1836. msecs_to_jiffies(ATH5K_TUNE_CALIBRATION_INTERVAL_FULL);
  1837. tasklet_schedule(&ah->calib);
  1838. }
  1839. /* we could use SWI to generate enough interrupts to meet our
  1840. * calibration interval requirements, if necessary:
  1841. * AR5K_REG_ENABLE_BITS(ah, AR5K_CR, AR5K_CR_SWI); */
  1842. }
  1843. static void
  1844. ath5k_schedule_rx(struct ath5k_hw *ah)
  1845. {
  1846. ah->rx_pending = true;
  1847. tasklet_schedule(&ah->rxtq);
  1848. }
  1849. static void
  1850. ath5k_schedule_tx(struct ath5k_hw *ah)
  1851. {
  1852. ah->tx_pending = true;
  1853. tasklet_schedule(&ah->txtq);
  1854. }
  1855. static irqreturn_t
  1856. ath5k_intr(int irq, void *dev_id)
  1857. {
  1858. struct ath5k_hw *ah = dev_id;
  1859. enum ath5k_int status;
  1860. unsigned int counter = 1000;
  1861. if (unlikely(test_bit(ATH_STAT_INVALID, ah->status) ||
  1862. ((ath5k_get_bus_type(ah) != ATH_AHB) &&
  1863. !ath5k_hw_is_intr_pending(ah))))
  1864. return IRQ_NONE;
  1865. do {
  1866. ath5k_hw_get_isr(ah, &status); /* NB: clears IRQ too */
  1867. ATH5K_DBG(ah, ATH5K_DEBUG_INTR, "status 0x%x/0x%x\n",
  1868. status, ah->imask);
  1869. if (unlikely(status & AR5K_INT_FATAL)) {
  1870. /*
  1871. * Fatal errors are unrecoverable.
  1872. * Typically these are caused by DMA errors.
  1873. */
  1874. ATH5K_DBG(ah, ATH5K_DEBUG_RESET,
  1875. "fatal int, resetting\n");
  1876. ieee80211_queue_work(ah->hw, &ah->reset_work);
  1877. } else if (unlikely(status & AR5K_INT_RXORN)) {
  1878. /*
  1879. * Receive buffers are full. Either the bus is busy or
  1880. * the CPU is not fast enough to process all received
  1881. * frames.
  1882. * Older chipsets need a reset to come out of this
  1883. * condition, but we treat it as RX for newer chips.
  1884. * We don't know exactly which versions need a reset -
  1885. * this guess is copied from the HAL.
  1886. */
  1887. ah->stats.rxorn_intr++;
  1888. if (ah->ah_mac_srev < AR5K_SREV_AR5212) {
  1889. ATH5K_DBG(ah, ATH5K_DEBUG_RESET,
  1890. "rx overrun, resetting\n");
  1891. ieee80211_queue_work(ah->hw, &ah->reset_work);
  1892. } else
  1893. ath5k_schedule_rx(ah);
  1894. } else {
  1895. if (status & AR5K_INT_SWBA)
  1896. tasklet_hi_schedule(&ah->beacontq);
  1897. if (status & AR5K_INT_RXEOL) {
  1898. /*
  1899. * NB: the hardware should re-read the link when
  1900. * RXE bit is written, but it doesn't work at
  1901. * least on older hardware revs.
  1902. */
  1903. ah->stats.rxeol_intr++;
  1904. }
  1905. if (status & AR5K_INT_TXURN) {
  1906. /* bump tx trigger level */
  1907. ath5k_hw_update_tx_triglevel(ah, true);
  1908. }
  1909. if (status & (AR5K_INT_RXOK | AR5K_INT_RXERR))
  1910. ath5k_schedule_rx(ah);
  1911. if (status & (AR5K_INT_TXOK | AR5K_INT_TXDESC
  1912. | AR5K_INT_TXERR | AR5K_INT_TXEOL))
  1913. ath5k_schedule_tx(ah);
  1914. if (status & AR5K_INT_BMISS) {
  1915. /* TODO */
  1916. }
  1917. if (status & AR5K_INT_MIB) {
  1918. ah->stats.mib_intr++;
  1919. ath5k_hw_update_mib_counters(ah);
  1920. ath5k_ani_mib_intr(ah);
  1921. }
  1922. if (status & AR5K_INT_GPIO)
  1923. tasklet_schedule(&ah->rf_kill.toggleq);
  1924. }
  1925. if (ath5k_get_bus_type(ah) == ATH_AHB)
  1926. break;
  1927. } while (ath5k_hw_is_intr_pending(ah) && --counter > 0);
  1928. if (ah->rx_pending || ah->tx_pending)
  1929. ath5k_set_current_imask(ah);
  1930. if (unlikely(!counter))
  1931. ATH5K_WARN(ah, "too many interrupts, giving up for now\n");
  1932. ath5k_intr_calibration_poll(ah);
  1933. return IRQ_HANDLED;
  1934. }
  1935. /*
  1936. * Periodically recalibrate the PHY to account
  1937. * for temperature/environment changes.
  1938. */
  1939. static void
  1940. ath5k_tasklet_calibrate(unsigned long data)
  1941. {
  1942. struct ath5k_hw *ah = (void *)data;
  1943. /* Only full calibration for now */
  1944. ah->ah_cal_mask |= AR5K_CALIBRATION_FULL;
  1945. ATH5K_DBG(ah, ATH5K_DEBUG_CALIBRATE, "channel %u/%x\n",
  1946. ieee80211_frequency_to_channel(ah->curchan->center_freq),
  1947. ah->curchan->hw_value);
  1948. if (ath5k_hw_gainf_calibrate(ah) == AR5K_RFGAIN_NEED_CHANGE) {
  1949. /*
  1950. * Rfgain is out of bounds, reset the chip
  1951. * to load new gain values.
  1952. */
  1953. ATH5K_DBG(ah, ATH5K_DEBUG_RESET, "calibration, resetting\n");
  1954. ieee80211_queue_work(ah->hw, &ah->reset_work);
  1955. }
  1956. if (ath5k_hw_phy_calibrate(ah, ah->curchan))
  1957. ATH5K_ERR(ah, "calibration of channel %u failed\n",
  1958. ieee80211_frequency_to_channel(
  1959. ah->curchan->center_freq));
  1960. /* Noise floor calibration interrupts rx/tx path while I/Q calibration
  1961. * doesn't.
  1962. * TODO: We should stop TX here, so that it doesn't interfere.
  1963. * Note that stopping the queues is not enough to stop TX! */
  1964. if (time_is_before_eq_jiffies(ah->ah_cal_next_nf)) {
  1965. ah->ah_cal_next_nf = jiffies +
  1966. msecs_to_jiffies(ATH5K_TUNE_CALIBRATION_INTERVAL_NF);
  1967. ath5k_hw_update_noise_floor(ah);
  1968. }
  1969. ah->ah_cal_mask &= ~AR5K_CALIBRATION_FULL;
  1970. }
  1971. static void
  1972. ath5k_tasklet_ani(unsigned long data)
  1973. {
  1974. struct ath5k_hw *ah = (void *)data;
  1975. ah->ah_cal_mask |= AR5K_CALIBRATION_ANI;
  1976. ath5k_ani_calibration(ah);
  1977. ah->ah_cal_mask &= ~AR5K_CALIBRATION_ANI;
  1978. }
  1979. static void
  1980. ath5k_tx_complete_poll_work(struct work_struct *work)
  1981. {
  1982. struct ath5k_hw *ah = container_of(work, struct ath5k_hw,
  1983. tx_complete_work.work);
  1984. struct ath5k_txq *txq;
  1985. int i;
  1986. bool needreset = false;
  1987. mutex_lock(&ah->lock);
  1988. for (i = 0; i < ARRAY_SIZE(ah->txqs); i++) {
  1989. if (ah->txqs[i].setup) {
  1990. txq = &ah->txqs[i];
  1991. spin_lock_bh(&txq->lock);
  1992. if (txq->txq_len > 1) {
  1993. if (txq->txq_poll_mark) {
  1994. ATH5K_DBG(ah, ATH5K_DEBUG_XMIT,
  1995. "TX queue stuck %d\n",
  1996. txq->qnum);
  1997. needreset = true;
  1998. txq->txq_stuck++;
  1999. spin_unlock_bh(&txq->lock);
  2000. break;
  2001. } else {
  2002. txq->txq_poll_mark = true;
  2003. }
  2004. }
  2005. spin_unlock_bh(&txq->lock);
  2006. }
  2007. }
  2008. if (needreset) {
  2009. ATH5K_DBG(ah, ATH5K_DEBUG_RESET,
  2010. "TX queues stuck, resetting\n");
  2011. ath5k_reset(ah, NULL, true);
  2012. }
  2013. mutex_unlock(&ah->lock);
  2014. ieee80211_queue_delayed_work(ah->hw, &ah->tx_complete_work,
  2015. msecs_to_jiffies(ATH5K_TX_COMPLETE_POLL_INT));
  2016. }
  2017. /*************************\
  2018. * Initialization routines *
  2019. \*************************/
  2020. int __devinit
  2021. ath5k_init_softc(struct ath5k_hw *ah, const struct ath_bus_ops *bus_ops)
  2022. {
  2023. struct ieee80211_hw *hw = ah->hw;
  2024. struct ath_common *common;
  2025. int ret;
  2026. int csz;
  2027. /* Initialize driver private data */
  2028. SET_IEEE80211_DEV(hw, ah->dev);
  2029. hw->flags = IEEE80211_HW_RX_INCLUDES_FCS |
  2030. IEEE80211_HW_HOST_BROADCAST_PS_BUFFERING |
  2031. IEEE80211_HW_SIGNAL_DBM |
  2032. IEEE80211_HW_REPORTS_TX_ACK_STATUS;
  2033. hw->wiphy->interface_modes =
  2034. BIT(NL80211_IFTYPE_AP) |
  2035. BIT(NL80211_IFTYPE_STATION) |
  2036. BIT(NL80211_IFTYPE_ADHOC) |
  2037. BIT(NL80211_IFTYPE_MESH_POINT);
  2038. /* both antennas can be configured as RX or TX */
  2039. hw->wiphy->available_antennas_tx = 0x3;
  2040. hw->wiphy->available_antennas_rx = 0x3;
  2041. hw->extra_tx_headroom = 2;
  2042. hw->channel_change_time = 5000;
  2043. /*
  2044. * Mark the device as detached to avoid processing
  2045. * interrupts until setup is complete.
  2046. */
  2047. __set_bit(ATH_STAT_INVALID, ah->status);
  2048. ah->opmode = NL80211_IFTYPE_STATION;
  2049. ah->bintval = 1000;
  2050. mutex_init(&ah->lock);
  2051. spin_lock_init(&ah->rxbuflock);
  2052. spin_lock_init(&ah->txbuflock);
  2053. spin_lock_init(&ah->block);
  2054. spin_lock_init(&ah->irqlock);
  2055. /* Setup interrupt handler */
  2056. ret = request_irq(ah->irq, ath5k_intr, IRQF_SHARED, "ath", ah);
  2057. if (ret) {
  2058. ATH5K_ERR(ah, "request_irq failed\n");
  2059. goto err;
  2060. }
  2061. common = ath5k_hw_common(ah);
  2062. common->ops = &ath5k_common_ops;
  2063. common->bus_ops = bus_ops;
  2064. common->ah = ah;
  2065. common->hw = hw;
  2066. common->priv = ah;
  2067. common->clockrate = 40;
  2068. /*
  2069. * Cache line size is used to size and align various
  2070. * structures used to communicate with the hardware.
  2071. */
  2072. ath5k_read_cachesize(common, &csz);
  2073. common->cachelsz = csz << 2; /* convert to bytes */
  2074. spin_lock_init(&common->cc_lock);
  2075. /* Initialize device */
  2076. ret = ath5k_hw_init(ah);
  2077. if (ret)
  2078. goto err_irq;
  2079. /* set up multi-rate retry capabilities */
  2080. if (ah->ah_version == AR5K_AR5212) {
  2081. hw->max_rates = 4;
  2082. hw->max_rate_tries = max(AR5K_INIT_RETRY_SHORT,
  2083. AR5K_INIT_RETRY_LONG);
  2084. }
  2085. hw->vif_data_size = sizeof(struct ath5k_vif);
  2086. /* Finish private driver data initialization */
  2087. ret = ath5k_init(hw);
  2088. if (ret)
  2089. goto err_ah;
  2090. ATH5K_INFO(ah, "Atheros AR%s chip found (MAC: 0x%x, PHY: 0x%x)\n",
  2091. ath5k_chip_name(AR5K_VERSION_MAC, ah->ah_mac_srev),
  2092. ah->ah_mac_srev,
  2093. ah->ah_phy_revision);
  2094. if (!ah->ah_single_chip) {
  2095. /* Single chip radio (!RF5111) */
  2096. if (ah->ah_radio_5ghz_revision &&
  2097. !ah->ah_radio_2ghz_revision) {
  2098. /* No 5GHz support -> report 2GHz radio */
  2099. if (!test_bit(AR5K_MODE_11A,
  2100. ah->ah_capabilities.cap_mode)) {
  2101. ATH5K_INFO(ah, "RF%s 2GHz radio found (0x%x)\n",
  2102. ath5k_chip_name(AR5K_VERSION_RAD,
  2103. ah->ah_radio_5ghz_revision),
  2104. ah->ah_radio_5ghz_revision);
  2105. /* No 2GHz support (5110 and some
  2106. * 5GHz only cards) -> report 5GHz radio */
  2107. } else if (!test_bit(AR5K_MODE_11B,
  2108. ah->ah_capabilities.cap_mode)) {
  2109. ATH5K_INFO(ah, "RF%s 5GHz radio found (0x%x)\n",
  2110. ath5k_chip_name(AR5K_VERSION_RAD,
  2111. ah->ah_radio_5ghz_revision),
  2112. ah->ah_radio_5ghz_revision);
  2113. /* Multiband radio */
  2114. } else {
  2115. ATH5K_INFO(ah, "RF%s multiband radio found"
  2116. " (0x%x)\n",
  2117. ath5k_chip_name(AR5K_VERSION_RAD,
  2118. ah->ah_radio_5ghz_revision),
  2119. ah->ah_radio_5ghz_revision);
  2120. }
  2121. }
  2122. /* Multi chip radio (RF5111 - RF2111) ->
  2123. * report both 2GHz/5GHz radios */
  2124. else if (ah->ah_radio_5ghz_revision &&
  2125. ah->ah_radio_2ghz_revision) {
  2126. ATH5K_INFO(ah, "RF%s 5GHz radio found (0x%x)\n",
  2127. ath5k_chip_name(AR5K_VERSION_RAD,
  2128. ah->ah_radio_5ghz_revision),
  2129. ah->ah_radio_5ghz_revision);
  2130. ATH5K_INFO(ah, "RF%s 2GHz radio found (0x%x)\n",
  2131. ath5k_chip_name(AR5K_VERSION_RAD,
  2132. ah->ah_radio_2ghz_revision),
  2133. ah->ah_radio_2ghz_revision);
  2134. }
  2135. }
  2136. ath5k_debug_init_device(ah);
  2137. /* ready to process interrupts */
  2138. __clear_bit(ATH_STAT_INVALID, ah->status);
  2139. return 0;
  2140. err_ah:
  2141. ath5k_hw_deinit(ah);
  2142. err_irq:
  2143. free_irq(ah->irq, ah);
  2144. err:
  2145. return ret;
  2146. }
  2147. static int
  2148. ath5k_stop_locked(struct ath5k_hw *ah)
  2149. {
  2150. ATH5K_DBG(ah, ATH5K_DEBUG_RESET, "invalid %u\n",
  2151. test_bit(ATH_STAT_INVALID, ah->status));
  2152. /*
  2153. * Shutdown the hardware and driver:
  2154. * stop output from above
  2155. * disable interrupts
  2156. * turn off timers
  2157. * turn off the radio
  2158. * clear transmit machinery
  2159. * clear receive machinery
  2160. * drain and release tx queues
  2161. * reclaim beacon resources
  2162. * power down hardware
  2163. *
  2164. * Note that some of this work is not possible if the
  2165. * hardware is gone (invalid).
  2166. */
  2167. ieee80211_stop_queues(ah->hw);
  2168. if (!test_bit(ATH_STAT_INVALID, ah->status)) {
  2169. ath5k_led_off(ah);
  2170. ath5k_hw_set_imr(ah, 0);
  2171. synchronize_irq(ah->irq);
  2172. ath5k_rx_stop(ah);
  2173. ath5k_hw_dma_stop(ah);
  2174. ath5k_drain_tx_buffs(ah);
  2175. ath5k_hw_phy_disable(ah);
  2176. }
  2177. return 0;
  2178. }
  2179. int ath5k_start(struct ieee80211_hw *hw)
  2180. {
  2181. struct ath5k_hw *ah = hw->priv;
  2182. struct ath_common *common = ath5k_hw_common(ah);
  2183. int ret, i;
  2184. mutex_lock(&ah->lock);
  2185. ATH5K_DBG(ah, ATH5K_DEBUG_RESET, "mode %d\n", ah->opmode);
  2186. /*
  2187. * Stop anything previously setup. This is safe
  2188. * no matter this is the first time through or not.
  2189. */
  2190. ath5k_stop_locked(ah);
  2191. /*
  2192. * The basic interface to setting the hardware in a good
  2193. * state is ``reset''. On return the hardware is known to
  2194. * be powered up and with interrupts disabled. This must
  2195. * be followed by initialization of the appropriate bits
  2196. * and then setup of the interrupt mask.
  2197. */
  2198. ah->curchan = ah->hw->conf.channel;
  2199. ah->imask = AR5K_INT_RXOK | AR5K_INT_RXERR | AR5K_INT_RXEOL |
  2200. AR5K_INT_RXORN | AR5K_INT_TXDESC | AR5K_INT_TXEOL |
  2201. AR5K_INT_FATAL | AR5K_INT_GLOBAL | AR5K_INT_MIB;
  2202. ret = ath5k_reset(ah, NULL, false);
  2203. if (ret)
  2204. goto done;
  2205. ath5k_rfkill_hw_start(ah);
  2206. /*
  2207. * Reset the key cache since some parts do not reset the
  2208. * contents on initial power up or resume from suspend.
  2209. */
  2210. for (i = 0; i < common->keymax; i++)
  2211. ath_hw_keyreset(common, (u16) i);
  2212. /* Use higher rates for acks instead of base
  2213. * rate */
  2214. ah->ah_ack_bitrate_high = true;
  2215. for (i = 0; i < ARRAY_SIZE(ah->bslot); i++)
  2216. ah->bslot[i] = NULL;
  2217. ret = 0;
  2218. done:
  2219. mmiowb();
  2220. mutex_unlock(&ah->lock);
  2221. ieee80211_queue_delayed_work(ah->hw, &ah->tx_complete_work,
  2222. msecs_to_jiffies(ATH5K_TX_COMPLETE_POLL_INT));
  2223. return ret;
  2224. }
  2225. static void ath5k_stop_tasklets(struct ath5k_hw *ah)
  2226. {
  2227. ah->rx_pending = false;
  2228. ah->tx_pending = false;
  2229. tasklet_kill(&ah->rxtq);
  2230. tasklet_kill(&ah->txtq);
  2231. tasklet_kill(&ah->calib);
  2232. tasklet_kill(&ah->beacontq);
  2233. tasklet_kill(&ah->ani_tasklet);
  2234. }
  2235. /*
  2236. * Stop the device, grabbing the top-level lock to protect
  2237. * against concurrent entry through ath5k_init (which can happen
  2238. * if another thread does a system call and the thread doing the
  2239. * stop is preempted).
  2240. */
  2241. void ath5k_stop(struct ieee80211_hw *hw)
  2242. {
  2243. struct ath5k_hw *ah = hw->priv;
  2244. int ret;
  2245. mutex_lock(&ah->lock);
  2246. ret = ath5k_stop_locked(ah);
  2247. if (ret == 0 && !test_bit(ATH_STAT_INVALID, ah->status)) {
  2248. /*
  2249. * Don't set the card in full sleep mode!
  2250. *
  2251. * a) When the device is in this state it must be carefully
  2252. * woken up or references to registers in the PCI clock
  2253. * domain may freeze the bus (and system). This varies
  2254. * by chip and is mostly an issue with newer parts
  2255. * (madwifi sources mentioned srev >= 0x78) that go to
  2256. * sleep more quickly.
  2257. *
  2258. * b) On older chips full sleep results a weird behaviour
  2259. * during wakeup. I tested various cards with srev < 0x78
  2260. * and they don't wake up after module reload, a second
  2261. * module reload is needed to bring the card up again.
  2262. *
  2263. * Until we figure out what's going on don't enable
  2264. * full chip reset on any chip (this is what Legacy HAL
  2265. * and Sam's HAL do anyway). Instead Perform a full reset
  2266. * on the device (same as initial state after attach) and
  2267. * leave it idle (keep MAC/BB on warm reset) */
  2268. ret = ath5k_hw_on_hold(ah);
  2269. ATH5K_DBG(ah, ATH5K_DEBUG_RESET,
  2270. "putting device to sleep\n");
  2271. }
  2272. mmiowb();
  2273. mutex_unlock(&ah->lock);
  2274. ath5k_stop_tasklets(ah);
  2275. cancel_delayed_work_sync(&ah->tx_complete_work);
  2276. ath5k_rfkill_hw_stop(ah);
  2277. }
  2278. /*
  2279. * Reset the hardware. If chan is not NULL, then also pause rx/tx
  2280. * and change to the given channel.
  2281. *
  2282. * This should be called with ah->lock.
  2283. */
  2284. static int
  2285. ath5k_reset(struct ath5k_hw *ah, struct ieee80211_channel *chan,
  2286. bool skip_pcu)
  2287. {
  2288. struct ath_common *common = ath5k_hw_common(ah);
  2289. int ret, ani_mode;
  2290. bool fast;
  2291. ATH5K_DBG(ah, ATH5K_DEBUG_RESET, "resetting\n");
  2292. ath5k_hw_set_imr(ah, 0);
  2293. synchronize_irq(ah->irq);
  2294. ath5k_stop_tasklets(ah);
  2295. /* Save ani mode and disable ANI during
  2296. * reset. If we don't we might get false
  2297. * PHY error interrupts. */
  2298. ani_mode = ah->ani_state.ani_mode;
  2299. ath5k_ani_init(ah, ATH5K_ANI_MODE_OFF);
  2300. /* We are going to empty hw queues
  2301. * so we should also free any remaining
  2302. * tx buffers */
  2303. ath5k_drain_tx_buffs(ah);
  2304. if (chan)
  2305. ah->curchan = chan;
  2306. fast = ((chan != NULL) && modparam_fastchanswitch) ? 1 : 0;
  2307. ret = ath5k_hw_reset(ah, ah->opmode, ah->curchan, fast, skip_pcu);
  2308. if (ret) {
  2309. ATH5K_ERR(ah, "can't reset hardware (%d)\n", ret);
  2310. goto err;
  2311. }
  2312. ret = ath5k_rx_start(ah);
  2313. if (ret) {
  2314. ATH5K_ERR(ah, "can't start recv logic\n");
  2315. goto err;
  2316. }
  2317. ath5k_ani_init(ah, ani_mode);
  2318. ah->ah_cal_next_full = jiffies + msecs_to_jiffies(100);
  2319. ah->ah_cal_next_ani = jiffies;
  2320. ah->ah_cal_next_nf = jiffies;
  2321. ewma_init(&ah->ah_beacon_rssi_avg, 1024, 8);
  2322. /* clear survey data and cycle counters */
  2323. memset(&ah->survey, 0, sizeof(ah->survey));
  2324. spin_lock_bh(&common->cc_lock);
  2325. ath_hw_cycle_counters_update(common);
  2326. memset(&common->cc_survey, 0, sizeof(common->cc_survey));
  2327. memset(&common->cc_ani, 0, sizeof(common->cc_ani));
  2328. spin_unlock_bh(&common->cc_lock);
  2329. /*
  2330. * Change channels and update the h/w rate map if we're switching;
  2331. * e.g. 11a to 11b/g.
  2332. *
  2333. * We may be doing a reset in response to an ioctl that changes the
  2334. * channel so update any state that might change as a result.
  2335. *
  2336. * XXX needed?
  2337. */
  2338. /* ath5k_chan_change(ah, c); */
  2339. ath5k_beacon_config(ah);
  2340. /* intrs are enabled by ath5k_beacon_config */
  2341. ieee80211_wake_queues(ah->hw);
  2342. return 0;
  2343. err:
  2344. return ret;
  2345. }
  2346. static void ath5k_reset_work(struct work_struct *work)
  2347. {
  2348. struct ath5k_hw *ah = container_of(work, struct ath5k_hw,
  2349. reset_work);
  2350. mutex_lock(&ah->lock);
  2351. ath5k_reset(ah, NULL, true);
  2352. mutex_unlock(&ah->lock);
  2353. }
  2354. static int __devinit
  2355. ath5k_init(struct ieee80211_hw *hw)
  2356. {
  2357. struct ath5k_hw *ah = hw->priv;
  2358. struct ath_regulatory *regulatory = ath5k_hw_regulatory(ah);
  2359. struct ath5k_txq *txq;
  2360. u8 mac[ETH_ALEN] = {};
  2361. int ret;
  2362. /*
  2363. * Check if the MAC has multi-rate retry support.
  2364. * We do this by trying to setup a fake extended
  2365. * descriptor. MACs that don't have support will
  2366. * return false w/o doing anything. MACs that do
  2367. * support it will return true w/o doing anything.
  2368. */
  2369. ret = ath5k_hw_setup_mrr_tx_desc(ah, NULL, 0, 0, 0, 0, 0, 0);
  2370. if (ret < 0)
  2371. goto err;
  2372. if (ret > 0)
  2373. __set_bit(ATH_STAT_MRRETRY, ah->status);
  2374. /*
  2375. * Collect the channel list. The 802.11 layer
  2376. * is responsible for filtering this list based
  2377. * on settings like the phy mode and regulatory
  2378. * domain restrictions.
  2379. */
  2380. ret = ath5k_setup_bands(hw);
  2381. if (ret) {
  2382. ATH5K_ERR(ah, "can't get channels\n");
  2383. goto err;
  2384. }
  2385. /*
  2386. * Allocate tx+rx descriptors and populate the lists.
  2387. */
  2388. ret = ath5k_desc_alloc(ah);
  2389. if (ret) {
  2390. ATH5K_ERR(ah, "can't allocate descriptors\n");
  2391. goto err;
  2392. }
  2393. /*
  2394. * Allocate hardware transmit queues: one queue for
  2395. * beacon frames and one data queue for each QoS
  2396. * priority. Note that hw functions handle resetting
  2397. * these queues at the needed time.
  2398. */
  2399. ret = ath5k_beaconq_setup(ah);
  2400. if (ret < 0) {
  2401. ATH5K_ERR(ah, "can't setup a beacon xmit queue\n");
  2402. goto err_desc;
  2403. }
  2404. ah->bhalq = ret;
  2405. ah->cabq = ath5k_txq_setup(ah, AR5K_TX_QUEUE_CAB, 0);
  2406. if (IS_ERR(ah->cabq)) {
  2407. ATH5K_ERR(ah, "can't setup cab queue\n");
  2408. ret = PTR_ERR(ah->cabq);
  2409. goto err_bhal;
  2410. }
  2411. /* 5211 and 5212 usually support 10 queues but we better rely on the
  2412. * capability information */
  2413. if (ah->ah_capabilities.cap_queues.q_tx_num >= 6) {
  2414. /* This order matches mac80211's queue priority, so we can
  2415. * directly use the mac80211 queue number without any mapping */
  2416. txq = ath5k_txq_setup(ah, AR5K_TX_QUEUE_DATA, AR5K_WME_AC_VO);
  2417. if (IS_ERR(txq)) {
  2418. ATH5K_ERR(ah, "can't setup xmit queue\n");
  2419. ret = PTR_ERR(txq);
  2420. goto err_queues;
  2421. }
  2422. txq = ath5k_txq_setup(ah, AR5K_TX_QUEUE_DATA, AR5K_WME_AC_VI);
  2423. if (IS_ERR(txq)) {
  2424. ATH5K_ERR(ah, "can't setup xmit queue\n");
  2425. ret = PTR_ERR(txq);
  2426. goto err_queues;
  2427. }
  2428. txq = ath5k_txq_setup(ah, AR5K_TX_QUEUE_DATA, AR5K_WME_AC_BE);
  2429. if (IS_ERR(txq)) {
  2430. ATH5K_ERR(ah, "can't setup xmit queue\n");
  2431. ret = PTR_ERR(txq);
  2432. goto err_queues;
  2433. }
  2434. txq = ath5k_txq_setup(ah, AR5K_TX_QUEUE_DATA, AR5K_WME_AC_BK);
  2435. if (IS_ERR(txq)) {
  2436. ATH5K_ERR(ah, "can't setup xmit queue\n");
  2437. ret = PTR_ERR(txq);
  2438. goto err_queues;
  2439. }
  2440. hw->queues = 4;
  2441. } else {
  2442. /* older hardware (5210) can only support one data queue */
  2443. txq = ath5k_txq_setup(ah, AR5K_TX_QUEUE_DATA, AR5K_WME_AC_BE);
  2444. if (IS_ERR(txq)) {
  2445. ATH5K_ERR(ah, "can't setup xmit queue\n");
  2446. ret = PTR_ERR(txq);
  2447. goto err_queues;
  2448. }
  2449. hw->queues = 1;
  2450. }
  2451. tasklet_init(&ah->rxtq, ath5k_tasklet_rx, (unsigned long)ah);
  2452. tasklet_init(&ah->txtq, ath5k_tasklet_tx, (unsigned long)ah);
  2453. tasklet_init(&ah->calib, ath5k_tasklet_calibrate, (unsigned long)ah);
  2454. tasklet_init(&ah->beacontq, ath5k_tasklet_beacon, (unsigned long)ah);
  2455. tasklet_init(&ah->ani_tasklet, ath5k_tasklet_ani, (unsigned long)ah);
  2456. INIT_WORK(&ah->reset_work, ath5k_reset_work);
  2457. INIT_DELAYED_WORK(&ah->tx_complete_work, ath5k_tx_complete_poll_work);
  2458. ret = ath5k_hw_common(ah)->bus_ops->eeprom_read_mac(ah, mac);
  2459. if (ret) {
  2460. ATH5K_ERR(ah, "unable to read address from EEPROM\n");
  2461. goto err_queues;
  2462. }
  2463. SET_IEEE80211_PERM_ADDR(hw, mac);
  2464. memcpy(&ah->lladdr, mac, ETH_ALEN);
  2465. /* All MAC address bits matter for ACKs */
  2466. ath5k_update_bssid_mask_and_opmode(ah, NULL);
  2467. regulatory->current_rd = ah->ah_capabilities.cap_eeprom.ee_regdomain;
  2468. ret = ath_regd_init(regulatory, hw->wiphy, ath5k_reg_notifier);
  2469. if (ret) {
  2470. ATH5K_ERR(ah, "can't initialize regulatory system\n");
  2471. goto err_queues;
  2472. }
  2473. ret = ieee80211_register_hw(hw);
  2474. if (ret) {
  2475. ATH5K_ERR(ah, "can't register ieee80211 hw\n");
  2476. goto err_queues;
  2477. }
  2478. if (!ath_is_world_regd(regulatory))
  2479. regulatory_hint(hw->wiphy, regulatory->alpha2);
  2480. ath5k_init_leds(ah);
  2481. ath5k_sysfs_register(ah);
  2482. return 0;
  2483. err_queues:
  2484. ath5k_txq_release(ah);
  2485. err_bhal:
  2486. ath5k_hw_release_tx_queue(ah, ah->bhalq);
  2487. err_desc:
  2488. ath5k_desc_free(ah);
  2489. err:
  2490. return ret;
  2491. }
  2492. void
  2493. ath5k_deinit_softc(struct ath5k_hw *ah)
  2494. {
  2495. struct ieee80211_hw *hw = ah->hw;
  2496. /*
  2497. * NB: the order of these is important:
  2498. * o call the 802.11 layer before detaching ath5k_hw to
  2499. * ensure callbacks into the driver to delete global
  2500. * key cache entries can be handled
  2501. * o reclaim the tx queue data structures after calling
  2502. * the 802.11 layer as we'll get called back to reclaim
  2503. * node state and potentially want to use them
  2504. * o to cleanup the tx queues the hal is called, so detach
  2505. * it last
  2506. * XXX: ??? detach ath5k_hw ???
  2507. * Other than that, it's straightforward...
  2508. */
  2509. ieee80211_unregister_hw(hw);
  2510. ath5k_desc_free(ah);
  2511. ath5k_txq_release(ah);
  2512. ath5k_hw_release_tx_queue(ah, ah->bhalq);
  2513. ath5k_unregister_leds(ah);
  2514. ath5k_sysfs_unregister(ah);
  2515. /*
  2516. * NB: can't reclaim these until after ieee80211_ifdetach
  2517. * returns because we'll get called back to reclaim node
  2518. * state and potentially want to use them.
  2519. */
  2520. ath5k_hw_deinit(ah);
  2521. free_irq(ah->irq, ah);
  2522. }
  2523. bool
  2524. ath5k_any_vif_assoc(struct ath5k_hw *ah)
  2525. {
  2526. struct ath5k_vif_iter_data iter_data;
  2527. iter_data.hw_macaddr = NULL;
  2528. iter_data.any_assoc = false;
  2529. iter_data.need_set_hw_addr = false;
  2530. iter_data.found_active = true;
  2531. ieee80211_iterate_active_interfaces_atomic(ah->hw, ath5k_vif_iter,
  2532. &iter_data);
  2533. return iter_data.any_assoc;
  2534. }
  2535. void
  2536. ath5k_set_beacon_filter(struct ieee80211_hw *hw, bool enable)
  2537. {
  2538. struct ath5k_hw *ah = hw->priv;
  2539. u32 rfilt;
  2540. rfilt = ath5k_hw_get_rx_filter(ah);
  2541. if (enable)
  2542. rfilt |= AR5K_RX_FILTER_BEACON;
  2543. else
  2544. rfilt &= ~AR5K_RX_FILTER_BEACON;
  2545. ath5k_hw_set_rx_filter(ah, rfilt);
  2546. ah->filter_flags = rfilt;
  2547. }