iwl-agn.c 117 KB

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  1. /******************************************************************************
  2. *
  3. * Copyright(c) 2003 - 2010 Intel Corporation. All rights reserved.
  4. *
  5. * Portions of this file are derived from the ipw3945 project, as well
  6. * as portions of the ieee80211 subsystem header files.
  7. *
  8. * This program is free software; you can redistribute it and/or modify it
  9. * under the terms of version 2 of the GNU General Public License as
  10. * published by the Free Software Foundation.
  11. *
  12. * This program is distributed in the hope that it will be useful, but WITHOUT
  13. * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  14. * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
  15. * more details.
  16. *
  17. * You should have received a copy of the GNU General Public License along with
  18. * this program; if not, write to the Free Software Foundation, Inc.,
  19. * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
  20. *
  21. * The full GNU General Public License is included in this distribution in the
  22. * file called LICENSE.
  23. *
  24. * Contact Information:
  25. * Intel Linux Wireless <ilw@linux.intel.com>
  26. * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
  27. *
  28. *****************************************************************************/
  29. #include <linux/kernel.h>
  30. #include <linux/module.h>
  31. #include <linux/init.h>
  32. #include <linux/pci.h>
  33. #include <linux/dma-mapping.h>
  34. #include <linux/delay.h>
  35. #include <linux/sched.h>
  36. #include <linux/skbuff.h>
  37. #include <linux/netdevice.h>
  38. #include <linux/wireless.h>
  39. #include <linux/firmware.h>
  40. #include <linux/etherdevice.h>
  41. #include <linux/if_arp.h>
  42. #include <net/mac80211.h>
  43. #include <asm/div64.h>
  44. #define DRV_NAME "iwlagn"
  45. #include "iwl-eeprom.h"
  46. #include "iwl-dev.h"
  47. #include "iwl-core.h"
  48. #include "iwl-io.h"
  49. #include "iwl-helpers.h"
  50. #include "iwl-sta.h"
  51. #include "iwl-calib.h"
  52. #include "iwl-agn.h"
  53. /******************************************************************************
  54. *
  55. * module boiler plate
  56. *
  57. ******************************************************************************/
  58. /*
  59. * module name, copyright, version, etc.
  60. */
  61. #define DRV_DESCRIPTION "Intel(R) Wireless WiFi Link AGN driver for Linux"
  62. #ifdef CONFIG_IWLWIFI_DEBUG
  63. #define VD "d"
  64. #else
  65. #define VD
  66. #endif
  67. #define DRV_VERSION IWLWIFI_VERSION VD
  68. MODULE_DESCRIPTION(DRV_DESCRIPTION);
  69. MODULE_VERSION(DRV_VERSION);
  70. MODULE_AUTHOR(DRV_COPYRIGHT " " DRV_AUTHOR);
  71. MODULE_LICENSE("GPL");
  72. MODULE_ALIAS("iwl4965");
  73. /**
  74. * iwl_commit_rxon - commit staging_rxon to hardware
  75. *
  76. * The RXON command in staging_rxon is committed to the hardware and
  77. * the active_rxon structure is updated with the new data. This
  78. * function correctly transitions out of the RXON_ASSOC_MSK state if
  79. * a HW tune is required based on the RXON structure changes.
  80. */
  81. int iwl_commit_rxon(struct iwl_priv *priv)
  82. {
  83. /* cast away the const for active_rxon in this function */
  84. struct iwl_rxon_cmd *active_rxon = (void *)&priv->active_rxon;
  85. int ret;
  86. bool new_assoc =
  87. !!(priv->staging_rxon.filter_flags & RXON_FILTER_ASSOC_MSK);
  88. if (!iwl_is_alive(priv))
  89. return -EBUSY;
  90. /* always get timestamp with Rx frame */
  91. priv->staging_rxon.flags |= RXON_FLG_TSF2HOST_MSK;
  92. ret = iwl_check_rxon_cmd(priv);
  93. if (ret) {
  94. IWL_ERR(priv, "Invalid RXON configuration. Not committing.\n");
  95. return -EINVAL;
  96. }
  97. /*
  98. * receive commit_rxon request
  99. * abort any previous channel switch if still in process
  100. */
  101. if (priv->switch_rxon.switch_in_progress &&
  102. (priv->switch_rxon.channel != priv->staging_rxon.channel)) {
  103. IWL_DEBUG_11H(priv, "abort channel switch on %d\n",
  104. le16_to_cpu(priv->switch_rxon.channel));
  105. priv->switch_rxon.switch_in_progress = false;
  106. }
  107. /* If we don't need to send a full RXON, we can use
  108. * iwl_rxon_assoc_cmd which is used to reconfigure filter
  109. * and other flags for the current radio configuration. */
  110. if (!iwl_full_rxon_required(priv)) {
  111. ret = iwl_send_rxon_assoc(priv);
  112. if (ret) {
  113. IWL_ERR(priv, "Error setting RXON_ASSOC (%d)\n", ret);
  114. return ret;
  115. }
  116. memcpy(active_rxon, &priv->staging_rxon, sizeof(*active_rxon));
  117. iwl_print_rx_config_cmd(priv);
  118. return 0;
  119. }
  120. /* If we are currently associated and the new config requires
  121. * an RXON_ASSOC and the new config wants the associated mask enabled,
  122. * we must clear the associated from the active configuration
  123. * before we apply the new config */
  124. if (iwl_is_associated(priv) && new_assoc) {
  125. IWL_DEBUG_INFO(priv, "Toggling associated bit on current RXON\n");
  126. active_rxon->filter_flags &= ~RXON_FILTER_ASSOC_MSK;
  127. ret = iwl_send_cmd_pdu(priv, REPLY_RXON,
  128. sizeof(struct iwl_rxon_cmd),
  129. &priv->active_rxon);
  130. /* If the mask clearing failed then we set
  131. * active_rxon back to what it was previously */
  132. if (ret) {
  133. active_rxon->filter_flags |= RXON_FILTER_ASSOC_MSK;
  134. IWL_ERR(priv, "Error clearing ASSOC_MSK (%d)\n", ret);
  135. return ret;
  136. }
  137. iwl_clear_ucode_stations(priv);
  138. iwl_restore_stations(priv);
  139. ret = iwl_restore_default_wep_keys(priv);
  140. if (ret) {
  141. IWL_ERR(priv, "Failed to restore WEP keys (%d)\n", ret);
  142. return ret;
  143. }
  144. }
  145. IWL_DEBUG_INFO(priv, "Sending RXON\n"
  146. "* with%s RXON_FILTER_ASSOC_MSK\n"
  147. "* channel = %d\n"
  148. "* bssid = %pM\n",
  149. (new_assoc ? "" : "out"),
  150. le16_to_cpu(priv->staging_rxon.channel),
  151. priv->staging_rxon.bssid_addr);
  152. iwl_set_rxon_hwcrypto(priv, !priv->cfg->mod_params->sw_crypto);
  153. /* Apply the new configuration
  154. * RXON unassoc clears the station table in uCode so restoration of
  155. * stations is needed after it (the RXON command) completes
  156. */
  157. if (!new_assoc) {
  158. ret = iwl_send_cmd_pdu(priv, REPLY_RXON,
  159. sizeof(struct iwl_rxon_cmd), &priv->staging_rxon);
  160. if (ret) {
  161. IWL_ERR(priv, "Error setting new RXON (%d)\n", ret);
  162. return ret;
  163. }
  164. IWL_DEBUG_INFO(priv, "Return from !new_assoc RXON.\n");
  165. memcpy(active_rxon, &priv->staging_rxon, sizeof(*active_rxon));
  166. iwl_clear_ucode_stations(priv);
  167. iwl_restore_stations(priv);
  168. ret = iwl_restore_default_wep_keys(priv);
  169. if (ret) {
  170. IWL_ERR(priv, "Failed to restore WEP keys (%d)\n", ret);
  171. return ret;
  172. }
  173. }
  174. priv->start_calib = 0;
  175. if (new_assoc) {
  176. /*
  177. * allow CTS-to-self if possible for new association.
  178. * this is relevant only for 5000 series and up,
  179. * but will not damage 4965
  180. */
  181. priv->staging_rxon.flags |= RXON_FLG_SELF_CTS_EN;
  182. /* Apply the new configuration
  183. * RXON assoc doesn't clear the station table in uCode,
  184. */
  185. ret = iwl_send_cmd_pdu(priv, REPLY_RXON,
  186. sizeof(struct iwl_rxon_cmd), &priv->staging_rxon);
  187. if (ret) {
  188. IWL_ERR(priv, "Error setting new RXON (%d)\n", ret);
  189. return ret;
  190. }
  191. memcpy(active_rxon, &priv->staging_rxon, sizeof(*active_rxon));
  192. }
  193. iwl_print_rx_config_cmd(priv);
  194. iwl_init_sensitivity(priv);
  195. /* If we issue a new RXON command which required a tune then we must
  196. * send a new TXPOWER command or we won't be able to Tx any frames */
  197. ret = iwl_set_tx_power(priv, priv->tx_power_user_lmt, true);
  198. if (ret) {
  199. IWL_ERR(priv, "Error sending TX power (%d)\n", ret);
  200. return ret;
  201. }
  202. return 0;
  203. }
  204. void iwl_update_chain_flags(struct iwl_priv *priv)
  205. {
  206. if (priv->cfg->ops->hcmd->set_rxon_chain)
  207. priv->cfg->ops->hcmd->set_rxon_chain(priv);
  208. iwlcore_commit_rxon(priv);
  209. }
  210. static void iwl_clear_free_frames(struct iwl_priv *priv)
  211. {
  212. struct list_head *element;
  213. IWL_DEBUG_INFO(priv, "%d frames on pre-allocated heap on clear.\n",
  214. priv->frames_count);
  215. while (!list_empty(&priv->free_frames)) {
  216. element = priv->free_frames.next;
  217. list_del(element);
  218. kfree(list_entry(element, struct iwl_frame, list));
  219. priv->frames_count--;
  220. }
  221. if (priv->frames_count) {
  222. IWL_WARN(priv, "%d frames still in use. Did we lose one?\n",
  223. priv->frames_count);
  224. priv->frames_count = 0;
  225. }
  226. }
  227. static struct iwl_frame *iwl_get_free_frame(struct iwl_priv *priv)
  228. {
  229. struct iwl_frame *frame;
  230. struct list_head *element;
  231. if (list_empty(&priv->free_frames)) {
  232. frame = kzalloc(sizeof(*frame), GFP_KERNEL);
  233. if (!frame) {
  234. IWL_ERR(priv, "Could not allocate frame!\n");
  235. return NULL;
  236. }
  237. priv->frames_count++;
  238. return frame;
  239. }
  240. element = priv->free_frames.next;
  241. list_del(element);
  242. return list_entry(element, struct iwl_frame, list);
  243. }
  244. static void iwl_free_frame(struct iwl_priv *priv, struct iwl_frame *frame)
  245. {
  246. memset(frame, 0, sizeof(*frame));
  247. list_add(&frame->list, &priv->free_frames);
  248. }
  249. static u32 iwl_fill_beacon_frame(struct iwl_priv *priv,
  250. struct ieee80211_hdr *hdr,
  251. int left)
  252. {
  253. if (!iwl_is_associated(priv) || !priv->ibss_beacon ||
  254. ((priv->iw_mode != NL80211_IFTYPE_ADHOC) &&
  255. (priv->iw_mode != NL80211_IFTYPE_AP)))
  256. return 0;
  257. if (priv->ibss_beacon->len > left)
  258. return 0;
  259. memcpy(hdr, priv->ibss_beacon->data, priv->ibss_beacon->len);
  260. return priv->ibss_beacon->len;
  261. }
  262. /* Parse the beacon frame to find the TIM element and set tim_idx & tim_size */
  263. static void iwl_set_beacon_tim(struct iwl_priv *priv,
  264. struct iwl_tx_beacon_cmd *tx_beacon_cmd,
  265. u8 *beacon, u32 frame_size)
  266. {
  267. u16 tim_idx;
  268. struct ieee80211_mgmt *mgmt = (struct ieee80211_mgmt *)beacon;
  269. /*
  270. * The index is relative to frame start but we start looking at the
  271. * variable-length part of the beacon.
  272. */
  273. tim_idx = mgmt->u.beacon.variable - beacon;
  274. /* Parse variable-length elements of beacon to find WLAN_EID_TIM */
  275. while ((tim_idx < (frame_size - 2)) &&
  276. (beacon[tim_idx] != WLAN_EID_TIM))
  277. tim_idx += beacon[tim_idx+1] + 2;
  278. /* If TIM field was found, set variables */
  279. if ((tim_idx < (frame_size - 1)) && (beacon[tim_idx] == WLAN_EID_TIM)) {
  280. tx_beacon_cmd->tim_idx = cpu_to_le16(tim_idx);
  281. tx_beacon_cmd->tim_size = beacon[tim_idx+1];
  282. } else
  283. IWL_WARN(priv, "Unable to find TIM Element in beacon\n");
  284. }
  285. static unsigned int iwl_hw_get_beacon_cmd(struct iwl_priv *priv,
  286. struct iwl_frame *frame)
  287. {
  288. struct iwl_tx_beacon_cmd *tx_beacon_cmd;
  289. u32 frame_size;
  290. u32 rate_flags;
  291. u32 rate;
  292. /*
  293. * We have to set up the TX command, the TX Beacon command, and the
  294. * beacon contents.
  295. */
  296. /* Initialize memory */
  297. tx_beacon_cmd = &frame->u.beacon;
  298. memset(tx_beacon_cmd, 0, sizeof(*tx_beacon_cmd));
  299. /* Set up TX beacon contents */
  300. frame_size = iwl_fill_beacon_frame(priv, tx_beacon_cmd->frame,
  301. sizeof(frame->u) - sizeof(*tx_beacon_cmd));
  302. if (WARN_ON_ONCE(frame_size > MAX_MPDU_SIZE))
  303. return 0;
  304. /* Set up TX command fields */
  305. tx_beacon_cmd->tx.len = cpu_to_le16((u16)frame_size);
  306. tx_beacon_cmd->tx.sta_id = priv->hw_params.bcast_sta_id;
  307. tx_beacon_cmd->tx.stop_time.life_time = TX_CMD_LIFE_TIME_INFINITE;
  308. tx_beacon_cmd->tx.tx_flags = TX_CMD_FLG_SEQ_CTL_MSK |
  309. TX_CMD_FLG_TSF_MSK | TX_CMD_FLG_STA_RATE_MSK;
  310. /* Set up TX beacon command fields */
  311. iwl_set_beacon_tim(priv, tx_beacon_cmd, (u8 *)tx_beacon_cmd->frame,
  312. frame_size);
  313. /* Set up packet rate and flags */
  314. rate = iwl_rate_get_lowest_plcp(priv);
  315. priv->mgmt_tx_ant = iwl_toggle_tx_ant(priv, priv->mgmt_tx_ant);
  316. rate_flags = iwl_ant_idx_to_flags(priv->mgmt_tx_ant);
  317. if ((rate >= IWL_FIRST_CCK_RATE) && (rate <= IWL_LAST_CCK_RATE))
  318. rate_flags |= RATE_MCS_CCK_MSK;
  319. tx_beacon_cmd->tx.rate_n_flags = iwl_hw_set_rate_n_flags(rate,
  320. rate_flags);
  321. return sizeof(*tx_beacon_cmd) + frame_size;
  322. }
  323. static int iwl_send_beacon_cmd(struct iwl_priv *priv)
  324. {
  325. struct iwl_frame *frame;
  326. unsigned int frame_size;
  327. int rc;
  328. frame = iwl_get_free_frame(priv);
  329. if (!frame) {
  330. IWL_ERR(priv, "Could not obtain free frame buffer for beacon "
  331. "command.\n");
  332. return -ENOMEM;
  333. }
  334. frame_size = iwl_hw_get_beacon_cmd(priv, frame);
  335. if (!frame_size) {
  336. IWL_ERR(priv, "Error configuring the beacon command\n");
  337. iwl_free_frame(priv, frame);
  338. return -EINVAL;
  339. }
  340. rc = iwl_send_cmd_pdu(priv, REPLY_TX_BEACON, frame_size,
  341. &frame->u.cmd[0]);
  342. iwl_free_frame(priv, frame);
  343. return rc;
  344. }
  345. static inline dma_addr_t iwl_tfd_tb_get_addr(struct iwl_tfd *tfd, u8 idx)
  346. {
  347. struct iwl_tfd_tb *tb = &tfd->tbs[idx];
  348. dma_addr_t addr = get_unaligned_le32(&tb->lo);
  349. if (sizeof(dma_addr_t) > sizeof(u32))
  350. addr |=
  351. ((dma_addr_t)(le16_to_cpu(tb->hi_n_len) & 0xF) << 16) << 16;
  352. return addr;
  353. }
  354. static inline u16 iwl_tfd_tb_get_len(struct iwl_tfd *tfd, u8 idx)
  355. {
  356. struct iwl_tfd_tb *tb = &tfd->tbs[idx];
  357. return le16_to_cpu(tb->hi_n_len) >> 4;
  358. }
  359. static inline void iwl_tfd_set_tb(struct iwl_tfd *tfd, u8 idx,
  360. dma_addr_t addr, u16 len)
  361. {
  362. struct iwl_tfd_tb *tb = &tfd->tbs[idx];
  363. u16 hi_n_len = len << 4;
  364. put_unaligned_le32(addr, &tb->lo);
  365. if (sizeof(dma_addr_t) > sizeof(u32))
  366. hi_n_len |= ((addr >> 16) >> 16) & 0xF;
  367. tb->hi_n_len = cpu_to_le16(hi_n_len);
  368. tfd->num_tbs = idx + 1;
  369. }
  370. static inline u8 iwl_tfd_get_num_tbs(struct iwl_tfd *tfd)
  371. {
  372. return tfd->num_tbs & 0x1f;
  373. }
  374. /**
  375. * iwl_hw_txq_free_tfd - Free all chunks referenced by TFD [txq->q.read_ptr]
  376. * @priv - driver private data
  377. * @txq - tx queue
  378. *
  379. * Does NOT advance any TFD circular buffer read/write indexes
  380. * Does NOT free the TFD itself (which is within circular buffer)
  381. */
  382. void iwl_hw_txq_free_tfd(struct iwl_priv *priv, struct iwl_tx_queue *txq)
  383. {
  384. struct iwl_tfd *tfd_tmp = (struct iwl_tfd *)txq->tfds;
  385. struct iwl_tfd *tfd;
  386. struct pci_dev *dev = priv->pci_dev;
  387. int index = txq->q.read_ptr;
  388. int i;
  389. int num_tbs;
  390. tfd = &tfd_tmp[index];
  391. /* Sanity check on number of chunks */
  392. num_tbs = iwl_tfd_get_num_tbs(tfd);
  393. if (num_tbs >= IWL_NUM_OF_TBS) {
  394. IWL_ERR(priv, "Too many chunks: %i\n", num_tbs);
  395. /* @todo issue fatal error, it is quite serious situation */
  396. return;
  397. }
  398. /* Unmap tx_cmd */
  399. if (num_tbs)
  400. pci_unmap_single(dev,
  401. pci_unmap_addr(&txq->meta[index], mapping),
  402. pci_unmap_len(&txq->meta[index], len),
  403. PCI_DMA_BIDIRECTIONAL);
  404. /* Unmap chunks, if any. */
  405. for (i = 1; i < num_tbs; i++) {
  406. pci_unmap_single(dev, iwl_tfd_tb_get_addr(tfd, i),
  407. iwl_tfd_tb_get_len(tfd, i), PCI_DMA_TODEVICE);
  408. if (txq->txb) {
  409. dev_kfree_skb(txq->txb[txq->q.read_ptr].skb[i - 1]);
  410. txq->txb[txq->q.read_ptr].skb[i - 1] = NULL;
  411. }
  412. }
  413. }
  414. int iwl_hw_txq_attach_buf_to_tfd(struct iwl_priv *priv,
  415. struct iwl_tx_queue *txq,
  416. dma_addr_t addr, u16 len,
  417. u8 reset, u8 pad)
  418. {
  419. struct iwl_queue *q;
  420. struct iwl_tfd *tfd, *tfd_tmp;
  421. u32 num_tbs;
  422. q = &txq->q;
  423. tfd_tmp = (struct iwl_tfd *)txq->tfds;
  424. tfd = &tfd_tmp[q->write_ptr];
  425. if (reset)
  426. memset(tfd, 0, sizeof(*tfd));
  427. num_tbs = iwl_tfd_get_num_tbs(tfd);
  428. /* Each TFD can point to a maximum 20 Tx buffers */
  429. if (num_tbs >= IWL_NUM_OF_TBS) {
  430. IWL_ERR(priv, "Error can not send more than %d chunks\n",
  431. IWL_NUM_OF_TBS);
  432. return -EINVAL;
  433. }
  434. BUG_ON(addr & ~DMA_BIT_MASK(36));
  435. if (unlikely(addr & ~IWL_TX_DMA_MASK))
  436. IWL_ERR(priv, "Unaligned address = %llx\n",
  437. (unsigned long long)addr);
  438. iwl_tfd_set_tb(tfd, num_tbs, addr, len);
  439. return 0;
  440. }
  441. /*
  442. * Tell nic where to find circular buffer of Tx Frame Descriptors for
  443. * given Tx queue, and enable the DMA channel used for that queue.
  444. *
  445. * 4965 supports up to 16 Tx queues in DRAM, mapped to up to 8 Tx DMA
  446. * channels supported in hardware.
  447. */
  448. int iwl_hw_tx_queue_init(struct iwl_priv *priv,
  449. struct iwl_tx_queue *txq)
  450. {
  451. int txq_id = txq->q.id;
  452. /* Circular buffer (TFD queue in DRAM) physical base address */
  453. iwl_write_direct32(priv, FH_MEM_CBBC_QUEUE(txq_id),
  454. txq->q.dma_addr >> 8);
  455. return 0;
  456. }
  457. /******************************************************************************
  458. *
  459. * Generic RX handler implementations
  460. *
  461. ******************************************************************************/
  462. static void iwl_rx_reply_alive(struct iwl_priv *priv,
  463. struct iwl_rx_mem_buffer *rxb)
  464. {
  465. struct iwl_rx_packet *pkt = rxb_addr(rxb);
  466. struct iwl_alive_resp *palive;
  467. struct delayed_work *pwork;
  468. palive = &pkt->u.alive_frame;
  469. IWL_DEBUG_INFO(priv, "Alive ucode status 0x%08X revision "
  470. "0x%01X 0x%01X\n",
  471. palive->is_valid, palive->ver_type,
  472. palive->ver_subtype);
  473. if (palive->ver_subtype == INITIALIZE_SUBTYPE) {
  474. IWL_DEBUG_INFO(priv, "Initialization Alive received.\n");
  475. memcpy(&priv->card_alive_init,
  476. &pkt->u.alive_frame,
  477. sizeof(struct iwl_init_alive_resp));
  478. pwork = &priv->init_alive_start;
  479. } else {
  480. IWL_DEBUG_INFO(priv, "Runtime Alive received.\n");
  481. memcpy(&priv->card_alive, &pkt->u.alive_frame,
  482. sizeof(struct iwl_alive_resp));
  483. pwork = &priv->alive_start;
  484. }
  485. /* We delay the ALIVE response by 5ms to
  486. * give the HW RF Kill time to activate... */
  487. if (palive->is_valid == UCODE_VALID_OK)
  488. queue_delayed_work(priv->workqueue, pwork,
  489. msecs_to_jiffies(5));
  490. else
  491. IWL_WARN(priv, "uCode did not respond OK.\n");
  492. }
  493. static void iwl_bg_beacon_update(struct work_struct *work)
  494. {
  495. struct iwl_priv *priv =
  496. container_of(work, struct iwl_priv, beacon_update);
  497. struct sk_buff *beacon;
  498. /* Pull updated AP beacon from mac80211. will fail if not in AP mode */
  499. beacon = ieee80211_beacon_get(priv->hw, priv->vif);
  500. if (!beacon) {
  501. IWL_ERR(priv, "update beacon failed\n");
  502. return;
  503. }
  504. mutex_lock(&priv->mutex);
  505. /* new beacon skb is allocated every time; dispose previous.*/
  506. if (priv->ibss_beacon)
  507. dev_kfree_skb(priv->ibss_beacon);
  508. priv->ibss_beacon = beacon;
  509. mutex_unlock(&priv->mutex);
  510. iwl_send_beacon_cmd(priv);
  511. }
  512. /**
  513. * iwl_bg_statistics_periodic - Timer callback to queue statistics
  514. *
  515. * This callback is provided in order to send a statistics request.
  516. *
  517. * This timer function is continually reset to execute within
  518. * REG_RECALIB_PERIOD seconds since the last STATISTICS_NOTIFICATION
  519. * was received. We need to ensure we receive the statistics in order
  520. * to update the temperature used for calibrating the TXPOWER.
  521. */
  522. static void iwl_bg_statistics_periodic(unsigned long data)
  523. {
  524. struct iwl_priv *priv = (struct iwl_priv *)data;
  525. if (test_bit(STATUS_EXIT_PENDING, &priv->status))
  526. return;
  527. /* dont send host command if rf-kill is on */
  528. if (!iwl_is_ready_rf(priv))
  529. return;
  530. iwl_send_statistics_request(priv, CMD_ASYNC, false);
  531. }
  532. static void iwl_print_cont_event_trace(struct iwl_priv *priv, u32 base,
  533. u32 start_idx, u32 num_events,
  534. u32 mode)
  535. {
  536. u32 i;
  537. u32 ptr; /* SRAM byte address of log data */
  538. u32 ev, time, data; /* event log data */
  539. unsigned long reg_flags;
  540. if (mode == 0)
  541. ptr = base + (4 * sizeof(u32)) + (start_idx * 2 * sizeof(u32));
  542. else
  543. ptr = base + (4 * sizeof(u32)) + (start_idx * 3 * sizeof(u32));
  544. /* Make sure device is powered up for SRAM reads */
  545. spin_lock_irqsave(&priv->reg_lock, reg_flags);
  546. if (iwl_grab_nic_access(priv)) {
  547. spin_unlock_irqrestore(&priv->reg_lock, reg_flags);
  548. return;
  549. }
  550. /* Set starting address; reads will auto-increment */
  551. _iwl_write_direct32(priv, HBUS_TARG_MEM_RADDR, ptr);
  552. rmb();
  553. /*
  554. * "time" is actually "data" for mode 0 (no timestamp).
  555. * place event id # at far right for easier visual parsing.
  556. */
  557. for (i = 0; i < num_events; i++) {
  558. ev = _iwl_read_direct32(priv, HBUS_TARG_MEM_RDAT);
  559. time = _iwl_read_direct32(priv, HBUS_TARG_MEM_RDAT);
  560. if (mode == 0) {
  561. trace_iwlwifi_dev_ucode_cont_event(priv,
  562. 0, time, ev);
  563. } else {
  564. data = _iwl_read_direct32(priv, HBUS_TARG_MEM_RDAT);
  565. trace_iwlwifi_dev_ucode_cont_event(priv,
  566. time, data, ev);
  567. }
  568. }
  569. /* Allow device to power down */
  570. iwl_release_nic_access(priv);
  571. spin_unlock_irqrestore(&priv->reg_lock, reg_flags);
  572. }
  573. static void iwl_continuous_event_trace(struct iwl_priv *priv)
  574. {
  575. u32 capacity; /* event log capacity in # entries */
  576. u32 base; /* SRAM byte address of event log header */
  577. u32 mode; /* 0 - no timestamp, 1 - timestamp recorded */
  578. u32 num_wraps; /* # times uCode wrapped to top of log */
  579. u32 next_entry; /* index of next entry to be written by uCode */
  580. if (priv->ucode_type == UCODE_INIT)
  581. base = le32_to_cpu(priv->card_alive_init.error_event_table_ptr);
  582. else
  583. base = le32_to_cpu(priv->card_alive.log_event_table_ptr);
  584. if (priv->cfg->ops->lib->is_valid_rtc_data_addr(base)) {
  585. capacity = iwl_read_targ_mem(priv, base);
  586. num_wraps = iwl_read_targ_mem(priv, base + (2 * sizeof(u32)));
  587. mode = iwl_read_targ_mem(priv, base + (1 * sizeof(u32)));
  588. next_entry = iwl_read_targ_mem(priv, base + (3 * sizeof(u32)));
  589. } else
  590. return;
  591. if (num_wraps == priv->event_log.num_wraps) {
  592. iwl_print_cont_event_trace(priv,
  593. base, priv->event_log.next_entry,
  594. next_entry - priv->event_log.next_entry,
  595. mode);
  596. priv->event_log.non_wraps_count++;
  597. } else {
  598. if ((num_wraps - priv->event_log.num_wraps) > 1)
  599. priv->event_log.wraps_more_count++;
  600. else
  601. priv->event_log.wraps_once_count++;
  602. trace_iwlwifi_dev_ucode_wrap_event(priv,
  603. num_wraps - priv->event_log.num_wraps,
  604. next_entry, priv->event_log.next_entry);
  605. if (next_entry < priv->event_log.next_entry) {
  606. iwl_print_cont_event_trace(priv, base,
  607. priv->event_log.next_entry,
  608. capacity - priv->event_log.next_entry,
  609. mode);
  610. iwl_print_cont_event_trace(priv, base, 0,
  611. next_entry, mode);
  612. } else {
  613. iwl_print_cont_event_trace(priv, base,
  614. next_entry, capacity - next_entry,
  615. mode);
  616. iwl_print_cont_event_trace(priv, base, 0,
  617. next_entry, mode);
  618. }
  619. }
  620. priv->event_log.num_wraps = num_wraps;
  621. priv->event_log.next_entry = next_entry;
  622. }
  623. /**
  624. * iwl_bg_ucode_trace - Timer callback to log ucode event
  625. *
  626. * The timer is continually set to execute every
  627. * UCODE_TRACE_PERIOD milliseconds after the last timer expired
  628. * this function is to perform continuous uCode event logging operation
  629. * if enabled
  630. */
  631. static void iwl_bg_ucode_trace(unsigned long data)
  632. {
  633. struct iwl_priv *priv = (struct iwl_priv *)data;
  634. if (test_bit(STATUS_EXIT_PENDING, &priv->status))
  635. return;
  636. if (priv->event_log.ucode_trace) {
  637. iwl_continuous_event_trace(priv);
  638. /* Reschedule the timer to occur in UCODE_TRACE_PERIOD */
  639. mod_timer(&priv->ucode_trace,
  640. jiffies + msecs_to_jiffies(UCODE_TRACE_PERIOD));
  641. }
  642. }
  643. static void iwl_rx_beacon_notif(struct iwl_priv *priv,
  644. struct iwl_rx_mem_buffer *rxb)
  645. {
  646. #ifdef CONFIG_IWLWIFI_DEBUG
  647. struct iwl_rx_packet *pkt = rxb_addr(rxb);
  648. struct iwl4965_beacon_notif *beacon =
  649. (struct iwl4965_beacon_notif *)pkt->u.raw;
  650. u8 rate = iwl_hw_get_rate(beacon->beacon_notify_hdr.rate_n_flags);
  651. IWL_DEBUG_RX(priv, "beacon status %x retries %d iss %d "
  652. "tsf %d %d rate %d\n",
  653. le32_to_cpu(beacon->beacon_notify_hdr.u.status) & TX_STATUS_MSK,
  654. beacon->beacon_notify_hdr.failure_frame,
  655. le32_to_cpu(beacon->ibss_mgr_status),
  656. le32_to_cpu(beacon->high_tsf),
  657. le32_to_cpu(beacon->low_tsf), rate);
  658. #endif
  659. if ((priv->iw_mode == NL80211_IFTYPE_AP) &&
  660. (!test_bit(STATUS_EXIT_PENDING, &priv->status)))
  661. queue_work(priv->workqueue, &priv->beacon_update);
  662. }
  663. /* Handle notification from uCode that card's power state is changing
  664. * due to software, hardware, or critical temperature RFKILL */
  665. static void iwl_rx_card_state_notif(struct iwl_priv *priv,
  666. struct iwl_rx_mem_buffer *rxb)
  667. {
  668. struct iwl_rx_packet *pkt = rxb_addr(rxb);
  669. u32 flags = le32_to_cpu(pkt->u.card_state_notif.flags);
  670. unsigned long status = priv->status;
  671. IWL_DEBUG_RF_KILL(priv, "Card state received: HW:%s SW:%s CT:%s\n",
  672. (flags & HW_CARD_DISABLED) ? "Kill" : "On",
  673. (flags & SW_CARD_DISABLED) ? "Kill" : "On",
  674. (flags & CT_CARD_DISABLED) ?
  675. "Reached" : "Not reached");
  676. if (flags & (SW_CARD_DISABLED | HW_CARD_DISABLED |
  677. CT_CARD_DISABLED)) {
  678. iwl_write32(priv, CSR_UCODE_DRV_GP1_SET,
  679. CSR_UCODE_DRV_GP1_BIT_CMD_BLOCKED);
  680. iwl_write_direct32(priv, HBUS_TARG_MBX_C,
  681. HBUS_TARG_MBX_C_REG_BIT_CMD_BLOCKED);
  682. if (!(flags & RXON_CARD_DISABLED)) {
  683. iwl_write32(priv, CSR_UCODE_DRV_GP1_CLR,
  684. CSR_UCODE_DRV_GP1_BIT_CMD_BLOCKED);
  685. iwl_write_direct32(priv, HBUS_TARG_MBX_C,
  686. HBUS_TARG_MBX_C_REG_BIT_CMD_BLOCKED);
  687. }
  688. if (flags & CT_CARD_DISABLED)
  689. iwl_tt_enter_ct_kill(priv);
  690. }
  691. if (!(flags & CT_CARD_DISABLED))
  692. iwl_tt_exit_ct_kill(priv);
  693. if (flags & HW_CARD_DISABLED)
  694. set_bit(STATUS_RF_KILL_HW, &priv->status);
  695. else
  696. clear_bit(STATUS_RF_KILL_HW, &priv->status);
  697. if (!(flags & RXON_CARD_DISABLED))
  698. iwl_scan_cancel(priv);
  699. if ((test_bit(STATUS_RF_KILL_HW, &status) !=
  700. test_bit(STATUS_RF_KILL_HW, &priv->status)))
  701. wiphy_rfkill_set_hw_state(priv->hw->wiphy,
  702. test_bit(STATUS_RF_KILL_HW, &priv->status));
  703. else
  704. wake_up_interruptible(&priv->wait_command_queue);
  705. }
  706. int iwl_set_pwr_src(struct iwl_priv *priv, enum iwl_pwr_src src)
  707. {
  708. if (src == IWL_PWR_SRC_VAUX) {
  709. if (pci_pme_capable(priv->pci_dev, PCI_D3cold))
  710. iwl_set_bits_mask_prph(priv, APMG_PS_CTRL_REG,
  711. APMG_PS_CTRL_VAL_PWR_SRC_VAUX,
  712. ~APMG_PS_CTRL_MSK_PWR_SRC);
  713. } else {
  714. iwl_set_bits_mask_prph(priv, APMG_PS_CTRL_REG,
  715. APMG_PS_CTRL_VAL_PWR_SRC_VMAIN,
  716. ~APMG_PS_CTRL_MSK_PWR_SRC);
  717. }
  718. return 0;
  719. }
  720. /**
  721. * iwl_setup_rx_handlers - Initialize Rx handler callbacks
  722. *
  723. * Setup the RX handlers for each of the reply types sent from the uCode
  724. * to the host.
  725. *
  726. * This function chains into the hardware specific files for them to setup
  727. * any hardware specific handlers as well.
  728. */
  729. static void iwl_setup_rx_handlers(struct iwl_priv *priv)
  730. {
  731. priv->rx_handlers[REPLY_ALIVE] = iwl_rx_reply_alive;
  732. priv->rx_handlers[REPLY_ERROR] = iwl_rx_reply_error;
  733. priv->rx_handlers[CHANNEL_SWITCH_NOTIFICATION] = iwl_rx_csa;
  734. priv->rx_handlers[SPECTRUM_MEASURE_NOTIFICATION] =
  735. iwl_rx_spectrum_measure_notif;
  736. priv->rx_handlers[PM_SLEEP_NOTIFICATION] = iwl_rx_pm_sleep_notif;
  737. priv->rx_handlers[PM_DEBUG_STATISTIC_NOTIFIC] =
  738. iwl_rx_pm_debug_statistics_notif;
  739. priv->rx_handlers[BEACON_NOTIFICATION] = iwl_rx_beacon_notif;
  740. /*
  741. * The same handler is used for both the REPLY to a discrete
  742. * statistics request from the host as well as for the periodic
  743. * statistics notifications (after received beacons) from the uCode.
  744. */
  745. priv->rx_handlers[REPLY_STATISTICS_CMD] = iwl_reply_statistics;
  746. priv->rx_handlers[STATISTICS_NOTIFICATION] = iwl_rx_statistics;
  747. iwl_setup_rx_scan_handlers(priv);
  748. /* status change handler */
  749. priv->rx_handlers[CARD_STATE_NOTIFICATION] = iwl_rx_card_state_notif;
  750. priv->rx_handlers[MISSED_BEACONS_NOTIFICATION] =
  751. iwl_rx_missed_beacon_notif;
  752. /* Rx handlers */
  753. priv->rx_handlers[REPLY_RX_PHY_CMD] = iwlagn_rx_reply_rx_phy;
  754. priv->rx_handlers[REPLY_RX_MPDU_CMD] = iwlagn_rx_reply_rx;
  755. /* block ack */
  756. priv->rx_handlers[REPLY_COMPRESSED_BA] = iwlagn_rx_reply_compressed_ba;
  757. /* Set up hardware specific Rx handlers */
  758. priv->cfg->ops->lib->rx_handler_setup(priv);
  759. }
  760. /**
  761. * iwl_rx_handle - Main entry function for receiving responses from uCode
  762. *
  763. * Uses the priv->rx_handlers callback function array to invoke
  764. * the appropriate handlers, including command responses,
  765. * frame-received notifications, and other notifications.
  766. */
  767. void iwl_rx_handle(struct iwl_priv *priv)
  768. {
  769. struct iwl_rx_mem_buffer *rxb;
  770. struct iwl_rx_packet *pkt;
  771. struct iwl_rx_queue *rxq = &priv->rxq;
  772. u32 r, i;
  773. int reclaim;
  774. unsigned long flags;
  775. u8 fill_rx = 0;
  776. u32 count = 8;
  777. int total_empty;
  778. /* uCode's read index (stored in shared DRAM) indicates the last Rx
  779. * buffer that the driver may process (last buffer filled by ucode). */
  780. r = le16_to_cpu(rxq->rb_stts->closed_rb_num) & 0x0FFF;
  781. i = rxq->read;
  782. /* Rx interrupt, but nothing sent from uCode */
  783. if (i == r)
  784. IWL_DEBUG_RX(priv, "r = %d, i = %d\n", r, i);
  785. /* calculate total frames need to be restock after handling RX */
  786. total_empty = r - rxq->write_actual;
  787. if (total_empty < 0)
  788. total_empty += RX_QUEUE_SIZE;
  789. if (total_empty > (RX_QUEUE_SIZE / 2))
  790. fill_rx = 1;
  791. while (i != r) {
  792. rxb = rxq->queue[i];
  793. /* If an RXB doesn't have a Rx queue slot associated with it,
  794. * then a bug has been introduced in the queue refilling
  795. * routines -- catch it here */
  796. BUG_ON(rxb == NULL);
  797. rxq->queue[i] = NULL;
  798. pci_unmap_page(priv->pci_dev, rxb->page_dma,
  799. PAGE_SIZE << priv->hw_params.rx_page_order,
  800. PCI_DMA_FROMDEVICE);
  801. pkt = rxb_addr(rxb);
  802. trace_iwlwifi_dev_rx(priv, pkt,
  803. le32_to_cpu(pkt->len_n_flags) & FH_RSCSR_FRAME_SIZE_MSK);
  804. /* Reclaim a command buffer only if this packet is a response
  805. * to a (driver-originated) command.
  806. * If the packet (e.g. Rx frame) originated from uCode,
  807. * there is no command buffer to reclaim.
  808. * Ucode should set SEQ_RX_FRAME bit if ucode-originated,
  809. * but apparently a few don't get set; catch them here. */
  810. reclaim = !(pkt->hdr.sequence & SEQ_RX_FRAME) &&
  811. (pkt->hdr.cmd != REPLY_RX_PHY_CMD) &&
  812. (pkt->hdr.cmd != REPLY_RX) &&
  813. (pkt->hdr.cmd != REPLY_RX_MPDU_CMD) &&
  814. (pkt->hdr.cmd != REPLY_COMPRESSED_BA) &&
  815. (pkt->hdr.cmd != STATISTICS_NOTIFICATION) &&
  816. (pkt->hdr.cmd != REPLY_TX);
  817. /* Based on type of command response or notification,
  818. * handle those that need handling via function in
  819. * rx_handlers table. See iwl_setup_rx_handlers() */
  820. if (priv->rx_handlers[pkt->hdr.cmd]) {
  821. IWL_DEBUG_RX(priv, "r = %d, i = %d, %s, 0x%02x\n", r,
  822. i, get_cmd_string(pkt->hdr.cmd), pkt->hdr.cmd);
  823. priv->isr_stats.rx_handlers[pkt->hdr.cmd]++;
  824. priv->rx_handlers[pkt->hdr.cmd] (priv, rxb);
  825. } else {
  826. /* No handling needed */
  827. IWL_DEBUG_RX(priv,
  828. "r %d i %d No handler needed for %s, 0x%02x\n",
  829. r, i, get_cmd_string(pkt->hdr.cmd),
  830. pkt->hdr.cmd);
  831. }
  832. /*
  833. * XXX: After here, we should always check rxb->page
  834. * against NULL before touching it or its virtual
  835. * memory (pkt). Because some rx_handler might have
  836. * already taken or freed the pages.
  837. */
  838. if (reclaim) {
  839. /* Invoke any callbacks, transfer the buffer to caller,
  840. * and fire off the (possibly) blocking iwl_send_cmd()
  841. * as we reclaim the driver command queue */
  842. if (rxb->page)
  843. iwl_tx_cmd_complete(priv, rxb);
  844. else
  845. IWL_WARN(priv, "Claim null rxb?\n");
  846. }
  847. /* Reuse the page if possible. For notification packets and
  848. * SKBs that fail to Rx correctly, add them back into the
  849. * rx_free list for reuse later. */
  850. spin_lock_irqsave(&rxq->lock, flags);
  851. if (rxb->page != NULL) {
  852. rxb->page_dma = pci_map_page(priv->pci_dev, rxb->page,
  853. 0, PAGE_SIZE << priv->hw_params.rx_page_order,
  854. PCI_DMA_FROMDEVICE);
  855. list_add_tail(&rxb->list, &rxq->rx_free);
  856. rxq->free_count++;
  857. } else
  858. list_add_tail(&rxb->list, &rxq->rx_used);
  859. spin_unlock_irqrestore(&rxq->lock, flags);
  860. i = (i + 1) & RX_QUEUE_MASK;
  861. /* If there are a lot of unused frames,
  862. * restock the Rx queue so ucode wont assert. */
  863. if (fill_rx) {
  864. count++;
  865. if (count >= 8) {
  866. rxq->read = i;
  867. iwlagn_rx_replenish_now(priv);
  868. count = 0;
  869. }
  870. }
  871. }
  872. /* Backtrack one entry */
  873. rxq->read = i;
  874. if (fill_rx)
  875. iwlagn_rx_replenish_now(priv);
  876. else
  877. iwlagn_rx_queue_restock(priv);
  878. }
  879. /* call this function to flush any scheduled tasklet */
  880. static inline void iwl_synchronize_irq(struct iwl_priv *priv)
  881. {
  882. /* wait to make sure we flush pending tasklet*/
  883. synchronize_irq(priv->pci_dev->irq);
  884. tasklet_kill(&priv->irq_tasklet);
  885. }
  886. static void iwl_irq_tasklet_legacy(struct iwl_priv *priv)
  887. {
  888. u32 inta, handled = 0;
  889. u32 inta_fh;
  890. unsigned long flags;
  891. u32 i;
  892. #ifdef CONFIG_IWLWIFI_DEBUG
  893. u32 inta_mask;
  894. #endif
  895. spin_lock_irqsave(&priv->lock, flags);
  896. /* Ack/clear/reset pending uCode interrupts.
  897. * Note: Some bits in CSR_INT are "OR" of bits in CSR_FH_INT_STATUS,
  898. * and will clear only when CSR_FH_INT_STATUS gets cleared. */
  899. inta = iwl_read32(priv, CSR_INT);
  900. iwl_write32(priv, CSR_INT, inta);
  901. /* Ack/clear/reset pending flow-handler (DMA) interrupts.
  902. * Any new interrupts that happen after this, either while we're
  903. * in this tasklet, or later, will show up in next ISR/tasklet. */
  904. inta_fh = iwl_read32(priv, CSR_FH_INT_STATUS);
  905. iwl_write32(priv, CSR_FH_INT_STATUS, inta_fh);
  906. #ifdef CONFIG_IWLWIFI_DEBUG
  907. if (iwl_get_debug_level(priv) & IWL_DL_ISR) {
  908. /* just for debug */
  909. inta_mask = iwl_read32(priv, CSR_INT_MASK);
  910. IWL_DEBUG_ISR(priv, "inta 0x%08x, enabled 0x%08x, fh 0x%08x\n",
  911. inta, inta_mask, inta_fh);
  912. }
  913. #endif
  914. spin_unlock_irqrestore(&priv->lock, flags);
  915. /* Since CSR_INT and CSR_FH_INT_STATUS reads and clears are not
  916. * atomic, make sure that inta covers all the interrupts that
  917. * we've discovered, even if FH interrupt came in just after
  918. * reading CSR_INT. */
  919. if (inta_fh & CSR49_FH_INT_RX_MASK)
  920. inta |= CSR_INT_BIT_FH_RX;
  921. if (inta_fh & CSR49_FH_INT_TX_MASK)
  922. inta |= CSR_INT_BIT_FH_TX;
  923. /* Now service all interrupt bits discovered above. */
  924. if (inta & CSR_INT_BIT_HW_ERR) {
  925. IWL_ERR(priv, "Hardware error detected. Restarting.\n");
  926. /* Tell the device to stop sending interrupts */
  927. iwl_disable_interrupts(priv);
  928. priv->isr_stats.hw++;
  929. iwl_irq_handle_error(priv);
  930. handled |= CSR_INT_BIT_HW_ERR;
  931. return;
  932. }
  933. #ifdef CONFIG_IWLWIFI_DEBUG
  934. if (iwl_get_debug_level(priv) & (IWL_DL_ISR)) {
  935. /* NIC fires this, but we don't use it, redundant with WAKEUP */
  936. if (inta & CSR_INT_BIT_SCD) {
  937. IWL_DEBUG_ISR(priv, "Scheduler finished to transmit "
  938. "the frame/frames.\n");
  939. priv->isr_stats.sch++;
  940. }
  941. /* Alive notification via Rx interrupt will do the real work */
  942. if (inta & CSR_INT_BIT_ALIVE) {
  943. IWL_DEBUG_ISR(priv, "Alive interrupt\n");
  944. priv->isr_stats.alive++;
  945. }
  946. }
  947. #endif
  948. /* Safely ignore these bits for debug checks below */
  949. inta &= ~(CSR_INT_BIT_SCD | CSR_INT_BIT_ALIVE);
  950. /* HW RF KILL switch toggled */
  951. if (inta & CSR_INT_BIT_RF_KILL) {
  952. int hw_rf_kill = 0;
  953. if (!(iwl_read32(priv, CSR_GP_CNTRL) &
  954. CSR_GP_CNTRL_REG_FLAG_HW_RF_KILL_SW))
  955. hw_rf_kill = 1;
  956. IWL_WARN(priv, "RF_KILL bit toggled to %s.\n",
  957. hw_rf_kill ? "disable radio" : "enable radio");
  958. priv->isr_stats.rfkill++;
  959. /* driver only loads ucode once setting the interface up.
  960. * the driver allows loading the ucode even if the radio
  961. * is killed. Hence update the killswitch state here. The
  962. * rfkill handler will care about restarting if needed.
  963. */
  964. if (!test_bit(STATUS_ALIVE, &priv->status)) {
  965. if (hw_rf_kill)
  966. set_bit(STATUS_RF_KILL_HW, &priv->status);
  967. else
  968. clear_bit(STATUS_RF_KILL_HW, &priv->status);
  969. wiphy_rfkill_set_hw_state(priv->hw->wiphy, hw_rf_kill);
  970. }
  971. handled |= CSR_INT_BIT_RF_KILL;
  972. }
  973. /* Chip got too hot and stopped itself */
  974. if (inta & CSR_INT_BIT_CT_KILL) {
  975. IWL_ERR(priv, "Microcode CT kill error detected.\n");
  976. priv->isr_stats.ctkill++;
  977. handled |= CSR_INT_BIT_CT_KILL;
  978. }
  979. /* Error detected by uCode */
  980. if (inta & CSR_INT_BIT_SW_ERR) {
  981. IWL_ERR(priv, "Microcode SW error detected. "
  982. " Restarting 0x%X.\n", inta);
  983. priv->isr_stats.sw++;
  984. priv->isr_stats.sw_err = inta;
  985. iwl_irq_handle_error(priv);
  986. handled |= CSR_INT_BIT_SW_ERR;
  987. }
  988. /*
  989. * uCode wakes up after power-down sleep.
  990. * Tell device about any new tx or host commands enqueued,
  991. * and about any Rx buffers made available while asleep.
  992. */
  993. if (inta & CSR_INT_BIT_WAKEUP) {
  994. IWL_DEBUG_ISR(priv, "Wakeup interrupt\n");
  995. iwl_rx_queue_update_write_ptr(priv, &priv->rxq);
  996. for (i = 0; i < priv->hw_params.max_txq_num; i++)
  997. iwl_txq_update_write_ptr(priv, &priv->txq[i]);
  998. priv->isr_stats.wakeup++;
  999. handled |= CSR_INT_BIT_WAKEUP;
  1000. }
  1001. /* All uCode command responses, including Tx command responses,
  1002. * Rx "responses" (frame-received notification), and other
  1003. * notifications from uCode come through here*/
  1004. if (inta & (CSR_INT_BIT_FH_RX | CSR_INT_BIT_SW_RX)) {
  1005. iwl_rx_handle(priv);
  1006. priv->isr_stats.rx++;
  1007. handled |= (CSR_INT_BIT_FH_RX | CSR_INT_BIT_SW_RX);
  1008. }
  1009. /* This "Tx" DMA channel is used only for loading uCode */
  1010. if (inta & CSR_INT_BIT_FH_TX) {
  1011. IWL_DEBUG_ISR(priv, "uCode load interrupt\n");
  1012. priv->isr_stats.tx++;
  1013. handled |= CSR_INT_BIT_FH_TX;
  1014. /* Wake up uCode load routine, now that load is complete */
  1015. priv->ucode_write_complete = 1;
  1016. wake_up_interruptible(&priv->wait_command_queue);
  1017. }
  1018. if (inta & ~handled) {
  1019. IWL_ERR(priv, "Unhandled INTA bits 0x%08x\n", inta & ~handled);
  1020. priv->isr_stats.unhandled++;
  1021. }
  1022. if (inta & ~(priv->inta_mask)) {
  1023. IWL_WARN(priv, "Disabled INTA bits 0x%08x were pending\n",
  1024. inta & ~priv->inta_mask);
  1025. IWL_WARN(priv, " with FH_INT = 0x%08x\n", inta_fh);
  1026. }
  1027. /* Re-enable all interrupts */
  1028. /* only Re-enable if diabled by irq */
  1029. if (test_bit(STATUS_INT_ENABLED, &priv->status))
  1030. iwl_enable_interrupts(priv);
  1031. #ifdef CONFIG_IWLWIFI_DEBUG
  1032. if (iwl_get_debug_level(priv) & (IWL_DL_ISR)) {
  1033. inta = iwl_read32(priv, CSR_INT);
  1034. inta_mask = iwl_read32(priv, CSR_INT_MASK);
  1035. inta_fh = iwl_read32(priv, CSR_FH_INT_STATUS);
  1036. IWL_DEBUG_ISR(priv, "End inta 0x%08x, enabled 0x%08x, fh 0x%08x, "
  1037. "flags 0x%08lx\n", inta, inta_mask, inta_fh, flags);
  1038. }
  1039. #endif
  1040. }
  1041. /* tasklet for iwlagn interrupt */
  1042. static void iwl_irq_tasklet(struct iwl_priv *priv)
  1043. {
  1044. u32 inta = 0;
  1045. u32 handled = 0;
  1046. unsigned long flags;
  1047. u32 i;
  1048. #ifdef CONFIG_IWLWIFI_DEBUG
  1049. u32 inta_mask;
  1050. #endif
  1051. spin_lock_irqsave(&priv->lock, flags);
  1052. /* Ack/clear/reset pending uCode interrupts.
  1053. * Note: Some bits in CSR_INT are "OR" of bits in CSR_FH_INT_STATUS,
  1054. */
  1055. /* There is a hardware bug in the interrupt mask function that some
  1056. * interrupts (i.e. CSR_INT_BIT_SCD) can still be generated even if
  1057. * they are disabled in the CSR_INT_MASK register. Furthermore the
  1058. * ICT interrupt handling mechanism has another bug that might cause
  1059. * these unmasked interrupts fail to be detected. We workaround the
  1060. * hardware bugs here by ACKing all the possible interrupts so that
  1061. * interrupt coalescing can still be achieved.
  1062. */
  1063. iwl_write32(priv, CSR_INT, priv->_agn.inta | ~priv->inta_mask);
  1064. inta = priv->_agn.inta;
  1065. #ifdef CONFIG_IWLWIFI_DEBUG
  1066. if (iwl_get_debug_level(priv) & IWL_DL_ISR) {
  1067. /* just for debug */
  1068. inta_mask = iwl_read32(priv, CSR_INT_MASK);
  1069. IWL_DEBUG_ISR(priv, "inta 0x%08x, enabled 0x%08x\n ",
  1070. inta, inta_mask);
  1071. }
  1072. #endif
  1073. spin_unlock_irqrestore(&priv->lock, flags);
  1074. /* saved interrupt in inta variable now we can reset priv->_agn.inta */
  1075. priv->_agn.inta = 0;
  1076. /* Now service all interrupt bits discovered above. */
  1077. if (inta & CSR_INT_BIT_HW_ERR) {
  1078. IWL_ERR(priv, "Hardware error detected. Restarting.\n");
  1079. /* Tell the device to stop sending interrupts */
  1080. iwl_disable_interrupts(priv);
  1081. priv->isr_stats.hw++;
  1082. iwl_irq_handle_error(priv);
  1083. handled |= CSR_INT_BIT_HW_ERR;
  1084. return;
  1085. }
  1086. #ifdef CONFIG_IWLWIFI_DEBUG
  1087. if (iwl_get_debug_level(priv) & (IWL_DL_ISR)) {
  1088. /* NIC fires this, but we don't use it, redundant with WAKEUP */
  1089. if (inta & CSR_INT_BIT_SCD) {
  1090. IWL_DEBUG_ISR(priv, "Scheduler finished to transmit "
  1091. "the frame/frames.\n");
  1092. priv->isr_stats.sch++;
  1093. }
  1094. /* Alive notification via Rx interrupt will do the real work */
  1095. if (inta & CSR_INT_BIT_ALIVE) {
  1096. IWL_DEBUG_ISR(priv, "Alive interrupt\n");
  1097. priv->isr_stats.alive++;
  1098. }
  1099. }
  1100. #endif
  1101. /* Safely ignore these bits for debug checks below */
  1102. inta &= ~(CSR_INT_BIT_SCD | CSR_INT_BIT_ALIVE);
  1103. /* HW RF KILL switch toggled */
  1104. if (inta & CSR_INT_BIT_RF_KILL) {
  1105. int hw_rf_kill = 0;
  1106. if (!(iwl_read32(priv, CSR_GP_CNTRL) &
  1107. CSR_GP_CNTRL_REG_FLAG_HW_RF_KILL_SW))
  1108. hw_rf_kill = 1;
  1109. IWL_WARN(priv, "RF_KILL bit toggled to %s.\n",
  1110. hw_rf_kill ? "disable radio" : "enable radio");
  1111. priv->isr_stats.rfkill++;
  1112. /* driver only loads ucode once setting the interface up.
  1113. * the driver allows loading the ucode even if the radio
  1114. * is killed. Hence update the killswitch state here. The
  1115. * rfkill handler will care about restarting if needed.
  1116. */
  1117. if (!test_bit(STATUS_ALIVE, &priv->status)) {
  1118. if (hw_rf_kill)
  1119. set_bit(STATUS_RF_KILL_HW, &priv->status);
  1120. else
  1121. clear_bit(STATUS_RF_KILL_HW, &priv->status);
  1122. wiphy_rfkill_set_hw_state(priv->hw->wiphy, hw_rf_kill);
  1123. }
  1124. handled |= CSR_INT_BIT_RF_KILL;
  1125. }
  1126. /* Chip got too hot and stopped itself */
  1127. if (inta & CSR_INT_BIT_CT_KILL) {
  1128. IWL_ERR(priv, "Microcode CT kill error detected.\n");
  1129. priv->isr_stats.ctkill++;
  1130. handled |= CSR_INT_BIT_CT_KILL;
  1131. }
  1132. /* Error detected by uCode */
  1133. if (inta & CSR_INT_BIT_SW_ERR) {
  1134. IWL_ERR(priv, "Microcode SW error detected. "
  1135. " Restarting 0x%X.\n", inta);
  1136. priv->isr_stats.sw++;
  1137. priv->isr_stats.sw_err = inta;
  1138. iwl_irq_handle_error(priv);
  1139. handled |= CSR_INT_BIT_SW_ERR;
  1140. }
  1141. /* uCode wakes up after power-down sleep */
  1142. if (inta & CSR_INT_BIT_WAKEUP) {
  1143. IWL_DEBUG_ISR(priv, "Wakeup interrupt\n");
  1144. iwl_rx_queue_update_write_ptr(priv, &priv->rxq);
  1145. for (i = 0; i < priv->hw_params.max_txq_num; i++)
  1146. iwl_txq_update_write_ptr(priv, &priv->txq[i]);
  1147. priv->isr_stats.wakeup++;
  1148. handled |= CSR_INT_BIT_WAKEUP;
  1149. }
  1150. /* All uCode command responses, including Tx command responses,
  1151. * Rx "responses" (frame-received notification), and other
  1152. * notifications from uCode come through here*/
  1153. if (inta & (CSR_INT_BIT_FH_RX | CSR_INT_BIT_SW_RX |
  1154. CSR_INT_BIT_RX_PERIODIC)) {
  1155. IWL_DEBUG_ISR(priv, "Rx interrupt\n");
  1156. if (inta & (CSR_INT_BIT_FH_RX | CSR_INT_BIT_SW_RX)) {
  1157. handled |= (CSR_INT_BIT_FH_RX | CSR_INT_BIT_SW_RX);
  1158. iwl_write32(priv, CSR_FH_INT_STATUS,
  1159. CSR49_FH_INT_RX_MASK);
  1160. }
  1161. if (inta & CSR_INT_BIT_RX_PERIODIC) {
  1162. handled |= CSR_INT_BIT_RX_PERIODIC;
  1163. iwl_write32(priv, CSR_INT, CSR_INT_BIT_RX_PERIODIC);
  1164. }
  1165. /* Sending RX interrupt require many steps to be done in the
  1166. * the device:
  1167. * 1- write interrupt to current index in ICT table.
  1168. * 2- dma RX frame.
  1169. * 3- update RX shared data to indicate last write index.
  1170. * 4- send interrupt.
  1171. * This could lead to RX race, driver could receive RX interrupt
  1172. * but the shared data changes does not reflect this;
  1173. * periodic interrupt will detect any dangling Rx activity.
  1174. */
  1175. /* Disable periodic interrupt; we use it as just a one-shot. */
  1176. iwl_write8(priv, CSR_INT_PERIODIC_REG,
  1177. CSR_INT_PERIODIC_DIS);
  1178. iwl_rx_handle(priv);
  1179. /*
  1180. * Enable periodic interrupt in 8 msec only if we received
  1181. * real RX interrupt (instead of just periodic int), to catch
  1182. * any dangling Rx interrupt. If it was just the periodic
  1183. * interrupt, there was no dangling Rx activity, and no need
  1184. * to extend the periodic interrupt; one-shot is enough.
  1185. */
  1186. if (inta & (CSR_INT_BIT_FH_RX | CSR_INT_BIT_SW_RX))
  1187. iwl_write8(priv, CSR_INT_PERIODIC_REG,
  1188. CSR_INT_PERIODIC_ENA);
  1189. priv->isr_stats.rx++;
  1190. }
  1191. /* This "Tx" DMA channel is used only for loading uCode */
  1192. if (inta & CSR_INT_BIT_FH_TX) {
  1193. iwl_write32(priv, CSR_FH_INT_STATUS, CSR49_FH_INT_TX_MASK);
  1194. IWL_DEBUG_ISR(priv, "uCode load interrupt\n");
  1195. priv->isr_stats.tx++;
  1196. handled |= CSR_INT_BIT_FH_TX;
  1197. /* Wake up uCode load routine, now that load is complete */
  1198. priv->ucode_write_complete = 1;
  1199. wake_up_interruptible(&priv->wait_command_queue);
  1200. }
  1201. if (inta & ~handled) {
  1202. IWL_ERR(priv, "Unhandled INTA bits 0x%08x\n", inta & ~handled);
  1203. priv->isr_stats.unhandled++;
  1204. }
  1205. if (inta & ~(priv->inta_mask)) {
  1206. IWL_WARN(priv, "Disabled INTA bits 0x%08x were pending\n",
  1207. inta & ~priv->inta_mask);
  1208. }
  1209. /* Re-enable all interrupts */
  1210. /* only Re-enable if diabled by irq */
  1211. if (test_bit(STATUS_INT_ENABLED, &priv->status))
  1212. iwl_enable_interrupts(priv);
  1213. }
  1214. /* the threshold ratio of actual_ack_cnt to expected_ack_cnt in percent */
  1215. #define ACK_CNT_RATIO (50)
  1216. #define BA_TIMEOUT_CNT (5)
  1217. #define BA_TIMEOUT_MAX (16)
  1218. /**
  1219. * iwl_good_ack_health - checks for ACK count ratios, BA timeout retries.
  1220. *
  1221. * When the ACK count ratio is 0 and aggregated BA timeout retries exceeding
  1222. * the BA_TIMEOUT_MAX, reload firmware and bring system back to normal
  1223. * operation state.
  1224. */
  1225. bool iwl_good_ack_health(struct iwl_priv *priv,
  1226. struct iwl_rx_packet *pkt)
  1227. {
  1228. bool rc = true;
  1229. int actual_ack_cnt_delta, expected_ack_cnt_delta;
  1230. int ba_timeout_delta;
  1231. actual_ack_cnt_delta =
  1232. le32_to_cpu(pkt->u.stats.tx.actual_ack_cnt) -
  1233. le32_to_cpu(priv->statistics.tx.actual_ack_cnt);
  1234. expected_ack_cnt_delta =
  1235. le32_to_cpu(pkt->u.stats.tx.expected_ack_cnt) -
  1236. le32_to_cpu(priv->statistics.tx.expected_ack_cnt);
  1237. ba_timeout_delta =
  1238. le32_to_cpu(pkt->u.stats.tx.agg.ba_timeout) -
  1239. le32_to_cpu(priv->statistics.tx.agg.ba_timeout);
  1240. if ((priv->_agn.agg_tids_count > 0) &&
  1241. (expected_ack_cnt_delta > 0) &&
  1242. (((actual_ack_cnt_delta * 100) / expected_ack_cnt_delta)
  1243. < ACK_CNT_RATIO) &&
  1244. (ba_timeout_delta > BA_TIMEOUT_CNT)) {
  1245. IWL_DEBUG_RADIO(priv, "actual_ack_cnt delta = %d,"
  1246. " expected_ack_cnt = %d\n",
  1247. actual_ack_cnt_delta, expected_ack_cnt_delta);
  1248. #ifdef CONFIG_IWLWIFI_DEBUG
  1249. IWL_DEBUG_RADIO(priv, "rx_detected_cnt delta = %d\n",
  1250. priv->delta_statistics.tx.rx_detected_cnt);
  1251. IWL_DEBUG_RADIO(priv,
  1252. "ack_or_ba_timeout_collision delta = %d\n",
  1253. priv->delta_statistics.tx.
  1254. ack_or_ba_timeout_collision);
  1255. #endif
  1256. IWL_DEBUG_RADIO(priv, "agg ba_timeout delta = %d\n",
  1257. ba_timeout_delta);
  1258. if (!actual_ack_cnt_delta &&
  1259. (ba_timeout_delta >= BA_TIMEOUT_MAX))
  1260. rc = false;
  1261. }
  1262. return rc;
  1263. }
  1264. /******************************************************************************
  1265. *
  1266. * uCode download functions
  1267. *
  1268. ******************************************************************************/
  1269. static void iwl_dealloc_ucode_pci(struct iwl_priv *priv)
  1270. {
  1271. iwl_free_fw_desc(priv->pci_dev, &priv->ucode_code);
  1272. iwl_free_fw_desc(priv->pci_dev, &priv->ucode_data);
  1273. iwl_free_fw_desc(priv->pci_dev, &priv->ucode_data_backup);
  1274. iwl_free_fw_desc(priv->pci_dev, &priv->ucode_init);
  1275. iwl_free_fw_desc(priv->pci_dev, &priv->ucode_init_data);
  1276. iwl_free_fw_desc(priv->pci_dev, &priv->ucode_boot);
  1277. }
  1278. static void iwl_nic_start(struct iwl_priv *priv)
  1279. {
  1280. /* Remove all resets to allow NIC to operate */
  1281. iwl_write32(priv, CSR_RESET, 0);
  1282. }
  1283. struct iwlagn_ucode_capabilities {
  1284. u32 max_probe_length;
  1285. };
  1286. static void iwl_ucode_callback(const struct firmware *ucode_raw, void *context);
  1287. static int iwl_mac_setup_register(struct iwl_priv *priv,
  1288. struct iwlagn_ucode_capabilities *capa);
  1289. static int __must_check iwl_request_firmware(struct iwl_priv *priv, bool first)
  1290. {
  1291. const char *name_pre = priv->cfg->fw_name_pre;
  1292. if (first)
  1293. priv->fw_index = priv->cfg->ucode_api_max;
  1294. else
  1295. priv->fw_index--;
  1296. if (priv->fw_index < priv->cfg->ucode_api_min) {
  1297. IWL_ERR(priv, "no suitable firmware found!\n");
  1298. return -ENOENT;
  1299. }
  1300. sprintf(priv->firmware_name, "%s%d%s",
  1301. name_pre, priv->fw_index, ".ucode");
  1302. IWL_DEBUG_INFO(priv, "attempting to load firmware '%s'\n",
  1303. priv->firmware_name);
  1304. return request_firmware_nowait(THIS_MODULE, 1, priv->firmware_name,
  1305. &priv->pci_dev->dev, GFP_KERNEL, priv,
  1306. iwl_ucode_callback);
  1307. }
  1308. struct iwlagn_firmware_pieces {
  1309. const void *inst, *data, *init, *init_data, *boot;
  1310. size_t inst_size, data_size, init_size, init_data_size, boot_size;
  1311. u32 build;
  1312. };
  1313. static int iwlagn_load_legacy_firmware(struct iwl_priv *priv,
  1314. const struct firmware *ucode_raw,
  1315. struct iwlagn_firmware_pieces *pieces)
  1316. {
  1317. struct iwl_ucode_header *ucode = (void *)ucode_raw->data;
  1318. u32 api_ver, hdr_size;
  1319. const u8 *src;
  1320. priv->ucode_ver = le32_to_cpu(ucode->ver);
  1321. api_ver = IWL_UCODE_API(priv->ucode_ver);
  1322. switch (api_ver) {
  1323. default:
  1324. /*
  1325. * 4965 doesn't revision the firmware file format
  1326. * along with the API version, it always uses v1
  1327. * file format.
  1328. */
  1329. if ((priv->hw_rev & CSR_HW_REV_TYPE_MSK) !=
  1330. CSR_HW_REV_TYPE_4965) {
  1331. hdr_size = 28;
  1332. if (ucode_raw->size < hdr_size) {
  1333. IWL_ERR(priv, "File size too small!\n");
  1334. return -EINVAL;
  1335. }
  1336. pieces->build = le32_to_cpu(ucode->u.v2.build);
  1337. pieces->inst_size = le32_to_cpu(ucode->u.v2.inst_size);
  1338. pieces->data_size = le32_to_cpu(ucode->u.v2.data_size);
  1339. pieces->init_size = le32_to_cpu(ucode->u.v2.init_size);
  1340. pieces->init_data_size = le32_to_cpu(ucode->u.v2.init_data_size);
  1341. pieces->boot_size = le32_to_cpu(ucode->u.v2.boot_size);
  1342. src = ucode->u.v2.data;
  1343. break;
  1344. }
  1345. /* fall through for 4965 */
  1346. case 0:
  1347. case 1:
  1348. case 2:
  1349. hdr_size = 24;
  1350. if (ucode_raw->size < hdr_size) {
  1351. IWL_ERR(priv, "File size too small!\n");
  1352. return -EINVAL;
  1353. }
  1354. pieces->build = 0;
  1355. pieces->inst_size = le32_to_cpu(ucode->u.v1.inst_size);
  1356. pieces->data_size = le32_to_cpu(ucode->u.v1.data_size);
  1357. pieces->init_size = le32_to_cpu(ucode->u.v1.init_size);
  1358. pieces->init_data_size = le32_to_cpu(ucode->u.v1.init_data_size);
  1359. pieces->boot_size = le32_to_cpu(ucode->u.v1.boot_size);
  1360. src = ucode->u.v1.data;
  1361. break;
  1362. }
  1363. /* Verify size of file vs. image size info in file's header */
  1364. if (ucode_raw->size != hdr_size + pieces->inst_size +
  1365. pieces->data_size + pieces->init_size +
  1366. pieces->init_data_size + pieces->boot_size) {
  1367. IWL_ERR(priv,
  1368. "uCode file size %d does not match expected size\n",
  1369. (int)ucode_raw->size);
  1370. return -EINVAL;
  1371. }
  1372. pieces->inst = src;
  1373. src += pieces->inst_size;
  1374. pieces->data = src;
  1375. src += pieces->data_size;
  1376. pieces->init = src;
  1377. src += pieces->init_size;
  1378. pieces->init_data = src;
  1379. src += pieces->init_data_size;
  1380. pieces->boot = src;
  1381. src += pieces->boot_size;
  1382. return 0;
  1383. }
  1384. static int iwlagn_wanted_ucode_alternative = 1;
  1385. static int iwlagn_load_firmware(struct iwl_priv *priv,
  1386. const struct firmware *ucode_raw,
  1387. struct iwlagn_firmware_pieces *pieces,
  1388. struct iwlagn_ucode_capabilities *capa)
  1389. {
  1390. struct iwl_tlv_ucode_header *ucode = (void *)ucode_raw->data;
  1391. struct iwl_ucode_tlv *tlv;
  1392. size_t len = ucode_raw->size;
  1393. const u8 *data;
  1394. int wanted_alternative = iwlagn_wanted_ucode_alternative, tmp;
  1395. u64 alternatives;
  1396. if (len < sizeof(*ucode))
  1397. return -EINVAL;
  1398. if (ucode->magic != cpu_to_le32(IWL_TLV_UCODE_MAGIC))
  1399. return -EINVAL;
  1400. /*
  1401. * Check which alternatives are present, and "downgrade"
  1402. * when the chosen alternative is not present, warning
  1403. * the user when that happens. Some files may not have
  1404. * any alternatives, so don't warn in that case.
  1405. */
  1406. alternatives = le64_to_cpu(ucode->alternatives);
  1407. tmp = wanted_alternative;
  1408. if (wanted_alternative > 63)
  1409. wanted_alternative = 63;
  1410. while (wanted_alternative && !(alternatives & BIT(wanted_alternative)))
  1411. wanted_alternative--;
  1412. if (wanted_alternative && wanted_alternative != tmp)
  1413. IWL_WARN(priv,
  1414. "uCode alternative %d not available, choosing %d\n",
  1415. tmp, wanted_alternative);
  1416. priv->ucode_ver = le32_to_cpu(ucode->ver);
  1417. pieces->build = le32_to_cpu(ucode->build);
  1418. data = ucode->data;
  1419. len -= sizeof(*ucode);
  1420. while (len >= sizeof(*tlv)) {
  1421. u32 tlv_len;
  1422. enum iwl_ucode_tlv_type tlv_type;
  1423. u16 tlv_alt;
  1424. const u8 *tlv_data;
  1425. len -= sizeof(*tlv);
  1426. tlv = (void *)data;
  1427. tlv_len = le32_to_cpu(tlv->length);
  1428. tlv_type = le16_to_cpu(tlv->type);
  1429. tlv_alt = le16_to_cpu(tlv->alternative);
  1430. tlv_data = tlv->data;
  1431. if (len < tlv_len)
  1432. return -EINVAL;
  1433. len -= ALIGN(tlv_len, 4);
  1434. data += sizeof(*tlv) + ALIGN(tlv_len, 4);
  1435. /*
  1436. * Alternative 0 is always valid.
  1437. *
  1438. * Skip alternative TLVs that are not selected.
  1439. */
  1440. if (tlv_alt != 0 && tlv_alt != wanted_alternative)
  1441. continue;
  1442. switch (tlv_type) {
  1443. case IWL_UCODE_TLV_INST:
  1444. pieces->inst = tlv_data;
  1445. pieces->inst_size = tlv_len;
  1446. break;
  1447. case IWL_UCODE_TLV_DATA:
  1448. pieces->data = tlv_data;
  1449. pieces->data_size = tlv_len;
  1450. break;
  1451. case IWL_UCODE_TLV_INIT:
  1452. pieces->init = tlv_data;
  1453. pieces->init_size = tlv_len;
  1454. break;
  1455. case IWL_UCODE_TLV_INIT_DATA:
  1456. pieces->init_data = tlv_data;
  1457. pieces->init_data_size = tlv_len;
  1458. break;
  1459. case IWL_UCODE_TLV_BOOT:
  1460. pieces->boot = tlv_data;
  1461. pieces->boot_size = tlv_len;
  1462. break;
  1463. case IWL_UCODE_TLV_PROBE_MAX_LEN:
  1464. if (tlv_len != 4)
  1465. return -EINVAL;
  1466. capa->max_probe_length =
  1467. le32_to_cpup((__le32 *)tlv_data);
  1468. break;
  1469. default:
  1470. break;
  1471. }
  1472. }
  1473. if (len)
  1474. return -EINVAL;
  1475. return 0;
  1476. }
  1477. /**
  1478. * iwl_ucode_callback - callback when firmware was loaded
  1479. *
  1480. * If loaded successfully, copies the firmware into buffers
  1481. * for the card to fetch (via DMA).
  1482. */
  1483. static void iwl_ucode_callback(const struct firmware *ucode_raw, void *context)
  1484. {
  1485. struct iwl_priv *priv = context;
  1486. struct iwl_ucode_header *ucode;
  1487. int err;
  1488. struct iwlagn_firmware_pieces pieces;
  1489. const unsigned int api_max = priv->cfg->ucode_api_max;
  1490. const unsigned int api_min = priv->cfg->ucode_api_min;
  1491. u32 api_ver;
  1492. char buildstr[25];
  1493. u32 build;
  1494. struct iwlagn_ucode_capabilities ucode_capa = {
  1495. .max_probe_length = 200,
  1496. };
  1497. memset(&pieces, 0, sizeof(pieces));
  1498. if (!ucode_raw) {
  1499. IWL_ERR(priv, "request for firmware file '%s' failed.\n",
  1500. priv->firmware_name);
  1501. goto try_again;
  1502. }
  1503. IWL_DEBUG_INFO(priv, "Loaded firmware file '%s' (%zd bytes).\n",
  1504. priv->firmware_name, ucode_raw->size);
  1505. /* Make sure that we got at least the API version number */
  1506. if (ucode_raw->size < 4) {
  1507. IWL_ERR(priv, "File size way too small!\n");
  1508. goto try_again;
  1509. }
  1510. /* Data from ucode file: header followed by uCode images */
  1511. ucode = (struct iwl_ucode_header *)ucode_raw->data;
  1512. if (ucode->ver)
  1513. err = iwlagn_load_legacy_firmware(priv, ucode_raw, &pieces);
  1514. else
  1515. err = iwlagn_load_firmware(priv, ucode_raw, &pieces,
  1516. &ucode_capa);
  1517. if (err)
  1518. goto try_again;
  1519. api_ver = IWL_UCODE_API(priv->ucode_ver);
  1520. build = pieces.build;
  1521. /*
  1522. * api_ver should match the api version forming part of the
  1523. * firmware filename ... but we don't check for that and only rely
  1524. * on the API version read from firmware header from here on forward
  1525. */
  1526. if (api_ver < api_min || api_ver > api_max) {
  1527. IWL_ERR(priv, "Driver unable to support your firmware API. "
  1528. "Driver supports v%u, firmware is v%u.\n",
  1529. api_max, api_ver);
  1530. goto try_again;
  1531. }
  1532. if (api_ver != api_max)
  1533. IWL_ERR(priv, "Firmware has old API version. Expected v%u, "
  1534. "got v%u. New firmware can be obtained "
  1535. "from http://www.intellinuxwireless.org.\n",
  1536. api_max, api_ver);
  1537. if (build)
  1538. sprintf(buildstr, " build %u", build);
  1539. else
  1540. buildstr[0] = '\0';
  1541. IWL_INFO(priv, "loaded firmware version %u.%u.%u.%u%s\n",
  1542. IWL_UCODE_MAJOR(priv->ucode_ver),
  1543. IWL_UCODE_MINOR(priv->ucode_ver),
  1544. IWL_UCODE_API(priv->ucode_ver),
  1545. IWL_UCODE_SERIAL(priv->ucode_ver),
  1546. buildstr);
  1547. snprintf(priv->hw->wiphy->fw_version,
  1548. sizeof(priv->hw->wiphy->fw_version),
  1549. "%u.%u.%u.%u%s",
  1550. IWL_UCODE_MAJOR(priv->ucode_ver),
  1551. IWL_UCODE_MINOR(priv->ucode_ver),
  1552. IWL_UCODE_API(priv->ucode_ver),
  1553. IWL_UCODE_SERIAL(priv->ucode_ver),
  1554. buildstr);
  1555. /*
  1556. * For any of the failures below (before allocating pci memory)
  1557. * we will try to load a version with a smaller API -- maybe the
  1558. * user just got a corrupted version of the latest API.
  1559. */
  1560. IWL_DEBUG_INFO(priv, "f/w package hdr ucode version raw = 0x%x\n",
  1561. priv->ucode_ver);
  1562. IWL_DEBUG_INFO(priv, "f/w package hdr runtime inst size = %Zd\n",
  1563. pieces.inst_size);
  1564. IWL_DEBUG_INFO(priv, "f/w package hdr runtime data size = %Zd\n",
  1565. pieces.data_size);
  1566. IWL_DEBUG_INFO(priv, "f/w package hdr init inst size = %Zd\n",
  1567. pieces.init_size);
  1568. IWL_DEBUG_INFO(priv, "f/w package hdr init data size = %Zd\n",
  1569. pieces.init_data_size);
  1570. IWL_DEBUG_INFO(priv, "f/w package hdr boot inst size = %Zd\n",
  1571. pieces.boot_size);
  1572. /* Verify that uCode images will fit in card's SRAM */
  1573. if (pieces.inst_size > priv->hw_params.max_inst_size) {
  1574. IWL_ERR(priv, "uCode instr len %Zd too large to fit in\n",
  1575. pieces.inst_size);
  1576. goto try_again;
  1577. }
  1578. if (pieces.data_size > priv->hw_params.max_data_size) {
  1579. IWL_ERR(priv, "uCode data len %Zd too large to fit in\n",
  1580. pieces.data_size);
  1581. goto try_again;
  1582. }
  1583. if (pieces.init_size > priv->hw_params.max_inst_size) {
  1584. IWL_ERR(priv, "uCode init instr len %Zd too large to fit in\n",
  1585. pieces.init_size);
  1586. goto try_again;
  1587. }
  1588. if (pieces.init_data_size > priv->hw_params.max_data_size) {
  1589. IWL_ERR(priv, "uCode init data len %Zd too large to fit in\n",
  1590. pieces.init_data_size);
  1591. goto try_again;
  1592. }
  1593. if (pieces.boot_size > priv->hw_params.max_bsm_size) {
  1594. IWL_ERR(priv, "uCode boot instr len %Zd too large to fit in\n",
  1595. pieces.boot_size);
  1596. goto try_again;
  1597. }
  1598. /* Allocate ucode buffers for card's bus-master loading ... */
  1599. /* Runtime instructions and 2 copies of data:
  1600. * 1) unmodified from disk
  1601. * 2) backup cache for save/restore during power-downs */
  1602. priv->ucode_code.len = pieces.inst_size;
  1603. iwl_alloc_fw_desc(priv->pci_dev, &priv->ucode_code);
  1604. priv->ucode_data.len = pieces.data_size;
  1605. iwl_alloc_fw_desc(priv->pci_dev, &priv->ucode_data);
  1606. priv->ucode_data_backup.len = pieces.data_size;
  1607. iwl_alloc_fw_desc(priv->pci_dev, &priv->ucode_data_backup);
  1608. if (!priv->ucode_code.v_addr || !priv->ucode_data.v_addr ||
  1609. !priv->ucode_data_backup.v_addr)
  1610. goto err_pci_alloc;
  1611. /* Initialization instructions and data */
  1612. if (pieces.init_size && pieces.init_data_size) {
  1613. priv->ucode_init.len = pieces.init_size;
  1614. iwl_alloc_fw_desc(priv->pci_dev, &priv->ucode_init);
  1615. priv->ucode_init_data.len = pieces.init_data_size;
  1616. iwl_alloc_fw_desc(priv->pci_dev, &priv->ucode_init_data);
  1617. if (!priv->ucode_init.v_addr || !priv->ucode_init_data.v_addr)
  1618. goto err_pci_alloc;
  1619. }
  1620. /* Bootstrap (instructions only, no data) */
  1621. if (pieces.boot_size) {
  1622. priv->ucode_boot.len = pieces.boot_size;
  1623. iwl_alloc_fw_desc(priv->pci_dev, &priv->ucode_boot);
  1624. if (!priv->ucode_boot.v_addr)
  1625. goto err_pci_alloc;
  1626. }
  1627. /* Copy images into buffers for card's bus-master reads ... */
  1628. /* Runtime instructions (first block of data in file) */
  1629. IWL_DEBUG_INFO(priv, "Copying (but not loading) uCode instr len %Zd\n",
  1630. pieces.inst_size);
  1631. memcpy(priv->ucode_code.v_addr, pieces.inst, pieces.inst_size);
  1632. IWL_DEBUG_INFO(priv, "uCode instr buf vaddr = 0x%p, paddr = 0x%08x\n",
  1633. priv->ucode_code.v_addr, (u32)priv->ucode_code.p_addr);
  1634. /*
  1635. * Runtime data
  1636. * NOTE: Copy into backup buffer will be done in iwl_up()
  1637. */
  1638. IWL_DEBUG_INFO(priv, "Copying (but not loading) uCode data len %Zd\n",
  1639. pieces.data_size);
  1640. memcpy(priv->ucode_data.v_addr, pieces.data, pieces.data_size);
  1641. memcpy(priv->ucode_data_backup.v_addr, pieces.data, pieces.data_size);
  1642. /* Initialization instructions */
  1643. if (pieces.init_size) {
  1644. IWL_DEBUG_INFO(priv, "Copying (but not loading) init instr len %Zd\n",
  1645. pieces.init_size);
  1646. memcpy(priv->ucode_init.v_addr, pieces.init, pieces.init_size);
  1647. }
  1648. /* Initialization data */
  1649. if (pieces.init_data_size) {
  1650. IWL_DEBUG_INFO(priv, "Copying (but not loading) init data len %Zd\n",
  1651. pieces.init_data_size);
  1652. memcpy(priv->ucode_init_data.v_addr, pieces.init_data,
  1653. pieces.init_data_size);
  1654. }
  1655. /* Bootstrap instructions */
  1656. IWL_DEBUG_INFO(priv, "Copying (but not loading) boot instr len %Zd\n",
  1657. pieces.boot_size);
  1658. memcpy(priv->ucode_boot.v_addr, pieces.boot, pieces.boot_size);
  1659. /**************************************************
  1660. * This is still part of probe() in a sense...
  1661. *
  1662. * 9. Setup and register with mac80211 and debugfs
  1663. **************************************************/
  1664. err = iwl_mac_setup_register(priv, &ucode_capa);
  1665. if (err)
  1666. goto out_unbind;
  1667. err = iwl_dbgfs_register(priv, DRV_NAME);
  1668. if (err)
  1669. IWL_ERR(priv, "failed to create debugfs files. Ignoring error: %d\n", err);
  1670. /* We have our copies now, allow OS release its copies */
  1671. release_firmware(ucode_raw);
  1672. complete(&priv->_agn.firmware_loading_complete);
  1673. return;
  1674. try_again:
  1675. /* try next, if any */
  1676. if (iwl_request_firmware(priv, false))
  1677. goto out_unbind;
  1678. release_firmware(ucode_raw);
  1679. return;
  1680. err_pci_alloc:
  1681. IWL_ERR(priv, "failed to allocate pci memory\n");
  1682. iwl_dealloc_ucode_pci(priv);
  1683. out_unbind:
  1684. complete(&priv->_agn.firmware_loading_complete);
  1685. device_release_driver(&priv->pci_dev->dev);
  1686. release_firmware(ucode_raw);
  1687. }
  1688. static const char *desc_lookup_text[] = {
  1689. "OK",
  1690. "FAIL",
  1691. "BAD_PARAM",
  1692. "BAD_CHECKSUM",
  1693. "NMI_INTERRUPT_WDG",
  1694. "SYSASSERT",
  1695. "FATAL_ERROR",
  1696. "BAD_COMMAND",
  1697. "HW_ERROR_TUNE_LOCK",
  1698. "HW_ERROR_TEMPERATURE",
  1699. "ILLEGAL_CHAN_FREQ",
  1700. "VCC_NOT_STABLE",
  1701. "FH_ERROR",
  1702. "NMI_INTERRUPT_HOST",
  1703. "NMI_INTERRUPT_ACTION_PT",
  1704. "NMI_INTERRUPT_UNKNOWN",
  1705. "UCODE_VERSION_MISMATCH",
  1706. "HW_ERROR_ABS_LOCK",
  1707. "HW_ERROR_CAL_LOCK_FAIL",
  1708. "NMI_INTERRUPT_INST_ACTION_PT",
  1709. "NMI_INTERRUPT_DATA_ACTION_PT",
  1710. "NMI_TRM_HW_ER",
  1711. "NMI_INTERRUPT_TRM",
  1712. "NMI_INTERRUPT_BREAK_POINT"
  1713. "DEBUG_0",
  1714. "DEBUG_1",
  1715. "DEBUG_2",
  1716. "DEBUG_3",
  1717. "ADVANCED SYSASSERT"
  1718. };
  1719. static const char *desc_lookup(int i)
  1720. {
  1721. int max = ARRAY_SIZE(desc_lookup_text) - 1;
  1722. if (i < 0 || i > max)
  1723. i = max;
  1724. return desc_lookup_text[i];
  1725. }
  1726. #define ERROR_START_OFFSET (1 * sizeof(u32))
  1727. #define ERROR_ELEM_SIZE (7 * sizeof(u32))
  1728. void iwl_dump_nic_error_log(struct iwl_priv *priv)
  1729. {
  1730. u32 data2, line;
  1731. u32 desc, time, count, base, data1;
  1732. u32 blink1, blink2, ilink1, ilink2;
  1733. u32 pc, hcmd;
  1734. if (priv->ucode_type == UCODE_INIT)
  1735. base = le32_to_cpu(priv->card_alive_init.error_event_table_ptr);
  1736. else
  1737. base = le32_to_cpu(priv->card_alive.error_event_table_ptr);
  1738. if (!priv->cfg->ops->lib->is_valid_rtc_data_addr(base)) {
  1739. IWL_ERR(priv,
  1740. "Not valid error log pointer 0x%08X for %s uCode\n",
  1741. base, (priv->ucode_type == UCODE_INIT) ? "Init" : "RT");
  1742. return;
  1743. }
  1744. count = iwl_read_targ_mem(priv, base);
  1745. if (ERROR_START_OFFSET <= count * ERROR_ELEM_SIZE) {
  1746. IWL_ERR(priv, "Start IWL Error Log Dump:\n");
  1747. IWL_ERR(priv, "Status: 0x%08lX, count: %d\n",
  1748. priv->status, count);
  1749. }
  1750. desc = iwl_read_targ_mem(priv, base + 1 * sizeof(u32));
  1751. pc = iwl_read_targ_mem(priv, base + 2 * sizeof(u32));
  1752. blink1 = iwl_read_targ_mem(priv, base + 3 * sizeof(u32));
  1753. blink2 = iwl_read_targ_mem(priv, base + 4 * sizeof(u32));
  1754. ilink1 = iwl_read_targ_mem(priv, base + 5 * sizeof(u32));
  1755. ilink2 = iwl_read_targ_mem(priv, base + 6 * sizeof(u32));
  1756. data1 = iwl_read_targ_mem(priv, base + 7 * sizeof(u32));
  1757. data2 = iwl_read_targ_mem(priv, base + 8 * sizeof(u32));
  1758. line = iwl_read_targ_mem(priv, base + 9 * sizeof(u32));
  1759. time = iwl_read_targ_mem(priv, base + 11 * sizeof(u32));
  1760. hcmd = iwl_read_targ_mem(priv, base + 22 * sizeof(u32));
  1761. trace_iwlwifi_dev_ucode_error(priv, desc, time, data1, data2, line,
  1762. blink1, blink2, ilink1, ilink2);
  1763. IWL_ERR(priv, "Desc Time "
  1764. "data1 data2 line\n");
  1765. IWL_ERR(priv, "%-28s (#%02d) %010u 0x%08X 0x%08X %u\n",
  1766. desc_lookup(desc), desc, time, data1, data2, line);
  1767. IWL_ERR(priv, "pc blink1 blink2 ilink1 ilink2 hcmd\n");
  1768. IWL_ERR(priv, "0x%05X 0x%05X 0x%05X 0x%05X 0x%05X 0x%05X\n",
  1769. pc, blink1, blink2, ilink1, ilink2, hcmd);
  1770. }
  1771. #define EVENT_START_OFFSET (4 * sizeof(u32))
  1772. /**
  1773. * iwl_print_event_log - Dump error event log to syslog
  1774. *
  1775. */
  1776. static int iwl_print_event_log(struct iwl_priv *priv, u32 start_idx,
  1777. u32 num_events, u32 mode,
  1778. int pos, char **buf, size_t bufsz)
  1779. {
  1780. u32 i;
  1781. u32 base; /* SRAM byte address of event log header */
  1782. u32 event_size; /* 2 u32s, or 3 u32s if timestamp recorded */
  1783. u32 ptr; /* SRAM byte address of log data */
  1784. u32 ev, time, data; /* event log data */
  1785. unsigned long reg_flags;
  1786. if (num_events == 0)
  1787. return pos;
  1788. if (priv->ucode_type == UCODE_INIT)
  1789. base = le32_to_cpu(priv->card_alive_init.log_event_table_ptr);
  1790. else
  1791. base = le32_to_cpu(priv->card_alive.log_event_table_ptr);
  1792. if (mode == 0)
  1793. event_size = 2 * sizeof(u32);
  1794. else
  1795. event_size = 3 * sizeof(u32);
  1796. ptr = base + EVENT_START_OFFSET + (start_idx * event_size);
  1797. /* Make sure device is powered up for SRAM reads */
  1798. spin_lock_irqsave(&priv->reg_lock, reg_flags);
  1799. iwl_grab_nic_access(priv);
  1800. /* Set starting address; reads will auto-increment */
  1801. _iwl_write_direct32(priv, HBUS_TARG_MEM_RADDR, ptr);
  1802. rmb();
  1803. /* "time" is actually "data" for mode 0 (no timestamp).
  1804. * place event id # at far right for easier visual parsing. */
  1805. for (i = 0; i < num_events; i++) {
  1806. ev = _iwl_read_direct32(priv, HBUS_TARG_MEM_RDAT);
  1807. time = _iwl_read_direct32(priv, HBUS_TARG_MEM_RDAT);
  1808. if (mode == 0) {
  1809. /* data, ev */
  1810. if (bufsz) {
  1811. pos += scnprintf(*buf + pos, bufsz - pos,
  1812. "EVT_LOG:0x%08x:%04u\n",
  1813. time, ev);
  1814. } else {
  1815. trace_iwlwifi_dev_ucode_event(priv, 0,
  1816. time, ev);
  1817. IWL_ERR(priv, "EVT_LOG:0x%08x:%04u\n",
  1818. time, ev);
  1819. }
  1820. } else {
  1821. data = _iwl_read_direct32(priv, HBUS_TARG_MEM_RDAT);
  1822. if (bufsz) {
  1823. pos += scnprintf(*buf + pos, bufsz - pos,
  1824. "EVT_LOGT:%010u:0x%08x:%04u\n",
  1825. time, data, ev);
  1826. } else {
  1827. IWL_ERR(priv, "EVT_LOGT:%010u:0x%08x:%04u\n",
  1828. time, data, ev);
  1829. trace_iwlwifi_dev_ucode_event(priv, time,
  1830. data, ev);
  1831. }
  1832. }
  1833. }
  1834. /* Allow device to power down */
  1835. iwl_release_nic_access(priv);
  1836. spin_unlock_irqrestore(&priv->reg_lock, reg_flags);
  1837. return pos;
  1838. }
  1839. /**
  1840. * iwl_print_last_event_logs - Dump the newest # of event log to syslog
  1841. */
  1842. static int iwl_print_last_event_logs(struct iwl_priv *priv, u32 capacity,
  1843. u32 num_wraps, u32 next_entry,
  1844. u32 size, u32 mode,
  1845. int pos, char **buf, size_t bufsz)
  1846. {
  1847. /*
  1848. * display the newest DEFAULT_LOG_ENTRIES entries
  1849. * i.e the entries just before the next ont that uCode would fill.
  1850. */
  1851. if (num_wraps) {
  1852. if (next_entry < size) {
  1853. pos = iwl_print_event_log(priv,
  1854. capacity - (size - next_entry),
  1855. size - next_entry, mode,
  1856. pos, buf, bufsz);
  1857. pos = iwl_print_event_log(priv, 0,
  1858. next_entry, mode,
  1859. pos, buf, bufsz);
  1860. } else
  1861. pos = iwl_print_event_log(priv, next_entry - size,
  1862. size, mode, pos, buf, bufsz);
  1863. } else {
  1864. if (next_entry < size) {
  1865. pos = iwl_print_event_log(priv, 0, next_entry,
  1866. mode, pos, buf, bufsz);
  1867. } else {
  1868. pos = iwl_print_event_log(priv, next_entry - size,
  1869. size, mode, pos, buf, bufsz);
  1870. }
  1871. }
  1872. return pos;
  1873. }
  1874. #define DEFAULT_DUMP_EVENT_LOG_ENTRIES (20)
  1875. int iwl_dump_nic_event_log(struct iwl_priv *priv, bool full_log,
  1876. char **buf, bool display)
  1877. {
  1878. u32 base; /* SRAM byte address of event log header */
  1879. u32 capacity; /* event log capacity in # entries */
  1880. u32 mode; /* 0 - no timestamp, 1 - timestamp recorded */
  1881. u32 num_wraps; /* # times uCode wrapped to top of log */
  1882. u32 next_entry; /* index of next entry to be written by uCode */
  1883. u32 size; /* # entries that we'll print */
  1884. int pos = 0;
  1885. size_t bufsz = 0;
  1886. if (priv->ucode_type == UCODE_INIT)
  1887. base = le32_to_cpu(priv->card_alive_init.log_event_table_ptr);
  1888. else
  1889. base = le32_to_cpu(priv->card_alive.log_event_table_ptr);
  1890. if (!priv->cfg->ops->lib->is_valid_rtc_data_addr(base)) {
  1891. IWL_ERR(priv,
  1892. "Invalid event log pointer 0x%08X for %s uCode\n",
  1893. base, (priv->ucode_type == UCODE_INIT) ? "Init" : "RT");
  1894. return -EINVAL;
  1895. }
  1896. /* event log header */
  1897. capacity = iwl_read_targ_mem(priv, base);
  1898. mode = iwl_read_targ_mem(priv, base + (1 * sizeof(u32)));
  1899. num_wraps = iwl_read_targ_mem(priv, base + (2 * sizeof(u32)));
  1900. next_entry = iwl_read_targ_mem(priv, base + (3 * sizeof(u32)));
  1901. if (capacity > priv->cfg->max_event_log_size) {
  1902. IWL_ERR(priv, "Log capacity %d is bogus, limit to %d entries\n",
  1903. capacity, priv->cfg->max_event_log_size);
  1904. capacity = priv->cfg->max_event_log_size;
  1905. }
  1906. if (next_entry > priv->cfg->max_event_log_size) {
  1907. IWL_ERR(priv, "Log write index %d is bogus, limit to %d\n",
  1908. next_entry, priv->cfg->max_event_log_size);
  1909. next_entry = priv->cfg->max_event_log_size;
  1910. }
  1911. size = num_wraps ? capacity : next_entry;
  1912. /* bail out if nothing in log */
  1913. if (size == 0) {
  1914. IWL_ERR(priv, "Start IWL Event Log Dump: nothing in log\n");
  1915. return pos;
  1916. }
  1917. #ifdef CONFIG_IWLWIFI_DEBUG
  1918. if (!(iwl_get_debug_level(priv) & IWL_DL_FW_ERRORS) && !full_log)
  1919. size = (size > DEFAULT_DUMP_EVENT_LOG_ENTRIES)
  1920. ? DEFAULT_DUMP_EVENT_LOG_ENTRIES : size;
  1921. #else
  1922. size = (size > DEFAULT_DUMP_EVENT_LOG_ENTRIES)
  1923. ? DEFAULT_DUMP_EVENT_LOG_ENTRIES : size;
  1924. #endif
  1925. IWL_ERR(priv, "Start IWL Event Log Dump: display last %u entries\n",
  1926. size);
  1927. #ifdef CONFIG_IWLWIFI_DEBUG
  1928. if (display) {
  1929. if (full_log)
  1930. bufsz = capacity * 48;
  1931. else
  1932. bufsz = size * 48;
  1933. *buf = kmalloc(bufsz, GFP_KERNEL);
  1934. if (!*buf)
  1935. return -ENOMEM;
  1936. }
  1937. if ((iwl_get_debug_level(priv) & IWL_DL_FW_ERRORS) || full_log) {
  1938. /*
  1939. * if uCode has wrapped back to top of log,
  1940. * start at the oldest entry,
  1941. * i.e the next one that uCode would fill.
  1942. */
  1943. if (num_wraps)
  1944. pos = iwl_print_event_log(priv, next_entry,
  1945. capacity - next_entry, mode,
  1946. pos, buf, bufsz);
  1947. /* (then/else) start at top of log */
  1948. pos = iwl_print_event_log(priv, 0,
  1949. next_entry, mode, pos, buf, bufsz);
  1950. } else
  1951. pos = iwl_print_last_event_logs(priv, capacity, num_wraps,
  1952. next_entry, size, mode,
  1953. pos, buf, bufsz);
  1954. #else
  1955. pos = iwl_print_last_event_logs(priv, capacity, num_wraps,
  1956. next_entry, size, mode,
  1957. pos, buf, bufsz);
  1958. #endif
  1959. return pos;
  1960. }
  1961. /**
  1962. * iwl_alive_start - called after REPLY_ALIVE notification received
  1963. * from protocol/runtime uCode (initialization uCode's
  1964. * Alive gets handled by iwl_init_alive_start()).
  1965. */
  1966. static void iwl_alive_start(struct iwl_priv *priv)
  1967. {
  1968. int ret = 0;
  1969. IWL_DEBUG_INFO(priv, "Runtime Alive received.\n");
  1970. if (priv->card_alive.is_valid != UCODE_VALID_OK) {
  1971. /* We had an error bringing up the hardware, so take it
  1972. * all the way back down so we can try again */
  1973. IWL_DEBUG_INFO(priv, "Alive failed.\n");
  1974. goto restart;
  1975. }
  1976. /* Initialize uCode has loaded Runtime uCode ... verify inst image.
  1977. * This is a paranoid check, because we would not have gotten the
  1978. * "runtime" alive if code weren't properly loaded. */
  1979. if (iwl_verify_ucode(priv)) {
  1980. /* Runtime instruction load was bad;
  1981. * take it all the way back down so we can try again */
  1982. IWL_DEBUG_INFO(priv, "Bad runtime uCode load.\n");
  1983. goto restart;
  1984. }
  1985. ret = priv->cfg->ops->lib->alive_notify(priv);
  1986. if (ret) {
  1987. IWL_WARN(priv,
  1988. "Could not complete ALIVE transition [ntf]: %d\n", ret);
  1989. goto restart;
  1990. }
  1991. /* After the ALIVE response, we can send host commands to the uCode */
  1992. set_bit(STATUS_ALIVE, &priv->status);
  1993. if (priv->cfg->ops->lib->recover_from_tx_stall) {
  1994. /* Enable timer to monitor the driver queues */
  1995. mod_timer(&priv->monitor_recover,
  1996. jiffies +
  1997. msecs_to_jiffies(priv->cfg->monitor_recover_period));
  1998. }
  1999. if (iwl_is_rfkill(priv))
  2000. return;
  2001. ieee80211_wake_queues(priv->hw);
  2002. priv->active_rate = IWL_RATES_MASK;
  2003. /* Configure Tx antenna selection based on H/W config */
  2004. if (priv->cfg->ops->hcmd->set_tx_ant)
  2005. priv->cfg->ops->hcmd->set_tx_ant(priv, priv->cfg->valid_tx_ant);
  2006. if (iwl_is_associated(priv)) {
  2007. struct iwl_rxon_cmd *active_rxon =
  2008. (struct iwl_rxon_cmd *)&priv->active_rxon;
  2009. /* apply any changes in staging */
  2010. priv->staging_rxon.filter_flags |= RXON_FILTER_ASSOC_MSK;
  2011. active_rxon->filter_flags &= ~RXON_FILTER_ASSOC_MSK;
  2012. } else {
  2013. /* Initialize our rx_config data */
  2014. iwl_connection_init_rx_config(priv, NULL);
  2015. if (priv->cfg->ops->hcmd->set_rxon_chain)
  2016. priv->cfg->ops->hcmd->set_rxon_chain(priv);
  2017. memcpy(priv->staging_rxon.node_addr, priv->mac_addr, ETH_ALEN);
  2018. }
  2019. /* Configure Bluetooth device coexistence support */
  2020. priv->cfg->ops->hcmd->send_bt_config(priv);
  2021. iwl_reset_run_time_calib(priv);
  2022. /* Configure the adapter for unassociated operation */
  2023. iwlcore_commit_rxon(priv);
  2024. /* At this point, the NIC is initialized and operational */
  2025. iwl_rf_kill_ct_config(priv);
  2026. iwl_leds_init(priv);
  2027. IWL_DEBUG_INFO(priv, "ALIVE processing complete.\n");
  2028. set_bit(STATUS_READY, &priv->status);
  2029. wake_up_interruptible(&priv->wait_command_queue);
  2030. iwl_power_update_mode(priv, true);
  2031. IWL_DEBUG_INFO(priv, "Updated power mode\n");
  2032. return;
  2033. restart:
  2034. queue_work(priv->workqueue, &priv->restart);
  2035. }
  2036. static void iwl_cancel_deferred_work(struct iwl_priv *priv);
  2037. static void __iwl_down(struct iwl_priv *priv)
  2038. {
  2039. unsigned long flags;
  2040. int exit_pending = test_bit(STATUS_EXIT_PENDING, &priv->status);
  2041. IWL_DEBUG_INFO(priv, DRV_NAME " is going down\n");
  2042. if (!exit_pending)
  2043. set_bit(STATUS_EXIT_PENDING, &priv->status);
  2044. iwl_clear_ucode_stations(priv);
  2045. iwl_dealloc_bcast_station(priv);
  2046. /* Unblock any waiting calls */
  2047. wake_up_interruptible_all(&priv->wait_command_queue);
  2048. /* Wipe out the EXIT_PENDING status bit if we are not actually
  2049. * exiting the module */
  2050. if (!exit_pending)
  2051. clear_bit(STATUS_EXIT_PENDING, &priv->status);
  2052. /* stop and reset the on-board processor */
  2053. iwl_write32(priv, CSR_RESET, CSR_RESET_REG_FLAG_NEVO_RESET);
  2054. /* tell the device to stop sending interrupts */
  2055. spin_lock_irqsave(&priv->lock, flags);
  2056. iwl_disable_interrupts(priv);
  2057. spin_unlock_irqrestore(&priv->lock, flags);
  2058. iwl_synchronize_irq(priv);
  2059. if (priv->mac80211_registered)
  2060. ieee80211_stop_queues(priv->hw);
  2061. /* If we have not previously called iwl_init() then
  2062. * clear all bits but the RF Kill bit and return */
  2063. if (!iwl_is_init(priv)) {
  2064. priv->status = test_bit(STATUS_RF_KILL_HW, &priv->status) <<
  2065. STATUS_RF_KILL_HW |
  2066. test_bit(STATUS_GEO_CONFIGURED, &priv->status) <<
  2067. STATUS_GEO_CONFIGURED |
  2068. test_bit(STATUS_EXIT_PENDING, &priv->status) <<
  2069. STATUS_EXIT_PENDING;
  2070. goto exit;
  2071. }
  2072. /* ...otherwise clear out all the status bits but the RF Kill
  2073. * bit and continue taking the NIC down. */
  2074. priv->status &= test_bit(STATUS_RF_KILL_HW, &priv->status) <<
  2075. STATUS_RF_KILL_HW |
  2076. test_bit(STATUS_GEO_CONFIGURED, &priv->status) <<
  2077. STATUS_GEO_CONFIGURED |
  2078. test_bit(STATUS_FW_ERROR, &priv->status) <<
  2079. STATUS_FW_ERROR |
  2080. test_bit(STATUS_EXIT_PENDING, &priv->status) <<
  2081. STATUS_EXIT_PENDING;
  2082. /* device going down, Stop using ICT table */
  2083. iwl_disable_ict(priv);
  2084. iwlagn_txq_ctx_stop(priv);
  2085. iwlagn_rxq_stop(priv);
  2086. /* Power-down device's busmaster DMA clocks */
  2087. iwl_write_prph(priv, APMG_CLK_DIS_REG, APMG_CLK_VAL_DMA_CLK_RQT);
  2088. udelay(5);
  2089. /* Make sure (redundant) we've released our request to stay awake */
  2090. iwl_clear_bit(priv, CSR_GP_CNTRL, CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ);
  2091. /* Stop the device, and put it in low power state */
  2092. priv->cfg->ops->lib->apm_ops.stop(priv);
  2093. exit:
  2094. memset(&priv->card_alive, 0, sizeof(struct iwl_alive_resp));
  2095. if (priv->ibss_beacon)
  2096. dev_kfree_skb(priv->ibss_beacon);
  2097. priv->ibss_beacon = NULL;
  2098. /* clear out any free frames */
  2099. iwl_clear_free_frames(priv);
  2100. }
  2101. static void iwl_down(struct iwl_priv *priv)
  2102. {
  2103. mutex_lock(&priv->mutex);
  2104. __iwl_down(priv);
  2105. mutex_unlock(&priv->mutex);
  2106. iwl_cancel_deferred_work(priv);
  2107. }
  2108. #define HW_READY_TIMEOUT (50)
  2109. static int iwl_set_hw_ready(struct iwl_priv *priv)
  2110. {
  2111. int ret = 0;
  2112. iwl_set_bit(priv, CSR_HW_IF_CONFIG_REG,
  2113. CSR_HW_IF_CONFIG_REG_BIT_NIC_READY);
  2114. /* See if we got it */
  2115. ret = iwl_poll_bit(priv, CSR_HW_IF_CONFIG_REG,
  2116. CSR_HW_IF_CONFIG_REG_BIT_NIC_READY,
  2117. CSR_HW_IF_CONFIG_REG_BIT_NIC_READY,
  2118. HW_READY_TIMEOUT);
  2119. if (ret != -ETIMEDOUT)
  2120. priv->hw_ready = true;
  2121. else
  2122. priv->hw_ready = false;
  2123. IWL_DEBUG_INFO(priv, "hardware %s\n",
  2124. (priv->hw_ready == 1) ? "ready" : "not ready");
  2125. return ret;
  2126. }
  2127. static int iwl_prepare_card_hw(struct iwl_priv *priv)
  2128. {
  2129. int ret = 0;
  2130. IWL_DEBUG_INFO(priv, "iwl_prepare_card_hw enter\n");
  2131. ret = iwl_set_hw_ready(priv);
  2132. if (priv->hw_ready)
  2133. return ret;
  2134. /* If HW is not ready, prepare the conditions to check again */
  2135. iwl_set_bit(priv, CSR_HW_IF_CONFIG_REG,
  2136. CSR_HW_IF_CONFIG_REG_PREPARE);
  2137. ret = iwl_poll_bit(priv, CSR_HW_IF_CONFIG_REG,
  2138. ~CSR_HW_IF_CONFIG_REG_BIT_NIC_PREPARE_DONE,
  2139. CSR_HW_IF_CONFIG_REG_BIT_NIC_PREPARE_DONE, 150000);
  2140. /* HW should be ready by now, check again. */
  2141. if (ret != -ETIMEDOUT)
  2142. iwl_set_hw_ready(priv);
  2143. return ret;
  2144. }
  2145. #define MAX_HW_RESTARTS 5
  2146. static int __iwl_up(struct iwl_priv *priv)
  2147. {
  2148. int i;
  2149. int ret;
  2150. if (test_bit(STATUS_EXIT_PENDING, &priv->status)) {
  2151. IWL_WARN(priv, "Exit pending; will not bring the NIC up\n");
  2152. return -EIO;
  2153. }
  2154. if (!priv->ucode_data_backup.v_addr || !priv->ucode_data.v_addr) {
  2155. IWL_ERR(priv, "ucode not available for device bringup\n");
  2156. return -EIO;
  2157. }
  2158. ret = iwl_alloc_bcast_station(priv, true);
  2159. if (ret)
  2160. return ret;
  2161. iwl_prepare_card_hw(priv);
  2162. if (!priv->hw_ready) {
  2163. IWL_WARN(priv, "Exit HW not ready\n");
  2164. return -EIO;
  2165. }
  2166. /* If platform's RF_KILL switch is NOT set to KILL */
  2167. if (iwl_read32(priv, CSR_GP_CNTRL) & CSR_GP_CNTRL_REG_FLAG_HW_RF_KILL_SW)
  2168. clear_bit(STATUS_RF_KILL_HW, &priv->status);
  2169. else
  2170. set_bit(STATUS_RF_KILL_HW, &priv->status);
  2171. if (iwl_is_rfkill(priv)) {
  2172. wiphy_rfkill_set_hw_state(priv->hw->wiphy, true);
  2173. iwl_enable_interrupts(priv);
  2174. IWL_WARN(priv, "Radio disabled by HW RF Kill switch\n");
  2175. return 0;
  2176. }
  2177. iwl_write32(priv, CSR_INT, 0xFFFFFFFF);
  2178. ret = iwlagn_hw_nic_init(priv);
  2179. if (ret) {
  2180. IWL_ERR(priv, "Unable to init nic\n");
  2181. return ret;
  2182. }
  2183. /* make sure rfkill handshake bits are cleared */
  2184. iwl_write32(priv, CSR_UCODE_DRV_GP1_CLR, CSR_UCODE_SW_BIT_RFKILL);
  2185. iwl_write32(priv, CSR_UCODE_DRV_GP1_CLR,
  2186. CSR_UCODE_DRV_GP1_BIT_CMD_BLOCKED);
  2187. /* clear (again), then enable host interrupts */
  2188. iwl_write32(priv, CSR_INT, 0xFFFFFFFF);
  2189. iwl_enable_interrupts(priv);
  2190. /* really make sure rfkill handshake bits are cleared */
  2191. iwl_write32(priv, CSR_UCODE_DRV_GP1_CLR, CSR_UCODE_SW_BIT_RFKILL);
  2192. iwl_write32(priv, CSR_UCODE_DRV_GP1_CLR, CSR_UCODE_SW_BIT_RFKILL);
  2193. /* Copy original ucode data image from disk into backup cache.
  2194. * This will be used to initialize the on-board processor's
  2195. * data SRAM for a clean start when the runtime program first loads. */
  2196. memcpy(priv->ucode_data_backup.v_addr, priv->ucode_data.v_addr,
  2197. priv->ucode_data.len);
  2198. for (i = 0; i < MAX_HW_RESTARTS; i++) {
  2199. /* load bootstrap state machine,
  2200. * load bootstrap program into processor's memory,
  2201. * prepare to load the "initialize" uCode */
  2202. ret = priv->cfg->ops->lib->load_ucode(priv);
  2203. if (ret) {
  2204. IWL_ERR(priv, "Unable to set up bootstrap uCode: %d\n",
  2205. ret);
  2206. continue;
  2207. }
  2208. /* start card; "initialize" will load runtime ucode */
  2209. iwl_nic_start(priv);
  2210. IWL_DEBUG_INFO(priv, DRV_NAME " is coming up\n");
  2211. return 0;
  2212. }
  2213. set_bit(STATUS_EXIT_PENDING, &priv->status);
  2214. __iwl_down(priv);
  2215. clear_bit(STATUS_EXIT_PENDING, &priv->status);
  2216. /* tried to restart and config the device for as long as our
  2217. * patience could withstand */
  2218. IWL_ERR(priv, "Unable to initialize device after %d attempts.\n", i);
  2219. return -EIO;
  2220. }
  2221. /*****************************************************************************
  2222. *
  2223. * Workqueue callbacks
  2224. *
  2225. *****************************************************************************/
  2226. static void iwl_bg_init_alive_start(struct work_struct *data)
  2227. {
  2228. struct iwl_priv *priv =
  2229. container_of(data, struct iwl_priv, init_alive_start.work);
  2230. if (test_bit(STATUS_EXIT_PENDING, &priv->status))
  2231. return;
  2232. mutex_lock(&priv->mutex);
  2233. priv->cfg->ops->lib->init_alive_start(priv);
  2234. mutex_unlock(&priv->mutex);
  2235. }
  2236. static void iwl_bg_alive_start(struct work_struct *data)
  2237. {
  2238. struct iwl_priv *priv =
  2239. container_of(data, struct iwl_priv, alive_start.work);
  2240. if (test_bit(STATUS_EXIT_PENDING, &priv->status))
  2241. return;
  2242. /* enable dram interrupt */
  2243. iwl_reset_ict(priv);
  2244. mutex_lock(&priv->mutex);
  2245. iwl_alive_start(priv);
  2246. mutex_unlock(&priv->mutex);
  2247. }
  2248. static void iwl_bg_run_time_calib_work(struct work_struct *work)
  2249. {
  2250. struct iwl_priv *priv = container_of(work, struct iwl_priv,
  2251. run_time_calib_work);
  2252. mutex_lock(&priv->mutex);
  2253. if (test_bit(STATUS_EXIT_PENDING, &priv->status) ||
  2254. test_bit(STATUS_SCANNING, &priv->status)) {
  2255. mutex_unlock(&priv->mutex);
  2256. return;
  2257. }
  2258. if (priv->start_calib) {
  2259. iwl_chain_noise_calibration(priv, &priv->statistics);
  2260. iwl_sensitivity_calibration(priv, &priv->statistics);
  2261. }
  2262. mutex_unlock(&priv->mutex);
  2263. return;
  2264. }
  2265. static void iwl_bg_restart(struct work_struct *data)
  2266. {
  2267. struct iwl_priv *priv = container_of(data, struct iwl_priv, restart);
  2268. if (test_bit(STATUS_EXIT_PENDING, &priv->status))
  2269. return;
  2270. if (test_and_clear_bit(STATUS_FW_ERROR, &priv->status)) {
  2271. mutex_lock(&priv->mutex);
  2272. priv->vif = NULL;
  2273. priv->is_open = 0;
  2274. mutex_unlock(&priv->mutex);
  2275. iwl_down(priv);
  2276. ieee80211_restart_hw(priv->hw);
  2277. } else {
  2278. iwl_down(priv);
  2279. if (test_bit(STATUS_EXIT_PENDING, &priv->status))
  2280. return;
  2281. mutex_lock(&priv->mutex);
  2282. __iwl_up(priv);
  2283. mutex_unlock(&priv->mutex);
  2284. }
  2285. }
  2286. static void iwl_bg_rx_replenish(struct work_struct *data)
  2287. {
  2288. struct iwl_priv *priv =
  2289. container_of(data, struct iwl_priv, rx_replenish);
  2290. if (test_bit(STATUS_EXIT_PENDING, &priv->status))
  2291. return;
  2292. mutex_lock(&priv->mutex);
  2293. iwlagn_rx_replenish(priv);
  2294. mutex_unlock(&priv->mutex);
  2295. }
  2296. #define IWL_DELAY_NEXT_SCAN (HZ*2)
  2297. void iwl_post_associate(struct iwl_priv *priv, struct ieee80211_vif *vif)
  2298. {
  2299. struct ieee80211_conf *conf = NULL;
  2300. int ret = 0;
  2301. if (!vif || !priv->is_open)
  2302. return;
  2303. if (vif->type == NL80211_IFTYPE_AP) {
  2304. IWL_ERR(priv, "%s Should not be called in AP mode\n", __func__);
  2305. return;
  2306. }
  2307. if (test_bit(STATUS_EXIT_PENDING, &priv->status))
  2308. return;
  2309. iwl_scan_cancel_timeout(priv, 200);
  2310. conf = ieee80211_get_hw_conf(priv->hw);
  2311. priv->staging_rxon.filter_flags &= ~RXON_FILTER_ASSOC_MSK;
  2312. iwlcore_commit_rxon(priv);
  2313. iwl_setup_rxon_timing(priv, vif);
  2314. ret = iwl_send_cmd_pdu(priv, REPLY_RXON_TIMING,
  2315. sizeof(priv->rxon_timing), &priv->rxon_timing);
  2316. if (ret)
  2317. IWL_WARN(priv, "REPLY_RXON_TIMING failed - "
  2318. "Attempting to continue.\n");
  2319. priv->staging_rxon.filter_flags |= RXON_FILTER_ASSOC_MSK;
  2320. iwl_set_rxon_ht(priv, &priv->current_ht_config);
  2321. if (priv->cfg->ops->hcmd->set_rxon_chain)
  2322. priv->cfg->ops->hcmd->set_rxon_chain(priv);
  2323. priv->staging_rxon.assoc_id = cpu_to_le16(vif->bss_conf.aid);
  2324. IWL_DEBUG_ASSOC(priv, "assoc id %d beacon interval %d\n",
  2325. vif->bss_conf.aid, vif->bss_conf.beacon_int);
  2326. if (vif->bss_conf.assoc_capability & WLAN_CAPABILITY_SHORT_PREAMBLE)
  2327. priv->staging_rxon.flags |= RXON_FLG_SHORT_PREAMBLE_MSK;
  2328. else
  2329. priv->staging_rxon.flags &= ~RXON_FLG_SHORT_PREAMBLE_MSK;
  2330. if (priv->staging_rxon.flags & RXON_FLG_BAND_24G_MSK) {
  2331. if (vif->bss_conf.assoc_capability &
  2332. WLAN_CAPABILITY_SHORT_SLOT_TIME)
  2333. priv->staging_rxon.flags |= RXON_FLG_SHORT_SLOT_MSK;
  2334. else
  2335. priv->staging_rxon.flags &= ~RXON_FLG_SHORT_SLOT_MSK;
  2336. if (vif->type == NL80211_IFTYPE_ADHOC)
  2337. priv->staging_rxon.flags &= ~RXON_FLG_SHORT_SLOT_MSK;
  2338. }
  2339. iwlcore_commit_rxon(priv);
  2340. IWL_DEBUG_ASSOC(priv, "Associated as %d to: %pM\n",
  2341. vif->bss_conf.aid, priv->active_rxon.bssid_addr);
  2342. switch (vif->type) {
  2343. case NL80211_IFTYPE_STATION:
  2344. break;
  2345. case NL80211_IFTYPE_ADHOC:
  2346. iwl_send_beacon_cmd(priv);
  2347. break;
  2348. default:
  2349. IWL_ERR(priv, "%s Should not be called in %d mode\n",
  2350. __func__, vif->type);
  2351. break;
  2352. }
  2353. /* the chain noise calibration will enabled PM upon completion
  2354. * If chain noise has already been run, then we need to enable
  2355. * power management here */
  2356. if (priv->chain_noise_data.state == IWL_CHAIN_NOISE_DONE)
  2357. iwl_power_update_mode(priv, false);
  2358. /* Enable Rx differential gain and sensitivity calibrations */
  2359. iwl_chain_noise_reset(priv);
  2360. priv->start_calib = 1;
  2361. }
  2362. /*****************************************************************************
  2363. *
  2364. * mac80211 entry point functions
  2365. *
  2366. *****************************************************************************/
  2367. #define UCODE_READY_TIMEOUT (4 * HZ)
  2368. /*
  2369. * Not a mac80211 entry point function, but it fits in with all the
  2370. * other mac80211 functions grouped here.
  2371. */
  2372. static int iwl_mac_setup_register(struct iwl_priv *priv,
  2373. struct iwlagn_ucode_capabilities *capa)
  2374. {
  2375. int ret;
  2376. struct ieee80211_hw *hw = priv->hw;
  2377. hw->rate_control_algorithm = "iwl-agn-rs";
  2378. /* Tell mac80211 our characteristics */
  2379. hw->flags = IEEE80211_HW_SIGNAL_DBM |
  2380. IEEE80211_HW_AMPDU_AGGREGATION |
  2381. IEEE80211_HW_SPECTRUM_MGMT;
  2382. if (!priv->cfg->broken_powersave)
  2383. hw->flags |= IEEE80211_HW_SUPPORTS_PS |
  2384. IEEE80211_HW_SUPPORTS_DYNAMIC_PS;
  2385. if (priv->cfg->sku & IWL_SKU_N)
  2386. hw->flags |= IEEE80211_HW_SUPPORTS_DYNAMIC_SMPS |
  2387. IEEE80211_HW_SUPPORTS_STATIC_SMPS;
  2388. hw->sta_data_size = sizeof(struct iwl_station_priv);
  2389. hw->vif_data_size = sizeof(struct iwl_vif_priv);
  2390. hw->wiphy->interface_modes =
  2391. BIT(NL80211_IFTYPE_STATION) |
  2392. BIT(NL80211_IFTYPE_ADHOC);
  2393. hw->wiphy->flags |= WIPHY_FLAG_CUSTOM_REGULATORY |
  2394. WIPHY_FLAG_DISABLE_BEACON_HINTS;
  2395. /*
  2396. * For now, disable PS by default because it affects
  2397. * RX performance significantly.
  2398. */
  2399. hw->wiphy->flags &= ~WIPHY_FLAG_PS_ON_BY_DEFAULT;
  2400. hw->wiphy->max_scan_ssids = PROBE_OPTION_MAX;
  2401. /* we create the 802.11 header and a zero-length SSID element */
  2402. hw->wiphy->max_scan_ie_len = capa->max_probe_length - 24 - 2;
  2403. /* Default value; 4 EDCA QOS priorities */
  2404. hw->queues = 4;
  2405. hw->max_listen_interval = IWL_CONN_MAX_LISTEN_INTERVAL;
  2406. if (priv->bands[IEEE80211_BAND_2GHZ].n_channels)
  2407. priv->hw->wiphy->bands[IEEE80211_BAND_2GHZ] =
  2408. &priv->bands[IEEE80211_BAND_2GHZ];
  2409. if (priv->bands[IEEE80211_BAND_5GHZ].n_channels)
  2410. priv->hw->wiphy->bands[IEEE80211_BAND_5GHZ] =
  2411. &priv->bands[IEEE80211_BAND_5GHZ];
  2412. ret = ieee80211_register_hw(priv->hw);
  2413. if (ret) {
  2414. IWL_ERR(priv, "Failed to register hw (error %d)\n", ret);
  2415. return ret;
  2416. }
  2417. priv->mac80211_registered = 1;
  2418. return 0;
  2419. }
  2420. static int iwl_mac_start(struct ieee80211_hw *hw)
  2421. {
  2422. struct iwl_priv *priv = hw->priv;
  2423. int ret;
  2424. IWL_DEBUG_MAC80211(priv, "enter\n");
  2425. /* we should be verifying the device is ready to be opened */
  2426. mutex_lock(&priv->mutex);
  2427. ret = __iwl_up(priv);
  2428. mutex_unlock(&priv->mutex);
  2429. if (ret)
  2430. return ret;
  2431. if (iwl_is_rfkill(priv))
  2432. goto out;
  2433. IWL_DEBUG_INFO(priv, "Start UP work done.\n");
  2434. /* Wait for START_ALIVE from Run Time ucode. Otherwise callbacks from
  2435. * mac80211 will not be run successfully. */
  2436. ret = wait_event_interruptible_timeout(priv->wait_command_queue,
  2437. test_bit(STATUS_READY, &priv->status),
  2438. UCODE_READY_TIMEOUT);
  2439. if (!ret) {
  2440. if (!test_bit(STATUS_READY, &priv->status)) {
  2441. IWL_ERR(priv, "START_ALIVE timeout after %dms.\n",
  2442. jiffies_to_msecs(UCODE_READY_TIMEOUT));
  2443. return -ETIMEDOUT;
  2444. }
  2445. }
  2446. iwl_led_start(priv);
  2447. out:
  2448. priv->is_open = 1;
  2449. IWL_DEBUG_MAC80211(priv, "leave\n");
  2450. return 0;
  2451. }
  2452. static void iwl_mac_stop(struct ieee80211_hw *hw)
  2453. {
  2454. struct iwl_priv *priv = hw->priv;
  2455. IWL_DEBUG_MAC80211(priv, "enter\n");
  2456. if (!priv->is_open)
  2457. return;
  2458. priv->is_open = 0;
  2459. if (iwl_is_ready_rf(priv) || test_bit(STATUS_SCAN_HW, &priv->status)) {
  2460. /* stop mac, cancel any scan request and clear
  2461. * RXON_FILTER_ASSOC_MSK BIT
  2462. */
  2463. mutex_lock(&priv->mutex);
  2464. iwl_scan_cancel_timeout(priv, 100);
  2465. mutex_unlock(&priv->mutex);
  2466. }
  2467. iwl_down(priv);
  2468. flush_workqueue(priv->workqueue);
  2469. /* enable interrupts again in order to receive rfkill changes */
  2470. iwl_write32(priv, CSR_INT, 0xFFFFFFFF);
  2471. iwl_enable_interrupts(priv);
  2472. IWL_DEBUG_MAC80211(priv, "leave\n");
  2473. }
  2474. static int iwl_mac_tx(struct ieee80211_hw *hw, struct sk_buff *skb)
  2475. {
  2476. struct iwl_priv *priv = hw->priv;
  2477. IWL_DEBUG_MACDUMP(priv, "enter\n");
  2478. IWL_DEBUG_TX(priv, "dev->xmit(%d bytes) at rate 0x%02x\n", skb->len,
  2479. ieee80211_get_tx_rate(hw, IEEE80211_SKB_CB(skb))->bitrate);
  2480. if (iwlagn_tx_skb(priv, skb))
  2481. dev_kfree_skb_any(skb);
  2482. IWL_DEBUG_MACDUMP(priv, "leave\n");
  2483. return NETDEV_TX_OK;
  2484. }
  2485. void iwl_config_ap(struct iwl_priv *priv, struct ieee80211_vif *vif)
  2486. {
  2487. int ret = 0;
  2488. if (test_bit(STATUS_EXIT_PENDING, &priv->status))
  2489. return;
  2490. /* The following should be done only at AP bring up */
  2491. if (!iwl_is_associated(priv)) {
  2492. /* RXON - unassoc (to set timing command) */
  2493. priv->staging_rxon.filter_flags &= ~RXON_FILTER_ASSOC_MSK;
  2494. iwlcore_commit_rxon(priv);
  2495. /* RXON Timing */
  2496. iwl_setup_rxon_timing(priv, vif);
  2497. ret = iwl_send_cmd_pdu(priv, REPLY_RXON_TIMING,
  2498. sizeof(priv->rxon_timing), &priv->rxon_timing);
  2499. if (ret)
  2500. IWL_WARN(priv, "REPLY_RXON_TIMING failed - "
  2501. "Attempting to continue.\n");
  2502. /* AP has all antennas */
  2503. priv->chain_noise_data.active_chains =
  2504. priv->hw_params.valid_rx_ant;
  2505. iwl_set_rxon_ht(priv, &priv->current_ht_config);
  2506. if (priv->cfg->ops->hcmd->set_rxon_chain)
  2507. priv->cfg->ops->hcmd->set_rxon_chain(priv);
  2508. priv->staging_rxon.assoc_id = 0;
  2509. if (vif->bss_conf.assoc_capability &
  2510. WLAN_CAPABILITY_SHORT_PREAMBLE)
  2511. priv->staging_rxon.flags |=
  2512. RXON_FLG_SHORT_PREAMBLE_MSK;
  2513. else
  2514. priv->staging_rxon.flags &=
  2515. ~RXON_FLG_SHORT_PREAMBLE_MSK;
  2516. if (priv->staging_rxon.flags & RXON_FLG_BAND_24G_MSK) {
  2517. if (vif->bss_conf.assoc_capability &
  2518. WLAN_CAPABILITY_SHORT_SLOT_TIME)
  2519. priv->staging_rxon.flags |=
  2520. RXON_FLG_SHORT_SLOT_MSK;
  2521. else
  2522. priv->staging_rxon.flags &=
  2523. ~RXON_FLG_SHORT_SLOT_MSK;
  2524. if (vif->type == NL80211_IFTYPE_ADHOC)
  2525. priv->staging_rxon.flags &=
  2526. ~RXON_FLG_SHORT_SLOT_MSK;
  2527. }
  2528. /* restore RXON assoc */
  2529. priv->staging_rxon.filter_flags |= RXON_FILTER_ASSOC_MSK;
  2530. iwlcore_commit_rxon(priv);
  2531. }
  2532. iwl_send_beacon_cmd(priv);
  2533. /* FIXME - we need to add code here to detect a totally new
  2534. * configuration, reset the AP, unassoc, rxon timing, assoc,
  2535. * clear sta table, add BCAST sta... */
  2536. }
  2537. static void iwl_mac_update_tkip_key(struct ieee80211_hw *hw,
  2538. struct ieee80211_vif *vif,
  2539. struct ieee80211_key_conf *keyconf,
  2540. struct ieee80211_sta *sta,
  2541. u32 iv32, u16 *phase1key)
  2542. {
  2543. struct iwl_priv *priv = hw->priv;
  2544. IWL_DEBUG_MAC80211(priv, "enter\n");
  2545. iwl_update_tkip_key(priv, keyconf, sta,
  2546. iv32, phase1key);
  2547. IWL_DEBUG_MAC80211(priv, "leave\n");
  2548. }
  2549. static int iwl_mac_set_key(struct ieee80211_hw *hw, enum set_key_cmd cmd,
  2550. struct ieee80211_vif *vif,
  2551. struct ieee80211_sta *sta,
  2552. struct ieee80211_key_conf *key)
  2553. {
  2554. struct iwl_priv *priv = hw->priv;
  2555. int ret;
  2556. u8 sta_id;
  2557. bool is_default_wep_key = false;
  2558. IWL_DEBUG_MAC80211(priv, "enter\n");
  2559. if (priv->cfg->mod_params->sw_crypto) {
  2560. IWL_DEBUG_MAC80211(priv, "leave - hwcrypto disabled\n");
  2561. return -EOPNOTSUPP;
  2562. }
  2563. if (sta) {
  2564. sta_id = iwl_sta_id(sta);
  2565. if (sta_id == IWL_INVALID_STATION) {
  2566. IWL_DEBUG_MAC80211(priv, "leave - %pM not in station map.\n",
  2567. sta->addr);
  2568. return -EINVAL;
  2569. }
  2570. } else {
  2571. sta_id = priv->hw_params.bcast_sta_id;
  2572. }
  2573. mutex_lock(&priv->mutex);
  2574. iwl_scan_cancel_timeout(priv, 100);
  2575. /*
  2576. * If we are getting WEP group key and we didn't receive any key mapping
  2577. * so far, we are in legacy wep mode (group key only), otherwise we are
  2578. * in 1X mode.
  2579. * In legacy wep mode, we use another host command to the uCode.
  2580. */
  2581. if (key->alg == ALG_WEP && !sta && vif->type != NL80211_IFTYPE_AP) {
  2582. if (cmd == SET_KEY)
  2583. is_default_wep_key = !priv->key_mapping_key;
  2584. else
  2585. is_default_wep_key =
  2586. (key->hw_key_idx == HW_KEY_DEFAULT);
  2587. }
  2588. switch (cmd) {
  2589. case SET_KEY:
  2590. if (is_default_wep_key)
  2591. ret = iwl_set_default_wep_key(priv, key);
  2592. else
  2593. ret = iwl_set_dynamic_key(priv, key, sta_id);
  2594. IWL_DEBUG_MAC80211(priv, "enable hwcrypto key\n");
  2595. break;
  2596. case DISABLE_KEY:
  2597. if (is_default_wep_key)
  2598. ret = iwl_remove_default_wep_key(priv, key);
  2599. else
  2600. ret = iwl_remove_dynamic_key(priv, key, sta_id);
  2601. IWL_DEBUG_MAC80211(priv, "disable hwcrypto key\n");
  2602. break;
  2603. default:
  2604. ret = -EINVAL;
  2605. }
  2606. mutex_unlock(&priv->mutex);
  2607. IWL_DEBUG_MAC80211(priv, "leave\n");
  2608. return ret;
  2609. }
  2610. static int iwl_mac_ampdu_action(struct ieee80211_hw *hw,
  2611. struct ieee80211_vif *vif,
  2612. enum ieee80211_ampdu_mlme_action action,
  2613. struct ieee80211_sta *sta, u16 tid, u16 *ssn)
  2614. {
  2615. struct iwl_priv *priv = hw->priv;
  2616. int ret;
  2617. IWL_DEBUG_HT(priv, "A-MPDU action on addr %pM tid %d\n",
  2618. sta->addr, tid);
  2619. if (!(priv->cfg->sku & IWL_SKU_N))
  2620. return -EACCES;
  2621. switch (action) {
  2622. case IEEE80211_AMPDU_RX_START:
  2623. IWL_DEBUG_HT(priv, "start Rx\n");
  2624. return iwl_sta_rx_agg_start(priv, sta, tid, *ssn);
  2625. case IEEE80211_AMPDU_RX_STOP:
  2626. IWL_DEBUG_HT(priv, "stop Rx\n");
  2627. ret = iwl_sta_rx_agg_stop(priv, sta, tid);
  2628. if (test_bit(STATUS_EXIT_PENDING, &priv->status))
  2629. return 0;
  2630. else
  2631. return ret;
  2632. case IEEE80211_AMPDU_TX_START:
  2633. IWL_DEBUG_HT(priv, "start Tx\n");
  2634. ret = iwlagn_tx_agg_start(priv, vif, sta, tid, ssn);
  2635. if (ret == 0) {
  2636. priv->_agn.agg_tids_count++;
  2637. IWL_DEBUG_HT(priv, "priv->_agn.agg_tids_count = %u\n",
  2638. priv->_agn.agg_tids_count);
  2639. }
  2640. return ret;
  2641. case IEEE80211_AMPDU_TX_STOP:
  2642. IWL_DEBUG_HT(priv, "stop Tx\n");
  2643. ret = iwlagn_tx_agg_stop(priv, vif, sta, tid);
  2644. if ((ret == 0) && (priv->_agn.agg_tids_count > 0)) {
  2645. priv->_agn.agg_tids_count--;
  2646. IWL_DEBUG_HT(priv, "priv->_agn.agg_tids_count = %u\n",
  2647. priv->_agn.agg_tids_count);
  2648. }
  2649. if (test_bit(STATUS_EXIT_PENDING, &priv->status))
  2650. return 0;
  2651. else
  2652. return ret;
  2653. case IEEE80211_AMPDU_TX_OPERATIONAL:
  2654. /* do nothing */
  2655. return -EOPNOTSUPP;
  2656. default:
  2657. IWL_DEBUG_HT(priv, "unknown\n");
  2658. return -EINVAL;
  2659. break;
  2660. }
  2661. return 0;
  2662. }
  2663. static void iwl_mac_sta_notify(struct ieee80211_hw *hw,
  2664. struct ieee80211_vif *vif,
  2665. enum sta_notify_cmd cmd,
  2666. struct ieee80211_sta *sta)
  2667. {
  2668. struct iwl_priv *priv = hw->priv;
  2669. struct iwl_station_priv *sta_priv = (void *)sta->drv_priv;
  2670. int sta_id;
  2671. switch (cmd) {
  2672. case STA_NOTIFY_SLEEP:
  2673. WARN_ON(!sta_priv->client);
  2674. sta_priv->asleep = true;
  2675. if (atomic_read(&sta_priv->pending_frames) > 0)
  2676. ieee80211_sta_block_awake(hw, sta, true);
  2677. break;
  2678. case STA_NOTIFY_AWAKE:
  2679. WARN_ON(!sta_priv->client);
  2680. if (!sta_priv->asleep)
  2681. break;
  2682. sta_priv->asleep = false;
  2683. sta_id = iwl_sta_id(sta);
  2684. if (sta_id != IWL_INVALID_STATION)
  2685. iwl_sta_modify_ps_wake(priv, sta_id);
  2686. break;
  2687. default:
  2688. break;
  2689. }
  2690. }
  2691. static int iwlagn_mac_sta_add(struct ieee80211_hw *hw,
  2692. struct ieee80211_vif *vif,
  2693. struct ieee80211_sta *sta)
  2694. {
  2695. struct iwl_priv *priv = hw->priv;
  2696. struct iwl_station_priv *sta_priv = (void *)sta->drv_priv;
  2697. bool is_ap = vif->type == NL80211_IFTYPE_STATION;
  2698. int ret;
  2699. u8 sta_id;
  2700. sta_priv->common.sta_id = IWL_INVALID_STATION;
  2701. IWL_DEBUG_INFO(priv, "received request to add station %pM\n",
  2702. sta->addr);
  2703. atomic_set(&sta_priv->pending_frames, 0);
  2704. if (vif->type == NL80211_IFTYPE_AP)
  2705. sta_priv->client = true;
  2706. ret = iwl_add_station_common(priv, sta->addr, is_ap, &sta->ht_cap,
  2707. &sta_id);
  2708. if (ret) {
  2709. IWL_ERR(priv, "Unable to add station %pM (%d)\n",
  2710. sta->addr, ret);
  2711. /* Should we return success if return code is EEXIST ? */
  2712. return ret;
  2713. }
  2714. sta_priv->common.sta_id = sta_id;
  2715. /* Initialize rate scaling */
  2716. IWL_DEBUG_INFO(priv, "Initializing rate scaling for station %pM\n",
  2717. sta->addr);
  2718. iwl_rs_rate_init(priv, sta, sta_id);
  2719. return 0;
  2720. }
  2721. /*****************************************************************************
  2722. *
  2723. * sysfs attributes
  2724. *
  2725. *****************************************************************************/
  2726. #ifdef CONFIG_IWLWIFI_DEBUG
  2727. /*
  2728. * The following adds a new attribute to the sysfs representation
  2729. * of this device driver (i.e. a new file in /sys/class/net/wlan0/device/)
  2730. * used for controlling the debug level.
  2731. *
  2732. * See the level definitions in iwl for details.
  2733. *
  2734. * The debug_level being managed using sysfs below is a per device debug
  2735. * level that is used instead of the global debug level if it (the per
  2736. * device debug level) is set.
  2737. */
  2738. static ssize_t show_debug_level(struct device *d,
  2739. struct device_attribute *attr, char *buf)
  2740. {
  2741. struct iwl_priv *priv = dev_get_drvdata(d);
  2742. return sprintf(buf, "0x%08X\n", iwl_get_debug_level(priv));
  2743. }
  2744. static ssize_t store_debug_level(struct device *d,
  2745. struct device_attribute *attr,
  2746. const char *buf, size_t count)
  2747. {
  2748. struct iwl_priv *priv = dev_get_drvdata(d);
  2749. unsigned long val;
  2750. int ret;
  2751. ret = strict_strtoul(buf, 0, &val);
  2752. if (ret)
  2753. IWL_ERR(priv, "%s is not in hex or decimal form.\n", buf);
  2754. else {
  2755. priv->debug_level = val;
  2756. if (iwl_alloc_traffic_mem(priv))
  2757. IWL_ERR(priv,
  2758. "Not enough memory to generate traffic log\n");
  2759. }
  2760. return strnlen(buf, count);
  2761. }
  2762. static DEVICE_ATTR(debug_level, S_IWUSR | S_IRUGO,
  2763. show_debug_level, store_debug_level);
  2764. #endif /* CONFIG_IWLWIFI_DEBUG */
  2765. static ssize_t show_temperature(struct device *d,
  2766. struct device_attribute *attr, char *buf)
  2767. {
  2768. struct iwl_priv *priv = dev_get_drvdata(d);
  2769. if (!iwl_is_alive(priv))
  2770. return -EAGAIN;
  2771. return sprintf(buf, "%d\n", priv->temperature);
  2772. }
  2773. static DEVICE_ATTR(temperature, S_IRUGO, show_temperature, NULL);
  2774. static ssize_t show_tx_power(struct device *d,
  2775. struct device_attribute *attr, char *buf)
  2776. {
  2777. struct iwl_priv *priv = dev_get_drvdata(d);
  2778. if (!iwl_is_ready_rf(priv))
  2779. return sprintf(buf, "off\n");
  2780. else
  2781. return sprintf(buf, "%d\n", priv->tx_power_user_lmt);
  2782. }
  2783. static ssize_t store_tx_power(struct device *d,
  2784. struct device_attribute *attr,
  2785. const char *buf, size_t count)
  2786. {
  2787. struct iwl_priv *priv = dev_get_drvdata(d);
  2788. unsigned long val;
  2789. int ret;
  2790. ret = strict_strtoul(buf, 10, &val);
  2791. if (ret)
  2792. IWL_INFO(priv, "%s is not in decimal form.\n", buf);
  2793. else {
  2794. ret = iwl_set_tx_power(priv, val, false);
  2795. if (ret)
  2796. IWL_ERR(priv, "failed setting tx power (0x%d).\n",
  2797. ret);
  2798. else
  2799. ret = count;
  2800. }
  2801. return ret;
  2802. }
  2803. static DEVICE_ATTR(tx_power, S_IWUSR | S_IRUGO, show_tx_power, store_tx_power);
  2804. static ssize_t show_rts_ht_protection(struct device *d,
  2805. struct device_attribute *attr, char *buf)
  2806. {
  2807. struct iwl_priv *priv = dev_get_drvdata(d);
  2808. return sprintf(buf, "%s\n",
  2809. priv->cfg->use_rts_for_ht ? "RTS/CTS" : "CTS-to-self");
  2810. }
  2811. static ssize_t store_rts_ht_protection(struct device *d,
  2812. struct device_attribute *attr,
  2813. const char *buf, size_t count)
  2814. {
  2815. struct iwl_priv *priv = dev_get_drvdata(d);
  2816. unsigned long val;
  2817. int ret;
  2818. ret = strict_strtoul(buf, 10, &val);
  2819. if (ret)
  2820. IWL_INFO(priv, "Input is not in decimal form.\n");
  2821. else {
  2822. if (!iwl_is_associated(priv))
  2823. priv->cfg->use_rts_for_ht = val ? true : false;
  2824. else
  2825. IWL_ERR(priv, "Sta associated with AP - "
  2826. "Change protection mechanism is not allowed\n");
  2827. ret = count;
  2828. }
  2829. return ret;
  2830. }
  2831. static DEVICE_ATTR(rts_ht_protection, S_IWUSR | S_IRUGO,
  2832. show_rts_ht_protection, store_rts_ht_protection);
  2833. /*****************************************************************************
  2834. *
  2835. * driver setup and teardown
  2836. *
  2837. *****************************************************************************/
  2838. static void iwl_setup_deferred_work(struct iwl_priv *priv)
  2839. {
  2840. priv->workqueue = create_singlethread_workqueue(DRV_NAME);
  2841. init_waitqueue_head(&priv->wait_command_queue);
  2842. INIT_WORK(&priv->restart, iwl_bg_restart);
  2843. INIT_WORK(&priv->rx_replenish, iwl_bg_rx_replenish);
  2844. INIT_WORK(&priv->beacon_update, iwl_bg_beacon_update);
  2845. INIT_WORK(&priv->run_time_calib_work, iwl_bg_run_time_calib_work);
  2846. INIT_DELAYED_WORK(&priv->init_alive_start, iwl_bg_init_alive_start);
  2847. INIT_DELAYED_WORK(&priv->alive_start, iwl_bg_alive_start);
  2848. iwl_setup_scan_deferred_work(priv);
  2849. if (priv->cfg->ops->lib->setup_deferred_work)
  2850. priv->cfg->ops->lib->setup_deferred_work(priv);
  2851. init_timer(&priv->statistics_periodic);
  2852. priv->statistics_periodic.data = (unsigned long)priv;
  2853. priv->statistics_periodic.function = iwl_bg_statistics_periodic;
  2854. init_timer(&priv->ucode_trace);
  2855. priv->ucode_trace.data = (unsigned long)priv;
  2856. priv->ucode_trace.function = iwl_bg_ucode_trace;
  2857. if (priv->cfg->ops->lib->recover_from_tx_stall) {
  2858. init_timer(&priv->monitor_recover);
  2859. priv->monitor_recover.data = (unsigned long)priv;
  2860. priv->monitor_recover.function =
  2861. priv->cfg->ops->lib->recover_from_tx_stall;
  2862. }
  2863. if (!priv->cfg->use_isr_legacy)
  2864. tasklet_init(&priv->irq_tasklet, (void (*)(unsigned long))
  2865. iwl_irq_tasklet, (unsigned long)priv);
  2866. else
  2867. tasklet_init(&priv->irq_tasklet, (void (*)(unsigned long))
  2868. iwl_irq_tasklet_legacy, (unsigned long)priv);
  2869. }
  2870. static void iwl_cancel_deferred_work(struct iwl_priv *priv)
  2871. {
  2872. if (priv->cfg->ops->lib->cancel_deferred_work)
  2873. priv->cfg->ops->lib->cancel_deferred_work(priv);
  2874. cancel_delayed_work_sync(&priv->init_alive_start);
  2875. cancel_delayed_work(&priv->scan_check);
  2876. cancel_work_sync(&priv->start_internal_scan);
  2877. cancel_delayed_work(&priv->alive_start);
  2878. cancel_work_sync(&priv->beacon_update);
  2879. del_timer_sync(&priv->statistics_periodic);
  2880. del_timer_sync(&priv->ucode_trace);
  2881. if (priv->cfg->ops->lib->recover_from_tx_stall)
  2882. del_timer_sync(&priv->monitor_recover);
  2883. }
  2884. static void iwl_init_hw_rates(struct iwl_priv *priv,
  2885. struct ieee80211_rate *rates)
  2886. {
  2887. int i;
  2888. for (i = 0; i < IWL_RATE_COUNT_LEGACY; i++) {
  2889. rates[i].bitrate = iwl_rates[i].ieee * 5;
  2890. rates[i].hw_value = i; /* Rate scaling will work on indexes */
  2891. rates[i].hw_value_short = i;
  2892. rates[i].flags = 0;
  2893. if ((i >= IWL_FIRST_CCK_RATE) && (i <= IWL_LAST_CCK_RATE)) {
  2894. /*
  2895. * If CCK != 1M then set short preamble rate flag.
  2896. */
  2897. rates[i].flags |=
  2898. (iwl_rates[i].plcp == IWL_RATE_1M_PLCP) ?
  2899. 0 : IEEE80211_RATE_SHORT_PREAMBLE;
  2900. }
  2901. }
  2902. }
  2903. static int iwl_init_drv(struct iwl_priv *priv)
  2904. {
  2905. int ret;
  2906. priv->ibss_beacon = NULL;
  2907. spin_lock_init(&priv->sta_lock);
  2908. spin_lock_init(&priv->hcmd_lock);
  2909. INIT_LIST_HEAD(&priv->free_frames);
  2910. mutex_init(&priv->mutex);
  2911. mutex_init(&priv->sync_cmd_mutex);
  2912. priv->ieee_channels = NULL;
  2913. priv->ieee_rates = NULL;
  2914. priv->band = IEEE80211_BAND_2GHZ;
  2915. priv->iw_mode = NL80211_IFTYPE_STATION;
  2916. priv->current_ht_config.smps = IEEE80211_SMPS_STATIC;
  2917. priv->missed_beacon_threshold = IWL_MISSED_BEACON_THRESHOLD_DEF;
  2918. priv->_agn.agg_tids_count = 0;
  2919. /* initialize force reset */
  2920. priv->force_reset[IWL_RF_RESET].reset_duration =
  2921. IWL_DELAY_NEXT_FORCE_RF_RESET;
  2922. priv->force_reset[IWL_FW_RESET].reset_duration =
  2923. IWL_DELAY_NEXT_FORCE_FW_RELOAD;
  2924. /* Choose which receivers/antennas to use */
  2925. if (priv->cfg->ops->hcmd->set_rxon_chain)
  2926. priv->cfg->ops->hcmd->set_rxon_chain(priv);
  2927. iwl_init_scan_params(priv);
  2928. /* Set the tx_power_user_lmt to the lowest power level
  2929. * this value will get overwritten by channel max power avg
  2930. * from eeprom */
  2931. priv->tx_power_user_lmt = IWLAGN_TX_POWER_TARGET_POWER_MIN;
  2932. ret = iwl_init_channel_map(priv);
  2933. if (ret) {
  2934. IWL_ERR(priv, "initializing regulatory failed: %d\n", ret);
  2935. goto err;
  2936. }
  2937. ret = iwlcore_init_geos(priv);
  2938. if (ret) {
  2939. IWL_ERR(priv, "initializing geos failed: %d\n", ret);
  2940. goto err_free_channel_map;
  2941. }
  2942. iwl_init_hw_rates(priv, priv->ieee_rates);
  2943. return 0;
  2944. err_free_channel_map:
  2945. iwl_free_channel_map(priv);
  2946. err:
  2947. return ret;
  2948. }
  2949. static void iwl_uninit_drv(struct iwl_priv *priv)
  2950. {
  2951. iwl_calib_free_results(priv);
  2952. iwlcore_free_geos(priv);
  2953. iwl_free_channel_map(priv);
  2954. kfree(priv->scan_cmd);
  2955. }
  2956. static struct attribute *iwl_sysfs_entries[] = {
  2957. &dev_attr_temperature.attr,
  2958. &dev_attr_tx_power.attr,
  2959. &dev_attr_rts_ht_protection.attr,
  2960. #ifdef CONFIG_IWLWIFI_DEBUG
  2961. &dev_attr_debug_level.attr,
  2962. #endif
  2963. NULL
  2964. };
  2965. static struct attribute_group iwl_attribute_group = {
  2966. .name = NULL, /* put in device directory */
  2967. .attrs = iwl_sysfs_entries,
  2968. };
  2969. static struct ieee80211_ops iwl_hw_ops = {
  2970. .tx = iwl_mac_tx,
  2971. .start = iwl_mac_start,
  2972. .stop = iwl_mac_stop,
  2973. .add_interface = iwl_mac_add_interface,
  2974. .remove_interface = iwl_mac_remove_interface,
  2975. .config = iwl_mac_config,
  2976. .configure_filter = iwl_configure_filter,
  2977. .set_key = iwl_mac_set_key,
  2978. .update_tkip_key = iwl_mac_update_tkip_key,
  2979. .conf_tx = iwl_mac_conf_tx,
  2980. .reset_tsf = iwl_mac_reset_tsf,
  2981. .bss_info_changed = iwl_bss_info_changed,
  2982. .ampdu_action = iwl_mac_ampdu_action,
  2983. .hw_scan = iwl_mac_hw_scan,
  2984. .sta_notify = iwl_mac_sta_notify,
  2985. .sta_add = iwlagn_mac_sta_add,
  2986. .sta_remove = iwl_mac_sta_remove,
  2987. };
  2988. static int iwl_pci_probe(struct pci_dev *pdev, const struct pci_device_id *ent)
  2989. {
  2990. int err = 0;
  2991. struct iwl_priv *priv;
  2992. struct ieee80211_hw *hw;
  2993. struct iwl_cfg *cfg = (struct iwl_cfg *)(ent->driver_data);
  2994. unsigned long flags;
  2995. u16 pci_cmd;
  2996. /************************
  2997. * 1. Allocating HW data
  2998. ************************/
  2999. /* Disabling hardware scan means that mac80211 will perform scans
  3000. * "the hard way", rather than using device's scan. */
  3001. if (cfg->mod_params->disable_hw_scan) {
  3002. if (iwl_debug_level & IWL_DL_INFO)
  3003. dev_printk(KERN_DEBUG, &(pdev->dev),
  3004. "Disabling hw_scan\n");
  3005. iwl_hw_ops.hw_scan = NULL;
  3006. }
  3007. hw = iwl_alloc_all(cfg, &iwl_hw_ops);
  3008. if (!hw) {
  3009. err = -ENOMEM;
  3010. goto out;
  3011. }
  3012. priv = hw->priv;
  3013. /* At this point both hw and priv are allocated. */
  3014. SET_IEEE80211_DEV(hw, &pdev->dev);
  3015. IWL_DEBUG_INFO(priv, "*** LOAD DRIVER ***\n");
  3016. priv->cfg = cfg;
  3017. priv->pci_dev = pdev;
  3018. priv->inta_mask = CSR_INI_SET_MASK;
  3019. #ifdef CONFIG_IWLWIFI_DEBUG
  3020. atomic_set(&priv->restrict_refcnt, 0);
  3021. #endif
  3022. if (iwl_alloc_traffic_mem(priv))
  3023. IWL_ERR(priv, "Not enough memory to generate traffic log\n");
  3024. /**************************
  3025. * 2. Initializing PCI bus
  3026. **************************/
  3027. if (pci_enable_device(pdev)) {
  3028. err = -ENODEV;
  3029. goto out_ieee80211_free_hw;
  3030. }
  3031. pci_set_master(pdev);
  3032. err = pci_set_dma_mask(pdev, DMA_BIT_MASK(36));
  3033. if (!err)
  3034. err = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(36));
  3035. if (err) {
  3036. err = pci_set_dma_mask(pdev, DMA_BIT_MASK(32));
  3037. if (!err)
  3038. err = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(32));
  3039. /* both attempts failed: */
  3040. if (err) {
  3041. IWL_WARN(priv, "No suitable DMA available.\n");
  3042. goto out_pci_disable_device;
  3043. }
  3044. }
  3045. err = pci_request_regions(pdev, DRV_NAME);
  3046. if (err)
  3047. goto out_pci_disable_device;
  3048. pci_set_drvdata(pdev, priv);
  3049. /***********************
  3050. * 3. Read REV register
  3051. ***********************/
  3052. priv->hw_base = pci_iomap(pdev, 0, 0);
  3053. if (!priv->hw_base) {
  3054. err = -ENODEV;
  3055. goto out_pci_release_regions;
  3056. }
  3057. IWL_DEBUG_INFO(priv, "pci_resource_len = 0x%08llx\n",
  3058. (unsigned long long) pci_resource_len(pdev, 0));
  3059. IWL_DEBUG_INFO(priv, "pci_resource_base = %p\n", priv->hw_base);
  3060. /* these spin locks will be used in apm_ops.init and EEPROM access
  3061. * we should init now
  3062. */
  3063. spin_lock_init(&priv->reg_lock);
  3064. spin_lock_init(&priv->lock);
  3065. /*
  3066. * stop and reset the on-board processor just in case it is in a
  3067. * strange state ... like being left stranded by a primary kernel
  3068. * and this is now the kdump kernel trying to start up
  3069. */
  3070. iwl_write32(priv, CSR_RESET, CSR_RESET_REG_FLAG_NEVO_RESET);
  3071. iwl_hw_detect(priv);
  3072. IWL_INFO(priv, "Detected %s, REV=0x%X\n",
  3073. priv->cfg->name, priv->hw_rev);
  3074. /* We disable the RETRY_TIMEOUT register (0x41) to keep
  3075. * PCI Tx retries from interfering with C3 CPU state */
  3076. pci_write_config_byte(pdev, PCI_CFG_RETRY_TIMEOUT, 0x00);
  3077. iwl_prepare_card_hw(priv);
  3078. if (!priv->hw_ready) {
  3079. IWL_WARN(priv, "Failed, HW not ready\n");
  3080. goto out_iounmap;
  3081. }
  3082. /*****************
  3083. * 4. Read EEPROM
  3084. *****************/
  3085. /* Read the EEPROM */
  3086. err = iwl_eeprom_init(priv);
  3087. if (err) {
  3088. IWL_ERR(priv, "Unable to init EEPROM\n");
  3089. goto out_iounmap;
  3090. }
  3091. err = iwl_eeprom_check_version(priv);
  3092. if (err)
  3093. goto out_free_eeprom;
  3094. /* extract MAC Address */
  3095. iwl_eeprom_get_mac(priv, priv->mac_addr);
  3096. IWL_DEBUG_INFO(priv, "MAC address: %pM\n", priv->mac_addr);
  3097. SET_IEEE80211_PERM_ADDR(priv->hw, priv->mac_addr);
  3098. /************************
  3099. * 5. Setup HW constants
  3100. ************************/
  3101. if (iwl_set_hw_params(priv)) {
  3102. IWL_ERR(priv, "failed to set hw parameters\n");
  3103. goto out_free_eeprom;
  3104. }
  3105. /*******************
  3106. * 6. Setup priv
  3107. *******************/
  3108. err = iwl_init_drv(priv);
  3109. if (err)
  3110. goto out_free_eeprom;
  3111. /* At this point both hw and priv are initialized. */
  3112. /********************
  3113. * 7. Setup services
  3114. ********************/
  3115. spin_lock_irqsave(&priv->lock, flags);
  3116. iwl_disable_interrupts(priv);
  3117. spin_unlock_irqrestore(&priv->lock, flags);
  3118. pci_enable_msi(priv->pci_dev);
  3119. iwl_alloc_isr_ict(priv);
  3120. err = request_irq(priv->pci_dev->irq, priv->cfg->ops->lib->isr,
  3121. IRQF_SHARED, DRV_NAME, priv);
  3122. if (err) {
  3123. IWL_ERR(priv, "Error allocating IRQ %d\n", priv->pci_dev->irq);
  3124. goto out_disable_msi;
  3125. }
  3126. err = sysfs_create_group(&pdev->dev.kobj, &iwl_attribute_group);
  3127. if (err) {
  3128. IWL_ERR(priv, "failed to create sysfs device attributes\n");
  3129. goto out_free_irq;
  3130. }
  3131. iwl_setup_deferred_work(priv);
  3132. iwl_setup_rx_handlers(priv);
  3133. /*********************************************
  3134. * 8. Enable interrupts and read RFKILL state
  3135. *********************************************/
  3136. /* enable interrupts if needed: hw bug w/a */
  3137. pci_read_config_word(priv->pci_dev, PCI_COMMAND, &pci_cmd);
  3138. if (pci_cmd & PCI_COMMAND_INTX_DISABLE) {
  3139. pci_cmd &= ~PCI_COMMAND_INTX_DISABLE;
  3140. pci_write_config_word(priv->pci_dev, PCI_COMMAND, pci_cmd);
  3141. }
  3142. iwl_enable_interrupts(priv);
  3143. /* If platform's RF_KILL switch is NOT set to KILL */
  3144. if (iwl_read32(priv, CSR_GP_CNTRL) & CSR_GP_CNTRL_REG_FLAG_HW_RF_KILL_SW)
  3145. clear_bit(STATUS_RF_KILL_HW, &priv->status);
  3146. else
  3147. set_bit(STATUS_RF_KILL_HW, &priv->status);
  3148. wiphy_rfkill_set_hw_state(priv->hw->wiphy,
  3149. test_bit(STATUS_RF_KILL_HW, &priv->status));
  3150. iwl_power_initialize(priv);
  3151. iwl_tt_initialize(priv);
  3152. init_completion(&priv->_agn.firmware_loading_complete);
  3153. err = iwl_request_firmware(priv, true);
  3154. if (err)
  3155. goto out_remove_sysfs;
  3156. return 0;
  3157. out_remove_sysfs:
  3158. destroy_workqueue(priv->workqueue);
  3159. priv->workqueue = NULL;
  3160. sysfs_remove_group(&pdev->dev.kobj, &iwl_attribute_group);
  3161. out_free_irq:
  3162. free_irq(priv->pci_dev->irq, priv);
  3163. iwl_free_isr_ict(priv);
  3164. out_disable_msi:
  3165. pci_disable_msi(priv->pci_dev);
  3166. iwl_uninit_drv(priv);
  3167. out_free_eeprom:
  3168. iwl_eeprom_free(priv);
  3169. out_iounmap:
  3170. pci_iounmap(pdev, priv->hw_base);
  3171. out_pci_release_regions:
  3172. pci_set_drvdata(pdev, NULL);
  3173. pci_release_regions(pdev);
  3174. out_pci_disable_device:
  3175. pci_disable_device(pdev);
  3176. out_ieee80211_free_hw:
  3177. iwl_free_traffic_mem(priv);
  3178. ieee80211_free_hw(priv->hw);
  3179. out:
  3180. return err;
  3181. }
  3182. static void __devexit iwl_pci_remove(struct pci_dev *pdev)
  3183. {
  3184. struct iwl_priv *priv = pci_get_drvdata(pdev);
  3185. unsigned long flags;
  3186. if (!priv)
  3187. return;
  3188. wait_for_completion(&priv->_agn.firmware_loading_complete);
  3189. IWL_DEBUG_INFO(priv, "*** UNLOAD DRIVER ***\n");
  3190. iwl_dbgfs_unregister(priv);
  3191. sysfs_remove_group(&pdev->dev.kobj, &iwl_attribute_group);
  3192. /* ieee80211_unregister_hw call wil cause iwl_mac_stop to
  3193. * to be called and iwl_down since we are removing the device
  3194. * we need to set STATUS_EXIT_PENDING bit.
  3195. */
  3196. set_bit(STATUS_EXIT_PENDING, &priv->status);
  3197. if (priv->mac80211_registered) {
  3198. ieee80211_unregister_hw(priv->hw);
  3199. priv->mac80211_registered = 0;
  3200. } else {
  3201. iwl_down(priv);
  3202. }
  3203. /*
  3204. * Make sure device is reset to low power before unloading driver.
  3205. * This may be redundant with iwl_down(), but there are paths to
  3206. * run iwl_down() without calling apm_ops.stop(), and there are
  3207. * paths to avoid running iwl_down() at all before leaving driver.
  3208. * This (inexpensive) call *makes sure* device is reset.
  3209. */
  3210. priv->cfg->ops->lib->apm_ops.stop(priv);
  3211. iwl_tt_exit(priv);
  3212. /* make sure we flush any pending irq or
  3213. * tasklet for the driver
  3214. */
  3215. spin_lock_irqsave(&priv->lock, flags);
  3216. iwl_disable_interrupts(priv);
  3217. spin_unlock_irqrestore(&priv->lock, flags);
  3218. iwl_synchronize_irq(priv);
  3219. iwl_dealloc_ucode_pci(priv);
  3220. if (priv->rxq.bd)
  3221. iwlagn_rx_queue_free(priv, &priv->rxq);
  3222. iwlagn_hw_txq_ctx_free(priv);
  3223. iwl_eeprom_free(priv);
  3224. /*netif_stop_queue(dev); */
  3225. flush_workqueue(priv->workqueue);
  3226. /* ieee80211_unregister_hw calls iwl_mac_stop, which flushes
  3227. * priv->workqueue... so we can't take down the workqueue
  3228. * until now... */
  3229. destroy_workqueue(priv->workqueue);
  3230. priv->workqueue = NULL;
  3231. iwl_free_traffic_mem(priv);
  3232. free_irq(priv->pci_dev->irq, priv);
  3233. pci_disable_msi(priv->pci_dev);
  3234. pci_iounmap(pdev, priv->hw_base);
  3235. pci_release_regions(pdev);
  3236. pci_disable_device(pdev);
  3237. pci_set_drvdata(pdev, NULL);
  3238. iwl_uninit_drv(priv);
  3239. iwl_free_isr_ict(priv);
  3240. if (priv->ibss_beacon)
  3241. dev_kfree_skb(priv->ibss_beacon);
  3242. ieee80211_free_hw(priv->hw);
  3243. }
  3244. /*****************************************************************************
  3245. *
  3246. * driver and module entry point
  3247. *
  3248. *****************************************************************************/
  3249. /* Hardware specific file defines the PCI IDs table for that hardware module */
  3250. static DEFINE_PCI_DEVICE_TABLE(iwl_hw_card_ids) = {
  3251. #ifdef CONFIG_IWL4965
  3252. {IWL_PCI_DEVICE(0x4229, PCI_ANY_ID, iwl4965_agn_cfg)},
  3253. {IWL_PCI_DEVICE(0x4230, PCI_ANY_ID, iwl4965_agn_cfg)},
  3254. #endif /* CONFIG_IWL4965 */
  3255. #ifdef CONFIG_IWL5000
  3256. /* 5100 Series WiFi */
  3257. {IWL_PCI_DEVICE(0x4232, 0x1201, iwl5100_agn_cfg)}, /* Mini Card */
  3258. {IWL_PCI_DEVICE(0x4232, 0x1301, iwl5100_agn_cfg)}, /* Half Mini Card */
  3259. {IWL_PCI_DEVICE(0x4232, 0x1204, iwl5100_agn_cfg)}, /* Mini Card */
  3260. {IWL_PCI_DEVICE(0x4232, 0x1304, iwl5100_agn_cfg)}, /* Half Mini Card */
  3261. {IWL_PCI_DEVICE(0x4232, 0x1205, iwl5100_bgn_cfg)}, /* Mini Card */
  3262. {IWL_PCI_DEVICE(0x4232, 0x1305, iwl5100_bgn_cfg)}, /* Half Mini Card */
  3263. {IWL_PCI_DEVICE(0x4232, 0x1206, iwl5100_abg_cfg)}, /* Mini Card */
  3264. {IWL_PCI_DEVICE(0x4232, 0x1306, iwl5100_abg_cfg)}, /* Half Mini Card */
  3265. {IWL_PCI_DEVICE(0x4232, 0x1221, iwl5100_agn_cfg)}, /* Mini Card */
  3266. {IWL_PCI_DEVICE(0x4232, 0x1321, iwl5100_agn_cfg)}, /* Half Mini Card */
  3267. {IWL_PCI_DEVICE(0x4232, 0x1224, iwl5100_agn_cfg)}, /* Mini Card */
  3268. {IWL_PCI_DEVICE(0x4232, 0x1324, iwl5100_agn_cfg)}, /* Half Mini Card */
  3269. {IWL_PCI_DEVICE(0x4232, 0x1225, iwl5100_bgn_cfg)}, /* Mini Card */
  3270. {IWL_PCI_DEVICE(0x4232, 0x1325, iwl5100_bgn_cfg)}, /* Half Mini Card */
  3271. {IWL_PCI_DEVICE(0x4232, 0x1226, iwl5100_abg_cfg)}, /* Mini Card */
  3272. {IWL_PCI_DEVICE(0x4232, 0x1326, iwl5100_abg_cfg)}, /* Half Mini Card */
  3273. {IWL_PCI_DEVICE(0x4237, 0x1211, iwl5100_agn_cfg)}, /* Mini Card */
  3274. {IWL_PCI_DEVICE(0x4237, 0x1311, iwl5100_agn_cfg)}, /* Half Mini Card */
  3275. {IWL_PCI_DEVICE(0x4237, 0x1214, iwl5100_agn_cfg)}, /* Mini Card */
  3276. {IWL_PCI_DEVICE(0x4237, 0x1314, iwl5100_agn_cfg)}, /* Half Mini Card */
  3277. {IWL_PCI_DEVICE(0x4237, 0x1215, iwl5100_bgn_cfg)}, /* Mini Card */
  3278. {IWL_PCI_DEVICE(0x4237, 0x1315, iwl5100_bgn_cfg)}, /* Half Mini Card */
  3279. {IWL_PCI_DEVICE(0x4237, 0x1216, iwl5100_abg_cfg)}, /* Mini Card */
  3280. {IWL_PCI_DEVICE(0x4237, 0x1316, iwl5100_abg_cfg)}, /* Half Mini Card */
  3281. /* 5300 Series WiFi */
  3282. {IWL_PCI_DEVICE(0x4235, 0x1021, iwl5300_agn_cfg)}, /* Mini Card */
  3283. {IWL_PCI_DEVICE(0x4235, 0x1121, iwl5300_agn_cfg)}, /* Half Mini Card */
  3284. {IWL_PCI_DEVICE(0x4235, 0x1024, iwl5300_agn_cfg)}, /* Mini Card */
  3285. {IWL_PCI_DEVICE(0x4235, 0x1124, iwl5300_agn_cfg)}, /* Half Mini Card */
  3286. {IWL_PCI_DEVICE(0x4235, 0x1001, iwl5300_agn_cfg)}, /* Mini Card */
  3287. {IWL_PCI_DEVICE(0x4235, 0x1101, iwl5300_agn_cfg)}, /* Half Mini Card */
  3288. {IWL_PCI_DEVICE(0x4235, 0x1004, iwl5300_agn_cfg)}, /* Mini Card */
  3289. {IWL_PCI_DEVICE(0x4235, 0x1104, iwl5300_agn_cfg)}, /* Half Mini Card */
  3290. {IWL_PCI_DEVICE(0x4236, 0x1011, iwl5300_agn_cfg)}, /* Mini Card */
  3291. {IWL_PCI_DEVICE(0x4236, 0x1111, iwl5300_agn_cfg)}, /* Half Mini Card */
  3292. {IWL_PCI_DEVICE(0x4236, 0x1014, iwl5300_agn_cfg)}, /* Mini Card */
  3293. {IWL_PCI_DEVICE(0x4236, 0x1114, iwl5300_agn_cfg)}, /* Half Mini Card */
  3294. /* 5350 Series WiFi/WiMax */
  3295. {IWL_PCI_DEVICE(0x423A, 0x1001, iwl5350_agn_cfg)}, /* Mini Card */
  3296. {IWL_PCI_DEVICE(0x423A, 0x1021, iwl5350_agn_cfg)}, /* Mini Card */
  3297. {IWL_PCI_DEVICE(0x423B, 0x1011, iwl5350_agn_cfg)}, /* Mini Card */
  3298. /* 5150 Series Wifi/WiMax */
  3299. {IWL_PCI_DEVICE(0x423C, 0x1201, iwl5150_agn_cfg)}, /* Mini Card */
  3300. {IWL_PCI_DEVICE(0x423C, 0x1301, iwl5150_agn_cfg)}, /* Half Mini Card */
  3301. {IWL_PCI_DEVICE(0x423C, 0x1206, iwl5150_abg_cfg)}, /* Mini Card */
  3302. {IWL_PCI_DEVICE(0x423C, 0x1306, iwl5150_abg_cfg)}, /* Half Mini Card */
  3303. {IWL_PCI_DEVICE(0x423C, 0x1221, iwl5150_agn_cfg)}, /* Mini Card */
  3304. {IWL_PCI_DEVICE(0x423C, 0x1321, iwl5150_agn_cfg)}, /* Half Mini Card */
  3305. {IWL_PCI_DEVICE(0x423D, 0x1211, iwl5150_agn_cfg)}, /* Mini Card */
  3306. {IWL_PCI_DEVICE(0x423D, 0x1311, iwl5150_agn_cfg)}, /* Half Mini Card */
  3307. {IWL_PCI_DEVICE(0x423D, 0x1216, iwl5150_abg_cfg)}, /* Mini Card */
  3308. {IWL_PCI_DEVICE(0x423D, 0x1316, iwl5150_abg_cfg)}, /* Half Mini Card */
  3309. /* 6x00 Series */
  3310. {IWL_PCI_DEVICE(0x422B, 0x1101, iwl6000_3agn_cfg)},
  3311. {IWL_PCI_DEVICE(0x422B, 0x1121, iwl6000_3agn_cfg)},
  3312. {IWL_PCI_DEVICE(0x422C, 0x1301, iwl6000i_2agn_cfg)},
  3313. {IWL_PCI_DEVICE(0x422C, 0x1306, iwl6000i_2abg_cfg)},
  3314. {IWL_PCI_DEVICE(0x422C, 0x1307, iwl6000i_2bg_cfg)},
  3315. {IWL_PCI_DEVICE(0x422C, 0x1321, iwl6000i_2agn_cfg)},
  3316. {IWL_PCI_DEVICE(0x422C, 0x1326, iwl6000i_2abg_cfg)},
  3317. {IWL_PCI_DEVICE(0x4238, 0x1111, iwl6000_3agn_cfg)},
  3318. {IWL_PCI_DEVICE(0x4239, 0x1311, iwl6000i_2agn_cfg)},
  3319. {IWL_PCI_DEVICE(0x4239, 0x1316, iwl6000i_2abg_cfg)},
  3320. /* 6x00 Series Gen2a */
  3321. {IWL_PCI_DEVICE(0x0082, 0x1201, iwl6000g2a_2agn_cfg)},
  3322. {IWL_PCI_DEVICE(0x0085, 0x1211, iwl6000g2a_2agn_cfg)},
  3323. {IWL_PCI_DEVICE(0x0082, 0x1221, iwl6000g2a_2agn_cfg)},
  3324. /* 6x50 WiFi/WiMax Series */
  3325. {IWL_PCI_DEVICE(0x0087, 0x1301, iwl6050_2agn_cfg)},
  3326. {IWL_PCI_DEVICE(0x0087, 0x1306, iwl6050_2abg_cfg)},
  3327. {IWL_PCI_DEVICE(0x0087, 0x1321, iwl6050_2agn_cfg)},
  3328. {IWL_PCI_DEVICE(0x0087, 0x1326, iwl6050_2abg_cfg)},
  3329. {IWL_PCI_DEVICE(0x0089, 0x1311, iwl6050_2agn_cfg)},
  3330. {IWL_PCI_DEVICE(0x0089, 0x1316, iwl6050_2abg_cfg)},
  3331. /* 1000 Series WiFi */
  3332. {IWL_PCI_DEVICE(0x0083, 0x1205, iwl1000_bgn_cfg)},
  3333. {IWL_PCI_DEVICE(0x0083, 0x1305, iwl1000_bgn_cfg)},
  3334. {IWL_PCI_DEVICE(0x0083, 0x1225, iwl1000_bgn_cfg)},
  3335. {IWL_PCI_DEVICE(0x0083, 0x1325, iwl1000_bgn_cfg)},
  3336. {IWL_PCI_DEVICE(0x0084, 0x1215, iwl1000_bgn_cfg)},
  3337. {IWL_PCI_DEVICE(0x0084, 0x1315, iwl1000_bgn_cfg)},
  3338. {IWL_PCI_DEVICE(0x0083, 0x1206, iwl1000_bg_cfg)},
  3339. {IWL_PCI_DEVICE(0x0083, 0x1306, iwl1000_bg_cfg)},
  3340. {IWL_PCI_DEVICE(0x0083, 0x1226, iwl1000_bg_cfg)},
  3341. {IWL_PCI_DEVICE(0x0083, 0x1326, iwl1000_bg_cfg)},
  3342. {IWL_PCI_DEVICE(0x0084, 0x1216, iwl1000_bg_cfg)},
  3343. {IWL_PCI_DEVICE(0x0084, 0x1316, iwl1000_bg_cfg)},
  3344. #endif /* CONFIG_IWL5000 */
  3345. {0}
  3346. };
  3347. MODULE_DEVICE_TABLE(pci, iwl_hw_card_ids);
  3348. static struct pci_driver iwl_driver = {
  3349. .name = DRV_NAME,
  3350. .id_table = iwl_hw_card_ids,
  3351. .probe = iwl_pci_probe,
  3352. .remove = __devexit_p(iwl_pci_remove),
  3353. #ifdef CONFIG_PM
  3354. .suspend = iwl_pci_suspend,
  3355. .resume = iwl_pci_resume,
  3356. #endif
  3357. };
  3358. static int __init iwl_init(void)
  3359. {
  3360. int ret;
  3361. printk(KERN_INFO DRV_NAME ": " DRV_DESCRIPTION ", " DRV_VERSION "\n");
  3362. printk(KERN_INFO DRV_NAME ": " DRV_COPYRIGHT "\n");
  3363. ret = iwlagn_rate_control_register();
  3364. if (ret) {
  3365. printk(KERN_ERR DRV_NAME
  3366. "Unable to register rate control algorithm: %d\n", ret);
  3367. return ret;
  3368. }
  3369. ret = pci_register_driver(&iwl_driver);
  3370. if (ret) {
  3371. printk(KERN_ERR DRV_NAME "Unable to initialize PCI module\n");
  3372. goto error_register;
  3373. }
  3374. return ret;
  3375. error_register:
  3376. iwlagn_rate_control_unregister();
  3377. return ret;
  3378. }
  3379. static void __exit iwl_exit(void)
  3380. {
  3381. pci_unregister_driver(&iwl_driver);
  3382. iwlagn_rate_control_unregister();
  3383. }
  3384. module_exit(iwl_exit);
  3385. module_init(iwl_init);
  3386. #ifdef CONFIG_IWLWIFI_DEBUG
  3387. module_param_named(debug50, iwl_debug_level, uint, S_IRUGO);
  3388. MODULE_PARM_DESC(debug50, "50XX debug output mask (deprecated)");
  3389. module_param_named(debug, iwl_debug_level, uint, S_IRUGO | S_IWUSR);
  3390. MODULE_PARM_DESC(debug, "debug output mask");
  3391. #endif
  3392. module_param_named(swcrypto50, iwlagn_mod_params.sw_crypto, bool, S_IRUGO);
  3393. MODULE_PARM_DESC(swcrypto50,
  3394. "using crypto in software (default 0 [hardware]) (deprecated)");
  3395. module_param_named(swcrypto, iwlagn_mod_params.sw_crypto, int, S_IRUGO);
  3396. MODULE_PARM_DESC(swcrypto, "using crypto in software (default 0 [hardware])");
  3397. module_param_named(queues_num50,
  3398. iwlagn_mod_params.num_of_queues, int, S_IRUGO);
  3399. MODULE_PARM_DESC(queues_num50,
  3400. "number of hw queues in 50xx series (deprecated)");
  3401. module_param_named(queues_num, iwlagn_mod_params.num_of_queues, int, S_IRUGO);
  3402. MODULE_PARM_DESC(queues_num, "number of hw queues.");
  3403. module_param_named(11n_disable50, iwlagn_mod_params.disable_11n, int, S_IRUGO);
  3404. MODULE_PARM_DESC(11n_disable50, "disable 50XX 11n functionality (deprecated)");
  3405. module_param_named(11n_disable, iwlagn_mod_params.disable_11n, int, S_IRUGO);
  3406. MODULE_PARM_DESC(11n_disable, "disable 11n functionality");
  3407. module_param_named(amsdu_size_8K50, iwlagn_mod_params.amsdu_size_8K,
  3408. int, S_IRUGO);
  3409. MODULE_PARM_DESC(amsdu_size_8K50,
  3410. "enable 8K amsdu size in 50XX series (deprecated)");
  3411. module_param_named(amsdu_size_8K, iwlagn_mod_params.amsdu_size_8K,
  3412. int, S_IRUGO);
  3413. MODULE_PARM_DESC(amsdu_size_8K, "enable 8K amsdu size");
  3414. module_param_named(fw_restart50, iwlagn_mod_params.restart_fw, int, S_IRUGO);
  3415. MODULE_PARM_DESC(fw_restart50,
  3416. "restart firmware in case of error (deprecated)");
  3417. module_param_named(fw_restart, iwlagn_mod_params.restart_fw, int, S_IRUGO);
  3418. MODULE_PARM_DESC(fw_restart, "restart firmware in case of error");
  3419. module_param_named(
  3420. disable_hw_scan, iwlagn_mod_params.disable_hw_scan, int, S_IRUGO);
  3421. MODULE_PARM_DESC(disable_hw_scan, "disable hardware scanning (default 0)");
  3422. module_param_named(ucode_alternative, iwlagn_wanted_ucode_alternative, int,
  3423. S_IRUGO);
  3424. MODULE_PARM_DESC(ucode_alternative,
  3425. "specify ucode alternative to use from ucode file");