lapic.c 26 KB

123456789101112131415161718192021222324252627282930313233343536373839404142434445464748495051525354555657585960616263646566676869707172737475767778798081828384858687888990919293949596979899100101102103104105106107108109110111112113114115116117118119120121122123124125126127128129130131132133134135136137138139140141142143144145146147148149150151152153154155156157158159160161162163164165166167168169170171172173174175176177178179180181182183184185186187188189190191192193194195196197198199200201202203204205206207208209210211212213214215216217218219220221222223224225226227228229230231232233234235236237238239240241242243244245246247248249250251252253254255256257258259260261262263264265266267268269270271272273274275276277278279280281282283284285286287288289290291292293294295296297298299300301302303304305306307308309310311312313314315316317318319320321322323324325326327328329330331332333334335336337338339340341342343344345346347348349350351352353354355356357358359360361362363364365366367368369370371372373374375376377378379380381382383384385386387388389390391392393394395396397398399400401402403404405406407408409410411412413414415416417418419420421422423424425426427428429430431432433434435436437438439440441442443444445446447448449450451452453454455456457458459460461462463464465466467468469470471472473474475476477478479480481482483484485486487488489490491492493494495496497498499500501502503504505506507508509510511512513514515516517518519520521522523524525526527528529530531532533534535536537538539540541542543544545546547548549550551552553554555556557558559560561562563564565566567568569570571572573574575576577578579580581582583584585586587588589590591592593594595596597598599600601602603604605606607608609610611612613614615616617618619620621622623624625626627628629630631632633634635636637638639640641642643644645646647648649650651652653654655656657658659660661662663664665666667668669670671672673674675676677678679680681682683684685686687688689690691692693694695696697698699700701702703704705706707708709710711712713714715716717718719720721722723724725726727728729730731732733734735736737738739740741742743744745746747748749750751752753754755756757758759760761762763764765766767768769770771772773774775776777778779780781782783784785786787788789790791792793794795796797798799800801802803804805806807808809810811812813814815816817818819820821822823824825826827828829830831832833834835836837838839840841842843844845846847848849850851852853854855856857858859860861862863864865866867868869870871872873874875876877878879880881882883884885886887888889890891892893894895896897898899900901902903904905906907908909910911912913914915916917918919920921922923924925926927928929930931932933934935936937938939940941942943944945946947948949950951952953954955956957958959960961962963964965966967968969970971972973974975976977978979980981982983984985986987988989990991992993994995996997998999100010011002100310041005100610071008100910101011101210131014101510161017101810191020102110221023102410251026102710281029103010311032103310341035103610371038103910401041104210431044104510461047104810491050105110521053105410551056105710581059106010611062106310641065106610671068106910701071107210731074107510761077107810791080108110821083108410851086108710881089109010911092109310941095109610971098109911001101110211031104110511061107110811091110
  1. /*
  2. * Local APIC virtualization
  3. *
  4. * Copyright (C) 2006 Qumranet, Inc.
  5. * Copyright (C) 2007 Novell
  6. * Copyright (C) 2007 Intel
  7. *
  8. * Authors:
  9. * Dor Laor <dor.laor@qumranet.com>
  10. * Gregory Haskins <ghaskins@novell.com>
  11. * Yaozu (Eddie) Dong <eddie.dong@intel.com>
  12. *
  13. * Based on Xen 3.1 code, Copyright (c) 2004, Intel Corporation.
  14. *
  15. * This work is licensed under the terms of the GNU GPL, version 2. See
  16. * the COPYING file in the top-level directory.
  17. */
  18. #include <linux/kvm_host.h>
  19. #include <linux/kvm.h>
  20. #include <linux/mm.h>
  21. #include <linux/highmem.h>
  22. #include <linux/smp.h>
  23. #include <linux/hrtimer.h>
  24. #include <linux/io.h>
  25. #include <linux/module.h>
  26. #include <linux/math64.h>
  27. #include <asm/processor.h>
  28. #include <asm/msr.h>
  29. #include <asm/page.h>
  30. #include <asm/current.h>
  31. #include <asm/apicdef.h>
  32. #include <asm/atomic.h>
  33. #include "kvm_cache_regs.h"
  34. #include "irq.h"
  35. #include "trace.h"
  36. #ifndef CONFIG_X86_64
  37. #define mod_64(x, y) ((x) - (y) * div64_u64(x, y))
  38. #else
  39. #define mod_64(x, y) ((x) % (y))
  40. #endif
  41. #define PRId64 "d"
  42. #define PRIx64 "llx"
  43. #define PRIu64 "u"
  44. #define PRIo64 "o"
  45. #define APIC_BUS_CYCLE_NS 1
  46. /* #define apic_debug(fmt,arg...) printk(KERN_WARNING fmt,##arg) */
  47. #define apic_debug(fmt, arg...)
  48. #define APIC_LVT_NUM 6
  49. /* 14 is the version for Xeon and Pentium 8.4.8*/
  50. #define APIC_VERSION (0x14UL | ((APIC_LVT_NUM - 1) << 16))
  51. #define LAPIC_MMIO_LENGTH (1 << 12)
  52. /* followed define is not in apicdef.h */
  53. #define APIC_SHORT_MASK 0xc0000
  54. #define APIC_DEST_NOSHORT 0x0
  55. #define APIC_DEST_MASK 0x800
  56. #define MAX_APIC_VECTOR 256
  57. #define VEC_POS(v) ((v) & (32 - 1))
  58. #define REG_POS(v) (((v) >> 5) << 4)
  59. static inline u32 apic_get_reg(struct kvm_lapic *apic, int reg_off)
  60. {
  61. return *((u32 *) (apic->regs + reg_off));
  62. }
  63. static inline void apic_set_reg(struct kvm_lapic *apic, int reg_off, u32 val)
  64. {
  65. *((u32 *) (apic->regs + reg_off)) = val;
  66. }
  67. static inline int apic_test_and_set_vector(int vec, void *bitmap)
  68. {
  69. return test_and_set_bit(VEC_POS(vec), (bitmap) + REG_POS(vec));
  70. }
  71. static inline int apic_test_and_clear_vector(int vec, void *bitmap)
  72. {
  73. return test_and_clear_bit(VEC_POS(vec), (bitmap) + REG_POS(vec));
  74. }
  75. static inline void apic_set_vector(int vec, void *bitmap)
  76. {
  77. set_bit(VEC_POS(vec), (bitmap) + REG_POS(vec));
  78. }
  79. static inline void apic_clear_vector(int vec, void *bitmap)
  80. {
  81. clear_bit(VEC_POS(vec), (bitmap) + REG_POS(vec));
  82. }
  83. static inline int apic_hw_enabled(struct kvm_lapic *apic)
  84. {
  85. return (apic)->vcpu->arch.apic_base & MSR_IA32_APICBASE_ENABLE;
  86. }
  87. static inline int apic_sw_enabled(struct kvm_lapic *apic)
  88. {
  89. return apic_get_reg(apic, APIC_SPIV) & APIC_SPIV_APIC_ENABLED;
  90. }
  91. static inline int apic_enabled(struct kvm_lapic *apic)
  92. {
  93. return apic_sw_enabled(apic) && apic_hw_enabled(apic);
  94. }
  95. #define LVT_MASK \
  96. (APIC_LVT_MASKED | APIC_SEND_PENDING | APIC_VECTOR_MASK)
  97. #define LINT_MASK \
  98. (LVT_MASK | APIC_MODE_MASK | APIC_INPUT_POLARITY | \
  99. APIC_LVT_REMOTE_IRR | APIC_LVT_LEVEL_TRIGGER)
  100. static inline int kvm_apic_id(struct kvm_lapic *apic)
  101. {
  102. return (apic_get_reg(apic, APIC_ID) >> 24) & 0xff;
  103. }
  104. static inline int apic_lvt_enabled(struct kvm_lapic *apic, int lvt_type)
  105. {
  106. return !(apic_get_reg(apic, lvt_type) & APIC_LVT_MASKED);
  107. }
  108. static inline int apic_lvt_vector(struct kvm_lapic *apic, int lvt_type)
  109. {
  110. return apic_get_reg(apic, lvt_type) & APIC_VECTOR_MASK;
  111. }
  112. static inline int apic_lvtt_period(struct kvm_lapic *apic)
  113. {
  114. return apic_get_reg(apic, APIC_LVTT) & APIC_LVT_TIMER_PERIODIC;
  115. }
  116. static inline int apic_lvt_nmi_mode(u32 lvt_val)
  117. {
  118. return (lvt_val & (APIC_MODE_MASK | APIC_LVT_MASKED)) == APIC_DM_NMI;
  119. }
  120. static unsigned int apic_lvt_mask[APIC_LVT_NUM] = {
  121. LVT_MASK | APIC_LVT_TIMER_PERIODIC, /* LVTT */
  122. LVT_MASK | APIC_MODE_MASK, /* LVTTHMR */
  123. LVT_MASK | APIC_MODE_MASK, /* LVTPC */
  124. LINT_MASK, LINT_MASK, /* LVT0-1 */
  125. LVT_MASK /* LVTERR */
  126. };
  127. static int find_highest_vector(void *bitmap)
  128. {
  129. u32 *word = bitmap;
  130. int word_offset = MAX_APIC_VECTOR >> 5;
  131. while ((word_offset != 0) && (word[(--word_offset) << 2] == 0))
  132. continue;
  133. if (likely(!word_offset && !word[0]))
  134. return -1;
  135. else
  136. return fls(word[word_offset << 2]) - 1 + (word_offset << 5);
  137. }
  138. static inline int apic_test_and_set_irr(int vec, struct kvm_lapic *apic)
  139. {
  140. apic->irr_pending = true;
  141. return apic_test_and_set_vector(vec, apic->regs + APIC_IRR);
  142. }
  143. static inline int apic_search_irr(struct kvm_lapic *apic)
  144. {
  145. return find_highest_vector(apic->regs + APIC_IRR);
  146. }
  147. static inline int apic_find_highest_irr(struct kvm_lapic *apic)
  148. {
  149. int result;
  150. if (!apic->irr_pending)
  151. return -1;
  152. result = apic_search_irr(apic);
  153. ASSERT(result == -1 || result >= 16);
  154. return result;
  155. }
  156. static inline void apic_clear_irr(int vec, struct kvm_lapic *apic)
  157. {
  158. apic->irr_pending = false;
  159. apic_clear_vector(vec, apic->regs + APIC_IRR);
  160. if (apic_search_irr(apic) != -1)
  161. apic->irr_pending = true;
  162. }
  163. int kvm_lapic_find_highest_irr(struct kvm_vcpu *vcpu)
  164. {
  165. struct kvm_lapic *apic = vcpu->arch.apic;
  166. int highest_irr;
  167. /* This may race with setting of irr in __apic_accept_irq() and
  168. * value returned may be wrong, but kvm_vcpu_kick() in __apic_accept_irq
  169. * will cause vmexit immediately and the value will be recalculated
  170. * on the next vmentry.
  171. */
  172. if (!apic)
  173. return 0;
  174. highest_irr = apic_find_highest_irr(apic);
  175. return highest_irr;
  176. }
  177. static int __apic_accept_irq(struct kvm_lapic *apic, int delivery_mode,
  178. int vector, int level, int trig_mode);
  179. int kvm_apic_set_irq(struct kvm_vcpu *vcpu, struct kvm_lapic_irq *irq)
  180. {
  181. struct kvm_lapic *apic = vcpu->arch.apic;
  182. return __apic_accept_irq(apic, irq->delivery_mode, irq->vector,
  183. irq->level, irq->trig_mode);
  184. }
  185. static inline int apic_find_highest_isr(struct kvm_lapic *apic)
  186. {
  187. int result;
  188. result = find_highest_vector(apic->regs + APIC_ISR);
  189. ASSERT(result == -1 || result >= 16);
  190. return result;
  191. }
  192. static void apic_update_ppr(struct kvm_lapic *apic)
  193. {
  194. u32 tpr, isrv, ppr;
  195. int isr;
  196. tpr = apic_get_reg(apic, APIC_TASKPRI);
  197. isr = apic_find_highest_isr(apic);
  198. isrv = (isr != -1) ? isr : 0;
  199. if ((tpr & 0xf0) >= (isrv & 0xf0))
  200. ppr = tpr & 0xff;
  201. else
  202. ppr = isrv & 0xf0;
  203. apic_debug("vlapic %p, ppr 0x%x, isr 0x%x, isrv 0x%x",
  204. apic, ppr, isr, isrv);
  205. apic_set_reg(apic, APIC_PROCPRI, ppr);
  206. }
  207. static void apic_set_tpr(struct kvm_lapic *apic, u32 tpr)
  208. {
  209. apic_set_reg(apic, APIC_TASKPRI, tpr);
  210. apic_update_ppr(apic);
  211. }
  212. int kvm_apic_match_physical_addr(struct kvm_lapic *apic, u16 dest)
  213. {
  214. return dest == 0xff || kvm_apic_id(apic) == dest;
  215. }
  216. int kvm_apic_match_logical_addr(struct kvm_lapic *apic, u8 mda)
  217. {
  218. int result = 0;
  219. u8 logical_id;
  220. logical_id = GET_APIC_LOGICAL_ID(apic_get_reg(apic, APIC_LDR));
  221. switch (apic_get_reg(apic, APIC_DFR)) {
  222. case APIC_DFR_FLAT:
  223. if (logical_id & mda)
  224. result = 1;
  225. break;
  226. case APIC_DFR_CLUSTER:
  227. if (((logical_id >> 4) == (mda >> 0x4))
  228. && (logical_id & mda & 0xf))
  229. result = 1;
  230. break;
  231. default:
  232. printk(KERN_WARNING "Bad DFR vcpu %d: %08x\n",
  233. apic->vcpu->vcpu_id, apic_get_reg(apic, APIC_DFR));
  234. break;
  235. }
  236. return result;
  237. }
  238. int kvm_apic_match_dest(struct kvm_vcpu *vcpu, struct kvm_lapic *source,
  239. int short_hand, int dest, int dest_mode)
  240. {
  241. int result = 0;
  242. struct kvm_lapic *target = vcpu->arch.apic;
  243. apic_debug("target %p, source %p, dest 0x%x, "
  244. "dest_mode 0x%x, short_hand 0x%x\n",
  245. target, source, dest, dest_mode, short_hand);
  246. ASSERT(!target);
  247. switch (short_hand) {
  248. case APIC_DEST_NOSHORT:
  249. if (dest_mode == 0)
  250. /* Physical mode. */
  251. result = kvm_apic_match_physical_addr(target, dest);
  252. else
  253. /* Logical mode. */
  254. result = kvm_apic_match_logical_addr(target, dest);
  255. break;
  256. case APIC_DEST_SELF:
  257. result = (target == source);
  258. break;
  259. case APIC_DEST_ALLINC:
  260. result = 1;
  261. break;
  262. case APIC_DEST_ALLBUT:
  263. result = (target != source);
  264. break;
  265. default:
  266. printk(KERN_WARNING "Bad dest shorthand value %x\n",
  267. short_hand);
  268. break;
  269. }
  270. return result;
  271. }
  272. /*
  273. * Add a pending IRQ into lapic.
  274. * Return 1 if successfully added and 0 if discarded.
  275. */
  276. static int __apic_accept_irq(struct kvm_lapic *apic, int delivery_mode,
  277. int vector, int level, int trig_mode)
  278. {
  279. int result = 0;
  280. struct kvm_vcpu *vcpu = apic->vcpu;
  281. switch (delivery_mode) {
  282. case APIC_DM_LOWEST:
  283. vcpu->arch.apic_arb_prio++;
  284. case APIC_DM_FIXED:
  285. /* FIXME add logic for vcpu on reset */
  286. if (unlikely(!apic_enabled(apic)))
  287. break;
  288. result = !apic_test_and_set_irr(vector, apic);
  289. if (!result) {
  290. if (trig_mode)
  291. apic_debug("level trig mode repeatedly for "
  292. "vector %d", vector);
  293. break;
  294. }
  295. if (trig_mode) {
  296. apic_debug("level trig mode for vector %d", vector);
  297. apic_set_vector(vector, apic->regs + APIC_TMR);
  298. } else
  299. apic_clear_vector(vector, apic->regs + APIC_TMR);
  300. kvm_vcpu_kick(vcpu);
  301. break;
  302. case APIC_DM_REMRD:
  303. printk(KERN_DEBUG "Ignoring delivery mode 3\n");
  304. break;
  305. case APIC_DM_SMI:
  306. printk(KERN_DEBUG "Ignoring guest SMI\n");
  307. break;
  308. case APIC_DM_NMI:
  309. result = 1;
  310. kvm_inject_nmi(vcpu);
  311. kvm_vcpu_kick(vcpu);
  312. break;
  313. case APIC_DM_INIT:
  314. if (level) {
  315. result = 1;
  316. if (vcpu->arch.mp_state == KVM_MP_STATE_RUNNABLE)
  317. printk(KERN_DEBUG
  318. "INIT on a runnable vcpu %d\n",
  319. vcpu->vcpu_id);
  320. vcpu->arch.mp_state = KVM_MP_STATE_INIT_RECEIVED;
  321. kvm_vcpu_kick(vcpu);
  322. } else {
  323. apic_debug("Ignoring de-assert INIT to vcpu %d\n",
  324. vcpu->vcpu_id);
  325. }
  326. break;
  327. case APIC_DM_STARTUP:
  328. apic_debug("SIPI to vcpu %d vector 0x%02x\n",
  329. vcpu->vcpu_id, vector);
  330. if (vcpu->arch.mp_state == KVM_MP_STATE_INIT_RECEIVED) {
  331. result = 1;
  332. vcpu->arch.sipi_vector = vector;
  333. vcpu->arch.mp_state = KVM_MP_STATE_SIPI_RECEIVED;
  334. kvm_vcpu_kick(vcpu);
  335. }
  336. break;
  337. case APIC_DM_EXTINT:
  338. /*
  339. * Should only be called by kvm_apic_local_deliver() with LVT0,
  340. * before NMI watchdog was enabled. Already handled by
  341. * kvm_apic_accept_pic_intr().
  342. */
  343. break;
  344. default:
  345. printk(KERN_ERR "TODO: unsupported delivery mode %x\n",
  346. delivery_mode);
  347. break;
  348. }
  349. return result;
  350. }
  351. int kvm_apic_compare_prio(struct kvm_vcpu *vcpu1, struct kvm_vcpu *vcpu2)
  352. {
  353. return vcpu1->arch.apic_arb_prio - vcpu2->arch.apic_arb_prio;
  354. }
  355. static void apic_set_eoi(struct kvm_lapic *apic)
  356. {
  357. int vector = apic_find_highest_isr(apic);
  358. int trigger_mode;
  359. /*
  360. * Not every write EOI will has corresponding ISR,
  361. * one example is when Kernel check timer on setup_IO_APIC
  362. */
  363. if (vector == -1)
  364. return;
  365. apic_clear_vector(vector, apic->regs + APIC_ISR);
  366. apic_update_ppr(apic);
  367. if (apic_test_and_clear_vector(vector, apic->regs + APIC_TMR))
  368. trigger_mode = IOAPIC_LEVEL_TRIG;
  369. else
  370. trigger_mode = IOAPIC_EDGE_TRIG;
  371. mutex_lock(&apic->vcpu->kvm->irq_lock);
  372. kvm_ioapic_update_eoi(apic->vcpu->kvm, vector, trigger_mode);
  373. mutex_unlock(&apic->vcpu->kvm->irq_lock);
  374. }
  375. static void apic_send_ipi(struct kvm_lapic *apic)
  376. {
  377. u32 icr_low = apic_get_reg(apic, APIC_ICR);
  378. u32 icr_high = apic_get_reg(apic, APIC_ICR2);
  379. struct kvm_lapic_irq irq;
  380. irq.vector = icr_low & APIC_VECTOR_MASK;
  381. irq.delivery_mode = icr_low & APIC_MODE_MASK;
  382. irq.dest_mode = icr_low & APIC_DEST_MASK;
  383. irq.level = icr_low & APIC_INT_ASSERT;
  384. irq.trig_mode = icr_low & APIC_INT_LEVELTRIG;
  385. irq.shorthand = icr_low & APIC_SHORT_MASK;
  386. irq.dest_id = GET_APIC_DEST_FIELD(icr_high);
  387. apic_debug("icr_high 0x%x, icr_low 0x%x, "
  388. "short_hand 0x%x, dest 0x%x, trig_mode 0x%x, level 0x%x, "
  389. "dest_mode 0x%x, delivery_mode 0x%x, vector 0x%x\n",
  390. icr_high, icr_low, irq.shorthand, irq.dest_id,
  391. irq.trig_mode, irq.level, irq.dest_mode, irq.delivery_mode,
  392. irq.vector);
  393. mutex_lock(&apic->vcpu->kvm->irq_lock);
  394. kvm_irq_delivery_to_apic(apic->vcpu->kvm, apic, &irq);
  395. mutex_unlock(&apic->vcpu->kvm->irq_lock);
  396. }
  397. static u32 apic_get_tmcct(struct kvm_lapic *apic)
  398. {
  399. ktime_t remaining;
  400. s64 ns;
  401. u32 tmcct;
  402. ASSERT(apic != NULL);
  403. /* if initial count is 0, current count should also be 0 */
  404. if (apic_get_reg(apic, APIC_TMICT) == 0)
  405. return 0;
  406. remaining = hrtimer_expires_remaining(&apic->lapic_timer.timer);
  407. if (ktime_to_ns(remaining) < 0)
  408. remaining = ktime_set(0, 0);
  409. ns = mod_64(ktime_to_ns(remaining), apic->lapic_timer.period);
  410. tmcct = div64_u64(ns,
  411. (APIC_BUS_CYCLE_NS * apic->divide_count));
  412. return tmcct;
  413. }
  414. static void __report_tpr_access(struct kvm_lapic *apic, bool write)
  415. {
  416. struct kvm_vcpu *vcpu = apic->vcpu;
  417. struct kvm_run *run = vcpu->run;
  418. set_bit(KVM_REQ_REPORT_TPR_ACCESS, &vcpu->requests);
  419. run->tpr_access.rip = kvm_rip_read(vcpu);
  420. run->tpr_access.is_write = write;
  421. }
  422. static inline void report_tpr_access(struct kvm_lapic *apic, bool write)
  423. {
  424. if (apic->vcpu->arch.tpr_access_reporting)
  425. __report_tpr_access(apic, write);
  426. }
  427. static u32 __apic_read(struct kvm_lapic *apic, unsigned int offset)
  428. {
  429. u32 val = 0;
  430. if (offset >= LAPIC_MMIO_LENGTH)
  431. return 0;
  432. switch (offset) {
  433. case APIC_ARBPRI:
  434. printk(KERN_WARNING "Access APIC ARBPRI register "
  435. "which is for P6\n");
  436. break;
  437. case APIC_TMCCT: /* Timer CCR */
  438. val = apic_get_tmcct(apic);
  439. break;
  440. case APIC_TASKPRI:
  441. report_tpr_access(apic, false);
  442. /* fall thru */
  443. default:
  444. apic_update_ppr(apic);
  445. val = apic_get_reg(apic, offset);
  446. break;
  447. }
  448. return val;
  449. }
  450. static inline struct kvm_lapic *to_lapic(struct kvm_io_device *dev)
  451. {
  452. return container_of(dev, struct kvm_lapic, dev);
  453. }
  454. static int apic_mmio_in_range(struct kvm_lapic *apic, gpa_t addr)
  455. {
  456. return apic_hw_enabled(apic) &&
  457. addr >= apic->base_address &&
  458. addr < apic->base_address + LAPIC_MMIO_LENGTH;
  459. }
  460. static int apic_mmio_read(struct kvm_io_device *this,
  461. gpa_t address, int len, void *data)
  462. {
  463. struct kvm_lapic *apic = to_lapic(this);
  464. unsigned int offset = address - apic->base_address;
  465. unsigned char alignment = offset & 0xf;
  466. u32 result;
  467. if (!apic_mmio_in_range(apic, address))
  468. return -EOPNOTSUPP;
  469. if ((alignment + len) > 4) {
  470. printk(KERN_ERR "KVM_APIC_READ: alignment error %lx %d",
  471. (unsigned long)address, len);
  472. return 0;
  473. }
  474. result = __apic_read(apic, offset & ~0xf);
  475. trace_kvm_apic_read(offset, result);
  476. switch (len) {
  477. case 1:
  478. case 2:
  479. case 4:
  480. memcpy(data, (char *)&result + alignment, len);
  481. break;
  482. default:
  483. printk(KERN_ERR "Local APIC read with len = %x, "
  484. "should be 1,2, or 4 instead\n", len);
  485. break;
  486. }
  487. return 0;
  488. }
  489. static void update_divide_count(struct kvm_lapic *apic)
  490. {
  491. u32 tmp1, tmp2, tdcr;
  492. tdcr = apic_get_reg(apic, APIC_TDCR);
  493. tmp1 = tdcr & 0xf;
  494. tmp2 = ((tmp1 & 0x3) | ((tmp1 & 0x8) >> 1)) + 1;
  495. apic->divide_count = 0x1 << (tmp2 & 0x7);
  496. apic_debug("timer divide count is 0x%x\n",
  497. apic->divide_count);
  498. }
  499. static void start_apic_timer(struct kvm_lapic *apic)
  500. {
  501. ktime_t now = apic->lapic_timer.timer.base->get_time();
  502. apic->lapic_timer.period = apic_get_reg(apic, APIC_TMICT) *
  503. APIC_BUS_CYCLE_NS * apic->divide_count;
  504. atomic_set(&apic->lapic_timer.pending, 0);
  505. if (!apic->lapic_timer.period)
  506. return;
  507. hrtimer_start(&apic->lapic_timer.timer,
  508. ktime_add_ns(now, apic->lapic_timer.period),
  509. HRTIMER_MODE_ABS);
  510. apic_debug("%s: bus cycle is %" PRId64 "ns, now 0x%016"
  511. PRIx64 ", "
  512. "timer initial count 0x%x, period %lldns, "
  513. "expire @ 0x%016" PRIx64 ".\n", __func__,
  514. APIC_BUS_CYCLE_NS, ktime_to_ns(now),
  515. apic_get_reg(apic, APIC_TMICT),
  516. apic->lapic_timer.period,
  517. ktime_to_ns(ktime_add_ns(now,
  518. apic->lapic_timer.period)));
  519. }
  520. static void apic_manage_nmi_watchdog(struct kvm_lapic *apic, u32 lvt0_val)
  521. {
  522. int nmi_wd_enabled = apic_lvt_nmi_mode(apic_get_reg(apic, APIC_LVT0));
  523. if (apic_lvt_nmi_mode(lvt0_val)) {
  524. if (!nmi_wd_enabled) {
  525. apic_debug("Receive NMI setting on APIC_LVT0 "
  526. "for cpu %d\n", apic->vcpu->vcpu_id);
  527. apic->vcpu->kvm->arch.vapics_in_nmi_mode++;
  528. }
  529. } else if (nmi_wd_enabled)
  530. apic->vcpu->kvm->arch.vapics_in_nmi_mode--;
  531. }
  532. static int apic_mmio_write(struct kvm_io_device *this,
  533. gpa_t address, int len, const void *data)
  534. {
  535. struct kvm_lapic *apic = to_lapic(this);
  536. unsigned int offset = address - apic->base_address;
  537. unsigned char alignment = offset & 0xf;
  538. u32 val;
  539. if (!apic_mmio_in_range(apic, address))
  540. return -EOPNOTSUPP;
  541. /*
  542. * APIC register must be aligned on 128-bits boundary.
  543. * 32/64/128 bits registers must be accessed thru 32 bits.
  544. * Refer SDM 8.4.1
  545. */
  546. if (len != 4 || alignment) {
  547. /* Don't shout loud, $infamous_os would cause only noise. */
  548. apic_debug("apic write: bad size=%d %lx\n",
  549. len, (long)address);
  550. return 0;
  551. }
  552. val = *(u32 *) data;
  553. /* too common printing */
  554. if (offset != APIC_EOI)
  555. apic_debug("%s: offset 0x%x with length 0x%x, and value is "
  556. "0x%x\n", __func__, offset, len, val);
  557. offset &= 0xff0;
  558. trace_kvm_apic_write(offset, val);
  559. switch (offset) {
  560. case APIC_ID: /* Local APIC ID */
  561. apic_set_reg(apic, APIC_ID, val);
  562. break;
  563. case APIC_TASKPRI:
  564. report_tpr_access(apic, true);
  565. apic_set_tpr(apic, val & 0xff);
  566. break;
  567. case APIC_EOI:
  568. apic_set_eoi(apic);
  569. break;
  570. case APIC_LDR:
  571. apic_set_reg(apic, APIC_LDR, val & APIC_LDR_MASK);
  572. break;
  573. case APIC_DFR:
  574. apic_set_reg(apic, APIC_DFR, val | 0x0FFFFFFF);
  575. break;
  576. case APIC_SPIV:
  577. apic_set_reg(apic, APIC_SPIV, val & 0x3ff);
  578. if (!(val & APIC_SPIV_APIC_ENABLED)) {
  579. int i;
  580. u32 lvt_val;
  581. for (i = 0; i < APIC_LVT_NUM; i++) {
  582. lvt_val = apic_get_reg(apic,
  583. APIC_LVTT + 0x10 * i);
  584. apic_set_reg(apic, APIC_LVTT + 0x10 * i,
  585. lvt_val | APIC_LVT_MASKED);
  586. }
  587. atomic_set(&apic->lapic_timer.pending, 0);
  588. }
  589. break;
  590. case APIC_ICR:
  591. /* No delay here, so we always clear the pending bit */
  592. apic_set_reg(apic, APIC_ICR, val & ~(1 << 12));
  593. apic_send_ipi(apic);
  594. break;
  595. case APIC_ICR2:
  596. apic_set_reg(apic, APIC_ICR2, val & 0xff000000);
  597. break;
  598. case APIC_LVT0:
  599. apic_manage_nmi_watchdog(apic, val);
  600. case APIC_LVTT:
  601. case APIC_LVTTHMR:
  602. case APIC_LVTPC:
  603. case APIC_LVT1:
  604. case APIC_LVTERR:
  605. /* TODO: Check vector */
  606. if (!apic_sw_enabled(apic))
  607. val |= APIC_LVT_MASKED;
  608. val &= apic_lvt_mask[(offset - APIC_LVTT) >> 4];
  609. apic_set_reg(apic, offset, val);
  610. break;
  611. case APIC_TMICT:
  612. hrtimer_cancel(&apic->lapic_timer.timer);
  613. apic_set_reg(apic, APIC_TMICT, val);
  614. start_apic_timer(apic);
  615. return 0;
  616. case APIC_TDCR:
  617. if (val & 4)
  618. printk(KERN_ERR "KVM_WRITE:TDCR %x\n", val);
  619. apic_set_reg(apic, APIC_TDCR, val);
  620. update_divide_count(apic);
  621. break;
  622. default:
  623. apic_debug("Local APIC Write to read-only register %x\n",
  624. offset);
  625. break;
  626. }
  627. return 0;
  628. }
  629. void kvm_free_lapic(struct kvm_vcpu *vcpu)
  630. {
  631. if (!vcpu->arch.apic)
  632. return;
  633. hrtimer_cancel(&vcpu->arch.apic->lapic_timer.timer);
  634. if (vcpu->arch.apic->regs_page)
  635. __free_page(vcpu->arch.apic->regs_page);
  636. kfree(vcpu->arch.apic);
  637. }
  638. /*
  639. *----------------------------------------------------------------------
  640. * LAPIC interface
  641. *----------------------------------------------------------------------
  642. */
  643. void kvm_lapic_set_tpr(struct kvm_vcpu *vcpu, unsigned long cr8)
  644. {
  645. struct kvm_lapic *apic = vcpu->arch.apic;
  646. if (!apic)
  647. return;
  648. apic_set_tpr(apic, ((cr8 & 0x0f) << 4)
  649. | (apic_get_reg(apic, APIC_TASKPRI) & 4));
  650. }
  651. u64 kvm_lapic_get_cr8(struct kvm_vcpu *vcpu)
  652. {
  653. struct kvm_lapic *apic = vcpu->arch.apic;
  654. u64 tpr;
  655. if (!apic)
  656. return 0;
  657. tpr = (u64) apic_get_reg(apic, APIC_TASKPRI);
  658. return (tpr & 0xf0) >> 4;
  659. }
  660. void kvm_lapic_set_base(struct kvm_vcpu *vcpu, u64 value)
  661. {
  662. struct kvm_lapic *apic = vcpu->arch.apic;
  663. if (!apic) {
  664. value |= MSR_IA32_APICBASE_BSP;
  665. vcpu->arch.apic_base = value;
  666. return;
  667. }
  668. if (!kvm_vcpu_is_bsp(apic->vcpu))
  669. value &= ~MSR_IA32_APICBASE_BSP;
  670. vcpu->arch.apic_base = value;
  671. apic->base_address = apic->vcpu->arch.apic_base &
  672. MSR_IA32_APICBASE_BASE;
  673. /* with FSB delivery interrupt, we can restart APIC functionality */
  674. apic_debug("apic base msr is 0x%016" PRIx64 ", and base address is "
  675. "0x%lx.\n", apic->vcpu->arch.apic_base, apic->base_address);
  676. }
  677. void kvm_lapic_reset(struct kvm_vcpu *vcpu)
  678. {
  679. struct kvm_lapic *apic;
  680. int i;
  681. apic_debug("%s\n", __func__);
  682. ASSERT(vcpu);
  683. apic = vcpu->arch.apic;
  684. ASSERT(apic != NULL);
  685. /* Stop the timer in case it's a reset to an active apic */
  686. hrtimer_cancel(&apic->lapic_timer.timer);
  687. apic_set_reg(apic, APIC_ID, vcpu->vcpu_id << 24);
  688. apic_set_reg(apic, APIC_LVR, APIC_VERSION);
  689. for (i = 0; i < APIC_LVT_NUM; i++)
  690. apic_set_reg(apic, APIC_LVTT + 0x10 * i, APIC_LVT_MASKED);
  691. apic_set_reg(apic, APIC_LVT0,
  692. SET_APIC_DELIVERY_MODE(0, APIC_MODE_EXTINT));
  693. apic_set_reg(apic, APIC_DFR, 0xffffffffU);
  694. apic_set_reg(apic, APIC_SPIV, 0xff);
  695. apic_set_reg(apic, APIC_TASKPRI, 0);
  696. apic_set_reg(apic, APIC_LDR, 0);
  697. apic_set_reg(apic, APIC_ESR, 0);
  698. apic_set_reg(apic, APIC_ICR, 0);
  699. apic_set_reg(apic, APIC_ICR2, 0);
  700. apic_set_reg(apic, APIC_TDCR, 0);
  701. apic_set_reg(apic, APIC_TMICT, 0);
  702. for (i = 0; i < 8; i++) {
  703. apic_set_reg(apic, APIC_IRR + 0x10 * i, 0);
  704. apic_set_reg(apic, APIC_ISR + 0x10 * i, 0);
  705. apic_set_reg(apic, APIC_TMR + 0x10 * i, 0);
  706. }
  707. apic->irr_pending = false;
  708. update_divide_count(apic);
  709. atomic_set(&apic->lapic_timer.pending, 0);
  710. if (kvm_vcpu_is_bsp(vcpu))
  711. vcpu->arch.apic_base |= MSR_IA32_APICBASE_BSP;
  712. apic_update_ppr(apic);
  713. vcpu->arch.apic_arb_prio = 0;
  714. apic_debug(KERN_INFO "%s: vcpu=%p, id=%d, base_msr="
  715. "0x%016" PRIx64 ", base_address=0x%0lx.\n", __func__,
  716. vcpu, kvm_apic_id(apic),
  717. vcpu->arch.apic_base, apic->base_address);
  718. }
  719. bool kvm_apic_present(struct kvm_vcpu *vcpu)
  720. {
  721. return vcpu->arch.apic && apic_hw_enabled(vcpu->arch.apic);
  722. }
  723. int kvm_lapic_enabled(struct kvm_vcpu *vcpu)
  724. {
  725. return kvm_apic_present(vcpu) && apic_sw_enabled(vcpu->arch.apic);
  726. }
  727. /*
  728. *----------------------------------------------------------------------
  729. * timer interface
  730. *----------------------------------------------------------------------
  731. */
  732. static bool lapic_is_periodic(struct kvm_timer *ktimer)
  733. {
  734. struct kvm_lapic *apic = container_of(ktimer, struct kvm_lapic,
  735. lapic_timer);
  736. return apic_lvtt_period(apic);
  737. }
  738. int apic_has_pending_timer(struct kvm_vcpu *vcpu)
  739. {
  740. struct kvm_lapic *lapic = vcpu->arch.apic;
  741. if (lapic && apic_enabled(lapic) && apic_lvt_enabled(lapic, APIC_LVTT))
  742. return atomic_read(&lapic->lapic_timer.pending);
  743. return 0;
  744. }
  745. static int kvm_apic_local_deliver(struct kvm_lapic *apic, int lvt_type)
  746. {
  747. u32 reg = apic_get_reg(apic, lvt_type);
  748. int vector, mode, trig_mode;
  749. if (apic_hw_enabled(apic) && !(reg & APIC_LVT_MASKED)) {
  750. vector = reg & APIC_VECTOR_MASK;
  751. mode = reg & APIC_MODE_MASK;
  752. trig_mode = reg & APIC_LVT_LEVEL_TRIGGER;
  753. return __apic_accept_irq(apic, mode, vector, 1, trig_mode);
  754. }
  755. return 0;
  756. }
  757. void kvm_apic_nmi_wd_deliver(struct kvm_vcpu *vcpu)
  758. {
  759. struct kvm_lapic *apic = vcpu->arch.apic;
  760. if (apic)
  761. kvm_apic_local_deliver(apic, APIC_LVT0);
  762. }
  763. static struct kvm_timer_ops lapic_timer_ops = {
  764. .is_periodic = lapic_is_periodic,
  765. };
  766. static const struct kvm_io_device_ops apic_mmio_ops = {
  767. .read = apic_mmio_read,
  768. .write = apic_mmio_write,
  769. };
  770. int kvm_create_lapic(struct kvm_vcpu *vcpu)
  771. {
  772. struct kvm_lapic *apic;
  773. ASSERT(vcpu != NULL);
  774. apic_debug("apic_init %d\n", vcpu->vcpu_id);
  775. apic = kzalloc(sizeof(*apic), GFP_KERNEL);
  776. if (!apic)
  777. goto nomem;
  778. vcpu->arch.apic = apic;
  779. apic->regs_page = alloc_page(GFP_KERNEL);
  780. if (apic->regs_page == NULL) {
  781. printk(KERN_ERR "malloc apic regs error for vcpu %x\n",
  782. vcpu->vcpu_id);
  783. goto nomem_free_apic;
  784. }
  785. apic->regs = page_address(apic->regs_page);
  786. memset(apic->regs, 0, PAGE_SIZE);
  787. apic->vcpu = vcpu;
  788. hrtimer_init(&apic->lapic_timer.timer, CLOCK_MONOTONIC,
  789. HRTIMER_MODE_ABS);
  790. apic->lapic_timer.timer.function = kvm_timer_fn;
  791. apic->lapic_timer.t_ops = &lapic_timer_ops;
  792. apic->lapic_timer.kvm = vcpu->kvm;
  793. apic->lapic_timer.vcpu = vcpu;
  794. apic->base_address = APIC_DEFAULT_PHYS_BASE;
  795. vcpu->arch.apic_base = APIC_DEFAULT_PHYS_BASE;
  796. kvm_lapic_reset(vcpu);
  797. kvm_iodevice_init(&apic->dev, &apic_mmio_ops);
  798. return 0;
  799. nomem_free_apic:
  800. kfree(apic);
  801. nomem:
  802. return -ENOMEM;
  803. }
  804. int kvm_apic_has_interrupt(struct kvm_vcpu *vcpu)
  805. {
  806. struct kvm_lapic *apic = vcpu->arch.apic;
  807. int highest_irr;
  808. if (!apic || !apic_enabled(apic))
  809. return -1;
  810. apic_update_ppr(apic);
  811. highest_irr = apic_find_highest_irr(apic);
  812. if ((highest_irr == -1) ||
  813. ((highest_irr & 0xF0) <= apic_get_reg(apic, APIC_PROCPRI)))
  814. return -1;
  815. return highest_irr;
  816. }
  817. int kvm_apic_accept_pic_intr(struct kvm_vcpu *vcpu)
  818. {
  819. u32 lvt0 = apic_get_reg(vcpu->arch.apic, APIC_LVT0);
  820. int r = 0;
  821. if (kvm_vcpu_is_bsp(vcpu)) {
  822. if (!apic_hw_enabled(vcpu->arch.apic))
  823. r = 1;
  824. if ((lvt0 & APIC_LVT_MASKED) == 0 &&
  825. GET_APIC_DELIVERY_MODE(lvt0) == APIC_MODE_EXTINT)
  826. r = 1;
  827. }
  828. return r;
  829. }
  830. void kvm_inject_apic_timer_irqs(struct kvm_vcpu *vcpu)
  831. {
  832. struct kvm_lapic *apic = vcpu->arch.apic;
  833. if (apic && atomic_read(&apic->lapic_timer.pending) > 0) {
  834. if (kvm_apic_local_deliver(apic, APIC_LVTT))
  835. atomic_dec(&apic->lapic_timer.pending);
  836. }
  837. }
  838. int kvm_get_apic_interrupt(struct kvm_vcpu *vcpu)
  839. {
  840. int vector = kvm_apic_has_interrupt(vcpu);
  841. struct kvm_lapic *apic = vcpu->arch.apic;
  842. if (vector == -1)
  843. return -1;
  844. apic_set_vector(vector, apic->regs + APIC_ISR);
  845. apic_update_ppr(apic);
  846. apic_clear_irr(vector, apic);
  847. return vector;
  848. }
  849. void kvm_apic_post_state_restore(struct kvm_vcpu *vcpu)
  850. {
  851. struct kvm_lapic *apic = vcpu->arch.apic;
  852. apic->base_address = vcpu->arch.apic_base &
  853. MSR_IA32_APICBASE_BASE;
  854. apic_set_reg(apic, APIC_LVR, APIC_VERSION);
  855. apic_update_ppr(apic);
  856. hrtimer_cancel(&apic->lapic_timer.timer);
  857. update_divide_count(apic);
  858. start_apic_timer(apic);
  859. }
  860. void __kvm_migrate_apic_timer(struct kvm_vcpu *vcpu)
  861. {
  862. struct kvm_lapic *apic = vcpu->arch.apic;
  863. struct hrtimer *timer;
  864. if (!apic)
  865. return;
  866. timer = &apic->lapic_timer.timer;
  867. if (hrtimer_cancel(timer))
  868. hrtimer_start_expires(timer, HRTIMER_MODE_ABS);
  869. }
  870. void kvm_lapic_sync_from_vapic(struct kvm_vcpu *vcpu)
  871. {
  872. u32 data;
  873. void *vapic;
  874. if (!irqchip_in_kernel(vcpu->kvm) || !vcpu->arch.apic->vapic_addr)
  875. return;
  876. vapic = kmap_atomic(vcpu->arch.apic->vapic_page, KM_USER0);
  877. data = *(u32 *)(vapic + offset_in_page(vcpu->arch.apic->vapic_addr));
  878. kunmap_atomic(vapic, KM_USER0);
  879. apic_set_tpr(vcpu->arch.apic, data & 0xff);
  880. }
  881. void kvm_lapic_sync_to_vapic(struct kvm_vcpu *vcpu)
  882. {
  883. u32 data, tpr;
  884. int max_irr, max_isr;
  885. struct kvm_lapic *apic;
  886. void *vapic;
  887. if (!irqchip_in_kernel(vcpu->kvm) || !vcpu->arch.apic->vapic_addr)
  888. return;
  889. apic = vcpu->arch.apic;
  890. tpr = apic_get_reg(apic, APIC_TASKPRI) & 0xff;
  891. max_irr = apic_find_highest_irr(apic);
  892. if (max_irr < 0)
  893. max_irr = 0;
  894. max_isr = apic_find_highest_isr(apic);
  895. if (max_isr < 0)
  896. max_isr = 0;
  897. data = (tpr & 0xff) | ((max_isr & 0xf0) << 8) | (max_irr << 24);
  898. vapic = kmap_atomic(vcpu->arch.apic->vapic_page, KM_USER0);
  899. *(u32 *)(vapic + offset_in_page(vcpu->arch.apic->vapic_addr)) = data;
  900. kunmap_atomic(vapic, KM_USER0);
  901. }
  902. void kvm_lapic_set_vapic_addr(struct kvm_vcpu *vcpu, gpa_t vapic_addr)
  903. {
  904. if (!irqchip_in_kernel(vcpu->kvm))
  905. return;
  906. vcpu->arch.apic->vapic_addr = vapic_addr;
  907. }