tegra124.dtsi 3.2 KB

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  1. #include <dt-bindings/interrupt-controller/arm-gic.h>
  2. #include "skeleton.dtsi"
  3. / {
  4. compatible = "nvidia,tegra124";
  5. interrupt-parent = <&gic>;
  6. gic: interrupt-controller@50041000 {
  7. compatible = "arm,cortex-a15-gic";
  8. #interrupt-cells = <3>;
  9. interrupt-controller;
  10. reg = <0x50041000 0x1000>,
  11. <0x50042000 0x1000>,
  12. <0x50044000 0x2000>,
  13. <0x50046000 0x2000>;
  14. interrupts = <GIC_PPI 9
  15. (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
  16. };
  17. timer@60005000 {
  18. compatible = "nvidia,tegra124-timer", "nvidia,tegra20-timer";
  19. reg = <0x60005000 0x400>;
  20. interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
  21. <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>,
  22. <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>,
  23. <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>,
  24. <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>,
  25. <GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>;
  26. };
  27. /*
  28. * There are two serial driver i.e. 8250 based simple serial
  29. * driver and APB DMA based serial driver for higher baudrate
  30. * and performace. To enable the 8250 based driver, the compatible
  31. * is "nvidia,tegra124-uart", "nvidia,tegra20-uart" and to enable
  32. * the APB DMA based serial driver, the comptible is
  33. * "nvidia,tegra124-hsuart", "nvidia,tegra30-hsuart".
  34. */
  35. serial@70006000 {
  36. compatible = "nvidia,tegra124-uart", "nvidia,tegra20-uart";
  37. reg = <0x70006000 0x40>;
  38. reg-shift = <2>;
  39. interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
  40. status = "disabled";
  41. };
  42. serial@70006040 {
  43. compatible = "nvidia,tegra124-uart", "nvidia,tegra20-uart";
  44. reg = <0x70006040 0x40>;
  45. reg-shift = <2>;
  46. interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
  47. status = "disabled";
  48. };
  49. serial@70006200 {
  50. compatible = "nvidia,tegra124-uart", "nvidia,tegra20-uart";
  51. reg = <0x70006200 0x40>;
  52. reg-shift = <2>;
  53. interrupts = <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>;
  54. status = "disabled";
  55. };
  56. serial@70006300 {
  57. compatible = "nvidia,tegra124-uart", "nvidia,tegra20-uart";
  58. reg = <0x70006300 0x40>;
  59. reg-shift = <2>;
  60. interrupts = <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>;
  61. status = "disabled";
  62. };
  63. serial@70006400 {
  64. compatible = "nvidia,tegra124-uart", "nvidia,tegra20-uart";
  65. reg = <0x70006400 0x40>;
  66. reg-shift = <2>;
  67. interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>;
  68. status = "disabled";
  69. };
  70. rtc@7000e000 {
  71. compatible = "nvidia,tegra124-rtc", "nvidia,tegra20-rtc";
  72. reg = <0x7000e000 0x100>;
  73. interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>;
  74. };
  75. pmc@7000e400 {
  76. compatible = "nvidia,tegra124-pmc";
  77. reg = <0x7000e400 0x400>;
  78. };
  79. cpus {
  80. #address-cells = <1>;
  81. #size-cells = <0>;
  82. cpu@0 {
  83. device_type = "cpu";
  84. compatible = "arm,cortex-a15";
  85. reg = <0>;
  86. };
  87. cpu@1 {
  88. device_type = "cpu";
  89. compatible = "arm,cortex-a15";
  90. reg = <1>;
  91. };
  92. cpu@2 {
  93. device_type = "cpu";
  94. compatible = "arm,cortex-a15";
  95. reg = <2>;
  96. };
  97. cpu@3 {
  98. device_type = "cpu";
  99. compatible = "arm,cortex-a15";
  100. reg = <3>;
  101. };
  102. };
  103. timer {
  104. compatible = "arm,armv7-timer";
  105. interrupts = <GIC_PPI 13
  106. (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
  107. <GIC_PPI 14
  108. (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
  109. <GIC_PPI 11
  110. (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
  111. <GIC_PPI 10
  112. (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>;
  113. };
  114. };