cpsw.c 31 KB

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  1. /*
  2. * Texas Instruments Ethernet Switch Driver
  3. *
  4. * Copyright (C) 2012 Texas Instruments
  5. *
  6. * This program is free software; you can redistribute it and/or
  7. * modify it under the terms of the GNU General Public License as
  8. * published by the Free Software Foundation version 2.
  9. *
  10. * This program is distributed "as is" WITHOUT ANY WARRANTY of any
  11. * kind, whether express or implied; without even the implied warranty
  12. * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  13. * GNU General Public License for more details.
  14. */
  15. #include <linux/kernel.h>
  16. #include <linux/io.h>
  17. #include <linux/clk.h>
  18. #include <linux/timer.h>
  19. #include <linux/module.h>
  20. #include <linux/platform_device.h>
  21. #include <linux/irqreturn.h>
  22. #include <linux/interrupt.h>
  23. #include <linux/if_ether.h>
  24. #include <linux/etherdevice.h>
  25. #include <linux/netdevice.h>
  26. #include <linux/phy.h>
  27. #include <linux/workqueue.h>
  28. #include <linux/delay.h>
  29. #include <linux/pm_runtime.h>
  30. #include <linux/of.h>
  31. #include <linux/of_net.h>
  32. #include <linux/of_device.h>
  33. #include <linux/platform_data/cpsw.h>
  34. #include "cpsw_ale.h"
  35. #include "davinci_cpdma.h"
  36. #define CPSW_DEBUG (NETIF_MSG_HW | NETIF_MSG_WOL | \
  37. NETIF_MSG_DRV | NETIF_MSG_LINK | \
  38. NETIF_MSG_IFUP | NETIF_MSG_INTR | \
  39. NETIF_MSG_PROBE | NETIF_MSG_TIMER | \
  40. NETIF_MSG_IFDOWN | NETIF_MSG_RX_ERR | \
  41. NETIF_MSG_TX_ERR | NETIF_MSG_TX_DONE | \
  42. NETIF_MSG_PKTDATA | NETIF_MSG_TX_QUEUED | \
  43. NETIF_MSG_RX_STATUS)
  44. #define cpsw_info(priv, type, format, ...) \
  45. do { \
  46. if (netif_msg_##type(priv) && net_ratelimit()) \
  47. dev_info(priv->dev, format, ## __VA_ARGS__); \
  48. } while (0)
  49. #define cpsw_err(priv, type, format, ...) \
  50. do { \
  51. if (netif_msg_##type(priv) && net_ratelimit()) \
  52. dev_err(priv->dev, format, ## __VA_ARGS__); \
  53. } while (0)
  54. #define cpsw_dbg(priv, type, format, ...) \
  55. do { \
  56. if (netif_msg_##type(priv) && net_ratelimit()) \
  57. dev_dbg(priv->dev, format, ## __VA_ARGS__); \
  58. } while (0)
  59. #define cpsw_notice(priv, type, format, ...) \
  60. do { \
  61. if (netif_msg_##type(priv) && net_ratelimit()) \
  62. dev_notice(priv->dev, format, ## __VA_ARGS__); \
  63. } while (0)
  64. #define ALE_ALL_PORTS 0x7
  65. #define CPSW_MAJOR_VERSION(reg) (reg >> 8 & 0x7)
  66. #define CPSW_MINOR_VERSION(reg) (reg & 0xff)
  67. #define CPSW_RTL_VERSION(reg) ((reg >> 11) & 0x1f)
  68. #define CPDMA_RXTHRESH 0x0c0
  69. #define CPDMA_RXFREE 0x0e0
  70. #define CPDMA_TXHDP 0x00
  71. #define CPDMA_RXHDP 0x20
  72. #define CPDMA_TXCP 0x40
  73. #define CPDMA_RXCP 0x60
  74. #define cpsw_dma_regs(base, offset) \
  75. (void __iomem *)((base) + (offset))
  76. #define cpsw_dma_rxthresh(base, offset) \
  77. (void __iomem *)((base) + (offset) + CPDMA_RXTHRESH)
  78. #define cpsw_dma_rxfree(base, offset) \
  79. (void __iomem *)((base) + (offset) + CPDMA_RXFREE)
  80. #define cpsw_dma_txhdp(base, offset) \
  81. (void __iomem *)((base) + (offset) + CPDMA_TXHDP)
  82. #define cpsw_dma_rxhdp(base, offset) \
  83. (void __iomem *)((base) + (offset) + CPDMA_RXHDP)
  84. #define cpsw_dma_txcp(base, offset) \
  85. (void __iomem *)((base) + (offset) + CPDMA_TXCP)
  86. #define cpsw_dma_rxcp(base, offset) \
  87. (void __iomem *)((base) + (offset) + CPDMA_RXCP)
  88. #define CPSW_POLL_WEIGHT 64
  89. #define CPSW_MIN_PACKET_SIZE 60
  90. #define CPSW_MAX_PACKET_SIZE (1500 + 14 + 4 + 4)
  91. #define RX_PRIORITY_MAPPING 0x76543210
  92. #define TX_PRIORITY_MAPPING 0x33221100
  93. #define CPDMA_TX_PRIORITY_MAP 0x76543210
  94. #define cpsw_enable_irq(priv) \
  95. do { \
  96. u32 i; \
  97. for (i = 0; i < priv->num_irqs; i++) \
  98. enable_irq(priv->irqs_table[i]); \
  99. } while (0);
  100. #define cpsw_disable_irq(priv) \
  101. do { \
  102. u32 i; \
  103. for (i = 0; i < priv->num_irqs; i++) \
  104. disable_irq_nosync(priv->irqs_table[i]); \
  105. } while (0);
  106. static int debug_level;
  107. module_param(debug_level, int, 0);
  108. MODULE_PARM_DESC(debug_level, "cpsw debug level (NETIF_MSG bits)");
  109. static int ale_ageout = 10;
  110. module_param(ale_ageout, int, 0);
  111. MODULE_PARM_DESC(ale_ageout, "cpsw ale ageout interval (seconds)");
  112. static int rx_packet_max = CPSW_MAX_PACKET_SIZE;
  113. module_param(rx_packet_max, int, 0);
  114. MODULE_PARM_DESC(rx_packet_max, "maximum receive packet size (bytes)");
  115. struct cpsw_wr_regs {
  116. u32 id_ver;
  117. u32 soft_reset;
  118. u32 control;
  119. u32 int_control;
  120. u32 rx_thresh_en;
  121. u32 rx_en;
  122. u32 tx_en;
  123. u32 misc_en;
  124. };
  125. struct cpsw_ss_regs {
  126. u32 id_ver;
  127. u32 control;
  128. u32 soft_reset;
  129. u32 stat_port_en;
  130. u32 ptype;
  131. u32 soft_idle;
  132. u32 thru_rate;
  133. u32 gap_thresh;
  134. u32 tx_start_wds;
  135. u32 flow_control;
  136. u32 vlan_ltype;
  137. u32 ts_ltype;
  138. u32 dlr_ltype;
  139. };
  140. struct cpsw_slave_regs {
  141. u32 max_blks;
  142. u32 blk_cnt;
  143. u32 flow_thresh;
  144. u32 port_vlan;
  145. u32 tx_pri_map;
  146. u32 ts_ctl;
  147. u32 ts_seq_ltype;
  148. u32 ts_vlan;
  149. u32 sa_lo;
  150. u32 sa_hi;
  151. };
  152. struct cpsw_host_regs {
  153. u32 max_blks;
  154. u32 blk_cnt;
  155. u32 flow_thresh;
  156. u32 port_vlan;
  157. u32 tx_pri_map;
  158. u32 cpdma_tx_pri_map;
  159. u32 cpdma_rx_chan_map;
  160. };
  161. struct cpsw_sliver_regs {
  162. u32 id_ver;
  163. u32 mac_control;
  164. u32 mac_status;
  165. u32 soft_reset;
  166. u32 rx_maxlen;
  167. u32 __reserved_0;
  168. u32 rx_pause;
  169. u32 tx_pause;
  170. u32 __reserved_1;
  171. u32 rx_pri_map;
  172. };
  173. struct cpsw_slave {
  174. struct cpsw_slave_regs __iomem *regs;
  175. struct cpsw_sliver_regs __iomem *sliver;
  176. int slave_num;
  177. u32 mac_control;
  178. struct cpsw_slave_data *data;
  179. struct phy_device *phy;
  180. };
  181. struct cpsw_priv {
  182. spinlock_t lock;
  183. struct platform_device *pdev;
  184. struct net_device *ndev;
  185. struct resource *cpsw_res;
  186. struct resource *cpsw_ss_res;
  187. struct napi_struct napi;
  188. struct device *dev;
  189. struct cpsw_platform_data data;
  190. struct cpsw_ss_regs __iomem *regs;
  191. struct cpsw_wr_regs __iomem *wr_regs;
  192. struct cpsw_host_regs __iomem *host_port_regs;
  193. u32 msg_enable;
  194. struct net_device_stats stats;
  195. int rx_packet_max;
  196. int host_port;
  197. struct clk *clk;
  198. u8 mac_addr[ETH_ALEN];
  199. struct cpsw_slave *slaves;
  200. struct cpdma_ctlr *dma;
  201. struct cpdma_chan *txch, *rxch;
  202. struct cpsw_ale *ale;
  203. /* snapshot of IRQ numbers */
  204. u32 irqs_table[4];
  205. u32 num_irqs;
  206. };
  207. #define napi_to_priv(napi) container_of(napi, struct cpsw_priv, napi)
  208. #define for_each_slave(priv, func, arg...) \
  209. do { \
  210. int idx; \
  211. for (idx = 0; idx < (priv)->data.slaves; idx++) \
  212. (func)((priv)->slaves + idx, ##arg); \
  213. } while (0)
  214. static void cpsw_ndo_set_rx_mode(struct net_device *ndev)
  215. {
  216. struct cpsw_priv *priv = netdev_priv(ndev);
  217. if (ndev->flags & IFF_PROMISC) {
  218. /* Enable promiscuous mode */
  219. dev_err(priv->dev, "Ignoring Promiscuous mode\n");
  220. return;
  221. }
  222. /* Clear all mcast from ALE */
  223. cpsw_ale_flush_multicast(priv->ale, ALE_ALL_PORTS << priv->host_port);
  224. if (!netdev_mc_empty(ndev)) {
  225. struct netdev_hw_addr *ha;
  226. /* program multicast address list into ALE register */
  227. netdev_for_each_mc_addr(ha, ndev) {
  228. cpsw_ale_add_mcast(priv->ale, (u8 *)ha->addr,
  229. ALE_ALL_PORTS << priv->host_port, 0, 0);
  230. }
  231. }
  232. }
  233. static void cpsw_intr_enable(struct cpsw_priv *priv)
  234. {
  235. __raw_writel(0xFF, &priv->wr_regs->tx_en);
  236. __raw_writel(0xFF, &priv->wr_regs->rx_en);
  237. cpdma_ctlr_int_ctrl(priv->dma, true);
  238. return;
  239. }
  240. static void cpsw_intr_disable(struct cpsw_priv *priv)
  241. {
  242. __raw_writel(0, &priv->wr_regs->tx_en);
  243. __raw_writel(0, &priv->wr_regs->rx_en);
  244. cpdma_ctlr_int_ctrl(priv->dma, false);
  245. return;
  246. }
  247. void cpsw_tx_handler(void *token, int len, int status)
  248. {
  249. struct sk_buff *skb = token;
  250. struct net_device *ndev = skb->dev;
  251. struct cpsw_priv *priv = netdev_priv(ndev);
  252. if (unlikely(netif_queue_stopped(ndev)))
  253. netif_start_queue(ndev);
  254. priv->stats.tx_packets++;
  255. priv->stats.tx_bytes += len;
  256. dev_kfree_skb_any(skb);
  257. }
  258. void cpsw_rx_handler(void *token, int len, int status)
  259. {
  260. struct sk_buff *skb = token;
  261. struct net_device *ndev = skb->dev;
  262. struct cpsw_priv *priv = netdev_priv(ndev);
  263. int ret = 0;
  264. /* free and bail if we are shutting down */
  265. if (unlikely(!netif_running(ndev)) ||
  266. unlikely(!netif_carrier_ok(ndev))) {
  267. dev_kfree_skb_any(skb);
  268. return;
  269. }
  270. if (likely(status >= 0)) {
  271. skb_put(skb, len);
  272. skb->protocol = eth_type_trans(skb, ndev);
  273. netif_receive_skb(skb);
  274. priv->stats.rx_bytes += len;
  275. priv->stats.rx_packets++;
  276. skb = NULL;
  277. }
  278. if (unlikely(!netif_running(ndev))) {
  279. if (skb)
  280. dev_kfree_skb_any(skb);
  281. return;
  282. }
  283. if (likely(!skb)) {
  284. skb = netdev_alloc_skb_ip_align(ndev, priv->rx_packet_max);
  285. if (WARN_ON(!skb))
  286. return;
  287. ret = cpdma_chan_submit(priv->rxch, skb, skb->data,
  288. skb_tailroom(skb), GFP_KERNEL);
  289. }
  290. WARN_ON(ret < 0);
  291. }
  292. static irqreturn_t cpsw_interrupt(int irq, void *dev_id)
  293. {
  294. struct cpsw_priv *priv = dev_id;
  295. if (likely(netif_running(priv->ndev))) {
  296. cpsw_intr_disable(priv);
  297. cpsw_disable_irq(priv);
  298. napi_schedule(&priv->napi);
  299. }
  300. return IRQ_HANDLED;
  301. }
  302. static inline int cpsw_get_slave_port(struct cpsw_priv *priv, u32 slave_num)
  303. {
  304. if (priv->host_port == 0)
  305. return slave_num + 1;
  306. else
  307. return slave_num;
  308. }
  309. static int cpsw_poll(struct napi_struct *napi, int budget)
  310. {
  311. struct cpsw_priv *priv = napi_to_priv(napi);
  312. int num_tx, num_rx;
  313. num_tx = cpdma_chan_process(priv->txch, 128);
  314. num_rx = cpdma_chan_process(priv->rxch, budget);
  315. if (num_rx || num_tx)
  316. cpsw_dbg(priv, intr, "poll %d rx, %d tx pkts\n",
  317. num_rx, num_tx);
  318. if (num_rx < budget) {
  319. napi_complete(napi);
  320. cpsw_intr_enable(priv);
  321. cpdma_ctlr_eoi(priv->dma);
  322. cpsw_enable_irq(priv);
  323. }
  324. return num_rx;
  325. }
  326. static inline void soft_reset(const char *module, void __iomem *reg)
  327. {
  328. unsigned long timeout = jiffies + HZ;
  329. __raw_writel(1, reg);
  330. do {
  331. cpu_relax();
  332. } while ((__raw_readl(reg) & 1) && time_after(timeout, jiffies));
  333. WARN(__raw_readl(reg) & 1, "failed to soft-reset %s\n", module);
  334. }
  335. #define mac_hi(mac) (((mac)[0] << 0) | ((mac)[1] << 8) | \
  336. ((mac)[2] << 16) | ((mac)[3] << 24))
  337. #define mac_lo(mac) (((mac)[4] << 0) | ((mac)[5] << 8))
  338. static void cpsw_set_slave_mac(struct cpsw_slave *slave,
  339. struct cpsw_priv *priv)
  340. {
  341. __raw_writel(mac_hi(priv->mac_addr), &slave->regs->sa_hi);
  342. __raw_writel(mac_lo(priv->mac_addr), &slave->regs->sa_lo);
  343. }
  344. static void _cpsw_adjust_link(struct cpsw_slave *slave,
  345. struct cpsw_priv *priv, bool *link)
  346. {
  347. struct phy_device *phy = slave->phy;
  348. u32 mac_control = 0;
  349. u32 slave_port;
  350. if (!phy)
  351. return;
  352. slave_port = cpsw_get_slave_port(priv, slave->slave_num);
  353. if (phy->link) {
  354. mac_control = priv->data.mac_control;
  355. /* enable forwarding */
  356. cpsw_ale_control_set(priv->ale, slave_port,
  357. ALE_PORT_STATE, ALE_PORT_STATE_FORWARD);
  358. if (phy->speed == 1000)
  359. mac_control |= BIT(7); /* GIGABITEN */
  360. if (phy->duplex)
  361. mac_control |= BIT(0); /* FULLDUPLEXEN */
  362. /* set speed_in input in case RMII mode is used in 100Mbps */
  363. if (phy->speed == 100)
  364. mac_control |= BIT(15);
  365. *link = true;
  366. } else {
  367. mac_control = 0;
  368. /* disable forwarding */
  369. cpsw_ale_control_set(priv->ale, slave_port,
  370. ALE_PORT_STATE, ALE_PORT_STATE_DISABLE);
  371. }
  372. if (mac_control != slave->mac_control) {
  373. phy_print_status(phy);
  374. __raw_writel(mac_control, &slave->sliver->mac_control);
  375. }
  376. slave->mac_control = mac_control;
  377. }
  378. static void cpsw_adjust_link(struct net_device *ndev)
  379. {
  380. struct cpsw_priv *priv = netdev_priv(ndev);
  381. bool link = false;
  382. for_each_slave(priv, _cpsw_adjust_link, priv, &link);
  383. if (link) {
  384. netif_carrier_on(ndev);
  385. if (netif_running(ndev))
  386. netif_wake_queue(ndev);
  387. } else {
  388. netif_carrier_off(ndev);
  389. netif_stop_queue(ndev);
  390. }
  391. }
  392. static inline int __show_stat(char *buf, int maxlen, const char *name, u32 val)
  393. {
  394. static char *leader = "........................................";
  395. if (!val)
  396. return 0;
  397. else
  398. return snprintf(buf, maxlen, "%s %s %10d\n", name,
  399. leader + strlen(name), val);
  400. }
  401. static void cpsw_slave_open(struct cpsw_slave *slave, struct cpsw_priv *priv)
  402. {
  403. char name[32];
  404. u32 slave_port;
  405. sprintf(name, "slave-%d", slave->slave_num);
  406. soft_reset(name, &slave->sliver->soft_reset);
  407. /* setup priority mapping */
  408. __raw_writel(RX_PRIORITY_MAPPING, &slave->sliver->rx_pri_map);
  409. __raw_writel(TX_PRIORITY_MAPPING, &slave->regs->tx_pri_map);
  410. /* setup max packet size, and mac address */
  411. __raw_writel(priv->rx_packet_max, &slave->sliver->rx_maxlen);
  412. cpsw_set_slave_mac(slave, priv);
  413. slave->mac_control = 0; /* no link yet */
  414. slave_port = cpsw_get_slave_port(priv, slave->slave_num);
  415. cpsw_ale_add_mcast(priv->ale, priv->ndev->broadcast,
  416. 1 << slave_port, 0, ALE_MCAST_FWD_2);
  417. slave->phy = phy_connect(priv->ndev, slave->data->phy_id,
  418. &cpsw_adjust_link, 0, slave->data->phy_if);
  419. if (IS_ERR(slave->phy)) {
  420. dev_err(priv->dev, "phy %s not found on slave %d\n",
  421. slave->data->phy_id, slave->slave_num);
  422. slave->phy = NULL;
  423. } else {
  424. dev_info(priv->dev, "phy found : id is : 0x%x\n",
  425. slave->phy->phy_id);
  426. phy_start(slave->phy);
  427. }
  428. }
  429. static void cpsw_init_host_port(struct cpsw_priv *priv)
  430. {
  431. /* soft reset the controller and initialize ale */
  432. soft_reset("cpsw", &priv->regs->soft_reset);
  433. cpsw_ale_start(priv->ale);
  434. /* switch to vlan unaware mode */
  435. cpsw_ale_control_set(priv->ale, 0, ALE_VLAN_AWARE, 0);
  436. /* setup host port priority mapping */
  437. __raw_writel(CPDMA_TX_PRIORITY_MAP,
  438. &priv->host_port_regs->cpdma_tx_pri_map);
  439. __raw_writel(0, &priv->host_port_regs->cpdma_rx_chan_map);
  440. cpsw_ale_control_set(priv->ale, priv->host_port,
  441. ALE_PORT_STATE, ALE_PORT_STATE_FORWARD);
  442. cpsw_ale_add_ucast(priv->ale, priv->mac_addr, priv->host_port, 0);
  443. cpsw_ale_add_mcast(priv->ale, priv->ndev->broadcast,
  444. 1 << priv->host_port, 0, ALE_MCAST_FWD_2);
  445. }
  446. static int cpsw_ndo_open(struct net_device *ndev)
  447. {
  448. struct cpsw_priv *priv = netdev_priv(ndev);
  449. int i, ret;
  450. u32 reg;
  451. cpsw_intr_disable(priv);
  452. netif_carrier_off(ndev);
  453. pm_runtime_get_sync(&priv->pdev->dev);
  454. reg = __raw_readl(&priv->regs->id_ver);
  455. dev_info(priv->dev, "initializing cpsw version %d.%d (%d)\n",
  456. CPSW_MAJOR_VERSION(reg), CPSW_MINOR_VERSION(reg),
  457. CPSW_RTL_VERSION(reg));
  458. /* initialize host and slave ports */
  459. cpsw_init_host_port(priv);
  460. for_each_slave(priv, cpsw_slave_open, priv);
  461. /* setup tx dma to fixed prio and zero offset */
  462. cpdma_control_set(priv->dma, CPDMA_TX_PRIO_FIXED, 1);
  463. cpdma_control_set(priv->dma, CPDMA_RX_BUFFER_OFFSET, 0);
  464. /* disable priority elevation and enable statistics on all ports */
  465. __raw_writel(0, &priv->regs->ptype);
  466. /* enable statistics collection only on the host port */
  467. __raw_writel(0x7, &priv->regs->stat_port_en);
  468. if (WARN_ON(!priv->data.rx_descs))
  469. priv->data.rx_descs = 128;
  470. for (i = 0; i < priv->data.rx_descs; i++) {
  471. struct sk_buff *skb;
  472. ret = -ENOMEM;
  473. skb = netdev_alloc_skb_ip_align(priv->ndev,
  474. priv->rx_packet_max);
  475. if (!skb)
  476. break;
  477. ret = cpdma_chan_submit(priv->rxch, skb, skb->data,
  478. skb_tailroom(skb), GFP_KERNEL);
  479. if (WARN_ON(ret < 0))
  480. break;
  481. }
  482. /* continue even if we didn't manage to submit all receive descs */
  483. cpsw_info(priv, ifup, "submitted %d rx descriptors\n", i);
  484. cpdma_ctlr_start(priv->dma);
  485. cpsw_intr_enable(priv);
  486. napi_enable(&priv->napi);
  487. cpdma_ctlr_eoi(priv->dma);
  488. return 0;
  489. }
  490. static void cpsw_slave_stop(struct cpsw_slave *slave, struct cpsw_priv *priv)
  491. {
  492. if (!slave->phy)
  493. return;
  494. phy_stop(slave->phy);
  495. phy_disconnect(slave->phy);
  496. slave->phy = NULL;
  497. }
  498. static int cpsw_ndo_stop(struct net_device *ndev)
  499. {
  500. struct cpsw_priv *priv = netdev_priv(ndev);
  501. cpsw_info(priv, ifdown, "shutting down cpsw device\n");
  502. cpsw_intr_disable(priv);
  503. cpdma_ctlr_int_ctrl(priv->dma, false);
  504. cpdma_ctlr_stop(priv->dma);
  505. netif_stop_queue(priv->ndev);
  506. napi_disable(&priv->napi);
  507. netif_carrier_off(priv->ndev);
  508. cpsw_ale_stop(priv->ale);
  509. for_each_slave(priv, cpsw_slave_stop, priv);
  510. pm_runtime_put_sync(&priv->pdev->dev);
  511. return 0;
  512. }
  513. static netdev_tx_t cpsw_ndo_start_xmit(struct sk_buff *skb,
  514. struct net_device *ndev)
  515. {
  516. struct cpsw_priv *priv = netdev_priv(ndev);
  517. int ret;
  518. ndev->trans_start = jiffies;
  519. if (skb_padto(skb, CPSW_MIN_PACKET_SIZE)) {
  520. cpsw_err(priv, tx_err, "packet pad failed\n");
  521. priv->stats.tx_dropped++;
  522. return NETDEV_TX_OK;
  523. }
  524. ret = cpdma_chan_submit(priv->txch, skb, skb->data,
  525. skb->len, GFP_KERNEL);
  526. if (unlikely(ret != 0)) {
  527. cpsw_err(priv, tx_err, "desc submit failed\n");
  528. goto fail;
  529. }
  530. return NETDEV_TX_OK;
  531. fail:
  532. priv->stats.tx_dropped++;
  533. netif_stop_queue(ndev);
  534. return NETDEV_TX_BUSY;
  535. }
  536. static void cpsw_ndo_change_rx_flags(struct net_device *ndev, int flags)
  537. {
  538. /*
  539. * The switch cannot operate in promiscuous mode without substantial
  540. * headache. For promiscuous mode to work, we would need to put the
  541. * ALE in bypass mode and route all traffic to the host port.
  542. * Subsequently, the host will need to operate as a "bridge", learn,
  543. * and flood as needed. For now, we simply complain here and
  544. * do nothing about it :-)
  545. */
  546. if ((flags & IFF_PROMISC) && (ndev->flags & IFF_PROMISC))
  547. dev_err(&ndev->dev, "promiscuity ignored!\n");
  548. /*
  549. * The switch cannot filter multicast traffic unless it is configured
  550. * in "VLAN Aware" mode. Unfortunately, VLAN awareness requires a
  551. * whole bunch of additional logic that this driver does not implement
  552. * at present.
  553. */
  554. if ((flags & IFF_ALLMULTI) && !(ndev->flags & IFF_ALLMULTI))
  555. dev_err(&ndev->dev, "multicast traffic cannot be filtered!\n");
  556. }
  557. static void cpsw_ndo_tx_timeout(struct net_device *ndev)
  558. {
  559. struct cpsw_priv *priv = netdev_priv(ndev);
  560. cpsw_err(priv, tx_err, "transmit timeout, restarting dma\n");
  561. priv->stats.tx_errors++;
  562. cpsw_intr_disable(priv);
  563. cpdma_ctlr_int_ctrl(priv->dma, false);
  564. cpdma_chan_stop(priv->txch);
  565. cpdma_chan_start(priv->txch);
  566. cpdma_ctlr_int_ctrl(priv->dma, true);
  567. cpsw_intr_enable(priv);
  568. cpdma_ctlr_eoi(priv->dma);
  569. }
  570. static struct net_device_stats *cpsw_ndo_get_stats(struct net_device *ndev)
  571. {
  572. struct cpsw_priv *priv = netdev_priv(ndev);
  573. return &priv->stats;
  574. }
  575. #ifdef CONFIG_NET_POLL_CONTROLLER
  576. static void cpsw_ndo_poll_controller(struct net_device *ndev)
  577. {
  578. struct cpsw_priv *priv = netdev_priv(ndev);
  579. cpsw_intr_disable(priv);
  580. cpdma_ctlr_int_ctrl(priv->dma, false);
  581. cpsw_interrupt(ndev->irq, priv);
  582. cpdma_ctlr_int_ctrl(priv->dma, true);
  583. cpsw_intr_enable(priv);
  584. cpdma_ctlr_eoi(priv->dma);
  585. }
  586. #endif
  587. static const struct net_device_ops cpsw_netdev_ops = {
  588. .ndo_open = cpsw_ndo_open,
  589. .ndo_stop = cpsw_ndo_stop,
  590. .ndo_start_xmit = cpsw_ndo_start_xmit,
  591. .ndo_change_rx_flags = cpsw_ndo_change_rx_flags,
  592. .ndo_validate_addr = eth_validate_addr,
  593. .ndo_change_mtu = eth_change_mtu,
  594. .ndo_tx_timeout = cpsw_ndo_tx_timeout,
  595. .ndo_get_stats = cpsw_ndo_get_stats,
  596. .ndo_set_rx_mode = cpsw_ndo_set_rx_mode,
  597. #ifdef CONFIG_NET_POLL_CONTROLLER
  598. .ndo_poll_controller = cpsw_ndo_poll_controller,
  599. #endif
  600. };
  601. static void cpsw_get_drvinfo(struct net_device *ndev,
  602. struct ethtool_drvinfo *info)
  603. {
  604. struct cpsw_priv *priv = netdev_priv(ndev);
  605. strcpy(info->driver, "TI CPSW Driver v1.0");
  606. strcpy(info->version, "1.0");
  607. strcpy(info->bus_info, priv->pdev->name);
  608. }
  609. static u32 cpsw_get_msglevel(struct net_device *ndev)
  610. {
  611. struct cpsw_priv *priv = netdev_priv(ndev);
  612. return priv->msg_enable;
  613. }
  614. static void cpsw_set_msglevel(struct net_device *ndev, u32 value)
  615. {
  616. struct cpsw_priv *priv = netdev_priv(ndev);
  617. priv->msg_enable = value;
  618. }
  619. static const struct ethtool_ops cpsw_ethtool_ops = {
  620. .get_drvinfo = cpsw_get_drvinfo,
  621. .get_msglevel = cpsw_get_msglevel,
  622. .set_msglevel = cpsw_set_msglevel,
  623. .get_link = ethtool_op_get_link,
  624. };
  625. static void cpsw_slave_init(struct cpsw_slave *slave, struct cpsw_priv *priv)
  626. {
  627. void __iomem *regs = priv->regs;
  628. int slave_num = slave->slave_num;
  629. struct cpsw_slave_data *data = priv->data.slave_data + slave_num;
  630. slave->data = data;
  631. slave->regs = regs + data->slave_reg_ofs;
  632. slave->sliver = regs + data->sliver_reg_ofs;
  633. }
  634. static int cpsw_probe_dt(struct cpsw_platform_data *data,
  635. struct platform_device *pdev)
  636. {
  637. struct device_node *node = pdev->dev.of_node;
  638. struct device_node *slave_node;
  639. int i = 0, ret;
  640. u32 prop;
  641. if (!node)
  642. return -EINVAL;
  643. if (of_property_read_u32(node, "slaves", &prop)) {
  644. pr_err("Missing slaves property in the DT.\n");
  645. return -EINVAL;
  646. }
  647. data->slaves = prop;
  648. data->slave_data = kzalloc(sizeof(struct cpsw_slave_data) *
  649. data->slaves, GFP_KERNEL);
  650. if (!data->slave_data) {
  651. pr_err("Could not allocate slave memory.\n");
  652. return -EINVAL;
  653. }
  654. data->no_bd_ram = of_property_read_bool(node, "no_bd_ram");
  655. if (of_property_read_u32(node, "cpdma_channels", &prop)) {
  656. pr_err("Missing cpdma_channels property in the DT.\n");
  657. ret = -EINVAL;
  658. goto error_ret;
  659. }
  660. data->channels = prop;
  661. if (of_property_read_u32(node, "host_port_no", &prop)) {
  662. pr_err("Missing host_port_no property in the DT.\n");
  663. ret = -EINVAL;
  664. goto error_ret;
  665. }
  666. data->host_port_num = prop;
  667. if (of_property_read_u32(node, "cpdma_reg_ofs", &prop)) {
  668. pr_err("Missing cpdma_reg_ofs property in the DT.\n");
  669. ret = -EINVAL;
  670. goto error_ret;
  671. }
  672. data->cpdma_reg_ofs = prop;
  673. if (of_property_read_u32(node, "cpdma_sram_ofs", &prop)) {
  674. pr_err("Missing cpdma_sram_ofs property in the DT.\n");
  675. ret = -EINVAL;
  676. goto error_ret;
  677. }
  678. data->cpdma_sram_ofs = prop;
  679. if (of_property_read_u32(node, "ale_reg_ofs", &prop)) {
  680. pr_err("Missing ale_reg_ofs property in the DT.\n");
  681. ret = -EINVAL;
  682. goto error_ret;
  683. }
  684. data->ale_reg_ofs = prop;
  685. if (of_property_read_u32(node, "ale_entries", &prop)) {
  686. pr_err("Missing ale_entries property in the DT.\n");
  687. ret = -EINVAL;
  688. goto error_ret;
  689. }
  690. data->ale_entries = prop;
  691. if (of_property_read_u32(node, "host_port_reg_ofs", &prop)) {
  692. pr_err("Missing host_port_reg_ofs property in the DT.\n");
  693. ret = -EINVAL;
  694. goto error_ret;
  695. }
  696. data->host_port_reg_ofs = prop;
  697. if (of_property_read_u32(node, "hw_stats_reg_ofs", &prop)) {
  698. pr_err("Missing hw_stats_reg_ofs property in the DT.\n");
  699. ret = -EINVAL;
  700. goto error_ret;
  701. }
  702. data->hw_stats_reg_ofs = prop;
  703. if (of_property_read_u32(node, "bd_ram_ofs", &prop)) {
  704. pr_err("Missing bd_ram_ofs property in the DT.\n");
  705. ret = -EINVAL;
  706. goto error_ret;
  707. }
  708. data->bd_ram_ofs = prop;
  709. if (of_property_read_u32(node, "bd_ram_size", &prop)) {
  710. pr_err("Missing bd_ram_size property in the DT.\n");
  711. ret = -EINVAL;
  712. goto error_ret;
  713. }
  714. data->bd_ram_size = prop;
  715. if (of_property_read_u32(node, "rx_descs", &prop)) {
  716. pr_err("Missing rx_descs property in the DT.\n");
  717. ret = -EINVAL;
  718. goto error_ret;
  719. }
  720. data->rx_descs = prop;
  721. if (of_property_read_u32(node, "mac_control", &prop)) {
  722. pr_err("Missing mac_control property in the DT.\n");
  723. ret = -EINVAL;
  724. goto error_ret;
  725. }
  726. data->mac_control = prop;
  727. for_each_child_of_node(node, slave_node) {
  728. struct cpsw_slave_data *slave_data = data->slave_data + i;
  729. const char *phy_id = NULL;
  730. const void *mac_addr = NULL;
  731. if (of_property_read_string(slave_node, "phy_id", &phy_id)) {
  732. pr_err("Missing slave[%d] phy_id property\n", i);
  733. ret = -EINVAL;
  734. goto error_ret;
  735. }
  736. slave_data->phy_id = phy_id;
  737. if (of_property_read_u32(slave_node, "slave_reg_ofs", &prop)) {
  738. pr_err("Missing slave[%d] slave_reg_ofs property\n", i);
  739. ret = -EINVAL;
  740. goto error_ret;
  741. }
  742. slave_data->slave_reg_ofs = prop;
  743. if (of_property_read_u32(slave_node, "sliver_reg_ofs",
  744. &prop)) {
  745. pr_err("Missing slave[%d] sliver_reg_ofs property\n",
  746. i);
  747. ret = -EINVAL;
  748. goto error_ret;
  749. }
  750. slave_data->sliver_reg_ofs = prop;
  751. mac_addr = of_get_mac_address(slave_node);
  752. if (mac_addr)
  753. memcpy(slave_data->mac_addr, mac_addr, ETH_ALEN);
  754. i++;
  755. }
  756. return 0;
  757. error_ret:
  758. kfree(data->slave_data);
  759. return ret;
  760. }
  761. static int __devinit cpsw_probe(struct platform_device *pdev)
  762. {
  763. struct cpsw_platform_data *data = pdev->dev.platform_data;
  764. struct net_device *ndev;
  765. struct cpsw_priv *priv;
  766. struct cpdma_params dma_params;
  767. struct cpsw_ale_params ale_params;
  768. void __iomem *regs;
  769. struct resource *res;
  770. int ret = 0, i, k = 0;
  771. ndev = alloc_etherdev(sizeof(struct cpsw_priv));
  772. if (!ndev) {
  773. pr_err("error allocating net_device\n");
  774. return -ENOMEM;
  775. }
  776. platform_set_drvdata(pdev, ndev);
  777. priv = netdev_priv(ndev);
  778. spin_lock_init(&priv->lock);
  779. priv->pdev = pdev;
  780. priv->ndev = ndev;
  781. priv->dev = &ndev->dev;
  782. priv->msg_enable = netif_msg_init(debug_level, CPSW_DEBUG);
  783. priv->rx_packet_max = max(rx_packet_max, 128);
  784. if (cpsw_probe_dt(&priv->data, pdev)) {
  785. pr_err("cpsw: platform data missing\n");
  786. ret = -ENODEV;
  787. goto clean_ndev_ret;
  788. }
  789. data = &priv->data;
  790. if (is_valid_ether_addr(data->slave_data[0].mac_addr)) {
  791. memcpy(priv->mac_addr, data->slave_data[0].mac_addr, ETH_ALEN);
  792. pr_info("Detected MACID = %pM", priv->mac_addr);
  793. } else {
  794. eth_random_addr(priv->mac_addr);
  795. pr_info("Random MACID = %pM", priv->mac_addr);
  796. }
  797. memcpy(ndev->dev_addr, priv->mac_addr, ETH_ALEN);
  798. priv->slaves = kzalloc(sizeof(struct cpsw_slave) * data->slaves,
  799. GFP_KERNEL);
  800. if (!priv->slaves) {
  801. ret = -EBUSY;
  802. goto clean_ndev_ret;
  803. }
  804. for (i = 0; i < data->slaves; i++)
  805. priv->slaves[i].slave_num = i;
  806. pm_runtime_enable(&pdev->dev);
  807. priv->clk = clk_get(&pdev->dev, "fck");
  808. if (IS_ERR(priv->clk)) {
  809. dev_err(&pdev->dev, "fck is not found\n");
  810. ret = -ENODEV;
  811. goto clean_slave_ret;
  812. }
  813. priv->cpsw_res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
  814. if (!priv->cpsw_res) {
  815. dev_err(priv->dev, "error getting i/o resource\n");
  816. ret = -ENOENT;
  817. goto clean_clk_ret;
  818. }
  819. if (!request_mem_region(priv->cpsw_res->start,
  820. resource_size(priv->cpsw_res), ndev->name)) {
  821. dev_err(priv->dev, "failed request i/o region\n");
  822. ret = -ENXIO;
  823. goto clean_clk_ret;
  824. }
  825. regs = ioremap(priv->cpsw_res->start, resource_size(priv->cpsw_res));
  826. if (!regs) {
  827. dev_err(priv->dev, "unable to map i/o region\n");
  828. goto clean_cpsw_iores_ret;
  829. }
  830. priv->regs = regs;
  831. priv->host_port = data->host_port_num;
  832. priv->host_port_regs = regs + data->host_port_reg_ofs;
  833. priv->cpsw_ss_res = platform_get_resource(pdev, IORESOURCE_MEM, 1);
  834. if (!priv->cpsw_ss_res) {
  835. dev_err(priv->dev, "error getting i/o resource\n");
  836. ret = -ENOENT;
  837. goto clean_clk_ret;
  838. }
  839. if (!request_mem_region(priv->cpsw_ss_res->start,
  840. resource_size(priv->cpsw_ss_res), ndev->name)) {
  841. dev_err(priv->dev, "failed request i/o region\n");
  842. ret = -ENXIO;
  843. goto clean_clk_ret;
  844. }
  845. regs = ioremap(priv->cpsw_ss_res->start,
  846. resource_size(priv->cpsw_ss_res));
  847. if (!regs) {
  848. dev_err(priv->dev, "unable to map i/o region\n");
  849. goto clean_cpsw_ss_iores_ret;
  850. }
  851. priv->wr_regs = regs;
  852. for_each_slave(priv, cpsw_slave_init, priv);
  853. memset(&dma_params, 0, sizeof(dma_params));
  854. dma_params.dev = &pdev->dev;
  855. dma_params.dmaregs = cpsw_dma_regs((u32)priv->regs,
  856. data->cpdma_reg_ofs);
  857. dma_params.rxthresh = cpsw_dma_rxthresh((u32)priv->regs,
  858. data->cpdma_reg_ofs);
  859. dma_params.rxfree = cpsw_dma_rxfree((u32)priv->regs,
  860. data->cpdma_reg_ofs);
  861. dma_params.txhdp = cpsw_dma_txhdp((u32)priv->regs,
  862. data->cpdma_sram_ofs);
  863. dma_params.rxhdp = cpsw_dma_rxhdp((u32)priv->regs,
  864. data->cpdma_sram_ofs);
  865. dma_params.txcp = cpsw_dma_txcp((u32)priv->regs,
  866. data->cpdma_sram_ofs);
  867. dma_params.rxcp = cpsw_dma_rxcp((u32)priv->regs,
  868. data->cpdma_sram_ofs);
  869. dma_params.num_chan = data->channels;
  870. dma_params.has_soft_reset = true;
  871. dma_params.min_packet_size = CPSW_MIN_PACKET_SIZE;
  872. dma_params.desc_mem_size = data->bd_ram_size;
  873. dma_params.desc_align = 16;
  874. dma_params.has_ext_regs = true;
  875. dma_params.desc_mem_phys = data->no_bd_ram ? 0 :
  876. (u32 __force)priv->cpsw_res->start + data->bd_ram_ofs;
  877. dma_params.desc_hw_addr = data->hw_ram_addr ?
  878. data->hw_ram_addr : dma_params.desc_mem_phys ;
  879. priv->dma = cpdma_ctlr_create(&dma_params);
  880. if (!priv->dma) {
  881. dev_err(priv->dev, "error initializing dma\n");
  882. ret = -ENOMEM;
  883. goto clean_iomap_ret;
  884. }
  885. priv->txch = cpdma_chan_create(priv->dma, tx_chan_num(0),
  886. cpsw_tx_handler);
  887. priv->rxch = cpdma_chan_create(priv->dma, rx_chan_num(0),
  888. cpsw_rx_handler);
  889. if (WARN_ON(!priv->txch || !priv->rxch)) {
  890. dev_err(priv->dev, "error initializing dma channels\n");
  891. ret = -ENOMEM;
  892. goto clean_dma_ret;
  893. }
  894. memset(&ale_params, 0, sizeof(ale_params));
  895. ale_params.dev = &ndev->dev;
  896. ale_params.ale_regs = (void *)((u32)priv->regs) +
  897. ((u32)data->ale_reg_ofs);
  898. ale_params.ale_ageout = ale_ageout;
  899. ale_params.ale_entries = data->ale_entries;
  900. ale_params.ale_ports = data->slaves;
  901. priv->ale = cpsw_ale_create(&ale_params);
  902. if (!priv->ale) {
  903. dev_err(priv->dev, "error initializing ale engine\n");
  904. ret = -ENODEV;
  905. goto clean_dma_ret;
  906. }
  907. ndev->irq = platform_get_irq(pdev, 0);
  908. if (ndev->irq < 0) {
  909. dev_err(priv->dev, "error getting irq resource\n");
  910. ret = -ENOENT;
  911. goto clean_ale_ret;
  912. }
  913. while ((res = platform_get_resource(priv->pdev, IORESOURCE_IRQ, k))) {
  914. for (i = res->start; i <= res->end; i++) {
  915. if (request_irq(i, cpsw_interrupt, IRQF_DISABLED,
  916. dev_name(&pdev->dev), priv)) {
  917. dev_err(priv->dev, "error attaching irq\n");
  918. goto clean_ale_ret;
  919. }
  920. priv->irqs_table[k] = i;
  921. priv->num_irqs = k;
  922. }
  923. k++;
  924. }
  925. ndev->flags |= IFF_ALLMULTI; /* see cpsw_ndo_change_rx_flags() */
  926. ndev->netdev_ops = &cpsw_netdev_ops;
  927. SET_ETHTOOL_OPS(ndev, &cpsw_ethtool_ops);
  928. netif_napi_add(ndev, &priv->napi, cpsw_poll, CPSW_POLL_WEIGHT);
  929. /* register the network device */
  930. SET_NETDEV_DEV(ndev, &pdev->dev);
  931. ret = register_netdev(ndev);
  932. if (ret) {
  933. dev_err(priv->dev, "error registering net device\n");
  934. ret = -ENODEV;
  935. goto clean_irq_ret;
  936. }
  937. cpsw_notice(priv, probe, "initialized device (regs %x, irq %d)\n",
  938. priv->cpsw_res->start, ndev->irq);
  939. return 0;
  940. clean_irq_ret:
  941. free_irq(ndev->irq, priv);
  942. clean_ale_ret:
  943. cpsw_ale_destroy(priv->ale);
  944. clean_dma_ret:
  945. cpdma_chan_destroy(priv->txch);
  946. cpdma_chan_destroy(priv->rxch);
  947. cpdma_ctlr_destroy(priv->dma);
  948. clean_iomap_ret:
  949. iounmap(priv->regs);
  950. clean_cpsw_ss_iores_ret:
  951. release_mem_region(priv->cpsw_ss_res->start,
  952. resource_size(priv->cpsw_ss_res));
  953. clean_cpsw_iores_ret:
  954. release_mem_region(priv->cpsw_res->start,
  955. resource_size(priv->cpsw_res));
  956. clean_clk_ret:
  957. clk_put(priv->clk);
  958. clean_slave_ret:
  959. pm_runtime_disable(&pdev->dev);
  960. kfree(priv->slaves);
  961. clean_ndev_ret:
  962. free_netdev(ndev);
  963. return ret;
  964. }
  965. static int __devexit cpsw_remove(struct platform_device *pdev)
  966. {
  967. struct net_device *ndev = platform_get_drvdata(pdev);
  968. struct cpsw_priv *priv = netdev_priv(ndev);
  969. pr_info("removing device");
  970. platform_set_drvdata(pdev, NULL);
  971. free_irq(ndev->irq, priv);
  972. cpsw_ale_destroy(priv->ale);
  973. cpdma_chan_destroy(priv->txch);
  974. cpdma_chan_destroy(priv->rxch);
  975. cpdma_ctlr_destroy(priv->dma);
  976. iounmap(priv->regs);
  977. release_mem_region(priv->cpsw_res->start,
  978. resource_size(priv->cpsw_res));
  979. release_mem_region(priv->cpsw_ss_res->start,
  980. resource_size(priv->cpsw_ss_res));
  981. pm_runtime_disable(&pdev->dev);
  982. clk_put(priv->clk);
  983. kfree(priv->slaves);
  984. free_netdev(ndev);
  985. return 0;
  986. }
  987. static int cpsw_suspend(struct device *dev)
  988. {
  989. struct platform_device *pdev = to_platform_device(dev);
  990. struct net_device *ndev = platform_get_drvdata(pdev);
  991. if (netif_running(ndev))
  992. cpsw_ndo_stop(ndev);
  993. pm_runtime_put_sync(&pdev->dev);
  994. return 0;
  995. }
  996. static int cpsw_resume(struct device *dev)
  997. {
  998. struct platform_device *pdev = to_platform_device(dev);
  999. struct net_device *ndev = platform_get_drvdata(pdev);
  1000. pm_runtime_get_sync(&pdev->dev);
  1001. if (netif_running(ndev))
  1002. cpsw_ndo_open(ndev);
  1003. return 0;
  1004. }
  1005. static const struct dev_pm_ops cpsw_pm_ops = {
  1006. .suspend = cpsw_suspend,
  1007. .resume = cpsw_resume,
  1008. };
  1009. static const struct of_device_id cpsw_of_mtable[] = {
  1010. { .compatible = "ti,cpsw", },
  1011. { /* sentinel */ },
  1012. };
  1013. static struct platform_driver cpsw_driver = {
  1014. .driver = {
  1015. .name = "cpsw",
  1016. .owner = THIS_MODULE,
  1017. .pm = &cpsw_pm_ops,
  1018. .of_match_table = of_match_ptr(cpsw_of_mtable),
  1019. },
  1020. .probe = cpsw_probe,
  1021. .remove = __devexit_p(cpsw_remove),
  1022. };
  1023. static int __init cpsw_init(void)
  1024. {
  1025. return platform_driver_register(&cpsw_driver);
  1026. }
  1027. late_initcall(cpsw_init);
  1028. static void __exit cpsw_exit(void)
  1029. {
  1030. platform_driver_unregister(&cpsw_driver);
  1031. }
  1032. module_exit(cpsw_exit);
  1033. MODULE_LICENSE("GPL");
  1034. MODULE_AUTHOR("Cyril Chemparathy <cyril@ti.com>");
  1035. MODULE_AUTHOR("Mugunthan V N <mugunthanvnm@ti.com>");
  1036. MODULE_DESCRIPTION("TI CPSW Ethernet driver");