common.c 27 KB

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  1. #include <linux/init.h>
  2. #include <linux/kernel.h>
  3. #include <linux/sched.h>
  4. #include <linux/string.h>
  5. #include <linux/bootmem.h>
  6. #include <linux/bitops.h>
  7. #include <linux/module.h>
  8. #include <linux/kgdb.h>
  9. #include <linux/topology.h>
  10. #include <linux/delay.h>
  11. #include <linux/smp.h>
  12. #include <linux/percpu.h>
  13. #include <asm/i387.h>
  14. #include <asm/msr.h>
  15. #include <asm/io.h>
  16. #include <asm/linkage.h>
  17. #include <asm/mmu_context.h>
  18. #include <asm/mtrr.h>
  19. #include <asm/mce.h>
  20. #include <asm/pat.h>
  21. #include <asm/asm.h>
  22. #include <asm/numa.h>
  23. #ifdef CONFIG_X86_LOCAL_APIC
  24. #include <asm/mpspec.h>
  25. #include <asm/apic.h>
  26. #include <mach_apic.h>
  27. #include <asm/genapic.h>
  28. #endif
  29. #include <asm/pda.h>
  30. #include <asm/pgtable.h>
  31. #include <asm/processor.h>
  32. #include <asm/desc.h>
  33. #include <asm/atomic.h>
  34. #include <asm/proto.h>
  35. #include <asm/sections.h>
  36. #include <asm/setup.h>
  37. #include "cpu.h"
  38. static struct cpu_dev *this_cpu __cpuinitdata;
  39. #ifdef CONFIG_X86_64
  40. /* We need valid kernel segments for data and code in long mode too
  41. * IRET will check the segment types kkeil 2000/10/28
  42. * Also sysret mandates a special GDT layout
  43. */
  44. /* The TLS descriptors are currently at a different place compared to i386.
  45. Hopefully nobody expects them at a fixed place (Wine?) */
  46. DEFINE_PER_CPU(struct gdt_page, gdt_page) = { .gdt = {
  47. [GDT_ENTRY_KERNEL32_CS] = { { { 0x0000ffff, 0x00cf9b00 } } },
  48. [GDT_ENTRY_KERNEL_CS] = { { { 0x0000ffff, 0x00af9b00 } } },
  49. [GDT_ENTRY_KERNEL_DS] = { { { 0x0000ffff, 0x00cf9300 } } },
  50. [GDT_ENTRY_DEFAULT_USER32_CS] = { { { 0x0000ffff, 0x00cffb00 } } },
  51. [GDT_ENTRY_DEFAULT_USER_DS] = { { { 0x0000ffff, 0x00cff300 } } },
  52. [GDT_ENTRY_DEFAULT_USER_CS] = { { { 0x0000ffff, 0x00affb00 } } },
  53. } };
  54. #else
  55. DEFINE_PER_CPU_PAGE_ALIGNED(struct gdt_page, gdt_page) = { .gdt = {
  56. [GDT_ENTRY_KERNEL_CS] = { { { 0x0000ffff, 0x00cf9a00 } } },
  57. [GDT_ENTRY_KERNEL_DS] = { { { 0x0000ffff, 0x00cf9200 } } },
  58. [GDT_ENTRY_DEFAULT_USER_CS] = { { { 0x0000ffff, 0x00cffa00 } } },
  59. [GDT_ENTRY_DEFAULT_USER_DS] = { { { 0x0000ffff, 0x00cff200 } } },
  60. /*
  61. * Segments used for calling PnP BIOS have byte granularity.
  62. * They code segments and data segments have fixed 64k limits,
  63. * the transfer segment sizes are set at run time.
  64. */
  65. /* 32-bit code */
  66. [GDT_ENTRY_PNPBIOS_CS32] = { { { 0x0000ffff, 0x00409a00 } } },
  67. /* 16-bit code */
  68. [GDT_ENTRY_PNPBIOS_CS16] = { { { 0x0000ffff, 0x00009a00 } } },
  69. /* 16-bit data */
  70. [GDT_ENTRY_PNPBIOS_DS] = { { { 0x0000ffff, 0x00009200 } } },
  71. /* 16-bit data */
  72. [GDT_ENTRY_PNPBIOS_TS1] = { { { 0x00000000, 0x00009200 } } },
  73. /* 16-bit data */
  74. [GDT_ENTRY_PNPBIOS_TS2] = { { { 0x00000000, 0x00009200 } } },
  75. /*
  76. * The APM segments have byte granularity and their bases
  77. * are set at run time. All have 64k limits.
  78. */
  79. /* 32-bit code */
  80. [GDT_ENTRY_APMBIOS_BASE] = { { { 0x0000ffff, 0x00409a00 } } },
  81. /* 16-bit code */
  82. [GDT_ENTRY_APMBIOS_BASE+1] = { { { 0x0000ffff, 0x00009a00 } } },
  83. /* data */
  84. [GDT_ENTRY_APMBIOS_BASE+2] = { { { 0x0000ffff, 0x00409200 } } },
  85. [GDT_ENTRY_ESPFIX_SS] = { { { 0x00000000, 0x00c09200 } } },
  86. [GDT_ENTRY_PERCPU] = { { { 0x00000000, 0x00000000 } } },
  87. } };
  88. #endif
  89. EXPORT_PER_CPU_SYMBOL_GPL(gdt_page);
  90. #ifdef CONFIG_X86_32
  91. static int cachesize_override __cpuinitdata = -1;
  92. static int disable_x86_serial_nr __cpuinitdata = 1;
  93. static int __init cachesize_setup(char *str)
  94. {
  95. get_option(&str, &cachesize_override);
  96. return 1;
  97. }
  98. __setup("cachesize=", cachesize_setup);
  99. static int __init x86_fxsr_setup(char *s)
  100. {
  101. setup_clear_cpu_cap(X86_FEATURE_FXSR);
  102. setup_clear_cpu_cap(X86_FEATURE_XMM);
  103. return 1;
  104. }
  105. __setup("nofxsr", x86_fxsr_setup);
  106. static int __init x86_sep_setup(char *s)
  107. {
  108. setup_clear_cpu_cap(X86_FEATURE_SEP);
  109. return 1;
  110. }
  111. __setup("nosep", x86_sep_setup);
  112. /* Standard macro to see if a specific flag is changeable */
  113. static inline int flag_is_changeable_p(u32 flag)
  114. {
  115. u32 f1, f2;
  116. asm("pushfl\n\t"
  117. "pushfl\n\t"
  118. "popl %0\n\t"
  119. "movl %0,%1\n\t"
  120. "xorl %2,%0\n\t"
  121. "pushl %0\n\t"
  122. "popfl\n\t"
  123. "pushfl\n\t"
  124. "popl %0\n\t"
  125. "popfl\n\t"
  126. : "=&r" (f1), "=&r" (f2)
  127. : "ir" (flag));
  128. return ((f1^f2) & flag) != 0;
  129. }
  130. /* Probe for the CPUID instruction */
  131. static int __cpuinit have_cpuid_p(void)
  132. {
  133. return flag_is_changeable_p(X86_EFLAGS_ID);
  134. }
  135. static void __cpuinit squash_the_stupid_serial_number(struct cpuinfo_x86 *c)
  136. {
  137. if (cpu_has(c, X86_FEATURE_PN) && disable_x86_serial_nr) {
  138. /* Disable processor serial number */
  139. unsigned long lo, hi;
  140. rdmsr(MSR_IA32_BBL_CR_CTL, lo, hi);
  141. lo |= 0x200000;
  142. wrmsr(MSR_IA32_BBL_CR_CTL, lo, hi);
  143. printk(KERN_NOTICE "CPU serial number disabled.\n");
  144. clear_cpu_cap(c, X86_FEATURE_PN);
  145. /* Disabling the serial number may affect the cpuid level */
  146. c->cpuid_level = cpuid_eax(0);
  147. }
  148. }
  149. static int __init x86_serial_nr_setup(char *s)
  150. {
  151. disable_x86_serial_nr = 0;
  152. return 1;
  153. }
  154. __setup("serialnumber", x86_serial_nr_setup);
  155. #else
  156. static inline int flag_is_changeable_p(u32 flag)
  157. {
  158. return 1;
  159. }
  160. /* Probe for the CPUID instruction */
  161. static inline int have_cpuid_p(void)
  162. {
  163. return 1;
  164. }
  165. static inline void squash_the_stupid_serial_number(struct cpuinfo_x86 *c)
  166. {
  167. }
  168. #endif
  169. /*
  170. * Naming convention should be: <Name> [(<Codename>)]
  171. * This table only is used unless init_<vendor>() below doesn't set it;
  172. * in particular, if CPUID levels 0x80000002..4 are supported, this isn't used
  173. *
  174. */
  175. /* Look up CPU names by table lookup. */
  176. static char __cpuinit *table_lookup_model(struct cpuinfo_x86 *c)
  177. {
  178. struct cpu_model_info *info;
  179. if (c->x86_model >= 16)
  180. return NULL; /* Range check */
  181. if (!this_cpu)
  182. return NULL;
  183. info = this_cpu->c_models;
  184. while (info && info->family) {
  185. if (info->family == c->x86)
  186. return info->model_names[c->x86_model];
  187. info++;
  188. }
  189. return NULL; /* Not found */
  190. }
  191. __u32 cleared_cpu_caps[NCAPINTS] __cpuinitdata;
  192. /* Current gdt points %fs at the "master" per-cpu area: after this,
  193. * it's on the real one. */
  194. void switch_to_new_gdt(void)
  195. {
  196. struct desc_ptr gdt_descr;
  197. gdt_descr.address = (long)get_cpu_gdt_table(smp_processor_id());
  198. gdt_descr.size = GDT_SIZE - 1;
  199. load_gdt(&gdt_descr);
  200. #ifdef CONFIG_X86_32
  201. asm("mov %0, %%fs" : : "r" (__KERNEL_PERCPU) : "memory");
  202. #endif
  203. }
  204. static struct cpu_dev *cpu_devs[X86_VENDOR_NUM] = {};
  205. static void __cpuinit default_init(struct cpuinfo_x86 *c)
  206. {
  207. #ifdef CONFIG_X86_64
  208. display_cacheinfo(c);
  209. #else
  210. /* Not much we can do here... */
  211. /* Check if at least it has cpuid */
  212. if (c->cpuid_level == -1) {
  213. /* No cpuid. It must be an ancient CPU */
  214. if (c->x86 == 4)
  215. strcpy(c->x86_model_id, "486");
  216. else if (c->x86 == 3)
  217. strcpy(c->x86_model_id, "386");
  218. }
  219. #endif
  220. }
  221. static struct cpu_dev __cpuinitdata default_cpu = {
  222. .c_init = default_init,
  223. .c_vendor = "Unknown",
  224. .c_x86_vendor = X86_VENDOR_UNKNOWN,
  225. };
  226. static void __cpuinit get_model_name(struct cpuinfo_x86 *c)
  227. {
  228. unsigned int *v;
  229. char *p, *q;
  230. if (c->extended_cpuid_level < 0x80000004)
  231. return;
  232. v = (unsigned int *) c->x86_model_id;
  233. cpuid(0x80000002, &v[0], &v[1], &v[2], &v[3]);
  234. cpuid(0x80000003, &v[4], &v[5], &v[6], &v[7]);
  235. cpuid(0x80000004, &v[8], &v[9], &v[10], &v[11]);
  236. c->x86_model_id[48] = 0;
  237. /* Intel chips right-justify this string for some dumb reason;
  238. undo that brain damage */
  239. p = q = &c->x86_model_id[0];
  240. while (*p == ' ')
  241. p++;
  242. if (p != q) {
  243. while (*p)
  244. *q++ = *p++;
  245. while (q <= &c->x86_model_id[48])
  246. *q++ = '\0'; /* Zero-pad the rest */
  247. }
  248. }
  249. void __cpuinit display_cacheinfo(struct cpuinfo_x86 *c)
  250. {
  251. unsigned int n, dummy, ebx, ecx, edx, l2size;
  252. n = c->extended_cpuid_level;
  253. if (n >= 0x80000005) {
  254. cpuid(0x80000005, &dummy, &ebx, &ecx, &edx);
  255. printk(KERN_INFO "CPU: L1 I Cache: %dK (%d bytes/line), D cache %dK (%d bytes/line)\n",
  256. edx>>24, edx&0xFF, ecx>>24, ecx&0xFF);
  257. c->x86_cache_size = (ecx>>24) + (edx>>24);
  258. #ifdef CONFIG_X86_64
  259. /* On K8 L1 TLB is inclusive, so don't count it */
  260. c->x86_tlbsize = 0;
  261. #endif
  262. }
  263. if (n < 0x80000006) /* Some chips just has a large L1. */
  264. return;
  265. cpuid(0x80000006, &dummy, &ebx, &ecx, &edx);
  266. l2size = ecx >> 16;
  267. #ifdef CONFIG_X86_64
  268. c->x86_tlbsize += ((ebx >> 16) & 0xfff) + (ebx & 0xfff);
  269. #else
  270. /* do processor-specific cache resizing */
  271. if (this_cpu->c_size_cache)
  272. l2size = this_cpu->c_size_cache(c, l2size);
  273. /* Allow user to override all this if necessary. */
  274. if (cachesize_override != -1)
  275. l2size = cachesize_override;
  276. if (l2size == 0)
  277. return; /* Again, no L2 cache is possible */
  278. #endif
  279. c->x86_cache_size = l2size;
  280. printk(KERN_INFO "CPU: L2 Cache: %dK (%d bytes/line)\n",
  281. l2size, ecx & 0xFF);
  282. }
  283. void __cpuinit detect_ht(struct cpuinfo_x86 *c)
  284. {
  285. #ifdef CONFIG_X86_HT
  286. u32 eax, ebx, ecx, edx;
  287. int index_msb, core_bits;
  288. if (!cpu_has(c, X86_FEATURE_HT))
  289. return;
  290. if (cpu_has(c, X86_FEATURE_CMP_LEGACY))
  291. goto out;
  292. if (cpu_has(c, X86_FEATURE_XTOPOLOGY))
  293. return;
  294. cpuid(1, &eax, &ebx, &ecx, &edx);
  295. smp_num_siblings = (ebx & 0xff0000) >> 16;
  296. if (smp_num_siblings == 1) {
  297. printk(KERN_INFO "CPU: Hyper-Threading is disabled\n");
  298. } else if (smp_num_siblings > 1) {
  299. if (smp_num_siblings > NR_CPUS) {
  300. printk(KERN_WARNING "CPU: Unsupported number of siblings %d",
  301. smp_num_siblings);
  302. smp_num_siblings = 1;
  303. return;
  304. }
  305. index_msb = get_count_order(smp_num_siblings);
  306. #ifdef CONFIG_X86_64
  307. c->phys_proc_id = phys_pkg_id(index_msb);
  308. #else
  309. c->phys_proc_id = phys_pkg_id(c->initial_apicid, index_msb);
  310. #endif
  311. smp_num_siblings = smp_num_siblings / c->x86_max_cores;
  312. index_msb = get_count_order(smp_num_siblings);
  313. core_bits = get_count_order(c->x86_max_cores);
  314. #ifdef CONFIG_X86_64
  315. c->cpu_core_id = phys_pkg_id(index_msb) &
  316. ((1 << core_bits) - 1);
  317. #else
  318. c->cpu_core_id = phys_pkg_id(c->initial_apicid, index_msb) &
  319. ((1 << core_bits) - 1);
  320. #endif
  321. }
  322. out:
  323. if ((c->x86_max_cores * smp_num_siblings) > 1) {
  324. printk(KERN_INFO "CPU: Physical Processor ID: %d\n",
  325. c->phys_proc_id);
  326. printk(KERN_INFO "CPU: Processor Core ID: %d\n",
  327. c->cpu_core_id);
  328. }
  329. #endif
  330. }
  331. static void __cpuinit get_cpu_vendor(struct cpuinfo_x86 *c)
  332. {
  333. char *v = c->x86_vendor_id;
  334. int i;
  335. static int printed;
  336. for (i = 0; i < X86_VENDOR_NUM; i++) {
  337. if (!cpu_devs[i])
  338. break;
  339. if (!strcmp(v, cpu_devs[i]->c_ident[0]) ||
  340. (cpu_devs[i]->c_ident[1] &&
  341. !strcmp(v, cpu_devs[i]->c_ident[1]))) {
  342. this_cpu = cpu_devs[i];
  343. c->x86_vendor = this_cpu->c_x86_vendor;
  344. return;
  345. }
  346. }
  347. if (!printed) {
  348. printed++;
  349. printk(KERN_ERR "CPU: vendor_id '%s' unknown, using generic init.\n", v);
  350. printk(KERN_ERR "CPU: Your system may be unstable.\n");
  351. }
  352. c->x86_vendor = X86_VENDOR_UNKNOWN;
  353. this_cpu = &default_cpu;
  354. }
  355. void __cpuinit cpu_detect(struct cpuinfo_x86 *c)
  356. {
  357. /* Get vendor name */
  358. cpuid(0x00000000, (unsigned int *)&c->cpuid_level,
  359. (unsigned int *)&c->x86_vendor_id[0],
  360. (unsigned int *)&c->x86_vendor_id[8],
  361. (unsigned int *)&c->x86_vendor_id[4]);
  362. c->x86 = 4;
  363. /* Intel-defined flags: level 0x00000001 */
  364. if (c->cpuid_level >= 0x00000001) {
  365. u32 junk, tfms, cap0, misc;
  366. cpuid(0x00000001, &tfms, &misc, &junk, &cap0);
  367. c->x86 = (tfms >> 8) & 0xf;
  368. c->x86_model = (tfms >> 4) & 0xf;
  369. c->x86_mask = tfms & 0xf;
  370. if (c->x86 == 0xf)
  371. c->x86 += (tfms >> 20) & 0xff;
  372. if (c->x86 >= 0x6)
  373. c->x86_model += ((tfms >> 16) & 0xf) << 4;
  374. if (cap0 & (1<<19)) {
  375. c->x86_clflush_size = ((misc >> 8) & 0xff) * 8;
  376. c->x86_cache_alignment = c->x86_clflush_size;
  377. }
  378. }
  379. }
  380. static void __cpuinit get_cpu_cap(struct cpuinfo_x86 *c)
  381. {
  382. u32 tfms, xlvl;
  383. u32 ebx;
  384. /* Intel-defined flags: level 0x00000001 */
  385. if (c->cpuid_level >= 0x00000001) {
  386. u32 capability, excap;
  387. cpuid(0x00000001, &tfms, &ebx, &excap, &capability);
  388. c->x86_capability[0] = capability;
  389. c->x86_capability[4] = excap;
  390. }
  391. /* AMD-defined flags: level 0x80000001 */
  392. xlvl = cpuid_eax(0x80000000);
  393. c->extended_cpuid_level = xlvl;
  394. if ((xlvl & 0xffff0000) == 0x80000000) {
  395. if (xlvl >= 0x80000001) {
  396. c->x86_capability[1] = cpuid_edx(0x80000001);
  397. c->x86_capability[6] = cpuid_ecx(0x80000001);
  398. }
  399. }
  400. #ifdef CONFIG_X86_64
  401. if (c->extended_cpuid_level >= 0x80000008) {
  402. u32 eax = cpuid_eax(0x80000008);
  403. c->x86_virt_bits = (eax >> 8) & 0xff;
  404. c->x86_phys_bits = eax & 0xff;
  405. }
  406. #endif
  407. if (c->extended_cpuid_level >= 0x80000007)
  408. c->x86_power = cpuid_edx(0x80000007);
  409. }
  410. static void __cpuinit identify_cpu_without_cpuid(struct cpuinfo_x86 *c)
  411. {
  412. #ifdef CONFIG_X86_32
  413. int i;
  414. /*
  415. * First of all, decide if this is a 486 or higher
  416. * It's a 486 if we can modify the AC flag
  417. */
  418. if (flag_is_changeable_p(X86_EFLAGS_AC))
  419. c->x86 = 4;
  420. else
  421. c->x86 = 3;
  422. for (i = 0; i < X86_VENDOR_NUM; i++)
  423. if (cpu_devs[i] && cpu_devs[i]->c_identify) {
  424. c->x86_vendor_id[0] = 0;
  425. cpu_devs[i]->c_identify(c);
  426. if (c->x86_vendor_id[0]) {
  427. get_cpu_vendor(c);
  428. break;
  429. }
  430. }
  431. #endif
  432. }
  433. /*
  434. * Do minimum CPU detection early.
  435. * Fields really needed: vendor, cpuid_level, family, model, mask,
  436. * cache alignment.
  437. * The others are not touched to avoid unwanted side effects.
  438. *
  439. * WARNING: this function is only called on the BP. Don't add code here
  440. * that is supposed to run on all CPUs.
  441. */
  442. static void __init early_identify_cpu(struct cpuinfo_x86 *c)
  443. {
  444. #ifdef CONFIG_X86_64
  445. c->x86_clflush_size = 64;
  446. #else
  447. c->x86_clflush_size = 32;
  448. #endif
  449. c->x86_cache_alignment = c->x86_clflush_size;
  450. memset(&c->x86_capability, 0, sizeof c->x86_capability);
  451. c->extended_cpuid_level = 0;
  452. if (!have_cpuid_p())
  453. identify_cpu_without_cpuid(c);
  454. /* cyrix could have cpuid enabled via c_identify()*/
  455. if (!have_cpuid_p())
  456. return;
  457. cpu_detect(c);
  458. get_cpu_vendor(c);
  459. get_cpu_cap(c);
  460. if (this_cpu->c_early_init)
  461. this_cpu->c_early_init(c);
  462. validate_pat_support(c);
  463. }
  464. void __init early_cpu_init(void)
  465. {
  466. struct cpu_dev **cdev;
  467. int count = 0;
  468. printk("KERNEL supported cpus:\n");
  469. for (cdev = __x86_cpu_dev_start; cdev < __x86_cpu_dev_end; cdev++) {
  470. struct cpu_dev *cpudev = *cdev;
  471. unsigned int j;
  472. if (count >= X86_VENDOR_NUM)
  473. break;
  474. cpu_devs[count] = cpudev;
  475. count++;
  476. for (j = 0; j < 2; j++) {
  477. if (!cpudev->c_ident[j])
  478. continue;
  479. printk(" %s %s\n", cpudev->c_vendor,
  480. cpudev->c_ident[j]);
  481. }
  482. }
  483. early_identify_cpu(&boot_cpu_data);
  484. }
  485. /*
  486. * The NOPL instruction is supposed to exist on all CPUs with
  487. * family >= 6; unfortunately, that's not true in practice because
  488. * of early VIA chips and (more importantly) broken virtualizers that
  489. * are not easy to detect. In the latter case it doesn't even *fail*
  490. * reliably, so probing for it doesn't even work. Disable it completely
  491. * unless we can find a reliable way to detect all the broken cases.
  492. */
  493. static void __cpuinit detect_nopl(struct cpuinfo_x86 *c)
  494. {
  495. clear_cpu_cap(c, X86_FEATURE_NOPL);
  496. }
  497. static void __cpuinit generic_identify(struct cpuinfo_x86 *c)
  498. {
  499. c->extended_cpuid_level = 0;
  500. if (!have_cpuid_p())
  501. identify_cpu_without_cpuid(c);
  502. /* cyrix could have cpuid enabled via c_identify()*/
  503. if (!have_cpuid_p())
  504. return;
  505. cpu_detect(c);
  506. get_cpu_vendor(c);
  507. get_cpu_cap(c);
  508. if (c->cpuid_level >= 0x00000001) {
  509. c->initial_apicid = (cpuid_ebx(1) >> 24) & 0xFF;
  510. #ifdef CONFIG_X86_32
  511. # ifdef CONFIG_X86_HT
  512. c->apicid = phys_pkg_id(c->initial_apicid, 0);
  513. # else
  514. c->apicid = c->initial_apicid;
  515. # endif
  516. #endif
  517. #ifdef CONFIG_X86_HT
  518. c->phys_proc_id = c->initial_apicid;
  519. #endif
  520. }
  521. get_model_name(c); /* Default name */
  522. init_scattered_cpuid_features(c);
  523. detect_nopl(c);
  524. }
  525. /*
  526. * This does the hard work of actually picking apart the CPU stuff...
  527. */
  528. static void __cpuinit identify_cpu(struct cpuinfo_x86 *c)
  529. {
  530. int i;
  531. c->loops_per_jiffy = loops_per_jiffy;
  532. c->x86_cache_size = -1;
  533. c->x86_vendor = X86_VENDOR_UNKNOWN;
  534. c->x86_model = c->x86_mask = 0; /* So far unknown... */
  535. c->x86_vendor_id[0] = '\0'; /* Unset */
  536. c->x86_model_id[0] = '\0'; /* Unset */
  537. c->x86_max_cores = 1;
  538. c->x86_coreid_bits = 0;
  539. #ifdef CONFIG_X86_64
  540. c->x86_clflush_size = 64;
  541. #else
  542. c->cpuid_level = -1; /* CPUID not detected */
  543. c->x86_clflush_size = 32;
  544. #endif
  545. c->x86_cache_alignment = c->x86_clflush_size;
  546. memset(&c->x86_capability, 0, sizeof c->x86_capability);
  547. generic_identify(c);
  548. if (this_cpu->c_identify)
  549. this_cpu->c_identify(c);
  550. #ifdef CONFIG_X86_64
  551. c->apicid = phys_pkg_id(0);
  552. #endif
  553. /*
  554. * Vendor-specific initialization. In this section we
  555. * canonicalize the feature flags, meaning if there are
  556. * features a certain CPU supports which CPUID doesn't
  557. * tell us, CPUID claiming incorrect flags, or other bugs,
  558. * we handle them here.
  559. *
  560. * At the end of this section, c->x86_capability better
  561. * indicate the features this CPU genuinely supports!
  562. */
  563. if (this_cpu->c_init)
  564. this_cpu->c_init(c);
  565. /* Disable the PN if appropriate */
  566. squash_the_stupid_serial_number(c);
  567. /*
  568. * The vendor-specific functions might have changed features. Now
  569. * we do "generic changes."
  570. */
  571. /* If the model name is still unset, do table lookup. */
  572. if (!c->x86_model_id[0]) {
  573. char *p;
  574. p = table_lookup_model(c);
  575. if (p)
  576. strcpy(c->x86_model_id, p);
  577. else
  578. /* Last resort... */
  579. sprintf(c->x86_model_id, "%02x/%02x",
  580. c->x86, c->x86_model);
  581. }
  582. #ifdef CONFIG_X86_64
  583. detect_ht(c);
  584. #endif
  585. /*
  586. * On SMP, boot_cpu_data holds the common feature set between
  587. * all CPUs; so make sure that we indicate which features are
  588. * common between the CPUs. The first time this routine gets
  589. * executed, c == &boot_cpu_data.
  590. */
  591. if (c != &boot_cpu_data) {
  592. /* AND the already accumulated flags with these */
  593. for (i = 0; i < NCAPINTS; i++)
  594. boot_cpu_data.x86_capability[i] &= c->x86_capability[i];
  595. }
  596. /* Clear all flags overriden by options */
  597. for (i = 0; i < NCAPINTS; i++)
  598. c->x86_capability[i] &= ~cleared_cpu_caps[i];
  599. #ifdef CONFIG_X86_MCE
  600. /* Init Machine Check Exception if available. */
  601. mcheck_init(c);
  602. #endif
  603. select_idle_routine(c);
  604. #if defined(CONFIG_NUMA) && defined(CONFIG_X86_64)
  605. numa_add_cpu(smp_processor_id());
  606. #endif
  607. }
  608. void __init identify_boot_cpu(void)
  609. {
  610. identify_cpu(&boot_cpu_data);
  611. #ifdef CONFIG_X86_32
  612. sysenter_setup();
  613. enable_sep_cpu();
  614. #endif
  615. }
  616. void __cpuinit identify_secondary_cpu(struct cpuinfo_x86 *c)
  617. {
  618. BUG_ON(c == &boot_cpu_data);
  619. identify_cpu(c);
  620. #ifdef CONFIG_X86_32
  621. enable_sep_cpu();
  622. #endif
  623. mtrr_ap_init();
  624. }
  625. struct msr_range {
  626. unsigned min;
  627. unsigned max;
  628. };
  629. static struct msr_range msr_range_array[] __cpuinitdata = {
  630. { 0x00000000, 0x00000418},
  631. { 0xc0000000, 0xc000040b},
  632. { 0xc0010000, 0xc0010142},
  633. { 0xc0011000, 0xc001103b},
  634. };
  635. static void __cpuinit print_cpu_msr(void)
  636. {
  637. unsigned index;
  638. u64 val;
  639. int i;
  640. unsigned index_min, index_max;
  641. for (i = 0; i < ARRAY_SIZE(msr_range_array); i++) {
  642. index_min = msr_range_array[i].min;
  643. index_max = msr_range_array[i].max;
  644. for (index = index_min; index < index_max; index++) {
  645. if (rdmsrl_amd_safe(index, &val))
  646. continue;
  647. printk(KERN_INFO " MSR%08x: %016llx\n", index, val);
  648. }
  649. }
  650. }
  651. static int show_msr __cpuinitdata;
  652. static __init int setup_show_msr(char *arg)
  653. {
  654. int num;
  655. get_option(&arg, &num);
  656. if (num > 0)
  657. show_msr = num;
  658. return 1;
  659. }
  660. __setup("show_msr=", setup_show_msr);
  661. static __init int setup_noclflush(char *arg)
  662. {
  663. setup_clear_cpu_cap(X86_FEATURE_CLFLSH);
  664. return 1;
  665. }
  666. __setup("noclflush", setup_noclflush);
  667. void __cpuinit print_cpu_info(struct cpuinfo_x86 *c)
  668. {
  669. char *vendor = NULL;
  670. if (c->x86_vendor < X86_VENDOR_NUM)
  671. vendor = this_cpu->c_vendor;
  672. else if (c->cpuid_level >= 0)
  673. vendor = c->x86_vendor_id;
  674. if (vendor && !strstr(c->x86_model_id, vendor))
  675. printk(KERN_CONT "%s ", vendor);
  676. if (c->x86_model_id[0])
  677. printk(KERN_CONT "%s", c->x86_model_id);
  678. else
  679. printk(KERN_CONT "%d86", c->x86);
  680. if (c->x86_mask || c->cpuid_level >= 0)
  681. printk(KERN_CONT " stepping %02x\n", c->x86_mask);
  682. else
  683. printk(KERN_CONT "\n");
  684. #ifdef CONFIG_SMP
  685. if (c->cpu_index < show_msr)
  686. print_cpu_msr();
  687. #else
  688. if (show_msr)
  689. print_cpu_msr();
  690. #endif
  691. }
  692. static __init int setup_disablecpuid(char *arg)
  693. {
  694. int bit;
  695. if (get_option(&arg, &bit) && bit < NCAPINTS*32)
  696. setup_clear_cpu_cap(bit);
  697. else
  698. return 0;
  699. return 1;
  700. }
  701. __setup("clearcpuid=", setup_disablecpuid);
  702. cpumask_t cpu_initialized __cpuinitdata = CPU_MASK_NONE;
  703. #ifdef CONFIG_X86_64
  704. struct x8664_pda **_cpu_pda __read_mostly;
  705. EXPORT_SYMBOL(_cpu_pda);
  706. struct desc_ptr idt_descr = { 256 * 16 - 1, (unsigned long) idt_table };
  707. char boot_cpu_stack[IRQSTACKSIZE] __page_aligned_bss;
  708. void __cpuinit pda_init(int cpu)
  709. {
  710. struct x8664_pda *pda = cpu_pda(cpu);
  711. /* Setup up data that may be needed in __get_free_pages early */
  712. loadsegment(fs, 0);
  713. loadsegment(gs, 0);
  714. /* Memory clobbers used to order PDA accessed */
  715. mb();
  716. wrmsrl(MSR_GS_BASE, pda);
  717. mb();
  718. pda->cpunumber = cpu;
  719. pda->irqcount = -1;
  720. pda->kernelstack = (unsigned long)stack_thread_info() -
  721. PDA_STACKOFFSET + THREAD_SIZE;
  722. pda->active_mm = &init_mm;
  723. pda->mmu_state = 0;
  724. if (cpu == 0) {
  725. /* others are initialized in smpboot.c */
  726. pda->pcurrent = &init_task;
  727. pda->irqstackptr = boot_cpu_stack;
  728. pda->irqstackptr += IRQSTACKSIZE - 64;
  729. } else {
  730. if (!pda->irqstackptr) {
  731. pda->irqstackptr = (char *)
  732. __get_free_pages(GFP_ATOMIC, IRQSTACK_ORDER);
  733. if (!pda->irqstackptr)
  734. panic("cannot allocate irqstack for cpu %d",
  735. cpu);
  736. pda->irqstackptr += IRQSTACKSIZE - 64;
  737. }
  738. if (pda->nodenumber == 0 && cpu_to_node(cpu) != NUMA_NO_NODE)
  739. pda->nodenumber = cpu_to_node(cpu);
  740. }
  741. }
  742. char boot_exception_stacks[(N_EXCEPTION_STACKS - 1) * EXCEPTION_STKSZ +
  743. DEBUG_STKSZ] __page_aligned_bss;
  744. extern asmlinkage void ignore_sysret(void);
  745. /* May not be marked __init: used by software suspend */
  746. void syscall_init(void)
  747. {
  748. /*
  749. * LSTAR and STAR live in a bit strange symbiosis.
  750. * They both write to the same internal register. STAR allows to
  751. * set CS/DS but only a 32bit target. LSTAR sets the 64bit rip.
  752. */
  753. wrmsrl(MSR_STAR, ((u64)__USER32_CS)<<48 | ((u64)__KERNEL_CS)<<32);
  754. wrmsrl(MSR_LSTAR, system_call);
  755. wrmsrl(MSR_CSTAR, ignore_sysret);
  756. #ifdef CONFIG_IA32_EMULATION
  757. syscall32_cpu_init();
  758. #endif
  759. /* Flags to clear on syscall */
  760. wrmsrl(MSR_SYSCALL_MASK,
  761. X86_EFLAGS_TF|X86_EFLAGS_DF|X86_EFLAGS_IF|X86_EFLAGS_IOPL);
  762. }
  763. unsigned long kernel_eflags;
  764. /*
  765. * Copies of the original ist values from the tss are only accessed during
  766. * debugging, no special alignment required.
  767. */
  768. DEFINE_PER_CPU(struct orig_ist, orig_ist);
  769. #else
  770. /* Make sure %fs is initialized properly in idle threads */
  771. struct pt_regs * __cpuinit idle_regs(struct pt_regs *regs)
  772. {
  773. memset(regs, 0, sizeof(struct pt_regs));
  774. regs->fs = __KERNEL_PERCPU;
  775. return regs;
  776. }
  777. #endif
  778. /*
  779. * cpu_init() initializes state that is per-CPU. Some data is already
  780. * initialized (naturally) in the bootstrap process, such as the GDT
  781. * and IDT. We reload them nevertheless, this function acts as a
  782. * 'CPU state barrier', nothing should get across.
  783. * A lot of state is already set up in PDA init for 64 bit
  784. */
  785. #ifdef CONFIG_X86_64
  786. void __cpuinit cpu_init(void)
  787. {
  788. int cpu = stack_smp_processor_id();
  789. struct tss_struct *t = &per_cpu(init_tss, cpu);
  790. struct orig_ist *orig_ist = &per_cpu(orig_ist, cpu);
  791. unsigned long v;
  792. char *estacks = NULL;
  793. struct task_struct *me;
  794. int i;
  795. /* CPU 0 is initialised in head64.c */
  796. if (cpu != 0)
  797. pda_init(cpu);
  798. else
  799. estacks = boot_exception_stacks;
  800. me = current;
  801. if (cpu_test_and_set(cpu, cpu_initialized))
  802. panic("CPU#%d already initialized!\n", cpu);
  803. printk(KERN_INFO "Initializing CPU#%d\n", cpu);
  804. clear_in_cr4(X86_CR4_VME|X86_CR4_PVI|X86_CR4_TSD|X86_CR4_DE);
  805. /*
  806. * Initialize the per-CPU GDT with the boot GDT,
  807. * and set up the GDT descriptor:
  808. */
  809. switch_to_new_gdt();
  810. load_idt((const struct desc_ptr *)&idt_descr);
  811. memset(me->thread.tls_array, 0, GDT_ENTRY_TLS_ENTRIES * 8);
  812. syscall_init();
  813. wrmsrl(MSR_FS_BASE, 0);
  814. wrmsrl(MSR_KERNEL_GS_BASE, 0);
  815. barrier();
  816. check_efer();
  817. if (cpu != 0 && x2apic)
  818. enable_x2apic();
  819. /*
  820. * set up and load the per-CPU TSS
  821. */
  822. if (!orig_ist->ist[0]) {
  823. static const unsigned int order[N_EXCEPTION_STACKS] = {
  824. [0 ... N_EXCEPTION_STACKS - 1] = EXCEPTION_STACK_ORDER,
  825. [DEBUG_STACK - 1] = DEBUG_STACK_ORDER
  826. };
  827. for (v = 0; v < N_EXCEPTION_STACKS; v++) {
  828. if (cpu) {
  829. estacks = (char *)__get_free_pages(GFP_ATOMIC, order[v]);
  830. if (!estacks)
  831. panic("Cannot allocate exception "
  832. "stack %ld %d\n", v, cpu);
  833. }
  834. estacks += PAGE_SIZE << order[v];
  835. orig_ist->ist[v] = t->x86_tss.ist[v] =
  836. (unsigned long)estacks;
  837. }
  838. }
  839. t->x86_tss.io_bitmap_base = offsetof(struct tss_struct, io_bitmap);
  840. /*
  841. * <= is required because the CPU will access up to
  842. * 8 bits beyond the end of the IO permission bitmap.
  843. */
  844. for (i = 0; i <= IO_BITMAP_LONGS; i++)
  845. t->io_bitmap[i] = ~0UL;
  846. atomic_inc(&init_mm.mm_count);
  847. me->active_mm = &init_mm;
  848. if (me->mm)
  849. BUG();
  850. enter_lazy_tlb(&init_mm, me);
  851. load_sp0(t, &current->thread);
  852. set_tss_desc(cpu, t);
  853. load_TR_desc();
  854. load_LDT(&init_mm.context);
  855. #ifdef CONFIG_KGDB
  856. /*
  857. * If the kgdb is connected no debug regs should be altered. This
  858. * is only applicable when KGDB and a KGDB I/O module are built
  859. * into the kernel and you are using early debugging with
  860. * kgdbwait. KGDB will control the kernel HW breakpoint registers.
  861. */
  862. if (kgdb_connected && arch_kgdb_ops.correct_hw_break)
  863. arch_kgdb_ops.correct_hw_break();
  864. else {
  865. #endif
  866. /*
  867. * Clear all 6 debug registers:
  868. */
  869. set_debugreg(0UL, 0);
  870. set_debugreg(0UL, 1);
  871. set_debugreg(0UL, 2);
  872. set_debugreg(0UL, 3);
  873. set_debugreg(0UL, 6);
  874. set_debugreg(0UL, 7);
  875. #ifdef CONFIG_KGDB
  876. /* If the kgdb is connected no debug regs should be altered. */
  877. }
  878. #endif
  879. fpu_init();
  880. raw_local_save_flags(kernel_eflags);
  881. if (is_uv_system())
  882. uv_cpu_init();
  883. }
  884. #else
  885. void __cpuinit cpu_init(void)
  886. {
  887. int cpu = smp_processor_id();
  888. struct task_struct *curr = current;
  889. struct tss_struct *t = &per_cpu(init_tss, cpu);
  890. struct thread_struct *thread = &curr->thread;
  891. if (cpu_test_and_set(cpu, cpu_initialized)) {
  892. printk(KERN_WARNING "CPU#%d already initialized!\n", cpu);
  893. for (;;) local_irq_enable();
  894. }
  895. printk(KERN_INFO "Initializing CPU#%d\n", cpu);
  896. if (cpu_has_vme || cpu_has_tsc || cpu_has_de)
  897. clear_in_cr4(X86_CR4_VME|X86_CR4_PVI|X86_CR4_TSD|X86_CR4_DE);
  898. load_idt(&idt_descr);
  899. switch_to_new_gdt();
  900. /*
  901. * Set up and load the per-CPU TSS and LDT
  902. */
  903. atomic_inc(&init_mm.mm_count);
  904. curr->active_mm = &init_mm;
  905. if (curr->mm)
  906. BUG();
  907. enter_lazy_tlb(&init_mm, curr);
  908. load_sp0(t, thread);
  909. set_tss_desc(cpu, t);
  910. load_TR_desc();
  911. load_LDT(&init_mm.context);
  912. #ifdef CONFIG_DOUBLEFAULT
  913. /* Set up doublefault TSS pointer in the GDT */
  914. __set_tss_desc(cpu, GDT_ENTRY_DOUBLEFAULT_TSS, &doublefault_tss);
  915. #endif
  916. /* Clear %gs. */
  917. asm volatile ("mov %0, %%gs" : : "r" (0));
  918. /* Clear all 6 debug registers: */
  919. set_debugreg(0, 0);
  920. set_debugreg(0, 1);
  921. set_debugreg(0, 2);
  922. set_debugreg(0, 3);
  923. set_debugreg(0, 6);
  924. set_debugreg(0, 7);
  925. /*
  926. * Force FPU initialization:
  927. */
  928. if (cpu_has_xsave)
  929. current_thread_info()->status = TS_XSAVE;
  930. else
  931. current_thread_info()->status = 0;
  932. clear_used_math();
  933. mxcsr_feature_mask_init();
  934. /*
  935. * Boot processor to setup the FP and extended state context info.
  936. */
  937. if (!smp_processor_id())
  938. init_thread_xstate();
  939. xsave_init();
  940. }
  941. #endif