nv84_crypt.c 3.1 KB

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  1. /*
  2. * Copyright 2010 Red Hat Inc.
  3. *
  4. * Permission is hereby granted, free of charge, to any person obtaining a
  5. * copy of this software and associated documentation files (the "Software"),
  6. * to deal in the Software without restriction, including without limitation
  7. * the rights to use, copy, modify, merge, publish, distribute, sublicense,
  8. * and/or sell copies of the Software, and to permit persons to whom the
  9. * Software is furnished to do so, subject to the following conditions:
  10. *
  11. * The above copyright notice and this permission notice shall be included in
  12. * all copies or substantial portions of the Software.
  13. *
  14. * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15. * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16. * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
  17. * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18. * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19. * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20. * OTHER DEALINGS IN THE SOFTWARE.
  21. *
  22. * Authors: Ben Skeggs
  23. */
  24. #include "drmP.h"
  25. #include "nouveau_drv.h"
  26. int
  27. nv84_crypt_create_context(struct nouveau_channel *chan)
  28. {
  29. struct drm_device *dev = chan->dev;
  30. struct drm_nouveau_private *dev_priv = dev->dev_private;
  31. struct nouveau_gpuobj *ramin = chan->ramin;
  32. int ret;
  33. NV_DEBUG(dev, "ch%d\n", chan->id);
  34. ret = nouveau_gpuobj_new(dev, chan, 256, 0x1000,
  35. NVOBJ_FLAG_ZERO_ALLOC | NVOBJ_FLAG_ZERO_FREE,
  36. &chan->crypt_ctx);
  37. if (ret)
  38. return ret;
  39. nv_wo32(ramin, 0xa0, 0x00190000);
  40. nv_wo32(ramin, 0xa4, chan->crypt_ctx->vinst + 0xff);
  41. nv_wo32(ramin, 0xa8, chan->crypt_ctx->vinst);
  42. nv_wo32(ramin, 0xac, 0);
  43. nv_wo32(ramin, 0xb0, 0);
  44. nv_wo32(ramin, 0xb4, 0);
  45. dev_priv->engine.instmem.flush(dev);
  46. return 0;
  47. }
  48. void
  49. nv84_crypt_destroy_context(struct nouveau_channel *chan)
  50. {
  51. struct drm_device *dev = chan->dev;
  52. u32 inst;
  53. if (!chan->ramin)
  54. return;
  55. inst = (chan->ramin->vinst >> 12);
  56. inst |= 0x80000000;
  57. /* mark context as invalid if still on the hardware, not
  58. * doing this causes issues the next time PCRYPT is used,
  59. * unsurprisingly :)
  60. */
  61. nv_wr32(dev, 0x10200c, 0x00000000);
  62. if (nv_rd32(dev, 0x102188) == inst)
  63. nv_mask(dev, 0x102188, 0x80000000, 0x00000000);
  64. if (nv_rd32(dev, 0x10218c) == inst)
  65. nv_mask(dev, 0x10218c, 0x80000000, 0x00000000);
  66. nv_wr32(dev, 0x10200c, 0x00000010);
  67. nouveau_gpuobj_ref(NULL, &chan->crypt_ctx);
  68. }
  69. void
  70. nv84_crypt_tlb_flush(struct drm_device *dev)
  71. {
  72. nv50_vm_flush(dev, 0x0a);
  73. }
  74. int
  75. nv84_crypt_init(struct drm_device *dev)
  76. {
  77. struct drm_nouveau_private *dev_priv = dev->dev_private;
  78. struct nouveau_crypt_engine *pcrypt = &dev_priv->engine.crypt;
  79. if (!pcrypt->registered) {
  80. NVOBJ_CLASS(dev, 0x74c1, CRYPT);
  81. pcrypt->registered = true;
  82. }
  83. nv_mask(dev, 0x000200, 0x00004000, 0x00000000);
  84. nv_mask(dev, 0x000200, 0x00004000, 0x00004000);
  85. nv_wr32(dev, 0x102130, 0xffffffff);
  86. nv_wr32(dev, 0x102140, 0xffffffbf);
  87. nv_wr32(dev, 0x10200c, 0x00000010);
  88. return 0;
  89. }
  90. void
  91. nv84_crypt_fini(struct drm_device *dev)
  92. {
  93. nv_wr32(dev, 0x102140, 0x00000000);
  94. }