events.c 44 KB

123456789101112131415161718192021222324252627282930313233343536373839404142434445464748495051525354555657585960616263646566676869707172737475767778798081828384858687888990919293949596979899100101102103104105106107108109110111112113114115116117118119120121122123124125126127128129130131132133134135136137138139140141142143144145146147148149150151152153154155156157158159160161162163164165166167168169170171172173174175176177178179180181182183184185186187188189190191192193194195196197198199200201202203204205206207208209210211212213214215216217218219220221222223224225226227228229230231232233234235236237238239240241242243244245246247248249250251252253254255256257258259260261262263264265266267268269270271272273274275276277278279280281282283284285286287288289290291292293294295296297298299300301302303304305306307308309310311312313314315316317318319320321322323324325326327328329330331332333334335336337338339340341342343344345346347348349350351352353354355356357358359360361362363364365366367368369370371372373374375376377378379380381382383384385386387388389390391392393394395396397398399400401402403404405406407408409410411412413414415416417418419420421422423424425426427428429430431432433434435436437438439440441442443444445446447448449450451452453454455456457458459460461462463464465466467468469470471472473474475476477478479480481482483484485486487488489490491492493494495496497498499500501502503504505506507508509510511512513514515516517518519520521522523524525526527528529530531532533534535536537538539540541542543544545546547548549550551552553554555556557558559560561562563564565566567568569570571572573574575576577578579580581582583584585586587588589590591592593594595596597598599600601602603604605606607608609610611612613614615616617618619620621622623624625626627628629630631632633634635636637638639640641642643644645646647648649650651652653654655656657658659660661662663664665666667668669670671672673674675676677678679680681682683684685686687688689690691692693694695696697698699700701702703704705706707708709710711712713714715716717718719720721722723724725726727728729730731732733734735736737738739740741742743744745746747748749750751752753754755756757758759760761762763764765766767768769770771772773774775776777778779780781782783784785786787788789790791792793794795796797798799800801802803804805806807808809810811812813814815816817818819820821822823824825826827828829830831832833834835836837838839840841842843844845846847848849850851852853854855856857858859860861862863864865866867868869870871872873874875876877878879880881882883884885886887888889890891892893894895896897898899900901902903904905906907908909910911912913914915916917918919920921922923924925926927928929930931932933934935936937938939940941942943944945946947948949950951952953954955956957958959960961962963964965966967968969970971972973974975976977978979980981982983984985986987988989990991992993994995996997998999100010011002100310041005100610071008100910101011101210131014101510161017101810191020102110221023102410251026102710281029103010311032103310341035103610371038103910401041104210431044104510461047104810491050105110521053105410551056105710581059106010611062106310641065106610671068106910701071107210731074107510761077107810791080108110821083108410851086108710881089109010911092109310941095109610971098109911001101110211031104110511061107110811091110111111121113111411151116111711181119112011211122112311241125112611271128112911301131113211331134113511361137113811391140114111421143114411451146114711481149115011511152115311541155115611571158115911601161116211631164116511661167116811691170117111721173117411751176117711781179118011811182118311841185118611871188118911901191119211931194119511961197119811991200120112021203120412051206120712081209121012111212121312141215121612171218121912201221122212231224122512261227122812291230123112321233123412351236123712381239124012411242124312441245124612471248124912501251125212531254125512561257125812591260126112621263126412651266126712681269127012711272127312741275127612771278127912801281128212831284128512861287128812891290129112921293129412951296129712981299130013011302130313041305130613071308130913101311131213131314131513161317131813191320132113221323132413251326132713281329133013311332133313341335133613371338133913401341134213431344134513461347134813491350135113521353135413551356135713581359136013611362136313641365136613671368136913701371137213731374137513761377137813791380138113821383138413851386138713881389139013911392139313941395139613971398139914001401140214031404140514061407140814091410141114121413141414151416141714181419142014211422142314241425142614271428142914301431143214331434143514361437143814391440144114421443144414451446144714481449145014511452145314541455145614571458145914601461146214631464146514661467146814691470147114721473147414751476147714781479148014811482148314841485148614871488148914901491149214931494149514961497149814991500150115021503150415051506150715081509151015111512151315141515151615171518151915201521152215231524152515261527152815291530153115321533153415351536153715381539154015411542154315441545154615471548154915501551155215531554155515561557155815591560156115621563156415651566156715681569157015711572157315741575157615771578157915801581158215831584158515861587158815891590159115921593159415951596159715981599160016011602160316041605160616071608160916101611161216131614161516161617161816191620162116221623162416251626162716281629163016311632163316341635163616371638163916401641164216431644164516461647164816491650165116521653165416551656165716581659166016611662166316641665166616671668166916701671167216731674167516761677167816791680168116821683168416851686168716881689169016911692169316941695169616971698169917001701170217031704170517061707170817091710171117121713171417151716171717181719172017211722172317241725172617271728172917301731173217331734173517361737173817391740174117421743174417451746174717481749175017511752175317541755175617571758175917601761176217631764176517661767176817691770177117721773177417751776177717781779178017811782178317841785178617871788178917901791179217931794179517961797179817991800180118021803180418051806180718081809181018111812181318141815181618171818181918201821182218231824182518261827182818291830183118321833183418351836183718381839184018411842184318441845184618471848184918501851185218531854185518561857185818591860186118621863186418651866186718681869187018711872187318741875187618771878187918801881188218831884188518861887188818891890189118921893189418951896189718981899190019011902190319041905190619071908190919101911191219131914191519161917191819191920192119221923192419251926192719281929193019311932193319341935
  1. /*
  2. * Xen event channels
  3. *
  4. * Xen models interrupts with abstract event channels. Because each
  5. * domain gets 1024 event channels, but NR_IRQ is not that large, we
  6. * must dynamically map irqs<->event channels. The event channels
  7. * interface with the rest of the kernel by defining a xen interrupt
  8. * chip. When an event is received, it is mapped to an irq and sent
  9. * through the normal interrupt processing path.
  10. *
  11. * There are four kinds of events which can be mapped to an event
  12. * channel:
  13. *
  14. * 1. Inter-domain notifications. This includes all the virtual
  15. * device events, since they're driven by front-ends in another domain
  16. * (typically dom0).
  17. * 2. VIRQs, typically used for timers. These are per-cpu events.
  18. * 3. IPIs.
  19. * 4. PIRQs - Hardware interrupts.
  20. *
  21. * Jeremy Fitzhardinge <jeremy@xensource.com>, XenSource Inc, 2007
  22. */
  23. #define pr_fmt(fmt) "xen:" KBUILD_MODNAME ": " fmt
  24. #include <linux/linkage.h>
  25. #include <linux/interrupt.h>
  26. #include <linux/irq.h>
  27. #include <linux/module.h>
  28. #include <linux/string.h>
  29. #include <linux/bootmem.h>
  30. #include <linux/slab.h>
  31. #include <linux/irqnr.h>
  32. #include <linux/pci.h>
  33. #ifdef CONFIG_X86
  34. #include <asm/desc.h>
  35. #include <asm/ptrace.h>
  36. #include <asm/irq.h>
  37. #include <asm/idle.h>
  38. #include <asm/io_apic.h>
  39. #include <asm/xen/page.h>
  40. #include <asm/xen/pci.h>
  41. #endif
  42. #include <asm/sync_bitops.h>
  43. #include <asm/xen/hypercall.h>
  44. #include <asm/xen/hypervisor.h>
  45. #include <xen/xen.h>
  46. #include <xen/hvm.h>
  47. #include <xen/xen-ops.h>
  48. #include <xen/events.h>
  49. #include <xen/interface/xen.h>
  50. #include <xen/interface/event_channel.h>
  51. #include <xen/interface/hvm/hvm_op.h>
  52. #include <xen/interface/hvm/params.h>
  53. #include <xen/interface/physdev.h>
  54. #include <xen/interface/sched.h>
  55. #include <xen/interface/vcpu.h>
  56. #include <asm/hw_irq.h>
  57. /*
  58. * This lock protects updates to the following mapping and reference-count
  59. * arrays. The lock does not need to be acquired to read the mapping tables.
  60. */
  61. static DEFINE_MUTEX(irq_mapping_update_lock);
  62. static LIST_HEAD(xen_irq_list_head);
  63. /* IRQ <-> VIRQ mapping. */
  64. static DEFINE_PER_CPU(int [NR_VIRQS], virq_to_irq) = {[0 ... NR_VIRQS-1] = -1};
  65. /* IRQ <-> IPI mapping */
  66. static DEFINE_PER_CPU(int [XEN_NR_IPIS], ipi_to_irq) = {[0 ... XEN_NR_IPIS-1] = -1};
  67. /* Interrupt types. */
  68. enum xen_irq_type {
  69. IRQT_UNBOUND = 0,
  70. IRQT_PIRQ,
  71. IRQT_VIRQ,
  72. IRQT_IPI,
  73. IRQT_EVTCHN
  74. };
  75. /*
  76. * Packed IRQ information:
  77. * type - enum xen_irq_type
  78. * event channel - irq->event channel mapping
  79. * cpu - cpu this event channel is bound to
  80. * index - type-specific information:
  81. * PIRQ - physical IRQ, GSI, flags, and owner domain
  82. * VIRQ - virq number
  83. * IPI - IPI vector
  84. * EVTCHN -
  85. */
  86. struct irq_info {
  87. struct list_head list;
  88. int refcnt;
  89. enum xen_irq_type type; /* type */
  90. unsigned irq;
  91. unsigned short evtchn; /* event channel */
  92. unsigned short cpu; /* cpu bound */
  93. union {
  94. unsigned short virq;
  95. enum ipi_vector ipi;
  96. struct {
  97. unsigned short pirq;
  98. unsigned short gsi;
  99. unsigned char flags;
  100. uint16_t domid;
  101. } pirq;
  102. } u;
  103. };
  104. #define PIRQ_NEEDS_EOI (1 << 0)
  105. #define PIRQ_SHAREABLE (1 << 1)
  106. static int *evtchn_to_irq;
  107. #ifdef CONFIG_X86
  108. static unsigned long *pirq_eoi_map;
  109. #endif
  110. static bool (*pirq_needs_eoi)(unsigned irq);
  111. /*
  112. * Note sizeof(xen_ulong_t) can be more than sizeof(unsigned long). Be
  113. * careful to only use bitops which allow for this (e.g
  114. * test_bit/find_first_bit and friends but not __ffs) and to pass
  115. * BITS_PER_EVTCHN_WORD as the bitmask length.
  116. */
  117. #define BITS_PER_EVTCHN_WORD (sizeof(xen_ulong_t)*8)
  118. /*
  119. * Make a bitmask (i.e. unsigned long *) of a xen_ulong_t
  120. * array. Primarily to avoid long lines (hence the terse name).
  121. */
  122. #define BM(x) (unsigned long *)(x)
  123. /* Find the first set bit in a evtchn mask */
  124. #define EVTCHN_FIRST_BIT(w) find_first_bit(BM(&(w)), BITS_PER_EVTCHN_WORD)
  125. static DEFINE_PER_CPU(xen_ulong_t [NR_EVENT_CHANNELS/BITS_PER_EVTCHN_WORD],
  126. cpu_evtchn_mask);
  127. /* Xen will never allocate port zero for any purpose. */
  128. #define VALID_EVTCHN(chn) ((chn) != 0)
  129. static struct irq_chip xen_dynamic_chip;
  130. static struct irq_chip xen_percpu_chip;
  131. static struct irq_chip xen_pirq_chip;
  132. static void enable_dynirq(struct irq_data *data);
  133. static void disable_dynirq(struct irq_data *data);
  134. /* Get info for IRQ */
  135. static struct irq_info *info_for_irq(unsigned irq)
  136. {
  137. return irq_get_handler_data(irq);
  138. }
  139. /* Constructors for packed IRQ information. */
  140. static void xen_irq_info_common_init(struct irq_info *info,
  141. unsigned irq,
  142. enum xen_irq_type type,
  143. unsigned short evtchn,
  144. unsigned short cpu)
  145. {
  146. BUG_ON(info->type != IRQT_UNBOUND && info->type != type);
  147. info->type = type;
  148. info->irq = irq;
  149. info->evtchn = evtchn;
  150. info->cpu = cpu;
  151. evtchn_to_irq[evtchn] = irq;
  152. irq_clear_status_flags(irq, IRQ_NOREQUEST|IRQ_NOAUTOEN);
  153. }
  154. static void xen_irq_info_evtchn_init(unsigned irq,
  155. unsigned short evtchn)
  156. {
  157. struct irq_info *info = info_for_irq(irq);
  158. xen_irq_info_common_init(info, irq, IRQT_EVTCHN, evtchn, 0);
  159. }
  160. static void xen_irq_info_ipi_init(unsigned cpu,
  161. unsigned irq,
  162. unsigned short evtchn,
  163. enum ipi_vector ipi)
  164. {
  165. struct irq_info *info = info_for_irq(irq);
  166. xen_irq_info_common_init(info, irq, IRQT_IPI, evtchn, 0);
  167. info->u.ipi = ipi;
  168. per_cpu(ipi_to_irq, cpu)[ipi] = irq;
  169. }
  170. static void xen_irq_info_virq_init(unsigned cpu,
  171. unsigned irq,
  172. unsigned short evtchn,
  173. unsigned short virq)
  174. {
  175. struct irq_info *info = info_for_irq(irq);
  176. xen_irq_info_common_init(info, irq, IRQT_VIRQ, evtchn, 0);
  177. info->u.virq = virq;
  178. per_cpu(virq_to_irq, cpu)[virq] = irq;
  179. }
  180. static void xen_irq_info_pirq_init(unsigned irq,
  181. unsigned short evtchn,
  182. unsigned short pirq,
  183. unsigned short gsi,
  184. uint16_t domid,
  185. unsigned char flags)
  186. {
  187. struct irq_info *info = info_for_irq(irq);
  188. xen_irq_info_common_init(info, irq, IRQT_PIRQ, evtchn, 0);
  189. info->u.pirq.pirq = pirq;
  190. info->u.pirq.gsi = gsi;
  191. info->u.pirq.domid = domid;
  192. info->u.pirq.flags = flags;
  193. }
  194. /*
  195. * Accessors for packed IRQ information.
  196. */
  197. static unsigned int evtchn_from_irq(unsigned irq)
  198. {
  199. if (unlikely(WARN(irq < 0 || irq >= nr_irqs, "Invalid irq %d!\n", irq)))
  200. return 0;
  201. return info_for_irq(irq)->evtchn;
  202. }
  203. unsigned irq_from_evtchn(unsigned int evtchn)
  204. {
  205. return evtchn_to_irq[evtchn];
  206. }
  207. EXPORT_SYMBOL_GPL(irq_from_evtchn);
  208. static enum ipi_vector ipi_from_irq(unsigned irq)
  209. {
  210. struct irq_info *info = info_for_irq(irq);
  211. BUG_ON(info == NULL);
  212. BUG_ON(info->type != IRQT_IPI);
  213. return info->u.ipi;
  214. }
  215. static unsigned virq_from_irq(unsigned irq)
  216. {
  217. struct irq_info *info = info_for_irq(irq);
  218. BUG_ON(info == NULL);
  219. BUG_ON(info->type != IRQT_VIRQ);
  220. return info->u.virq;
  221. }
  222. static unsigned pirq_from_irq(unsigned irq)
  223. {
  224. struct irq_info *info = info_for_irq(irq);
  225. BUG_ON(info == NULL);
  226. BUG_ON(info->type != IRQT_PIRQ);
  227. return info->u.pirq.pirq;
  228. }
  229. static enum xen_irq_type type_from_irq(unsigned irq)
  230. {
  231. return info_for_irq(irq)->type;
  232. }
  233. static unsigned cpu_from_irq(unsigned irq)
  234. {
  235. return info_for_irq(irq)->cpu;
  236. }
  237. static unsigned int cpu_from_evtchn(unsigned int evtchn)
  238. {
  239. int irq = evtchn_to_irq[evtchn];
  240. unsigned ret = 0;
  241. if (irq != -1)
  242. ret = cpu_from_irq(irq);
  243. return ret;
  244. }
  245. #ifdef CONFIG_X86
  246. static bool pirq_check_eoi_map(unsigned irq)
  247. {
  248. return test_bit(pirq_from_irq(irq), pirq_eoi_map);
  249. }
  250. #endif
  251. static bool pirq_needs_eoi_flag(unsigned irq)
  252. {
  253. struct irq_info *info = info_for_irq(irq);
  254. BUG_ON(info->type != IRQT_PIRQ);
  255. return info->u.pirq.flags & PIRQ_NEEDS_EOI;
  256. }
  257. static inline xen_ulong_t active_evtchns(unsigned int cpu,
  258. struct shared_info *sh,
  259. unsigned int idx)
  260. {
  261. return sh->evtchn_pending[idx] &
  262. per_cpu(cpu_evtchn_mask, cpu)[idx] &
  263. ~sh->evtchn_mask[idx];
  264. }
  265. static void bind_evtchn_to_cpu(unsigned int chn, unsigned int cpu)
  266. {
  267. int irq = evtchn_to_irq[chn];
  268. BUG_ON(irq == -1);
  269. #ifdef CONFIG_SMP
  270. cpumask_copy(irq_to_desc(irq)->irq_data.affinity, cpumask_of(cpu));
  271. #endif
  272. clear_bit(chn, BM(per_cpu(cpu_evtchn_mask, cpu_from_irq(irq))));
  273. set_bit(chn, BM(per_cpu(cpu_evtchn_mask, cpu)));
  274. info_for_irq(irq)->cpu = cpu;
  275. }
  276. static void init_evtchn_cpu_bindings(void)
  277. {
  278. int i;
  279. #ifdef CONFIG_SMP
  280. struct irq_info *info;
  281. /* By default all event channels notify CPU#0. */
  282. list_for_each_entry(info, &xen_irq_list_head, list) {
  283. struct irq_desc *desc = irq_to_desc(info->irq);
  284. cpumask_copy(desc->irq_data.affinity, cpumask_of(0));
  285. }
  286. #endif
  287. for_each_possible_cpu(i)
  288. memset(per_cpu(cpu_evtchn_mask, i),
  289. (i == 0) ? ~0 : 0, NR_EVENT_CHANNELS/8);
  290. }
  291. static inline void clear_evtchn(int port)
  292. {
  293. struct shared_info *s = HYPERVISOR_shared_info;
  294. sync_clear_bit(port, BM(&s->evtchn_pending[0]));
  295. }
  296. static inline void set_evtchn(int port)
  297. {
  298. struct shared_info *s = HYPERVISOR_shared_info;
  299. sync_set_bit(port, BM(&s->evtchn_pending[0]));
  300. }
  301. static inline int test_evtchn(int port)
  302. {
  303. struct shared_info *s = HYPERVISOR_shared_info;
  304. return sync_test_bit(port, BM(&s->evtchn_pending[0]));
  305. }
  306. /**
  307. * notify_remote_via_irq - send event to remote end of event channel via irq
  308. * @irq: irq of event channel to send event to
  309. *
  310. * Unlike notify_remote_via_evtchn(), this is safe to use across
  311. * save/restore. Notifications on a broken connection are silently
  312. * dropped.
  313. */
  314. void notify_remote_via_irq(int irq)
  315. {
  316. int evtchn = evtchn_from_irq(irq);
  317. if (VALID_EVTCHN(evtchn))
  318. notify_remote_via_evtchn(evtchn);
  319. }
  320. EXPORT_SYMBOL_GPL(notify_remote_via_irq);
  321. static void mask_evtchn(int port)
  322. {
  323. struct shared_info *s = HYPERVISOR_shared_info;
  324. sync_set_bit(port, BM(&s->evtchn_mask[0]));
  325. }
  326. static void unmask_evtchn(int port)
  327. {
  328. struct shared_info *s = HYPERVISOR_shared_info;
  329. unsigned int cpu = get_cpu();
  330. int do_hypercall = 0, evtchn_pending = 0;
  331. BUG_ON(!irqs_disabled());
  332. if (unlikely((cpu != cpu_from_evtchn(port))))
  333. do_hypercall = 1;
  334. else {
  335. /*
  336. * Need to clear the mask before checking pending to
  337. * avoid a race with an event becoming pending.
  338. *
  339. * EVTCHNOP_unmask will only trigger an upcall if the
  340. * mask bit was set, so if a hypercall is needed
  341. * remask the event.
  342. */
  343. sync_clear_bit(port, BM(&s->evtchn_mask[0]));
  344. evtchn_pending = sync_test_bit(port, BM(&s->evtchn_pending[0]));
  345. if (unlikely(evtchn_pending && xen_hvm_domain())) {
  346. sync_set_bit(port, BM(&s->evtchn_mask[0]));
  347. do_hypercall = 1;
  348. }
  349. }
  350. /* Slow path (hypercall) if this is a non-local port or if this is
  351. * an hvm domain and an event is pending (hvm domains don't have
  352. * their own implementation of irq_enable). */
  353. if (do_hypercall) {
  354. struct evtchn_unmask unmask = { .port = port };
  355. (void)HYPERVISOR_event_channel_op(EVTCHNOP_unmask, &unmask);
  356. } else {
  357. struct vcpu_info *vcpu_info = __this_cpu_read(xen_vcpu);
  358. /*
  359. * The following is basically the equivalent of
  360. * 'hw_resend_irq'. Just like a real IO-APIC we 'lose
  361. * the interrupt edge' if the channel is masked.
  362. */
  363. if (evtchn_pending &&
  364. !sync_test_and_set_bit(port / BITS_PER_EVTCHN_WORD,
  365. BM(&vcpu_info->evtchn_pending_sel)))
  366. vcpu_info->evtchn_upcall_pending = 1;
  367. }
  368. put_cpu();
  369. }
  370. static void xen_irq_init(unsigned irq)
  371. {
  372. struct irq_info *info;
  373. #ifdef CONFIG_SMP
  374. struct irq_desc *desc = irq_to_desc(irq);
  375. /* By default all event channels notify CPU#0. */
  376. cpumask_copy(desc->irq_data.affinity, cpumask_of(0));
  377. #endif
  378. info = kzalloc(sizeof(*info), GFP_KERNEL);
  379. if (info == NULL)
  380. panic("Unable to allocate metadata for IRQ%d\n", irq);
  381. info->type = IRQT_UNBOUND;
  382. info->refcnt = -1;
  383. irq_set_handler_data(irq, info);
  384. list_add_tail(&info->list, &xen_irq_list_head);
  385. }
  386. static int __must_check xen_allocate_irq_dynamic(void)
  387. {
  388. int first = 0;
  389. int irq;
  390. #ifdef CONFIG_X86_IO_APIC
  391. /*
  392. * For an HVM guest or domain 0 which see "real" (emulated or
  393. * actual respectively) GSIs we allocate dynamic IRQs
  394. * e.g. those corresponding to event channels or MSIs
  395. * etc. from the range above those "real" GSIs to avoid
  396. * collisions.
  397. */
  398. if (xen_initial_domain() || xen_hvm_domain())
  399. first = get_nr_irqs_gsi();
  400. #endif
  401. irq = irq_alloc_desc_from(first, -1);
  402. if (irq >= 0)
  403. xen_irq_init(irq);
  404. return irq;
  405. }
  406. static int __must_check xen_allocate_irq_gsi(unsigned gsi)
  407. {
  408. int irq;
  409. /*
  410. * A PV guest has no concept of a GSI (since it has no ACPI
  411. * nor access to/knowledge of the physical APICs). Therefore
  412. * all IRQs are dynamically allocated from the entire IRQ
  413. * space.
  414. */
  415. if (xen_pv_domain() && !xen_initial_domain())
  416. return xen_allocate_irq_dynamic();
  417. /* Legacy IRQ descriptors are already allocated by the arch. */
  418. if (gsi < NR_IRQS_LEGACY)
  419. irq = gsi;
  420. else
  421. irq = irq_alloc_desc_at(gsi, -1);
  422. xen_irq_init(irq);
  423. return irq;
  424. }
  425. static void xen_free_irq(unsigned irq)
  426. {
  427. struct irq_info *info = irq_get_handler_data(irq);
  428. if (WARN_ON(!info))
  429. return;
  430. list_del(&info->list);
  431. irq_set_handler_data(irq, NULL);
  432. WARN_ON(info->refcnt > 0);
  433. kfree(info);
  434. /* Legacy IRQ descriptors are managed by the arch. */
  435. if (irq < NR_IRQS_LEGACY)
  436. return;
  437. irq_free_desc(irq);
  438. }
  439. static void pirq_query_unmask(int irq)
  440. {
  441. struct physdev_irq_status_query irq_status;
  442. struct irq_info *info = info_for_irq(irq);
  443. BUG_ON(info->type != IRQT_PIRQ);
  444. irq_status.irq = pirq_from_irq(irq);
  445. if (HYPERVISOR_physdev_op(PHYSDEVOP_irq_status_query, &irq_status))
  446. irq_status.flags = 0;
  447. info->u.pirq.flags &= ~PIRQ_NEEDS_EOI;
  448. if (irq_status.flags & XENIRQSTAT_needs_eoi)
  449. info->u.pirq.flags |= PIRQ_NEEDS_EOI;
  450. }
  451. static bool probing_irq(int irq)
  452. {
  453. struct irq_desc *desc = irq_to_desc(irq);
  454. return desc && desc->action == NULL;
  455. }
  456. static void eoi_pirq(struct irq_data *data)
  457. {
  458. int evtchn = evtchn_from_irq(data->irq);
  459. struct physdev_eoi eoi = { .irq = pirq_from_irq(data->irq) };
  460. int rc = 0;
  461. irq_move_irq(data);
  462. if (VALID_EVTCHN(evtchn))
  463. clear_evtchn(evtchn);
  464. if (pirq_needs_eoi(data->irq)) {
  465. rc = HYPERVISOR_physdev_op(PHYSDEVOP_eoi, &eoi);
  466. WARN_ON(rc);
  467. }
  468. }
  469. static void mask_ack_pirq(struct irq_data *data)
  470. {
  471. disable_dynirq(data);
  472. eoi_pirq(data);
  473. }
  474. static unsigned int __startup_pirq(unsigned int irq)
  475. {
  476. struct evtchn_bind_pirq bind_pirq;
  477. struct irq_info *info = info_for_irq(irq);
  478. int evtchn = evtchn_from_irq(irq);
  479. int rc;
  480. BUG_ON(info->type != IRQT_PIRQ);
  481. if (VALID_EVTCHN(evtchn))
  482. goto out;
  483. bind_pirq.pirq = pirq_from_irq(irq);
  484. /* NB. We are happy to share unless we are probing. */
  485. bind_pirq.flags = info->u.pirq.flags & PIRQ_SHAREABLE ?
  486. BIND_PIRQ__WILL_SHARE : 0;
  487. rc = HYPERVISOR_event_channel_op(EVTCHNOP_bind_pirq, &bind_pirq);
  488. if (rc != 0) {
  489. if (!probing_irq(irq))
  490. pr_info("Failed to obtain physical IRQ %d\n", irq);
  491. return 0;
  492. }
  493. evtchn = bind_pirq.port;
  494. pirq_query_unmask(irq);
  495. evtchn_to_irq[evtchn] = irq;
  496. bind_evtchn_to_cpu(evtchn, 0);
  497. info->evtchn = evtchn;
  498. out:
  499. unmask_evtchn(evtchn);
  500. eoi_pirq(irq_get_irq_data(irq));
  501. return 0;
  502. }
  503. static unsigned int startup_pirq(struct irq_data *data)
  504. {
  505. return __startup_pirq(data->irq);
  506. }
  507. static void shutdown_pirq(struct irq_data *data)
  508. {
  509. struct evtchn_close close;
  510. unsigned int irq = data->irq;
  511. struct irq_info *info = info_for_irq(irq);
  512. int evtchn = evtchn_from_irq(irq);
  513. BUG_ON(info->type != IRQT_PIRQ);
  514. if (!VALID_EVTCHN(evtchn))
  515. return;
  516. mask_evtchn(evtchn);
  517. close.port = evtchn;
  518. if (HYPERVISOR_event_channel_op(EVTCHNOP_close, &close) != 0)
  519. BUG();
  520. bind_evtchn_to_cpu(evtchn, 0);
  521. evtchn_to_irq[evtchn] = -1;
  522. info->evtchn = 0;
  523. }
  524. static void enable_pirq(struct irq_data *data)
  525. {
  526. startup_pirq(data);
  527. }
  528. static void disable_pirq(struct irq_data *data)
  529. {
  530. disable_dynirq(data);
  531. }
  532. int xen_irq_from_gsi(unsigned gsi)
  533. {
  534. struct irq_info *info;
  535. list_for_each_entry(info, &xen_irq_list_head, list) {
  536. if (info->type != IRQT_PIRQ)
  537. continue;
  538. if (info->u.pirq.gsi == gsi)
  539. return info->irq;
  540. }
  541. return -1;
  542. }
  543. EXPORT_SYMBOL_GPL(xen_irq_from_gsi);
  544. /*
  545. * Do not make any assumptions regarding the relationship between the
  546. * IRQ number returned here and the Xen pirq argument.
  547. *
  548. * Note: We don't assign an event channel until the irq actually started
  549. * up. Return an existing irq if we've already got one for the gsi.
  550. *
  551. * Shareable implies level triggered, not shareable implies edge
  552. * triggered here.
  553. */
  554. int xen_bind_pirq_gsi_to_irq(unsigned gsi,
  555. unsigned pirq, int shareable, char *name)
  556. {
  557. int irq = -1;
  558. struct physdev_irq irq_op;
  559. mutex_lock(&irq_mapping_update_lock);
  560. irq = xen_irq_from_gsi(gsi);
  561. if (irq != -1) {
  562. pr_info("%s: returning irq %d for gsi %u\n",
  563. __func__, irq, gsi);
  564. goto out;
  565. }
  566. irq = xen_allocate_irq_gsi(gsi);
  567. if (irq < 0)
  568. goto out;
  569. irq_op.irq = irq;
  570. irq_op.vector = 0;
  571. /* Only the privileged domain can do this. For non-priv, the pcifront
  572. * driver provides a PCI bus that does the call to do exactly
  573. * this in the priv domain. */
  574. if (xen_initial_domain() &&
  575. HYPERVISOR_physdev_op(PHYSDEVOP_alloc_irq_vector, &irq_op)) {
  576. xen_free_irq(irq);
  577. irq = -ENOSPC;
  578. goto out;
  579. }
  580. xen_irq_info_pirq_init(irq, 0, pirq, gsi, DOMID_SELF,
  581. shareable ? PIRQ_SHAREABLE : 0);
  582. pirq_query_unmask(irq);
  583. /* We try to use the handler with the appropriate semantic for the
  584. * type of interrupt: if the interrupt is an edge triggered
  585. * interrupt we use handle_edge_irq.
  586. *
  587. * On the other hand if the interrupt is level triggered we use
  588. * handle_fasteoi_irq like the native code does for this kind of
  589. * interrupts.
  590. *
  591. * Depending on the Xen version, pirq_needs_eoi might return true
  592. * not only for level triggered interrupts but for edge triggered
  593. * interrupts too. In any case Xen always honors the eoi mechanism,
  594. * not injecting any more pirqs of the same kind if the first one
  595. * hasn't received an eoi yet. Therefore using the fasteoi handler
  596. * is the right choice either way.
  597. */
  598. if (shareable)
  599. irq_set_chip_and_handler_name(irq, &xen_pirq_chip,
  600. handle_fasteoi_irq, name);
  601. else
  602. irq_set_chip_and_handler_name(irq, &xen_pirq_chip,
  603. handle_edge_irq, name);
  604. out:
  605. mutex_unlock(&irq_mapping_update_lock);
  606. return irq;
  607. }
  608. #ifdef CONFIG_PCI_MSI
  609. int xen_allocate_pirq_msi(struct pci_dev *dev, struct msi_desc *msidesc)
  610. {
  611. int rc;
  612. struct physdev_get_free_pirq op_get_free_pirq;
  613. op_get_free_pirq.type = MAP_PIRQ_TYPE_MSI;
  614. rc = HYPERVISOR_physdev_op(PHYSDEVOP_get_free_pirq, &op_get_free_pirq);
  615. WARN_ONCE(rc == -ENOSYS,
  616. "hypervisor does not support the PHYSDEVOP_get_free_pirq interface\n");
  617. return rc ? -1 : op_get_free_pirq.pirq;
  618. }
  619. int xen_bind_pirq_msi_to_irq(struct pci_dev *dev, struct msi_desc *msidesc,
  620. int pirq, const char *name, domid_t domid)
  621. {
  622. int irq, ret;
  623. mutex_lock(&irq_mapping_update_lock);
  624. irq = xen_allocate_irq_dynamic();
  625. if (irq < 0)
  626. goto out;
  627. irq_set_chip_and_handler_name(irq, &xen_pirq_chip, handle_edge_irq,
  628. name);
  629. xen_irq_info_pirq_init(irq, 0, pirq, 0, domid, 0);
  630. ret = irq_set_msi_desc(irq, msidesc);
  631. if (ret < 0)
  632. goto error_irq;
  633. out:
  634. mutex_unlock(&irq_mapping_update_lock);
  635. return irq;
  636. error_irq:
  637. mutex_unlock(&irq_mapping_update_lock);
  638. xen_free_irq(irq);
  639. return ret;
  640. }
  641. #endif
  642. int xen_destroy_irq(int irq)
  643. {
  644. struct irq_desc *desc;
  645. struct physdev_unmap_pirq unmap_irq;
  646. struct irq_info *info = info_for_irq(irq);
  647. int rc = -ENOENT;
  648. mutex_lock(&irq_mapping_update_lock);
  649. desc = irq_to_desc(irq);
  650. if (!desc)
  651. goto out;
  652. if (xen_initial_domain()) {
  653. unmap_irq.pirq = info->u.pirq.pirq;
  654. unmap_irq.domid = info->u.pirq.domid;
  655. rc = HYPERVISOR_physdev_op(PHYSDEVOP_unmap_pirq, &unmap_irq);
  656. /* If another domain quits without making the pci_disable_msix
  657. * call, the Xen hypervisor takes care of freeing the PIRQs
  658. * (free_domain_pirqs).
  659. */
  660. if ((rc == -ESRCH && info->u.pirq.domid != DOMID_SELF))
  661. pr_info("domain %d does not have %d anymore\n",
  662. info->u.pirq.domid, info->u.pirq.pirq);
  663. else if (rc) {
  664. pr_warn("unmap irq failed %d\n", rc);
  665. goto out;
  666. }
  667. }
  668. xen_free_irq(irq);
  669. out:
  670. mutex_unlock(&irq_mapping_update_lock);
  671. return rc;
  672. }
  673. int xen_irq_from_pirq(unsigned pirq)
  674. {
  675. int irq;
  676. struct irq_info *info;
  677. mutex_lock(&irq_mapping_update_lock);
  678. list_for_each_entry(info, &xen_irq_list_head, list) {
  679. if (info->type != IRQT_PIRQ)
  680. continue;
  681. irq = info->irq;
  682. if (info->u.pirq.pirq == pirq)
  683. goto out;
  684. }
  685. irq = -1;
  686. out:
  687. mutex_unlock(&irq_mapping_update_lock);
  688. return irq;
  689. }
  690. int xen_pirq_from_irq(unsigned irq)
  691. {
  692. return pirq_from_irq(irq);
  693. }
  694. EXPORT_SYMBOL_GPL(xen_pirq_from_irq);
  695. int bind_evtchn_to_irq(unsigned int evtchn)
  696. {
  697. int irq;
  698. mutex_lock(&irq_mapping_update_lock);
  699. irq = evtchn_to_irq[evtchn];
  700. if (irq == -1) {
  701. irq = xen_allocate_irq_dynamic();
  702. if (irq < 0)
  703. goto out;
  704. irq_set_chip_and_handler_name(irq, &xen_dynamic_chip,
  705. handle_edge_irq, "event");
  706. xen_irq_info_evtchn_init(irq, evtchn);
  707. } else {
  708. struct irq_info *info = info_for_irq(irq);
  709. WARN_ON(info == NULL || info->type != IRQT_EVTCHN);
  710. }
  711. out:
  712. mutex_unlock(&irq_mapping_update_lock);
  713. return irq;
  714. }
  715. EXPORT_SYMBOL_GPL(bind_evtchn_to_irq);
  716. static int bind_ipi_to_irq(unsigned int ipi, unsigned int cpu)
  717. {
  718. struct evtchn_bind_ipi bind_ipi;
  719. int evtchn, irq;
  720. mutex_lock(&irq_mapping_update_lock);
  721. irq = per_cpu(ipi_to_irq, cpu)[ipi];
  722. if (irq == -1) {
  723. irq = xen_allocate_irq_dynamic();
  724. if (irq < 0)
  725. goto out;
  726. irq_set_chip_and_handler_name(irq, &xen_percpu_chip,
  727. handle_percpu_irq, "ipi");
  728. bind_ipi.vcpu = cpu;
  729. if (HYPERVISOR_event_channel_op(EVTCHNOP_bind_ipi,
  730. &bind_ipi) != 0)
  731. BUG();
  732. evtchn = bind_ipi.port;
  733. xen_irq_info_ipi_init(cpu, irq, evtchn, ipi);
  734. bind_evtchn_to_cpu(evtchn, cpu);
  735. } else {
  736. struct irq_info *info = info_for_irq(irq);
  737. WARN_ON(info == NULL || info->type != IRQT_IPI);
  738. }
  739. out:
  740. mutex_unlock(&irq_mapping_update_lock);
  741. return irq;
  742. }
  743. static int bind_interdomain_evtchn_to_irq(unsigned int remote_domain,
  744. unsigned int remote_port)
  745. {
  746. struct evtchn_bind_interdomain bind_interdomain;
  747. int err;
  748. bind_interdomain.remote_dom = remote_domain;
  749. bind_interdomain.remote_port = remote_port;
  750. err = HYPERVISOR_event_channel_op(EVTCHNOP_bind_interdomain,
  751. &bind_interdomain);
  752. return err ? : bind_evtchn_to_irq(bind_interdomain.local_port);
  753. }
  754. static int find_virq(unsigned int virq, unsigned int cpu)
  755. {
  756. struct evtchn_status status;
  757. int port, rc = -ENOENT;
  758. memset(&status, 0, sizeof(status));
  759. for (port = 0; port <= NR_EVENT_CHANNELS; port++) {
  760. status.dom = DOMID_SELF;
  761. status.port = port;
  762. rc = HYPERVISOR_event_channel_op(EVTCHNOP_status, &status);
  763. if (rc < 0)
  764. continue;
  765. if (status.status != EVTCHNSTAT_virq)
  766. continue;
  767. if (status.u.virq == virq && status.vcpu == cpu) {
  768. rc = port;
  769. break;
  770. }
  771. }
  772. return rc;
  773. }
  774. int bind_virq_to_irq(unsigned int virq, unsigned int cpu)
  775. {
  776. struct evtchn_bind_virq bind_virq;
  777. int evtchn, irq, ret;
  778. mutex_lock(&irq_mapping_update_lock);
  779. irq = per_cpu(virq_to_irq, cpu)[virq];
  780. if (irq == -1) {
  781. irq = xen_allocate_irq_dynamic();
  782. if (irq < 0)
  783. goto out;
  784. irq_set_chip_and_handler_name(irq, &xen_percpu_chip,
  785. handle_percpu_irq, "virq");
  786. bind_virq.virq = virq;
  787. bind_virq.vcpu = cpu;
  788. ret = HYPERVISOR_event_channel_op(EVTCHNOP_bind_virq,
  789. &bind_virq);
  790. if (ret == 0)
  791. evtchn = bind_virq.port;
  792. else {
  793. if (ret == -EEXIST)
  794. ret = find_virq(virq, cpu);
  795. BUG_ON(ret < 0);
  796. evtchn = ret;
  797. }
  798. xen_irq_info_virq_init(cpu, irq, evtchn, virq);
  799. bind_evtchn_to_cpu(evtchn, cpu);
  800. } else {
  801. struct irq_info *info = info_for_irq(irq);
  802. WARN_ON(info == NULL || info->type != IRQT_VIRQ);
  803. }
  804. out:
  805. mutex_unlock(&irq_mapping_update_lock);
  806. return irq;
  807. }
  808. static void unbind_from_irq(unsigned int irq)
  809. {
  810. struct evtchn_close close;
  811. int evtchn = evtchn_from_irq(irq);
  812. struct irq_info *info = irq_get_handler_data(irq);
  813. if (WARN_ON(!info))
  814. return;
  815. mutex_lock(&irq_mapping_update_lock);
  816. if (info->refcnt > 0) {
  817. info->refcnt--;
  818. if (info->refcnt != 0)
  819. goto done;
  820. }
  821. if (VALID_EVTCHN(evtchn)) {
  822. close.port = evtchn;
  823. if (HYPERVISOR_event_channel_op(EVTCHNOP_close, &close) != 0)
  824. BUG();
  825. switch (type_from_irq(irq)) {
  826. case IRQT_VIRQ:
  827. per_cpu(virq_to_irq, cpu_from_evtchn(evtchn))
  828. [virq_from_irq(irq)] = -1;
  829. break;
  830. case IRQT_IPI:
  831. per_cpu(ipi_to_irq, cpu_from_evtchn(evtchn))
  832. [ipi_from_irq(irq)] = -1;
  833. break;
  834. default:
  835. break;
  836. }
  837. /* Closed ports are implicitly re-bound to VCPU0. */
  838. bind_evtchn_to_cpu(evtchn, 0);
  839. evtchn_to_irq[evtchn] = -1;
  840. }
  841. BUG_ON(info_for_irq(irq)->type == IRQT_UNBOUND);
  842. xen_free_irq(irq);
  843. done:
  844. mutex_unlock(&irq_mapping_update_lock);
  845. }
  846. int bind_evtchn_to_irqhandler(unsigned int evtchn,
  847. irq_handler_t handler,
  848. unsigned long irqflags,
  849. const char *devname, void *dev_id)
  850. {
  851. int irq, retval;
  852. irq = bind_evtchn_to_irq(evtchn);
  853. if (irq < 0)
  854. return irq;
  855. retval = request_irq(irq, handler, irqflags, devname, dev_id);
  856. if (retval != 0) {
  857. unbind_from_irq(irq);
  858. return retval;
  859. }
  860. return irq;
  861. }
  862. EXPORT_SYMBOL_GPL(bind_evtchn_to_irqhandler);
  863. int bind_interdomain_evtchn_to_irqhandler(unsigned int remote_domain,
  864. unsigned int remote_port,
  865. irq_handler_t handler,
  866. unsigned long irqflags,
  867. const char *devname,
  868. void *dev_id)
  869. {
  870. int irq, retval;
  871. irq = bind_interdomain_evtchn_to_irq(remote_domain, remote_port);
  872. if (irq < 0)
  873. return irq;
  874. retval = request_irq(irq, handler, irqflags, devname, dev_id);
  875. if (retval != 0) {
  876. unbind_from_irq(irq);
  877. return retval;
  878. }
  879. return irq;
  880. }
  881. EXPORT_SYMBOL_GPL(bind_interdomain_evtchn_to_irqhandler);
  882. int bind_virq_to_irqhandler(unsigned int virq, unsigned int cpu,
  883. irq_handler_t handler,
  884. unsigned long irqflags, const char *devname, void *dev_id)
  885. {
  886. int irq, retval;
  887. irq = bind_virq_to_irq(virq, cpu);
  888. if (irq < 0)
  889. return irq;
  890. retval = request_irq(irq, handler, irqflags, devname, dev_id);
  891. if (retval != 0) {
  892. unbind_from_irq(irq);
  893. return retval;
  894. }
  895. return irq;
  896. }
  897. EXPORT_SYMBOL_GPL(bind_virq_to_irqhandler);
  898. int bind_ipi_to_irqhandler(enum ipi_vector ipi,
  899. unsigned int cpu,
  900. irq_handler_t handler,
  901. unsigned long irqflags,
  902. const char *devname,
  903. void *dev_id)
  904. {
  905. int irq, retval;
  906. irq = bind_ipi_to_irq(ipi, cpu);
  907. if (irq < 0)
  908. return irq;
  909. irqflags |= IRQF_NO_SUSPEND | IRQF_FORCE_RESUME | IRQF_EARLY_RESUME;
  910. retval = request_irq(irq, handler, irqflags, devname, dev_id);
  911. if (retval != 0) {
  912. unbind_from_irq(irq);
  913. return retval;
  914. }
  915. return irq;
  916. }
  917. void unbind_from_irqhandler(unsigned int irq, void *dev_id)
  918. {
  919. struct irq_info *info = irq_get_handler_data(irq);
  920. if (WARN_ON(!info))
  921. return;
  922. free_irq(irq, dev_id);
  923. unbind_from_irq(irq);
  924. }
  925. EXPORT_SYMBOL_GPL(unbind_from_irqhandler);
  926. int evtchn_make_refcounted(unsigned int evtchn)
  927. {
  928. int irq = evtchn_to_irq[evtchn];
  929. struct irq_info *info;
  930. if (irq == -1)
  931. return -ENOENT;
  932. info = irq_get_handler_data(irq);
  933. if (!info)
  934. return -ENOENT;
  935. WARN_ON(info->refcnt != -1);
  936. info->refcnt = 1;
  937. return 0;
  938. }
  939. EXPORT_SYMBOL_GPL(evtchn_make_refcounted);
  940. int evtchn_get(unsigned int evtchn)
  941. {
  942. int irq;
  943. struct irq_info *info;
  944. int err = -ENOENT;
  945. if (evtchn >= NR_EVENT_CHANNELS)
  946. return -EINVAL;
  947. mutex_lock(&irq_mapping_update_lock);
  948. irq = evtchn_to_irq[evtchn];
  949. if (irq == -1)
  950. goto done;
  951. info = irq_get_handler_data(irq);
  952. if (!info)
  953. goto done;
  954. err = -EINVAL;
  955. if (info->refcnt <= 0)
  956. goto done;
  957. info->refcnt++;
  958. err = 0;
  959. done:
  960. mutex_unlock(&irq_mapping_update_lock);
  961. return err;
  962. }
  963. EXPORT_SYMBOL_GPL(evtchn_get);
  964. void evtchn_put(unsigned int evtchn)
  965. {
  966. int irq = evtchn_to_irq[evtchn];
  967. if (WARN_ON(irq == -1))
  968. return;
  969. unbind_from_irq(irq);
  970. }
  971. EXPORT_SYMBOL_GPL(evtchn_put);
  972. void xen_send_IPI_one(unsigned int cpu, enum ipi_vector vector)
  973. {
  974. int irq;
  975. #ifdef CONFIG_X86
  976. if (unlikely(vector == XEN_NMI_VECTOR)) {
  977. int rc = HYPERVISOR_vcpu_op(VCPUOP_send_nmi, cpu, NULL);
  978. if (rc < 0)
  979. printk(KERN_WARNING "Sending nmi to CPU%d failed (rc:%d)\n", cpu, rc);
  980. return;
  981. }
  982. #endif
  983. irq = per_cpu(ipi_to_irq, cpu)[vector];
  984. BUG_ON(irq < 0);
  985. notify_remote_via_irq(irq);
  986. }
  987. irqreturn_t xen_debug_interrupt(int irq, void *dev_id)
  988. {
  989. struct shared_info *sh = HYPERVISOR_shared_info;
  990. int cpu = smp_processor_id();
  991. xen_ulong_t *cpu_evtchn = per_cpu(cpu_evtchn_mask, cpu);
  992. int i;
  993. unsigned long flags;
  994. static DEFINE_SPINLOCK(debug_lock);
  995. struct vcpu_info *v;
  996. spin_lock_irqsave(&debug_lock, flags);
  997. printk("\nvcpu %d\n ", cpu);
  998. for_each_online_cpu(i) {
  999. int pending;
  1000. v = per_cpu(xen_vcpu, i);
  1001. pending = (get_irq_regs() && i == cpu)
  1002. ? xen_irqs_disabled(get_irq_regs())
  1003. : v->evtchn_upcall_mask;
  1004. printk("%d: masked=%d pending=%d event_sel %0*"PRI_xen_ulong"\n ", i,
  1005. pending, v->evtchn_upcall_pending,
  1006. (int)(sizeof(v->evtchn_pending_sel)*2),
  1007. v->evtchn_pending_sel);
  1008. }
  1009. v = per_cpu(xen_vcpu, cpu);
  1010. printk("\npending:\n ");
  1011. for (i = ARRAY_SIZE(sh->evtchn_pending)-1; i >= 0; i--)
  1012. printk("%0*"PRI_xen_ulong"%s",
  1013. (int)sizeof(sh->evtchn_pending[0])*2,
  1014. sh->evtchn_pending[i],
  1015. i % 8 == 0 ? "\n " : " ");
  1016. printk("\nglobal mask:\n ");
  1017. for (i = ARRAY_SIZE(sh->evtchn_mask)-1; i >= 0; i--)
  1018. printk("%0*"PRI_xen_ulong"%s",
  1019. (int)(sizeof(sh->evtchn_mask[0])*2),
  1020. sh->evtchn_mask[i],
  1021. i % 8 == 0 ? "\n " : " ");
  1022. printk("\nglobally unmasked:\n ");
  1023. for (i = ARRAY_SIZE(sh->evtchn_mask)-1; i >= 0; i--)
  1024. printk("%0*"PRI_xen_ulong"%s",
  1025. (int)(sizeof(sh->evtchn_mask[0])*2),
  1026. sh->evtchn_pending[i] & ~sh->evtchn_mask[i],
  1027. i % 8 == 0 ? "\n " : " ");
  1028. printk("\nlocal cpu%d mask:\n ", cpu);
  1029. for (i = (NR_EVENT_CHANNELS/BITS_PER_EVTCHN_WORD)-1; i >= 0; i--)
  1030. printk("%0*"PRI_xen_ulong"%s", (int)(sizeof(cpu_evtchn[0])*2),
  1031. cpu_evtchn[i],
  1032. i % 8 == 0 ? "\n " : " ");
  1033. printk("\nlocally unmasked:\n ");
  1034. for (i = ARRAY_SIZE(sh->evtchn_mask)-1; i >= 0; i--) {
  1035. xen_ulong_t pending = sh->evtchn_pending[i]
  1036. & ~sh->evtchn_mask[i]
  1037. & cpu_evtchn[i];
  1038. printk("%0*"PRI_xen_ulong"%s",
  1039. (int)(sizeof(sh->evtchn_mask[0])*2),
  1040. pending, i % 8 == 0 ? "\n " : " ");
  1041. }
  1042. printk("\npending list:\n");
  1043. for (i = 0; i < NR_EVENT_CHANNELS; i++) {
  1044. if (sync_test_bit(i, BM(sh->evtchn_pending))) {
  1045. int word_idx = i / BITS_PER_EVTCHN_WORD;
  1046. printk(" %d: event %d -> irq %d%s%s%s\n",
  1047. cpu_from_evtchn(i), i,
  1048. evtchn_to_irq[i],
  1049. sync_test_bit(word_idx, BM(&v->evtchn_pending_sel))
  1050. ? "" : " l2-clear",
  1051. !sync_test_bit(i, BM(sh->evtchn_mask))
  1052. ? "" : " globally-masked",
  1053. sync_test_bit(i, BM(cpu_evtchn))
  1054. ? "" : " locally-masked");
  1055. }
  1056. }
  1057. spin_unlock_irqrestore(&debug_lock, flags);
  1058. return IRQ_HANDLED;
  1059. }
  1060. static DEFINE_PER_CPU(unsigned, xed_nesting_count);
  1061. static DEFINE_PER_CPU(unsigned int, current_word_idx);
  1062. static DEFINE_PER_CPU(unsigned int, current_bit_idx);
  1063. /*
  1064. * Mask out the i least significant bits of w
  1065. */
  1066. #define MASK_LSBS(w, i) (w & ((~((xen_ulong_t)0UL)) << i))
  1067. /*
  1068. * Search the CPUs pending events bitmasks. For each one found, map
  1069. * the event number to an irq, and feed it into do_IRQ() for
  1070. * handling.
  1071. *
  1072. * Xen uses a two-level bitmap to speed searching. The first level is
  1073. * a bitset of words which contain pending event bits. The second
  1074. * level is a bitset of pending events themselves.
  1075. */
  1076. static void __xen_evtchn_do_upcall(void)
  1077. {
  1078. int start_word_idx, start_bit_idx;
  1079. int word_idx, bit_idx;
  1080. int i, irq;
  1081. int cpu = get_cpu();
  1082. struct shared_info *s = HYPERVISOR_shared_info;
  1083. struct vcpu_info *vcpu_info = __this_cpu_read(xen_vcpu);
  1084. unsigned count;
  1085. do {
  1086. xen_ulong_t pending_words;
  1087. xen_ulong_t pending_bits;
  1088. struct irq_desc *desc;
  1089. vcpu_info->evtchn_upcall_pending = 0;
  1090. if (__this_cpu_inc_return(xed_nesting_count) - 1)
  1091. goto out;
  1092. /*
  1093. * Master flag must be cleared /before/ clearing
  1094. * selector flag. xchg_xen_ulong must contain an
  1095. * appropriate barrier.
  1096. */
  1097. if ((irq = per_cpu(virq_to_irq, cpu)[VIRQ_TIMER]) != -1) {
  1098. int evtchn = evtchn_from_irq(irq);
  1099. word_idx = evtchn / BITS_PER_LONG;
  1100. pending_bits = evtchn % BITS_PER_LONG;
  1101. if (active_evtchns(cpu, s, word_idx) & (1ULL << pending_bits)) {
  1102. desc = irq_to_desc(irq);
  1103. if (desc)
  1104. generic_handle_irq_desc(irq, desc);
  1105. }
  1106. }
  1107. pending_words = xchg_xen_ulong(&vcpu_info->evtchn_pending_sel, 0);
  1108. start_word_idx = __this_cpu_read(current_word_idx);
  1109. start_bit_idx = __this_cpu_read(current_bit_idx);
  1110. word_idx = start_word_idx;
  1111. for (i = 0; pending_words != 0; i++) {
  1112. xen_ulong_t words;
  1113. words = MASK_LSBS(pending_words, word_idx);
  1114. /*
  1115. * If we masked out all events, wrap to beginning.
  1116. */
  1117. if (words == 0) {
  1118. word_idx = 0;
  1119. bit_idx = 0;
  1120. continue;
  1121. }
  1122. word_idx = EVTCHN_FIRST_BIT(words);
  1123. pending_bits = active_evtchns(cpu, s, word_idx);
  1124. bit_idx = 0; /* usually scan entire word from start */
  1125. /*
  1126. * We scan the starting word in two parts.
  1127. *
  1128. * 1st time: start in the middle, scanning the
  1129. * upper bits.
  1130. *
  1131. * 2nd time: scan the whole word (not just the
  1132. * parts skipped in the first pass) -- if an
  1133. * event in the previously scanned bits is
  1134. * pending again it would just be scanned on
  1135. * the next loop anyway.
  1136. */
  1137. if (word_idx == start_word_idx) {
  1138. if (i == 0)
  1139. bit_idx = start_bit_idx;
  1140. }
  1141. do {
  1142. xen_ulong_t bits;
  1143. int port;
  1144. bits = MASK_LSBS(pending_bits, bit_idx);
  1145. /* If we masked out all events, move on. */
  1146. if (bits == 0)
  1147. break;
  1148. bit_idx = EVTCHN_FIRST_BIT(bits);
  1149. /* Process port. */
  1150. port = (word_idx * BITS_PER_EVTCHN_WORD) + bit_idx;
  1151. irq = evtchn_to_irq[port];
  1152. if (irq != -1) {
  1153. desc = irq_to_desc(irq);
  1154. if (desc)
  1155. generic_handle_irq_desc(irq, desc);
  1156. }
  1157. bit_idx = (bit_idx + 1) % BITS_PER_EVTCHN_WORD;
  1158. /* Next caller starts at last processed + 1 */
  1159. __this_cpu_write(current_word_idx,
  1160. bit_idx ? word_idx :
  1161. (word_idx+1) % BITS_PER_EVTCHN_WORD);
  1162. __this_cpu_write(current_bit_idx, bit_idx);
  1163. } while (bit_idx != 0);
  1164. /* Scan start_l1i twice; all others once. */
  1165. if ((word_idx != start_word_idx) || (i != 0))
  1166. pending_words &= ~(1UL << word_idx);
  1167. word_idx = (word_idx + 1) % BITS_PER_EVTCHN_WORD;
  1168. }
  1169. BUG_ON(!irqs_disabled());
  1170. count = __this_cpu_read(xed_nesting_count);
  1171. __this_cpu_write(xed_nesting_count, 0);
  1172. } while (count != 1 || vcpu_info->evtchn_upcall_pending);
  1173. out:
  1174. put_cpu();
  1175. }
  1176. void xen_evtchn_do_upcall(struct pt_regs *regs)
  1177. {
  1178. struct pt_regs *old_regs = set_irq_regs(regs);
  1179. irq_enter();
  1180. #ifdef CONFIG_X86
  1181. exit_idle();
  1182. #endif
  1183. __xen_evtchn_do_upcall();
  1184. irq_exit();
  1185. set_irq_regs(old_regs);
  1186. }
  1187. void xen_hvm_evtchn_do_upcall(void)
  1188. {
  1189. __xen_evtchn_do_upcall();
  1190. }
  1191. EXPORT_SYMBOL_GPL(xen_hvm_evtchn_do_upcall);
  1192. /* Rebind a new event channel to an existing irq. */
  1193. void rebind_evtchn_irq(int evtchn, int irq)
  1194. {
  1195. struct irq_info *info = info_for_irq(irq);
  1196. if (WARN_ON(!info))
  1197. return;
  1198. /* Make sure the irq is masked, since the new event channel
  1199. will also be masked. */
  1200. disable_irq(irq);
  1201. mutex_lock(&irq_mapping_update_lock);
  1202. /* After resume the irq<->evtchn mappings are all cleared out */
  1203. BUG_ON(evtchn_to_irq[evtchn] != -1);
  1204. /* Expect irq to have been bound before,
  1205. so there should be a proper type */
  1206. BUG_ON(info->type == IRQT_UNBOUND);
  1207. xen_irq_info_evtchn_init(irq, evtchn);
  1208. mutex_unlock(&irq_mapping_update_lock);
  1209. /* new event channels are always bound to cpu 0 */
  1210. irq_set_affinity(irq, cpumask_of(0));
  1211. /* Unmask the event channel. */
  1212. enable_irq(irq);
  1213. }
  1214. /* Rebind an evtchn so that it gets delivered to a specific cpu */
  1215. static int rebind_irq_to_cpu(unsigned irq, unsigned tcpu)
  1216. {
  1217. struct shared_info *s = HYPERVISOR_shared_info;
  1218. struct evtchn_bind_vcpu bind_vcpu;
  1219. int evtchn = evtchn_from_irq(irq);
  1220. int masked;
  1221. if (!VALID_EVTCHN(evtchn))
  1222. return -1;
  1223. /*
  1224. * Events delivered via platform PCI interrupts are always
  1225. * routed to vcpu 0 and hence cannot be rebound.
  1226. */
  1227. if (xen_hvm_domain() && !xen_have_vector_callback)
  1228. return -1;
  1229. /* Send future instances of this interrupt to other vcpu. */
  1230. bind_vcpu.port = evtchn;
  1231. bind_vcpu.vcpu = tcpu;
  1232. /*
  1233. * Mask the event while changing the VCPU binding to prevent
  1234. * it being delivered on an unexpected VCPU.
  1235. */
  1236. masked = sync_test_and_set_bit(evtchn, BM(s->evtchn_mask));
  1237. /*
  1238. * If this fails, it usually just indicates that we're dealing with a
  1239. * virq or IPI channel, which don't actually need to be rebound. Ignore
  1240. * it, but don't do the xenlinux-level rebind in that case.
  1241. */
  1242. if (HYPERVISOR_event_channel_op(EVTCHNOP_bind_vcpu, &bind_vcpu) >= 0)
  1243. bind_evtchn_to_cpu(evtchn, tcpu);
  1244. if (!masked)
  1245. unmask_evtchn(evtchn);
  1246. return 0;
  1247. }
  1248. static int set_affinity_irq(struct irq_data *data, const struct cpumask *dest,
  1249. bool force)
  1250. {
  1251. unsigned tcpu = cpumask_first(dest);
  1252. return rebind_irq_to_cpu(data->irq, tcpu);
  1253. }
  1254. int resend_irq_on_evtchn(unsigned int irq)
  1255. {
  1256. int masked, evtchn = evtchn_from_irq(irq);
  1257. struct shared_info *s = HYPERVISOR_shared_info;
  1258. if (!VALID_EVTCHN(evtchn))
  1259. return 1;
  1260. masked = sync_test_and_set_bit(evtchn, BM(s->evtchn_mask));
  1261. sync_set_bit(evtchn, BM(s->evtchn_pending));
  1262. if (!masked)
  1263. unmask_evtchn(evtchn);
  1264. return 1;
  1265. }
  1266. static void enable_dynirq(struct irq_data *data)
  1267. {
  1268. int evtchn = evtchn_from_irq(data->irq);
  1269. if (VALID_EVTCHN(evtchn))
  1270. unmask_evtchn(evtchn);
  1271. }
  1272. static void disable_dynirq(struct irq_data *data)
  1273. {
  1274. int evtchn = evtchn_from_irq(data->irq);
  1275. if (VALID_EVTCHN(evtchn))
  1276. mask_evtchn(evtchn);
  1277. }
  1278. static void ack_dynirq(struct irq_data *data)
  1279. {
  1280. int evtchn = evtchn_from_irq(data->irq);
  1281. irq_move_irq(data);
  1282. if (VALID_EVTCHN(evtchn))
  1283. clear_evtchn(evtchn);
  1284. }
  1285. static void mask_ack_dynirq(struct irq_data *data)
  1286. {
  1287. disable_dynirq(data);
  1288. ack_dynirq(data);
  1289. }
  1290. static int retrigger_dynirq(struct irq_data *data)
  1291. {
  1292. int evtchn = evtchn_from_irq(data->irq);
  1293. struct shared_info *sh = HYPERVISOR_shared_info;
  1294. int ret = 0;
  1295. if (VALID_EVTCHN(evtchn)) {
  1296. int masked;
  1297. masked = sync_test_and_set_bit(evtchn, BM(sh->evtchn_mask));
  1298. sync_set_bit(evtchn, BM(sh->evtchn_pending));
  1299. if (!masked)
  1300. unmask_evtchn(evtchn);
  1301. ret = 1;
  1302. }
  1303. return ret;
  1304. }
  1305. static void restore_pirqs(void)
  1306. {
  1307. int pirq, rc, irq, gsi;
  1308. struct physdev_map_pirq map_irq;
  1309. struct irq_info *info;
  1310. list_for_each_entry(info, &xen_irq_list_head, list) {
  1311. if (info->type != IRQT_PIRQ)
  1312. continue;
  1313. pirq = info->u.pirq.pirq;
  1314. gsi = info->u.pirq.gsi;
  1315. irq = info->irq;
  1316. /* save/restore of PT devices doesn't work, so at this point the
  1317. * only devices present are GSI based emulated devices */
  1318. if (!gsi)
  1319. continue;
  1320. map_irq.domid = DOMID_SELF;
  1321. map_irq.type = MAP_PIRQ_TYPE_GSI;
  1322. map_irq.index = gsi;
  1323. map_irq.pirq = pirq;
  1324. rc = HYPERVISOR_physdev_op(PHYSDEVOP_map_pirq, &map_irq);
  1325. if (rc) {
  1326. pr_warn("xen map irq failed gsi=%d irq=%d pirq=%d rc=%d\n",
  1327. gsi, irq, pirq, rc);
  1328. xen_free_irq(irq);
  1329. continue;
  1330. }
  1331. printk(KERN_DEBUG "xen: --> irq=%d, pirq=%d\n", irq, map_irq.pirq);
  1332. __startup_pirq(irq);
  1333. }
  1334. }
  1335. static void restore_cpu_virqs(unsigned int cpu)
  1336. {
  1337. struct evtchn_bind_virq bind_virq;
  1338. int virq, irq, evtchn;
  1339. for (virq = 0; virq < NR_VIRQS; virq++) {
  1340. if ((irq = per_cpu(virq_to_irq, cpu)[virq]) == -1)
  1341. continue;
  1342. BUG_ON(virq_from_irq(irq) != virq);
  1343. /* Get a new binding from Xen. */
  1344. bind_virq.virq = virq;
  1345. bind_virq.vcpu = cpu;
  1346. if (HYPERVISOR_event_channel_op(EVTCHNOP_bind_virq,
  1347. &bind_virq) != 0)
  1348. BUG();
  1349. evtchn = bind_virq.port;
  1350. /* Record the new mapping. */
  1351. xen_irq_info_virq_init(cpu, irq, evtchn, virq);
  1352. bind_evtchn_to_cpu(evtchn, cpu);
  1353. }
  1354. }
  1355. static void restore_cpu_ipis(unsigned int cpu)
  1356. {
  1357. struct evtchn_bind_ipi bind_ipi;
  1358. int ipi, irq, evtchn;
  1359. for (ipi = 0; ipi < XEN_NR_IPIS; ipi++) {
  1360. if ((irq = per_cpu(ipi_to_irq, cpu)[ipi]) == -1)
  1361. continue;
  1362. BUG_ON(ipi_from_irq(irq) != ipi);
  1363. /* Get a new binding from Xen. */
  1364. bind_ipi.vcpu = cpu;
  1365. if (HYPERVISOR_event_channel_op(EVTCHNOP_bind_ipi,
  1366. &bind_ipi) != 0)
  1367. BUG();
  1368. evtchn = bind_ipi.port;
  1369. /* Record the new mapping. */
  1370. xen_irq_info_ipi_init(cpu, irq, evtchn, ipi);
  1371. bind_evtchn_to_cpu(evtchn, cpu);
  1372. }
  1373. }
  1374. /* Clear an irq's pending state, in preparation for polling on it */
  1375. void xen_clear_irq_pending(int irq)
  1376. {
  1377. int evtchn = evtchn_from_irq(irq);
  1378. if (VALID_EVTCHN(evtchn))
  1379. clear_evtchn(evtchn);
  1380. }
  1381. EXPORT_SYMBOL(xen_clear_irq_pending);
  1382. void xen_set_irq_pending(int irq)
  1383. {
  1384. int evtchn = evtchn_from_irq(irq);
  1385. if (VALID_EVTCHN(evtchn))
  1386. set_evtchn(evtchn);
  1387. }
  1388. bool xen_test_irq_pending(int irq)
  1389. {
  1390. int evtchn = evtchn_from_irq(irq);
  1391. bool ret = false;
  1392. if (VALID_EVTCHN(evtchn))
  1393. ret = test_evtchn(evtchn);
  1394. return ret;
  1395. }
  1396. /* Poll waiting for an irq to become pending with timeout. In the usual case,
  1397. * the irq will be disabled so it won't deliver an interrupt. */
  1398. void xen_poll_irq_timeout(int irq, u64 timeout)
  1399. {
  1400. evtchn_port_t evtchn = evtchn_from_irq(irq);
  1401. if (VALID_EVTCHN(evtchn)) {
  1402. struct sched_poll poll;
  1403. poll.nr_ports = 1;
  1404. poll.timeout = timeout;
  1405. set_xen_guest_handle(poll.ports, &evtchn);
  1406. if (HYPERVISOR_sched_op(SCHEDOP_poll, &poll) != 0)
  1407. BUG();
  1408. }
  1409. }
  1410. EXPORT_SYMBOL(xen_poll_irq_timeout);
  1411. /* Poll waiting for an irq to become pending. In the usual case, the
  1412. * irq will be disabled so it won't deliver an interrupt. */
  1413. void xen_poll_irq(int irq)
  1414. {
  1415. xen_poll_irq_timeout(irq, 0 /* no timeout */);
  1416. }
  1417. /* Check whether the IRQ line is shared with other guests. */
  1418. int xen_test_irq_shared(int irq)
  1419. {
  1420. struct irq_info *info = info_for_irq(irq);
  1421. struct physdev_irq_status_query irq_status;
  1422. if (WARN_ON(!info))
  1423. return -ENOENT;
  1424. irq_status.irq = info->u.pirq.pirq;
  1425. if (HYPERVISOR_physdev_op(PHYSDEVOP_irq_status_query, &irq_status))
  1426. return 0;
  1427. return !(irq_status.flags & XENIRQSTAT_shared);
  1428. }
  1429. EXPORT_SYMBOL_GPL(xen_test_irq_shared);
  1430. void xen_irq_resume(void)
  1431. {
  1432. unsigned int cpu, evtchn;
  1433. struct irq_info *info;
  1434. init_evtchn_cpu_bindings();
  1435. /* New event-channel space is not 'live' yet. */
  1436. for (evtchn = 0; evtchn < NR_EVENT_CHANNELS; evtchn++)
  1437. mask_evtchn(evtchn);
  1438. /* No IRQ <-> event-channel mappings. */
  1439. list_for_each_entry(info, &xen_irq_list_head, list)
  1440. info->evtchn = 0; /* zap event-channel binding */
  1441. for (evtchn = 0; evtchn < NR_EVENT_CHANNELS; evtchn++)
  1442. evtchn_to_irq[evtchn] = -1;
  1443. for_each_possible_cpu(cpu) {
  1444. restore_cpu_virqs(cpu);
  1445. restore_cpu_ipis(cpu);
  1446. }
  1447. restore_pirqs();
  1448. }
  1449. static struct irq_chip xen_dynamic_chip __read_mostly = {
  1450. .name = "xen-dyn",
  1451. .irq_disable = disable_dynirq,
  1452. .irq_mask = disable_dynirq,
  1453. .irq_unmask = enable_dynirq,
  1454. .irq_ack = ack_dynirq,
  1455. .irq_mask_ack = mask_ack_dynirq,
  1456. .irq_set_affinity = set_affinity_irq,
  1457. .irq_retrigger = retrigger_dynirq,
  1458. };
  1459. static struct irq_chip xen_pirq_chip __read_mostly = {
  1460. .name = "xen-pirq",
  1461. .irq_startup = startup_pirq,
  1462. .irq_shutdown = shutdown_pirq,
  1463. .irq_enable = enable_pirq,
  1464. .irq_disable = disable_pirq,
  1465. .irq_mask = disable_dynirq,
  1466. .irq_unmask = enable_dynirq,
  1467. .irq_ack = eoi_pirq,
  1468. .irq_eoi = eoi_pirq,
  1469. .irq_mask_ack = mask_ack_pirq,
  1470. .irq_set_affinity = set_affinity_irq,
  1471. .irq_retrigger = retrigger_dynirq,
  1472. };
  1473. static struct irq_chip xen_percpu_chip __read_mostly = {
  1474. .name = "xen-percpu",
  1475. .irq_disable = disable_dynirq,
  1476. .irq_mask = disable_dynirq,
  1477. .irq_unmask = enable_dynirq,
  1478. .irq_ack = ack_dynirq,
  1479. };
  1480. int xen_set_callback_via(uint64_t via)
  1481. {
  1482. struct xen_hvm_param a;
  1483. a.domid = DOMID_SELF;
  1484. a.index = HVM_PARAM_CALLBACK_IRQ;
  1485. a.value = via;
  1486. return HYPERVISOR_hvm_op(HVMOP_set_param, &a);
  1487. }
  1488. EXPORT_SYMBOL_GPL(xen_set_callback_via);
  1489. #ifdef CONFIG_XEN_PVHVM
  1490. /* Vector callbacks are better than PCI interrupts to receive event
  1491. * channel notifications because we can receive vector callbacks on any
  1492. * vcpu and we don't need PCI support or APIC interactions. */
  1493. void xen_callback_vector(void)
  1494. {
  1495. int rc;
  1496. uint64_t callback_via;
  1497. if (xen_have_vector_callback) {
  1498. callback_via = HVM_CALLBACK_VECTOR(HYPERVISOR_CALLBACK_VECTOR);
  1499. rc = xen_set_callback_via(callback_via);
  1500. if (rc) {
  1501. pr_err("Request for Xen HVM callback vector failed\n");
  1502. xen_have_vector_callback = 0;
  1503. return;
  1504. }
  1505. pr_info("Xen HVM callback vector for event delivery is enabled\n");
  1506. /* in the restore case the vector has already been allocated */
  1507. if (!test_bit(HYPERVISOR_CALLBACK_VECTOR, used_vectors))
  1508. alloc_intr_gate(HYPERVISOR_CALLBACK_VECTOR,
  1509. xen_hvm_callback_vector);
  1510. }
  1511. }
  1512. #else
  1513. void xen_callback_vector(void) {}
  1514. #endif
  1515. void __init xen_init_IRQ(void)
  1516. {
  1517. int i;
  1518. evtchn_to_irq = kcalloc(NR_EVENT_CHANNELS, sizeof(*evtchn_to_irq),
  1519. GFP_KERNEL);
  1520. BUG_ON(!evtchn_to_irq);
  1521. for (i = 0; i < NR_EVENT_CHANNELS; i++)
  1522. evtchn_to_irq[i] = -1;
  1523. init_evtchn_cpu_bindings();
  1524. /* No event channels are 'live' right now. */
  1525. for (i = 0; i < NR_EVENT_CHANNELS; i++)
  1526. mask_evtchn(i);
  1527. pirq_needs_eoi = pirq_needs_eoi_flag;
  1528. #ifdef CONFIG_X86
  1529. if (xen_hvm_domain()) {
  1530. xen_callback_vector();
  1531. native_init_IRQ();
  1532. /* pci_xen_hvm_init must be called after native_init_IRQ so that
  1533. * __acpi_register_gsi can point at the right function */
  1534. pci_xen_hvm_init();
  1535. } else {
  1536. int rc;
  1537. struct physdev_pirq_eoi_gmfn eoi_gmfn;
  1538. irq_ctx_init(smp_processor_id());
  1539. if (xen_initial_domain())
  1540. pci_xen_initial_domain();
  1541. pirq_eoi_map = (void *)__get_free_page(GFP_KERNEL|__GFP_ZERO);
  1542. eoi_gmfn.gmfn = virt_to_mfn(pirq_eoi_map);
  1543. rc = HYPERVISOR_physdev_op(PHYSDEVOP_pirq_eoi_gmfn_v2, &eoi_gmfn);
  1544. if (rc != 0) {
  1545. free_page((unsigned long) pirq_eoi_map);
  1546. pirq_eoi_map = NULL;
  1547. } else
  1548. pirq_needs_eoi = pirq_check_eoi_map;
  1549. }
  1550. #endif
  1551. }