quirks.c 44 KB

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  1. /*
  2. * This file contains work-arounds for many known PCI hardware
  3. * bugs. Devices present only on certain architectures (host
  4. * bridges et cetera) should be handled in arch-specific code.
  5. *
  6. * Note: any quirks for hotpluggable devices must _NOT_ be declared __init.
  7. *
  8. * Copyright (c) 1999 Martin Mares <mj@ucw.cz>
  9. *
  10. * The bridge optimization stuff has been removed. If you really
  11. * have a silly BIOS which is unable to set your host bridge right,
  12. * use the PowerTweak utility (see http://powertweak.sourceforge.net).
  13. */
  14. #include <linux/config.h>
  15. #include <linux/types.h>
  16. #include <linux/kernel.h>
  17. #include <linux/pci.h>
  18. #include <linux/init.h>
  19. #include <linux/delay.h>
  20. #include "pci.h"
  21. /* Deal with broken BIOS'es that neglect to enable passive release,
  22. which can cause problems in combination with the 82441FX/PPro MTRRs */
  23. static void __devinit quirk_passive_release(struct pci_dev *dev)
  24. {
  25. struct pci_dev *d = NULL;
  26. unsigned char dlc;
  27. /* We have to make sure a particular bit is set in the PIIX3
  28. ISA bridge, so we have to go out and find it. */
  29. while ((d = pci_get_device(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82371SB_0, d))) {
  30. pci_read_config_byte(d, 0x82, &dlc);
  31. if (!(dlc & 1<<1)) {
  32. printk(KERN_ERR "PCI: PIIX3: Enabling Passive Release on %s\n", pci_name(d));
  33. dlc |= 1<<1;
  34. pci_write_config_byte(d, 0x82, dlc);
  35. }
  36. }
  37. }
  38. DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82441, quirk_passive_release );
  39. /* The VIA VP2/VP3/MVP3 seem to have some 'features'. There may be a workaround
  40. but VIA don't answer queries. If you happen to have good contacts at VIA
  41. ask them for me please -- Alan
  42. This appears to be BIOS not version dependent. So presumably there is a
  43. chipset level fix */
  44. int isa_dma_bridge_buggy; /* Exported */
  45. static void __devinit quirk_isa_dma_hangs(struct pci_dev *dev)
  46. {
  47. if (!isa_dma_bridge_buggy) {
  48. isa_dma_bridge_buggy=1;
  49. printk(KERN_INFO "Activating ISA DMA hang workarounds.\n");
  50. }
  51. }
  52. /*
  53. * Its not totally clear which chipsets are the problematic ones
  54. * We know 82C586 and 82C596 variants are affected.
  55. */
  56. DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C586_0, quirk_isa_dma_hangs );
  57. DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C596, quirk_isa_dma_hangs );
  58. DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82371SB_0, quirk_isa_dma_hangs );
  59. DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AL, PCI_DEVICE_ID_AL_M1533, quirk_isa_dma_hangs );
  60. DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_NEC, PCI_DEVICE_ID_NEC_CBUS_1, quirk_isa_dma_hangs );
  61. DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_NEC, PCI_DEVICE_ID_NEC_CBUS_2, quirk_isa_dma_hangs );
  62. DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_NEC, PCI_DEVICE_ID_NEC_CBUS_3, quirk_isa_dma_hangs );
  63. int pci_pci_problems;
  64. /*
  65. * Chipsets where PCI->PCI transfers vanish or hang
  66. */
  67. static void __devinit quirk_nopcipci(struct pci_dev *dev)
  68. {
  69. if ((pci_pci_problems & PCIPCI_FAIL)==0) {
  70. printk(KERN_INFO "Disabling direct PCI/PCI transfers.\n");
  71. pci_pci_problems |= PCIPCI_FAIL;
  72. }
  73. }
  74. DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_5597, quirk_nopcipci );
  75. DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_496, quirk_nopcipci );
  76. /*
  77. * Triton requires workarounds to be used by the drivers
  78. */
  79. static void __devinit quirk_triton(struct pci_dev *dev)
  80. {
  81. if ((pci_pci_problems&PCIPCI_TRITON)==0) {
  82. printk(KERN_INFO "Limiting direct PCI/PCI transfers.\n");
  83. pci_pci_problems |= PCIPCI_TRITON;
  84. }
  85. }
  86. DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82437, quirk_triton );
  87. DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82437VX, quirk_triton );
  88. DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82439, quirk_triton );
  89. DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82439TX, quirk_triton );
  90. /*
  91. * VIA Apollo KT133 needs PCI latency patch
  92. * Made according to a windows driver based patch by George E. Breese
  93. * see PCI Latency Adjust on http://www.viahardware.com/download/viatweak.shtm
  94. * Also see http://www.au-ja.org/review-kt133a-1-en.phtml for
  95. * the info on which Mr Breese based his work.
  96. *
  97. * Updated based on further information from the site and also on
  98. * information provided by VIA
  99. */
  100. static void __devinit quirk_vialatency(struct pci_dev *dev)
  101. {
  102. struct pci_dev *p;
  103. u8 rev;
  104. u8 busarb;
  105. /* Ok we have a potential problem chipset here. Now see if we have
  106. a buggy southbridge */
  107. p = pci_get_device(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C686, NULL);
  108. if (p!=NULL) {
  109. pci_read_config_byte(p, PCI_CLASS_REVISION, &rev);
  110. /* 0x40 - 0x4f == 686B, 0x10 - 0x2f == 686A; thanks Dan Hollis */
  111. /* Check for buggy part revisions */
  112. if (rev < 0x40 || rev > 0x42)
  113. goto exit;
  114. } else {
  115. p = pci_get_device(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8231, NULL);
  116. if (p==NULL) /* No problem parts */
  117. goto exit;
  118. pci_read_config_byte(p, PCI_CLASS_REVISION, &rev);
  119. /* Check for buggy part revisions */
  120. if (rev < 0x10 || rev > 0x12)
  121. goto exit;
  122. }
  123. /*
  124. * Ok we have the problem. Now set the PCI master grant to
  125. * occur every master grant. The apparent bug is that under high
  126. * PCI load (quite common in Linux of course) you can get data
  127. * loss when the CPU is held off the bus for 3 bus master requests
  128. * This happens to include the IDE controllers....
  129. *
  130. * VIA only apply this fix when an SB Live! is present but under
  131. * both Linux and Windows this isnt enough, and we have seen
  132. * corruption without SB Live! but with things like 3 UDMA IDE
  133. * controllers. So we ignore that bit of the VIA recommendation..
  134. */
  135. pci_read_config_byte(dev, 0x76, &busarb);
  136. /* Set bit 4 and bi 5 of byte 76 to 0x01
  137. "Master priority rotation on every PCI master grant */
  138. busarb &= ~(1<<5);
  139. busarb |= (1<<4);
  140. pci_write_config_byte(dev, 0x76, busarb);
  141. printk(KERN_INFO "Applying VIA southbridge workaround.\n");
  142. exit:
  143. pci_dev_put(p);
  144. }
  145. DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8363_0, quirk_vialatency );
  146. DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8371_1, quirk_vialatency );
  147. DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8361, quirk_vialatency );
  148. /*
  149. * VIA Apollo VP3 needs ETBF on BT848/878
  150. */
  151. static void __devinit quirk_viaetbf(struct pci_dev *dev)
  152. {
  153. if ((pci_pci_problems&PCIPCI_VIAETBF)==0) {
  154. printk(KERN_INFO "Limiting direct PCI/PCI transfers.\n");
  155. pci_pci_problems |= PCIPCI_VIAETBF;
  156. }
  157. }
  158. DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C597_0, quirk_viaetbf );
  159. static void __devinit quirk_vsfx(struct pci_dev *dev)
  160. {
  161. if ((pci_pci_problems&PCIPCI_VSFX)==0) {
  162. printk(KERN_INFO "Limiting direct PCI/PCI transfers.\n");
  163. pci_pci_problems |= PCIPCI_VSFX;
  164. }
  165. }
  166. DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C576, quirk_vsfx );
  167. /*
  168. * Ali Magik requires workarounds to be used by the drivers
  169. * that DMA to AGP space. Latency must be set to 0xA and triton
  170. * workaround applied too
  171. * [Info kindly provided by ALi]
  172. */
  173. static void __init quirk_alimagik(struct pci_dev *dev)
  174. {
  175. if ((pci_pci_problems&PCIPCI_ALIMAGIK)==0) {
  176. printk(KERN_INFO "Limiting direct PCI/PCI transfers.\n");
  177. pci_pci_problems |= PCIPCI_ALIMAGIK|PCIPCI_TRITON;
  178. }
  179. }
  180. DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AL, PCI_DEVICE_ID_AL_M1647, quirk_alimagik );
  181. DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AL, PCI_DEVICE_ID_AL_M1651, quirk_alimagik );
  182. /*
  183. * Natoma has some interesting boundary conditions with Zoran stuff
  184. * at least
  185. */
  186. static void __devinit quirk_natoma(struct pci_dev *dev)
  187. {
  188. if ((pci_pci_problems&PCIPCI_NATOMA)==0) {
  189. printk(KERN_INFO "Limiting direct PCI/PCI transfers.\n");
  190. pci_pci_problems |= PCIPCI_NATOMA;
  191. }
  192. }
  193. DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82441, quirk_natoma );
  194. DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82443LX_0, quirk_natoma );
  195. DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82443LX_1, quirk_natoma );
  196. DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82443BX_0, quirk_natoma );
  197. DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82443BX_1, quirk_natoma );
  198. DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82443BX_2, quirk_natoma );
  199. /*
  200. * This chip can cause PCI parity errors if config register 0xA0 is read
  201. * while DMAs are occurring.
  202. */
  203. static void __devinit quirk_citrine(struct pci_dev *dev)
  204. {
  205. dev->cfg_size = 0xA0;
  206. }
  207. DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_IBM, PCI_DEVICE_ID_IBM_CITRINE, quirk_citrine );
  208. /*
  209. * S3 868 and 968 chips report region size equal to 32M, but they decode 64M.
  210. * If it's needed, re-allocate the region.
  211. */
  212. static void __devinit quirk_s3_64M(struct pci_dev *dev)
  213. {
  214. struct resource *r = &dev->resource[0];
  215. if ((r->start & 0x3ffffff) || r->end != r->start + 0x3ffffff) {
  216. r->start = 0;
  217. r->end = 0x3ffffff;
  218. }
  219. }
  220. DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_S3, PCI_DEVICE_ID_S3_868, quirk_s3_64M );
  221. DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_S3, PCI_DEVICE_ID_S3_968, quirk_s3_64M );
  222. static void __devinit quirk_io_region(struct pci_dev *dev, unsigned region, unsigned size, int nr)
  223. {
  224. region &= ~(size-1);
  225. if (region) {
  226. struct resource *res = dev->resource + nr;
  227. res->name = pci_name(dev);
  228. res->start = region;
  229. res->end = region + size - 1;
  230. res->flags = IORESOURCE_IO;
  231. pci_claim_resource(dev, nr);
  232. }
  233. }
  234. /*
  235. * ATI Northbridge setups MCE the processor if you even
  236. * read somewhere between 0x3b0->0x3bb or read 0x3d3
  237. */
  238. static void __devinit quirk_ati_exploding_mce(struct pci_dev *dev)
  239. {
  240. printk(KERN_INFO "ATI Northbridge, reserving I/O ports 0x3b0 to 0x3bb.\n");
  241. /* Mae rhaid i ni beidio ag edrych ar y lleoliadiau I/O hyn */
  242. request_region(0x3b0, 0x0C, "RadeonIGP");
  243. request_region(0x3d3, 0x01, "RadeonIGP");
  244. }
  245. DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_RS100, quirk_ati_exploding_mce );
  246. /*
  247. * Let's make the southbridge information explicit instead
  248. * of having to worry about people probing the ACPI areas,
  249. * for example.. (Yes, it happens, and if you read the wrong
  250. * ACPI register it will put the machine to sleep with no
  251. * way of waking it up again. Bummer).
  252. *
  253. * ALI M7101: Two IO regions pointed to by words at
  254. * 0xE0 (64 bytes of ACPI registers)
  255. * 0xE2 (32 bytes of SMB registers)
  256. */
  257. static void __devinit quirk_ali7101_acpi(struct pci_dev *dev)
  258. {
  259. u16 region;
  260. pci_read_config_word(dev, 0xE0, &region);
  261. quirk_io_region(dev, region, 64, PCI_BRIDGE_RESOURCES);
  262. pci_read_config_word(dev, 0xE2, &region);
  263. quirk_io_region(dev, region, 32, PCI_BRIDGE_RESOURCES+1);
  264. }
  265. DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_AL, PCI_DEVICE_ID_AL_M7101, quirk_ali7101_acpi );
  266. /*
  267. * PIIX4 ACPI: Two IO regions pointed to by longwords at
  268. * 0x40 (64 bytes of ACPI registers)
  269. * 0x90 (32 bytes of SMB registers)
  270. */
  271. static void __devinit quirk_piix4_acpi(struct pci_dev *dev)
  272. {
  273. u32 region;
  274. pci_read_config_dword(dev, 0x40, &region);
  275. quirk_io_region(dev, region, 64, PCI_BRIDGE_RESOURCES);
  276. pci_read_config_dword(dev, 0x90, &region);
  277. quirk_io_region(dev, region, 32, PCI_BRIDGE_RESOURCES+1);
  278. }
  279. DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82371AB_3, quirk_piix4_acpi );
  280. /*
  281. * ICH4, ICH4-M, ICH5, ICH5-M ACPI: Three IO regions pointed to by longwords at
  282. * 0x40 (128 bytes of ACPI, GPIO & TCO registers)
  283. * 0x58 (64 bytes of GPIO I/O space)
  284. */
  285. static void __devinit quirk_ich4_lpc_acpi(struct pci_dev *dev)
  286. {
  287. u32 region;
  288. pci_read_config_dword(dev, 0x40, &region);
  289. quirk_io_region(dev, region, 128, PCI_BRIDGE_RESOURCES);
  290. pci_read_config_dword(dev, 0x58, &region);
  291. quirk_io_region(dev, region, 64, PCI_BRIDGE_RESOURCES+1);
  292. }
  293. DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801AA_0, quirk_ich4_lpc_acpi );
  294. DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801AB_0, quirk_ich4_lpc_acpi );
  295. DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801BA_0, quirk_ich4_lpc_acpi );
  296. DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801BA_10, quirk_ich4_lpc_acpi );
  297. DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801CA_0, quirk_ich4_lpc_acpi );
  298. DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801CA_12, quirk_ich4_lpc_acpi );
  299. DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801DB_0, quirk_ich4_lpc_acpi );
  300. DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801DB_12, quirk_ich4_lpc_acpi );
  301. DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801EB_0, quirk_ich4_lpc_acpi );
  302. /*
  303. * VIA ACPI: One IO region pointed to by longword at
  304. * 0x48 or 0x20 (256 bytes of ACPI registers)
  305. */
  306. static void __devinit quirk_vt82c586_acpi(struct pci_dev *dev)
  307. {
  308. u8 rev;
  309. u32 region;
  310. pci_read_config_byte(dev, PCI_CLASS_REVISION, &rev);
  311. if (rev & 0x10) {
  312. pci_read_config_dword(dev, 0x48, &region);
  313. region &= PCI_BASE_ADDRESS_IO_MASK;
  314. quirk_io_region(dev, region, 256, PCI_BRIDGE_RESOURCES);
  315. }
  316. }
  317. DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C586_3, quirk_vt82c586_acpi );
  318. /*
  319. * VIA VT82C686 ACPI: Three IO region pointed to by (long)words at
  320. * 0x48 (256 bytes of ACPI registers)
  321. * 0x70 (128 bytes of hardware monitoring register)
  322. * 0x90 (16 bytes of SMB registers)
  323. */
  324. static void __devinit quirk_vt82c686_acpi(struct pci_dev *dev)
  325. {
  326. u16 hm;
  327. u32 smb;
  328. quirk_vt82c586_acpi(dev);
  329. pci_read_config_word(dev, 0x70, &hm);
  330. hm &= PCI_BASE_ADDRESS_IO_MASK;
  331. quirk_io_region(dev, hm, 128, PCI_BRIDGE_RESOURCES + 1);
  332. pci_read_config_dword(dev, 0x90, &smb);
  333. smb &= PCI_BASE_ADDRESS_IO_MASK;
  334. quirk_io_region(dev, smb, 16, PCI_BRIDGE_RESOURCES + 2);
  335. }
  336. DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C686_4, quirk_vt82c686_acpi );
  337. #ifdef CONFIG_X86_IO_APIC
  338. #include <asm/io_apic.h>
  339. /*
  340. * VIA 686A/B: If an IO-APIC is active, we need to route all on-chip
  341. * devices to the external APIC.
  342. *
  343. * TODO: When we have device-specific interrupt routers,
  344. * this code will go away from quirks.
  345. */
  346. static void __devinit quirk_via_ioapic(struct pci_dev *dev)
  347. {
  348. u8 tmp;
  349. if (nr_ioapics < 1)
  350. tmp = 0; /* nothing routed to external APIC */
  351. else
  352. tmp = 0x1f; /* all known bits (4-0) routed to external APIC */
  353. printk(KERN_INFO "PCI: %sbling Via external APIC routing\n",
  354. tmp == 0 ? "Disa" : "Ena");
  355. /* Offset 0x58: External APIC IRQ output control */
  356. pci_write_config_byte (dev, 0x58, tmp);
  357. }
  358. DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C686, quirk_via_ioapic );
  359. /*
  360. * The AMD io apic can hang the box when an apic irq is masked.
  361. * We check all revs >= B0 (yet not in the pre production!) as the bug
  362. * is currently marked NoFix
  363. *
  364. * We have multiple reports of hangs with this chipset that went away with
  365. * noapic specified. For the moment we assume its the errata. We may be wrong
  366. * of course. However the advice is demonstrably good even if so..
  367. */
  368. static void __devinit quirk_amd_ioapic(struct pci_dev *dev)
  369. {
  370. u8 rev;
  371. pci_read_config_byte(dev, PCI_REVISION_ID, &rev);
  372. if (rev >= 0x02) {
  373. printk(KERN_WARNING "I/O APIC: AMD Errata #22 may be present. In the event of instability try\n");
  374. printk(KERN_WARNING " : booting with the \"noapic\" option.\n");
  375. }
  376. }
  377. DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_VIPER_7410, quirk_amd_ioapic );
  378. static void __init quirk_ioapic_rmw(struct pci_dev *dev)
  379. {
  380. if (dev->devfn == 0 && dev->bus->number == 0)
  381. sis_apic_bug = 1;
  382. }
  383. DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_SI, PCI_ANY_ID, quirk_ioapic_rmw );
  384. int pci_msi_quirk;
  385. #define AMD8131_revA0 0x01
  386. #define AMD8131_revB0 0x11
  387. #define AMD8131_MISC 0x40
  388. #define AMD8131_NIOAMODE_BIT 0
  389. static void __init quirk_amd_8131_ioapic(struct pci_dev *dev)
  390. {
  391. unsigned char revid, tmp;
  392. pci_msi_quirk = 1;
  393. printk(KERN_WARNING "PCI: MSI quirk detected. pci_msi_quirk set.\n");
  394. if (nr_ioapics == 0)
  395. return;
  396. pci_read_config_byte(dev, PCI_REVISION_ID, &revid);
  397. if (revid == AMD8131_revA0 || revid == AMD8131_revB0) {
  398. printk(KERN_INFO "Fixing up AMD8131 IOAPIC mode\n");
  399. pci_read_config_byte( dev, AMD8131_MISC, &tmp);
  400. tmp &= ~(1 << AMD8131_NIOAMODE_BIT);
  401. pci_write_config_byte( dev, AMD8131_MISC, tmp);
  402. }
  403. }
  404. DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_8131_APIC, quirk_amd_8131_ioapic );
  405. #endif /* CONFIG_X86_IO_APIC */
  406. /*
  407. * Via 686A/B: The PCI_INTERRUPT_LINE register for the on-chip
  408. * devices, USB0/1, AC97, MC97, and ACPI, has an unusual feature:
  409. * when written, it makes an internal connection to the PIC.
  410. * For these devices, this register is defined to be 4 bits wide.
  411. * Normally this is fine. However for IO-APIC motherboards, or
  412. * non-x86 architectures (yes Via exists on PPC among other places),
  413. * we must mask the PCI_INTERRUPT_LINE value versus 0xf to get
  414. * interrupts delivered properly.
  415. *
  416. * TODO: When we have device-specific interrupt routers,
  417. * quirk_via_irqpic will go away from quirks.
  418. */
  419. /*
  420. * FIXME: it is questionable that quirk_via_acpi
  421. * is needed. It shows up as an ISA bridge, and does not
  422. * support the PCI_INTERRUPT_LINE register at all. Therefore
  423. * it seems like setting the pci_dev's 'irq' to the
  424. * value of the ACPI SCI interrupt is only done for convenience.
  425. * -jgarzik
  426. */
  427. static void __devinit quirk_via_acpi(struct pci_dev *d)
  428. {
  429. /*
  430. * VIA ACPI device: SCI IRQ line in PCI config byte 0x42
  431. */
  432. u8 irq;
  433. pci_read_config_byte(d, 0x42, &irq);
  434. irq &= 0xf;
  435. if (irq && (irq != 2))
  436. d->irq = irq;
  437. }
  438. DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C586_3, quirk_via_acpi );
  439. DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C686_4, quirk_via_acpi );
  440. /*
  441. * PIIX3 USB: We have to disable USB interrupts that are
  442. * hardwired to PIRQD# and may be shared with an
  443. * external device.
  444. *
  445. * Legacy Support Register (LEGSUP):
  446. * bit13: USB PIRQ Enable (USBPIRQDEN),
  447. * bit4: Trap/SMI On IRQ Enable (USBSMIEN).
  448. *
  449. * We mask out all r/wc bits, too.
  450. */
  451. static void __devinit quirk_piix3_usb(struct pci_dev *dev)
  452. {
  453. u16 legsup;
  454. pci_read_config_word(dev, 0xc0, &legsup);
  455. legsup &= 0x50ef;
  456. pci_write_config_word(dev, 0xc0, legsup);
  457. }
  458. DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82371SB_2, quirk_piix3_usb );
  459. DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82371AB_2, quirk_piix3_usb );
  460. /*
  461. * VIA VT82C598 has its device ID settable and many BIOSes
  462. * set it to the ID of VT82C597 for backward compatibility.
  463. * We need to switch it off to be able to recognize the real
  464. * type of the chip.
  465. */
  466. static void __devinit quirk_vt82c598_id(struct pci_dev *dev)
  467. {
  468. pci_write_config_byte(dev, 0xfc, 0);
  469. pci_read_config_word(dev, PCI_DEVICE_ID, &dev->device);
  470. }
  471. DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C597_0, quirk_vt82c598_id );
  472. /*
  473. * CardBus controllers have a legacy base address that enables them
  474. * to respond as i82365 pcmcia controllers. We don't want them to
  475. * do this even if the Linux CardBus driver is not loaded, because
  476. * the Linux i82365 driver does not (and should not) handle CardBus.
  477. */
  478. static void __devinit quirk_cardbus_legacy(struct pci_dev *dev)
  479. {
  480. if ((PCI_CLASS_BRIDGE_CARDBUS << 8) ^ dev->class)
  481. return;
  482. pci_write_config_dword(dev, PCI_CB_LEGACY_MODE_BASE, 0);
  483. }
  484. DECLARE_PCI_FIXUP_FINAL(PCI_ANY_ID, PCI_ANY_ID, quirk_cardbus_legacy);
  485. /*
  486. * Following the PCI ordering rules is optional on the AMD762. I'm not
  487. * sure what the designers were smoking but let's not inhale...
  488. *
  489. * To be fair to AMD, it follows the spec by default, its BIOS people
  490. * who turn it off!
  491. */
  492. static void __devinit quirk_amd_ordering(struct pci_dev *dev)
  493. {
  494. u32 pcic;
  495. pci_read_config_dword(dev, 0x4C, &pcic);
  496. if ((pcic&6)!=6) {
  497. pcic |= 6;
  498. printk(KERN_WARNING "BIOS failed to enable PCI standards compliance, fixing this error.\n");
  499. pci_write_config_dword(dev, 0x4C, pcic);
  500. pci_read_config_dword(dev, 0x84, &pcic);
  501. pcic |= (1<<23); /* Required in this mode */
  502. pci_write_config_dword(dev, 0x84, pcic);
  503. }
  504. }
  505. DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_FE_GATE_700C, quirk_amd_ordering );
  506. /*
  507. * DreamWorks provided workaround for Dunord I-3000 problem
  508. *
  509. * This card decodes and responds to addresses not apparently
  510. * assigned to it. We force a larger allocation to ensure that
  511. * nothing gets put too close to it.
  512. */
  513. static void __devinit quirk_dunord ( struct pci_dev * dev )
  514. {
  515. struct resource *r = &dev->resource [1];
  516. r->start = 0;
  517. r->end = 0xffffff;
  518. }
  519. DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_DUNORD, PCI_DEVICE_ID_DUNORD_I3000, quirk_dunord );
  520. /*
  521. * i82380FB mobile docking controller: its PCI-to-PCI bridge
  522. * is subtractive decoding (transparent), and does indicate this
  523. * in the ProgIf. Unfortunately, the ProgIf value is wrong - 0x80
  524. * instead of 0x01.
  525. */
  526. static void __devinit quirk_transparent_bridge(struct pci_dev *dev)
  527. {
  528. dev->transparent = 1;
  529. }
  530. DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82380FB, quirk_transparent_bridge );
  531. DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_TOSHIBA, 0x605, quirk_transparent_bridge );
  532. /*
  533. * Common misconfiguration of the MediaGX/Geode PCI master that will
  534. * reduce PCI bandwidth from 70MB/s to 25MB/s. See the GXM/GXLV/GX1
  535. * datasheets found at http://www.national.com/ds/GX for info on what
  536. * these bits do. <christer@weinigel.se>
  537. */
  538. static void __init quirk_mediagx_master(struct pci_dev *dev)
  539. {
  540. u8 reg;
  541. pci_read_config_byte(dev, 0x41, &reg);
  542. if (reg & 2) {
  543. reg &= ~2;
  544. printk(KERN_INFO "PCI: Fixup for MediaGX/Geode Slave Disconnect Boundary (0x41=0x%02x)\n", reg);
  545. pci_write_config_byte(dev, 0x41, reg);
  546. }
  547. }
  548. DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_CYRIX, PCI_DEVICE_ID_CYRIX_PCI_MASTER, quirk_mediagx_master );
  549. /*
  550. * As per PCI spec, ignore base address registers 0-3 of the IDE controllers
  551. * running in Compatible mode (bits 0 and 2 in the ProgIf for primary and
  552. * secondary channels respectively). If the device reports Compatible mode
  553. * but does use BAR0-3 for address decoding, we assume that firmware has
  554. * programmed these BARs with standard values (0x1f0,0x3f4 and 0x170,0x374).
  555. * Exceptions (if they exist) must be handled in chip/architecture specific
  556. * fixups.
  557. *
  558. * Note: for non x86 people. You may need an arch specific quirk to handle
  559. * moving IDE devices to native mode as well. Some plug in card devices power
  560. * up in compatible mode and assume the BIOS will adjust them.
  561. *
  562. * Q: should we load the 0x1f0,0x3f4 into the registers or zap them as
  563. * we do now ? We don't want is pci_enable_device to come along
  564. * and assign new resources. Both approaches work for that.
  565. */
  566. static void __devinit quirk_ide_bases(struct pci_dev *dev)
  567. {
  568. struct resource *res;
  569. int first_bar = 2, last_bar = 0;
  570. if ((dev->class >> 8) != PCI_CLASS_STORAGE_IDE)
  571. return;
  572. res = &dev->resource[0];
  573. /* primary channel: ProgIf bit 0, BAR0, BAR1 */
  574. if (!(dev->class & 1) && (res[0].flags || res[1].flags)) {
  575. res[0].start = res[0].end = res[0].flags = 0;
  576. res[1].start = res[1].end = res[1].flags = 0;
  577. first_bar = 0;
  578. last_bar = 1;
  579. }
  580. /* secondary channel: ProgIf bit 2, BAR2, BAR3 */
  581. if (!(dev->class & 4) && (res[2].flags || res[3].flags)) {
  582. res[2].start = res[2].end = res[2].flags = 0;
  583. res[3].start = res[3].end = res[3].flags = 0;
  584. last_bar = 3;
  585. }
  586. if (!last_bar)
  587. return;
  588. printk(KERN_INFO "PCI: Ignoring BAR%d-%d of IDE controller %s\n",
  589. first_bar, last_bar, pci_name(dev));
  590. }
  591. DECLARE_PCI_FIXUP_HEADER(PCI_ANY_ID, PCI_ANY_ID, quirk_ide_bases);
  592. /*
  593. * Ensure C0 rev restreaming is off. This is normally done by
  594. * the BIOS but in the odd case it is not the results are corruption
  595. * hence the presence of a Linux check
  596. */
  597. static void __init quirk_disable_pxb(struct pci_dev *pdev)
  598. {
  599. u16 config;
  600. u8 rev;
  601. pci_read_config_byte(pdev, PCI_REVISION_ID, &rev);
  602. if (rev != 0x04) /* Only C0 requires this */
  603. return;
  604. pci_read_config_word(pdev, 0x40, &config);
  605. if (config & (1<<6)) {
  606. config &= ~(1<<6);
  607. pci_write_config_word(pdev, 0x40, config);
  608. printk(KERN_INFO "PCI: C0 revision 450NX. Disabling PCI restreaming.\n");
  609. }
  610. }
  611. DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82454NX, quirk_disable_pxb );
  612. /*
  613. * VIA northbridges care about PCI_INTERRUPT_LINE
  614. */
  615. int via_interrupt_line_quirk;
  616. static void __devinit quirk_via_bridge(struct pci_dev *pdev)
  617. {
  618. if(pdev->devfn == 0) {
  619. printk(KERN_INFO "PCI: Via IRQ fixup\n");
  620. via_interrupt_line_quirk = 1;
  621. }
  622. }
  623. DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_ANY_ID, quirk_via_bridge );
  624. /*
  625. * Serverworks CSB5 IDE does not fully support native mode
  626. */
  627. static void __devinit quirk_svwks_csb5ide(struct pci_dev *pdev)
  628. {
  629. u8 prog;
  630. pci_read_config_byte(pdev, PCI_CLASS_PROG, &prog);
  631. if (prog & 5) {
  632. prog &= ~5;
  633. pdev->class &= ~5;
  634. pci_write_config_byte(pdev, PCI_CLASS_PROG, prog);
  635. /* need to re-assign BARs for compat mode */
  636. quirk_ide_bases(pdev);
  637. }
  638. }
  639. DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_SERVERWORKS, PCI_DEVICE_ID_SERVERWORKS_CSB5IDE, quirk_svwks_csb5ide );
  640. /*
  641. * Intel 82801CAM ICH3-M datasheet says IDE modes must be the same
  642. */
  643. static void __init quirk_ide_samemode(struct pci_dev *pdev)
  644. {
  645. u8 prog;
  646. pci_read_config_byte(pdev, PCI_CLASS_PROG, &prog);
  647. if (((prog & 1) && !(prog & 4)) || ((prog & 4) && !(prog & 1))) {
  648. printk(KERN_INFO "PCI: IDE mode mismatch; forcing legacy mode\n");
  649. prog &= ~5;
  650. pdev->class &= ~5;
  651. pci_write_config_byte(pdev, PCI_CLASS_PROG, prog);
  652. /* need to re-assign BARs for compat mode */
  653. quirk_ide_bases(pdev);
  654. }
  655. }
  656. DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801CA_10, quirk_ide_samemode);
  657. /* This was originally an Alpha specific thing, but it really fits here.
  658. * The i82375 PCI/EISA bridge appears as non-classified. Fix that.
  659. */
  660. static void __init quirk_eisa_bridge(struct pci_dev *dev)
  661. {
  662. dev->class = PCI_CLASS_BRIDGE_EISA << 8;
  663. }
  664. DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82375, quirk_eisa_bridge );
  665. /*
  666. * On ASUS P4B boards, the SMBus PCI Device within the ICH2/4 southbridge
  667. * is not activated. The myth is that Asus said that they do not want the
  668. * users to be irritated by just another PCI Device in the Win98 device
  669. * manager. (see the file prog/hotplug/README.p4b in the lm_sensors
  670. * package 2.7.0 for details)
  671. *
  672. * The SMBus PCI Device can be activated by setting a bit in the ICH LPC
  673. * bridge. Unfortunately, this device has no subvendor/subdevice ID. So it
  674. * becomes necessary to do this tweak in two steps -- I've chosen the Host
  675. * bridge as trigger.
  676. */
  677. static int __initdata asus_hides_smbus = 0;
  678. static void __init asus_hides_smbus_hostbridge(struct pci_dev *dev)
  679. {
  680. if (unlikely(dev->subsystem_vendor == PCI_VENDOR_ID_ASUSTEK)) {
  681. if (dev->device == PCI_DEVICE_ID_INTEL_82845_HB)
  682. switch(dev->subsystem_device) {
  683. case 0x8070: /* P4B */
  684. case 0x8088: /* P4B533 */
  685. case 0x1626: /* L3C notebook */
  686. asus_hides_smbus = 1;
  687. }
  688. if (dev->device == PCI_DEVICE_ID_INTEL_82845G_HB)
  689. switch(dev->subsystem_device) {
  690. case 0x80b1: /* P4GE-V */
  691. case 0x80b2: /* P4PE */
  692. case 0x8093: /* P4B533-V */
  693. asus_hides_smbus = 1;
  694. }
  695. if (dev->device == PCI_DEVICE_ID_INTEL_82850_HB)
  696. switch(dev->subsystem_device) {
  697. case 0x8030: /* P4T533 */
  698. asus_hides_smbus = 1;
  699. }
  700. if (dev->device == PCI_DEVICE_ID_INTEL_7205_0)
  701. switch (dev->subsystem_device) {
  702. case 0x8070: /* P4G8X Deluxe */
  703. asus_hides_smbus = 1;
  704. }
  705. if (dev->device == PCI_DEVICE_ID_INTEL_82855GM_HB)
  706. switch (dev->subsystem_device) {
  707. case 0x1751: /* M2N notebook */
  708. case 0x1821: /* M5N notebook */
  709. asus_hides_smbus = 1;
  710. }
  711. if (dev->device == PCI_DEVICE_ID_INTEL_82855PM_HB)
  712. switch (dev->subsystem_device) {
  713. case 0x184b: /* W1N notebook */
  714. case 0x186a: /* M6Ne notebook */
  715. asus_hides_smbus = 1;
  716. }
  717. } else if (unlikely(dev->subsystem_vendor == PCI_VENDOR_ID_HP)) {
  718. if (dev->device == PCI_DEVICE_ID_INTEL_82855PM_HB)
  719. switch(dev->subsystem_device) {
  720. case 0x088C: /* HP Compaq nc8000 */
  721. case 0x0890: /* HP Compaq nc6000 */
  722. asus_hides_smbus = 1;
  723. }
  724. if (dev->device == PCI_DEVICE_ID_INTEL_82865_HB)
  725. switch (dev->subsystem_device) {
  726. case 0x12bc: /* HP D330L */
  727. asus_hides_smbus = 1;
  728. }
  729. } else if (unlikely(dev->subsystem_vendor == PCI_VENDOR_ID_TOSHIBA)) {
  730. if (dev->device == PCI_DEVICE_ID_INTEL_82855GM_HB)
  731. switch(dev->subsystem_device) {
  732. case 0x0001: /* Toshiba Satellite A40 */
  733. asus_hides_smbus = 1;
  734. }
  735. } else if (unlikely(dev->subsystem_vendor == PCI_VENDOR_ID_SAMSUNG)) {
  736. if (dev->device == PCI_DEVICE_ID_INTEL_82855PM_HB)
  737. switch(dev->subsystem_device) {
  738. case 0xC00C: /* Samsung P35 notebook */
  739. asus_hides_smbus = 1;
  740. }
  741. }
  742. }
  743. DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82845_HB, asus_hides_smbus_hostbridge );
  744. DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82845G_HB, asus_hides_smbus_hostbridge );
  745. DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82850_HB, asus_hides_smbus_hostbridge );
  746. DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82865_HB, asus_hides_smbus_hostbridge );
  747. DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_7205_0, asus_hides_smbus_hostbridge );
  748. DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82855PM_HB, asus_hides_smbus_hostbridge );
  749. DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82855GM_HB, asus_hides_smbus_hostbridge );
  750. static void __init asus_hides_smbus_lpc(struct pci_dev *dev)
  751. {
  752. u16 val;
  753. if (likely(!asus_hides_smbus))
  754. return;
  755. pci_read_config_word(dev, 0xF2, &val);
  756. if (val & 0x8) {
  757. pci_write_config_word(dev, 0xF2, val & (~0x8));
  758. pci_read_config_word(dev, 0xF2, &val);
  759. if (val & 0x8)
  760. printk(KERN_INFO "PCI: i801 SMBus device continues to play 'hide and seek'! 0x%x\n", val);
  761. else
  762. printk(KERN_INFO "PCI: Enabled i801 SMBus device\n");
  763. }
  764. }
  765. DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801DB_0, asus_hides_smbus_lpc );
  766. DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801BA_0, asus_hides_smbus_lpc );
  767. DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801CA_12, asus_hides_smbus_lpc );
  768. DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801DB_12, asus_hides_smbus_lpc );
  769. DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801EB_0, asus_hides_smbus_lpc );
  770. /*
  771. * SiS 96x south bridge: BIOS typically hides SMBus device...
  772. */
  773. static void __init quirk_sis_96x_smbus(struct pci_dev *dev)
  774. {
  775. u8 val = 0;
  776. printk(KERN_INFO "Enabling SiS 96x SMBus.\n");
  777. pci_read_config_byte(dev, 0x77, &val);
  778. pci_write_config_byte(dev, 0x77, val & ~0x10);
  779. pci_read_config_byte(dev, 0x77, &val);
  780. }
  781. #define UHCI_USBLEGSUP 0xc0 /* legacy support */
  782. #define UHCI_USBCMD 0 /* command register */
  783. #define UHCI_USBSTS 2 /* status register */
  784. #define UHCI_USBINTR 4 /* interrupt register */
  785. #define UHCI_USBLEGSUP_DEFAULT 0x2000 /* only PIRQ enable set */
  786. #define UHCI_USBCMD_RUN (1 << 0) /* RUN/STOP bit */
  787. #define UHCI_USBCMD_GRESET (1 << 2) /* Global reset */
  788. #define UHCI_USBCMD_CONFIGURE (1 << 6) /* config semaphore */
  789. #define UHCI_USBSTS_HALTED (1 << 5) /* HCHalted bit */
  790. #define OHCI_CONTROL 0x04
  791. #define OHCI_CMDSTATUS 0x08
  792. #define OHCI_INTRSTATUS 0x0c
  793. #define OHCI_INTRENABLE 0x10
  794. #define OHCI_INTRDISABLE 0x14
  795. #define OHCI_OCR (1 << 3) /* ownership change request */
  796. #define OHCI_CTRL_IR (1 << 8) /* interrupt routing */
  797. #define OHCI_INTR_OC (1 << 30) /* ownership change */
  798. #define EHCI_HCC_PARAMS 0x08 /* extended capabilities */
  799. #define EHCI_USBCMD 0 /* command register */
  800. #define EHCI_USBCMD_RUN (1 << 0) /* RUN/STOP bit */
  801. #define EHCI_USBSTS 4 /* status register */
  802. #define EHCI_USBSTS_HALTED (1 << 12) /* HCHalted bit */
  803. #define EHCI_USBINTR 8 /* interrupt register */
  804. #define EHCI_USBLEGSUP 0 /* legacy support register */
  805. #define EHCI_USBLEGSUP_BIOS (1 << 16) /* BIOS semaphore */
  806. #define EHCI_USBLEGSUP_OS (1 << 24) /* OS semaphore */
  807. #define EHCI_USBLEGCTLSTS 4 /* legacy control/status */
  808. #define EHCI_USBLEGCTLSTS_SOOE (1 << 13) /* SMI on ownership change */
  809. int usb_early_handoff __devinitdata = 0;
  810. static int __init usb_handoff_early(char *str)
  811. {
  812. usb_early_handoff = 1;
  813. return 0;
  814. }
  815. __setup("usb-handoff", usb_handoff_early);
  816. static void __devinit quirk_usb_handoff_uhci(struct pci_dev *pdev)
  817. {
  818. unsigned long base = 0;
  819. int wait_time, delta;
  820. u16 val, sts;
  821. int i;
  822. for (i = 0; i < PCI_ROM_RESOURCE; i++)
  823. if ((pci_resource_flags(pdev, i) & IORESOURCE_IO)) {
  824. base = pci_resource_start(pdev, i);
  825. break;
  826. }
  827. if (!base)
  828. return;
  829. /*
  830. * stop controller
  831. */
  832. sts = inw(base + UHCI_USBSTS);
  833. val = inw(base + UHCI_USBCMD);
  834. val &= ~(u16)(UHCI_USBCMD_RUN | UHCI_USBCMD_CONFIGURE);
  835. outw(val, base + UHCI_USBCMD);
  836. /*
  837. * wait while it stops if it was running
  838. */
  839. if ((sts & UHCI_USBSTS_HALTED) == 0)
  840. {
  841. wait_time = 1000;
  842. delta = 100;
  843. do {
  844. outw(0x1f, base + UHCI_USBSTS);
  845. udelay(delta);
  846. wait_time -= delta;
  847. val = inw(base + UHCI_USBSTS);
  848. if (val & UHCI_USBSTS_HALTED)
  849. break;
  850. } while (wait_time > 0);
  851. }
  852. /*
  853. * disable interrupts & legacy support
  854. */
  855. outw(0, base + UHCI_USBINTR);
  856. outw(0x1f, base + UHCI_USBSTS);
  857. pci_read_config_word(pdev, UHCI_USBLEGSUP, &val);
  858. if (val & 0xbf)
  859. pci_write_config_word(pdev, UHCI_USBLEGSUP, UHCI_USBLEGSUP_DEFAULT);
  860. }
  861. static void __devinit quirk_usb_handoff_ohci(struct pci_dev *pdev)
  862. {
  863. void __iomem *base;
  864. int wait_time;
  865. base = ioremap_nocache(pci_resource_start(pdev, 0),
  866. pci_resource_len(pdev, 0));
  867. if (base == NULL) return;
  868. if (readl(base + OHCI_CONTROL) & OHCI_CTRL_IR) {
  869. wait_time = 500; /* 0.5 seconds */
  870. writel(OHCI_INTR_OC, base + OHCI_INTRENABLE);
  871. writel(OHCI_OCR, base + OHCI_CMDSTATUS);
  872. while (wait_time > 0 &&
  873. readl(base + OHCI_CONTROL) & OHCI_CTRL_IR) {
  874. wait_time -= 10;
  875. msleep(10);
  876. }
  877. }
  878. /*
  879. * disable interrupts
  880. */
  881. writel(~(u32)0, base + OHCI_INTRDISABLE);
  882. writel(~(u32)0, base + OHCI_INTRSTATUS);
  883. iounmap(base);
  884. }
  885. static void __devinit quirk_usb_disable_ehci(struct pci_dev *pdev)
  886. {
  887. int wait_time, delta;
  888. void __iomem *base, *op_reg_base;
  889. u32 hcc_params, val, temp;
  890. u8 cap_length;
  891. base = ioremap_nocache(pci_resource_start(pdev, 0),
  892. pci_resource_len(pdev, 0));
  893. if (base == NULL) return;
  894. cap_length = readb(base);
  895. op_reg_base = base + cap_length;
  896. hcc_params = readl(base + EHCI_HCC_PARAMS);
  897. hcc_params = (hcc_params >> 8) & 0xff;
  898. if (hcc_params) {
  899. pci_read_config_dword(pdev,
  900. hcc_params + EHCI_USBLEGSUP,
  901. &val);
  902. if (((val & 0xff) == 1) && (val & EHCI_USBLEGSUP_BIOS)) {
  903. /*
  904. * Ok, BIOS is in smm mode, try to hand off...
  905. */
  906. pci_read_config_dword(pdev,
  907. hcc_params + EHCI_USBLEGCTLSTS,
  908. &temp);
  909. pci_write_config_dword(pdev,
  910. hcc_params + EHCI_USBLEGCTLSTS,
  911. temp | EHCI_USBLEGCTLSTS_SOOE);
  912. val |= EHCI_USBLEGSUP_OS;
  913. pci_write_config_dword(pdev,
  914. hcc_params + EHCI_USBLEGSUP,
  915. val);
  916. wait_time = 500;
  917. do {
  918. msleep(10);
  919. wait_time -= 10;
  920. pci_read_config_dword(pdev,
  921. hcc_params + EHCI_USBLEGSUP,
  922. &val);
  923. } while (wait_time && (val & EHCI_USBLEGSUP_BIOS));
  924. if (!wait_time) {
  925. /*
  926. * well, possibly buggy BIOS...
  927. */
  928. printk(KERN_WARNING "EHCI early BIOS handoff "
  929. "failed (BIOS bug ?)\n");
  930. pci_write_config_dword(pdev,
  931. hcc_params + EHCI_USBLEGSUP,
  932. EHCI_USBLEGSUP_OS);
  933. pci_write_config_dword(pdev,
  934. hcc_params + EHCI_USBLEGCTLSTS,
  935. 0);
  936. }
  937. }
  938. }
  939. /*
  940. * halt EHCI & disable its interrupts in any case
  941. */
  942. val = readl(op_reg_base + EHCI_USBSTS);
  943. if ((val & EHCI_USBSTS_HALTED) == 0) {
  944. val = readl(op_reg_base + EHCI_USBCMD);
  945. val &= ~EHCI_USBCMD_RUN;
  946. writel(val, op_reg_base + EHCI_USBCMD);
  947. wait_time = 2000;
  948. delta = 100;
  949. do {
  950. writel(0x3f, op_reg_base + EHCI_USBSTS);
  951. udelay(delta);
  952. wait_time -= delta;
  953. val = readl(op_reg_base + EHCI_USBSTS);
  954. if ((val == ~(u32)0) || (val & EHCI_USBSTS_HALTED)) {
  955. break;
  956. }
  957. } while (wait_time > 0);
  958. }
  959. writel(0, op_reg_base + EHCI_USBINTR);
  960. writel(0x3f, op_reg_base + EHCI_USBSTS);
  961. iounmap(base);
  962. return;
  963. }
  964. static void __devinit quirk_usb_early_handoff(struct pci_dev *pdev)
  965. {
  966. if (!usb_early_handoff)
  967. return;
  968. if (pdev->class == ((PCI_CLASS_SERIAL_USB << 8) | 0x00)) { /* UHCI */
  969. quirk_usb_handoff_uhci(pdev);
  970. } else if (pdev->class == ((PCI_CLASS_SERIAL_USB << 8) | 0x10)) { /* OHCI */
  971. quirk_usb_handoff_ohci(pdev);
  972. } else if (pdev->class == ((PCI_CLASS_SERIAL_USB << 8) | 0x20)) { /* EHCI */
  973. quirk_usb_disable_ehci(pdev);
  974. }
  975. return;
  976. }
  977. DECLARE_PCI_FIXUP_HEADER(PCI_ANY_ID, PCI_ANY_ID, quirk_usb_early_handoff);
  978. /*
  979. * ... This is further complicated by the fact that some SiS96x south
  980. * bridges pretend to be 85C503/5513 instead. In that case see if we
  981. * spotted a compatible north bridge to make sure.
  982. * (pci_find_device doesn't work yet)
  983. *
  984. * We can also enable the sis96x bit in the discovery register..
  985. */
  986. static int __devinitdata sis_96x_compatible = 0;
  987. #define SIS_DETECT_REGISTER 0x40
  988. static void __init quirk_sis_503(struct pci_dev *dev)
  989. {
  990. u8 reg;
  991. u16 devid;
  992. pci_read_config_byte(dev, SIS_DETECT_REGISTER, &reg);
  993. pci_write_config_byte(dev, SIS_DETECT_REGISTER, reg | (1 << 6));
  994. pci_read_config_word(dev, PCI_DEVICE_ID, &devid);
  995. if (((devid & 0xfff0) != 0x0960) && (devid != 0x0018)) {
  996. pci_write_config_byte(dev, SIS_DETECT_REGISTER, reg);
  997. return;
  998. }
  999. /* Make people aware that we changed the config.. */
  1000. printk(KERN_WARNING "Uncovering SIS%x that hid as a SIS503 (compatible=%d)\n", devid, sis_96x_compatible);
  1001. /*
  1002. * Ok, it now shows up as a 96x.. The 96x quirks are after
  1003. * the 503 quirk in the quirk table, so they'll automatically
  1004. * run and enable things like the SMBus device
  1005. */
  1006. dev->device = devid;
  1007. }
  1008. static void __init quirk_sis_96x_compatible(struct pci_dev *dev)
  1009. {
  1010. sis_96x_compatible = 1;
  1011. }
  1012. DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_645, quirk_sis_96x_compatible );
  1013. DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_646, quirk_sis_96x_compatible );
  1014. DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_648, quirk_sis_96x_compatible );
  1015. DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_650, quirk_sis_96x_compatible );
  1016. DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_651, quirk_sis_96x_compatible );
  1017. DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_735, quirk_sis_96x_compatible );
  1018. DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_503, quirk_sis_503 );
  1019. DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_961, quirk_sis_96x_smbus );
  1020. DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_962, quirk_sis_96x_smbus );
  1021. DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_963, quirk_sis_96x_smbus );
  1022. DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_LPC, quirk_sis_96x_smbus );
  1023. #ifdef CONFIG_X86_IO_APIC
  1024. static void __init quirk_alder_ioapic(struct pci_dev *pdev)
  1025. {
  1026. int i;
  1027. if ((pdev->class >> 8) != 0xff00)
  1028. return;
  1029. /* the first BAR is the location of the IO APIC...we must
  1030. * not touch this (and it's already covered by the fixmap), so
  1031. * forcibly insert it into the resource tree */
  1032. if (pci_resource_start(pdev, 0) && pci_resource_len(pdev, 0))
  1033. insert_resource(&iomem_resource, &pdev->resource[0]);
  1034. /* The next five BARs all seem to be rubbish, so just clean
  1035. * them out */
  1036. for (i=1; i < 6; i++) {
  1037. memset(&pdev->resource[i], 0, sizeof(pdev->resource[i]));
  1038. }
  1039. }
  1040. DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_EESSC, quirk_alder_ioapic );
  1041. #endif
  1042. #ifdef CONFIG_SCSI_SATA
  1043. static void __devinit quirk_intel_ide_combined(struct pci_dev *pdev)
  1044. {
  1045. u8 prog, comb, tmp;
  1046. int ich = 0;
  1047. /*
  1048. * Narrow down to Intel SATA PCI devices.
  1049. */
  1050. switch (pdev->device) {
  1051. /* PCI ids taken from drivers/scsi/ata_piix.c */
  1052. case 0x24d1:
  1053. case 0x24df:
  1054. case 0x25a3:
  1055. case 0x25b0:
  1056. ich = 5;
  1057. break;
  1058. case 0x2651:
  1059. case 0x2652:
  1060. case 0x2653:
  1061. case 0x2680: /* ESB2 */
  1062. ich = 6;
  1063. break;
  1064. case 0x27c0:
  1065. case 0x27c4:
  1066. ich = 7;
  1067. break;
  1068. default:
  1069. /* we do not handle this PCI device */
  1070. return;
  1071. }
  1072. /*
  1073. * Read combined mode register.
  1074. */
  1075. pci_read_config_byte(pdev, 0x90, &tmp); /* combined mode reg */
  1076. if (ich == 5) {
  1077. tmp &= 0x6; /* interesting bits 2:1, PATA primary/secondary */
  1078. if (tmp == 0x4) /* bits 10x */
  1079. comb = (1 << 0); /* SATA port 0, PATA port 1 */
  1080. else if (tmp == 0x6) /* bits 11x */
  1081. comb = (1 << 2); /* PATA port 0, SATA port 1 */
  1082. else
  1083. return; /* not in combined mode */
  1084. } else {
  1085. WARN_ON((ich != 6) && (ich != 7));
  1086. tmp &= 0x3; /* interesting bits 1:0 */
  1087. if (tmp & (1 << 0))
  1088. comb = (1 << 2); /* PATA port 0, SATA port 1 */
  1089. else if (tmp & (1 << 1))
  1090. comb = (1 << 0); /* SATA port 0, PATA port 1 */
  1091. else
  1092. return; /* not in combined mode */
  1093. }
  1094. /*
  1095. * Read programming interface register.
  1096. * (Tells us if it's legacy or native mode)
  1097. */
  1098. pci_read_config_byte(pdev, PCI_CLASS_PROG, &prog);
  1099. /* if SATA port is in native mode, we're ok. */
  1100. if (prog & comb)
  1101. return;
  1102. /* SATA port is in legacy mode. Reserve port so that
  1103. * IDE driver does not attempt to use it. If request_region
  1104. * fails, it will be obvious at boot time, so we don't bother
  1105. * checking return values.
  1106. */
  1107. if (comb == (1 << 0))
  1108. request_region(0x1f0, 8, "libata"); /* port 0 */
  1109. else
  1110. request_region(0x170, 8, "libata"); /* port 1 */
  1111. }
  1112. DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_ANY_ID, quirk_intel_ide_combined );
  1113. #endif /* CONFIG_SCSI_SATA */
  1114. int pcie_mch_quirk;
  1115. static void __devinit quirk_pcie_mch(struct pci_dev *pdev)
  1116. {
  1117. pcie_mch_quirk = 1;
  1118. }
  1119. DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_E7520_MCH, quirk_pcie_mch );
  1120. DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_E7320_MCH, quirk_pcie_mch );
  1121. DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_E7525_MCH, quirk_pcie_mch );
  1122. static void __devinit quirk_netmos(struct pci_dev *dev)
  1123. {
  1124. unsigned int num_parallel = (dev->subsystem_device & 0xf0) >> 4;
  1125. unsigned int num_serial = dev->subsystem_device & 0xf;
  1126. /*
  1127. * These Netmos parts are multiport serial devices with optional
  1128. * parallel ports. Even when parallel ports are present, they
  1129. * are identified as class SERIAL, which means the serial driver
  1130. * will claim them. To prevent this, mark them as class OTHER.
  1131. * These combo devices should be claimed by parport_serial.
  1132. *
  1133. * The subdevice ID is of the form 0x00PS, where <P> is the number
  1134. * of parallel ports and <S> is the number of serial ports.
  1135. */
  1136. switch (dev->device) {
  1137. case PCI_DEVICE_ID_NETMOS_9735:
  1138. case PCI_DEVICE_ID_NETMOS_9745:
  1139. case PCI_DEVICE_ID_NETMOS_9835:
  1140. case PCI_DEVICE_ID_NETMOS_9845:
  1141. case PCI_DEVICE_ID_NETMOS_9855:
  1142. if ((dev->class >> 8) == PCI_CLASS_COMMUNICATION_SERIAL &&
  1143. num_parallel) {
  1144. printk(KERN_INFO "PCI: Netmos %04x (%u parallel, "
  1145. "%u serial); changing class SERIAL to OTHER "
  1146. "(use parport_serial)\n",
  1147. dev->device, num_parallel, num_serial);
  1148. dev->class = (PCI_CLASS_COMMUNICATION_OTHER << 8) |
  1149. (dev->class & 0xff);
  1150. }
  1151. }
  1152. }
  1153. DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_NETMOS, PCI_ANY_ID, quirk_netmos);
  1154. static void pci_do_fixups(struct pci_dev *dev, struct pci_fixup *f, struct pci_fixup *end)
  1155. {
  1156. while (f < end) {
  1157. if ((f->vendor == dev->vendor || f->vendor == (u16) PCI_ANY_ID) &&
  1158. (f->device == dev->device || f->device == (u16) PCI_ANY_ID)) {
  1159. pr_debug("PCI: Calling quirk %p for %s\n", f->hook, pci_name(dev));
  1160. f->hook(dev);
  1161. }
  1162. f++;
  1163. }
  1164. }
  1165. extern struct pci_fixup __start_pci_fixups_early[];
  1166. extern struct pci_fixup __end_pci_fixups_early[];
  1167. extern struct pci_fixup __start_pci_fixups_header[];
  1168. extern struct pci_fixup __end_pci_fixups_header[];
  1169. extern struct pci_fixup __start_pci_fixups_final[];
  1170. extern struct pci_fixup __end_pci_fixups_final[];
  1171. extern struct pci_fixup __start_pci_fixups_enable[];
  1172. extern struct pci_fixup __end_pci_fixups_enable[];
  1173. void pci_fixup_device(enum pci_fixup_pass pass, struct pci_dev *dev)
  1174. {
  1175. struct pci_fixup *start, *end;
  1176. switch(pass) {
  1177. case pci_fixup_early:
  1178. start = __start_pci_fixups_early;
  1179. end = __end_pci_fixups_early;
  1180. break;
  1181. case pci_fixup_header:
  1182. start = __start_pci_fixups_header;
  1183. end = __end_pci_fixups_header;
  1184. break;
  1185. case pci_fixup_final:
  1186. start = __start_pci_fixups_final;
  1187. end = __end_pci_fixups_final;
  1188. break;
  1189. case pci_fixup_enable:
  1190. start = __start_pci_fixups_enable;
  1191. end = __end_pci_fixups_enable;
  1192. break;
  1193. default:
  1194. /* stupid compiler warning, you would think with an enum... */
  1195. return;
  1196. }
  1197. pci_do_fixups(dev, start, end);
  1198. }
  1199. EXPORT_SYMBOL(pcie_mch_quirk);
  1200. #ifdef CONFIG_HOTPLUG
  1201. EXPORT_SYMBOL(pci_fixup_device);
  1202. #endif