devices.c 23 KB

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  1. /*
  2. * linux/arch/arm/mach-omap2/devices.c
  3. *
  4. * OMAP2 platform device setup/initialization
  5. *
  6. * This program is free software; you can redistribute it and/or modify
  7. * it under the terms of the GNU General Public License as published by
  8. * the Free Software Foundation; either version 2 of the License, or
  9. * (at your option) any later version.
  10. */
  11. #include <linux/module.h>
  12. #include <linux/kernel.h>
  13. #include <linux/init.h>
  14. #include <linux/platform_device.h>
  15. #include <linux/io.h>
  16. #include <linux/clk.h>
  17. #include <linux/err.h>
  18. #include <mach/hardware.h>
  19. #include <mach/irqs.h>
  20. #include <asm/mach-types.h>
  21. #include <asm/mach/map.h>
  22. #include <asm/pmu.h>
  23. #include <plat/control.h>
  24. #include <plat/tc.h>
  25. #include <plat/board.h>
  26. #include <mach/gpio.h>
  27. #include <plat/mmc.h>
  28. #include <plat/dma.h>
  29. #include <plat/omap_hwmod.h>
  30. #include <plat/omap_device.h>
  31. #include "mux.h"
  32. #if defined(CONFIG_VIDEO_OMAP2) || defined(CONFIG_VIDEO_OMAP2_MODULE)
  33. static struct resource cam_resources[] = {
  34. {
  35. .start = OMAP24XX_CAMERA_BASE,
  36. .end = OMAP24XX_CAMERA_BASE + 0xfff,
  37. .flags = IORESOURCE_MEM,
  38. },
  39. {
  40. .start = INT_24XX_CAM_IRQ,
  41. .flags = IORESOURCE_IRQ,
  42. }
  43. };
  44. static struct platform_device omap_cam_device = {
  45. .name = "omap24xxcam",
  46. .id = -1,
  47. .num_resources = ARRAY_SIZE(cam_resources),
  48. .resource = cam_resources,
  49. };
  50. static inline void omap_init_camera(void)
  51. {
  52. platform_device_register(&omap_cam_device);
  53. }
  54. #elif defined(CONFIG_VIDEO_OMAP3) || defined(CONFIG_VIDEO_OMAP3_MODULE)
  55. static struct resource omap3isp_resources[] = {
  56. {
  57. .start = OMAP3430_ISP_BASE,
  58. .end = OMAP3430_ISP_END,
  59. .flags = IORESOURCE_MEM,
  60. },
  61. {
  62. .start = OMAP3430_ISP_CBUFF_BASE,
  63. .end = OMAP3430_ISP_CBUFF_END,
  64. .flags = IORESOURCE_MEM,
  65. },
  66. {
  67. .start = OMAP3430_ISP_CCP2_BASE,
  68. .end = OMAP3430_ISP_CCP2_END,
  69. .flags = IORESOURCE_MEM,
  70. },
  71. {
  72. .start = OMAP3430_ISP_CCDC_BASE,
  73. .end = OMAP3430_ISP_CCDC_END,
  74. .flags = IORESOURCE_MEM,
  75. },
  76. {
  77. .start = OMAP3430_ISP_HIST_BASE,
  78. .end = OMAP3430_ISP_HIST_END,
  79. .flags = IORESOURCE_MEM,
  80. },
  81. {
  82. .start = OMAP3430_ISP_H3A_BASE,
  83. .end = OMAP3430_ISP_H3A_END,
  84. .flags = IORESOURCE_MEM,
  85. },
  86. {
  87. .start = OMAP3430_ISP_PREV_BASE,
  88. .end = OMAP3430_ISP_PREV_END,
  89. .flags = IORESOURCE_MEM,
  90. },
  91. {
  92. .start = OMAP3430_ISP_RESZ_BASE,
  93. .end = OMAP3430_ISP_RESZ_END,
  94. .flags = IORESOURCE_MEM,
  95. },
  96. {
  97. .start = OMAP3430_ISP_SBL_BASE,
  98. .end = OMAP3430_ISP_SBL_END,
  99. .flags = IORESOURCE_MEM,
  100. },
  101. {
  102. .start = OMAP3430_ISP_CSI2A_BASE,
  103. .end = OMAP3430_ISP_CSI2A_END,
  104. .flags = IORESOURCE_MEM,
  105. },
  106. {
  107. .start = OMAP3430_ISP_CSI2PHY_BASE,
  108. .end = OMAP3430_ISP_CSI2PHY_END,
  109. .flags = IORESOURCE_MEM,
  110. },
  111. {
  112. .start = INT_34XX_CAM_IRQ,
  113. .flags = IORESOURCE_IRQ,
  114. }
  115. };
  116. static struct platform_device omap3isp_device = {
  117. .name = "omap3isp",
  118. .id = -1,
  119. .num_resources = ARRAY_SIZE(omap3isp_resources),
  120. .resource = omap3isp_resources,
  121. };
  122. static inline void omap_init_camera(void)
  123. {
  124. platform_device_register(&omap3isp_device);
  125. }
  126. #else
  127. static inline void omap_init_camera(void)
  128. {
  129. }
  130. #endif
  131. #if defined(CONFIG_OMAP_MBOX_FWK) || defined(CONFIG_OMAP_MBOX_FWK_MODULE)
  132. #define MBOX_REG_SIZE 0x120
  133. #ifdef CONFIG_ARCH_OMAP2
  134. static struct resource omap2_mbox_resources[] = {
  135. {
  136. .start = OMAP24XX_MAILBOX_BASE,
  137. .end = OMAP24XX_MAILBOX_BASE + MBOX_REG_SIZE - 1,
  138. .flags = IORESOURCE_MEM,
  139. },
  140. {
  141. .start = INT_24XX_MAIL_U0_MPU,
  142. .flags = IORESOURCE_IRQ,
  143. .name = "dsp",
  144. },
  145. {
  146. .start = INT_24XX_MAIL_U3_MPU,
  147. .flags = IORESOURCE_IRQ,
  148. .name = "iva",
  149. },
  150. };
  151. static int omap2_mbox_resources_sz = ARRAY_SIZE(omap2_mbox_resources);
  152. #else
  153. #define omap2_mbox_resources NULL
  154. #define omap2_mbox_resources_sz 0
  155. #endif
  156. #ifdef CONFIG_ARCH_OMAP3
  157. static struct resource omap3_mbox_resources[] = {
  158. {
  159. .start = OMAP34XX_MAILBOX_BASE,
  160. .end = OMAP34XX_MAILBOX_BASE + MBOX_REG_SIZE - 1,
  161. .flags = IORESOURCE_MEM,
  162. },
  163. {
  164. .start = INT_24XX_MAIL_U0_MPU,
  165. .flags = IORESOURCE_IRQ,
  166. .name = "dsp",
  167. },
  168. };
  169. static int omap3_mbox_resources_sz = ARRAY_SIZE(omap3_mbox_resources);
  170. #else
  171. #define omap3_mbox_resources NULL
  172. #define omap3_mbox_resources_sz 0
  173. #endif
  174. #ifdef CONFIG_ARCH_OMAP4
  175. #define OMAP4_MBOX_REG_SIZE 0x130
  176. static struct resource omap4_mbox_resources[] = {
  177. {
  178. .start = OMAP44XX_MAILBOX_BASE,
  179. .end = OMAP44XX_MAILBOX_BASE +
  180. OMAP4_MBOX_REG_SIZE - 1,
  181. .flags = IORESOURCE_MEM,
  182. },
  183. {
  184. .start = OMAP44XX_IRQ_MAIL_U0,
  185. .flags = IORESOURCE_IRQ,
  186. .name = "mbox",
  187. },
  188. };
  189. static int omap4_mbox_resources_sz = ARRAY_SIZE(omap4_mbox_resources);
  190. #else
  191. #define omap4_mbox_resources NULL
  192. #define omap4_mbox_resources_sz 0
  193. #endif
  194. static struct platform_device mbox_device = {
  195. .name = "omap-mailbox",
  196. .id = -1,
  197. };
  198. static inline void omap_init_mbox(void)
  199. {
  200. if (cpu_is_omap24xx()) {
  201. mbox_device.resource = omap2_mbox_resources;
  202. mbox_device.num_resources = omap2_mbox_resources_sz;
  203. } else if (cpu_is_omap34xx()) {
  204. mbox_device.resource = omap3_mbox_resources;
  205. mbox_device.num_resources = omap3_mbox_resources_sz;
  206. } else if (cpu_is_omap44xx()) {
  207. mbox_device.resource = omap4_mbox_resources;
  208. mbox_device.num_resources = omap4_mbox_resources_sz;
  209. } else {
  210. pr_err("%s: platform not supported\n", __func__);
  211. return;
  212. }
  213. platform_device_register(&mbox_device);
  214. }
  215. #else
  216. static inline void omap_init_mbox(void) { }
  217. #endif /* CONFIG_OMAP_MBOX_FWK */
  218. static inline void omap_init_sti(void) {}
  219. #if defined(CONFIG_SPI_OMAP24XX) || defined(CONFIG_SPI_OMAP24XX_MODULE)
  220. #include <plat/mcspi.h>
  221. #define OMAP2_MCSPI1_BASE 0x48098000
  222. #define OMAP2_MCSPI2_BASE 0x4809a000
  223. #define OMAP2_MCSPI3_BASE 0x480b8000
  224. #define OMAP2_MCSPI4_BASE 0x480ba000
  225. #define OMAP4_MCSPI1_BASE 0x48098100
  226. #define OMAP4_MCSPI2_BASE 0x4809a100
  227. #define OMAP4_MCSPI3_BASE 0x480b8100
  228. #define OMAP4_MCSPI4_BASE 0x480ba100
  229. static struct omap2_mcspi_platform_config omap2_mcspi1_config = {
  230. .num_cs = 4,
  231. };
  232. static struct resource omap2_mcspi1_resources[] = {
  233. {
  234. .start = OMAP2_MCSPI1_BASE,
  235. .end = OMAP2_MCSPI1_BASE + 0xff,
  236. .flags = IORESOURCE_MEM,
  237. },
  238. };
  239. static struct platform_device omap2_mcspi1 = {
  240. .name = "omap2_mcspi",
  241. .id = 1,
  242. .num_resources = ARRAY_SIZE(omap2_mcspi1_resources),
  243. .resource = omap2_mcspi1_resources,
  244. .dev = {
  245. .platform_data = &omap2_mcspi1_config,
  246. },
  247. };
  248. static struct omap2_mcspi_platform_config omap2_mcspi2_config = {
  249. .num_cs = 2,
  250. };
  251. static struct resource omap2_mcspi2_resources[] = {
  252. {
  253. .start = OMAP2_MCSPI2_BASE,
  254. .end = OMAP2_MCSPI2_BASE + 0xff,
  255. .flags = IORESOURCE_MEM,
  256. },
  257. };
  258. static struct platform_device omap2_mcspi2 = {
  259. .name = "omap2_mcspi",
  260. .id = 2,
  261. .num_resources = ARRAY_SIZE(omap2_mcspi2_resources),
  262. .resource = omap2_mcspi2_resources,
  263. .dev = {
  264. .platform_data = &omap2_mcspi2_config,
  265. },
  266. };
  267. #if defined(CONFIG_ARCH_OMAP2430) || defined(CONFIG_ARCH_OMAP3) || \
  268. defined(CONFIG_ARCH_OMAP4)
  269. static struct omap2_mcspi_platform_config omap2_mcspi3_config = {
  270. .num_cs = 2,
  271. };
  272. static struct resource omap2_mcspi3_resources[] = {
  273. {
  274. .start = OMAP2_MCSPI3_BASE,
  275. .end = OMAP2_MCSPI3_BASE + 0xff,
  276. .flags = IORESOURCE_MEM,
  277. },
  278. };
  279. static struct platform_device omap2_mcspi3 = {
  280. .name = "omap2_mcspi",
  281. .id = 3,
  282. .num_resources = ARRAY_SIZE(omap2_mcspi3_resources),
  283. .resource = omap2_mcspi3_resources,
  284. .dev = {
  285. .platform_data = &omap2_mcspi3_config,
  286. },
  287. };
  288. #endif
  289. #if defined(CONFIG_ARCH_OMAP3) || defined(CONFIG_ARCH_OMAP4)
  290. static struct omap2_mcspi_platform_config omap2_mcspi4_config = {
  291. .num_cs = 1,
  292. };
  293. static struct resource omap2_mcspi4_resources[] = {
  294. {
  295. .start = OMAP2_MCSPI4_BASE,
  296. .end = OMAP2_MCSPI4_BASE + 0xff,
  297. .flags = IORESOURCE_MEM,
  298. },
  299. };
  300. static struct platform_device omap2_mcspi4 = {
  301. .name = "omap2_mcspi",
  302. .id = 4,
  303. .num_resources = ARRAY_SIZE(omap2_mcspi4_resources),
  304. .resource = omap2_mcspi4_resources,
  305. .dev = {
  306. .platform_data = &omap2_mcspi4_config,
  307. },
  308. };
  309. #endif
  310. #ifdef CONFIG_ARCH_OMAP4
  311. static inline void omap4_mcspi_fixup(void)
  312. {
  313. omap2_mcspi1_resources[0].start = OMAP4_MCSPI1_BASE;
  314. omap2_mcspi1_resources[0].end = OMAP4_MCSPI1_BASE + 0xff;
  315. omap2_mcspi2_resources[0].start = OMAP4_MCSPI2_BASE;
  316. omap2_mcspi2_resources[0].end = OMAP4_MCSPI2_BASE + 0xff;
  317. omap2_mcspi3_resources[0].start = OMAP4_MCSPI3_BASE;
  318. omap2_mcspi3_resources[0].end = OMAP4_MCSPI3_BASE + 0xff;
  319. omap2_mcspi4_resources[0].start = OMAP4_MCSPI4_BASE;
  320. omap2_mcspi4_resources[0].end = OMAP4_MCSPI4_BASE + 0xff;
  321. }
  322. #else
  323. static inline void omap4_mcspi_fixup(void)
  324. {
  325. }
  326. #endif
  327. #if defined(CONFIG_ARCH_OMAP2430) || defined(CONFIG_ARCH_OMAP3) || \
  328. defined(CONFIG_ARCH_OMAP4)
  329. static inline void omap2_mcspi3_init(void)
  330. {
  331. platform_device_register(&omap2_mcspi3);
  332. }
  333. #else
  334. static inline void omap2_mcspi3_init(void)
  335. {
  336. }
  337. #endif
  338. #if defined(CONFIG_ARCH_OMAP3) || defined(CONFIG_ARCH_OMAP4)
  339. static inline void omap2_mcspi4_init(void)
  340. {
  341. platform_device_register(&omap2_mcspi4);
  342. }
  343. #else
  344. static inline void omap2_mcspi4_init(void)
  345. {
  346. }
  347. #endif
  348. static void omap_init_mcspi(void)
  349. {
  350. if (cpu_is_omap44xx())
  351. omap4_mcspi_fixup();
  352. platform_device_register(&omap2_mcspi1);
  353. platform_device_register(&omap2_mcspi2);
  354. if (cpu_is_omap2430() || cpu_is_omap343x() || cpu_is_omap44xx())
  355. omap2_mcspi3_init();
  356. if (cpu_is_omap343x() || cpu_is_omap44xx())
  357. omap2_mcspi4_init();
  358. }
  359. #else
  360. static inline void omap_init_mcspi(void) {}
  361. #endif
  362. static struct resource omap2_pmu_resource = {
  363. .start = 3,
  364. .end = 3,
  365. .flags = IORESOURCE_IRQ,
  366. };
  367. static struct resource omap3_pmu_resource = {
  368. .start = INT_34XX_BENCH_MPU_EMUL,
  369. .end = INT_34XX_BENCH_MPU_EMUL,
  370. .flags = IORESOURCE_IRQ,
  371. };
  372. static struct platform_device omap_pmu_device = {
  373. .name = "arm-pmu",
  374. .id = ARM_PMU_DEVICE_CPU,
  375. .num_resources = 1,
  376. };
  377. static void omap_init_pmu(void)
  378. {
  379. if (cpu_is_omap24xx())
  380. omap_pmu_device.resource = &omap2_pmu_resource;
  381. else if (cpu_is_omap34xx())
  382. omap_pmu_device.resource = &omap3_pmu_resource;
  383. else
  384. return;
  385. platform_device_register(&omap_pmu_device);
  386. }
  387. #if defined(CONFIG_CRYPTO_DEV_OMAP_SHAM) || defined(CONFIG_CRYPTO_DEV_OMAP_SHAM_MODULE)
  388. #ifdef CONFIG_ARCH_OMAP2
  389. static struct resource omap2_sham_resources[] = {
  390. {
  391. .start = OMAP24XX_SEC_SHA1MD5_BASE,
  392. .end = OMAP24XX_SEC_SHA1MD5_BASE + 0x64,
  393. .flags = IORESOURCE_MEM,
  394. },
  395. {
  396. .start = INT_24XX_SHA1MD5,
  397. .flags = IORESOURCE_IRQ,
  398. }
  399. };
  400. static int omap2_sham_resources_sz = ARRAY_SIZE(omap2_sham_resources);
  401. #else
  402. #define omap2_sham_resources NULL
  403. #define omap2_sham_resources_sz 0
  404. #endif
  405. #ifdef CONFIG_ARCH_OMAP3
  406. static struct resource omap3_sham_resources[] = {
  407. {
  408. .start = OMAP34XX_SEC_SHA1MD5_BASE,
  409. .end = OMAP34XX_SEC_SHA1MD5_BASE + 0x64,
  410. .flags = IORESOURCE_MEM,
  411. },
  412. {
  413. .start = INT_34XX_SHA1MD52_IRQ,
  414. .flags = IORESOURCE_IRQ,
  415. },
  416. {
  417. .start = OMAP34XX_DMA_SHA1MD5_RX,
  418. .flags = IORESOURCE_DMA,
  419. }
  420. };
  421. static int omap3_sham_resources_sz = ARRAY_SIZE(omap3_sham_resources);
  422. #else
  423. #define omap3_sham_resources NULL
  424. #define omap3_sham_resources_sz 0
  425. #endif
  426. static struct platform_device sham_device = {
  427. .name = "omap-sham",
  428. .id = -1,
  429. };
  430. static void omap_init_sham(void)
  431. {
  432. if (cpu_is_omap24xx()) {
  433. sham_device.resource = omap2_sham_resources;
  434. sham_device.num_resources = omap2_sham_resources_sz;
  435. } else if (cpu_is_omap34xx()) {
  436. sham_device.resource = omap3_sham_resources;
  437. sham_device.num_resources = omap3_sham_resources_sz;
  438. } else {
  439. pr_err("%s: platform not supported\n", __func__);
  440. return;
  441. }
  442. platform_device_register(&sham_device);
  443. }
  444. #else
  445. static inline void omap_init_sham(void) { }
  446. #endif
  447. #if defined(CONFIG_CRYPTO_DEV_OMAP_AES) || defined(CONFIG_CRYPTO_DEV_OMAP_AES_MODULE)
  448. #ifdef CONFIG_ARCH_OMAP2
  449. static struct resource omap2_aes_resources[] = {
  450. {
  451. .start = OMAP24XX_SEC_AES_BASE,
  452. .end = OMAP24XX_SEC_AES_BASE + 0x4C,
  453. .flags = IORESOURCE_MEM,
  454. },
  455. {
  456. .start = OMAP24XX_DMA_AES_TX,
  457. .flags = IORESOURCE_DMA,
  458. },
  459. {
  460. .start = OMAP24XX_DMA_AES_RX,
  461. .flags = IORESOURCE_DMA,
  462. }
  463. };
  464. static int omap2_aes_resources_sz = ARRAY_SIZE(omap2_aes_resources);
  465. #else
  466. #define omap2_aes_resources NULL
  467. #define omap2_aes_resources_sz 0
  468. #endif
  469. #ifdef CONFIG_ARCH_OMAP3
  470. static struct resource omap3_aes_resources[] = {
  471. {
  472. .start = OMAP34XX_SEC_AES_BASE,
  473. .end = OMAP34XX_SEC_AES_BASE + 0x4C,
  474. .flags = IORESOURCE_MEM,
  475. },
  476. {
  477. .start = OMAP34XX_DMA_AES2_TX,
  478. .flags = IORESOURCE_DMA,
  479. },
  480. {
  481. .start = OMAP34XX_DMA_AES2_RX,
  482. .flags = IORESOURCE_DMA,
  483. }
  484. };
  485. static int omap3_aes_resources_sz = ARRAY_SIZE(omap3_aes_resources);
  486. #else
  487. #define omap3_aes_resources NULL
  488. #define omap3_aes_resources_sz 0
  489. #endif
  490. static struct platform_device aes_device = {
  491. .name = "omap-aes",
  492. .id = -1,
  493. };
  494. static void omap_init_aes(void)
  495. {
  496. if (cpu_is_omap24xx()) {
  497. aes_device.resource = omap2_aes_resources;
  498. aes_device.num_resources = omap2_aes_resources_sz;
  499. } else if (cpu_is_omap34xx()) {
  500. aes_device.resource = omap3_aes_resources;
  501. aes_device.num_resources = omap3_aes_resources_sz;
  502. } else {
  503. pr_err("%s: platform not supported\n", __func__);
  504. return;
  505. }
  506. platform_device_register(&aes_device);
  507. }
  508. #else
  509. static inline void omap_init_aes(void) { }
  510. #endif
  511. /*-------------------------------------------------------------------------*/
  512. #if defined(CONFIG_ARCH_OMAP3) || defined(CONFIG_ARCH_OMAP4)
  513. #define MMCHS_SYSCONFIG 0x0010
  514. #define MMCHS_SYSCONFIG_SWRESET (1 << 1)
  515. #define MMCHS_SYSSTATUS 0x0014
  516. #define MMCHS_SYSSTATUS_RESETDONE (1 << 0)
  517. static struct platform_device dummy_pdev = {
  518. .dev = {
  519. .bus = &platform_bus_type,
  520. },
  521. };
  522. /**
  523. * omap_hsmmc_reset() - Full reset of each HS-MMC controller
  524. *
  525. * Ensure that each MMC controller is fully reset. Controllers
  526. * left in an unknown state (by bootloader) may prevent retention
  527. * or OFF-mode. This is especially important in cases where the
  528. * MMC driver is not enabled, _or_ built as a module.
  529. *
  530. * In order for reset to work, interface, functional and debounce
  531. * clocks must be enabled. The debounce clock comes from func_32k_clk
  532. * and is not under SW control, so we only enable i- and f-clocks.
  533. **/
  534. static void __init omap_hsmmc_reset(void)
  535. {
  536. u32 i, nr_controllers;
  537. if (cpu_is_omap242x())
  538. return;
  539. nr_controllers = cpu_is_omap44xx() ? OMAP44XX_NR_MMC :
  540. (cpu_is_omap34xx() ? OMAP34XX_NR_MMC : OMAP24XX_NR_MMC);
  541. for (i = 0; i < nr_controllers; i++) {
  542. u32 v, base = 0;
  543. struct clk *iclk, *fclk;
  544. struct device *dev = &dummy_pdev.dev;
  545. switch (i) {
  546. case 0:
  547. base = OMAP2_MMC1_BASE;
  548. break;
  549. case 1:
  550. base = OMAP2_MMC2_BASE;
  551. break;
  552. case 2:
  553. base = OMAP3_MMC3_BASE;
  554. break;
  555. case 3:
  556. if (!cpu_is_omap44xx())
  557. return;
  558. base = OMAP4_MMC4_BASE;
  559. break;
  560. case 4:
  561. if (!cpu_is_omap44xx())
  562. return;
  563. base = OMAP4_MMC5_BASE;
  564. break;
  565. }
  566. if (cpu_is_omap44xx())
  567. base += OMAP4_MMC_REG_OFFSET;
  568. dummy_pdev.id = i;
  569. dev_set_name(&dummy_pdev.dev, "mmci-omap-hs.%d", i);
  570. iclk = clk_get(dev, "ick");
  571. if (iclk && clk_enable(iclk))
  572. iclk = NULL;
  573. fclk = clk_get(dev, "fck");
  574. if (fclk && clk_enable(fclk))
  575. fclk = NULL;
  576. if (!iclk || !fclk) {
  577. printk(KERN_WARNING
  578. "%s: Unable to enable clocks for MMC%d, "
  579. "cannot reset.\n", __func__, i);
  580. break;
  581. }
  582. omap_writel(MMCHS_SYSCONFIG_SWRESET, base + MMCHS_SYSCONFIG);
  583. v = omap_readl(base + MMCHS_SYSSTATUS);
  584. while (!(omap_readl(base + MMCHS_SYSSTATUS) &
  585. MMCHS_SYSSTATUS_RESETDONE))
  586. cpu_relax();
  587. if (fclk) {
  588. clk_disable(fclk);
  589. clk_put(fclk);
  590. }
  591. if (iclk) {
  592. clk_disable(iclk);
  593. clk_put(iclk);
  594. }
  595. }
  596. }
  597. #else
  598. static inline void omap_hsmmc_reset(void) {}
  599. #endif
  600. #if defined(CONFIG_MMC_OMAP) || defined(CONFIG_MMC_OMAP_MODULE) || \
  601. defined(CONFIG_MMC_OMAP_HS) || defined(CONFIG_MMC_OMAP_HS_MODULE)
  602. static inline void omap2_mmc_mux(struct omap_mmc_platform_data *mmc_controller,
  603. int controller_nr)
  604. {
  605. if ((mmc_controller->slots[0].switch_pin > 0) && \
  606. (mmc_controller->slots[0].switch_pin < OMAP_MAX_GPIO_LINES))
  607. omap_mux_init_gpio(mmc_controller->slots[0].switch_pin,
  608. OMAP_PIN_INPUT_PULLUP);
  609. if ((mmc_controller->slots[0].gpio_wp > 0) && \
  610. (mmc_controller->slots[0].gpio_wp < OMAP_MAX_GPIO_LINES))
  611. omap_mux_init_gpio(mmc_controller->slots[0].gpio_wp,
  612. OMAP_PIN_INPUT_PULLUP);
  613. if (cpu_is_omap2420() && controller_nr == 0) {
  614. omap_mux_init_signal("sdmmc_cmd", 0);
  615. omap_mux_init_signal("sdmmc_clki", 0);
  616. omap_mux_init_signal("sdmmc_clko", 0);
  617. omap_mux_init_signal("sdmmc_dat0", 0);
  618. omap_mux_init_signal("sdmmc_dat_dir0", 0);
  619. omap_mux_init_signal("sdmmc_cmd_dir", 0);
  620. if (mmc_controller->slots[0].caps & MMC_CAP_4_BIT_DATA) {
  621. omap_mux_init_signal("sdmmc_dat1", 0);
  622. omap_mux_init_signal("sdmmc_dat2", 0);
  623. omap_mux_init_signal("sdmmc_dat3", 0);
  624. omap_mux_init_signal("sdmmc_dat_dir1", 0);
  625. omap_mux_init_signal("sdmmc_dat_dir2", 0);
  626. omap_mux_init_signal("sdmmc_dat_dir3", 0);
  627. }
  628. /*
  629. * Use internal loop-back in MMC/SDIO Module Input Clock
  630. * selection
  631. */
  632. if (mmc_controller->slots[0].internal_clock) {
  633. u32 v = omap_ctrl_readl(OMAP2_CONTROL_DEVCONF0);
  634. v |= (1 << 24);
  635. omap_ctrl_writel(v, OMAP2_CONTROL_DEVCONF0);
  636. }
  637. }
  638. if (cpu_is_omap34xx()) {
  639. if (controller_nr == 0) {
  640. omap_mux_init_signal("sdmmc1_clk",
  641. OMAP_PIN_INPUT_PULLUP);
  642. omap_mux_init_signal("sdmmc1_cmd",
  643. OMAP_PIN_INPUT_PULLUP);
  644. omap_mux_init_signal("sdmmc1_dat0",
  645. OMAP_PIN_INPUT_PULLUP);
  646. if (mmc_controller->slots[0].caps &
  647. (MMC_CAP_4_BIT_DATA | MMC_CAP_8_BIT_DATA)) {
  648. omap_mux_init_signal("sdmmc1_dat1",
  649. OMAP_PIN_INPUT_PULLUP);
  650. omap_mux_init_signal("sdmmc1_dat2",
  651. OMAP_PIN_INPUT_PULLUP);
  652. omap_mux_init_signal("sdmmc1_dat3",
  653. OMAP_PIN_INPUT_PULLUP);
  654. }
  655. if (mmc_controller->slots[0].caps &
  656. MMC_CAP_8_BIT_DATA) {
  657. omap_mux_init_signal("sdmmc1_dat4",
  658. OMAP_PIN_INPUT_PULLUP);
  659. omap_mux_init_signal("sdmmc1_dat5",
  660. OMAP_PIN_INPUT_PULLUP);
  661. omap_mux_init_signal("sdmmc1_dat6",
  662. OMAP_PIN_INPUT_PULLUP);
  663. omap_mux_init_signal("sdmmc1_dat7",
  664. OMAP_PIN_INPUT_PULLUP);
  665. }
  666. }
  667. if (controller_nr == 1) {
  668. /* MMC2 */
  669. omap_mux_init_signal("sdmmc2_clk",
  670. OMAP_PIN_INPUT_PULLUP);
  671. omap_mux_init_signal("sdmmc2_cmd",
  672. OMAP_PIN_INPUT_PULLUP);
  673. omap_mux_init_signal("sdmmc2_dat0",
  674. OMAP_PIN_INPUT_PULLUP);
  675. /*
  676. * For 8 wire configurations, Lines DAT4, 5, 6 and 7 need to be muxed
  677. * in the board-*.c files
  678. */
  679. if (mmc_controller->slots[0].caps &
  680. (MMC_CAP_4_BIT_DATA | MMC_CAP_8_BIT_DATA)) {
  681. omap_mux_init_signal("sdmmc2_dat1",
  682. OMAP_PIN_INPUT_PULLUP);
  683. omap_mux_init_signal("sdmmc2_dat2",
  684. OMAP_PIN_INPUT_PULLUP);
  685. omap_mux_init_signal("sdmmc2_dat3",
  686. OMAP_PIN_INPUT_PULLUP);
  687. }
  688. if (mmc_controller->slots[0].caps &
  689. MMC_CAP_8_BIT_DATA) {
  690. omap_mux_init_signal("sdmmc2_dat4.sdmmc2_dat4",
  691. OMAP_PIN_INPUT_PULLUP);
  692. omap_mux_init_signal("sdmmc2_dat5.sdmmc2_dat5",
  693. OMAP_PIN_INPUT_PULLUP);
  694. omap_mux_init_signal("sdmmc2_dat6.sdmmc2_dat6",
  695. OMAP_PIN_INPUT_PULLUP);
  696. omap_mux_init_signal("sdmmc2_dat7.sdmmc2_dat7",
  697. OMAP_PIN_INPUT_PULLUP);
  698. }
  699. }
  700. /*
  701. * For MMC3 the pins need to be muxed in the board-*.c files
  702. */
  703. }
  704. }
  705. void __init omap2_init_mmc(struct omap_mmc_platform_data **mmc_data,
  706. int nr_controllers)
  707. {
  708. int i;
  709. char *name;
  710. for (i = 0; i < nr_controllers; i++) {
  711. unsigned long base, size;
  712. unsigned int irq = 0;
  713. if (!mmc_data[i])
  714. continue;
  715. omap2_mmc_mux(mmc_data[i], i);
  716. switch (i) {
  717. case 0:
  718. base = OMAP2_MMC1_BASE;
  719. irq = INT_24XX_MMC_IRQ;
  720. break;
  721. case 1:
  722. base = OMAP2_MMC2_BASE;
  723. irq = INT_24XX_MMC2_IRQ;
  724. break;
  725. case 2:
  726. if (!cpu_is_omap44xx() && !cpu_is_omap34xx())
  727. return;
  728. base = OMAP3_MMC3_BASE;
  729. irq = INT_34XX_MMC3_IRQ;
  730. break;
  731. case 3:
  732. if (!cpu_is_omap44xx())
  733. return;
  734. base = OMAP4_MMC4_BASE;
  735. irq = OMAP44XX_IRQ_MMC4;
  736. break;
  737. case 4:
  738. if (!cpu_is_omap44xx())
  739. return;
  740. base = OMAP4_MMC5_BASE;
  741. irq = OMAP44XX_IRQ_MMC5;
  742. break;
  743. default:
  744. continue;
  745. }
  746. if (cpu_is_omap2420()) {
  747. size = OMAP2420_MMC_SIZE;
  748. name = "mmci-omap";
  749. } else if (cpu_is_omap44xx()) {
  750. if (i < 3)
  751. irq += OMAP44XX_IRQ_GIC_START;
  752. size = OMAP4_HSMMC_SIZE;
  753. name = "mmci-omap-hs";
  754. } else {
  755. size = OMAP3_HSMMC_SIZE;
  756. name = "mmci-omap-hs";
  757. }
  758. omap_mmc_add(name, i, base, size, irq, mmc_data[i]);
  759. };
  760. }
  761. #endif
  762. /*-------------------------------------------------------------------------*/
  763. #if defined(CONFIG_HDQ_MASTER_OMAP) || defined(CONFIG_HDQ_MASTER_OMAP_MODULE)
  764. #if defined(CONFIG_ARCH_OMAP2430) || defined(CONFIG_ARCH_OMAP3430)
  765. #define OMAP_HDQ_BASE 0x480B2000
  766. #endif
  767. static struct resource omap_hdq_resources[] = {
  768. {
  769. .start = OMAP_HDQ_BASE,
  770. .end = OMAP_HDQ_BASE + 0x1C,
  771. .flags = IORESOURCE_MEM,
  772. },
  773. {
  774. .start = INT_24XX_HDQ_IRQ,
  775. .flags = IORESOURCE_IRQ,
  776. },
  777. };
  778. static struct platform_device omap_hdq_dev = {
  779. .name = "omap_hdq",
  780. .id = 0,
  781. .dev = {
  782. .platform_data = NULL,
  783. },
  784. .num_resources = ARRAY_SIZE(omap_hdq_resources),
  785. .resource = omap_hdq_resources,
  786. };
  787. static inline void omap_hdq_init(void)
  788. {
  789. (void) platform_device_register(&omap_hdq_dev);
  790. }
  791. #else
  792. static inline void omap_hdq_init(void) {}
  793. #endif
  794. /*---------------------------------------------------------------------------*/
  795. #if defined(CONFIG_VIDEO_OMAP2_VOUT) || \
  796. defined(CONFIG_VIDEO_OMAP2_VOUT_MODULE)
  797. #if defined(CONFIG_FB_OMAP2) || defined(CONFIG_FB_OMAP2_MODULE)
  798. static struct resource omap_vout_resource[3 - CONFIG_FB_OMAP2_NUM_FBS] = {
  799. };
  800. #else
  801. static struct resource omap_vout_resource[2] = {
  802. };
  803. #endif
  804. static struct platform_device omap_vout_device = {
  805. .name = "omap_vout",
  806. .num_resources = ARRAY_SIZE(omap_vout_resource),
  807. .resource = &omap_vout_resource[0],
  808. .id = -1,
  809. };
  810. static void omap_init_vout(void)
  811. {
  812. if (platform_device_register(&omap_vout_device) < 0)
  813. printk(KERN_ERR "Unable to register OMAP-VOUT device\n");
  814. }
  815. #else
  816. static inline void omap_init_vout(void) {}
  817. #endif
  818. /*-------------------------------------------------------------------------*/
  819. static int __init omap2_init_devices(void)
  820. {
  821. /* please keep these calls, and their implementations above,
  822. * in alphabetical order so they're easier to sort through.
  823. */
  824. omap_hsmmc_reset();
  825. omap_init_camera();
  826. omap_init_mbox();
  827. omap_init_mcspi();
  828. omap_init_pmu();
  829. omap_hdq_init();
  830. omap_init_sti();
  831. omap_init_sham();
  832. omap_init_aes();
  833. omap_init_vout();
  834. return 0;
  835. }
  836. arch_initcall(omap2_init_devices);
  837. #if defined(CONFIG_OMAP_WATCHDOG) || defined(CONFIG_OMAP_WATCHDOG_MODULE)
  838. struct omap_device_pm_latency omap_wdt_latency[] = {
  839. [0] = {
  840. .deactivate_func = omap_device_idle_hwmods,
  841. .activate_func = omap_device_enable_hwmods,
  842. .flags = OMAP_DEVICE_LATENCY_AUTO_ADJUST,
  843. },
  844. };
  845. static int __init omap_init_wdt(void)
  846. {
  847. int id = -1;
  848. struct omap_device *od;
  849. struct omap_hwmod *oh;
  850. char *oh_name = "wd_timer2";
  851. char *dev_name = "omap_wdt";
  852. if (!cpu_class_is_omap2())
  853. return 0;
  854. oh = omap_hwmod_lookup(oh_name);
  855. if (!oh) {
  856. pr_err("Could not look up wd_timer%d hwmod\n", id);
  857. return -EINVAL;
  858. }
  859. od = omap_device_build(dev_name, id, oh, NULL, 0,
  860. omap_wdt_latency,
  861. ARRAY_SIZE(omap_wdt_latency), 0);
  862. WARN(IS_ERR(od), "Cant build omap_device for %s:%s.\n",
  863. dev_name, oh->name);
  864. return 0;
  865. }
  866. subsys_initcall(omap_init_wdt);
  867. #endif