board-ap325rxa.c 8.1 KB

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  1. /*
  2. * Renesas - AP-325RXA
  3. * (Compatible with Algo System ., LTD. - AP-320A)
  4. *
  5. * Copyright (C) 2008 Renesas Solutions Corp.
  6. * Author : Yusuke Goda <goda.yuske@renesas.com>
  7. *
  8. * This file is subject to the terms and conditions of the GNU General Public
  9. * License. See the file "COPYING" in the main directory of this archive
  10. * for more details.
  11. */
  12. #include <linux/init.h>
  13. #include <linux/device.h>
  14. #include <linux/interrupt.h>
  15. #include <linux/platform_device.h>
  16. #include <linux/mtd/physmap.h>
  17. #include <linux/delay.h>
  18. #include <linux/i2c.h>
  19. #include <linux/smc911x.h>
  20. #include <media/soc_camera_platform.h>
  21. #include <media/sh_mobile_ceu.h>
  22. #include <video/sh_mobile_lcdc.h>
  23. #include <asm/io.h>
  24. #include <asm/clock.h>
  25. static struct smc911x_platdata smc911x_info = {
  26. .flags = SMC911X_USE_32BIT,
  27. .irq_flags = IRQF_TRIGGER_LOW,
  28. };
  29. static struct resource smc9118_resources[] = {
  30. [0] = {
  31. .start = 0xb6080000,
  32. .end = 0xb60fffff,
  33. .flags = IORESOURCE_MEM,
  34. },
  35. [1] = {
  36. .start = 35,
  37. .end = 35,
  38. .flags = IORESOURCE_IRQ,
  39. }
  40. };
  41. static struct platform_device smc9118_device = {
  42. .name = "smc911x",
  43. .id = -1,
  44. .num_resources = ARRAY_SIZE(smc9118_resources),
  45. .resource = smc9118_resources,
  46. .dev = {
  47. .platform_data = &smc911x_info,
  48. },
  49. };
  50. /*
  51. * AP320 and AP325RXA has CPLD data in NOR Flash(0xA80000-0xABFFFF).
  52. * If this area erased, this board can not boot.
  53. */
  54. static struct mtd_partition ap325rxa_nor_flash_partitions[] = {
  55. {
  56. .name = "uboot",
  57. .offset = 0,
  58. .size = (1 * 1024 * 1024),
  59. .mask_flags = MTD_WRITEABLE, /* Read-only */
  60. }, {
  61. .name = "kernel",
  62. .offset = MTDPART_OFS_APPEND,
  63. .size = (2 * 1024 * 1024),
  64. }, {
  65. .name = "free-area0",
  66. .offset = MTDPART_OFS_APPEND,
  67. .size = ((7 * 1024 * 1024) + (512 * 1024)),
  68. }, {
  69. .name = "CPLD-Data",
  70. .offset = MTDPART_OFS_APPEND,
  71. .mask_flags = MTD_WRITEABLE, /* Read-only */
  72. .size = (1024 * 128 * 2),
  73. }, {
  74. .name = "free-area1",
  75. .offset = MTDPART_OFS_APPEND,
  76. .size = MTDPART_SIZ_FULL,
  77. },
  78. };
  79. static struct physmap_flash_data ap325rxa_nor_flash_data = {
  80. .width = 2,
  81. .parts = ap325rxa_nor_flash_partitions,
  82. .nr_parts = ARRAY_SIZE(ap325rxa_nor_flash_partitions),
  83. };
  84. static struct resource ap325rxa_nor_flash_resources[] = {
  85. [0] = {
  86. .name = "NOR Flash",
  87. .start = 0x00000000,
  88. .end = 0x00ffffff,
  89. .flags = IORESOURCE_MEM,
  90. }
  91. };
  92. static struct platform_device ap325rxa_nor_flash_device = {
  93. .name = "physmap-flash",
  94. .resource = ap325rxa_nor_flash_resources,
  95. .num_resources = ARRAY_SIZE(ap325rxa_nor_flash_resources),
  96. .dev = {
  97. .platform_data = &ap325rxa_nor_flash_data,
  98. },
  99. };
  100. #define FPGA_LCDREG 0xB4100180
  101. #define FPGA_BKLREG 0xB4100212
  102. #define FPGA_LCDREG_VAL 0x0018
  103. #define PORT_PHCR 0xA405010E
  104. #define PORT_PLCR 0xA4050114
  105. #define PORT_PMCR 0xA4050116
  106. #define PORT_PRCR 0xA405011C
  107. #define PORT_PSCR 0xA405011E
  108. #define PORT_PZCR 0xA405014C
  109. #define PORT_HIZCRA 0xA4050158
  110. #define PORT_MSELCRB 0xA4050182
  111. #define PORT_PSDR 0xA405013E
  112. #define PORT_PZDR 0xA405016C
  113. #define PORT_PSELD 0xA4050154
  114. static void ap320_wvga_power_on(void *board_data)
  115. {
  116. msleep(100);
  117. /* ASD AP-320/325 LCD ON */
  118. ctrl_outw(FPGA_LCDREG_VAL, FPGA_LCDREG);
  119. /* backlight */
  120. ctrl_outw((ctrl_inw(PORT_PSCR) & ~0x00C0) | 0x40, PORT_PSCR);
  121. ctrl_outb(ctrl_inb(PORT_PSDR) & ~0x08, PORT_PSDR);
  122. ctrl_outw(0x100, FPGA_BKLREG);
  123. }
  124. static struct sh_mobile_lcdc_info lcdc_info = {
  125. .clock_source = LCDC_CLK_EXTERNAL,
  126. .ch[0] = {
  127. .chan = LCDC_CHAN_MAINLCD,
  128. .bpp = 16,
  129. .interface_type = RGB18,
  130. .clock_divider = 1,
  131. .lcd_cfg = {
  132. .name = "LB070WV1",
  133. .xres = 800,
  134. .yres = 480,
  135. .left_margin = 40,
  136. .right_margin = 160,
  137. .hsync_len = 8,
  138. .upper_margin = 63,
  139. .lower_margin = 80,
  140. .vsync_len = 1,
  141. .sync = 0, /* hsync and vsync are active low */
  142. },
  143. .lcd_size_cfg = { /* 7.0 inch */
  144. .width = 152,
  145. .height = 91,
  146. },
  147. .board_cfg = {
  148. .display_on = ap320_wvga_power_on,
  149. },
  150. }
  151. };
  152. static struct resource lcdc_resources[] = {
  153. [0] = {
  154. .name = "LCDC",
  155. .start = 0xfe940000, /* P4-only space */
  156. .end = 0xfe941fff,
  157. .flags = IORESOURCE_MEM,
  158. },
  159. };
  160. static struct platform_device lcdc_device = {
  161. .name = "sh_mobile_lcdc_fb",
  162. .num_resources = ARRAY_SIZE(lcdc_resources),
  163. .resource = lcdc_resources,
  164. .dev = {
  165. .platform_data = &lcdc_info,
  166. },
  167. };
  168. #ifdef CONFIG_I2C
  169. static unsigned char camera_ncm03j_magic[] =
  170. {
  171. 0x87, 0x00, 0x88, 0x08, 0x89, 0x01, 0x8A, 0xE8,
  172. 0x1D, 0x00, 0x1E, 0x8A, 0x21, 0x00, 0x33, 0x36,
  173. 0x36, 0x60, 0x37, 0x08, 0x3B, 0x31, 0x44, 0x0F,
  174. 0x46, 0xF0, 0x4B, 0x28, 0x4C, 0x21, 0x4D, 0x55,
  175. 0x4E, 0x1B, 0x4F, 0xC7, 0x50, 0xFC, 0x51, 0x12,
  176. 0x58, 0x02, 0x66, 0xC0, 0x67, 0x46, 0x6B, 0xA0,
  177. 0x6C, 0x34, 0x7E, 0x25, 0x7F, 0x25, 0x8D, 0x0F,
  178. 0x92, 0x40, 0x93, 0x04, 0x94, 0x26, 0x95, 0x0A,
  179. 0x99, 0x03, 0x9A, 0xF0, 0x9B, 0x14, 0x9D, 0x7A,
  180. 0xC5, 0x02, 0xD6, 0x07, 0x59, 0x00, 0x5A, 0x1A,
  181. 0x5B, 0x2A, 0x5C, 0x37, 0x5D, 0x42, 0x5E, 0x56,
  182. 0xC8, 0x00, 0xC9, 0x1A, 0xCA, 0x2A, 0xCB, 0x37,
  183. 0xCC, 0x42, 0xCD, 0x56, 0xCE, 0x00, 0xCF, 0x1A,
  184. 0xD0, 0x2A, 0xD1, 0x37, 0xD2, 0x42, 0xD3, 0x56,
  185. 0x5F, 0x68, 0x60, 0x87, 0x61, 0xA3, 0x62, 0xBC,
  186. 0x63, 0xD4, 0x64, 0xEA, 0xD6, 0x0F,
  187. };
  188. static int camera_set_capture(struct soc_camera_platform_info *info,
  189. int enable)
  190. {
  191. struct i2c_adapter *a = i2c_get_adapter(0);
  192. struct i2c_msg msg;
  193. int ret = 0;
  194. int i;
  195. if (!enable)
  196. return 0; /* no disable for now */
  197. for (i = 0; i < ARRAY_SIZE(camera_ncm03j_magic); i += 2) {
  198. u_int8_t buf[8];
  199. msg.addr = 0x6e;
  200. msg.buf = buf;
  201. msg.len = 2;
  202. msg.flags = 0;
  203. buf[0] = camera_ncm03j_magic[i];
  204. buf[1] = camera_ncm03j_magic[i + 1];
  205. ret = (ret < 0) ? ret : i2c_transfer(a, &msg, 1);
  206. }
  207. return ret;
  208. }
  209. static struct soc_camera_platform_info camera_info = {
  210. .iface = 0,
  211. .format_name = "UYVY",
  212. .format_depth = 16,
  213. .format = {
  214. .pixelformat = V4L2_PIX_FMT_UYVY,
  215. .colorspace = V4L2_COLORSPACE_SMPTE170M,
  216. .width = 640,
  217. .height = 480,
  218. },
  219. .bus_param = SOCAM_PCLK_SAMPLE_RISING | SOCAM_HSYNC_ACTIVE_HIGH |
  220. SOCAM_VSYNC_ACTIVE_HIGH | SOCAM_MASTER | SOCAM_DATAWIDTH_8,
  221. .set_capture = camera_set_capture,
  222. };
  223. static struct platform_device camera_device = {
  224. .name = "soc_camera_platform",
  225. .dev = {
  226. .platform_data = &camera_info,
  227. },
  228. };
  229. #endif /* CONFIG_I2C */
  230. static struct sh_mobile_ceu_info sh_mobile_ceu_info = {
  231. .flags = SOCAM_PCLK_SAMPLE_RISING | SOCAM_HSYNC_ACTIVE_HIGH |
  232. SOCAM_VSYNC_ACTIVE_HIGH | SOCAM_MASTER | SOCAM_DATAWIDTH_8,
  233. };
  234. static struct resource ceu_resources[] = {
  235. [0] = {
  236. .name = "CEU",
  237. .start = 0xfe910000,
  238. .end = 0xfe91009f,
  239. .flags = IORESOURCE_MEM,
  240. },
  241. [1] = {
  242. .start = 52,
  243. .flags = IORESOURCE_IRQ,
  244. },
  245. [2] = {
  246. /* place holder for contiguous memory */
  247. },
  248. };
  249. static struct platform_device ceu_device = {
  250. .name = "sh_mobile_ceu",
  251. .num_resources = ARRAY_SIZE(ceu_resources),
  252. .resource = ceu_resources,
  253. .dev = {
  254. .platform_data = &sh_mobile_ceu_info,
  255. },
  256. };
  257. static struct platform_device *ap325rxa_devices[] __initdata = {
  258. &smc9118_device,
  259. &ap325rxa_nor_flash_device,
  260. &lcdc_device,
  261. &ceu_device,
  262. #ifdef CONFIG_I2C
  263. &camera_device,
  264. #endif
  265. };
  266. static struct i2c_board_info __initdata ap325rxa_i2c_devices[] = {
  267. };
  268. static int __init ap325rxa_devices_setup(void)
  269. {
  270. clk_always_enable("mstp200"); /* LCDC */
  271. clk_always_enable("mstp203"); /* CEU */
  272. platform_resource_setup_memory(&ceu_device, "ceu", 4 << 20);
  273. i2c_register_board_info(0, ap325rxa_i2c_devices,
  274. ARRAY_SIZE(ap325rxa_i2c_devices));
  275. return platform_add_devices(ap325rxa_devices,
  276. ARRAY_SIZE(ap325rxa_devices));
  277. }
  278. device_initcall(ap325rxa_devices_setup);
  279. static void __init ap325rxa_setup(char **cmdline_p)
  280. {
  281. /* LCDC configuration */
  282. ctrl_outw(ctrl_inw(PORT_PHCR) & ~0xffff, PORT_PHCR);
  283. ctrl_outw(ctrl_inw(PORT_PLCR) & ~0xffff, PORT_PLCR);
  284. ctrl_outw(ctrl_inw(PORT_PMCR) & ~0xffff, PORT_PMCR);
  285. ctrl_outw(ctrl_inw(PORT_PRCR) & ~0x03ff, PORT_PRCR);
  286. ctrl_outw(ctrl_inw(PORT_HIZCRA) & ~0x01C0, PORT_HIZCRA);
  287. /* CEU */
  288. ctrl_outw(ctrl_inw(PORT_MSELCRB) & ~0x0001, PORT_MSELCRB);
  289. ctrl_outw(ctrl_inw(PORT_PSELD) & ~0x0003, PORT_PSELD);
  290. ctrl_outw((ctrl_inw(PORT_PZCR) & ~0xff00) | 0x5500, PORT_PZCR);
  291. ctrl_outb((ctrl_inb(PORT_PZDR) & ~0xf0) | 0x20, PORT_PZDR);
  292. }
  293. static struct sh_machine_vector mv_ap325rxa __initmv = {
  294. .mv_name = "AP-325RXA",
  295. .mv_setup = ap325rxa_setup,
  296. };