caamalg.c 65 KB

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  1. /*
  2. * caam - Freescale FSL CAAM support for crypto API
  3. *
  4. * Copyright 2008-2011 Freescale Semiconductor, Inc.
  5. *
  6. * Based on talitos crypto API driver.
  7. *
  8. * relationship of job descriptors to shared descriptors (SteveC Dec 10 2008):
  9. *
  10. * --------------- ---------------
  11. * | JobDesc #1 |-------------------->| ShareDesc |
  12. * | *(packet 1) | | (PDB) |
  13. * --------------- |------------->| (hashKey) |
  14. * . | | (cipherKey) |
  15. * . | |-------->| (operation) |
  16. * --------------- | | ---------------
  17. * | JobDesc #2 |------| |
  18. * | *(packet 2) | |
  19. * --------------- |
  20. * . |
  21. * . |
  22. * --------------- |
  23. * | JobDesc #3 |------------
  24. * | *(packet 3) |
  25. * ---------------
  26. *
  27. * The SharedDesc never changes for a connection unless rekeyed, but
  28. * each packet will likely be in a different place. So all we need
  29. * to know to process the packet is where the input is, where the
  30. * output goes, and what context we want to process with. Context is
  31. * in the SharedDesc, packet references in the JobDesc.
  32. *
  33. * So, a job desc looks like:
  34. *
  35. * ---------------------
  36. * | Header |
  37. * | ShareDesc Pointer |
  38. * | SEQ_OUT_PTR |
  39. * | (output buffer) |
  40. * | (output length) |
  41. * | SEQ_IN_PTR |
  42. * | (input buffer) |
  43. * | (input length) |
  44. * ---------------------
  45. */
  46. #include "compat.h"
  47. #include "regs.h"
  48. #include "intern.h"
  49. #include "desc_constr.h"
  50. #include "jr.h"
  51. #include "error.h"
  52. #include "sg_sw_sec4.h"
  53. #include "key_gen.h"
  54. /*
  55. * crypto alg
  56. */
  57. #define CAAM_CRA_PRIORITY 3000
  58. /* max key is sum of AES_MAX_KEY_SIZE, max split key size */
  59. #define CAAM_MAX_KEY_SIZE (AES_MAX_KEY_SIZE + \
  60. SHA512_DIGEST_SIZE * 2)
  61. /* max IV is max of AES_BLOCK_SIZE, DES3_EDE_BLOCK_SIZE */
  62. #define CAAM_MAX_IV_LENGTH 16
  63. /* length of descriptors text */
  64. #define DESC_AEAD_BASE (4 * CAAM_CMD_SZ)
  65. #define DESC_AEAD_ENC_LEN (DESC_AEAD_BASE + 16 * CAAM_CMD_SZ)
  66. #define DESC_AEAD_DEC_LEN (DESC_AEAD_BASE + 21 * CAAM_CMD_SZ)
  67. #define DESC_AEAD_GIVENC_LEN (DESC_AEAD_ENC_LEN + 7 * CAAM_CMD_SZ)
  68. #define DESC_ABLKCIPHER_BASE (3 * CAAM_CMD_SZ)
  69. #define DESC_ABLKCIPHER_ENC_LEN (DESC_ABLKCIPHER_BASE + \
  70. 20 * CAAM_CMD_SZ)
  71. #define DESC_ABLKCIPHER_DEC_LEN (DESC_ABLKCIPHER_BASE + \
  72. 15 * CAAM_CMD_SZ)
  73. #define DESC_MAX_USED_BYTES (DESC_AEAD_GIVENC_LEN + \
  74. CAAM_MAX_KEY_SIZE)
  75. #define DESC_MAX_USED_LEN (DESC_MAX_USED_BYTES / CAAM_CMD_SZ)
  76. #ifdef DEBUG
  77. /* for print_hex_dumps with line references */
  78. #define debug(format, arg...) printk(format, arg)
  79. #else
  80. #define debug(format, arg...)
  81. #endif
  82. static struct list_head alg_list;
  83. /* Set DK bit in class 1 operation if shared */
  84. static inline void append_dec_op1(u32 *desc, u32 type)
  85. {
  86. u32 *jump_cmd, *uncond_jump_cmd;
  87. jump_cmd = append_jump(desc, JUMP_TEST_ALL | JUMP_COND_SHRD);
  88. append_operation(desc, type | OP_ALG_AS_INITFINAL |
  89. OP_ALG_DECRYPT);
  90. uncond_jump_cmd = append_jump(desc, JUMP_TEST_ALL);
  91. set_jump_tgt_here(desc, jump_cmd);
  92. append_operation(desc, type | OP_ALG_AS_INITFINAL |
  93. OP_ALG_DECRYPT | OP_ALG_AAI_DK);
  94. set_jump_tgt_here(desc, uncond_jump_cmd);
  95. }
  96. /*
  97. * Wait for completion of class 1 key loading before allowing
  98. * error propagation
  99. */
  100. static inline void append_dec_shr_done(u32 *desc)
  101. {
  102. u32 *jump_cmd;
  103. jump_cmd = append_jump(desc, JUMP_CLASS_CLASS1 | JUMP_TEST_ALL);
  104. set_jump_tgt_here(desc, jump_cmd);
  105. append_cmd(desc, SET_OK_NO_PROP_ERRORS | CMD_LOAD);
  106. }
  107. /*
  108. * For aead functions, read payload and write payload,
  109. * both of which are specified in req->src and req->dst
  110. */
  111. static inline void aead_append_src_dst(u32 *desc, u32 msg_type)
  112. {
  113. append_seq_fifo_load(desc, 0, FIFOLD_CLASS_BOTH |
  114. KEY_VLF | msg_type | FIFOLD_TYPE_LASTBOTH);
  115. append_seq_fifo_store(desc, 0, FIFOST_TYPE_MESSAGE_DATA | KEY_VLF);
  116. }
  117. /*
  118. * For aead encrypt and decrypt, read iv for both classes
  119. */
  120. static inline void aead_append_ld_iv(u32 *desc, int ivsize)
  121. {
  122. append_cmd(desc, CMD_SEQ_LOAD | LDST_SRCDST_BYTE_CONTEXT |
  123. LDST_CLASS_1_CCB | ivsize);
  124. append_move(desc, MOVE_SRC_CLASS1CTX | MOVE_DEST_CLASS2INFIFO | ivsize);
  125. }
  126. /*
  127. * For ablkcipher encrypt and decrypt, read from req->src and
  128. * write to req->dst
  129. */
  130. static inline void ablkcipher_append_src_dst(u32 *desc)
  131. {
  132. append_math_add(desc, VARSEQOUTLEN, SEQINLEN, REG0, CAAM_CMD_SZ);
  133. append_math_add(desc, VARSEQINLEN, SEQINLEN, REG0, CAAM_CMD_SZ);
  134. append_seq_fifo_load(desc, 0, FIFOLD_CLASS_CLASS1 |
  135. KEY_VLF | FIFOLD_TYPE_MSG | FIFOLD_TYPE_LAST1);
  136. append_seq_fifo_store(desc, 0, FIFOST_TYPE_MESSAGE_DATA | KEY_VLF);
  137. }
  138. /*
  139. * If all data, including src (with assoc and iv) or dst (with iv only) are
  140. * contiguous
  141. */
  142. #define GIV_SRC_CONTIG 1
  143. #define GIV_DST_CONTIG (1 << 1)
  144. /*
  145. * per-session context
  146. */
  147. struct caam_ctx {
  148. struct device *jrdev;
  149. u32 sh_desc_enc[DESC_MAX_USED_LEN];
  150. u32 sh_desc_dec[DESC_MAX_USED_LEN];
  151. u32 sh_desc_givenc[DESC_MAX_USED_LEN];
  152. dma_addr_t sh_desc_enc_dma;
  153. dma_addr_t sh_desc_dec_dma;
  154. dma_addr_t sh_desc_givenc_dma;
  155. u32 class1_alg_type;
  156. u32 class2_alg_type;
  157. u32 alg_op;
  158. u8 key[CAAM_MAX_KEY_SIZE];
  159. dma_addr_t key_dma;
  160. unsigned int enckeylen;
  161. unsigned int split_key_len;
  162. unsigned int split_key_pad_len;
  163. unsigned int authsize;
  164. };
  165. static void append_key_aead(u32 *desc, struct caam_ctx *ctx,
  166. int keys_fit_inline)
  167. {
  168. if (keys_fit_inline) {
  169. append_key_as_imm(desc, ctx->key, ctx->split_key_pad_len,
  170. ctx->split_key_len, CLASS_2 |
  171. KEY_DEST_MDHA_SPLIT | KEY_ENC);
  172. append_key_as_imm(desc, (void *)ctx->key +
  173. ctx->split_key_pad_len, ctx->enckeylen,
  174. ctx->enckeylen, CLASS_1 | KEY_DEST_CLASS_REG);
  175. } else {
  176. append_key(desc, ctx->key_dma, ctx->split_key_len, CLASS_2 |
  177. KEY_DEST_MDHA_SPLIT | KEY_ENC);
  178. append_key(desc, ctx->key_dma + ctx->split_key_pad_len,
  179. ctx->enckeylen, CLASS_1 | KEY_DEST_CLASS_REG);
  180. }
  181. }
  182. static void init_sh_desc_key_aead(u32 *desc, struct caam_ctx *ctx,
  183. int keys_fit_inline)
  184. {
  185. u32 *key_jump_cmd;
  186. init_sh_desc(desc, HDR_SHARE_SERIAL);
  187. /* Skip if already shared */
  188. key_jump_cmd = append_jump(desc, JUMP_JSL | JUMP_TEST_ALL |
  189. JUMP_COND_SHRD);
  190. append_key_aead(desc, ctx, keys_fit_inline);
  191. set_jump_tgt_here(desc, key_jump_cmd);
  192. /* Propagate errors from shared to job descriptor */
  193. append_cmd(desc, SET_OK_NO_PROP_ERRORS | CMD_LOAD);
  194. }
  195. static int aead_set_sh_desc(struct crypto_aead *aead)
  196. {
  197. struct aead_tfm *tfm = &aead->base.crt_aead;
  198. struct caam_ctx *ctx = crypto_aead_ctx(aead);
  199. struct device *jrdev = ctx->jrdev;
  200. bool keys_fit_inline = false;
  201. u32 *key_jump_cmd, *jump_cmd;
  202. u32 geniv, moveiv;
  203. u32 *desc;
  204. if (!ctx->enckeylen || !ctx->authsize)
  205. return 0;
  206. /*
  207. * Job Descriptor and Shared Descriptors
  208. * must all fit into the 64-word Descriptor h/w Buffer
  209. */
  210. if (DESC_AEAD_ENC_LEN + DESC_JOB_IO_LEN +
  211. ctx->split_key_pad_len + ctx->enckeylen <=
  212. CAAM_DESC_BYTES_MAX)
  213. keys_fit_inline = true;
  214. /* aead_encrypt shared descriptor */
  215. desc = ctx->sh_desc_enc;
  216. init_sh_desc_key_aead(desc, ctx, keys_fit_inline);
  217. /* Class 2 operation */
  218. append_operation(desc, ctx->class2_alg_type |
  219. OP_ALG_AS_INITFINAL | OP_ALG_ENCRYPT);
  220. /* cryptlen = seqoutlen - authsize */
  221. append_math_sub_imm_u32(desc, REG3, SEQOUTLEN, IMM, ctx->authsize);
  222. /* assoclen + cryptlen = seqinlen - ivsize */
  223. append_math_sub_imm_u32(desc, REG2, SEQINLEN, IMM, tfm->ivsize);
  224. /* assoclen + cryptlen = (assoclen + cryptlen) - cryptlen */
  225. append_math_sub(desc, VARSEQINLEN, REG2, REG3, CAAM_CMD_SZ);
  226. /* read assoc before reading payload */
  227. append_seq_fifo_load(desc, 0, FIFOLD_CLASS_CLASS2 | FIFOLD_TYPE_MSG |
  228. KEY_VLF);
  229. aead_append_ld_iv(desc, tfm->ivsize);
  230. /* Class 1 operation */
  231. append_operation(desc, ctx->class1_alg_type |
  232. OP_ALG_AS_INITFINAL | OP_ALG_ENCRYPT);
  233. /* Read and write cryptlen bytes */
  234. append_math_add(desc, VARSEQINLEN, ZERO, REG3, CAAM_CMD_SZ);
  235. append_math_add(desc, VARSEQOUTLEN, ZERO, REG3, CAAM_CMD_SZ);
  236. aead_append_src_dst(desc, FIFOLD_TYPE_MSG1OUT2);
  237. /* Write ICV */
  238. append_seq_store(desc, ctx->authsize, LDST_CLASS_2_CCB |
  239. LDST_SRCDST_BYTE_CONTEXT);
  240. ctx->sh_desc_enc_dma = dma_map_single(jrdev, desc,
  241. desc_bytes(desc),
  242. DMA_TO_DEVICE);
  243. if (dma_mapping_error(jrdev, ctx->sh_desc_enc_dma)) {
  244. dev_err(jrdev, "unable to map shared descriptor\n");
  245. return -ENOMEM;
  246. }
  247. #ifdef DEBUG
  248. print_hex_dump(KERN_ERR, "aead enc shdesc@"__stringify(__LINE__)": ",
  249. DUMP_PREFIX_ADDRESS, 16, 4, desc,
  250. desc_bytes(desc), 1);
  251. #endif
  252. /*
  253. * Job Descriptor and Shared Descriptors
  254. * must all fit into the 64-word Descriptor h/w Buffer
  255. */
  256. if (DESC_AEAD_DEC_LEN + DESC_JOB_IO_LEN +
  257. ctx->split_key_pad_len + ctx->enckeylen <=
  258. CAAM_DESC_BYTES_MAX)
  259. keys_fit_inline = true;
  260. desc = ctx->sh_desc_dec;
  261. /* aead_decrypt shared descriptor */
  262. init_sh_desc(desc, HDR_SHARE_SERIAL);
  263. /* Skip if already shared */
  264. key_jump_cmd = append_jump(desc, JUMP_JSL | JUMP_TEST_ALL |
  265. JUMP_COND_SHRD);
  266. append_key_aead(desc, ctx, keys_fit_inline);
  267. /* Only propagate error immediately if shared */
  268. jump_cmd = append_jump(desc, JUMP_TEST_ALL);
  269. set_jump_tgt_here(desc, key_jump_cmd);
  270. append_cmd(desc, SET_OK_NO_PROP_ERRORS | CMD_LOAD);
  271. set_jump_tgt_here(desc, jump_cmd);
  272. /* Class 2 operation */
  273. append_operation(desc, ctx->class2_alg_type |
  274. OP_ALG_AS_INITFINAL | OP_ALG_DECRYPT | OP_ALG_ICV_ON);
  275. /* assoclen + cryptlen = seqinlen - ivsize */
  276. append_math_sub_imm_u32(desc, REG3, SEQINLEN, IMM,
  277. ctx->authsize + tfm->ivsize)
  278. /* assoclen = (assoclen + cryptlen) - cryptlen */
  279. append_math_sub(desc, REG2, SEQOUTLEN, REG0, CAAM_CMD_SZ);
  280. append_math_sub(desc, VARSEQINLEN, REG3, REG2, CAAM_CMD_SZ);
  281. /* read assoc before reading payload */
  282. append_seq_fifo_load(desc, 0, FIFOLD_CLASS_CLASS2 | FIFOLD_TYPE_MSG |
  283. KEY_VLF);
  284. aead_append_ld_iv(desc, tfm->ivsize);
  285. append_dec_op1(desc, ctx->class1_alg_type);
  286. /* Read and write cryptlen bytes */
  287. append_math_add(desc, VARSEQINLEN, ZERO, REG2, CAAM_CMD_SZ);
  288. append_math_add(desc, VARSEQOUTLEN, ZERO, REG2, CAAM_CMD_SZ);
  289. aead_append_src_dst(desc, FIFOLD_TYPE_MSG);
  290. /* Load ICV */
  291. append_seq_fifo_load(desc, ctx->authsize, FIFOLD_CLASS_CLASS2 |
  292. FIFOLD_TYPE_LAST2 | FIFOLD_TYPE_ICV);
  293. append_dec_shr_done(desc);
  294. ctx->sh_desc_dec_dma = dma_map_single(jrdev, desc,
  295. desc_bytes(desc),
  296. DMA_TO_DEVICE);
  297. if (dma_mapping_error(jrdev, ctx->sh_desc_dec_dma)) {
  298. dev_err(jrdev, "unable to map shared descriptor\n");
  299. return -ENOMEM;
  300. }
  301. #ifdef DEBUG
  302. print_hex_dump(KERN_ERR, "aead dec shdesc@"__stringify(__LINE__)": ",
  303. DUMP_PREFIX_ADDRESS, 16, 4, desc,
  304. desc_bytes(desc), 1);
  305. #endif
  306. /*
  307. * Job Descriptor and Shared Descriptors
  308. * must all fit into the 64-word Descriptor h/w Buffer
  309. */
  310. if (DESC_AEAD_GIVENC_LEN + DESC_JOB_IO_LEN +
  311. ctx->split_key_pad_len + ctx->enckeylen <=
  312. CAAM_DESC_BYTES_MAX)
  313. keys_fit_inline = true;
  314. /* aead_givencrypt shared descriptor */
  315. desc = ctx->sh_desc_givenc;
  316. init_sh_desc_key_aead(desc, ctx, keys_fit_inline);
  317. /* Generate IV */
  318. geniv = NFIFOENTRY_STYPE_PAD | NFIFOENTRY_DEST_DECO |
  319. NFIFOENTRY_DTYPE_MSG | NFIFOENTRY_LC1 |
  320. NFIFOENTRY_PTYPE_RND | (tfm->ivsize << NFIFOENTRY_DLEN_SHIFT);
  321. append_load_imm_u32(desc, geniv, LDST_CLASS_IND_CCB |
  322. LDST_SRCDST_WORD_INFO_FIFO | LDST_IMM);
  323. append_cmd(desc, CMD_LOAD | DISABLE_AUTO_INFO_FIFO);
  324. append_move(desc, MOVE_SRC_INFIFO |
  325. MOVE_DEST_CLASS1CTX | (tfm->ivsize << MOVE_LEN_SHIFT));
  326. append_cmd(desc, CMD_LOAD | ENABLE_AUTO_INFO_FIFO);
  327. /* Copy IV to class 1 context */
  328. append_move(desc, MOVE_SRC_CLASS1CTX |
  329. MOVE_DEST_OUTFIFO | (tfm->ivsize << MOVE_LEN_SHIFT));
  330. /* Return to encryption */
  331. append_operation(desc, ctx->class2_alg_type |
  332. OP_ALG_AS_INITFINAL | OP_ALG_ENCRYPT);
  333. /* ivsize + cryptlen = seqoutlen - authsize */
  334. append_math_sub_imm_u32(desc, REG3, SEQOUTLEN, IMM, ctx->authsize);
  335. /* assoclen = seqinlen - (ivsize + cryptlen) */
  336. append_math_sub(desc, VARSEQINLEN, SEQINLEN, REG3, CAAM_CMD_SZ);
  337. /* read assoc before reading payload */
  338. append_seq_fifo_load(desc, 0, FIFOLD_CLASS_CLASS2 | FIFOLD_TYPE_MSG |
  339. KEY_VLF);
  340. /* Copy iv from class 1 ctx to class 2 fifo*/
  341. moveiv = NFIFOENTRY_STYPE_OFIFO | NFIFOENTRY_DEST_CLASS2 |
  342. NFIFOENTRY_DTYPE_MSG | (tfm->ivsize << NFIFOENTRY_DLEN_SHIFT);
  343. append_load_imm_u32(desc, moveiv, LDST_CLASS_IND_CCB |
  344. LDST_SRCDST_WORD_INFO_FIFO | LDST_IMM);
  345. append_load_imm_u32(desc, tfm->ivsize, LDST_CLASS_2_CCB |
  346. LDST_SRCDST_WORD_DATASZ_REG | LDST_IMM);
  347. /* Class 1 operation */
  348. append_operation(desc, ctx->class1_alg_type |
  349. OP_ALG_AS_INITFINAL | OP_ALG_ENCRYPT);
  350. /* Will write ivsize + cryptlen */
  351. append_math_add(desc, VARSEQOUTLEN, SEQINLEN, REG0, CAAM_CMD_SZ);
  352. /* Not need to reload iv */
  353. append_seq_fifo_load(desc, tfm->ivsize,
  354. FIFOLD_CLASS_SKIP);
  355. /* Will read cryptlen */
  356. append_math_add(desc, VARSEQINLEN, SEQINLEN, REG0, CAAM_CMD_SZ);
  357. aead_append_src_dst(desc, FIFOLD_TYPE_MSG1OUT2);
  358. /* Write ICV */
  359. append_seq_store(desc, ctx->authsize, LDST_CLASS_2_CCB |
  360. LDST_SRCDST_BYTE_CONTEXT);
  361. ctx->sh_desc_givenc_dma = dma_map_single(jrdev, desc,
  362. desc_bytes(desc),
  363. DMA_TO_DEVICE);
  364. if (dma_mapping_error(jrdev, ctx->sh_desc_givenc_dma)) {
  365. dev_err(jrdev, "unable to map shared descriptor\n");
  366. return -ENOMEM;
  367. }
  368. #ifdef DEBUG
  369. print_hex_dump(KERN_ERR, "aead givenc shdesc@"__stringify(__LINE__)": ",
  370. DUMP_PREFIX_ADDRESS, 16, 4, desc,
  371. desc_bytes(desc), 1);
  372. #endif
  373. return 0;
  374. }
  375. static int aead_setauthsize(struct crypto_aead *authenc,
  376. unsigned int authsize)
  377. {
  378. struct caam_ctx *ctx = crypto_aead_ctx(authenc);
  379. ctx->authsize = authsize;
  380. aead_set_sh_desc(authenc);
  381. return 0;
  382. }
  383. static u32 gen_split_aead_key(struct caam_ctx *ctx, const u8 *key_in,
  384. u32 authkeylen)
  385. {
  386. return gen_split_key(ctx->jrdev, ctx->key, ctx->split_key_len,
  387. ctx->split_key_pad_len, key_in, authkeylen,
  388. ctx->alg_op);
  389. }
  390. static int aead_setkey(struct crypto_aead *aead,
  391. const u8 *key, unsigned int keylen)
  392. {
  393. /* Sizes for MDHA pads (*not* keys): MD5, SHA1, 224, 256, 384, 512 */
  394. static const u8 mdpadlen[] = { 16, 20, 32, 32, 64, 64 };
  395. struct caam_ctx *ctx = crypto_aead_ctx(aead);
  396. struct device *jrdev = ctx->jrdev;
  397. struct rtattr *rta = (void *)key;
  398. struct crypto_authenc_key_param *param;
  399. unsigned int authkeylen;
  400. unsigned int enckeylen;
  401. int ret = 0;
  402. param = RTA_DATA(rta);
  403. enckeylen = be32_to_cpu(param->enckeylen);
  404. key += RTA_ALIGN(rta->rta_len);
  405. keylen -= RTA_ALIGN(rta->rta_len);
  406. if (keylen < enckeylen)
  407. goto badkey;
  408. authkeylen = keylen - enckeylen;
  409. if (keylen > CAAM_MAX_KEY_SIZE)
  410. goto badkey;
  411. /* Pick class 2 key length from algorithm submask */
  412. ctx->split_key_len = mdpadlen[(ctx->alg_op & OP_ALG_ALGSEL_SUBMASK) >>
  413. OP_ALG_ALGSEL_SHIFT] * 2;
  414. ctx->split_key_pad_len = ALIGN(ctx->split_key_len, 16);
  415. #ifdef DEBUG
  416. printk(KERN_ERR "keylen %d enckeylen %d authkeylen %d\n",
  417. keylen, enckeylen, authkeylen);
  418. printk(KERN_ERR "split_key_len %d split_key_pad_len %d\n",
  419. ctx->split_key_len, ctx->split_key_pad_len);
  420. print_hex_dump(KERN_ERR, "key in @"__stringify(__LINE__)": ",
  421. DUMP_PREFIX_ADDRESS, 16, 4, key, keylen, 1);
  422. #endif
  423. ret = gen_split_aead_key(ctx, key, authkeylen);
  424. if (ret) {
  425. goto badkey;
  426. }
  427. /* postpend encryption key to auth split key */
  428. memcpy(ctx->key + ctx->split_key_pad_len, key + authkeylen, enckeylen);
  429. ctx->key_dma = dma_map_single(jrdev, ctx->key, ctx->split_key_pad_len +
  430. enckeylen, DMA_TO_DEVICE);
  431. if (dma_mapping_error(jrdev, ctx->key_dma)) {
  432. dev_err(jrdev, "unable to map key i/o memory\n");
  433. return -ENOMEM;
  434. }
  435. #ifdef DEBUG
  436. print_hex_dump(KERN_ERR, "ctx.key@"__stringify(__LINE__)": ",
  437. DUMP_PREFIX_ADDRESS, 16, 4, ctx->key,
  438. ctx->split_key_pad_len + enckeylen, 1);
  439. #endif
  440. ctx->enckeylen = enckeylen;
  441. ret = aead_set_sh_desc(aead);
  442. if (ret) {
  443. dma_unmap_single(jrdev, ctx->key_dma, ctx->split_key_pad_len +
  444. enckeylen, DMA_TO_DEVICE);
  445. }
  446. return ret;
  447. badkey:
  448. crypto_aead_set_flags(aead, CRYPTO_TFM_RES_BAD_KEY_LEN);
  449. return -EINVAL;
  450. }
  451. static int ablkcipher_setkey(struct crypto_ablkcipher *ablkcipher,
  452. const u8 *key, unsigned int keylen)
  453. {
  454. struct caam_ctx *ctx = crypto_ablkcipher_ctx(ablkcipher);
  455. struct ablkcipher_tfm *tfm = &ablkcipher->base.crt_ablkcipher;
  456. struct device *jrdev = ctx->jrdev;
  457. int ret = 0;
  458. u32 *key_jump_cmd, *jump_cmd;
  459. u32 *desc;
  460. #ifdef DEBUG
  461. print_hex_dump(KERN_ERR, "key in @"__stringify(__LINE__)": ",
  462. DUMP_PREFIX_ADDRESS, 16, 4, key, keylen, 1);
  463. #endif
  464. memcpy(ctx->key, key, keylen);
  465. ctx->key_dma = dma_map_single(jrdev, ctx->key, keylen,
  466. DMA_TO_DEVICE);
  467. if (dma_mapping_error(jrdev, ctx->key_dma)) {
  468. dev_err(jrdev, "unable to map key i/o memory\n");
  469. return -ENOMEM;
  470. }
  471. ctx->enckeylen = keylen;
  472. /* ablkcipher_encrypt shared descriptor */
  473. desc = ctx->sh_desc_enc;
  474. init_sh_desc(desc, HDR_SHARE_SERIAL);
  475. /* Skip if already shared */
  476. key_jump_cmd = append_jump(desc, JUMP_JSL | JUMP_TEST_ALL |
  477. JUMP_COND_SHRD);
  478. /* Load class1 key only */
  479. append_key_as_imm(desc, (void *)ctx->key, ctx->enckeylen,
  480. ctx->enckeylen, CLASS_1 |
  481. KEY_DEST_CLASS_REG);
  482. set_jump_tgt_here(desc, key_jump_cmd);
  483. /* Propagate errors from shared to job descriptor */
  484. append_cmd(desc, SET_OK_NO_PROP_ERRORS | CMD_LOAD);
  485. /* Load iv */
  486. append_cmd(desc, CMD_SEQ_LOAD | LDST_SRCDST_BYTE_CONTEXT |
  487. LDST_CLASS_1_CCB | tfm->ivsize);
  488. /* Load operation */
  489. append_operation(desc, ctx->class1_alg_type |
  490. OP_ALG_AS_INITFINAL | OP_ALG_ENCRYPT);
  491. /* Perform operation */
  492. ablkcipher_append_src_dst(desc);
  493. ctx->sh_desc_enc_dma = dma_map_single(jrdev, desc,
  494. desc_bytes(desc),
  495. DMA_TO_DEVICE);
  496. if (dma_mapping_error(jrdev, ctx->sh_desc_enc_dma)) {
  497. dev_err(jrdev, "unable to map shared descriptor\n");
  498. return -ENOMEM;
  499. }
  500. #ifdef DEBUG
  501. print_hex_dump(KERN_ERR,
  502. "ablkcipher enc shdesc@"__stringify(__LINE__)": ",
  503. DUMP_PREFIX_ADDRESS, 16, 4, desc,
  504. desc_bytes(desc), 1);
  505. #endif
  506. /* ablkcipher_decrypt shared descriptor */
  507. desc = ctx->sh_desc_dec;
  508. init_sh_desc(desc, HDR_SHARE_SERIAL);
  509. /* Skip if already shared */
  510. key_jump_cmd = append_jump(desc, JUMP_JSL | JUMP_TEST_ALL |
  511. JUMP_COND_SHRD);
  512. /* Load class1 key only */
  513. append_key_as_imm(desc, (void *)ctx->key, ctx->enckeylen,
  514. ctx->enckeylen, CLASS_1 |
  515. KEY_DEST_CLASS_REG);
  516. /* For aead, only propagate error immediately if shared */
  517. jump_cmd = append_jump(desc, JUMP_TEST_ALL);
  518. set_jump_tgt_here(desc, key_jump_cmd);
  519. append_cmd(desc, SET_OK_NO_PROP_ERRORS | CMD_LOAD);
  520. set_jump_tgt_here(desc, jump_cmd);
  521. /* load IV */
  522. append_cmd(desc, CMD_SEQ_LOAD | LDST_SRCDST_BYTE_CONTEXT |
  523. LDST_CLASS_1_CCB | tfm->ivsize);
  524. /* Choose operation */
  525. append_dec_op1(desc, ctx->class1_alg_type);
  526. /* Perform operation */
  527. ablkcipher_append_src_dst(desc);
  528. /* Wait for key to load before allowing propagating error */
  529. append_dec_shr_done(desc);
  530. ctx->sh_desc_dec_dma = dma_map_single(jrdev, desc,
  531. desc_bytes(desc),
  532. DMA_TO_DEVICE);
  533. if (dma_mapping_error(jrdev, ctx->sh_desc_enc_dma)) {
  534. dev_err(jrdev, "unable to map shared descriptor\n");
  535. return -ENOMEM;
  536. }
  537. #ifdef DEBUG
  538. print_hex_dump(KERN_ERR,
  539. "ablkcipher dec shdesc@"__stringify(__LINE__)": ",
  540. DUMP_PREFIX_ADDRESS, 16, 4, desc,
  541. desc_bytes(desc), 1);
  542. #endif
  543. return ret;
  544. }
  545. /*
  546. * aead_edesc - s/w-extended aead descriptor
  547. * @assoc_nents: number of segments in associated data (SPI+Seq) scatterlist
  548. * @assoc_chained: if source is chained
  549. * @src_nents: number of segments in input scatterlist
  550. * @src_chained: if source is chained
  551. * @dst_nents: number of segments in output scatterlist
  552. * @dst_chained: if destination is chained
  553. * @iv_dma: dma address of iv for checking continuity and link table
  554. * @desc: h/w descriptor (variable length; must not exceed MAX_CAAM_DESCSIZE)
  555. * @sec4_sg_bytes: length of dma mapped sec4_sg space
  556. * @sec4_sg_dma: bus physical mapped address of h/w link table
  557. * @hw_desc: the h/w job descriptor followed by any referenced link tables
  558. */
  559. struct aead_edesc {
  560. int assoc_nents;
  561. bool assoc_chained;
  562. int src_nents;
  563. bool src_chained;
  564. int dst_nents;
  565. bool dst_chained;
  566. dma_addr_t iv_dma;
  567. int sec4_sg_bytes;
  568. dma_addr_t sec4_sg_dma;
  569. struct sec4_sg_entry *sec4_sg;
  570. u32 hw_desc[0];
  571. };
  572. /*
  573. * ablkcipher_edesc - s/w-extended ablkcipher descriptor
  574. * @src_nents: number of segments in input scatterlist
  575. * @src_chained: if source is chained
  576. * @dst_nents: number of segments in output scatterlist
  577. * @dst_chained: if destination is chained
  578. * @iv_dma: dma address of iv for checking continuity and link table
  579. * @desc: h/w descriptor (variable length; must not exceed MAX_CAAM_DESCSIZE)
  580. * @sec4_sg_bytes: length of dma mapped sec4_sg space
  581. * @sec4_sg_dma: bus physical mapped address of h/w link table
  582. * @hw_desc: the h/w job descriptor followed by any referenced link tables
  583. */
  584. struct ablkcipher_edesc {
  585. int src_nents;
  586. bool src_chained;
  587. int dst_nents;
  588. bool dst_chained;
  589. dma_addr_t iv_dma;
  590. int sec4_sg_bytes;
  591. dma_addr_t sec4_sg_dma;
  592. struct sec4_sg_entry *sec4_sg;
  593. u32 hw_desc[0];
  594. };
  595. static void caam_unmap(struct device *dev, struct scatterlist *src,
  596. struct scatterlist *dst, int src_nents,
  597. bool src_chained, int dst_nents, bool dst_chained,
  598. dma_addr_t iv_dma, int ivsize, dma_addr_t sec4_sg_dma,
  599. int sec4_sg_bytes)
  600. {
  601. if (dst != src) {
  602. dma_unmap_sg_chained(dev, src, src_nents ? : 1, DMA_TO_DEVICE,
  603. src_chained);
  604. dma_unmap_sg_chained(dev, dst, dst_nents ? : 1, DMA_FROM_DEVICE,
  605. dst_chained);
  606. } else {
  607. dma_unmap_sg_chained(dev, src, src_nents ? : 1,
  608. DMA_BIDIRECTIONAL, src_chained);
  609. }
  610. if (iv_dma)
  611. dma_unmap_single(dev, iv_dma, ivsize, DMA_TO_DEVICE);
  612. if (sec4_sg_bytes)
  613. dma_unmap_single(dev, sec4_sg_dma, sec4_sg_bytes,
  614. DMA_TO_DEVICE);
  615. }
  616. static void aead_unmap(struct device *dev,
  617. struct aead_edesc *edesc,
  618. struct aead_request *req)
  619. {
  620. struct crypto_aead *aead = crypto_aead_reqtfm(req);
  621. int ivsize = crypto_aead_ivsize(aead);
  622. dma_unmap_sg_chained(dev, req->assoc, edesc->assoc_nents,
  623. DMA_TO_DEVICE, edesc->assoc_chained);
  624. caam_unmap(dev, req->src, req->dst,
  625. edesc->src_nents, edesc->src_chained, edesc->dst_nents,
  626. edesc->dst_chained, edesc->iv_dma, ivsize,
  627. edesc->sec4_sg_dma, edesc->sec4_sg_bytes);
  628. }
  629. static void ablkcipher_unmap(struct device *dev,
  630. struct ablkcipher_edesc *edesc,
  631. struct ablkcipher_request *req)
  632. {
  633. struct crypto_ablkcipher *ablkcipher = crypto_ablkcipher_reqtfm(req);
  634. int ivsize = crypto_ablkcipher_ivsize(ablkcipher);
  635. caam_unmap(dev, req->src, req->dst,
  636. edesc->src_nents, edesc->src_chained, edesc->dst_nents,
  637. edesc->dst_chained, edesc->iv_dma, ivsize,
  638. edesc->sec4_sg_dma, edesc->sec4_sg_bytes);
  639. }
  640. static void aead_encrypt_done(struct device *jrdev, u32 *desc, u32 err,
  641. void *context)
  642. {
  643. struct aead_request *req = context;
  644. struct aead_edesc *edesc;
  645. #ifdef DEBUG
  646. struct crypto_aead *aead = crypto_aead_reqtfm(req);
  647. struct caam_ctx *ctx = crypto_aead_ctx(aead);
  648. int ivsize = crypto_aead_ivsize(aead);
  649. dev_err(jrdev, "%s %d: err 0x%x\n", __func__, __LINE__, err);
  650. #endif
  651. edesc = (struct aead_edesc *)((char *)desc -
  652. offsetof(struct aead_edesc, hw_desc));
  653. if (err) {
  654. char tmp[CAAM_ERROR_STR_MAX];
  655. dev_err(jrdev, "%08x: %s\n", err, caam_jr_strstatus(tmp, err));
  656. }
  657. aead_unmap(jrdev, edesc, req);
  658. #ifdef DEBUG
  659. print_hex_dump(KERN_ERR, "assoc @"__stringify(__LINE__)": ",
  660. DUMP_PREFIX_ADDRESS, 16, 4, sg_virt(req->assoc),
  661. req->assoclen , 1);
  662. print_hex_dump(KERN_ERR, "dstiv @"__stringify(__LINE__)": ",
  663. DUMP_PREFIX_ADDRESS, 16, 4, sg_virt(req->src) - ivsize,
  664. edesc->src_nents ? 100 : ivsize, 1);
  665. print_hex_dump(KERN_ERR, "dst @"__stringify(__LINE__)": ",
  666. DUMP_PREFIX_ADDRESS, 16, 4, sg_virt(req->src),
  667. edesc->src_nents ? 100 : req->cryptlen +
  668. ctx->authsize + 4, 1);
  669. #endif
  670. kfree(edesc);
  671. aead_request_complete(req, err);
  672. }
  673. static void aead_decrypt_done(struct device *jrdev, u32 *desc, u32 err,
  674. void *context)
  675. {
  676. struct aead_request *req = context;
  677. struct aead_edesc *edesc;
  678. #ifdef DEBUG
  679. struct crypto_aead *aead = crypto_aead_reqtfm(req);
  680. struct caam_ctx *ctx = crypto_aead_ctx(aead);
  681. int ivsize = crypto_aead_ivsize(aead);
  682. dev_err(jrdev, "%s %d: err 0x%x\n", __func__, __LINE__, err);
  683. #endif
  684. edesc = (struct aead_edesc *)((char *)desc -
  685. offsetof(struct aead_edesc, hw_desc));
  686. #ifdef DEBUG
  687. print_hex_dump(KERN_ERR, "dstiv @"__stringify(__LINE__)": ",
  688. DUMP_PREFIX_ADDRESS, 16, 4, req->iv,
  689. ivsize, 1);
  690. print_hex_dump(KERN_ERR, "dst @"__stringify(__LINE__)": ",
  691. DUMP_PREFIX_ADDRESS, 16, 4, sg_virt(req->dst),
  692. req->cryptlen - ctx->authsize, 1);
  693. #endif
  694. if (err) {
  695. char tmp[CAAM_ERROR_STR_MAX];
  696. dev_err(jrdev, "%08x: %s\n", err, caam_jr_strstatus(tmp, err));
  697. }
  698. aead_unmap(jrdev, edesc, req);
  699. /*
  700. * verify hw auth check passed else return -EBADMSG
  701. */
  702. if ((err & JRSTA_CCBERR_ERRID_MASK) == JRSTA_CCBERR_ERRID_ICVCHK)
  703. err = -EBADMSG;
  704. #ifdef DEBUG
  705. print_hex_dump(KERN_ERR, "iphdrout@"__stringify(__LINE__)": ",
  706. DUMP_PREFIX_ADDRESS, 16, 4,
  707. ((char *)sg_virt(req->assoc) - sizeof(struct iphdr)),
  708. sizeof(struct iphdr) + req->assoclen +
  709. ((req->cryptlen > 1500) ? 1500 : req->cryptlen) +
  710. ctx->authsize + 36, 1);
  711. if (!err && edesc->sec4_sg_bytes) {
  712. struct scatterlist *sg = sg_last(req->src, edesc->src_nents);
  713. print_hex_dump(KERN_ERR, "sglastout@"__stringify(__LINE__)": ",
  714. DUMP_PREFIX_ADDRESS, 16, 4, sg_virt(sg),
  715. sg->length + ctx->authsize + 16, 1);
  716. }
  717. #endif
  718. kfree(edesc);
  719. aead_request_complete(req, err);
  720. }
  721. static void ablkcipher_encrypt_done(struct device *jrdev, u32 *desc, u32 err,
  722. void *context)
  723. {
  724. struct ablkcipher_request *req = context;
  725. struct ablkcipher_edesc *edesc;
  726. #ifdef DEBUG
  727. struct crypto_ablkcipher *ablkcipher = crypto_ablkcipher_reqtfm(req);
  728. int ivsize = crypto_ablkcipher_ivsize(ablkcipher);
  729. dev_err(jrdev, "%s %d: err 0x%x\n", __func__, __LINE__, err);
  730. #endif
  731. edesc = (struct ablkcipher_edesc *)((char *)desc -
  732. offsetof(struct ablkcipher_edesc, hw_desc));
  733. if (err) {
  734. char tmp[CAAM_ERROR_STR_MAX];
  735. dev_err(jrdev, "%08x: %s\n", err, caam_jr_strstatus(tmp, err));
  736. }
  737. #ifdef DEBUG
  738. print_hex_dump(KERN_ERR, "dstiv @"__stringify(__LINE__)": ",
  739. DUMP_PREFIX_ADDRESS, 16, 4, req->info,
  740. edesc->src_nents > 1 ? 100 : ivsize, 1);
  741. print_hex_dump(KERN_ERR, "dst @"__stringify(__LINE__)": ",
  742. DUMP_PREFIX_ADDRESS, 16, 4, sg_virt(req->src),
  743. edesc->dst_nents > 1 ? 100 : req->nbytes, 1);
  744. #endif
  745. ablkcipher_unmap(jrdev, edesc, req);
  746. kfree(edesc);
  747. ablkcipher_request_complete(req, err);
  748. }
  749. static void ablkcipher_decrypt_done(struct device *jrdev, u32 *desc, u32 err,
  750. void *context)
  751. {
  752. struct ablkcipher_request *req = context;
  753. struct ablkcipher_edesc *edesc;
  754. #ifdef DEBUG
  755. struct crypto_ablkcipher *ablkcipher = crypto_ablkcipher_reqtfm(req);
  756. int ivsize = crypto_ablkcipher_ivsize(ablkcipher);
  757. dev_err(jrdev, "%s %d: err 0x%x\n", __func__, __LINE__, err);
  758. #endif
  759. edesc = (struct ablkcipher_edesc *)((char *)desc -
  760. offsetof(struct ablkcipher_edesc, hw_desc));
  761. if (err) {
  762. char tmp[CAAM_ERROR_STR_MAX];
  763. dev_err(jrdev, "%08x: %s\n", err, caam_jr_strstatus(tmp, err));
  764. }
  765. #ifdef DEBUG
  766. print_hex_dump(KERN_ERR, "dstiv @"__stringify(__LINE__)": ",
  767. DUMP_PREFIX_ADDRESS, 16, 4, req->info,
  768. ivsize, 1);
  769. print_hex_dump(KERN_ERR, "dst @"__stringify(__LINE__)": ",
  770. DUMP_PREFIX_ADDRESS, 16, 4, sg_virt(req->src),
  771. edesc->dst_nents > 1 ? 100 : req->nbytes, 1);
  772. #endif
  773. ablkcipher_unmap(jrdev, edesc, req);
  774. kfree(edesc);
  775. ablkcipher_request_complete(req, err);
  776. }
  777. /*
  778. * Fill in aead job descriptor
  779. */
  780. static void init_aead_job(u32 *sh_desc, dma_addr_t ptr,
  781. struct aead_edesc *edesc,
  782. struct aead_request *req,
  783. bool all_contig, bool encrypt)
  784. {
  785. struct crypto_aead *aead = crypto_aead_reqtfm(req);
  786. struct caam_ctx *ctx = crypto_aead_ctx(aead);
  787. int ivsize = crypto_aead_ivsize(aead);
  788. int authsize = ctx->authsize;
  789. u32 *desc = edesc->hw_desc;
  790. u32 out_options = 0, in_options;
  791. dma_addr_t dst_dma, src_dma;
  792. int len, sec4_sg_index = 0;
  793. #ifdef DEBUG
  794. debug("assoclen %d cryptlen %d authsize %d\n",
  795. req->assoclen, req->cryptlen, authsize);
  796. print_hex_dump(KERN_ERR, "assoc @"__stringify(__LINE__)": ",
  797. DUMP_PREFIX_ADDRESS, 16, 4, sg_virt(req->assoc),
  798. req->assoclen , 1);
  799. print_hex_dump(KERN_ERR, "presciv@"__stringify(__LINE__)": ",
  800. DUMP_PREFIX_ADDRESS, 16, 4, req->iv,
  801. edesc->src_nents ? 100 : ivsize, 1);
  802. print_hex_dump(KERN_ERR, "src @"__stringify(__LINE__)": ",
  803. DUMP_PREFIX_ADDRESS, 16, 4, sg_virt(req->src),
  804. edesc->src_nents ? 100 : req->cryptlen, 1);
  805. print_hex_dump(KERN_ERR, "shrdesc@"__stringify(__LINE__)": ",
  806. DUMP_PREFIX_ADDRESS, 16, 4, sh_desc,
  807. desc_bytes(sh_desc), 1);
  808. #endif
  809. len = desc_len(sh_desc);
  810. init_job_desc_shared(desc, ptr, len, HDR_SHARE_DEFER | HDR_REVERSE);
  811. if (all_contig) {
  812. src_dma = sg_dma_address(req->assoc);
  813. in_options = 0;
  814. } else {
  815. src_dma = edesc->sec4_sg_dma;
  816. sec4_sg_index += (edesc->assoc_nents ? : 1) + 1 +
  817. (edesc->src_nents ? : 1);
  818. in_options = LDST_SGF;
  819. }
  820. append_seq_in_ptr(desc, src_dma, req->assoclen + ivsize + req->cryptlen,
  821. in_options);
  822. if (likely(req->src == req->dst)) {
  823. if (all_contig) {
  824. dst_dma = sg_dma_address(req->src);
  825. } else {
  826. dst_dma = src_dma + sizeof(struct sec4_sg_entry) *
  827. ((edesc->assoc_nents ? : 1) + 1);
  828. out_options = LDST_SGF;
  829. }
  830. } else {
  831. if (!edesc->dst_nents) {
  832. dst_dma = sg_dma_address(req->dst);
  833. } else {
  834. dst_dma = edesc->sec4_sg_dma +
  835. sec4_sg_index *
  836. sizeof(struct sec4_sg_entry);
  837. out_options = LDST_SGF;
  838. }
  839. }
  840. if (encrypt)
  841. append_seq_out_ptr(desc, dst_dma, req->cryptlen + authsize,
  842. out_options);
  843. else
  844. append_seq_out_ptr(desc, dst_dma, req->cryptlen - authsize,
  845. out_options);
  846. }
  847. /*
  848. * Fill in aead givencrypt job descriptor
  849. */
  850. static void init_aead_giv_job(u32 *sh_desc, dma_addr_t ptr,
  851. struct aead_edesc *edesc,
  852. struct aead_request *req,
  853. int contig)
  854. {
  855. struct crypto_aead *aead = crypto_aead_reqtfm(req);
  856. struct caam_ctx *ctx = crypto_aead_ctx(aead);
  857. int ivsize = crypto_aead_ivsize(aead);
  858. int authsize = ctx->authsize;
  859. u32 *desc = edesc->hw_desc;
  860. u32 out_options = 0, in_options;
  861. dma_addr_t dst_dma, src_dma;
  862. int len, sec4_sg_index = 0;
  863. #ifdef DEBUG
  864. debug("assoclen %d cryptlen %d authsize %d\n",
  865. req->assoclen, req->cryptlen, authsize);
  866. print_hex_dump(KERN_ERR, "assoc @"__stringify(__LINE__)": ",
  867. DUMP_PREFIX_ADDRESS, 16, 4, sg_virt(req->assoc),
  868. req->assoclen , 1);
  869. print_hex_dump(KERN_ERR, "presciv@"__stringify(__LINE__)": ",
  870. DUMP_PREFIX_ADDRESS, 16, 4, req->iv, ivsize, 1);
  871. print_hex_dump(KERN_ERR, "src @"__stringify(__LINE__)": ",
  872. DUMP_PREFIX_ADDRESS, 16, 4, sg_virt(req->src),
  873. edesc->src_nents > 1 ? 100 : req->cryptlen, 1);
  874. print_hex_dump(KERN_ERR, "shrdesc@"__stringify(__LINE__)": ",
  875. DUMP_PREFIX_ADDRESS, 16, 4, sh_desc,
  876. desc_bytes(sh_desc), 1);
  877. #endif
  878. len = desc_len(sh_desc);
  879. init_job_desc_shared(desc, ptr, len, HDR_SHARE_DEFER | HDR_REVERSE);
  880. if (contig & GIV_SRC_CONTIG) {
  881. src_dma = sg_dma_address(req->assoc);
  882. in_options = 0;
  883. } else {
  884. src_dma = edesc->sec4_sg_dma;
  885. sec4_sg_index += edesc->assoc_nents + 1 + edesc->src_nents;
  886. in_options = LDST_SGF;
  887. }
  888. append_seq_in_ptr(desc, src_dma, req->assoclen + ivsize + req->cryptlen,
  889. in_options);
  890. if (contig & GIV_DST_CONTIG) {
  891. dst_dma = edesc->iv_dma;
  892. } else {
  893. if (likely(req->src == req->dst)) {
  894. dst_dma = src_dma + sizeof(struct sec4_sg_entry) *
  895. edesc->assoc_nents;
  896. out_options = LDST_SGF;
  897. } else {
  898. dst_dma = edesc->sec4_sg_dma +
  899. sec4_sg_index *
  900. sizeof(struct sec4_sg_entry);
  901. out_options = LDST_SGF;
  902. }
  903. }
  904. append_seq_out_ptr(desc, dst_dma, ivsize + req->cryptlen + authsize,
  905. out_options);
  906. }
  907. /*
  908. * Fill in ablkcipher job descriptor
  909. */
  910. static void init_ablkcipher_job(u32 *sh_desc, dma_addr_t ptr,
  911. struct ablkcipher_edesc *edesc,
  912. struct ablkcipher_request *req,
  913. bool iv_contig)
  914. {
  915. struct crypto_ablkcipher *ablkcipher = crypto_ablkcipher_reqtfm(req);
  916. int ivsize = crypto_ablkcipher_ivsize(ablkcipher);
  917. u32 *desc = edesc->hw_desc;
  918. u32 out_options = 0, in_options;
  919. dma_addr_t dst_dma, src_dma;
  920. int len, sec4_sg_index = 0;
  921. #ifdef DEBUG
  922. print_hex_dump(KERN_ERR, "presciv@"__stringify(__LINE__)": ",
  923. DUMP_PREFIX_ADDRESS, 16, 4, req->info,
  924. ivsize, 1);
  925. print_hex_dump(KERN_ERR, "src @"__stringify(__LINE__)": ",
  926. DUMP_PREFIX_ADDRESS, 16, 4, sg_virt(req->src),
  927. edesc->src_nents ? 100 : req->nbytes, 1);
  928. #endif
  929. len = desc_len(sh_desc);
  930. init_job_desc_shared(desc, ptr, len, HDR_SHARE_DEFER | HDR_REVERSE);
  931. if (iv_contig) {
  932. src_dma = edesc->iv_dma;
  933. in_options = 0;
  934. } else {
  935. src_dma = edesc->sec4_sg_dma;
  936. sec4_sg_index += (iv_contig ? 0 : 1) + edesc->src_nents;
  937. in_options = LDST_SGF;
  938. }
  939. append_seq_in_ptr(desc, src_dma, req->nbytes + ivsize, in_options);
  940. if (likely(req->src == req->dst)) {
  941. if (!edesc->src_nents && iv_contig) {
  942. dst_dma = sg_dma_address(req->src);
  943. } else {
  944. dst_dma = edesc->sec4_sg_dma +
  945. sizeof(struct sec4_sg_entry);
  946. out_options = LDST_SGF;
  947. }
  948. } else {
  949. if (!edesc->dst_nents) {
  950. dst_dma = sg_dma_address(req->dst);
  951. } else {
  952. dst_dma = edesc->sec4_sg_dma +
  953. sec4_sg_index * sizeof(struct sec4_sg_entry);
  954. out_options = LDST_SGF;
  955. }
  956. }
  957. append_seq_out_ptr(desc, dst_dma, req->nbytes, out_options);
  958. }
  959. /*
  960. * allocate and map the aead extended descriptor
  961. */
  962. static struct aead_edesc *aead_edesc_alloc(struct aead_request *req,
  963. int desc_bytes, bool *all_contig_ptr,
  964. bool encrypt)
  965. {
  966. struct crypto_aead *aead = crypto_aead_reqtfm(req);
  967. struct caam_ctx *ctx = crypto_aead_ctx(aead);
  968. struct device *jrdev = ctx->jrdev;
  969. gfp_t flags = (req->base.flags & (CRYPTO_TFM_REQ_MAY_BACKLOG |
  970. CRYPTO_TFM_REQ_MAY_SLEEP)) ? GFP_KERNEL : GFP_ATOMIC;
  971. int assoc_nents, src_nents, dst_nents = 0;
  972. struct aead_edesc *edesc;
  973. dma_addr_t iv_dma = 0;
  974. int sgc;
  975. bool all_contig = true;
  976. bool assoc_chained = false, src_chained = false, dst_chained = false;
  977. int ivsize = crypto_aead_ivsize(aead);
  978. int sec4_sg_index, sec4_sg_len = 0, sec4_sg_bytes;
  979. unsigned int authsize = ctx->authsize;
  980. assoc_nents = sg_count(req->assoc, req->assoclen, &assoc_chained);
  981. if (unlikely(req->dst != req->src)) {
  982. src_nents = sg_count(req->src, req->cryptlen, &src_chained);
  983. dst_nents = sg_count(req->dst,
  984. req->cryptlen +
  985. (encrypt ? authsize : (-authsize)),
  986. &dst_chained);
  987. } else {
  988. src_nents = sg_count(req->src,
  989. req->cryptlen +
  990. (encrypt ? authsize : 0),
  991. &src_chained);
  992. }
  993. sgc = dma_map_sg_chained(jrdev, req->assoc, assoc_nents ? : 1,
  994. DMA_TO_DEVICE, assoc_chained);
  995. if (likely(req->src == req->dst)) {
  996. sgc = dma_map_sg_chained(jrdev, req->src, src_nents ? : 1,
  997. DMA_BIDIRECTIONAL, src_chained);
  998. } else {
  999. sgc = dma_map_sg_chained(jrdev, req->src, src_nents ? : 1,
  1000. DMA_TO_DEVICE, src_chained);
  1001. sgc = dma_map_sg_chained(jrdev, req->dst, dst_nents ? : 1,
  1002. DMA_FROM_DEVICE, dst_chained);
  1003. }
  1004. /* Check if data are contiguous */
  1005. iv_dma = dma_map_single(jrdev, req->iv, ivsize, DMA_TO_DEVICE);
  1006. if (assoc_nents || sg_dma_address(req->assoc) + req->assoclen !=
  1007. iv_dma || src_nents || iv_dma + ivsize !=
  1008. sg_dma_address(req->src)) {
  1009. all_contig = false;
  1010. assoc_nents = assoc_nents ? : 1;
  1011. src_nents = src_nents ? : 1;
  1012. sec4_sg_len = assoc_nents + 1 + src_nents;
  1013. }
  1014. sec4_sg_len += dst_nents;
  1015. sec4_sg_bytes = sec4_sg_len * sizeof(struct sec4_sg_entry);
  1016. /* allocate space for base edesc and hw desc commands, link tables */
  1017. edesc = kmalloc(sizeof(struct aead_edesc) + desc_bytes +
  1018. sec4_sg_bytes, GFP_DMA | flags);
  1019. if (!edesc) {
  1020. dev_err(jrdev, "could not allocate extended descriptor\n");
  1021. return ERR_PTR(-ENOMEM);
  1022. }
  1023. edesc->assoc_nents = assoc_nents;
  1024. edesc->assoc_chained = assoc_chained;
  1025. edesc->src_nents = src_nents;
  1026. edesc->src_chained = src_chained;
  1027. edesc->dst_nents = dst_nents;
  1028. edesc->dst_chained = dst_chained;
  1029. edesc->iv_dma = iv_dma;
  1030. edesc->sec4_sg_bytes = sec4_sg_bytes;
  1031. edesc->sec4_sg = (void *)edesc + sizeof(struct aead_edesc) +
  1032. desc_bytes;
  1033. edesc->sec4_sg_dma = dma_map_single(jrdev, edesc->sec4_sg,
  1034. sec4_sg_bytes, DMA_TO_DEVICE);
  1035. *all_contig_ptr = all_contig;
  1036. sec4_sg_index = 0;
  1037. if (!all_contig) {
  1038. sg_to_sec4_sg(req->assoc,
  1039. (assoc_nents ? : 1),
  1040. edesc->sec4_sg +
  1041. sec4_sg_index, 0);
  1042. sec4_sg_index += assoc_nents ? : 1;
  1043. dma_to_sec4_sg_one(edesc->sec4_sg + sec4_sg_index,
  1044. iv_dma, ivsize, 0);
  1045. sec4_sg_index += 1;
  1046. sg_to_sec4_sg_last(req->src,
  1047. (src_nents ? : 1),
  1048. edesc->sec4_sg +
  1049. sec4_sg_index, 0);
  1050. sec4_sg_index += src_nents ? : 1;
  1051. }
  1052. if (dst_nents) {
  1053. sg_to_sec4_sg_last(req->dst, dst_nents,
  1054. edesc->sec4_sg + sec4_sg_index, 0);
  1055. }
  1056. return edesc;
  1057. }
  1058. static int aead_encrypt(struct aead_request *req)
  1059. {
  1060. struct aead_edesc *edesc;
  1061. struct crypto_aead *aead = crypto_aead_reqtfm(req);
  1062. struct caam_ctx *ctx = crypto_aead_ctx(aead);
  1063. struct device *jrdev = ctx->jrdev;
  1064. bool all_contig;
  1065. u32 *desc;
  1066. int ret = 0;
  1067. /* allocate extended descriptor */
  1068. edesc = aead_edesc_alloc(req, DESC_JOB_IO_LEN *
  1069. CAAM_CMD_SZ, &all_contig, true);
  1070. if (IS_ERR(edesc))
  1071. return PTR_ERR(edesc);
  1072. /* Create and submit job descriptor */
  1073. init_aead_job(ctx->sh_desc_enc, ctx->sh_desc_enc_dma, edesc, req,
  1074. all_contig, true);
  1075. #ifdef DEBUG
  1076. print_hex_dump(KERN_ERR, "aead jobdesc@"__stringify(__LINE__)": ",
  1077. DUMP_PREFIX_ADDRESS, 16, 4, edesc->hw_desc,
  1078. desc_bytes(edesc->hw_desc), 1);
  1079. #endif
  1080. desc = edesc->hw_desc;
  1081. ret = caam_jr_enqueue(jrdev, desc, aead_encrypt_done, req);
  1082. if (!ret) {
  1083. ret = -EINPROGRESS;
  1084. } else {
  1085. aead_unmap(jrdev, edesc, req);
  1086. kfree(edesc);
  1087. }
  1088. return ret;
  1089. }
  1090. static int aead_decrypt(struct aead_request *req)
  1091. {
  1092. struct aead_edesc *edesc;
  1093. struct crypto_aead *aead = crypto_aead_reqtfm(req);
  1094. struct caam_ctx *ctx = crypto_aead_ctx(aead);
  1095. struct device *jrdev = ctx->jrdev;
  1096. bool all_contig;
  1097. u32 *desc;
  1098. int ret = 0;
  1099. /* allocate extended descriptor */
  1100. edesc = aead_edesc_alloc(req, DESC_JOB_IO_LEN *
  1101. CAAM_CMD_SZ, &all_contig, false);
  1102. if (IS_ERR(edesc))
  1103. return PTR_ERR(edesc);
  1104. #ifdef DEBUG
  1105. print_hex_dump(KERN_ERR, "dec src@"__stringify(__LINE__)": ",
  1106. DUMP_PREFIX_ADDRESS, 16, 4, sg_virt(req->src),
  1107. req->cryptlen, 1);
  1108. #endif
  1109. /* Create and submit job descriptor*/
  1110. init_aead_job(ctx->sh_desc_dec,
  1111. ctx->sh_desc_dec_dma, edesc, req, all_contig, false);
  1112. #ifdef DEBUG
  1113. print_hex_dump(KERN_ERR, "aead jobdesc@"__stringify(__LINE__)": ",
  1114. DUMP_PREFIX_ADDRESS, 16, 4, edesc->hw_desc,
  1115. desc_bytes(edesc->hw_desc), 1);
  1116. #endif
  1117. desc = edesc->hw_desc;
  1118. ret = caam_jr_enqueue(jrdev, desc, aead_decrypt_done, req);
  1119. if (!ret) {
  1120. ret = -EINPROGRESS;
  1121. } else {
  1122. aead_unmap(jrdev, edesc, req);
  1123. kfree(edesc);
  1124. }
  1125. return ret;
  1126. }
  1127. /*
  1128. * allocate and map the aead extended descriptor for aead givencrypt
  1129. */
  1130. static struct aead_edesc *aead_giv_edesc_alloc(struct aead_givcrypt_request
  1131. *greq, int desc_bytes,
  1132. u32 *contig_ptr)
  1133. {
  1134. struct aead_request *req = &greq->areq;
  1135. struct crypto_aead *aead = crypto_aead_reqtfm(req);
  1136. struct caam_ctx *ctx = crypto_aead_ctx(aead);
  1137. struct device *jrdev = ctx->jrdev;
  1138. gfp_t flags = (req->base.flags & (CRYPTO_TFM_REQ_MAY_BACKLOG |
  1139. CRYPTO_TFM_REQ_MAY_SLEEP)) ? GFP_KERNEL : GFP_ATOMIC;
  1140. int assoc_nents, src_nents, dst_nents = 0;
  1141. struct aead_edesc *edesc;
  1142. dma_addr_t iv_dma = 0;
  1143. int sgc;
  1144. u32 contig = GIV_SRC_CONTIG | GIV_DST_CONTIG;
  1145. int ivsize = crypto_aead_ivsize(aead);
  1146. bool assoc_chained = false, src_chained = false, dst_chained = false;
  1147. int sec4_sg_index, sec4_sg_len = 0, sec4_sg_bytes;
  1148. assoc_nents = sg_count(req->assoc, req->assoclen, &assoc_chained);
  1149. src_nents = sg_count(req->src, req->cryptlen, &src_chained);
  1150. if (unlikely(req->dst != req->src))
  1151. dst_nents = sg_count(req->dst, req->cryptlen + ctx->authsize,
  1152. &dst_chained);
  1153. sgc = dma_map_sg_chained(jrdev, req->assoc, assoc_nents ? : 1,
  1154. DMA_TO_DEVICE, assoc_chained);
  1155. if (likely(req->src == req->dst)) {
  1156. sgc = dma_map_sg_chained(jrdev, req->src, src_nents ? : 1,
  1157. DMA_BIDIRECTIONAL, src_chained);
  1158. } else {
  1159. sgc = dma_map_sg_chained(jrdev, req->src, src_nents ? : 1,
  1160. DMA_TO_DEVICE, src_chained);
  1161. sgc = dma_map_sg_chained(jrdev, req->dst, dst_nents ? : 1,
  1162. DMA_FROM_DEVICE, dst_chained);
  1163. }
  1164. /* Check if data are contiguous */
  1165. iv_dma = dma_map_single(jrdev, greq->giv, ivsize, DMA_TO_DEVICE);
  1166. if (assoc_nents || sg_dma_address(req->assoc) + req->assoclen !=
  1167. iv_dma || src_nents || iv_dma + ivsize != sg_dma_address(req->src))
  1168. contig &= ~GIV_SRC_CONTIG;
  1169. if (dst_nents || iv_dma + ivsize != sg_dma_address(req->dst))
  1170. contig &= ~GIV_DST_CONTIG;
  1171. if (unlikely(req->src != req->dst)) {
  1172. dst_nents = dst_nents ? : 1;
  1173. sec4_sg_len += 1;
  1174. }
  1175. if (!(contig & GIV_SRC_CONTIG)) {
  1176. assoc_nents = assoc_nents ? : 1;
  1177. src_nents = src_nents ? : 1;
  1178. sec4_sg_len += assoc_nents + 1 + src_nents;
  1179. if (likely(req->src == req->dst))
  1180. contig &= ~GIV_DST_CONTIG;
  1181. }
  1182. sec4_sg_len += dst_nents;
  1183. sec4_sg_bytes = sec4_sg_len * sizeof(struct sec4_sg_entry);
  1184. /* allocate space for base edesc and hw desc commands, link tables */
  1185. edesc = kmalloc(sizeof(struct aead_edesc) + desc_bytes +
  1186. sec4_sg_bytes, GFP_DMA | flags);
  1187. if (!edesc) {
  1188. dev_err(jrdev, "could not allocate extended descriptor\n");
  1189. return ERR_PTR(-ENOMEM);
  1190. }
  1191. edesc->assoc_nents = assoc_nents;
  1192. edesc->assoc_chained = assoc_chained;
  1193. edesc->src_nents = src_nents;
  1194. edesc->src_chained = src_chained;
  1195. edesc->dst_nents = dst_nents;
  1196. edesc->dst_chained = dst_chained;
  1197. edesc->iv_dma = iv_dma;
  1198. edesc->sec4_sg_bytes = sec4_sg_bytes;
  1199. edesc->sec4_sg = (void *)edesc + sizeof(struct aead_edesc) +
  1200. desc_bytes;
  1201. edesc->sec4_sg_dma = dma_map_single(jrdev, edesc->sec4_sg,
  1202. sec4_sg_bytes, DMA_TO_DEVICE);
  1203. *contig_ptr = contig;
  1204. sec4_sg_index = 0;
  1205. if (!(contig & GIV_SRC_CONTIG)) {
  1206. sg_to_sec4_sg(req->assoc, assoc_nents,
  1207. edesc->sec4_sg +
  1208. sec4_sg_index, 0);
  1209. sec4_sg_index += assoc_nents;
  1210. dma_to_sec4_sg_one(edesc->sec4_sg + sec4_sg_index,
  1211. iv_dma, ivsize, 0);
  1212. sec4_sg_index += 1;
  1213. sg_to_sec4_sg_last(req->src, src_nents,
  1214. edesc->sec4_sg +
  1215. sec4_sg_index, 0);
  1216. sec4_sg_index += src_nents;
  1217. }
  1218. if (unlikely(req->src != req->dst && !(contig & GIV_DST_CONTIG))) {
  1219. dma_to_sec4_sg_one(edesc->sec4_sg + sec4_sg_index,
  1220. iv_dma, ivsize, 0);
  1221. sec4_sg_index += 1;
  1222. sg_to_sec4_sg_last(req->dst, dst_nents,
  1223. edesc->sec4_sg + sec4_sg_index, 0);
  1224. }
  1225. return edesc;
  1226. }
  1227. static int aead_givencrypt(struct aead_givcrypt_request *areq)
  1228. {
  1229. struct aead_request *req = &areq->areq;
  1230. struct aead_edesc *edesc;
  1231. struct crypto_aead *aead = crypto_aead_reqtfm(req);
  1232. struct caam_ctx *ctx = crypto_aead_ctx(aead);
  1233. struct device *jrdev = ctx->jrdev;
  1234. u32 contig;
  1235. u32 *desc;
  1236. int ret = 0;
  1237. /* allocate extended descriptor */
  1238. edesc = aead_giv_edesc_alloc(areq, DESC_JOB_IO_LEN *
  1239. CAAM_CMD_SZ, &contig);
  1240. if (IS_ERR(edesc))
  1241. return PTR_ERR(edesc);
  1242. #ifdef DEBUG
  1243. print_hex_dump(KERN_ERR, "giv src@"__stringify(__LINE__)": ",
  1244. DUMP_PREFIX_ADDRESS, 16, 4, sg_virt(req->src),
  1245. req->cryptlen, 1);
  1246. #endif
  1247. /* Create and submit job descriptor*/
  1248. init_aead_giv_job(ctx->sh_desc_givenc,
  1249. ctx->sh_desc_givenc_dma, edesc, req, contig);
  1250. #ifdef DEBUG
  1251. print_hex_dump(KERN_ERR, "aead jobdesc@"__stringify(__LINE__)": ",
  1252. DUMP_PREFIX_ADDRESS, 16, 4, edesc->hw_desc,
  1253. desc_bytes(edesc->hw_desc), 1);
  1254. #endif
  1255. desc = edesc->hw_desc;
  1256. ret = caam_jr_enqueue(jrdev, desc, aead_encrypt_done, req);
  1257. if (!ret) {
  1258. ret = -EINPROGRESS;
  1259. } else {
  1260. aead_unmap(jrdev, edesc, req);
  1261. kfree(edesc);
  1262. }
  1263. return ret;
  1264. }
  1265. /*
  1266. * allocate and map the ablkcipher extended descriptor for ablkcipher
  1267. */
  1268. static struct ablkcipher_edesc *ablkcipher_edesc_alloc(struct ablkcipher_request
  1269. *req, int desc_bytes,
  1270. bool *iv_contig_out)
  1271. {
  1272. struct crypto_ablkcipher *ablkcipher = crypto_ablkcipher_reqtfm(req);
  1273. struct caam_ctx *ctx = crypto_ablkcipher_ctx(ablkcipher);
  1274. struct device *jrdev = ctx->jrdev;
  1275. gfp_t flags = (req->base.flags & (CRYPTO_TFM_REQ_MAY_BACKLOG |
  1276. CRYPTO_TFM_REQ_MAY_SLEEP)) ?
  1277. GFP_KERNEL : GFP_ATOMIC;
  1278. int src_nents, dst_nents = 0, sec4_sg_bytes;
  1279. struct ablkcipher_edesc *edesc;
  1280. dma_addr_t iv_dma = 0;
  1281. bool iv_contig = false;
  1282. int sgc;
  1283. int ivsize = crypto_ablkcipher_ivsize(ablkcipher);
  1284. bool src_chained = false, dst_chained = false;
  1285. int sec4_sg_index;
  1286. src_nents = sg_count(req->src, req->nbytes, &src_chained);
  1287. if (req->dst != req->src)
  1288. dst_nents = sg_count(req->dst, req->nbytes, &dst_chained);
  1289. if (likely(req->src == req->dst)) {
  1290. sgc = dma_map_sg_chained(jrdev, req->src, src_nents ? : 1,
  1291. DMA_BIDIRECTIONAL, src_chained);
  1292. } else {
  1293. sgc = dma_map_sg_chained(jrdev, req->src, src_nents ? : 1,
  1294. DMA_TO_DEVICE, src_chained);
  1295. sgc = dma_map_sg_chained(jrdev, req->dst, dst_nents ? : 1,
  1296. DMA_FROM_DEVICE, dst_chained);
  1297. }
  1298. /*
  1299. * Check if iv can be contiguous with source and destination.
  1300. * If so, include it. If not, create scatterlist.
  1301. */
  1302. iv_dma = dma_map_single(jrdev, req->info, ivsize, DMA_TO_DEVICE);
  1303. if (!src_nents && iv_dma + ivsize == sg_dma_address(req->src))
  1304. iv_contig = true;
  1305. else
  1306. src_nents = src_nents ? : 1;
  1307. sec4_sg_bytes = ((iv_contig ? 0 : 1) + src_nents + dst_nents) *
  1308. sizeof(struct sec4_sg_entry);
  1309. /* allocate space for base edesc and hw desc commands, link tables */
  1310. edesc = kmalloc(sizeof(struct ablkcipher_edesc) + desc_bytes +
  1311. sec4_sg_bytes, GFP_DMA | flags);
  1312. if (!edesc) {
  1313. dev_err(jrdev, "could not allocate extended descriptor\n");
  1314. return ERR_PTR(-ENOMEM);
  1315. }
  1316. edesc->src_nents = src_nents;
  1317. edesc->src_chained = src_chained;
  1318. edesc->dst_nents = dst_nents;
  1319. edesc->dst_chained = dst_chained;
  1320. edesc->sec4_sg_bytes = sec4_sg_bytes;
  1321. edesc->sec4_sg = (void *)edesc + sizeof(struct ablkcipher_edesc) +
  1322. desc_bytes;
  1323. sec4_sg_index = 0;
  1324. if (!iv_contig) {
  1325. dma_to_sec4_sg_one(edesc->sec4_sg, iv_dma, ivsize, 0);
  1326. sg_to_sec4_sg_last(req->src, src_nents,
  1327. edesc->sec4_sg + 1, 0);
  1328. sec4_sg_index += 1 + src_nents;
  1329. }
  1330. if (dst_nents) {
  1331. sg_to_sec4_sg_last(req->dst, dst_nents,
  1332. edesc->sec4_sg + sec4_sg_index, 0);
  1333. }
  1334. edesc->sec4_sg_dma = dma_map_single(jrdev, edesc->sec4_sg,
  1335. sec4_sg_bytes, DMA_TO_DEVICE);
  1336. edesc->iv_dma = iv_dma;
  1337. #ifdef DEBUG
  1338. print_hex_dump(KERN_ERR, "ablkcipher sec4_sg@"__stringify(__LINE__)": ",
  1339. DUMP_PREFIX_ADDRESS, 16, 4, edesc->sec4_sg,
  1340. sec4_sg_bytes, 1);
  1341. #endif
  1342. *iv_contig_out = iv_contig;
  1343. return edesc;
  1344. }
  1345. static int ablkcipher_encrypt(struct ablkcipher_request *req)
  1346. {
  1347. struct ablkcipher_edesc *edesc;
  1348. struct crypto_ablkcipher *ablkcipher = crypto_ablkcipher_reqtfm(req);
  1349. struct caam_ctx *ctx = crypto_ablkcipher_ctx(ablkcipher);
  1350. struct device *jrdev = ctx->jrdev;
  1351. bool iv_contig;
  1352. u32 *desc;
  1353. int ret = 0;
  1354. /* allocate extended descriptor */
  1355. edesc = ablkcipher_edesc_alloc(req, DESC_JOB_IO_LEN *
  1356. CAAM_CMD_SZ, &iv_contig);
  1357. if (IS_ERR(edesc))
  1358. return PTR_ERR(edesc);
  1359. /* Create and submit job descriptor*/
  1360. init_ablkcipher_job(ctx->sh_desc_enc,
  1361. ctx->sh_desc_enc_dma, edesc, req, iv_contig);
  1362. #ifdef DEBUG
  1363. print_hex_dump(KERN_ERR, "ablkcipher jobdesc@"__stringify(__LINE__)": ",
  1364. DUMP_PREFIX_ADDRESS, 16, 4, edesc->hw_desc,
  1365. desc_bytes(edesc->hw_desc), 1);
  1366. #endif
  1367. desc = edesc->hw_desc;
  1368. ret = caam_jr_enqueue(jrdev, desc, ablkcipher_encrypt_done, req);
  1369. if (!ret) {
  1370. ret = -EINPROGRESS;
  1371. } else {
  1372. ablkcipher_unmap(jrdev, edesc, req);
  1373. kfree(edesc);
  1374. }
  1375. return ret;
  1376. }
  1377. static int ablkcipher_decrypt(struct ablkcipher_request *req)
  1378. {
  1379. struct ablkcipher_edesc *edesc;
  1380. struct crypto_ablkcipher *ablkcipher = crypto_ablkcipher_reqtfm(req);
  1381. struct caam_ctx *ctx = crypto_ablkcipher_ctx(ablkcipher);
  1382. struct device *jrdev = ctx->jrdev;
  1383. bool iv_contig;
  1384. u32 *desc;
  1385. int ret = 0;
  1386. /* allocate extended descriptor */
  1387. edesc = ablkcipher_edesc_alloc(req, DESC_JOB_IO_LEN *
  1388. CAAM_CMD_SZ, &iv_contig);
  1389. if (IS_ERR(edesc))
  1390. return PTR_ERR(edesc);
  1391. /* Create and submit job descriptor*/
  1392. init_ablkcipher_job(ctx->sh_desc_dec,
  1393. ctx->sh_desc_dec_dma, edesc, req, iv_contig);
  1394. desc = edesc->hw_desc;
  1395. #ifdef DEBUG
  1396. print_hex_dump(KERN_ERR, "ablkcipher jobdesc@"__stringify(__LINE__)": ",
  1397. DUMP_PREFIX_ADDRESS, 16, 4, edesc->hw_desc,
  1398. desc_bytes(edesc->hw_desc), 1);
  1399. #endif
  1400. ret = caam_jr_enqueue(jrdev, desc, ablkcipher_decrypt_done, req);
  1401. if (!ret) {
  1402. ret = -EINPROGRESS;
  1403. } else {
  1404. ablkcipher_unmap(jrdev, edesc, req);
  1405. kfree(edesc);
  1406. }
  1407. return ret;
  1408. }
  1409. #define template_aead template_u.aead
  1410. #define template_ablkcipher template_u.ablkcipher
  1411. struct caam_alg_template {
  1412. char name[CRYPTO_MAX_ALG_NAME];
  1413. char driver_name[CRYPTO_MAX_ALG_NAME];
  1414. unsigned int blocksize;
  1415. u32 type;
  1416. union {
  1417. struct ablkcipher_alg ablkcipher;
  1418. struct aead_alg aead;
  1419. struct blkcipher_alg blkcipher;
  1420. struct cipher_alg cipher;
  1421. struct compress_alg compress;
  1422. struct rng_alg rng;
  1423. } template_u;
  1424. u32 class1_alg_type;
  1425. u32 class2_alg_type;
  1426. u32 alg_op;
  1427. };
  1428. static struct caam_alg_template driver_algs[] = {
  1429. /* single-pass ipsec_esp descriptor */
  1430. {
  1431. .name = "authenc(hmac(md5),cbc(aes))",
  1432. .driver_name = "authenc-hmac-md5-cbc-aes-caam",
  1433. .blocksize = AES_BLOCK_SIZE,
  1434. .type = CRYPTO_ALG_TYPE_AEAD,
  1435. .template_aead = {
  1436. .setkey = aead_setkey,
  1437. .setauthsize = aead_setauthsize,
  1438. .encrypt = aead_encrypt,
  1439. .decrypt = aead_decrypt,
  1440. .givencrypt = aead_givencrypt,
  1441. .geniv = "<built-in>",
  1442. .ivsize = AES_BLOCK_SIZE,
  1443. .maxauthsize = MD5_DIGEST_SIZE,
  1444. },
  1445. .class1_alg_type = OP_ALG_ALGSEL_AES | OP_ALG_AAI_CBC,
  1446. .class2_alg_type = OP_ALG_ALGSEL_MD5 | OP_ALG_AAI_HMAC_PRECOMP,
  1447. .alg_op = OP_ALG_ALGSEL_MD5 | OP_ALG_AAI_HMAC,
  1448. },
  1449. {
  1450. .name = "authenc(hmac(sha1),cbc(aes))",
  1451. .driver_name = "authenc-hmac-sha1-cbc-aes-caam",
  1452. .blocksize = AES_BLOCK_SIZE,
  1453. .type = CRYPTO_ALG_TYPE_AEAD,
  1454. .template_aead = {
  1455. .setkey = aead_setkey,
  1456. .setauthsize = aead_setauthsize,
  1457. .encrypt = aead_encrypt,
  1458. .decrypt = aead_decrypt,
  1459. .givencrypt = aead_givencrypt,
  1460. .geniv = "<built-in>",
  1461. .ivsize = AES_BLOCK_SIZE,
  1462. .maxauthsize = SHA1_DIGEST_SIZE,
  1463. },
  1464. .class1_alg_type = OP_ALG_ALGSEL_AES | OP_ALG_AAI_CBC,
  1465. .class2_alg_type = OP_ALG_ALGSEL_SHA1 | OP_ALG_AAI_HMAC_PRECOMP,
  1466. .alg_op = OP_ALG_ALGSEL_SHA1 | OP_ALG_AAI_HMAC,
  1467. },
  1468. {
  1469. .name = "authenc(hmac(sha224),cbc(aes))",
  1470. .driver_name = "authenc-hmac-sha224-cbc-aes-caam",
  1471. .blocksize = AES_BLOCK_SIZE,
  1472. .type = CRYPTO_ALG_TYPE_AEAD,
  1473. .template_aead = {
  1474. .setkey = aead_setkey,
  1475. .setauthsize = aead_setauthsize,
  1476. .encrypt = aead_encrypt,
  1477. .decrypt = aead_decrypt,
  1478. .givencrypt = aead_givencrypt,
  1479. .geniv = "<built-in>",
  1480. .ivsize = AES_BLOCK_SIZE,
  1481. .maxauthsize = SHA224_DIGEST_SIZE,
  1482. },
  1483. .class1_alg_type = OP_ALG_ALGSEL_AES | OP_ALG_AAI_CBC,
  1484. .class2_alg_type = OP_ALG_ALGSEL_SHA224 |
  1485. OP_ALG_AAI_HMAC_PRECOMP,
  1486. .alg_op = OP_ALG_ALGSEL_SHA224 | OP_ALG_AAI_HMAC,
  1487. },
  1488. {
  1489. .name = "authenc(hmac(sha256),cbc(aes))",
  1490. .driver_name = "authenc-hmac-sha256-cbc-aes-caam",
  1491. .blocksize = AES_BLOCK_SIZE,
  1492. .type = CRYPTO_ALG_TYPE_AEAD,
  1493. .template_aead = {
  1494. .setkey = aead_setkey,
  1495. .setauthsize = aead_setauthsize,
  1496. .encrypt = aead_encrypt,
  1497. .decrypt = aead_decrypt,
  1498. .givencrypt = aead_givencrypt,
  1499. .geniv = "<built-in>",
  1500. .ivsize = AES_BLOCK_SIZE,
  1501. .maxauthsize = SHA256_DIGEST_SIZE,
  1502. },
  1503. .class1_alg_type = OP_ALG_ALGSEL_AES | OP_ALG_AAI_CBC,
  1504. .class2_alg_type = OP_ALG_ALGSEL_SHA256 |
  1505. OP_ALG_AAI_HMAC_PRECOMP,
  1506. .alg_op = OP_ALG_ALGSEL_SHA256 | OP_ALG_AAI_HMAC,
  1507. },
  1508. {
  1509. .name = "authenc(hmac(sha384),cbc(aes))",
  1510. .driver_name = "authenc-hmac-sha384-cbc-aes-caam",
  1511. .blocksize = AES_BLOCK_SIZE,
  1512. .type = CRYPTO_ALG_TYPE_AEAD,
  1513. .template_aead = {
  1514. .setkey = aead_setkey,
  1515. .setauthsize = aead_setauthsize,
  1516. .encrypt = aead_encrypt,
  1517. .decrypt = aead_decrypt,
  1518. .givencrypt = aead_givencrypt,
  1519. .geniv = "<built-in>",
  1520. .ivsize = AES_BLOCK_SIZE,
  1521. .maxauthsize = SHA384_DIGEST_SIZE,
  1522. },
  1523. .class1_alg_type = OP_ALG_ALGSEL_AES | OP_ALG_AAI_CBC,
  1524. .class2_alg_type = OP_ALG_ALGSEL_SHA384 |
  1525. OP_ALG_AAI_HMAC_PRECOMP,
  1526. .alg_op = OP_ALG_ALGSEL_SHA384 | OP_ALG_AAI_HMAC,
  1527. },
  1528. {
  1529. .name = "authenc(hmac(sha512),cbc(aes))",
  1530. .driver_name = "authenc-hmac-sha512-cbc-aes-caam",
  1531. .blocksize = AES_BLOCK_SIZE,
  1532. .type = CRYPTO_ALG_TYPE_AEAD,
  1533. .template_aead = {
  1534. .setkey = aead_setkey,
  1535. .setauthsize = aead_setauthsize,
  1536. .encrypt = aead_encrypt,
  1537. .decrypt = aead_decrypt,
  1538. .givencrypt = aead_givencrypt,
  1539. .geniv = "<built-in>",
  1540. .ivsize = AES_BLOCK_SIZE,
  1541. .maxauthsize = SHA512_DIGEST_SIZE,
  1542. },
  1543. .class1_alg_type = OP_ALG_ALGSEL_AES | OP_ALG_AAI_CBC,
  1544. .class2_alg_type = OP_ALG_ALGSEL_SHA512 |
  1545. OP_ALG_AAI_HMAC_PRECOMP,
  1546. .alg_op = OP_ALG_ALGSEL_SHA512 | OP_ALG_AAI_HMAC,
  1547. },
  1548. {
  1549. .name = "authenc(hmac(md5),cbc(des3_ede))",
  1550. .driver_name = "authenc-hmac-md5-cbc-des3_ede-caam",
  1551. .blocksize = DES3_EDE_BLOCK_SIZE,
  1552. .type = CRYPTO_ALG_TYPE_AEAD,
  1553. .template_aead = {
  1554. .setkey = aead_setkey,
  1555. .setauthsize = aead_setauthsize,
  1556. .encrypt = aead_encrypt,
  1557. .decrypt = aead_decrypt,
  1558. .givencrypt = aead_givencrypt,
  1559. .geniv = "<built-in>",
  1560. .ivsize = DES3_EDE_BLOCK_SIZE,
  1561. .maxauthsize = MD5_DIGEST_SIZE,
  1562. },
  1563. .class1_alg_type = OP_ALG_ALGSEL_3DES | OP_ALG_AAI_CBC,
  1564. .class2_alg_type = OP_ALG_ALGSEL_MD5 | OP_ALG_AAI_HMAC_PRECOMP,
  1565. .alg_op = OP_ALG_ALGSEL_MD5 | OP_ALG_AAI_HMAC,
  1566. },
  1567. {
  1568. .name = "authenc(hmac(sha1),cbc(des3_ede))",
  1569. .driver_name = "authenc-hmac-sha1-cbc-des3_ede-caam",
  1570. .blocksize = DES3_EDE_BLOCK_SIZE,
  1571. .type = CRYPTO_ALG_TYPE_AEAD,
  1572. .template_aead = {
  1573. .setkey = aead_setkey,
  1574. .setauthsize = aead_setauthsize,
  1575. .encrypt = aead_encrypt,
  1576. .decrypt = aead_decrypt,
  1577. .givencrypt = aead_givencrypt,
  1578. .geniv = "<built-in>",
  1579. .ivsize = DES3_EDE_BLOCK_SIZE,
  1580. .maxauthsize = SHA1_DIGEST_SIZE,
  1581. },
  1582. .class1_alg_type = OP_ALG_ALGSEL_3DES | OP_ALG_AAI_CBC,
  1583. .class2_alg_type = OP_ALG_ALGSEL_SHA1 | OP_ALG_AAI_HMAC_PRECOMP,
  1584. .alg_op = OP_ALG_ALGSEL_SHA1 | OP_ALG_AAI_HMAC,
  1585. },
  1586. {
  1587. .name = "authenc(hmac(sha224),cbc(des3_ede))",
  1588. .driver_name = "authenc-hmac-sha224-cbc-des3_ede-caam",
  1589. .blocksize = DES3_EDE_BLOCK_SIZE,
  1590. .type = CRYPTO_ALG_TYPE_AEAD,
  1591. .template_aead = {
  1592. .setkey = aead_setkey,
  1593. .setauthsize = aead_setauthsize,
  1594. .encrypt = aead_encrypt,
  1595. .decrypt = aead_decrypt,
  1596. .givencrypt = aead_givencrypt,
  1597. .geniv = "<built-in>",
  1598. .ivsize = DES3_EDE_BLOCK_SIZE,
  1599. .maxauthsize = SHA224_DIGEST_SIZE,
  1600. },
  1601. .class1_alg_type = OP_ALG_ALGSEL_3DES | OP_ALG_AAI_CBC,
  1602. .class2_alg_type = OP_ALG_ALGSEL_SHA224 |
  1603. OP_ALG_AAI_HMAC_PRECOMP,
  1604. .alg_op = OP_ALG_ALGSEL_SHA224 | OP_ALG_AAI_HMAC,
  1605. },
  1606. {
  1607. .name = "authenc(hmac(sha256),cbc(des3_ede))",
  1608. .driver_name = "authenc-hmac-sha256-cbc-des3_ede-caam",
  1609. .blocksize = DES3_EDE_BLOCK_SIZE,
  1610. .type = CRYPTO_ALG_TYPE_AEAD,
  1611. .template_aead = {
  1612. .setkey = aead_setkey,
  1613. .setauthsize = aead_setauthsize,
  1614. .encrypt = aead_encrypt,
  1615. .decrypt = aead_decrypt,
  1616. .givencrypt = aead_givencrypt,
  1617. .geniv = "<built-in>",
  1618. .ivsize = DES3_EDE_BLOCK_SIZE,
  1619. .maxauthsize = SHA256_DIGEST_SIZE,
  1620. },
  1621. .class1_alg_type = OP_ALG_ALGSEL_3DES | OP_ALG_AAI_CBC,
  1622. .class2_alg_type = OP_ALG_ALGSEL_SHA256 |
  1623. OP_ALG_AAI_HMAC_PRECOMP,
  1624. .alg_op = OP_ALG_ALGSEL_SHA256 | OP_ALG_AAI_HMAC,
  1625. },
  1626. {
  1627. .name = "authenc(hmac(sha384),cbc(des3_ede))",
  1628. .driver_name = "authenc-hmac-sha384-cbc-des3_ede-caam",
  1629. .blocksize = DES3_EDE_BLOCK_SIZE,
  1630. .type = CRYPTO_ALG_TYPE_AEAD,
  1631. .template_aead = {
  1632. .setkey = aead_setkey,
  1633. .setauthsize = aead_setauthsize,
  1634. .encrypt = aead_encrypt,
  1635. .decrypt = aead_decrypt,
  1636. .givencrypt = aead_givencrypt,
  1637. .geniv = "<built-in>",
  1638. .ivsize = DES3_EDE_BLOCK_SIZE,
  1639. .maxauthsize = SHA384_DIGEST_SIZE,
  1640. },
  1641. .class1_alg_type = OP_ALG_ALGSEL_3DES | OP_ALG_AAI_CBC,
  1642. .class2_alg_type = OP_ALG_ALGSEL_SHA384 |
  1643. OP_ALG_AAI_HMAC_PRECOMP,
  1644. .alg_op = OP_ALG_ALGSEL_SHA384 | OP_ALG_AAI_HMAC,
  1645. },
  1646. {
  1647. .name = "authenc(hmac(sha512),cbc(des3_ede))",
  1648. .driver_name = "authenc-hmac-sha512-cbc-des3_ede-caam",
  1649. .blocksize = DES3_EDE_BLOCK_SIZE,
  1650. .type = CRYPTO_ALG_TYPE_AEAD,
  1651. .template_aead = {
  1652. .setkey = aead_setkey,
  1653. .setauthsize = aead_setauthsize,
  1654. .encrypt = aead_encrypt,
  1655. .decrypt = aead_decrypt,
  1656. .givencrypt = aead_givencrypt,
  1657. .geniv = "<built-in>",
  1658. .ivsize = DES3_EDE_BLOCK_SIZE,
  1659. .maxauthsize = SHA512_DIGEST_SIZE,
  1660. },
  1661. .class1_alg_type = OP_ALG_ALGSEL_3DES | OP_ALG_AAI_CBC,
  1662. .class2_alg_type = OP_ALG_ALGSEL_SHA512 |
  1663. OP_ALG_AAI_HMAC_PRECOMP,
  1664. .alg_op = OP_ALG_ALGSEL_SHA512 | OP_ALG_AAI_HMAC,
  1665. },
  1666. {
  1667. .name = "authenc(hmac(md5),cbc(des))",
  1668. .driver_name = "authenc-hmac-md5-cbc-des-caam",
  1669. .blocksize = DES_BLOCK_SIZE,
  1670. .type = CRYPTO_ALG_TYPE_AEAD,
  1671. .template_aead = {
  1672. .setkey = aead_setkey,
  1673. .setauthsize = aead_setauthsize,
  1674. .encrypt = aead_encrypt,
  1675. .decrypt = aead_decrypt,
  1676. .givencrypt = aead_givencrypt,
  1677. .geniv = "<built-in>",
  1678. .ivsize = DES_BLOCK_SIZE,
  1679. .maxauthsize = MD5_DIGEST_SIZE,
  1680. },
  1681. .class1_alg_type = OP_ALG_ALGSEL_DES | OP_ALG_AAI_CBC,
  1682. .class2_alg_type = OP_ALG_ALGSEL_MD5 | OP_ALG_AAI_HMAC_PRECOMP,
  1683. .alg_op = OP_ALG_ALGSEL_MD5 | OP_ALG_AAI_HMAC,
  1684. },
  1685. {
  1686. .name = "authenc(hmac(sha1),cbc(des))",
  1687. .driver_name = "authenc-hmac-sha1-cbc-des-caam",
  1688. .blocksize = DES_BLOCK_SIZE,
  1689. .type = CRYPTO_ALG_TYPE_AEAD,
  1690. .template_aead = {
  1691. .setkey = aead_setkey,
  1692. .setauthsize = aead_setauthsize,
  1693. .encrypt = aead_encrypt,
  1694. .decrypt = aead_decrypt,
  1695. .givencrypt = aead_givencrypt,
  1696. .geniv = "<built-in>",
  1697. .ivsize = DES_BLOCK_SIZE,
  1698. .maxauthsize = SHA1_DIGEST_SIZE,
  1699. },
  1700. .class1_alg_type = OP_ALG_ALGSEL_DES | OP_ALG_AAI_CBC,
  1701. .class2_alg_type = OP_ALG_ALGSEL_SHA1 | OP_ALG_AAI_HMAC_PRECOMP,
  1702. .alg_op = OP_ALG_ALGSEL_SHA1 | OP_ALG_AAI_HMAC,
  1703. },
  1704. {
  1705. .name = "authenc(hmac(sha224),cbc(des))",
  1706. .driver_name = "authenc-hmac-sha224-cbc-des-caam",
  1707. .blocksize = DES_BLOCK_SIZE,
  1708. .type = CRYPTO_ALG_TYPE_AEAD,
  1709. .template_aead = {
  1710. .setkey = aead_setkey,
  1711. .setauthsize = aead_setauthsize,
  1712. .encrypt = aead_encrypt,
  1713. .decrypt = aead_decrypt,
  1714. .givencrypt = aead_givencrypt,
  1715. .geniv = "<built-in>",
  1716. .ivsize = DES_BLOCK_SIZE,
  1717. .maxauthsize = SHA224_DIGEST_SIZE,
  1718. },
  1719. .class1_alg_type = OP_ALG_ALGSEL_DES | OP_ALG_AAI_CBC,
  1720. .class2_alg_type = OP_ALG_ALGSEL_SHA224 |
  1721. OP_ALG_AAI_HMAC_PRECOMP,
  1722. .alg_op = OP_ALG_ALGSEL_SHA224 | OP_ALG_AAI_HMAC,
  1723. },
  1724. {
  1725. .name = "authenc(hmac(sha256),cbc(des))",
  1726. .driver_name = "authenc-hmac-sha256-cbc-des-caam",
  1727. .blocksize = DES_BLOCK_SIZE,
  1728. .type = CRYPTO_ALG_TYPE_AEAD,
  1729. .template_aead = {
  1730. .setkey = aead_setkey,
  1731. .setauthsize = aead_setauthsize,
  1732. .encrypt = aead_encrypt,
  1733. .decrypt = aead_decrypt,
  1734. .givencrypt = aead_givencrypt,
  1735. .geniv = "<built-in>",
  1736. .ivsize = DES_BLOCK_SIZE,
  1737. .maxauthsize = SHA256_DIGEST_SIZE,
  1738. },
  1739. .class1_alg_type = OP_ALG_ALGSEL_DES | OP_ALG_AAI_CBC,
  1740. .class2_alg_type = OP_ALG_ALGSEL_SHA256 |
  1741. OP_ALG_AAI_HMAC_PRECOMP,
  1742. .alg_op = OP_ALG_ALGSEL_SHA256 | OP_ALG_AAI_HMAC,
  1743. },
  1744. {
  1745. .name = "authenc(hmac(sha384),cbc(des))",
  1746. .driver_name = "authenc-hmac-sha384-cbc-des-caam",
  1747. .blocksize = DES_BLOCK_SIZE,
  1748. .type = CRYPTO_ALG_TYPE_AEAD,
  1749. .template_aead = {
  1750. .setkey = aead_setkey,
  1751. .setauthsize = aead_setauthsize,
  1752. .encrypt = aead_encrypt,
  1753. .decrypt = aead_decrypt,
  1754. .givencrypt = aead_givencrypt,
  1755. .geniv = "<built-in>",
  1756. .ivsize = DES_BLOCK_SIZE,
  1757. .maxauthsize = SHA384_DIGEST_SIZE,
  1758. },
  1759. .class1_alg_type = OP_ALG_ALGSEL_DES | OP_ALG_AAI_CBC,
  1760. .class2_alg_type = OP_ALG_ALGSEL_SHA384 |
  1761. OP_ALG_AAI_HMAC_PRECOMP,
  1762. .alg_op = OP_ALG_ALGSEL_SHA384 | OP_ALG_AAI_HMAC,
  1763. },
  1764. {
  1765. .name = "authenc(hmac(sha512),cbc(des))",
  1766. .driver_name = "authenc-hmac-sha512-cbc-des-caam",
  1767. .blocksize = DES_BLOCK_SIZE,
  1768. .type = CRYPTO_ALG_TYPE_AEAD,
  1769. .template_aead = {
  1770. .setkey = aead_setkey,
  1771. .setauthsize = aead_setauthsize,
  1772. .encrypt = aead_encrypt,
  1773. .decrypt = aead_decrypt,
  1774. .givencrypt = aead_givencrypt,
  1775. .geniv = "<built-in>",
  1776. .ivsize = DES_BLOCK_SIZE,
  1777. .maxauthsize = SHA512_DIGEST_SIZE,
  1778. },
  1779. .class1_alg_type = OP_ALG_ALGSEL_DES | OP_ALG_AAI_CBC,
  1780. .class2_alg_type = OP_ALG_ALGSEL_SHA512 |
  1781. OP_ALG_AAI_HMAC_PRECOMP,
  1782. .alg_op = OP_ALG_ALGSEL_SHA512 | OP_ALG_AAI_HMAC,
  1783. },
  1784. /* ablkcipher descriptor */
  1785. {
  1786. .name = "cbc(aes)",
  1787. .driver_name = "cbc-aes-caam",
  1788. .blocksize = AES_BLOCK_SIZE,
  1789. .type = CRYPTO_ALG_TYPE_ABLKCIPHER,
  1790. .template_ablkcipher = {
  1791. .setkey = ablkcipher_setkey,
  1792. .encrypt = ablkcipher_encrypt,
  1793. .decrypt = ablkcipher_decrypt,
  1794. .geniv = "eseqiv",
  1795. .min_keysize = AES_MIN_KEY_SIZE,
  1796. .max_keysize = AES_MAX_KEY_SIZE,
  1797. .ivsize = AES_BLOCK_SIZE,
  1798. },
  1799. .class1_alg_type = OP_ALG_ALGSEL_AES | OP_ALG_AAI_CBC,
  1800. },
  1801. {
  1802. .name = "cbc(des3_ede)",
  1803. .driver_name = "cbc-3des-caam",
  1804. .blocksize = DES3_EDE_BLOCK_SIZE,
  1805. .type = CRYPTO_ALG_TYPE_ABLKCIPHER,
  1806. .template_ablkcipher = {
  1807. .setkey = ablkcipher_setkey,
  1808. .encrypt = ablkcipher_encrypt,
  1809. .decrypt = ablkcipher_decrypt,
  1810. .geniv = "eseqiv",
  1811. .min_keysize = DES3_EDE_KEY_SIZE,
  1812. .max_keysize = DES3_EDE_KEY_SIZE,
  1813. .ivsize = DES3_EDE_BLOCK_SIZE,
  1814. },
  1815. .class1_alg_type = OP_ALG_ALGSEL_3DES | OP_ALG_AAI_CBC,
  1816. },
  1817. {
  1818. .name = "cbc(des)",
  1819. .driver_name = "cbc-des-caam",
  1820. .blocksize = DES_BLOCK_SIZE,
  1821. .type = CRYPTO_ALG_TYPE_ABLKCIPHER,
  1822. .template_ablkcipher = {
  1823. .setkey = ablkcipher_setkey,
  1824. .encrypt = ablkcipher_encrypt,
  1825. .decrypt = ablkcipher_decrypt,
  1826. .geniv = "eseqiv",
  1827. .min_keysize = DES_KEY_SIZE,
  1828. .max_keysize = DES_KEY_SIZE,
  1829. .ivsize = DES_BLOCK_SIZE,
  1830. },
  1831. .class1_alg_type = OP_ALG_ALGSEL_DES | OP_ALG_AAI_CBC,
  1832. }
  1833. };
  1834. struct caam_crypto_alg {
  1835. struct list_head entry;
  1836. int class1_alg_type;
  1837. int class2_alg_type;
  1838. int alg_op;
  1839. struct crypto_alg crypto_alg;
  1840. };
  1841. static int caam_cra_init(struct crypto_tfm *tfm)
  1842. {
  1843. struct crypto_alg *alg = tfm->__crt_alg;
  1844. struct caam_crypto_alg *caam_alg =
  1845. container_of(alg, struct caam_crypto_alg, crypto_alg);
  1846. struct caam_ctx *ctx = crypto_tfm_ctx(tfm);
  1847. ctx->jrdev = caam_jr_alloc();
  1848. if (IS_ERR(ctx->jrdev)) {
  1849. pr_err("Job Ring Device allocation for transform failed\n");
  1850. return PTR_ERR(ctx->jrdev);
  1851. }
  1852. /* copy descriptor header template value */
  1853. ctx->class1_alg_type = OP_TYPE_CLASS1_ALG | caam_alg->class1_alg_type;
  1854. ctx->class2_alg_type = OP_TYPE_CLASS2_ALG | caam_alg->class2_alg_type;
  1855. ctx->alg_op = OP_TYPE_CLASS2_ALG | caam_alg->alg_op;
  1856. return 0;
  1857. }
  1858. static void caam_cra_exit(struct crypto_tfm *tfm)
  1859. {
  1860. struct caam_ctx *ctx = crypto_tfm_ctx(tfm);
  1861. if (ctx->sh_desc_enc_dma &&
  1862. !dma_mapping_error(ctx->jrdev, ctx->sh_desc_enc_dma))
  1863. dma_unmap_single(ctx->jrdev, ctx->sh_desc_enc_dma,
  1864. desc_bytes(ctx->sh_desc_enc), DMA_TO_DEVICE);
  1865. if (ctx->sh_desc_dec_dma &&
  1866. !dma_mapping_error(ctx->jrdev, ctx->sh_desc_dec_dma))
  1867. dma_unmap_single(ctx->jrdev, ctx->sh_desc_dec_dma,
  1868. desc_bytes(ctx->sh_desc_dec), DMA_TO_DEVICE);
  1869. if (ctx->sh_desc_givenc_dma &&
  1870. !dma_mapping_error(ctx->jrdev, ctx->sh_desc_givenc_dma))
  1871. dma_unmap_single(ctx->jrdev, ctx->sh_desc_givenc_dma,
  1872. desc_bytes(ctx->sh_desc_givenc),
  1873. DMA_TO_DEVICE);
  1874. caam_jr_free(ctx->jrdev);
  1875. }
  1876. static void __exit caam_algapi_exit(void)
  1877. {
  1878. struct caam_crypto_alg *t_alg, *n;
  1879. if (!alg_list.next)
  1880. return;
  1881. list_for_each_entry_safe(t_alg, n, &alg_list, entry) {
  1882. crypto_unregister_alg(&t_alg->crypto_alg);
  1883. list_del(&t_alg->entry);
  1884. kfree(t_alg);
  1885. }
  1886. }
  1887. static struct caam_crypto_alg *caam_alg_alloc(struct caam_alg_template
  1888. *template)
  1889. {
  1890. struct caam_crypto_alg *t_alg;
  1891. struct crypto_alg *alg;
  1892. t_alg = kzalloc(sizeof(struct caam_crypto_alg), GFP_KERNEL);
  1893. if (!t_alg) {
  1894. pr_err("failed to allocate t_alg\n");
  1895. return ERR_PTR(-ENOMEM);
  1896. }
  1897. alg = &t_alg->crypto_alg;
  1898. snprintf(alg->cra_name, CRYPTO_MAX_ALG_NAME, "%s", template->name);
  1899. snprintf(alg->cra_driver_name, CRYPTO_MAX_ALG_NAME, "%s",
  1900. template->driver_name);
  1901. alg->cra_module = THIS_MODULE;
  1902. alg->cra_init = caam_cra_init;
  1903. alg->cra_exit = caam_cra_exit;
  1904. alg->cra_priority = CAAM_CRA_PRIORITY;
  1905. alg->cra_blocksize = template->blocksize;
  1906. alg->cra_alignmask = 0;
  1907. alg->cra_ctxsize = sizeof(struct caam_ctx);
  1908. alg->cra_flags = CRYPTO_ALG_ASYNC | CRYPTO_ALG_KERN_DRIVER_ONLY |
  1909. template->type;
  1910. switch (template->type) {
  1911. case CRYPTO_ALG_TYPE_ABLKCIPHER:
  1912. alg->cra_type = &crypto_ablkcipher_type;
  1913. alg->cra_ablkcipher = template->template_ablkcipher;
  1914. break;
  1915. case CRYPTO_ALG_TYPE_AEAD:
  1916. alg->cra_type = &crypto_aead_type;
  1917. alg->cra_aead = template->template_aead;
  1918. break;
  1919. }
  1920. t_alg->class1_alg_type = template->class1_alg_type;
  1921. t_alg->class2_alg_type = template->class2_alg_type;
  1922. t_alg->alg_op = template->alg_op;
  1923. return t_alg;
  1924. }
  1925. static int __init caam_algapi_init(void)
  1926. {
  1927. int i = 0, err = 0;
  1928. INIT_LIST_HEAD(&alg_list);
  1929. /* register crypto algorithms the device supports */
  1930. for (i = 0; i < ARRAY_SIZE(driver_algs); i++) {
  1931. /* TODO: check if h/w supports alg */
  1932. struct caam_crypto_alg *t_alg;
  1933. t_alg = caam_alg_alloc(&driver_algs[i]);
  1934. if (IS_ERR(t_alg)) {
  1935. err = PTR_ERR(t_alg);
  1936. pr_warn("%s alg allocation failed\n",
  1937. driver_algs[i].driver_name);
  1938. continue;
  1939. }
  1940. err = crypto_register_alg(&t_alg->crypto_alg);
  1941. if (err) {
  1942. pr_warn("%s alg registration failed\n",
  1943. t_alg->crypto_alg.cra_driver_name);
  1944. kfree(t_alg);
  1945. } else
  1946. list_add_tail(&t_alg->entry, &alg_list);
  1947. }
  1948. if (!list_empty(&alg_list))
  1949. pr_info("caam algorithms registered in /proc/crypto\n");
  1950. return err;
  1951. }
  1952. module_init(caam_algapi_init);
  1953. module_exit(caam_algapi_exit);
  1954. MODULE_LICENSE("GPL");
  1955. MODULE_DESCRIPTION("FSL CAAM support for crypto API");
  1956. MODULE_AUTHOR("Freescale Semiconductor - NMG/STC");