exynos_thermal.c 28 KB

12345678910111213141516171819202122232425262728293031323334353637383940414243444546474849505152535455565758596061626364656667686970717273747576777879808182838485868788899091929394959697989910010110210310410510610710810911011111211311411511611711811912012112212312412512612712812913013113213313413513613713813914014114214314414514614714814915015115215315415515615715815916016116216316416516616716816917017117217317417517617717817918018118218318418518618718818919019119219319419519619719819920020120220320420520620720820921021121221321421521621721821922022122222322422522622722822923023123223323423523623723823924024124224324424524624724824925025125225325425525625725825926026126226326426526626726826927027127227327427527627727827928028128228328428528628728828929029129229329429529629729829930030130230330430530630730830931031131231331431531631731831932032132232332432532632732832933033133233333433533633733833934034134234334434534634734834935035135235335435535635735835936036136236336436536636736836937037137237337437537637737837938038138238338438538638738838939039139239339439539639739839940040140240340440540640740840941041141241341441541641741841942042142242342442542642742842943043143243343443543643743843944044144244344444544644744844945045145245345445545645745845946046146246346446546646746846947047147247347447547647747847948048148248348448548648748848949049149249349449549649749849950050150250350450550650750850951051151251351451551651751851952052152252352452552652752852953053153253353453553653753853954054154254354454554654754854955055155255355455555655755855956056156256356456556656756856957057157257357457557657757857958058158258358458558658758858959059159259359459559659759859960060160260360460560660760860961061161261361461561661761861962062162262362462562662762862963063163263363463563663763863964064164264364464564664764864965065165265365465565665765865966066166266366466566666766866967067167267367467567667767867968068168268368468568668768868969069169269369469569669769869970070170270370470570670770870971071171271371471571671771871972072172272372472572672772872973073173273373473573673773873974074174274374474574674774874975075175275375475575675775875976076176276376476576676776876977077177277377477577677777877978078178278378478578678778878979079179279379479579679779879980080180280380480580680780880981081181281381481581681781881982082182282382482582682782882983083183283383483583683783883984084184284384484584684784884985085185285385485585685785885986086186286386486586686786886987087187287387487587687787887988088188288388488588688788888989089189289389489589689789889990090190290390490590690790890991091191291391491591691791891992092192292392492592692792892993093193293393493593693793893994094194294394494594694794894995095195295395495595695795895996096196296396496596696796896997097197297397497597697797897998098198298398498598698798898999099199299399499599699799899910001001100210031004100510061007100810091010101110121013101410151016101710181019102010211022102310241025102610271028102910301031103210331034103510361037103810391040104110421043104410451046104710481049105010511052105310541055105610571058105910601061106210631064106510661067106810691070107110721073107410751076107710781079108010811082108310841085108610871088108910901091109210931094109510961097109810991100
  1. /*
  2. * exynos_thermal.c - Samsung EXYNOS TMU (Thermal Management Unit)
  3. *
  4. * Copyright (C) 2011 Samsung Electronics
  5. * Donggeun Kim <dg77.kim@samsung.com>
  6. * Amit Daniel Kachhap <amit.kachhap@linaro.org>
  7. *
  8. * This program is free software; you can redistribute it and/or modify
  9. * it under the terms of the GNU General Public License as published by
  10. * the Free Software Foundation; either version 2 of the License, or
  11. * (at your option) any later version.
  12. *
  13. * This program is distributed in the hope that it will be useful,
  14. * but WITHOUT ANY WARRANTY; without even the implied warranty of
  15. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  16. * GNU General Public License for more details.
  17. *
  18. * You should have received a copy of the GNU General Public License
  19. * along with this program; if not, write to the Free Software
  20. * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
  21. *
  22. */
  23. #include <linux/module.h>
  24. #include <linux/err.h>
  25. #include <linux/kernel.h>
  26. #include <linux/slab.h>
  27. #include <linux/platform_device.h>
  28. #include <linux/interrupt.h>
  29. #include <linux/clk.h>
  30. #include <linux/workqueue.h>
  31. #include <linux/sysfs.h>
  32. #include <linux/kobject.h>
  33. #include <linux/io.h>
  34. #include <linux/mutex.h>
  35. #include <linux/platform_data/exynos_thermal.h>
  36. #include <linux/thermal.h>
  37. #include <linux/cpufreq.h>
  38. #include <linux/cpu_cooling.h>
  39. #include <linux/of.h>
  40. #include <plat/cpu.h>
  41. /* Exynos generic registers */
  42. #define EXYNOS_TMU_REG_TRIMINFO 0x0
  43. #define EXYNOS_TMU_REG_CONTROL 0x20
  44. #define EXYNOS_TMU_REG_STATUS 0x28
  45. #define EXYNOS_TMU_REG_CURRENT_TEMP 0x40
  46. #define EXYNOS_TMU_REG_INTEN 0x70
  47. #define EXYNOS_TMU_REG_INTSTAT 0x74
  48. #define EXYNOS_TMU_REG_INTCLEAR 0x78
  49. #define EXYNOS_TMU_TRIM_TEMP_MASK 0xff
  50. #define EXYNOS_TMU_GAIN_SHIFT 8
  51. #define EXYNOS_TMU_REF_VOLTAGE_SHIFT 24
  52. #define EXYNOS_TMU_CORE_ON 3
  53. #define EXYNOS_TMU_CORE_OFF 2
  54. #define EXYNOS_TMU_DEF_CODE_TO_TEMP_OFFSET 50
  55. /* Exynos4210 specific registers */
  56. #define EXYNOS4210_TMU_REG_THRESHOLD_TEMP 0x44
  57. #define EXYNOS4210_TMU_REG_TRIG_LEVEL0 0x50
  58. #define EXYNOS4210_TMU_REG_TRIG_LEVEL1 0x54
  59. #define EXYNOS4210_TMU_REG_TRIG_LEVEL2 0x58
  60. #define EXYNOS4210_TMU_REG_TRIG_LEVEL3 0x5C
  61. #define EXYNOS4210_TMU_REG_PAST_TEMP0 0x60
  62. #define EXYNOS4210_TMU_REG_PAST_TEMP1 0x64
  63. #define EXYNOS4210_TMU_REG_PAST_TEMP2 0x68
  64. #define EXYNOS4210_TMU_REG_PAST_TEMP3 0x6C
  65. #define EXYNOS4210_TMU_TRIG_LEVEL0_MASK 0x1
  66. #define EXYNOS4210_TMU_TRIG_LEVEL1_MASK 0x10
  67. #define EXYNOS4210_TMU_TRIG_LEVEL2_MASK 0x100
  68. #define EXYNOS4210_TMU_TRIG_LEVEL3_MASK 0x1000
  69. #define EXYNOS4210_TMU_INTCLEAR_VAL 0x1111
  70. /* Exynos5250 and Exynos4412 specific registers */
  71. #define EXYNOS_TMU_TRIMINFO_CON 0x14
  72. #define EXYNOS_THD_TEMP_RISE 0x50
  73. #define EXYNOS_THD_TEMP_FALL 0x54
  74. #define EXYNOS_EMUL_CON 0x80
  75. #define EXYNOS_TRIMINFO_RELOAD 0x1
  76. #define EXYNOS_TMU_CLEAR_RISE_INT 0x111
  77. #define EXYNOS_TMU_CLEAR_FALL_INT (0x111 << 16)
  78. #define EXYNOS_MUX_ADDR_VALUE 6
  79. #define EXYNOS_MUX_ADDR_SHIFT 20
  80. #define EXYNOS_TMU_TRIP_MODE_SHIFT 13
  81. #define EFUSE_MIN_VALUE 40
  82. #define EFUSE_MAX_VALUE 100
  83. /* In-kernel thermal framework related macros & definations */
  84. #define SENSOR_NAME_LEN 16
  85. #define MAX_TRIP_COUNT 8
  86. #define MAX_COOLING_DEVICE 4
  87. #define ACTIVE_INTERVAL 500
  88. #define IDLE_INTERVAL 10000
  89. #define MCELSIUS 1000
  90. #ifdef CONFIG_EXYNOS_THERMAL_EMUL
  91. #define EXYNOS_EMUL_TIME 0x57F0
  92. #define EXYNOS_EMUL_TIME_SHIFT 16
  93. #define EXYNOS_EMUL_DATA_SHIFT 8
  94. #define EXYNOS_EMUL_DATA_MASK 0xFF
  95. #define EXYNOS_EMUL_ENABLE 0x1
  96. #endif /* CONFIG_EXYNOS_THERMAL_EMUL */
  97. /* CPU Zone information */
  98. #define PANIC_ZONE 4
  99. #define WARN_ZONE 3
  100. #define MONITOR_ZONE 2
  101. #define SAFE_ZONE 1
  102. #define GET_ZONE(trip) (trip + 2)
  103. #define GET_TRIP(zone) (zone - 2)
  104. #define EXYNOS_ZONE_COUNT 3
  105. struct exynos_tmu_data {
  106. struct exynos_tmu_platform_data *pdata;
  107. struct resource *mem;
  108. void __iomem *base;
  109. int irq;
  110. enum soc_type soc;
  111. struct work_struct irq_work;
  112. struct mutex lock;
  113. struct clk *clk;
  114. u8 temp_error1, temp_error2;
  115. };
  116. struct thermal_trip_point_conf {
  117. int trip_val[MAX_TRIP_COUNT];
  118. int trip_count;
  119. };
  120. struct thermal_cooling_conf {
  121. struct freq_clip_table freq_data[MAX_TRIP_COUNT];
  122. int freq_clip_count;
  123. };
  124. struct thermal_sensor_conf {
  125. char name[SENSOR_NAME_LEN];
  126. int (*read_temperature)(void *data);
  127. struct thermal_trip_point_conf trip_data;
  128. struct thermal_cooling_conf cooling_data;
  129. void *private_data;
  130. };
  131. struct exynos_thermal_zone {
  132. enum thermal_device_mode mode;
  133. struct thermal_zone_device *therm_dev;
  134. struct thermal_cooling_device *cool_dev[MAX_COOLING_DEVICE];
  135. unsigned int cool_dev_size;
  136. struct platform_device *exynos4_dev;
  137. struct thermal_sensor_conf *sensor_conf;
  138. bool bind;
  139. };
  140. static struct exynos_thermal_zone *th_zone;
  141. static void exynos_unregister_thermal(void);
  142. static int exynos_register_thermal(struct thermal_sensor_conf *sensor_conf);
  143. /* Get mode callback functions for thermal zone */
  144. static int exynos_get_mode(struct thermal_zone_device *thermal,
  145. enum thermal_device_mode *mode)
  146. {
  147. if (th_zone)
  148. *mode = th_zone->mode;
  149. return 0;
  150. }
  151. /* Set mode callback functions for thermal zone */
  152. static int exynos_set_mode(struct thermal_zone_device *thermal,
  153. enum thermal_device_mode mode)
  154. {
  155. if (!th_zone->therm_dev) {
  156. pr_notice("thermal zone not registered\n");
  157. return 0;
  158. }
  159. mutex_lock(&th_zone->therm_dev->lock);
  160. if (mode == THERMAL_DEVICE_ENABLED)
  161. th_zone->therm_dev->polling_delay = IDLE_INTERVAL;
  162. else
  163. th_zone->therm_dev->polling_delay = 0;
  164. mutex_unlock(&th_zone->therm_dev->lock);
  165. th_zone->mode = mode;
  166. thermal_zone_device_update(th_zone->therm_dev);
  167. pr_info("thermal polling set for duration=%d msec\n",
  168. th_zone->therm_dev->polling_delay);
  169. return 0;
  170. }
  171. /* Get trip type callback functions for thermal zone */
  172. static int exynos_get_trip_type(struct thermal_zone_device *thermal, int trip,
  173. enum thermal_trip_type *type)
  174. {
  175. switch (GET_ZONE(trip)) {
  176. case MONITOR_ZONE:
  177. case WARN_ZONE:
  178. *type = THERMAL_TRIP_ACTIVE;
  179. break;
  180. case PANIC_ZONE:
  181. *type = THERMAL_TRIP_CRITICAL;
  182. break;
  183. default:
  184. return -EINVAL;
  185. }
  186. return 0;
  187. }
  188. /* Get trip temperature callback functions for thermal zone */
  189. static int exynos_get_trip_temp(struct thermal_zone_device *thermal, int trip,
  190. unsigned long *temp)
  191. {
  192. if (trip < GET_TRIP(MONITOR_ZONE) || trip > GET_TRIP(PANIC_ZONE))
  193. return -EINVAL;
  194. *temp = th_zone->sensor_conf->trip_data.trip_val[trip];
  195. /* convert the temperature into millicelsius */
  196. *temp = *temp * MCELSIUS;
  197. return 0;
  198. }
  199. /* Get critical temperature callback functions for thermal zone */
  200. static int exynos_get_crit_temp(struct thermal_zone_device *thermal,
  201. unsigned long *temp)
  202. {
  203. int ret;
  204. /* Panic zone */
  205. ret = exynos_get_trip_temp(thermal, GET_TRIP(PANIC_ZONE), temp);
  206. return ret;
  207. }
  208. static int exynos_get_frequency_level(unsigned int cpu, unsigned int freq)
  209. {
  210. int i = 0, ret = -EINVAL;
  211. struct cpufreq_frequency_table *table = NULL;
  212. #ifdef CONFIG_CPU_FREQ
  213. table = cpufreq_frequency_get_table(cpu);
  214. #endif
  215. if (!table)
  216. return ret;
  217. while (table[i].frequency != CPUFREQ_TABLE_END) {
  218. if (table[i].frequency == CPUFREQ_ENTRY_INVALID)
  219. continue;
  220. if (table[i].frequency == freq)
  221. return i;
  222. i++;
  223. }
  224. return ret;
  225. }
  226. /* Bind callback functions for thermal zone */
  227. static int exynos_bind(struct thermal_zone_device *thermal,
  228. struct thermal_cooling_device *cdev)
  229. {
  230. int ret = 0, i, tab_size, level;
  231. struct freq_clip_table *tab_ptr, *clip_data;
  232. struct thermal_sensor_conf *data = th_zone->sensor_conf;
  233. tab_ptr = (struct freq_clip_table *)data->cooling_data.freq_data;
  234. tab_size = data->cooling_data.freq_clip_count;
  235. if (tab_ptr == NULL || tab_size == 0)
  236. return -EINVAL;
  237. /* find the cooling device registered*/
  238. for (i = 0; i < th_zone->cool_dev_size; i++)
  239. if (cdev == th_zone->cool_dev[i])
  240. break;
  241. /* No matching cooling device */
  242. if (i == th_zone->cool_dev_size)
  243. return 0;
  244. /* Bind the thermal zone to the cpufreq cooling device */
  245. for (i = 0; i < tab_size; i++) {
  246. clip_data = (struct freq_clip_table *)&(tab_ptr[i]);
  247. level = exynos_get_frequency_level(0, clip_data->freq_clip_max);
  248. if (level < 0)
  249. return 0;
  250. switch (GET_ZONE(i)) {
  251. case MONITOR_ZONE:
  252. case WARN_ZONE:
  253. if (thermal_zone_bind_cooling_device(thermal, i, cdev,
  254. level, level)) {
  255. pr_err("error binding cdev inst %d\n", i);
  256. ret = -EINVAL;
  257. }
  258. th_zone->bind = true;
  259. break;
  260. default:
  261. ret = -EINVAL;
  262. }
  263. }
  264. return ret;
  265. }
  266. /* Unbind callback functions for thermal zone */
  267. static int exynos_unbind(struct thermal_zone_device *thermal,
  268. struct thermal_cooling_device *cdev)
  269. {
  270. int ret = 0, i, tab_size;
  271. struct thermal_sensor_conf *data = th_zone->sensor_conf;
  272. if (th_zone->bind == false)
  273. return 0;
  274. tab_size = data->cooling_data.freq_clip_count;
  275. if (tab_size == 0)
  276. return -EINVAL;
  277. /* find the cooling device registered*/
  278. for (i = 0; i < th_zone->cool_dev_size; i++)
  279. if (cdev == th_zone->cool_dev[i])
  280. break;
  281. /* No matching cooling device */
  282. if (i == th_zone->cool_dev_size)
  283. return 0;
  284. /* Bind the thermal zone to the cpufreq cooling device */
  285. for (i = 0; i < tab_size; i++) {
  286. switch (GET_ZONE(i)) {
  287. case MONITOR_ZONE:
  288. case WARN_ZONE:
  289. if (thermal_zone_unbind_cooling_device(thermal, i,
  290. cdev)) {
  291. pr_err("error unbinding cdev inst=%d\n", i);
  292. ret = -EINVAL;
  293. }
  294. th_zone->bind = false;
  295. break;
  296. default:
  297. ret = -EINVAL;
  298. }
  299. }
  300. return ret;
  301. }
  302. /* Get temperature callback functions for thermal zone */
  303. static int exynos_get_temp(struct thermal_zone_device *thermal,
  304. unsigned long *temp)
  305. {
  306. void *data;
  307. if (!th_zone->sensor_conf) {
  308. pr_info("Temperature sensor not initialised\n");
  309. return -EINVAL;
  310. }
  311. data = th_zone->sensor_conf->private_data;
  312. *temp = th_zone->sensor_conf->read_temperature(data);
  313. /* convert the temperature into millicelsius */
  314. *temp = *temp * MCELSIUS;
  315. return 0;
  316. }
  317. /* Get the temperature trend */
  318. static int exynos_get_trend(struct thermal_zone_device *thermal,
  319. int trip, enum thermal_trend *trend)
  320. {
  321. if (thermal->temperature >= trip)
  322. *trend = THERMAL_TREND_RAISING;
  323. else
  324. *trend = THERMAL_TREND_DROPPING;
  325. return 0;
  326. }
  327. /* Operation callback functions for thermal zone */
  328. static struct thermal_zone_device_ops const exynos_dev_ops = {
  329. .bind = exynos_bind,
  330. .unbind = exynos_unbind,
  331. .get_temp = exynos_get_temp,
  332. .get_trend = exynos_get_trend,
  333. .get_mode = exynos_get_mode,
  334. .set_mode = exynos_set_mode,
  335. .get_trip_type = exynos_get_trip_type,
  336. .get_trip_temp = exynos_get_trip_temp,
  337. .get_crit_temp = exynos_get_crit_temp,
  338. };
  339. /*
  340. * This function may be called from interrupt based temperature sensor
  341. * when threshold is changed.
  342. */
  343. static void exynos_report_trigger(void)
  344. {
  345. unsigned int i;
  346. char data[10];
  347. char *envp[] = { data, NULL };
  348. if (!th_zone || !th_zone->therm_dev)
  349. return;
  350. if (th_zone->bind == false) {
  351. for (i = 0; i < th_zone->cool_dev_size; i++) {
  352. if (!th_zone->cool_dev[i])
  353. continue;
  354. exynos_bind(th_zone->therm_dev,
  355. th_zone->cool_dev[i]);
  356. }
  357. }
  358. thermal_zone_device_update(th_zone->therm_dev);
  359. mutex_lock(&th_zone->therm_dev->lock);
  360. /* Find the level for which trip happened */
  361. for (i = 0; i < th_zone->sensor_conf->trip_data.trip_count; i++) {
  362. if (th_zone->therm_dev->last_temperature <
  363. th_zone->sensor_conf->trip_data.trip_val[i] * MCELSIUS)
  364. break;
  365. }
  366. if (th_zone->mode == THERMAL_DEVICE_ENABLED) {
  367. if (i > 0)
  368. th_zone->therm_dev->polling_delay = ACTIVE_INTERVAL;
  369. else
  370. th_zone->therm_dev->polling_delay = IDLE_INTERVAL;
  371. }
  372. snprintf(data, sizeof(data), "%u", i);
  373. kobject_uevent_env(&th_zone->therm_dev->device.kobj, KOBJ_CHANGE, envp);
  374. mutex_unlock(&th_zone->therm_dev->lock);
  375. }
  376. /* Register with the in-kernel thermal management */
  377. static int exynos_register_thermal(struct thermal_sensor_conf *sensor_conf)
  378. {
  379. int ret;
  380. struct cpumask mask_val;
  381. if (!sensor_conf || !sensor_conf->read_temperature) {
  382. pr_err("Temperature sensor not initialised\n");
  383. return -EINVAL;
  384. }
  385. th_zone = kzalloc(sizeof(struct exynos_thermal_zone), GFP_KERNEL);
  386. if (!th_zone)
  387. return -ENOMEM;
  388. th_zone->sensor_conf = sensor_conf;
  389. cpumask_set_cpu(0, &mask_val);
  390. th_zone->cool_dev[0] = cpufreq_cooling_register(&mask_val);
  391. if (IS_ERR(th_zone->cool_dev[0])) {
  392. pr_err("Failed to register cpufreq cooling device\n");
  393. ret = -EINVAL;
  394. goto err_unregister;
  395. }
  396. th_zone->cool_dev_size++;
  397. th_zone->therm_dev = thermal_zone_device_register(sensor_conf->name,
  398. EXYNOS_ZONE_COUNT, 0, NULL, &exynos_dev_ops, NULL, 0,
  399. IDLE_INTERVAL);
  400. if (IS_ERR(th_zone->therm_dev)) {
  401. pr_err("Failed to register thermal zone device\n");
  402. ret = -EINVAL;
  403. goto err_unregister;
  404. }
  405. th_zone->mode = THERMAL_DEVICE_ENABLED;
  406. pr_info("Exynos: Kernel Thermal management registered\n");
  407. return 0;
  408. err_unregister:
  409. exynos_unregister_thermal();
  410. return ret;
  411. }
  412. /* Un-Register with the in-kernel thermal management */
  413. static void exynos_unregister_thermal(void)
  414. {
  415. int i;
  416. if (!th_zone)
  417. return;
  418. if (th_zone->therm_dev)
  419. thermal_zone_device_unregister(th_zone->therm_dev);
  420. for (i = 0; i < th_zone->cool_dev_size; i++) {
  421. if (th_zone->cool_dev[i])
  422. cpufreq_cooling_unregister(th_zone->cool_dev[i]);
  423. }
  424. kfree(th_zone);
  425. pr_info("Exynos: Kernel Thermal management unregistered\n");
  426. }
  427. /*
  428. * TMU treats temperature as a mapped temperature code.
  429. * The temperature is converted differently depending on the calibration type.
  430. */
  431. static int temp_to_code(struct exynos_tmu_data *data, u8 temp)
  432. {
  433. struct exynos_tmu_platform_data *pdata = data->pdata;
  434. int temp_code;
  435. if (data->soc == SOC_ARCH_EXYNOS4210)
  436. /* temp should range between 25 and 125 */
  437. if (temp < 25 || temp > 125) {
  438. temp_code = -EINVAL;
  439. goto out;
  440. }
  441. switch (pdata->cal_type) {
  442. case TYPE_TWO_POINT_TRIMMING:
  443. temp_code = (temp - 25) *
  444. (data->temp_error2 - data->temp_error1) /
  445. (85 - 25) + data->temp_error1;
  446. break;
  447. case TYPE_ONE_POINT_TRIMMING:
  448. temp_code = temp + data->temp_error1 - 25;
  449. break;
  450. default:
  451. temp_code = temp + EXYNOS_TMU_DEF_CODE_TO_TEMP_OFFSET;
  452. break;
  453. }
  454. out:
  455. return temp_code;
  456. }
  457. /*
  458. * Calculate a temperature value from a temperature code.
  459. * The unit of the temperature is degree Celsius.
  460. */
  461. static int code_to_temp(struct exynos_tmu_data *data, u8 temp_code)
  462. {
  463. struct exynos_tmu_platform_data *pdata = data->pdata;
  464. int temp;
  465. if (data->soc == SOC_ARCH_EXYNOS4210)
  466. /* temp_code should range between 75 and 175 */
  467. if (temp_code < 75 || temp_code > 175) {
  468. temp = -ENODATA;
  469. goto out;
  470. }
  471. switch (pdata->cal_type) {
  472. case TYPE_TWO_POINT_TRIMMING:
  473. temp = (temp_code - data->temp_error1) * (85 - 25) /
  474. (data->temp_error2 - data->temp_error1) + 25;
  475. break;
  476. case TYPE_ONE_POINT_TRIMMING:
  477. temp = temp_code - data->temp_error1 + 25;
  478. break;
  479. default:
  480. temp = temp_code - EXYNOS_TMU_DEF_CODE_TO_TEMP_OFFSET;
  481. break;
  482. }
  483. out:
  484. return temp;
  485. }
  486. static int exynos_tmu_initialize(struct platform_device *pdev)
  487. {
  488. struct exynos_tmu_data *data = platform_get_drvdata(pdev);
  489. struct exynos_tmu_platform_data *pdata = data->pdata;
  490. unsigned int status, trim_info, rising_threshold;
  491. int ret = 0, threshold_code;
  492. mutex_lock(&data->lock);
  493. clk_enable(data->clk);
  494. status = readb(data->base + EXYNOS_TMU_REG_STATUS);
  495. if (!status) {
  496. ret = -EBUSY;
  497. goto out;
  498. }
  499. if (data->soc == SOC_ARCH_EXYNOS) {
  500. __raw_writel(EXYNOS_TRIMINFO_RELOAD,
  501. data->base + EXYNOS_TMU_TRIMINFO_CON);
  502. }
  503. /* Save trimming info in order to perform calibration */
  504. trim_info = readl(data->base + EXYNOS_TMU_REG_TRIMINFO);
  505. data->temp_error1 = trim_info & EXYNOS_TMU_TRIM_TEMP_MASK;
  506. data->temp_error2 = ((trim_info >> 8) & EXYNOS_TMU_TRIM_TEMP_MASK);
  507. if ((EFUSE_MIN_VALUE > data->temp_error1) ||
  508. (data->temp_error1 > EFUSE_MAX_VALUE) ||
  509. (data->temp_error2 != 0))
  510. data->temp_error1 = pdata->efuse_value;
  511. if (data->soc == SOC_ARCH_EXYNOS4210) {
  512. /* Write temperature code for threshold */
  513. threshold_code = temp_to_code(data, pdata->threshold);
  514. if (threshold_code < 0) {
  515. ret = threshold_code;
  516. goto out;
  517. }
  518. writeb(threshold_code,
  519. data->base + EXYNOS4210_TMU_REG_THRESHOLD_TEMP);
  520. writeb(pdata->trigger_levels[0],
  521. data->base + EXYNOS4210_TMU_REG_TRIG_LEVEL0);
  522. writeb(pdata->trigger_levels[1],
  523. data->base + EXYNOS4210_TMU_REG_TRIG_LEVEL1);
  524. writeb(pdata->trigger_levels[2],
  525. data->base + EXYNOS4210_TMU_REG_TRIG_LEVEL2);
  526. writeb(pdata->trigger_levels[3],
  527. data->base + EXYNOS4210_TMU_REG_TRIG_LEVEL3);
  528. writel(EXYNOS4210_TMU_INTCLEAR_VAL,
  529. data->base + EXYNOS_TMU_REG_INTCLEAR);
  530. } else if (data->soc == SOC_ARCH_EXYNOS) {
  531. /* Write temperature code for threshold */
  532. threshold_code = temp_to_code(data, pdata->trigger_levels[0]);
  533. if (threshold_code < 0) {
  534. ret = threshold_code;
  535. goto out;
  536. }
  537. rising_threshold = threshold_code;
  538. threshold_code = temp_to_code(data, pdata->trigger_levels[1]);
  539. if (threshold_code < 0) {
  540. ret = threshold_code;
  541. goto out;
  542. }
  543. rising_threshold |= (threshold_code << 8);
  544. threshold_code = temp_to_code(data, pdata->trigger_levels[2]);
  545. if (threshold_code < 0) {
  546. ret = threshold_code;
  547. goto out;
  548. }
  549. rising_threshold |= (threshold_code << 16);
  550. writel(rising_threshold,
  551. data->base + EXYNOS_THD_TEMP_RISE);
  552. writel(0, data->base + EXYNOS_THD_TEMP_FALL);
  553. writel(EXYNOS_TMU_CLEAR_RISE_INT|EXYNOS_TMU_CLEAR_FALL_INT,
  554. data->base + EXYNOS_TMU_REG_INTCLEAR);
  555. }
  556. out:
  557. clk_disable(data->clk);
  558. mutex_unlock(&data->lock);
  559. return ret;
  560. }
  561. static void exynos_tmu_control(struct platform_device *pdev, bool on)
  562. {
  563. struct exynos_tmu_data *data = platform_get_drvdata(pdev);
  564. struct exynos_tmu_platform_data *pdata = data->pdata;
  565. unsigned int con, interrupt_en;
  566. mutex_lock(&data->lock);
  567. clk_enable(data->clk);
  568. con = pdata->reference_voltage << EXYNOS_TMU_REF_VOLTAGE_SHIFT |
  569. pdata->gain << EXYNOS_TMU_GAIN_SHIFT;
  570. if (data->soc == SOC_ARCH_EXYNOS) {
  571. con |= pdata->noise_cancel_mode << EXYNOS_TMU_TRIP_MODE_SHIFT;
  572. con |= (EXYNOS_MUX_ADDR_VALUE << EXYNOS_MUX_ADDR_SHIFT);
  573. }
  574. if (on) {
  575. con |= EXYNOS_TMU_CORE_ON;
  576. interrupt_en = pdata->trigger_level3_en << 12 |
  577. pdata->trigger_level2_en << 8 |
  578. pdata->trigger_level1_en << 4 |
  579. pdata->trigger_level0_en;
  580. } else {
  581. con |= EXYNOS_TMU_CORE_OFF;
  582. interrupt_en = 0; /* Disable all interrupts */
  583. }
  584. writel(interrupt_en, data->base + EXYNOS_TMU_REG_INTEN);
  585. writel(con, data->base + EXYNOS_TMU_REG_CONTROL);
  586. clk_disable(data->clk);
  587. mutex_unlock(&data->lock);
  588. }
  589. static int exynos_tmu_read(struct exynos_tmu_data *data)
  590. {
  591. u8 temp_code;
  592. int temp;
  593. mutex_lock(&data->lock);
  594. clk_enable(data->clk);
  595. temp_code = readb(data->base + EXYNOS_TMU_REG_CURRENT_TEMP);
  596. temp = code_to_temp(data, temp_code);
  597. clk_disable(data->clk);
  598. mutex_unlock(&data->lock);
  599. return temp;
  600. }
  601. static void exynos_tmu_work(struct work_struct *work)
  602. {
  603. struct exynos_tmu_data *data = container_of(work,
  604. struct exynos_tmu_data, irq_work);
  605. mutex_lock(&data->lock);
  606. clk_enable(data->clk);
  607. if (data->soc == SOC_ARCH_EXYNOS)
  608. writel(EXYNOS_TMU_CLEAR_RISE_INT,
  609. data->base + EXYNOS_TMU_REG_INTCLEAR);
  610. else
  611. writel(EXYNOS4210_TMU_INTCLEAR_VAL,
  612. data->base + EXYNOS_TMU_REG_INTCLEAR);
  613. clk_disable(data->clk);
  614. mutex_unlock(&data->lock);
  615. exynos_report_trigger();
  616. enable_irq(data->irq);
  617. }
  618. static irqreturn_t exynos_tmu_irq(int irq, void *id)
  619. {
  620. struct exynos_tmu_data *data = id;
  621. disable_irq_nosync(irq);
  622. schedule_work(&data->irq_work);
  623. return IRQ_HANDLED;
  624. }
  625. static struct thermal_sensor_conf exynos_sensor_conf = {
  626. .name = "exynos-therm",
  627. .read_temperature = (int (*)(void *))exynos_tmu_read,
  628. };
  629. #if defined(CONFIG_CPU_EXYNOS4210)
  630. static struct exynos_tmu_platform_data const exynos4210_default_tmu_data = {
  631. .threshold = 80,
  632. .trigger_levels[0] = 5,
  633. .trigger_levels[1] = 20,
  634. .trigger_levels[2] = 30,
  635. .trigger_level0_en = 1,
  636. .trigger_level1_en = 1,
  637. .trigger_level2_en = 1,
  638. .trigger_level3_en = 0,
  639. .gain = 15,
  640. .reference_voltage = 7,
  641. .cal_type = TYPE_ONE_POINT_TRIMMING,
  642. .freq_tab[0] = {
  643. .freq_clip_max = 800 * 1000,
  644. .temp_level = 85,
  645. },
  646. .freq_tab[1] = {
  647. .freq_clip_max = 200 * 1000,
  648. .temp_level = 100,
  649. },
  650. .freq_tab_count = 2,
  651. .type = SOC_ARCH_EXYNOS4210,
  652. };
  653. #define EXYNOS4210_TMU_DRV_DATA (&exynos4210_default_tmu_data)
  654. #else
  655. #define EXYNOS4210_TMU_DRV_DATA (NULL)
  656. #endif
  657. #if defined(CONFIG_SOC_EXYNOS5250) || defined(CONFIG_SOC_EXYNOS4412)
  658. static struct exynos_tmu_platform_data const exynos_default_tmu_data = {
  659. .trigger_levels[0] = 85,
  660. .trigger_levels[1] = 103,
  661. .trigger_levels[2] = 110,
  662. .trigger_level0_en = 1,
  663. .trigger_level1_en = 1,
  664. .trigger_level2_en = 1,
  665. .trigger_level3_en = 0,
  666. .gain = 8,
  667. .reference_voltage = 16,
  668. .noise_cancel_mode = 4,
  669. .cal_type = TYPE_ONE_POINT_TRIMMING,
  670. .efuse_value = 55,
  671. .freq_tab[0] = {
  672. .freq_clip_max = 800 * 1000,
  673. .temp_level = 85,
  674. },
  675. .freq_tab[1] = {
  676. .freq_clip_max = 200 * 1000,
  677. .temp_level = 103,
  678. },
  679. .freq_tab_count = 2,
  680. .type = SOC_ARCH_EXYNOS,
  681. };
  682. #define EXYNOS_TMU_DRV_DATA (&exynos_default_tmu_data)
  683. #else
  684. #define EXYNOS_TMU_DRV_DATA (NULL)
  685. #endif
  686. #ifdef CONFIG_OF
  687. static const struct of_device_id exynos_tmu_match[] = {
  688. {
  689. .compatible = "samsung,exynos4210-tmu",
  690. .data = (void *)EXYNOS4210_TMU_DRV_DATA,
  691. },
  692. {
  693. .compatible = "samsung,exynos5250-tmu",
  694. .data = (void *)EXYNOS_TMU_DRV_DATA,
  695. },
  696. {},
  697. };
  698. MODULE_DEVICE_TABLE(of, exynos_tmu_match);
  699. #else
  700. #define exynos_tmu_match NULL
  701. #endif
  702. static struct platform_device_id exynos_tmu_driver_ids[] = {
  703. {
  704. .name = "exynos4210-tmu",
  705. .driver_data = (kernel_ulong_t)EXYNOS4210_TMU_DRV_DATA,
  706. },
  707. {
  708. .name = "exynos5250-tmu",
  709. .driver_data = (kernel_ulong_t)EXYNOS_TMU_DRV_DATA,
  710. },
  711. { },
  712. };
  713. MODULE_DEVICE_TABLE(platform, exynos_tmu_driver_ids);
  714. static inline struct exynos_tmu_platform_data *exynos_get_driver_data(
  715. struct platform_device *pdev)
  716. {
  717. #ifdef CONFIG_OF
  718. if (pdev->dev.of_node) {
  719. const struct of_device_id *match;
  720. match = of_match_node(exynos_tmu_match, pdev->dev.of_node);
  721. if (!match)
  722. return NULL;
  723. return (struct exynos_tmu_platform_data *) match->data;
  724. }
  725. #endif
  726. return (struct exynos_tmu_platform_data *)
  727. platform_get_device_id(pdev)->driver_data;
  728. }
  729. #ifdef CONFIG_EXYNOS_THERMAL_EMUL
  730. static ssize_t exynos_tmu_emulation_show(struct device *dev,
  731. struct device_attribute *attr,
  732. char *buf)
  733. {
  734. struct platform_device *pdev = container_of(dev,
  735. struct platform_device, dev);
  736. struct exynos_tmu_data *data = platform_get_drvdata(pdev);
  737. unsigned int reg;
  738. u8 temp_code;
  739. int temp = 0;
  740. if (data->soc == SOC_ARCH_EXYNOS4210)
  741. goto out;
  742. mutex_lock(&data->lock);
  743. clk_enable(data->clk);
  744. reg = readl(data->base + EXYNOS_EMUL_CON);
  745. clk_disable(data->clk);
  746. mutex_unlock(&data->lock);
  747. if (reg & EXYNOS_EMUL_ENABLE) {
  748. reg >>= EXYNOS_EMUL_DATA_SHIFT;
  749. temp_code = reg & EXYNOS_EMUL_DATA_MASK;
  750. temp = code_to_temp(data, temp_code);
  751. }
  752. out:
  753. return sprintf(buf, "%d\n", temp * MCELSIUS);
  754. }
  755. static ssize_t exynos_tmu_emulation_store(struct device *dev,
  756. struct device_attribute *attr,
  757. const char *buf, size_t count)
  758. {
  759. struct platform_device *pdev = container_of(dev,
  760. struct platform_device, dev);
  761. struct exynos_tmu_data *data = platform_get_drvdata(pdev);
  762. unsigned int reg;
  763. int temp;
  764. if (data->soc == SOC_ARCH_EXYNOS4210)
  765. goto out;
  766. if (!sscanf(buf, "%d\n", &temp) || temp < 0)
  767. return -EINVAL;
  768. mutex_lock(&data->lock);
  769. clk_enable(data->clk);
  770. reg = readl(data->base + EXYNOS_EMUL_CON);
  771. if (temp) {
  772. /* Both CELSIUS and MCELSIUS type are available for input */
  773. if (temp > MCELSIUS)
  774. temp /= MCELSIUS;
  775. reg = (EXYNOS_EMUL_TIME << EXYNOS_EMUL_TIME_SHIFT) |
  776. (temp_to_code(data, (temp / MCELSIUS))
  777. << EXYNOS_EMUL_DATA_SHIFT) | EXYNOS_EMUL_ENABLE;
  778. } else {
  779. reg &= ~EXYNOS_EMUL_ENABLE;
  780. }
  781. writel(reg, data->base + EXYNOS_EMUL_CON);
  782. clk_disable(data->clk);
  783. mutex_unlock(&data->lock);
  784. out:
  785. return count;
  786. }
  787. static DEVICE_ATTR(emulation, 0644, exynos_tmu_emulation_show,
  788. exynos_tmu_emulation_store);
  789. static int create_emulation_sysfs(struct device *dev)
  790. {
  791. return device_create_file(dev, &dev_attr_emulation);
  792. }
  793. static void remove_emulation_sysfs(struct device *dev)
  794. {
  795. device_remove_file(dev, &dev_attr_emulation);
  796. }
  797. #else
  798. static inline int create_emulation_sysfs(struct device *dev) { return 0; }
  799. static inline void remove_emulation_sysfs(struct device *dev) {}
  800. #endif
  801. static int __devinit exynos_tmu_probe(struct platform_device *pdev)
  802. {
  803. struct exynos_tmu_data *data;
  804. struct exynos_tmu_platform_data *pdata = pdev->dev.platform_data;
  805. int ret, i;
  806. if (!pdata)
  807. pdata = exynos_get_driver_data(pdev);
  808. if (!pdata) {
  809. dev_err(&pdev->dev, "No platform init data supplied.\n");
  810. return -ENODEV;
  811. }
  812. data = devm_kzalloc(&pdev->dev, sizeof(struct exynos_tmu_data),
  813. GFP_KERNEL);
  814. if (!data) {
  815. dev_err(&pdev->dev, "Failed to allocate driver structure\n");
  816. return -ENOMEM;
  817. }
  818. data->irq = platform_get_irq(pdev, 0);
  819. if (data->irq < 0) {
  820. dev_err(&pdev->dev, "Failed to get platform irq\n");
  821. return data->irq;
  822. }
  823. INIT_WORK(&data->irq_work, exynos_tmu_work);
  824. data->mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
  825. if (!data->mem) {
  826. dev_err(&pdev->dev, "Failed to get platform resource\n");
  827. return -ENOENT;
  828. }
  829. data->base = devm_request_and_ioremap(&pdev->dev, data->mem);
  830. if (!data->base) {
  831. dev_err(&pdev->dev, "Failed to ioremap memory\n");
  832. return -ENODEV;
  833. }
  834. ret = devm_request_irq(&pdev->dev, data->irq, exynos_tmu_irq,
  835. IRQF_TRIGGER_RISING, "exynos-tmu", data);
  836. if (ret) {
  837. dev_err(&pdev->dev, "Failed to request irq: %d\n", data->irq);
  838. return ret;
  839. }
  840. data->clk = clk_get(NULL, "tmu_apbif");
  841. if (IS_ERR(data->clk)) {
  842. dev_err(&pdev->dev, "Failed to get clock\n");
  843. return PTR_ERR(data->clk);
  844. }
  845. if (pdata->type == SOC_ARCH_EXYNOS ||
  846. pdata->type == SOC_ARCH_EXYNOS4210)
  847. data->soc = pdata->type;
  848. else {
  849. ret = -EINVAL;
  850. dev_err(&pdev->dev, "Platform not supported\n");
  851. goto err_clk;
  852. }
  853. data->pdata = pdata;
  854. platform_set_drvdata(pdev, data);
  855. mutex_init(&data->lock);
  856. ret = exynos_tmu_initialize(pdev);
  857. if (ret) {
  858. dev_err(&pdev->dev, "Failed to initialize TMU\n");
  859. goto err_clk;
  860. }
  861. exynos_tmu_control(pdev, true);
  862. /* Register the sensor with thermal management interface */
  863. (&exynos_sensor_conf)->private_data = data;
  864. exynos_sensor_conf.trip_data.trip_count = pdata->trigger_level0_en +
  865. pdata->trigger_level1_en + pdata->trigger_level2_en +
  866. pdata->trigger_level3_en;
  867. for (i = 0; i < exynos_sensor_conf.trip_data.trip_count; i++)
  868. exynos_sensor_conf.trip_data.trip_val[i] =
  869. pdata->threshold + pdata->trigger_levels[i];
  870. exynos_sensor_conf.cooling_data.freq_clip_count =
  871. pdata->freq_tab_count;
  872. for (i = 0; i < pdata->freq_tab_count; i++) {
  873. exynos_sensor_conf.cooling_data.freq_data[i].freq_clip_max =
  874. pdata->freq_tab[i].freq_clip_max;
  875. exynos_sensor_conf.cooling_data.freq_data[i].temp_level =
  876. pdata->freq_tab[i].temp_level;
  877. }
  878. ret = exynos_register_thermal(&exynos_sensor_conf);
  879. if (ret) {
  880. dev_err(&pdev->dev, "Failed to register thermal interface\n");
  881. goto err_clk;
  882. }
  883. ret = create_emulation_sysfs(&pdev->dev);
  884. if (ret)
  885. dev_err(&pdev->dev, "Failed to create emulation mode sysfs node\n");
  886. return 0;
  887. err_clk:
  888. platform_set_drvdata(pdev, NULL);
  889. clk_put(data->clk);
  890. return ret;
  891. }
  892. static int __devexit exynos_tmu_remove(struct platform_device *pdev)
  893. {
  894. struct exynos_tmu_data *data = platform_get_drvdata(pdev);
  895. remove_emulation_sysfs(&pdev->dev);
  896. exynos_tmu_control(pdev, false);
  897. exynos_unregister_thermal();
  898. clk_put(data->clk);
  899. platform_set_drvdata(pdev, NULL);
  900. return 0;
  901. }
  902. #ifdef CONFIG_PM_SLEEP
  903. static int exynos_tmu_suspend(struct device *dev)
  904. {
  905. exynos_tmu_control(to_platform_device(dev), false);
  906. return 0;
  907. }
  908. static int exynos_tmu_resume(struct device *dev)
  909. {
  910. struct platform_device *pdev = to_platform_device(dev);
  911. exynos_tmu_initialize(pdev);
  912. exynos_tmu_control(pdev, true);
  913. return 0;
  914. }
  915. static SIMPLE_DEV_PM_OPS(exynos_tmu_pm,
  916. exynos_tmu_suspend, exynos_tmu_resume);
  917. #define EXYNOS_TMU_PM (&exynos_tmu_pm)
  918. #else
  919. #define EXYNOS_TMU_PM NULL
  920. #endif
  921. static struct platform_driver exynos_tmu_driver = {
  922. .driver = {
  923. .name = "exynos-tmu",
  924. .owner = THIS_MODULE,
  925. .pm = EXYNOS_TMU_PM,
  926. .of_match_table = exynos_tmu_match,
  927. },
  928. .probe = exynos_tmu_probe,
  929. .remove = __devexit_p(exynos_tmu_remove),
  930. .id_table = exynos_tmu_driver_ids,
  931. };
  932. module_platform_driver(exynos_tmu_driver);
  933. MODULE_DESCRIPTION("EXYNOS TMU Driver");
  934. MODULE_AUTHOR("Donggeun Kim <dg77.kim@samsung.com>");
  935. MODULE_LICENSE("GPL");
  936. MODULE_ALIAS("platform:exynos-tmu");