qeth_core_main.c 123 KB

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  1. /*
  2. * drivers/s390/net/qeth_core_main.c
  3. *
  4. * Copyright IBM Corp. 2007
  5. * Author(s): Utz Bacher <utz.bacher@de.ibm.com>,
  6. * Frank Pavlic <fpavlic@de.ibm.com>,
  7. * Thomas Spatzier <tspat@de.ibm.com>,
  8. * Frank Blaschka <frank.blaschka@de.ibm.com>
  9. */
  10. #include <linux/module.h>
  11. #include <linux/moduleparam.h>
  12. #include <linux/string.h>
  13. #include <linux/errno.h>
  14. #include <linux/kernel.h>
  15. #include <linux/ip.h>
  16. #include <linux/ipv6.h>
  17. #include <linux/tcp.h>
  18. #include <linux/mii.h>
  19. #include <linux/kthread.h>
  20. #include <asm/ebcdic.h>
  21. #include <asm/io.h>
  22. #include <asm/s390_rdev.h>
  23. #include "qeth_core.h"
  24. #include "qeth_core_offl.h"
  25. struct qeth_dbf_info qeth_dbf[QETH_DBF_INFOS] = {
  26. /* define dbf - Name, Pages, Areas, Maxlen, Level, View, Handle */
  27. /* N P A M L V H */
  28. [QETH_DBF_SETUP] = {"qeth_setup",
  29. 8, 1, 8, 5, &debug_hex_ascii_view, NULL},
  30. [QETH_DBF_QERR] = {"qeth_qerr",
  31. 2, 1, 8, 2, &debug_hex_ascii_view, NULL},
  32. [QETH_DBF_TRACE] = {"qeth_trace",
  33. 4, 1, 8, 3, &debug_hex_ascii_view, NULL},
  34. [QETH_DBF_MSG] = {"qeth_msg",
  35. 8, 1, 128, 3, &debug_sprintf_view, NULL},
  36. [QETH_DBF_SENSE] = {"qeth_sense",
  37. 2, 1, 64, 2, &debug_hex_ascii_view, NULL},
  38. [QETH_DBF_MISC] = {"qeth_misc",
  39. 2, 1, 256, 2, &debug_hex_ascii_view, NULL},
  40. [QETH_DBF_CTRL] = {"qeth_control",
  41. 8, 1, QETH_DBF_CTRL_LEN, 5, &debug_hex_ascii_view, NULL},
  42. };
  43. EXPORT_SYMBOL_GPL(qeth_dbf);
  44. struct qeth_card_list_struct qeth_core_card_list;
  45. EXPORT_SYMBOL_GPL(qeth_core_card_list);
  46. struct kmem_cache *qeth_core_header_cache;
  47. EXPORT_SYMBOL_GPL(qeth_core_header_cache);
  48. static struct device *qeth_core_root_dev;
  49. static unsigned int known_devices[][10] = QETH_MODELLIST_ARRAY;
  50. static struct lock_class_key qdio_out_skb_queue_key;
  51. static void qeth_send_control_data_cb(struct qeth_channel *,
  52. struct qeth_cmd_buffer *);
  53. static int qeth_issue_next_read(struct qeth_card *);
  54. static struct qeth_cmd_buffer *qeth_get_buffer(struct qeth_channel *);
  55. static void qeth_setup_ccw(struct qeth_channel *, unsigned char *, __u32);
  56. static void qeth_free_buffer_pool(struct qeth_card *);
  57. static int qeth_qdio_establish(struct qeth_card *);
  58. static inline void __qeth_fill_buffer_frag(struct sk_buff *skb,
  59. struct qdio_buffer *buffer, int is_tso,
  60. int *next_element_to_fill)
  61. {
  62. struct skb_frag_struct *frag;
  63. int fragno;
  64. unsigned long addr;
  65. int element, cnt, dlen;
  66. fragno = skb_shinfo(skb)->nr_frags;
  67. element = *next_element_to_fill;
  68. dlen = 0;
  69. if (is_tso)
  70. buffer->element[element].flags =
  71. SBAL_FLAGS_MIDDLE_FRAG;
  72. else
  73. buffer->element[element].flags =
  74. SBAL_FLAGS_FIRST_FRAG;
  75. dlen = skb->len - skb->data_len;
  76. if (dlen) {
  77. buffer->element[element].addr = skb->data;
  78. buffer->element[element].length = dlen;
  79. element++;
  80. }
  81. for (cnt = 0; cnt < fragno; cnt++) {
  82. frag = &skb_shinfo(skb)->frags[cnt];
  83. addr = (page_to_pfn(frag->page) << PAGE_SHIFT) +
  84. frag->page_offset;
  85. buffer->element[element].addr = (char *)addr;
  86. buffer->element[element].length = frag->size;
  87. if (cnt < (fragno - 1))
  88. buffer->element[element].flags =
  89. SBAL_FLAGS_MIDDLE_FRAG;
  90. else
  91. buffer->element[element].flags =
  92. SBAL_FLAGS_LAST_FRAG;
  93. element++;
  94. }
  95. *next_element_to_fill = element;
  96. }
  97. static inline const char *qeth_get_cardname(struct qeth_card *card)
  98. {
  99. if (card->info.guestlan) {
  100. switch (card->info.type) {
  101. case QETH_CARD_TYPE_OSAE:
  102. return " Guest LAN QDIO";
  103. case QETH_CARD_TYPE_IQD:
  104. return " Guest LAN Hiper";
  105. default:
  106. return " unknown";
  107. }
  108. } else {
  109. switch (card->info.type) {
  110. case QETH_CARD_TYPE_OSAE:
  111. return " OSD Express";
  112. case QETH_CARD_TYPE_IQD:
  113. return " HiperSockets";
  114. case QETH_CARD_TYPE_OSN:
  115. return " OSN QDIO";
  116. default:
  117. return " unknown";
  118. }
  119. }
  120. return " n/a";
  121. }
  122. /* max length to be returned: 14 */
  123. const char *qeth_get_cardname_short(struct qeth_card *card)
  124. {
  125. if (card->info.guestlan) {
  126. switch (card->info.type) {
  127. case QETH_CARD_TYPE_OSAE:
  128. return "GuestLAN QDIO";
  129. case QETH_CARD_TYPE_IQD:
  130. return "GuestLAN Hiper";
  131. default:
  132. return "unknown";
  133. }
  134. } else {
  135. switch (card->info.type) {
  136. case QETH_CARD_TYPE_OSAE:
  137. switch (card->info.link_type) {
  138. case QETH_LINK_TYPE_FAST_ETH:
  139. return "OSD_100";
  140. case QETH_LINK_TYPE_HSTR:
  141. return "HSTR";
  142. case QETH_LINK_TYPE_GBIT_ETH:
  143. return "OSD_1000";
  144. case QETH_LINK_TYPE_10GBIT_ETH:
  145. return "OSD_10GIG";
  146. case QETH_LINK_TYPE_LANE_ETH100:
  147. return "OSD_FE_LANE";
  148. case QETH_LINK_TYPE_LANE_TR:
  149. return "OSD_TR_LANE";
  150. case QETH_LINK_TYPE_LANE_ETH1000:
  151. return "OSD_GbE_LANE";
  152. case QETH_LINK_TYPE_LANE:
  153. return "OSD_ATM_LANE";
  154. default:
  155. return "OSD_Express";
  156. }
  157. case QETH_CARD_TYPE_IQD:
  158. return "HiperSockets";
  159. case QETH_CARD_TYPE_OSN:
  160. return "OSN";
  161. default:
  162. return "unknown";
  163. }
  164. }
  165. return "n/a";
  166. }
  167. void qeth_set_allowed_threads(struct qeth_card *card, unsigned long threads,
  168. int clear_start_mask)
  169. {
  170. unsigned long flags;
  171. spin_lock_irqsave(&card->thread_mask_lock, flags);
  172. card->thread_allowed_mask = threads;
  173. if (clear_start_mask)
  174. card->thread_start_mask &= threads;
  175. spin_unlock_irqrestore(&card->thread_mask_lock, flags);
  176. wake_up(&card->wait_q);
  177. }
  178. EXPORT_SYMBOL_GPL(qeth_set_allowed_threads);
  179. int qeth_threads_running(struct qeth_card *card, unsigned long threads)
  180. {
  181. unsigned long flags;
  182. int rc = 0;
  183. spin_lock_irqsave(&card->thread_mask_lock, flags);
  184. rc = (card->thread_running_mask & threads);
  185. spin_unlock_irqrestore(&card->thread_mask_lock, flags);
  186. return rc;
  187. }
  188. EXPORT_SYMBOL_GPL(qeth_threads_running);
  189. int qeth_wait_for_threads(struct qeth_card *card, unsigned long threads)
  190. {
  191. return wait_event_interruptible(card->wait_q,
  192. qeth_threads_running(card, threads) == 0);
  193. }
  194. EXPORT_SYMBOL_GPL(qeth_wait_for_threads);
  195. void qeth_clear_working_pool_list(struct qeth_card *card)
  196. {
  197. struct qeth_buffer_pool_entry *pool_entry, *tmp;
  198. QETH_DBF_TEXT(TRACE, 5, "clwrklst");
  199. list_for_each_entry_safe(pool_entry, tmp,
  200. &card->qdio.in_buf_pool.entry_list, list){
  201. list_del(&pool_entry->list);
  202. }
  203. }
  204. EXPORT_SYMBOL_GPL(qeth_clear_working_pool_list);
  205. static int qeth_alloc_buffer_pool(struct qeth_card *card)
  206. {
  207. struct qeth_buffer_pool_entry *pool_entry;
  208. void *ptr;
  209. int i, j;
  210. QETH_DBF_TEXT(TRACE, 5, "alocpool");
  211. for (i = 0; i < card->qdio.init_pool.buf_count; ++i) {
  212. pool_entry = kmalloc(sizeof(*pool_entry), GFP_KERNEL);
  213. if (!pool_entry) {
  214. qeth_free_buffer_pool(card);
  215. return -ENOMEM;
  216. }
  217. for (j = 0; j < QETH_MAX_BUFFER_ELEMENTS(card); ++j) {
  218. ptr = (void *) __get_free_page(GFP_KERNEL);
  219. if (!ptr) {
  220. while (j > 0)
  221. free_page((unsigned long)
  222. pool_entry->elements[--j]);
  223. kfree(pool_entry);
  224. qeth_free_buffer_pool(card);
  225. return -ENOMEM;
  226. }
  227. pool_entry->elements[j] = ptr;
  228. }
  229. list_add(&pool_entry->init_list,
  230. &card->qdio.init_pool.entry_list);
  231. }
  232. return 0;
  233. }
  234. int qeth_realloc_buffer_pool(struct qeth_card *card, int bufcnt)
  235. {
  236. QETH_DBF_TEXT(TRACE, 2, "realcbp");
  237. if ((card->state != CARD_STATE_DOWN) &&
  238. (card->state != CARD_STATE_RECOVER))
  239. return -EPERM;
  240. /* TODO: steel/add buffers from/to a running card's buffer pool (?) */
  241. qeth_clear_working_pool_list(card);
  242. qeth_free_buffer_pool(card);
  243. card->qdio.in_buf_pool.buf_count = bufcnt;
  244. card->qdio.init_pool.buf_count = bufcnt;
  245. return qeth_alloc_buffer_pool(card);
  246. }
  247. int qeth_set_large_send(struct qeth_card *card,
  248. enum qeth_large_send_types type)
  249. {
  250. int rc = 0;
  251. if (card->dev == NULL) {
  252. card->options.large_send = type;
  253. return 0;
  254. }
  255. if (card->state == CARD_STATE_UP)
  256. netif_tx_disable(card->dev);
  257. card->options.large_send = type;
  258. switch (card->options.large_send) {
  259. case QETH_LARGE_SEND_EDDP:
  260. card->dev->features |= NETIF_F_TSO | NETIF_F_SG |
  261. NETIF_F_HW_CSUM;
  262. break;
  263. case QETH_LARGE_SEND_TSO:
  264. if (qeth_is_supported(card, IPA_OUTBOUND_TSO)) {
  265. card->dev->features |= NETIF_F_TSO | NETIF_F_SG |
  266. NETIF_F_HW_CSUM;
  267. } else {
  268. card->dev->features &= ~(NETIF_F_TSO | NETIF_F_SG |
  269. NETIF_F_HW_CSUM);
  270. card->options.large_send = QETH_LARGE_SEND_NO;
  271. rc = -EOPNOTSUPP;
  272. }
  273. break;
  274. default: /* includes QETH_LARGE_SEND_NO */
  275. card->dev->features &= ~(NETIF_F_TSO | NETIF_F_SG |
  276. NETIF_F_HW_CSUM);
  277. break;
  278. }
  279. if (card->state == CARD_STATE_UP)
  280. netif_wake_queue(card->dev);
  281. return rc;
  282. }
  283. EXPORT_SYMBOL_GPL(qeth_set_large_send);
  284. static int qeth_issue_next_read(struct qeth_card *card)
  285. {
  286. int rc;
  287. struct qeth_cmd_buffer *iob;
  288. QETH_DBF_TEXT(TRACE, 5, "issnxrd");
  289. if (card->read.state != CH_STATE_UP)
  290. return -EIO;
  291. iob = qeth_get_buffer(&card->read);
  292. if (!iob) {
  293. PRINT_WARN("issue_next_read failed: no iob available!\n");
  294. return -ENOMEM;
  295. }
  296. qeth_setup_ccw(&card->read, iob->data, QETH_BUFSIZE);
  297. QETH_DBF_TEXT(TRACE, 6, "noirqpnd");
  298. rc = ccw_device_start(card->read.ccwdev, &card->read.ccw,
  299. (addr_t) iob, 0, 0);
  300. if (rc) {
  301. PRINT_ERR("Error in starting next read ccw! rc=%i\n", rc);
  302. atomic_set(&card->read.irq_pending, 0);
  303. qeth_schedule_recovery(card);
  304. wake_up(&card->wait_q);
  305. }
  306. return rc;
  307. }
  308. static struct qeth_reply *qeth_alloc_reply(struct qeth_card *card)
  309. {
  310. struct qeth_reply *reply;
  311. reply = kzalloc(sizeof(struct qeth_reply), GFP_ATOMIC);
  312. if (reply) {
  313. atomic_set(&reply->refcnt, 1);
  314. atomic_set(&reply->received, 0);
  315. reply->card = card;
  316. };
  317. return reply;
  318. }
  319. static void qeth_get_reply(struct qeth_reply *reply)
  320. {
  321. WARN_ON(atomic_read(&reply->refcnt) <= 0);
  322. atomic_inc(&reply->refcnt);
  323. }
  324. static void qeth_put_reply(struct qeth_reply *reply)
  325. {
  326. WARN_ON(atomic_read(&reply->refcnt) <= 0);
  327. if (atomic_dec_and_test(&reply->refcnt))
  328. kfree(reply);
  329. }
  330. static void qeth_issue_ipa_msg(struct qeth_ipa_cmd *cmd, int rc,
  331. struct qeth_card *card)
  332. {
  333. char *ipa_name;
  334. int com = cmd->hdr.command;
  335. ipa_name = qeth_get_ipa_cmd_name(com);
  336. if (rc)
  337. QETH_DBF_MESSAGE(2, "IPA: %s(x%X) for %s returned x%X \"%s\"\n",
  338. ipa_name, com, QETH_CARD_IFNAME(card),
  339. rc, qeth_get_ipa_msg(rc));
  340. else
  341. QETH_DBF_MESSAGE(5, "IPA: %s(x%X) for %s succeeded\n",
  342. ipa_name, com, QETH_CARD_IFNAME(card));
  343. }
  344. static struct qeth_ipa_cmd *qeth_check_ipa_data(struct qeth_card *card,
  345. struct qeth_cmd_buffer *iob)
  346. {
  347. struct qeth_ipa_cmd *cmd = NULL;
  348. QETH_DBF_TEXT(TRACE, 5, "chkipad");
  349. if (IS_IPA(iob->data)) {
  350. cmd = (struct qeth_ipa_cmd *) PDU_ENCAPSULATION(iob->data);
  351. if (IS_IPA_REPLY(cmd)) {
  352. if (cmd->hdr.command < IPA_CMD_SETCCID ||
  353. cmd->hdr.command > IPA_CMD_MODCCID)
  354. qeth_issue_ipa_msg(cmd,
  355. cmd->hdr.return_code, card);
  356. return cmd;
  357. } else {
  358. switch (cmd->hdr.command) {
  359. case IPA_CMD_STOPLAN:
  360. PRINT_WARN("Link failure on %s (CHPID 0x%X) - "
  361. "there is a network problem or "
  362. "someone pulled the cable or "
  363. "disabled the port.\n",
  364. QETH_CARD_IFNAME(card),
  365. card->info.chpid);
  366. card->lan_online = 0;
  367. if (card->dev && netif_carrier_ok(card->dev))
  368. netif_carrier_off(card->dev);
  369. return NULL;
  370. case IPA_CMD_STARTLAN:
  371. PRINT_INFO("Link reestablished on %s "
  372. "(CHPID 0x%X). Scheduling "
  373. "IP address reset.\n",
  374. QETH_CARD_IFNAME(card),
  375. card->info.chpid);
  376. netif_carrier_on(card->dev);
  377. card->lan_online = 1;
  378. qeth_schedule_recovery(card);
  379. return NULL;
  380. case IPA_CMD_MODCCID:
  381. return cmd;
  382. case IPA_CMD_REGISTER_LOCAL_ADDR:
  383. QETH_DBF_TEXT(TRACE, 3, "irla");
  384. break;
  385. case IPA_CMD_UNREGISTER_LOCAL_ADDR:
  386. QETH_DBF_TEXT(TRACE, 3, "urla");
  387. break;
  388. default:
  389. QETH_DBF_MESSAGE(2, "Received data is IPA "
  390. "but not a reply!\n");
  391. break;
  392. }
  393. }
  394. }
  395. return cmd;
  396. }
  397. void qeth_clear_ipacmd_list(struct qeth_card *card)
  398. {
  399. struct qeth_reply *reply, *r;
  400. unsigned long flags;
  401. QETH_DBF_TEXT(TRACE, 4, "clipalst");
  402. spin_lock_irqsave(&card->lock, flags);
  403. list_for_each_entry_safe(reply, r, &card->cmd_waiter_list, list) {
  404. qeth_get_reply(reply);
  405. reply->rc = -EIO;
  406. atomic_inc(&reply->received);
  407. list_del_init(&reply->list);
  408. wake_up(&reply->wait_q);
  409. qeth_put_reply(reply);
  410. }
  411. spin_unlock_irqrestore(&card->lock, flags);
  412. }
  413. EXPORT_SYMBOL_GPL(qeth_clear_ipacmd_list);
  414. static int qeth_check_idx_response(unsigned char *buffer)
  415. {
  416. if (!buffer)
  417. return 0;
  418. QETH_DBF_HEX(CTRL, 2, buffer, QETH_DBF_CTRL_LEN);
  419. if ((buffer[2] & 0xc0) == 0xc0) {
  420. PRINT_WARN("received an IDX TERMINATE "
  421. "with cause code 0x%02x%s\n",
  422. buffer[4],
  423. ((buffer[4] == 0x22) ?
  424. " -- try another portname" : ""));
  425. QETH_DBF_TEXT(TRACE, 2, "ckidxres");
  426. QETH_DBF_TEXT(TRACE, 2, " idxterm");
  427. QETH_DBF_TEXT_(TRACE, 2, " rc%d", -EIO);
  428. return -EIO;
  429. }
  430. return 0;
  431. }
  432. static void qeth_setup_ccw(struct qeth_channel *channel, unsigned char *iob,
  433. __u32 len)
  434. {
  435. struct qeth_card *card;
  436. QETH_DBF_TEXT(TRACE, 4, "setupccw");
  437. card = CARD_FROM_CDEV(channel->ccwdev);
  438. if (channel == &card->read)
  439. memcpy(&channel->ccw, READ_CCW, sizeof(struct ccw1));
  440. else
  441. memcpy(&channel->ccw, WRITE_CCW, sizeof(struct ccw1));
  442. channel->ccw.count = len;
  443. channel->ccw.cda = (__u32) __pa(iob);
  444. }
  445. static struct qeth_cmd_buffer *__qeth_get_buffer(struct qeth_channel *channel)
  446. {
  447. __u8 index;
  448. QETH_DBF_TEXT(TRACE, 6, "getbuff");
  449. index = channel->io_buf_no;
  450. do {
  451. if (channel->iob[index].state == BUF_STATE_FREE) {
  452. channel->iob[index].state = BUF_STATE_LOCKED;
  453. channel->io_buf_no = (channel->io_buf_no + 1) %
  454. QETH_CMD_BUFFER_NO;
  455. memset(channel->iob[index].data, 0, QETH_BUFSIZE);
  456. return channel->iob + index;
  457. }
  458. index = (index + 1) % QETH_CMD_BUFFER_NO;
  459. } while (index != channel->io_buf_no);
  460. return NULL;
  461. }
  462. void qeth_release_buffer(struct qeth_channel *channel,
  463. struct qeth_cmd_buffer *iob)
  464. {
  465. unsigned long flags;
  466. QETH_DBF_TEXT(TRACE, 6, "relbuff");
  467. spin_lock_irqsave(&channel->iob_lock, flags);
  468. memset(iob->data, 0, QETH_BUFSIZE);
  469. iob->state = BUF_STATE_FREE;
  470. iob->callback = qeth_send_control_data_cb;
  471. iob->rc = 0;
  472. spin_unlock_irqrestore(&channel->iob_lock, flags);
  473. }
  474. EXPORT_SYMBOL_GPL(qeth_release_buffer);
  475. static struct qeth_cmd_buffer *qeth_get_buffer(struct qeth_channel *channel)
  476. {
  477. struct qeth_cmd_buffer *buffer = NULL;
  478. unsigned long flags;
  479. spin_lock_irqsave(&channel->iob_lock, flags);
  480. buffer = __qeth_get_buffer(channel);
  481. spin_unlock_irqrestore(&channel->iob_lock, flags);
  482. return buffer;
  483. }
  484. struct qeth_cmd_buffer *qeth_wait_for_buffer(struct qeth_channel *channel)
  485. {
  486. struct qeth_cmd_buffer *buffer;
  487. wait_event(channel->wait_q,
  488. ((buffer = qeth_get_buffer(channel)) != NULL));
  489. return buffer;
  490. }
  491. EXPORT_SYMBOL_GPL(qeth_wait_for_buffer);
  492. void qeth_clear_cmd_buffers(struct qeth_channel *channel)
  493. {
  494. int cnt;
  495. for (cnt = 0; cnt < QETH_CMD_BUFFER_NO; cnt++)
  496. qeth_release_buffer(channel, &channel->iob[cnt]);
  497. channel->buf_no = 0;
  498. channel->io_buf_no = 0;
  499. }
  500. EXPORT_SYMBOL_GPL(qeth_clear_cmd_buffers);
  501. static void qeth_send_control_data_cb(struct qeth_channel *channel,
  502. struct qeth_cmd_buffer *iob)
  503. {
  504. struct qeth_card *card;
  505. struct qeth_reply *reply, *r;
  506. struct qeth_ipa_cmd *cmd;
  507. unsigned long flags;
  508. int keep_reply;
  509. QETH_DBF_TEXT(TRACE, 4, "sndctlcb");
  510. card = CARD_FROM_CDEV(channel->ccwdev);
  511. if (qeth_check_idx_response(iob->data)) {
  512. qeth_clear_ipacmd_list(card);
  513. qeth_schedule_recovery(card);
  514. goto out;
  515. }
  516. cmd = qeth_check_ipa_data(card, iob);
  517. if ((cmd == NULL) && (card->state != CARD_STATE_DOWN))
  518. goto out;
  519. /*in case of OSN : check if cmd is set */
  520. if (card->info.type == QETH_CARD_TYPE_OSN &&
  521. cmd &&
  522. cmd->hdr.command != IPA_CMD_STARTLAN &&
  523. card->osn_info.assist_cb != NULL) {
  524. card->osn_info.assist_cb(card->dev, cmd);
  525. goto out;
  526. }
  527. spin_lock_irqsave(&card->lock, flags);
  528. list_for_each_entry_safe(reply, r, &card->cmd_waiter_list, list) {
  529. if ((reply->seqno == QETH_IDX_COMMAND_SEQNO) ||
  530. ((cmd) && (reply->seqno == cmd->hdr.seqno))) {
  531. qeth_get_reply(reply);
  532. list_del_init(&reply->list);
  533. spin_unlock_irqrestore(&card->lock, flags);
  534. keep_reply = 0;
  535. if (reply->callback != NULL) {
  536. if (cmd) {
  537. reply->offset = (__u16)((char *)cmd -
  538. (char *)iob->data);
  539. keep_reply = reply->callback(card,
  540. reply,
  541. (unsigned long)cmd);
  542. } else
  543. keep_reply = reply->callback(card,
  544. reply,
  545. (unsigned long)iob);
  546. }
  547. if (cmd)
  548. reply->rc = (u16) cmd->hdr.return_code;
  549. else if (iob->rc)
  550. reply->rc = iob->rc;
  551. if (keep_reply) {
  552. spin_lock_irqsave(&card->lock, flags);
  553. list_add_tail(&reply->list,
  554. &card->cmd_waiter_list);
  555. spin_unlock_irqrestore(&card->lock, flags);
  556. } else {
  557. atomic_inc(&reply->received);
  558. wake_up(&reply->wait_q);
  559. }
  560. qeth_put_reply(reply);
  561. goto out;
  562. }
  563. }
  564. spin_unlock_irqrestore(&card->lock, flags);
  565. out:
  566. memcpy(&card->seqno.pdu_hdr_ack,
  567. QETH_PDU_HEADER_SEQ_NO(iob->data),
  568. QETH_SEQ_NO_LENGTH);
  569. qeth_release_buffer(channel, iob);
  570. }
  571. static int qeth_setup_channel(struct qeth_channel *channel)
  572. {
  573. int cnt;
  574. QETH_DBF_TEXT(SETUP, 2, "setupch");
  575. for (cnt = 0; cnt < QETH_CMD_BUFFER_NO; cnt++) {
  576. channel->iob[cnt].data = (char *)
  577. kmalloc(QETH_BUFSIZE, GFP_DMA|GFP_KERNEL);
  578. if (channel->iob[cnt].data == NULL)
  579. break;
  580. channel->iob[cnt].state = BUF_STATE_FREE;
  581. channel->iob[cnt].channel = channel;
  582. channel->iob[cnt].callback = qeth_send_control_data_cb;
  583. channel->iob[cnt].rc = 0;
  584. }
  585. if (cnt < QETH_CMD_BUFFER_NO) {
  586. while (cnt-- > 0)
  587. kfree(channel->iob[cnt].data);
  588. return -ENOMEM;
  589. }
  590. channel->buf_no = 0;
  591. channel->io_buf_no = 0;
  592. atomic_set(&channel->irq_pending, 0);
  593. spin_lock_init(&channel->iob_lock);
  594. init_waitqueue_head(&channel->wait_q);
  595. return 0;
  596. }
  597. static int qeth_set_thread_start_bit(struct qeth_card *card,
  598. unsigned long thread)
  599. {
  600. unsigned long flags;
  601. spin_lock_irqsave(&card->thread_mask_lock, flags);
  602. if (!(card->thread_allowed_mask & thread) ||
  603. (card->thread_start_mask & thread)) {
  604. spin_unlock_irqrestore(&card->thread_mask_lock, flags);
  605. return -EPERM;
  606. }
  607. card->thread_start_mask |= thread;
  608. spin_unlock_irqrestore(&card->thread_mask_lock, flags);
  609. return 0;
  610. }
  611. void qeth_clear_thread_start_bit(struct qeth_card *card, unsigned long thread)
  612. {
  613. unsigned long flags;
  614. spin_lock_irqsave(&card->thread_mask_lock, flags);
  615. card->thread_start_mask &= ~thread;
  616. spin_unlock_irqrestore(&card->thread_mask_lock, flags);
  617. wake_up(&card->wait_q);
  618. }
  619. EXPORT_SYMBOL_GPL(qeth_clear_thread_start_bit);
  620. void qeth_clear_thread_running_bit(struct qeth_card *card, unsigned long thread)
  621. {
  622. unsigned long flags;
  623. spin_lock_irqsave(&card->thread_mask_lock, flags);
  624. card->thread_running_mask &= ~thread;
  625. spin_unlock_irqrestore(&card->thread_mask_lock, flags);
  626. wake_up(&card->wait_q);
  627. }
  628. EXPORT_SYMBOL_GPL(qeth_clear_thread_running_bit);
  629. static int __qeth_do_run_thread(struct qeth_card *card, unsigned long thread)
  630. {
  631. unsigned long flags;
  632. int rc = 0;
  633. spin_lock_irqsave(&card->thread_mask_lock, flags);
  634. if (card->thread_start_mask & thread) {
  635. if ((card->thread_allowed_mask & thread) &&
  636. !(card->thread_running_mask & thread)) {
  637. rc = 1;
  638. card->thread_start_mask &= ~thread;
  639. card->thread_running_mask |= thread;
  640. } else
  641. rc = -EPERM;
  642. }
  643. spin_unlock_irqrestore(&card->thread_mask_lock, flags);
  644. return rc;
  645. }
  646. int qeth_do_run_thread(struct qeth_card *card, unsigned long thread)
  647. {
  648. int rc = 0;
  649. wait_event(card->wait_q,
  650. (rc = __qeth_do_run_thread(card, thread)) >= 0);
  651. return rc;
  652. }
  653. EXPORT_SYMBOL_GPL(qeth_do_run_thread);
  654. void qeth_schedule_recovery(struct qeth_card *card)
  655. {
  656. QETH_DBF_TEXT(TRACE, 2, "startrec");
  657. if (qeth_set_thread_start_bit(card, QETH_RECOVER_THREAD) == 0)
  658. schedule_work(&card->kernel_thread_starter);
  659. }
  660. EXPORT_SYMBOL_GPL(qeth_schedule_recovery);
  661. static int qeth_get_problem(struct ccw_device *cdev, struct irb *irb)
  662. {
  663. int dstat, cstat;
  664. char *sense;
  665. sense = (char *) irb->ecw;
  666. cstat = irb->scsw.cmd.cstat;
  667. dstat = irb->scsw.cmd.dstat;
  668. if (cstat & (SCHN_STAT_CHN_CTRL_CHK | SCHN_STAT_INTF_CTRL_CHK |
  669. SCHN_STAT_CHN_DATA_CHK | SCHN_STAT_CHAIN_CHECK |
  670. SCHN_STAT_PROT_CHECK | SCHN_STAT_PROG_CHECK)) {
  671. QETH_DBF_TEXT(TRACE, 2, "CGENCHK");
  672. PRINT_WARN("check on device %s, dstat=x%x, cstat=x%x ",
  673. dev_name(&cdev->dev), dstat, cstat);
  674. print_hex_dump(KERN_WARNING, "qeth: irb ", DUMP_PREFIX_OFFSET,
  675. 16, 1, irb, 64, 1);
  676. return 1;
  677. }
  678. if (dstat & DEV_STAT_UNIT_CHECK) {
  679. if (sense[SENSE_RESETTING_EVENT_BYTE] &
  680. SENSE_RESETTING_EVENT_FLAG) {
  681. QETH_DBF_TEXT(TRACE, 2, "REVIND");
  682. return 1;
  683. }
  684. if (sense[SENSE_COMMAND_REJECT_BYTE] &
  685. SENSE_COMMAND_REJECT_FLAG) {
  686. QETH_DBF_TEXT(TRACE, 2, "CMDREJi");
  687. return 1;
  688. }
  689. if ((sense[2] == 0xaf) && (sense[3] == 0xfe)) {
  690. QETH_DBF_TEXT(TRACE, 2, "AFFE");
  691. return 1;
  692. }
  693. if ((!sense[0]) && (!sense[1]) && (!sense[2]) && (!sense[3])) {
  694. QETH_DBF_TEXT(TRACE, 2, "ZEROSEN");
  695. return 0;
  696. }
  697. QETH_DBF_TEXT(TRACE, 2, "DGENCHK");
  698. return 1;
  699. }
  700. return 0;
  701. }
  702. static long __qeth_check_irb_error(struct ccw_device *cdev,
  703. unsigned long intparm, struct irb *irb)
  704. {
  705. if (!IS_ERR(irb))
  706. return 0;
  707. switch (PTR_ERR(irb)) {
  708. case -EIO:
  709. PRINT_WARN("i/o-error on device %s\n", dev_name(&cdev->dev));
  710. QETH_DBF_TEXT(TRACE, 2, "ckirberr");
  711. QETH_DBF_TEXT_(TRACE, 2, " rc%d", -EIO);
  712. break;
  713. case -ETIMEDOUT:
  714. PRINT_WARN("timeout on device %s\n", dev_name(&cdev->dev));
  715. QETH_DBF_TEXT(TRACE, 2, "ckirberr");
  716. QETH_DBF_TEXT_(TRACE, 2, " rc%d", -ETIMEDOUT);
  717. if (intparm == QETH_RCD_PARM) {
  718. struct qeth_card *card = CARD_FROM_CDEV(cdev);
  719. if (card && (card->data.ccwdev == cdev)) {
  720. card->data.state = CH_STATE_DOWN;
  721. wake_up(&card->wait_q);
  722. }
  723. }
  724. break;
  725. default:
  726. PRINT_WARN("unknown error %ld on device %s\n", PTR_ERR(irb),
  727. dev_name(&cdev->dev));
  728. QETH_DBF_TEXT(TRACE, 2, "ckirberr");
  729. QETH_DBF_TEXT(TRACE, 2, " rc???");
  730. }
  731. return PTR_ERR(irb);
  732. }
  733. static void qeth_irq(struct ccw_device *cdev, unsigned long intparm,
  734. struct irb *irb)
  735. {
  736. int rc;
  737. int cstat, dstat;
  738. struct qeth_cmd_buffer *buffer;
  739. struct qeth_channel *channel;
  740. struct qeth_card *card;
  741. struct qeth_cmd_buffer *iob;
  742. __u8 index;
  743. QETH_DBF_TEXT(TRACE, 5, "irq");
  744. if (__qeth_check_irb_error(cdev, intparm, irb))
  745. return;
  746. cstat = irb->scsw.cmd.cstat;
  747. dstat = irb->scsw.cmd.dstat;
  748. card = CARD_FROM_CDEV(cdev);
  749. if (!card)
  750. return;
  751. if (card->read.ccwdev == cdev) {
  752. channel = &card->read;
  753. QETH_DBF_TEXT(TRACE, 5, "read");
  754. } else if (card->write.ccwdev == cdev) {
  755. channel = &card->write;
  756. QETH_DBF_TEXT(TRACE, 5, "write");
  757. } else {
  758. channel = &card->data;
  759. QETH_DBF_TEXT(TRACE, 5, "data");
  760. }
  761. atomic_set(&channel->irq_pending, 0);
  762. if (irb->scsw.cmd.fctl & (SCSW_FCTL_CLEAR_FUNC))
  763. channel->state = CH_STATE_STOPPED;
  764. if (irb->scsw.cmd.fctl & (SCSW_FCTL_HALT_FUNC))
  765. channel->state = CH_STATE_HALTED;
  766. /*let's wake up immediately on data channel*/
  767. if ((channel == &card->data) && (intparm != 0) &&
  768. (intparm != QETH_RCD_PARM))
  769. goto out;
  770. if (intparm == QETH_CLEAR_CHANNEL_PARM) {
  771. QETH_DBF_TEXT(TRACE, 6, "clrchpar");
  772. /* we don't have to handle this further */
  773. intparm = 0;
  774. }
  775. if (intparm == QETH_HALT_CHANNEL_PARM) {
  776. QETH_DBF_TEXT(TRACE, 6, "hltchpar");
  777. /* we don't have to handle this further */
  778. intparm = 0;
  779. }
  780. if ((dstat & DEV_STAT_UNIT_EXCEP) ||
  781. (dstat & DEV_STAT_UNIT_CHECK) ||
  782. (cstat)) {
  783. if (irb->esw.esw0.erw.cons) {
  784. /* TODO: we should make this s390dbf */
  785. PRINT_WARN("sense data available on channel %s.\n",
  786. CHANNEL_ID(channel));
  787. PRINT_WARN(" cstat 0x%X\n dstat 0x%X\n", cstat, dstat);
  788. print_hex_dump(KERN_WARNING, "qeth: irb ",
  789. DUMP_PREFIX_OFFSET, 16, 1, irb, 32, 1);
  790. print_hex_dump(KERN_WARNING, "qeth: sense data ",
  791. DUMP_PREFIX_OFFSET, 16, 1, irb->ecw, 32, 1);
  792. }
  793. if (intparm == QETH_RCD_PARM) {
  794. channel->state = CH_STATE_DOWN;
  795. goto out;
  796. }
  797. rc = qeth_get_problem(cdev, irb);
  798. if (rc) {
  799. qeth_clear_ipacmd_list(card);
  800. qeth_schedule_recovery(card);
  801. goto out;
  802. }
  803. }
  804. if (intparm == QETH_RCD_PARM) {
  805. channel->state = CH_STATE_RCD_DONE;
  806. goto out;
  807. }
  808. if (intparm) {
  809. buffer = (struct qeth_cmd_buffer *) __va((addr_t)intparm);
  810. buffer->state = BUF_STATE_PROCESSED;
  811. }
  812. if (channel == &card->data)
  813. return;
  814. if (channel == &card->read &&
  815. channel->state == CH_STATE_UP)
  816. qeth_issue_next_read(card);
  817. iob = channel->iob;
  818. index = channel->buf_no;
  819. while (iob[index].state == BUF_STATE_PROCESSED) {
  820. if (iob[index].callback != NULL)
  821. iob[index].callback(channel, iob + index);
  822. index = (index + 1) % QETH_CMD_BUFFER_NO;
  823. }
  824. channel->buf_no = index;
  825. out:
  826. wake_up(&card->wait_q);
  827. return;
  828. }
  829. static void qeth_clear_output_buffer(struct qeth_qdio_out_q *queue,
  830. struct qeth_qdio_out_buffer *buf)
  831. {
  832. int i;
  833. struct sk_buff *skb;
  834. /* is PCI flag set on buffer? */
  835. if (buf->buffer->element[0].flags & 0x40)
  836. atomic_dec(&queue->set_pci_flags_count);
  837. skb = skb_dequeue(&buf->skb_list);
  838. while (skb) {
  839. atomic_dec(&skb->users);
  840. dev_kfree_skb_any(skb);
  841. skb = skb_dequeue(&buf->skb_list);
  842. }
  843. qeth_eddp_buf_release_contexts(buf);
  844. for (i = 0; i < QETH_MAX_BUFFER_ELEMENTS(queue->card); ++i) {
  845. if (buf->buffer->element[i].addr && buf->is_header[i])
  846. kmem_cache_free(qeth_core_header_cache,
  847. buf->buffer->element[i].addr);
  848. buf->is_header[i] = 0;
  849. buf->buffer->element[i].length = 0;
  850. buf->buffer->element[i].addr = NULL;
  851. buf->buffer->element[i].flags = 0;
  852. }
  853. buf->next_element_to_fill = 0;
  854. atomic_set(&buf->state, QETH_QDIO_BUF_EMPTY);
  855. }
  856. void qeth_clear_qdio_buffers(struct qeth_card *card)
  857. {
  858. int i, j;
  859. QETH_DBF_TEXT(TRACE, 2, "clearqdbf");
  860. /* clear outbound buffers to free skbs */
  861. for (i = 0; i < card->qdio.no_out_queues; ++i)
  862. if (card->qdio.out_qs[i]) {
  863. for (j = 0; j < QDIO_MAX_BUFFERS_PER_Q; ++j)
  864. qeth_clear_output_buffer(card->qdio.out_qs[i],
  865. &card->qdio.out_qs[i]->bufs[j]);
  866. }
  867. }
  868. EXPORT_SYMBOL_GPL(qeth_clear_qdio_buffers);
  869. static void qeth_free_buffer_pool(struct qeth_card *card)
  870. {
  871. struct qeth_buffer_pool_entry *pool_entry, *tmp;
  872. int i = 0;
  873. QETH_DBF_TEXT(TRACE, 5, "freepool");
  874. list_for_each_entry_safe(pool_entry, tmp,
  875. &card->qdio.init_pool.entry_list, init_list){
  876. for (i = 0; i < QETH_MAX_BUFFER_ELEMENTS(card); ++i)
  877. free_page((unsigned long)pool_entry->elements[i]);
  878. list_del(&pool_entry->init_list);
  879. kfree(pool_entry);
  880. }
  881. }
  882. static void qeth_free_qdio_buffers(struct qeth_card *card)
  883. {
  884. int i, j;
  885. QETH_DBF_TEXT(TRACE, 2, "freeqdbf");
  886. if (atomic_xchg(&card->qdio.state, QETH_QDIO_UNINITIALIZED) ==
  887. QETH_QDIO_UNINITIALIZED)
  888. return;
  889. kfree(card->qdio.in_q);
  890. card->qdio.in_q = NULL;
  891. /* inbound buffer pool */
  892. qeth_free_buffer_pool(card);
  893. /* free outbound qdio_qs */
  894. if (card->qdio.out_qs) {
  895. for (i = 0; i < card->qdio.no_out_queues; ++i) {
  896. for (j = 0; j < QDIO_MAX_BUFFERS_PER_Q; ++j)
  897. qeth_clear_output_buffer(card->qdio.out_qs[i],
  898. &card->qdio.out_qs[i]->bufs[j]);
  899. kfree(card->qdio.out_qs[i]);
  900. }
  901. kfree(card->qdio.out_qs);
  902. card->qdio.out_qs = NULL;
  903. }
  904. }
  905. static void qeth_clean_channel(struct qeth_channel *channel)
  906. {
  907. int cnt;
  908. QETH_DBF_TEXT(SETUP, 2, "freech");
  909. for (cnt = 0; cnt < QETH_CMD_BUFFER_NO; cnt++)
  910. kfree(channel->iob[cnt].data);
  911. }
  912. static int qeth_is_1920_device(struct qeth_card *card)
  913. {
  914. int single_queue = 0;
  915. struct ccw_device *ccwdev;
  916. struct channelPath_dsc {
  917. u8 flags;
  918. u8 lsn;
  919. u8 desc;
  920. u8 chpid;
  921. u8 swla;
  922. u8 zeroes;
  923. u8 chla;
  924. u8 chpp;
  925. } *chp_dsc;
  926. QETH_DBF_TEXT(SETUP, 2, "chk_1920");
  927. ccwdev = card->data.ccwdev;
  928. chp_dsc = (struct channelPath_dsc *)ccw_device_get_chp_desc(ccwdev, 0);
  929. if (chp_dsc != NULL) {
  930. /* CHPP field bit 6 == 1 -> single queue */
  931. single_queue = ((chp_dsc->chpp & 0x02) == 0x02);
  932. kfree(chp_dsc);
  933. }
  934. QETH_DBF_TEXT_(SETUP, 2, "rc:%x", single_queue);
  935. return single_queue;
  936. }
  937. static void qeth_init_qdio_info(struct qeth_card *card)
  938. {
  939. QETH_DBF_TEXT(SETUP, 4, "intqdinf");
  940. atomic_set(&card->qdio.state, QETH_QDIO_UNINITIALIZED);
  941. /* inbound */
  942. card->qdio.in_buf_size = QETH_IN_BUF_SIZE_DEFAULT;
  943. card->qdio.init_pool.buf_count = QETH_IN_BUF_COUNT_DEFAULT;
  944. card->qdio.in_buf_pool.buf_count = card->qdio.init_pool.buf_count;
  945. INIT_LIST_HEAD(&card->qdio.in_buf_pool.entry_list);
  946. INIT_LIST_HEAD(&card->qdio.init_pool.entry_list);
  947. }
  948. static void qeth_set_intial_options(struct qeth_card *card)
  949. {
  950. card->options.route4.type = NO_ROUTER;
  951. card->options.route6.type = NO_ROUTER;
  952. card->options.checksum_type = QETH_CHECKSUM_DEFAULT;
  953. card->options.broadcast_mode = QETH_TR_BROADCAST_ALLRINGS;
  954. card->options.macaddr_mode = QETH_TR_MACADDR_NONCANONICAL;
  955. card->options.fake_broadcast = 0;
  956. card->options.add_hhlen = DEFAULT_ADD_HHLEN;
  957. card->options.fake_ll = 0;
  958. card->options.performance_stats = 0;
  959. card->options.rx_sg_cb = QETH_RX_SG_CB;
  960. }
  961. static int qeth_do_start_thread(struct qeth_card *card, unsigned long thread)
  962. {
  963. unsigned long flags;
  964. int rc = 0;
  965. spin_lock_irqsave(&card->thread_mask_lock, flags);
  966. QETH_DBF_TEXT_(TRACE, 4, " %02x%02x%02x",
  967. (u8) card->thread_start_mask,
  968. (u8) card->thread_allowed_mask,
  969. (u8) card->thread_running_mask);
  970. rc = (card->thread_start_mask & thread);
  971. spin_unlock_irqrestore(&card->thread_mask_lock, flags);
  972. return rc;
  973. }
  974. static void qeth_start_kernel_thread(struct work_struct *work)
  975. {
  976. struct qeth_card *card = container_of(work, struct qeth_card,
  977. kernel_thread_starter);
  978. QETH_DBF_TEXT(TRACE , 2, "strthrd");
  979. if (card->read.state != CH_STATE_UP &&
  980. card->write.state != CH_STATE_UP)
  981. return;
  982. if (qeth_do_start_thread(card, QETH_RECOVER_THREAD))
  983. kthread_run(card->discipline.recover, (void *) card,
  984. "qeth_recover");
  985. }
  986. static int qeth_setup_card(struct qeth_card *card)
  987. {
  988. QETH_DBF_TEXT(SETUP, 2, "setupcrd");
  989. QETH_DBF_HEX(SETUP, 2, &card, sizeof(void *));
  990. card->read.state = CH_STATE_DOWN;
  991. card->write.state = CH_STATE_DOWN;
  992. card->data.state = CH_STATE_DOWN;
  993. card->state = CARD_STATE_DOWN;
  994. card->lan_online = 0;
  995. card->use_hard_stop = 0;
  996. card->dev = NULL;
  997. spin_lock_init(&card->vlanlock);
  998. spin_lock_init(&card->mclock);
  999. card->vlangrp = NULL;
  1000. spin_lock_init(&card->lock);
  1001. spin_lock_init(&card->ip_lock);
  1002. spin_lock_init(&card->thread_mask_lock);
  1003. card->thread_start_mask = 0;
  1004. card->thread_allowed_mask = 0;
  1005. card->thread_running_mask = 0;
  1006. INIT_WORK(&card->kernel_thread_starter, qeth_start_kernel_thread);
  1007. INIT_LIST_HEAD(&card->ip_list);
  1008. card->ip_tbd_list = kmalloc(sizeof(struct list_head), GFP_KERNEL);
  1009. if (!card->ip_tbd_list) {
  1010. QETH_DBF_TEXT(SETUP, 0, "iptbdnom");
  1011. return -ENOMEM;
  1012. }
  1013. INIT_LIST_HEAD(card->ip_tbd_list);
  1014. INIT_LIST_HEAD(&card->cmd_waiter_list);
  1015. init_waitqueue_head(&card->wait_q);
  1016. /* intial options */
  1017. qeth_set_intial_options(card);
  1018. /* IP address takeover */
  1019. INIT_LIST_HEAD(&card->ipato.entries);
  1020. card->ipato.enabled = 0;
  1021. card->ipato.invert4 = 0;
  1022. card->ipato.invert6 = 0;
  1023. /* init QDIO stuff */
  1024. qeth_init_qdio_info(card);
  1025. return 0;
  1026. }
  1027. static struct qeth_card *qeth_alloc_card(void)
  1028. {
  1029. struct qeth_card *card;
  1030. QETH_DBF_TEXT(SETUP, 2, "alloccrd");
  1031. card = kzalloc(sizeof(struct qeth_card), GFP_DMA|GFP_KERNEL);
  1032. if (!card)
  1033. return NULL;
  1034. QETH_DBF_HEX(SETUP, 2, &card, sizeof(void *));
  1035. if (qeth_setup_channel(&card->read)) {
  1036. kfree(card);
  1037. return NULL;
  1038. }
  1039. if (qeth_setup_channel(&card->write)) {
  1040. qeth_clean_channel(&card->read);
  1041. kfree(card);
  1042. return NULL;
  1043. }
  1044. card->options.layer2 = -1;
  1045. return card;
  1046. }
  1047. static int qeth_determine_card_type(struct qeth_card *card)
  1048. {
  1049. int i = 0;
  1050. QETH_DBF_TEXT(SETUP, 2, "detcdtyp");
  1051. card->qdio.do_prio_queueing = QETH_PRIOQ_DEFAULT;
  1052. card->qdio.default_out_queue = QETH_DEFAULT_QUEUE;
  1053. while (known_devices[i][4]) {
  1054. if ((CARD_RDEV(card)->id.dev_type == known_devices[i][2]) &&
  1055. (CARD_RDEV(card)->id.dev_model == known_devices[i][3])) {
  1056. card->info.type = known_devices[i][4];
  1057. card->qdio.no_out_queues = known_devices[i][8];
  1058. card->info.is_multicast_different = known_devices[i][9];
  1059. if (qeth_is_1920_device(card)) {
  1060. PRINT_INFO("Priority Queueing not able "
  1061. "due to hardware limitations!\n");
  1062. card->qdio.no_out_queues = 1;
  1063. card->qdio.default_out_queue = 0;
  1064. }
  1065. return 0;
  1066. }
  1067. i++;
  1068. }
  1069. card->info.type = QETH_CARD_TYPE_UNKNOWN;
  1070. PRINT_ERR("unknown card type on device %s\n", CARD_BUS_ID(card));
  1071. return -ENOENT;
  1072. }
  1073. static int qeth_clear_channel(struct qeth_channel *channel)
  1074. {
  1075. unsigned long flags;
  1076. struct qeth_card *card;
  1077. int rc;
  1078. QETH_DBF_TEXT(TRACE, 3, "clearch");
  1079. card = CARD_FROM_CDEV(channel->ccwdev);
  1080. spin_lock_irqsave(get_ccwdev_lock(channel->ccwdev), flags);
  1081. rc = ccw_device_clear(channel->ccwdev, QETH_CLEAR_CHANNEL_PARM);
  1082. spin_unlock_irqrestore(get_ccwdev_lock(channel->ccwdev), flags);
  1083. if (rc)
  1084. return rc;
  1085. rc = wait_event_interruptible_timeout(card->wait_q,
  1086. channel->state == CH_STATE_STOPPED, QETH_TIMEOUT);
  1087. if (rc == -ERESTARTSYS)
  1088. return rc;
  1089. if (channel->state != CH_STATE_STOPPED)
  1090. return -ETIME;
  1091. channel->state = CH_STATE_DOWN;
  1092. return 0;
  1093. }
  1094. static int qeth_halt_channel(struct qeth_channel *channel)
  1095. {
  1096. unsigned long flags;
  1097. struct qeth_card *card;
  1098. int rc;
  1099. QETH_DBF_TEXT(TRACE, 3, "haltch");
  1100. card = CARD_FROM_CDEV(channel->ccwdev);
  1101. spin_lock_irqsave(get_ccwdev_lock(channel->ccwdev), flags);
  1102. rc = ccw_device_halt(channel->ccwdev, QETH_HALT_CHANNEL_PARM);
  1103. spin_unlock_irqrestore(get_ccwdev_lock(channel->ccwdev), flags);
  1104. if (rc)
  1105. return rc;
  1106. rc = wait_event_interruptible_timeout(card->wait_q,
  1107. channel->state == CH_STATE_HALTED, QETH_TIMEOUT);
  1108. if (rc == -ERESTARTSYS)
  1109. return rc;
  1110. if (channel->state != CH_STATE_HALTED)
  1111. return -ETIME;
  1112. return 0;
  1113. }
  1114. static int qeth_halt_channels(struct qeth_card *card)
  1115. {
  1116. int rc1 = 0, rc2 = 0, rc3 = 0;
  1117. QETH_DBF_TEXT(TRACE, 3, "haltchs");
  1118. rc1 = qeth_halt_channel(&card->read);
  1119. rc2 = qeth_halt_channel(&card->write);
  1120. rc3 = qeth_halt_channel(&card->data);
  1121. if (rc1)
  1122. return rc1;
  1123. if (rc2)
  1124. return rc2;
  1125. return rc3;
  1126. }
  1127. static int qeth_clear_channels(struct qeth_card *card)
  1128. {
  1129. int rc1 = 0, rc2 = 0, rc3 = 0;
  1130. QETH_DBF_TEXT(TRACE, 3, "clearchs");
  1131. rc1 = qeth_clear_channel(&card->read);
  1132. rc2 = qeth_clear_channel(&card->write);
  1133. rc3 = qeth_clear_channel(&card->data);
  1134. if (rc1)
  1135. return rc1;
  1136. if (rc2)
  1137. return rc2;
  1138. return rc3;
  1139. }
  1140. static int qeth_clear_halt_card(struct qeth_card *card, int halt)
  1141. {
  1142. int rc = 0;
  1143. QETH_DBF_TEXT(TRACE, 3, "clhacrd");
  1144. QETH_DBF_HEX(TRACE, 3, &card, sizeof(void *));
  1145. if (halt)
  1146. rc = qeth_halt_channels(card);
  1147. if (rc)
  1148. return rc;
  1149. return qeth_clear_channels(card);
  1150. }
  1151. int qeth_qdio_clear_card(struct qeth_card *card, int use_halt)
  1152. {
  1153. int rc = 0;
  1154. QETH_DBF_TEXT(TRACE, 3, "qdioclr");
  1155. switch (atomic_cmpxchg(&card->qdio.state, QETH_QDIO_ESTABLISHED,
  1156. QETH_QDIO_CLEANING)) {
  1157. case QETH_QDIO_ESTABLISHED:
  1158. if (card->info.type == QETH_CARD_TYPE_IQD)
  1159. rc = qdio_cleanup(CARD_DDEV(card),
  1160. QDIO_FLAG_CLEANUP_USING_HALT);
  1161. else
  1162. rc = qdio_cleanup(CARD_DDEV(card),
  1163. QDIO_FLAG_CLEANUP_USING_CLEAR);
  1164. if (rc)
  1165. QETH_DBF_TEXT_(TRACE, 3, "1err%d", rc);
  1166. atomic_set(&card->qdio.state, QETH_QDIO_ALLOCATED);
  1167. break;
  1168. case QETH_QDIO_CLEANING:
  1169. return rc;
  1170. default:
  1171. break;
  1172. }
  1173. rc = qeth_clear_halt_card(card, use_halt);
  1174. if (rc)
  1175. QETH_DBF_TEXT_(TRACE, 3, "2err%d", rc);
  1176. card->state = CARD_STATE_DOWN;
  1177. return rc;
  1178. }
  1179. EXPORT_SYMBOL_GPL(qeth_qdio_clear_card);
  1180. static int qeth_read_conf_data(struct qeth_card *card, void **buffer,
  1181. int *length)
  1182. {
  1183. struct ciw *ciw;
  1184. char *rcd_buf;
  1185. int ret;
  1186. struct qeth_channel *channel = &card->data;
  1187. unsigned long flags;
  1188. /*
  1189. * scan for RCD command in extended SenseID data
  1190. */
  1191. ciw = ccw_device_get_ciw(channel->ccwdev, CIW_TYPE_RCD);
  1192. if (!ciw || ciw->cmd == 0)
  1193. return -EOPNOTSUPP;
  1194. rcd_buf = kzalloc(ciw->count, GFP_KERNEL | GFP_DMA);
  1195. if (!rcd_buf)
  1196. return -ENOMEM;
  1197. channel->ccw.cmd_code = ciw->cmd;
  1198. channel->ccw.cda = (__u32) __pa(rcd_buf);
  1199. channel->ccw.count = ciw->count;
  1200. channel->ccw.flags = CCW_FLAG_SLI;
  1201. channel->state = CH_STATE_RCD;
  1202. spin_lock_irqsave(get_ccwdev_lock(channel->ccwdev), flags);
  1203. ret = ccw_device_start_timeout(channel->ccwdev, &channel->ccw,
  1204. QETH_RCD_PARM, LPM_ANYPATH, 0,
  1205. QETH_RCD_TIMEOUT);
  1206. spin_unlock_irqrestore(get_ccwdev_lock(channel->ccwdev), flags);
  1207. if (!ret)
  1208. wait_event(card->wait_q,
  1209. (channel->state == CH_STATE_RCD_DONE ||
  1210. channel->state == CH_STATE_DOWN));
  1211. if (channel->state == CH_STATE_DOWN)
  1212. ret = -EIO;
  1213. else
  1214. channel->state = CH_STATE_DOWN;
  1215. if (ret) {
  1216. kfree(rcd_buf);
  1217. *buffer = NULL;
  1218. *length = 0;
  1219. } else {
  1220. *length = ciw->count;
  1221. *buffer = rcd_buf;
  1222. }
  1223. return ret;
  1224. }
  1225. static int qeth_get_unitaddr(struct qeth_card *card)
  1226. {
  1227. int length;
  1228. char *prcd;
  1229. int rc;
  1230. QETH_DBF_TEXT(SETUP, 2, "getunit");
  1231. rc = qeth_read_conf_data(card, (void **) &prcd, &length);
  1232. if (rc) {
  1233. PRINT_ERR("qeth_read_conf_data for device %s returned %i\n",
  1234. CARD_DDEV_ID(card), rc);
  1235. return rc;
  1236. }
  1237. card->info.chpid = prcd[30];
  1238. card->info.unit_addr2 = prcd[31];
  1239. card->info.cula = prcd[63];
  1240. card->info.guestlan = ((prcd[0x10] == _ascebc['V']) &&
  1241. (prcd[0x11] == _ascebc['M']));
  1242. kfree(prcd);
  1243. return 0;
  1244. }
  1245. static void qeth_init_tokens(struct qeth_card *card)
  1246. {
  1247. card->token.issuer_rm_w = 0x00010103UL;
  1248. card->token.cm_filter_w = 0x00010108UL;
  1249. card->token.cm_connection_w = 0x0001010aUL;
  1250. card->token.ulp_filter_w = 0x0001010bUL;
  1251. card->token.ulp_connection_w = 0x0001010dUL;
  1252. }
  1253. static void qeth_init_func_level(struct qeth_card *card)
  1254. {
  1255. if (card->ipato.enabled) {
  1256. if (card->info.type == QETH_CARD_TYPE_IQD)
  1257. card->info.func_level =
  1258. QETH_IDX_FUNC_LEVEL_IQD_ENA_IPAT;
  1259. else
  1260. card->info.func_level =
  1261. QETH_IDX_FUNC_LEVEL_OSAE_ENA_IPAT;
  1262. } else {
  1263. if (card->info.type == QETH_CARD_TYPE_IQD)
  1264. /*FIXME:why do we have same values for dis and ena for
  1265. osae??? */
  1266. card->info.func_level =
  1267. QETH_IDX_FUNC_LEVEL_IQD_DIS_IPAT;
  1268. else
  1269. card->info.func_level =
  1270. QETH_IDX_FUNC_LEVEL_OSAE_DIS_IPAT;
  1271. }
  1272. }
  1273. static int qeth_idx_activate_get_answer(struct qeth_channel *channel,
  1274. void (*idx_reply_cb)(struct qeth_channel *,
  1275. struct qeth_cmd_buffer *))
  1276. {
  1277. struct qeth_cmd_buffer *iob;
  1278. unsigned long flags;
  1279. int rc;
  1280. struct qeth_card *card;
  1281. QETH_DBF_TEXT(SETUP, 2, "idxanswr");
  1282. card = CARD_FROM_CDEV(channel->ccwdev);
  1283. iob = qeth_get_buffer(channel);
  1284. iob->callback = idx_reply_cb;
  1285. memcpy(&channel->ccw, READ_CCW, sizeof(struct ccw1));
  1286. channel->ccw.count = QETH_BUFSIZE;
  1287. channel->ccw.cda = (__u32) __pa(iob->data);
  1288. wait_event(card->wait_q,
  1289. atomic_cmpxchg(&channel->irq_pending, 0, 1) == 0);
  1290. QETH_DBF_TEXT(SETUP, 6, "noirqpnd");
  1291. spin_lock_irqsave(get_ccwdev_lock(channel->ccwdev), flags);
  1292. rc = ccw_device_start(channel->ccwdev,
  1293. &channel->ccw, (addr_t) iob, 0, 0);
  1294. spin_unlock_irqrestore(get_ccwdev_lock(channel->ccwdev), flags);
  1295. if (rc) {
  1296. QETH_DBF_MESSAGE(2, "Error2 in activating channel rc=%d\n", rc);
  1297. QETH_DBF_TEXT_(SETUP, 2, "2err%d", rc);
  1298. atomic_set(&channel->irq_pending, 0);
  1299. wake_up(&card->wait_q);
  1300. return rc;
  1301. }
  1302. rc = wait_event_interruptible_timeout(card->wait_q,
  1303. channel->state == CH_STATE_UP, QETH_TIMEOUT);
  1304. if (rc == -ERESTARTSYS)
  1305. return rc;
  1306. if (channel->state != CH_STATE_UP) {
  1307. rc = -ETIME;
  1308. QETH_DBF_TEXT_(SETUP, 2, "3err%d", rc);
  1309. qeth_clear_cmd_buffers(channel);
  1310. } else
  1311. rc = 0;
  1312. return rc;
  1313. }
  1314. static int qeth_idx_activate_channel(struct qeth_channel *channel,
  1315. void (*idx_reply_cb)(struct qeth_channel *,
  1316. struct qeth_cmd_buffer *))
  1317. {
  1318. struct qeth_card *card;
  1319. struct qeth_cmd_buffer *iob;
  1320. unsigned long flags;
  1321. __u16 temp;
  1322. __u8 tmp;
  1323. int rc;
  1324. struct ccw_dev_id temp_devid;
  1325. card = CARD_FROM_CDEV(channel->ccwdev);
  1326. QETH_DBF_TEXT(SETUP, 2, "idxactch");
  1327. iob = qeth_get_buffer(channel);
  1328. iob->callback = idx_reply_cb;
  1329. memcpy(&channel->ccw, WRITE_CCW, sizeof(struct ccw1));
  1330. channel->ccw.count = IDX_ACTIVATE_SIZE;
  1331. channel->ccw.cda = (__u32) __pa(iob->data);
  1332. if (channel == &card->write) {
  1333. memcpy(iob->data, IDX_ACTIVATE_WRITE, IDX_ACTIVATE_SIZE);
  1334. memcpy(QETH_TRANSPORT_HEADER_SEQ_NO(iob->data),
  1335. &card->seqno.trans_hdr, QETH_SEQ_NO_LENGTH);
  1336. card->seqno.trans_hdr++;
  1337. } else {
  1338. memcpy(iob->data, IDX_ACTIVATE_READ, IDX_ACTIVATE_SIZE);
  1339. memcpy(QETH_TRANSPORT_HEADER_SEQ_NO(iob->data),
  1340. &card->seqno.trans_hdr, QETH_SEQ_NO_LENGTH);
  1341. }
  1342. tmp = ((__u8)card->info.portno) | 0x80;
  1343. memcpy(QETH_IDX_ACT_PNO(iob->data), &tmp, 1);
  1344. memcpy(QETH_IDX_ACT_ISSUER_RM_TOKEN(iob->data),
  1345. &card->token.issuer_rm_w, QETH_MPC_TOKEN_LENGTH);
  1346. memcpy(QETH_IDX_ACT_FUNC_LEVEL(iob->data),
  1347. &card->info.func_level, sizeof(__u16));
  1348. ccw_device_get_id(CARD_DDEV(card), &temp_devid);
  1349. memcpy(QETH_IDX_ACT_QDIO_DEV_CUA(iob->data), &temp_devid.devno, 2);
  1350. temp = (card->info.cula << 8) + card->info.unit_addr2;
  1351. memcpy(QETH_IDX_ACT_QDIO_DEV_REALADDR(iob->data), &temp, 2);
  1352. wait_event(card->wait_q,
  1353. atomic_cmpxchg(&channel->irq_pending, 0, 1) == 0);
  1354. QETH_DBF_TEXT(SETUP, 6, "noirqpnd");
  1355. spin_lock_irqsave(get_ccwdev_lock(channel->ccwdev), flags);
  1356. rc = ccw_device_start(channel->ccwdev,
  1357. &channel->ccw, (addr_t) iob, 0, 0);
  1358. spin_unlock_irqrestore(get_ccwdev_lock(channel->ccwdev), flags);
  1359. if (rc) {
  1360. QETH_DBF_MESSAGE(2, "Error1 in activating channel. rc=%d\n",
  1361. rc);
  1362. QETH_DBF_TEXT_(SETUP, 2, "1err%d", rc);
  1363. atomic_set(&channel->irq_pending, 0);
  1364. wake_up(&card->wait_q);
  1365. return rc;
  1366. }
  1367. rc = wait_event_interruptible_timeout(card->wait_q,
  1368. channel->state == CH_STATE_ACTIVATING, QETH_TIMEOUT);
  1369. if (rc == -ERESTARTSYS)
  1370. return rc;
  1371. if (channel->state != CH_STATE_ACTIVATING) {
  1372. PRINT_WARN("IDX activate timed out!\n");
  1373. QETH_DBF_TEXT_(SETUP, 2, "2err%d", -ETIME);
  1374. qeth_clear_cmd_buffers(channel);
  1375. return -ETIME;
  1376. }
  1377. return qeth_idx_activate_get_answer(channel, idx_reply_cb);
  1378. }
  1379. static int qeth_peer_func_level(int level)
  1380. {
  1381. if ((level & 0xff) == 8)
  1382. return (level & 0xff) + 0x400;
  1383. if (((level >> 8) & 3) == 1)
  1384. return (level & 0xff) + 0x200;
  1385. return level;
  1386. }
  1387. static void qeth_idx_write_cb(struct qeth_channel *channel,
  1388. struct qeth_cmd_buffer *iob)
  1389. {
  1390. struct qeth_card *card;
  1391. __u16 temp;
  1392. QETH_DBF_TEXT(SETUP , 2, "idxwrcb");
  1393. if (channel->state == CH_STATE_DOWN) {
  1394. channel->state = CH_STATE_ACTIVATING;
  1395. goto out;
  1396. }
  1397. card = CARD_FROM_CDEV(channel->ccwdev);
  1398. if (!(QETH_IS_IDX_ACT_POS_REPLY(iob->data))) {
  1399. if (QETH_IDX_ACT_CAUSE_CODE(iob->data) == 0x19)
  1400. PRINT_ERR("IDX_ACTIVATE on write channel device %s: "
  1401. "adapter exclusively used by another host\n",
  1402. CARD_WDEV_ID(card));
  1403. else
  1404. PRINT_ERR("IDX_ACTIVATE on write channel device %s: "
  1405. "negative reply\n", CARD_WDEV_ID(card));
  1406. goto out;
  1407. }
  1408. memcpy(&temp, QETH_IDX_ACT_FUNC_LEVEL(iob->data), 2);
  1409. if ((temp & ~0x0100) != qeth_peer_func_level(card->info.func_level)) {
  1410. PRINT_WARN("IDX_ACTIVATE on write channel device %s: "
  1411. "function level mismatch "
  1412. "(sent: 0x%x, received: 0x%x)\n",
  1413. CARD_WDEV_ID(card), card->info.func_level, temp);
  1414. goto out;
  1415. }
  1416. channel->state = CH_STATE_UP;
  1417. out:
  1418. qeth_release_buffer(channel, iob);
  1419. }
  1420. static void qeth_idx_read_cb(struct qeth_channel *channel,
  1421. struct qeth_cmd_buffer *iob)
  1422. {
  1423. struct qeth_card *card;
  1424. __u16 temp;
  1425. QETH_DBF_TEXT(SETUP , 2, "idxrdcb");
  1426. if (channel->state == CH_STATE_DOWN) {
  1427. channel->state = CH_STATE_ACTIVATING;
  1428. goto out;
  1429. }
  1430. card = CARD_FROM_CDEV(channel->ccwdev);
  1431. if (qeth_check_idx_response(iob->data))
  1432. goto out;
  1433. if (!(QETH_IS_IDX_ACT_POS_REPLY(iob->data))) {
  1434. if (QETH_IDX_ACT_CAUSE_CODE(iob->data) == 0x19)
  1435. PRINT_ERR("IDX_ACTIVATE on read channel device %s: "
  1436. "adapter exclusively used by another host\n",
  1437. CARD_RDEV_ID(card));
  1438. else
  1439. PRINT_ERR("IDX_ACTIVATE on read channel device %s: "
  1440. "negative reply\n", CARD_RDEV_ID(card));
  1441. goto out;
  1442. }
  1443. /**
  1444. * temporary fix for microcode bug
  1445. * to revert it,replace OR by AND
  1446. */
  1447. if ((!QETH_IDX_NO_PORTNAME_REQUIRED(iob->data)) ||
  1448. (card->info.type == QETH_CARD_TYPE_OSAE))
  1449. card->info.portname_required = 1;
  1450. memcpy(&temp, QETH_IDX_ACT_FUNC_LEVEL(iob->data), 2);
  1451. if (temp != qeth_peer_func_level(card->info.func_level)) {
  1452. PRINT_WARN("IDX_ACTIVATE on read channel device %s: function "
  1453. "level mismatch (sent: 0x%x, received: 0x%x)\n",
  1454. CARD_RDEV_ID(card), card->info.func_level, temp);
  1455. goto out;
  1456. }
  1457. memcpy(&card->token.issuer_rm_r,
  1458. QETH_IDX_ACT_ISSUER_RM_TOKEN(iob->data),
  1459. QETH_MPC_TOKEN_LENGTH);
  1460. memcpy(&card->info.mcl_level[0],
  1461. QETH_IDX_REPLY_LEVEL(iob->data), QETH_MCL_LENGTH);
  1462. channel->state = CH_STATE_UP;
  1463. out:
  1464. qeth_release_buffer(channel, iob);
  1465. }
  1466. void qeth_prepare_control_data(struct qeth_card *card, int len,
  1467. struct qeth_cmd_buffer *iob)
  1468. {
  1469. qeth_setup_ccw(&card->write, iob->data, len);
  1470. iob->callback = qeth_release_buffer;
  1471. memcpy(QETH_TRANSPORT_HEADER_SEQ_NO(iob->data),
  1472. &card->seqno.trans_hdr, QETH_SEQ_NO_LENGTH);
  1473. card->seqno.trans_hdr++;
  1474. memcpy(QETH_PDU_HEADER_SEQ_NO(iob->data),
  1475. &card->seqno.pdu_hdr, QETH_SEQ_NO_LENGTH);
  1476. card->seqno.pdu_hdr++;
  1477. memcpy(QETH_PDU_HEADER_ACK_SEQ_NO(iob->data),
  1478. &card->seqno.pdu_hdr_ack, QETH_SEQ_NO_LENGTH);
  1479. QETH_DBF_HEX(CTRL, 2, iob->data, QETH_DBF_CTRL_LEN);
  1480. }
  1481. EXPORT_SYMBOL_GPL(qeth_prepare_control_data);
  1482. int qeth_send_control_data(struct qeth_card *card, int len,
  1483. struct qeth_cmd_buffer *iob,
  1484. int (*reply_cb)(struct qeth_card *, struct qeth_reply *,
  1485. unsigned long),
  1486. void *reply_param)
  1487. {
  1488. int rc;
  1489. unsigned long flags;
  1490. struct qeth_reply *reply = NULL;
  1491. unsigned long timeout;
  1492. QETH_DBF_TEXT(TRACE, 2, "sendctl");
  1493. reply = qeth_alloc_reply(card);
  1494. if (!reply) {
  1495. return -ENOMEM;
  1496. }
  1497. reply->callback = reply_cb;
  1498. reply->param = reply_param;
  1499. if (card->state == CARD_STATE_DOWN)
  1500. reply->seqno = QETH_IDX_COMMAND_SEQNO;
  1501. else
  1502. reply->seqno = card->seqno.ipa++;
  1503. init_waitqueue_head(&reply->wait_q);
  1504. spin_lock_irqsave(&card->lock, flags);
  1505. list_add_tail(&reply->list, &card->cmd_waiter_list);
  1506. spin_unlock_irqrestore(&card->lock, flags);
  1507. QETH_DBF_HEX(CTRL, 2, iob->data, QETH_DBF_CTRL_LEN);
  1508. while (atomic_cmpxchg(&card->write.irq_pending, 0, 1)) ;
  1509. qeth_prepare_control_data(card, len, iob);
  1510. if (IS_IPA(iob->data))
  1511. timeout = jiffies + QETH_IPA_TIMEOUT;
  1512. else
  1513. timeout = jiffies + QETH_TIMEOUT;
  1514. QETH_DBF_TEXT(TRACE, 6, "noirqpnd");
  1515. spin_lock_irqsave(get_ccwdev_lock(card->write.ccwdev), flags);
  1516. rc = ccw_device_start(card->write.ccwdev, &card->write.ccw,
  1517. (addr_t) iob, 0, 0);
  1518. spin_unlock_irqrestore(get_ccwdev_lock(card->write.ccwdev), flags);
  1519. if (rc) {
  1520. PRINT_WARN("qeth_send_control_data: "
  1521. "ccw_device_start rc = %i\n", rc);
  1522. QETH_DBF_TEXT_(TRACE, 2, " err%d", rc);
  1523. spin_lock_irqsave(&card->lock, flags);
  1524. list_del_init(&reply->list);
  1525. qeth_put_reply(reply);
  1526. spin_unlock_irqrestore(&card->lock, flags);
  1527. qeth_release_buffer(iob->channel, iob);
  1528. atomic_set(&card->write.irq_pending, 0);
  1529. wake_up(&card->wait_q);
  1530. return rc;
  1531. }
  1532. while (!atomic_read(&reply->received)) {
  1533. if (time_after(jiffies, timeout)) {
  1534. spin_lock_irqsave(&reply->card->lock, flags);
  1535. list_del_init(&reply->list);
  1536. spin_unlock_irqrestore(&reply->card->lock, flags);
  1537. reply->rc = -ETIME;
  1538. atomic_inc(&reply->received);
  1539. wake_up(&reply->wait_q);
  1540. }
  1541. cpu_relax();
  1542. };
  1543. rc = reply->rc;
  1544. qeth_put_reply(reply);
  1545. return rc;
  1546. }
  1547. EXPORT_SYMBOL_GPL(qeth_send_control_data);
  1548. static int qeth_cm_enable_cb(struct qeth_card *card, struct qeth_reply *reply,
  1549. unsigned long data)
  1550. {
  1551. struct qeth_cmd_buffer *iob;
  1552. QETH_DBF_TEXT(SETUP, 2, "cmenblcb");
  1553. iob = (struct qeth_cmd_buffer *) data;
  1554. memcpy(&card->token.cm_filter_r,
  1555. QETH_CM_ENABLE_RESP_FILTER_TOKEN(iob->data),
  1556. QETH_MPC_TOKEN_LENGTH);
  1557. QETH_DBF_TEXT_(SETUP, 2, " rc%d", iob->rc);
  1558. return 0;
  1559. }
  1560. static int qeth_cm_enable(struct qeth_card *card)
  1561. {
  1562. int rc;
  1563. struct qeth_cmd_buffer *iob;
  1564. QETH_DBF_TEXT(SETUP, 2, "cmenable");
  1565. iob = qeth_wait_for_buffer(&card->write);
  1566. memcpy(iob->data, CM_ENABLE, CM_ENABLE_SIZE);
  1567. memcpy(QETH_CM_ENABLE_ISSUER_RM_TOKEN(iob->data),
  1568. &card->token.issuer_rm_r, QETH_MPC_TOKEN_LENGTH);
  1569. memcpy(QETH_CM_ENABLE_FILTER_TOKEN(iob->data),
  1570. &card->token.cm_filter_w, QETH_MPC_TOKEN_LENGTH);
  1571. rc = qeth_send_control_data(card, CM_ENABLE_SIZE, iob,
  1572. qeth_cm_enable_cb, NULL);
  1573. return rc;
  1574. }
  1575. static int qeth_cm_setup_cb(struct qeth_card *card, struct qeth_reply *reply,
  1576. unsigned long data)
  1577. {
  1578. struct qeth_cmd_buffer *iob;
  1579. QETH_DBF_TEXT(SETUP, 2, "cmsetpcb");
  1580. iob = (struct qeth_cmd_buffer *) data;
  1581. memcpy(&card->token.cm_connection_r,
  1582. QETH_CM_SETUP_RESP_DEST_ADDR(iob->data),
  1583. QETH_MPC_TOKEN_LENGTH);
  1584. QETH_DBF_TEXT_(SETUP, 2, " rc%d", iob->rc);
  1585. return 0;
  1586. }
  1587. static int qeth_cm_setup(struct qeth_card *card)
  1588. {
  1589. int rc;
  1590. struct qeth_cmd_buffer *iob;
  1591. QETH_DBF_TEXT(SETUP, 2, "cmsetup");
  1592. iob = qeth_wait_for_buffer(&card->write);
  1593. memcpy(iob->data, CM_SETUP, CM_SETUP_SIZE);
  1594. memcpy(QETH_CM_SETUP_DEST_ADDR(iob->data),
  1595. &card->token.issuer_rm_r, QETH_MPC_TOKEN_LENGTH);
  1596. memcpy(QETH_CM_SETUP_CONNECTION_TOKEN(iob->data),
  1597. &card->token.cm_connection_w, QETH_MPC_TOKEN_LENGTH);
  1598. memcpy(QETH_CM_SETUP_FILTER_TOKEN(iob->data),
  1599. &card->token.cm_filter_r, QETH_MPC_TOKEN_LENGTH);
  1600. rc = qeth_send_control_data(card, CM_SETUP_SIZE, iob,
  1601. qeth_cm_setup_cb, NULL);
  1602. return rc;
  1603. }
  1604. static inline int qeth_get_initial_mtu_for_card(struct qeth_card *card)
  1605. {
  1606. switch (card->info.type) {
  1607. case QETH_CARD_TYPE_UNKNOWN:
  1608. return 1500;
  1609. case QETH_CARD_TYPE_IQD:
  1610. return card->info.max_mtu;
  1611. case QETH_CARD_TYPE_OSAE:
  1612. switch (card->info.link_type) {
  1613. case QETH_LINK_TYPE_HSTR:
  1614. case QETH_LINK_TYPE_LANE_TR:
  1615. return 2000;
  1616. default:
  1617. return 1492;
  1618. }
  1619. default:
  1620. return 1500;
  1621. }
  1622. }
  1623. static inline int qeth_get_max_mtu_for_card(int cardtype)
  1624. {
  1625. switch (cardtype) {
  1626. case QETH_CARD_TYPE_UNKNOWN:
  1627. case QETH_CARD_TYPE_OSAE:
  1628. case QETH_CARD_TYPE_OSN:
  1629. return 61440;
  1630. case QETH_CARD_TYPE_IQD:
  1631. return 57344;
  1632. default:
  1633. return 1500;
  1634. }
  1635. }
  1636. static inline int qeth_get_mtu_out_of_mpc(int cardtype)
  1637. {
  1638. switch (cardtype) {
  1639. case QETH_CARD_TYPE_IQD:
  1640. return 1;
  1641. default:
  1642. return 0;
  1643. }
  1644. }
  1645. static inline int qeth_get_mtu_outof_framesize(int framesize)
  1646. {
  1647. switch (framesize) {
  1648. case 0x4000:
  1649. return 8192;
  1650. case 0x6000:
  1651. return 16384;
  1652. case 0xa000:
  1653. return 32768;
  1654. case 0xffff:
  1655. return 57344;
  1656. default:
  1657. return 0;
  1658. }
  1659. }
  1660. static inline int qeth_mtu_is_valid(struct qeth_card *card, int mtu)
  1661. {
  1662. switch (card->info.type) {
  1663. case QETH_CARD_TYPE_OSAE:
  1664. return ((mtu >= 576) && (mtu <= 61440));
  1665. case QETH_CARD_TYPE_IQD:
  1666. return ((mtu >= 576) &&
  1667. (mtu <= card->info.max_mtu + 4096 - 32));
  1668. case QETH_CARD_TYPE_OSN:
  1669. case QETH_CARD_TYPE_UNKNOWN:
  1670. default:
  1671. return 1;
  1672. }
  1673. }
  1674. static int qeth_ulp_enable_cb(struct qeth_card *card, struct qeth_reply *reply,
  1675. unsigned long data)
  1676. {
  1677. __u16 mtu, framesize;
  1678. __u16 len;
  1679. __u8 link_type;
  1680. struct qeth_cmd_buffer *iob;
  1681. QETH_DBF_TEXT(SETUP, 2, "ulpenacb");
  1682. iob = (struct qeth_cmd_buffer *) data;
  1683. memcpy(&card->token.ulp_filter_r,
  1684. QETH_ULP_ENABLE_RESP_FILTER_TOKEN(iob->data),
  1685. QETH_MPC_TOKEN_LENGTH);
  1686. if (qeth_get_mtu_out_of_mpc(card->info.type)) {
  1687. memcpy(&framesize, QETH_ULP_ENABLE_RESP_MAX_MTU(iob->data), 2);
  1688. mtu = qeth_get_mtu_outof_framesize(framesize);
  1689. if (!mtu) {
  1690. iob->rc = -EINVAL;
  1691. QETH_DBF_TEXT_(SETUP, 2, " rc%d", iob->rc);
  1692. return 0;
  1693. }
  1694. card->info.max_mtu = mtu;
  1695. card->info.initial_mtu = mtu;
  1696. card->qdio.in_buf_size = mtu + 2 * PAGE_SIZE;
  1697. } else {
  1698. card->info.initial_mtu = qeth_get_initial_mtu_for_card(card);
  1699. card->info.max_mtu = qeth_get_max_mtu_for_card(card->info.type);
  1700. card->qdio.in_buf_size = QETH_IN_BUF_SIZE_DEFAULT;
  1701. }
  1702. memcpy(&len, QETH_ULP_ENABLE_RESP_DIFINFO_LEN(iob->data), 2);
  1703. if (len >= QETH_MPC_DIFINFO_LEN_INDICATES_LINK_TYPE) {
  1704. memcpy(&link_type,
  1705. QETH_ULP_ENABLE_RESP_LINK_TYPE(iob->data), 1);
  1706. card->info.link_type = link_type;
  1707. } else
  1708. card->info.link_type = 0;
  1709. QETH_DBF_TEXT_(SETUP, 2, " rc%d", iob->rc);
  1710. return 0;
  1711. }
  1712. static int qeth_ulp_enable(struct qeth_card *card)
  1713. {
  1714. int rc;
  1715. char prot_type;
  1716. struct qeth_cmd_buffer *iob;
  1717. /*FIXME: trace view callbacks*/
  1718. QETH_DBF_TEXT(SETUP, 2, "ulpenabl");
  1719. iob = qeth_wait_for_buffer(&card->write);
  1720. memcpy(iob->data, ULP_ENABLE, ULP_ENABLE_SIZE);
  1721. *(QETH_ULP_ENABLE_LINKNUM(iob->data)) =
  1722. (__u8) card->info.portno;
  1723. if (card->options.layer2)
  1724. if (card->info.type == QETH_CARD_TYPE_OSN)
  1725. prot_type = QETH_PROT_OSN2;
  1726. else
  1727. prot_type = QETH_PROT_LAYER2;
  1728. else
  1729. prot_type = QETH_PROT_TCPIP;
  1730. memcpy(QETH_ULP_ENABLE_PROT_TYPE(iob->data), &prot_type, 1);
  1731. memcpy(QETH_ULP_ENABLE_DEST_ADDR(iob->data),
  1732. &card->token.cm_connection_r, QETH_MPC_TOKEN_LENGTH);
  1733. memcpy(QETH_ULP_ENABLE_FILTER_TOKEN(iob->data),
  1734. &card->token.ulp_filter_w, QETH_MPC_TOKEN_LENGTH);
  1735. memcpy(QETH_ULP_ENABLE_PORTNAME_AND_LL(iob->data),
  1736. card->info.portname, 9);
  1737. rc = qeth_send_control_data(card, ULP_ENABLE_SIZE, iob,
  1738. qeth_ulp_enable_cb, NULL);
  1739. return rc;
  1740. }
  1741. static int qeth_ulp_setup_cb(struct qeth_card *card, struct qeth_reply *reply,
  1742. unsigned long data)
  1743. {
  1744. struct qeth_cmd_buffer *iob;
  1745. QETH_DBF_TEXT(SETUP, 2, "ulpstpcb");
  1746. iob = (struct qeth_cmd_buffer *) data;
  1747. memcpy(&card->token.ulp_connection_r,
  1748. QETH_ULP_SETUP_RESP_CONNECTION_TOKEN(iob->data),
  1749. QETH_MPC_TOKEN_LENGTH);
  1750. QETH_DBF_TEXT_(SETUP, 2, " rc%d", iob->rc);
  1751. return 0;
  1752. }
  1753. static int qeth_ulp_setup(struct qeth_card *card)
  1754. {
  1755. int rc;
  1756. __u16 temp;
  1757. struct qeth_cmd_buffer *iob;
  1758. struct ccw_dev_id dev_id;
  1759. QETH_DBF_TEXT(SETUP, 2, "ulpsetup");
  1760. iob = qeth_wait_for_buffer(&card->write);
  1761. memcpy(iob->data, ULP_SETUP, ULP_SETUP_SIZE);
  1762. memcpy(QETH_ULP_SETUP_DEST_ADDR(iob->data),
  1763. &card->token.cm_connection_r, QETH_MPC_TOKEN_LENGTH);
  1764. memcpy(QETH_ULP_SETUP_CONNECTION_TOKEN(iob->data),
  1765. &card->token.ulp_connection_w, QETH_MPC_TOKEN_LENGTH);
  1766. memcpy(QETH_ULP_SETUP_FILTER_TOKEN(iob->data),
  1767. &card->token.ulp_filter_r, QETH_MPC_TOKEN_LENGTH);
  1768. ccw_device_get_id(CARD_DDEV(card), &dev_id);
  1769. memcpy(QETH_ULP_SETUP_CUA(iob->data), &dev_id.devno, 2);
  1770. temp = (card->info.cula << 8) + card->info.unit_addr2;
  1771. memcpy(QETH_ULP_SETUP_REAL_DEVADDR(iob->data), &temp, 2);
  1772. rc = qeth_send_control_data(card, ULP_SETUP_SIZE, iob,
  1773. qeth_ulp_setup_cb, NULL);
  1774. return rc;
  1775. }
  1776. static int qeth_alloc_qdio_buffers(struct qeth_card *card)
  1777. {
  1778. int i, j;
  1779. QETH_DBF_TEXT(SETUP, 2, "allcqdbf");
  1780. if (atomic_cmpxchg(&card->qdio.state, QETH_QDIO_UNINITIALIZED,
  1781. QETH_QDIO_ALLOCATED) != QETH_QDIO_UNINITIALIZED)
  1782. return 0;
  1783. card->qdio.in_q = kmalloc(sizeof(struct qeth_qdio_q),
  1784. GFP_KERNEL);
  1785. if (!card->qdio.in_q)
  1786. goto out_nomem;
  1787. QETH_DBF_TEXT(SETUP, 2, "inq");
  1788. QETH_DBF_HEX(SETUP, 2, &card->qdio.in_q, sizeof(void *));
  1789. memset(card->qdio.in_q, 0, sizeof(struct qeth_qdio_q));
  1790. /* give inbound qeth_qdio_buffers their qdio_buffers */
  1791. for (i = 0; i < QDIO_MAX_BUFFERS_PER_Q; ++i)
  1792. card->qdio.in_q->bufs[i].buffer =
  1793. &card->qdio.in_q->qdio_bufs[i];
  1794. /* inbound buffer pool */
  1795. if (qeth_alloc_buffer_pool(card))
  1796. goto out_freeinq;
  1797. /* outbound */
  1798. card->qdio.out_qs =
  1799. kmalloc(card->qdio.no_out_queues *
  1800. sizeof(struct qeth_qdio_out_q *), GFP_KERNEL);
  1801. if (!card->qdio.out_qs)
  1802. goto out_freepool;
  1803. for (i = 0; i < card->qdio.no_out_queues; ++i) {
  1804. card->qdio.out_qs[i] = kmalloc(sizeof(struct qeth_qdio_out_q),
  1805. GFP_KERNEL);
  1806. if (!card->qdio.out_qs[i])
  1807. goto out_freeoutq;
  1808. QETH_DBF_TEXT_(SETUP, 2, "outq %i", i);
  1809. QETH_DBF_HEX(SETUP, 2, &card->qdio.out_qs[i], sizeof(void *));
  1810. memset(card->qdio.out_qs[i], 0, sizeof(struct qeth_qdio_out_q));
  1811. card->qdio.out_qs[i]->queue_no = i;
  1812. /* give outbound qeth_qdio_buffers their qdio_buffers */
  1813. for (j = 0; j < QDIO_MAX_BUFFERS_PER_Q; ++j) {
  1814. card->qdio.out_qs[i]->bufs[j].buffer =
  1815. &card->qdio.out_qs[i]->qdio_bufs[j];
  1816. skb_queue_head_init(&card->qdio.out_qs[i]->bufs[j].
  1817. skb_list);
  1818. lockdep_set_class(
  1819. &card->qdio.out_qs[i]->bufs[j].skb_list.lock,
  1820. &qdio_out_skb_queue_key);
  1821. INIT_LIST_HEAD(&card->qdio.out_qs[i]->bufs[j].ctx_list);
  1822. }
  1823. }
  1824. return 0;
  1825. out_freeoutq:
  1826. while (i > 0)
  1827. kfree(card->qdio.out_qs[--i]);
  1828. kfree(card->qdio.out_qs);
  1829. card->qdio.out_qs = NULL;
  1830. out_freepool:
  1831. qeth_free_buffer_pool(card);
  1832. out_freeinq:
  1833. kfree(card->qdio.in_q);
  1834. card->qdio.in_q = NULL;
  1835. out_nomem:
  1836. atomic_set(&card->qdio.state, QETH_QDIO_UNINITIALIZED);
  1837. return -ENOMEM;
  1838. }
  1839. static void qeth_create_qib_param_field(struct qeth_card *card,
  1840. char *param_field)
  1841. {
  1842. param_field[0] = _ascebc['P'];
  1843. param_field[1] = _ascebc['C'];
  1844. param_field[2] = _ascebc['I'];
  1845. param_field[3] = _ascebc['T'];
  1846. *((unsigned int *) (&param_field[4])) = QETH_PCI_THRESHOLD_A(card);
  1847. *((unsigned int *) (&param_field[8])) = QETH_PCI_THRESHOLD_B(card);
  1848. *((unsigned int *) (&param_field[12])) = QETH_PCI_TIMER_VALUE(card);
  1849. }
  1850. static void qeth_create_qib_param_field_blkt(struct qeth_card *card,
  1851. char *param_field)
  1852. {
  1853. param_field[16] = _ascebc['B'];
  1854. param_field[17] = _ascebc['L'];
  1855. param_field[18] = _ascebc['K'];
  1856. param_field[19] = _ascebc['T'];
  1857. *((unsigned int *) (&param_field[20])) = card->info.blkt.time_total;
  1858. *((unsigned int *) (&param_field[24])) = card->info.blkt.inter_packet;
  1859. *((unsigned int *) (&param_field[28])) =
  1860. card->info.blkt.inter_packet_jumbo;
  1861. }
  1862. static int qeth_qdio_activate(struct qeth_card *card)
  1863. {
  1864. QETH_DBF_TEXT(SETUP, 3, "qdioact");
  1865. return qdio_activate(CARD_DDEV(card));
  1866. }
  1867. static int qeth_dm_act(struct qeth_card *card)
  1868. {
  1869. int rc;
  1870. struct qeth_cmd_buffer *iob;
  1871. QETH_DBF_TEXT(SETUP, 2, "dmact");
  1872. iob = qeth_wait_for_buffer(&card->write);
  1873. memcpy(iob->data, DM_ACT, DM_ACT_SIZE);
  1874. memcpy(QETH_DM_ACT_DEST_ADDR(iob->data),
  1875. &card->token.cm_connection_r, QETH_MPC_TOKEN_LENGTH);
  1876. memcpy(QETH_DM_ACT_CONNECTION_TOKEN(iob->data),
  1877. &card->token.ulp_connection_r, QETH_MPC_TOKEN_LENGTH);
  1878. rc = qeth_send_control_data(card, DM_ACT_SIZE, iob, NULL, NULL);
  1879. return rc;
  1880. }
  1881. static int qeth_mpc_initialize(struct qeth_card *card)
  1882. {
  1883. int rc;
  1884. QETH_DBF_TEXT(SETUP, 2, "mpcinit");
  1885. rc = qeth_issue_next_read(card);
  1886. if (rc) {
  1887. QETH_DBF_TEXT_(SETUP, 2, "1err%d", rc);
  1888. return rc;
  1889. }
  1890. rc = qeth_cm_enable(card);
  1891. if (rc) {
  1892. QETH_DBF_TEXT_(SETUP, 2, "2err%d", rc);
  1893. goto out_qdio;
  1894. }
  1895. rc = qeth_cm_setup(card);
  1896. if (rc) {
  1897. QETH_DBF_TEXT_(SETUP, 2, "3err%d", rc);
  1898. goto out_qdio;
  1899. }
  1900. rc = qeth_ulp_enable(card);
  1901. if (rc) {
  1902. QETH_DBF_TEXT_(SETUP, 2, "4err%d", rc);
  1903. goto out_qdio;
  1904. }
  1905. rc = qeth_ulp_setup(card);
  1906. if (rc) {
  1907. QETH_DBF_TEXT_(SETUP, 2, "5err%d", rc);
  1908. goto out_qdio;
  1909. }
  1910. rc = qeth_alloc_qdio_buffers(card);
  1911. if (rc) {
  1912. QETH_DBF_TEXT_(SETUP, 2, "5err%d", rc);
  1913. goto out_qdio;
  1914. }
  1915. rc = qeth_qdio_establish(card);
  1916. if (rc) {
  1917. QETH_DBF_TEXT_(SETUP, 2, "6err%d", rc);
  1918. qeth_free_qdio_buffers(card);
  1919. goto out_qdio;
  1920. }
  1921. rc = qeth_qdio_activate(card);
  1922. if (rc) {
  1923. QETH_DBF_TEXT_(SETUP, 2, "7err%d", rc);
  1924. goto out_qdio;
  1925. }
  1926. rc = qeth_dm_act(card);
  1927. if (rc) {
  1928. QETH_DBF_TEXT_(SETUP, 2, "8err%d", rc);
  1929. goto out_qdio;
  1930. }
  1931. return 0;
  1932. out_qdio:
  1933. qeth_qdio_clear_card(card, card->info.type != QETH_CARD_TYPE_IQD);
  1934. return rc;
  1935. }
  1936. static void qeth_print_status_with_portname(struct qeth_card *card)
  1937. {
  1938. char dbf_text[15];
  1939. int i;
  1940. sprintf(dbf_text, "%s", card->info.portname + 1);
  1941. for (i = 0; i < 8; i++)
  1942. dbf_text[i] =
  1943. (char) _ebcasc[(__u8) dbf_text[i]];
  1944. dbf_text[8] = 0;
  1945. PRINT_INFO("Device %s/%s/%s is a%s card%s%s%s\n"
  1946. "with link type %s (portname: %s)\n",
  1947. CARD_RDEV_ID(card),
  1948. CARD_WDEV_ID(card),
  1949. CARD_DDEV_ID(card),
  1950. qeth_get_cardname(card),
  1951. (card->info.mcl_level[0]) ? " (level: " : "",
  1952. (card->info.mcl_level[0]) ? card->info.mcl_level : "",
  1953. (card->info.mcl_level[0]) ? ")" : "",
  1954. qeth_get_cardname_short(card),
  1955. dbf_text);
  1956. }
  1957. static void qeth_print_status_no_portname(struct qeth_card *card)
  1958. {
  1959. if (card->info.portname[0])
  1960. PRINT_INFO("Device %s/%s/%s is a%s "
  1961. "card%s%s%s\nwith link type %s "
  1962. "(no portname needed by interface).\n",
  1963. CARD_RDEV_ID(card),
  1964. CARD_WDEV_ID(card),
  1965. CARD_DDEV_ID(card),
  1966. qeth_get_cardname(card),
  1967. (card->info.mcl_level[0]) ? " (level: " : "",
  1968. (card->info.mcl_level[0]) ? card->info.mcl_level : "",
  1969. (card->info.mcl_level[0]) ? ")" : "",
  1970. qeth_get_cardname_short(card));
  1971. else
  1972. PRINT_INFO("Device %s/%s/%s is a%s "
  1973. "card%s%s%s\nwith link type %s.\n",
  1974. CARD_RDEV_ID(card),
  1975. CARD_WDEV_ID(card),
  1976. CARD_DDEV_ID(card),
  1977. qeth_get_cardname(card),
  1978. (card->info.mcl_level[0]) ? " (level: " : "",
  1979. (card->info.mcl_level[0]) ? card->info.mcl_level : "",
  1980. (card->info.mcl_level[0]) ? ")" : "",
  1981. qeth_get_cardname_short(card));
  1982. }
  1983. void qeth_print_status_message(struct qeth_card *card)
  1984. {
  1985. switch (card->info.type) {
  1986. case QETH_CARD_TYPE_OSAE:
  1987. /* VM will use a non-zero first character
  1988. * to indicate a HiperSockets like reporting
  1989. * of the level OSA sets the first character to zero
  1990. * */
  1991. if (!card->info.mcl_level[0]) {
  1992. sprintf(card->info.mcl_level, "%02x%02x",
  1993. card->info.mcl_level[2],
  1994. card->info.mcl_level[3]);
  1995. card->info.mcl_level[QETH_MCL_LENGTH] = 0;
  1996. break;
  1997. }
  1998. /* fallthrough */
  1999. case QETH_CARD_TYPE_IQD:
  2000. if (card->info.guestlan) {
  2001. card->info.mcl_level[0] = (char) _ebcasc[(__u8)
  2002. card->info.mcl_level[0]];
  2003. card->info.mcl_level[1] = (char) _ebcasc[(__u8)
  2004. card->info.mcl_level[1]];
  2005. card->info.mcl_level[2] = (char) _ebcasc[(__u8)
  2006. card->info.mcl_level[2]];
  2007. card->info.mcl_level[3] = (char) _ebcasc[(__u8)
  2008. card->info.mcl_level[3]];
  2009. card->info.mcl_level[QETH_MCL_LENGTH] = 0;
  2010. }
  2011. break;
  2012. default:
  2013. memset(&card->info.mcl_level[0], 0, QETH_MCL_LENGTH + 1);
  2014. }
  2015. if (card->info.portname_required)
  2016. qeth_print_status_with_portname(card);
  2017. else
  2018. qeth_print_status_no_portname(card);
  2019. }
  2020. EXPORT_SYMBOL_GPL(qeth_print_status_message);
  2021. static void qeth_initialize_working_pool_list(struct qeth_card *card)
  2022. {
  2023. struct qeth_buffer_pool_entry *entry;
  2024. QETH_DBF_TEXT(TRACE, 5, "inwrklst");
  2025. list_for_each_entry(entry,
  2026. &card->qdio.init_pool.entry_list, init_list) {
  2027. qeth_put_buffer_pool_entry(card, entry);
  2028. }
  2029. }
  2030. static inline struct qeth_buffer_pool_entry *qeth_find_free_buffer_pool_entry(
  2031. struct qeth_card *card)
  2032. {
  2033. struct list_head *plh;
  2034. struct qeth_buffer_pool_entry *entry;
  2035. int i, free;
  2036. struct page *page;
  2037. if (list_empty(&card->qdio.in_buf_pool.entry_list))
  2038. return NULL;
  2039. list_for_each(plh, &card->qdio.in_buf_pool.entry_list) {
  2040. entry = list_entry(plh, struct qeth_buffer_pool_entry, list);
  2041. free = 1;
  2042. for (i = 0; i < QETH_MAX_BUFFER_ELEMENTS(card); ++i) {
  2043. if (page_count(virt_to_page(entry->elements[i])) > 1) {
  2044. free = 0;
  2045. break;
  2046. }
  2047. }
  2048. if (free) {
  2049. list_del_init(&entry->list);
  2050. return entry;
  2051. }
  2052. }
  2053. /* no free buffer in pool so take first one and swap pages */
  2054. entry = list_entry(card->qdio.in_buf_pool.entry_list.next,
  2055. struct qeth_buffer_pool_entry, list);
  2056. for (i = 0; i < QETH_MAX_BUFFER_ELEMENTS(card); ++i) {
  2057. if (page_count(virt_to_page(entry->elements[i])) > 1) {
  2058. page = alloc_page(GFP_ATOMIC);
  2059. if (!page) {
  2060. return NULL;
  2061. } else {
  2062. free_page((unsigned long)entry->elements[i]);
  2063. entry->elements[i] = page_address(page);
  2064. if (card->options.performance_stats)
  2065. card->perf_stats.sg_alloc_page_rx++;
  2066. }
  2067. }
  2068. }
  2069. list_del_init(&entry->list);
  2070. return entry;
  2071. }
  2072. static int qeth_init_input_buffer(struct qeth_card *card,
  2073. struct qeth_qdio_buffer *buf)
  2074. {
  2075. struct qeth_buffer_pool_entry *pool_entry;
  2076. int i;
  2077. pool_entry = qeth_find_free_buffer_pool_entry(card);
  2078. if (!pool_entry)
  2079. return 1;
  2080. /*
  2081. * since the buffer is accessed only from the input_tasklet
  2082. * there shouldn't be a need to synchronize; also, since we use
  2083. * the QETH_IN_BUF_REQUEUE_THRESHOLD we should never run out off
  2084. * buffers
  2085. */
  2086. BUG_ON(!pool_entry);
  2087. buf->pool_entry = pool_entry;
  2088. for (i = 0; i < QETH_MAX_BUFFER_ELEMENTS(card); ++i) {
  2089. buf->buffer->element[i].length = PAGE_SIZE;
  2090. buf->buffer->element[i].addr = pool_entry->elements[i];
  2091. if (i == QETH_MAX_BUFFER_ELEMENTS(card) - 1)
  2092. buf->buffer->element[i].flags = SBAL_FLAGS_LAST_ENTRY;
  2093. else
  2094. buf->buffer->element[i].flags = 0;
  2095. }
  2096. return 0;
  2097. }
  2098. int qeth_init_qdio_queues(struct qeth_card *card)
  2099. {
  2100. int i, j;
  2101. int rc;
  2102. QETH_DBF_TEXT(SETUP, 2, "initqdqs");
  2103. /* inbound queue */
  2104. memset(card->qdio.in_q->qdio_bufs, 0,
  2105. QDIO_MAX_BUFFERS_PER_Q * sizeof(struct qdio_buffer));
  2106. qeth_initialize_working_pool_list(card);
  2107. /*give only as many buffers to hardware as we have buffer pool entries*/
  2108. for (i = 0; i < card->qdio.in_buf_pool.buf_count - 1; ++i)
  2109. qeth_init_input_buffer(card, &card->qdio.in_q->bufs[i]);
  2110. card->qdio.in_q->next_buf_to_init =
  2111. card->qdio.in_buf_pool.buf_count - 1;
  2112. rc = do_QDIO(CARD_DDEV(card), QDIO_FLAG_SYNC_INPUT, 0, 0,
  2113. card->qdio.in_buf_pool.buf_count - 1);
  2114. if (rc) {
  2115. QETH_DBF_TEXT_(SETUP, 2, "1err%d", rc);
  2116. return rc;
  2117. }
  2118. /* outbound queue */
  2119. for (i = 0; i < card->qdio.no_out_queues; ++i) {
  2120. memset(card->qdio.out_qs[i]->qdio_bufs, 0,
  2121. QDIO_MAX_BUFFERS_PER_Q * sizeof(struct qdio_buffer));
  2122. for (j = 0; j < QDIO_MAX_BUFFERS_PER_Q; ++j) {
  2123. qeth_clear_output_buffer(card->qdio.out_qs[i],
  2124. &card->qdio.out_qs[i]->bufs[j]);
  2125. }
  2126. card->qdio.out_qs[i]->card = card;
  2127. card->qdio.out_qs[i]->next_buf_to_fill = 0;
  2128. card->qdio.out_qs[i]->do_pack = 0;
  2129. atomic_set(&card->qdio.out_qs[i]->used_buffers, 0);
  2130. atomic_set(&card->qdio.out_qs[i]->set_pci_flags_count, 0);
  2131. atomic_set(&card->qdio.out_qs[i]->state,
  2132. QETH_OUT_Q_UNLOCKED);
  2133. }
  2134. return 0;
  2135. }
  2136. EXPORT_SYMBOL_GPL(qeth_init_qdio_queues);
  2137. static inline __u8 qeth_get_ipa_adp_type(enum qeth_link_types link_type)
  2138. {
  2139. switch (link_type) {
  2140. case QETH_LINK_TYPE_HSTR:
  2141. return 2;
  2142. default:
  2143. return 1;
  2144. }
  2145. }
  2146. static void qeth_fill_ipacmd_header(struct qeth_card *card,
  2147. struct qeth_ipa_cmd *cmd, __u8 command,
  2148. enum qeth_prot_versions prot)
  2149. {
  2150. memset(cmd, 0, sizeof(struct qeth_ipa_cmd));
  2151. cmd->hdr.command = command;
  2152. cmd->hdr.initiator = IPA_CMD_INITIATOR_HOST;
  2153. cmd->hdr.seqno = card->seqno.ipa;
  2154. cmd->hdr.adapter_type = qeth_get_ipa_adp_type(card->info.link_type);
  2155. cmd->hdr.rel_adapter_no = (__u8) card->info.portno;
  2156. if (card->options.layer2)
  2157. cmd->hdr.prim_version_no = 2;
  2158. else
  2159. cmd->hdr.prim_version_no = 1;
  2160. cmd->hdr.param_count = 1;
  2161. cmd->hdr.prot_version = prot;
  2162. cmd->hdr.ipa_supported = 0;
  2163. cmd->hdr.ipa_enabled = 0;
  2164. }
  2165. struct qeth_cmd_buffer *qeth_get_ipacmd_buffer(struct qeth_card *card,
  2166. enum qeth_ipa_cmds ipacmd, enum qeth_prot_versions prot)
  2167. {
  2168. struct qeth_cmd_buffer *iob;
  2169. struct qeth_ipa_cmd *cmd;
  2170. iob = qeth_wait_for_buffer(&card->write);
  2171. cmd = (struct qeth_ipa_cmd *)(iob->data+IPA_PDU_HEADER_SIZE);
  2172. qeth_fill_ipacmd_header(card, cmd, ipacmd, prot);
  2173. return iob;
  2174. }
  2175. EXPORT_SYMBOL_GPL(qeth_get_ipacmd_buffer);
  2176. void qeth_prepare_ipa_cmd(struct qeth_card *card, struct qeth_cmd_buffer *iob,
  2177. char prot_type)
  2178. {
  2179. memcpy(iob->data, IPA_PDU_HEADER, IPA_PDU_HEADER_SIZE);
  2180. memcpy(QETH_IPA_CMD_PROT_TYPE(iob->data), &prot_type, 1);
  2181. memcpy(QETH_IPA_CMD_DEST_ADDR(iob->data),
  2182. &card->token.ulp_connection_r, QETH_MPC_TOKEN_LENGTH);
  2183. }
  2184. EXPORT_SYMBOL_GPL(qeth_prepare_ipa_cmd);
  2185. int qeth_send_ipa_cmd(struct qeth_card *card, struct qeth_cmd_buffer *iob,
  2186. int (*reply_cb)(struct qeth_card *, struct qeth_reply*,
  2187. unsigned long),
  2188. void *reply_param)
  2189. {
  2190. int rc;
  2191. char prot_type;
  2192. QETH_DBF_TEXT(TRACE, 4, "sendipa");
  2193. if (card->options.layer2)
  2194. if (card->info.type == QETH_CARD_TYPE_OSN)
  2195. prot_type = QETH_PROT_OSN2;
  2196. else
  2197. prot_type = QETH_PROT_LAYER2;
  2198. else
  2199. prot_type = QETH_PROT_TCPIP;
  2200. qeth_prepare_ipa_cmd(card, iob, prot_type);
  2201. rc = qeth_send_control_data(card, IPA_CMD_LENGTH,
  2202. iob, reply_cb, reply_param);
  2203. return rc;
  2204. }
  2205. EXPORT_SYMBOL_GPL(qeth_send_ipa_cmd);
  2206. static int qeth_send_startstoplan(struct qeth_card *card,
  2207. enum qeth_ipa_cmds ipacmd, enum qeth_prot_versions prot)
  2208. {
  2209. int rc;
  2210. struct qeth_cmd_buffer *iob;
  2211. iob = qeth_get_ipacmd_buffer(card, ipacmd, prot);
  2212. rc = qeth_send_ipa_cmd(card, iob, NULL, NULL);
  2213. return rc;
  2214. }
  2215. int qeth_send_startlan(struct qeth_card *card)
  2216. {
  2217. int rc;
  2218. QETH_DBF_TEXT(SETUP, 2, "strtlan");
  2219. rc = qeth_send_startstoplan(card, IPA_CMD_STARTLAN, 0);
  2220. return rc;
  2221. }
  2222. EXPORT_SYMBOL_GPL(qeth_send_startlan);
  2223. int qeth_send_stoplan(struct qeth_card *card)
  2224. {
  2225. int rc = 0;
  2226. /*
  2227. * TODO: according to the IPA format document page 14,
  2228. * TCP/IP (we!) never issue a STOPLAN
  2229. * is this right ?!?
  2230. */
  2231. QETH_DBF_TEXT(SETUP, 2, "stoplan");
  2232. rc = qeth_send_startstoplan(card, IPA_CMD_STOPLAN, 0);
  2233. return rc;
  2234. }
  2235. EXPORT_SYMBOL_GPL(qeth_send_stoplan);
  2236. int qeth_default_setadapterparms_cb(struct qeth_card *card,
  2237. struct qeth_reply *reply, unsigned long data)
  2238. {
  2239. struct qeth_ipa_cmd *cmd;
  2240. QETH_DBF_TEXT(TRACE, 4, "defadpcb");
  2241. cmd = (struct qeth_ipa_cmd *) data;
  2242. if (cmd->hdr.return_code == 0)
  2243. cmd->hdr.return_code =
  2244. cmd->data.setadapterparms.hdr.return_code;
  2245. return 0;
  2246. }
  2247. EXPORT_SYMBOL_GPL(qeth_default_setadapterparms_cb);
  2248. static int qeth_query_setadapterparms_cb(struct qeth_card *card,
  2249. struct qeth_reply *reply, unsigned long data)
  2250. {
  2251. struct qeth_ipa_cmd *cmd;
  2252. QETH_DBF_TEXT(TRACE, 3, "quyadpcb");
  2253. cmd = (struct qeth_ipa_cmd *) data;
  2254. if (cmd->data.setadapterparms.data.query_cmds_supp.lan_type & 0x7f)
  2255. card->info.link_type =
  2256. cmd->data.setadapterparms.data.query_cmds_supp.lan_type;
  2257. card->options.adp.supported_funcs =
  2258. cmd->data.setadapterparms.data.query_cmds_supp.supported_cmds;
  2259. return qeth_default_setadapterparms_cb(card, reply, (unsigned long)cmd);
  2260. }
  2261. struct qeth_cmd_buffer *qeth_get_adapter_cmd(struct qeth_card *card,
  2262. __u32 command, __u32 cmdlen)
  2263. {
  2264. struct qeth_cmd_buffer *iob;
  2265. struct qeth_ipa_cmd *cmd;
  2266. iob = qeth_get_ipacmd_buffer(card, IPA_CMD_SETADAPTERPARMS,
  2267. QETH_PROT_IPV4);
  2268. cmd = (struct qeth_ipa_cmd *)(iob->data+IPA_PDU_HEADER_SIZE);
  2269. cmd->data.setadapterparms.hdr.cmdlength = cmdlen;
  2270. cmd->data.setadapterparms.hdr.command_code = command;
  2271. cmd->data.setadapterparms.hdr.used_total = 1;
  2272. cmd->data.setadapterparms.hdr.seq_no = 1;
  2273. return iob;
  2274. }
  2275. EXPORT_SYMBOL_GPL(qeth_get_adapter_cmd);
  2276. int qeth_query_setadapterparms(struct qeth_card *card)
  2277. {
  2278. int rc;
  2279. struct qeth_cmd_buffer *iob;
  2280. QETH_DBF_TEXT(TRACE, 3, "queryadp");
  2281. iob = qeth_get_adapter_cmd(card, IPA_SETADP_QUERY_COMMANDS_SUPPORTED,
  2282. sizeof(struct qeth_ipacmd_setadpparms));
  2283. rc = qeth_send_ipa_cmd(card, iob, qeth_query_setadapterparms_cb, NULL);
  2284. return rc;
  2285. }
  2286. EXPORT_SYMBOL_GPL(qeth_query_setadapterparms);
  2287. int qeth_check_qdio_errors(struct qdio_buffer *buf, unsigned int qdio_error,
  2288. const char *dbftext)
  2289. {
  2290. if (qdio_error) {
  2291. QETH_DBF_TEXT(TRACE, 2, dbftext);
  2292. QETH_DBF_TEXT(QERR, 2, dbftext);
  2293. QETH_DBF_TEXT_(QERR, 2, " F15=%02X",
  2294. buf->element[15].flags & 0xff);
  2295. QETH_DBF_TEXT_(QERR, 2, " F14=%02X",
  2296. buf->element[14].flags & 0xff);
  2297. QETH_DBF_TEXT_(QERR, 2, " qerr=%X", qdio_error);
  2298. return 1;
  2299. }
  2300. return 0;
  2301. }
  2302. EXPORT_SYMBOL_GPL(qeth_check_qdio_errors);
  2303. void qeth_queue_input_buffer(struct qeth_card *card, int index)
  2304. {
  2305. struct qeth_qdio_q *queue = card->qdio.in_q;
  2306. int count;
  2307. int i;
  2308. int rc;
  2309. int newcount = 0;
  2310. count = (index < queue->next_buf_to_init)?
  2311. card->qdio.in_buf_pool.buf_count -
  2312. (queue->next_buf_to_init - index) :
  2313. card->qdio.in_buf_pool.buf_count -
  2314. (queue->next_buf_to_init + QDIO_MAX_BUFFERS_PER_Q - index);
  2315. /* only requeue at a certain threshold to avoid SIGAs */
  2316. if (count >= QETH_IN_BUF_REQUEUE_THRESHOLD(card)) {
  2317. for (i = queue->next_buf_to_init;
  2318. i < queue->next_buf_to_init + count; ++i) {
  2319. if (qeth_init_input_buffer(card,
  2320. &queue->bufs[i % QDIO_MAX_BUFFERS_PER_Q])) {
  2321. break;
  2322. } else {
  2323. newcount++;
  2324. }
  2325. }
  2326. if (newcount < count) {
  2327. /* we are in memory shortage so we switch back to
  2328. traditional skb allocation and drop packages */
  2329. atomic_set(&card->force_alloc_skb, 3);
  2330. count = newcount;
  2331. } else {
  2332. atomic_add_unless(&card->force_alloc_skb, -1, 0);
  2333. }
  2334. /*
  2335. * according to old code it should be avoided to requeue all
  2336. * 128 buffers in order to benefit from PCI avoidance.
  2337. * this function keeps at least one buffer (the buffer at
  2338. * 'index') un-requeued -> this buffer is the first buffer that
  2339. * will be requeued the next time
  2340. */
  2341. if (card->options.performance_stats) {
  2342. card->perf_stats.inbound_do_qdio_cnt++;
  2343. card->perf_stats.inbound_do_qdio_start_time =
  2344. qeth_get_micros();
  2345. }
  2346. rc = do_QDIO(CARD_DDEV(card), QDIO_FLAG_SYNC_INPUT, 0,
  2347. queue->next_buf_to_init, count);
  2348. if (card->options.performance_stats)
  2349. card->perf_stats.inbound_do_qdio_time +=
  2350. qeth_get_micros() -
  2351. card->perf_stats.inbound_do_qdio_start_time;
  2352. if (rc) {
  2353. PRINT_WARN("qeth_queue_input_buffer's do_QDIO "
  2354. "return %i (device %s).\n",
  2355. rc, CARD_DDEV_ID(card));
  2356. QETH_DBF_TEXT(TRACE, 2, "qinberr");
  2357. QETH_DBF_TEXT_(TRACE, 2, "%s", CARD_BUS_ID(card));
  2358. }
  2359. queue->next_buf_to_init = (queue->next_buf_to_init + count) %
  2360. QDIO_MAX_BUFFERS_PER_Q;
  2361. }
  2362. }
  2363. EXPORT_SYMBOL_GPL(qeth_queue_input_buffer);
  2364. static int qeth_handle_send_error(struct qeth_card *card,
  2365. struct qeth_qdio_out_buffer *buffer, unsigned int qdio_err)
  2366. {
  2367. int sbalf15 = buffer->buffer->element[15].flags & 0xff;
  2368. int cc = qdio_err & 3;
  2369. QETH_DBF_TEXT(TRACE, 6, "hdsnderr");
  2370. qeth_check_qdio_errors(buffer->buffer, qdio_err, "qouterr");
  2371. switch (cc) {
  2372. case 0:
  2373. if (qdio_err) {
  2374. QETH_DBF_TEXT(TRACE, 1, "lnkfail");
  2375. QETH_DBF_TEXT_(TRACE, 1, "%s", CARD_BUS_ID(card));
  2376. QETH_DBF_TEXT_(TRACE, 1, "%04x %02x",
  2377. (u16)qdio_err, (u8)sbalf15);
  2378. return QETH_SEND_ERROR_LINK_FAILURE;
  2379. }
  2380. return QETH_SEND_ERROR_NONE;
  2381. case 2:
  2382. if (qdio_err & QDIO_ERROR_SIGA_BUSY) {
  2383. QETH_DBF_TEXT(TRACE, 1, "SIGAcc2B");
  2384. QETH_DBF_TEXT_(TRACE, 1, "%s", CARD_BUS_ID(card));
  2385. return QETH_SEND_ERROR_KICK_IT;
  2386. }
  2387. if ((sbalf15 >= 15) && (sbalf15 <= 31))
  2388. return QETH_SEND_ERROR_RETRY;
  2389. return QETH_SEND_ERROR_LINK_FAILURE;
  2390. /* look at qdio_error and sbalf 15 */
  2391. case 1:
  2392. QETH_DBF_TEXT(TRACE, 1, "SIGAcc1");
  2393. QETH_DBF_TEXT_(TRACE, 1, "%s", CARD_BUS_ID(card));
  2394. return QETH_SEND_ERROR_LINK_FAILURE;
  2395. case 3:
  2396. default:
  2397. QETH_DBF_TEXT(TRACE, 1, "SIGAcc3");
  2398. QETH_DBF_TEXT_(TRACE, 1, "%s", CARD_BUS_ID(card));
  2399. return QETH_SEND_ERROR_KICK_IT;
  2400. }
  2401. }
  2402. /*
  2403. * Switched to packing state if the number of used buffers on a queue
  2404. * reaches a certain limit.
  2405. */
  2406. static void qeth_switch_to_packing_if_needed(struct qeth_qdio_out_q *queue)
  2407. {
  2408. if (!queue->do_pack) {
  2409. if (atomic_read(&queue->used_buffers)
  2410. >= QETH_HIGH_WATERMARK_PACK){
  2411. /* switch non-PACKING -> PACKING */
  2412. QETH_DBF_TEXT(TRACE, 6, "np->pack");
  2413. if (queue->card->options.performance_stats)
  2414. queue->card->perf_stats.sc_dp_p++;
  2415. queue->do_pack = 1;
  2416. }
  2417. }
  2418. }
  2419. /*
  2420. * Switches from packing to non-packing mode. If there is a packing
  2421. * buffer on the queue this buffer will be prepared to be flushed.
  2422. * In that case 1 is returned to inform the caller. If no buffer
  2423. * has to be flushed, zero is returned.
  2424. */
  2425. static int qeth_switch_to_nonpacking_if_needed(struct qeth_qdio_out_q *queue)
  2426. {
  2427. struct qeth_qdio_out_buffer *buffer;
  2428. int flush_count = 0;
  2429. if (queue->do_pack) {
  2430. if (atomic_read(&queue->used_buffers)
  2431. <= QETH_LOW_WATERMARK_PACK) {
  2432. /* switch PACKING -> non-PACKING */
  2433. QETH_DBF_TEXT(TRACE, 6, "pack->np");
  2434. if (queue->card->options.performance_stats)
  2435. queue->card->perf_stats.sc_p_dp++;
  2436. queue->do_pack = 0;
  2437. /* flush packing buffers */
  2438. buffer = &queue->bufs[queue->next_buf_to_fill];
  2439. if ((atomic_read(&buffer->state) ==
  2440. QETH_QDIO_BUF_EMPTY) &&
  2441. (buffer->next_element_to_fill > 0)) {
  2442. atomic_set(&buffer->state,
  2443. QETH_QDIO_BUF_PRIMED);
  2444. flush_count++;
  2445. queue->next_buf_to_fill =
  2446. (queue->next_buf_to_fill + 1) %
  2447. QDIO_MAX_BUFFERS_PER_Q;
  2448. }
  2449. }
  2450. }
  2451. return flush_count;
  2452. }
  2453. /*
  2454. * Called to flush a packing buffer if no more pci flags are on the queue.
  2455. * Checks if there is a packing buffer and prepares it to be flushed.
  2456. * In that case returns 1, otherwise zero.
  2457. */
  2458. static int qeth_flush_buffers_on_no_pci(struct qeth_qdio_out_q *queue)
  2459. {
  2460. struct qeth_qdio_out_buffer *buffer;
  2461. buffer = &queue->bufs[queue->next_buf_to_fill];
  2462. if ((atomic_read(&buffer->state) == QETH_QDIO_BUF_EMPTY) &&
  2463. (buffer->next_element_to_fill > 0)) {
  2464. /* it's a packing buffer */
  2465. atomic_set(&buffer->state, QETH_QDIO_BUF_PRIMED);
  2466. queue->next_buf_to_fill =
  2467. (queue->next_buf_to_fill + 1) % QDIO_MAX_BUFFERS_PER_Q;
  2468. return 1;
  2469. }
  2470. return 0;
  2471. }
  2472. static void qeth_flush_buffers(struct qeth_qdio_out_q *queue, int index,
  2473. int count)
  2474. {
  2475. struct qeth_qdio_out_buffer *buf;
  2476. int rc;
  2477. int i;
  2478. unsigned int qdio_flags;
  2479. for (i = index; i < index + count; ++i) {
  2480. buf = &queue->bufs[i % QDIO_MAX_BUFFERS_PER_Q];
  2481. buf->buffer->element[buf->next_element_to_fill - 1].flags |=
  2482. SBAL_FLAGS_LAST_ENTRY;
  2483. if (queue->card->info.type == QETH_CARD_TYPE_IQD)
  2484. continue;
  2485. if (!queue->do_pack) {
  2486. if ((atomic_read(&queue->used_buffers) >=
  2487. (QETH_HIGH_WATERMARK_PACK -
  2488. QETH_WATERMARK_PACK_FUZZ)) &&
  2489. !atomic_read(&queue->set_pci_flags_count)) {
  2490. /* it's likely that we'll go to packing
  2491. * mode soon */
  2492. atomic_inc(&queue->set_pci_flags_count);
  2493. buf->buffer->element[0].flags |= 0x40;
  2494. }
  2495. } else {
  2496. if (!atomic_read(&queue->set_pci_flags_count)) {
  2497. /*
  2498. * there's no outstanding PCI any more, so we
  2499. * have to request a PCI to be sure the the PCI
  2500. * will wake at some time in the future then we
  2501. * can flush packed buffers that might still be
  2502. * hanging around, which can happen if no
  2503. * further send was requested by the stack
  2504. */
  2505. atomic_inc(&queue->set_pci_flags_count);
  2506. buf->buffer->element[0].flags |= 0x40;
  2507. }
  2508. }
  2509. }
  2510. queue->card->dev->trans_start = jiffies;
  2511. if (queue->card->options.performance_stats) {
  2512. queue->card->perf_stats.outbound_do_qdio_cnt++;
  2513. queue->card->perf_stats.outbound_do_qdio_start_time =
  2514. qeth_get_micros();
  2515. }
  2516. qdio_flags = QDIO_FLAG_SYNC_OUTPUT;
  2517. if (atomic_read(&queue->set_pci_flags_count))
  2518. qdio_flags |= QDIO_FLAG_PCI_OUT;
  2519. rc = do_QDIO(CARD_DDEV(queue->card), qdio_flags,
  2520. queue->queue_no, index, count);
  2521. if (queue->card->options.performance_stats)
  2522. queue->card->perf_stats.outbound_do_qdio_time +=
  2523. qeth_get_micros() -
  2524. queue->card->perf_stats.outbound_do_qdio_start_time;
  2525. if (rc) {
  2526. QETH_DBF_TEXT(TRACE, 2, "flushbuf");
  2527. QETH_DBF_TEXT_(TRACE, 2, " err%d", rc);
  2528. QETH_DBF_TEXT_(TRACE, 2, "%s", CARD_DDEV_ID(queue->card));
  2529. queue->card->stats.tx_errors += count;
  2530. /* this must not happen under normal circumstances. if it
  2531. * happens something is really wrong -> recover */
  2532. qeth_schedule_recovery(queue->card);
  2533. return;
  2534. }
  2535. atomic_add(count, &queue->used_buffers);
  2536. if (queue->card->options.performance_stats)
  2537. queue->card->perf_stats.bufs_sent += count;
  2538. }
  2539. static void qeth_check_outbound_queue(struct qeth_qdio_out_q *queue)
  2540. {
  2541. int index;
  2542. int flush_cnt = 0;
  2543. int q_was_packing = 0;
  2544. /*
  2545. * check if weed have to switch to non-packing mode or if
  2546. * we have to get a pci flag out on the queue
  2547. */
  2548. if ((atomic_read(&queue->used_buffers) <= QETH_LOW_WATERMARK_PACK) ||
  2549. !atomic_read(&queue->set_pci_flags_count)) {
  2550. if (atomic_xchg(&queue->state, QETH_OUT_Q_LOCKED_FLUSH) ==
  2551. QETH_OUT_Q_UNLOCKED) {
  2552. /*
  2553. * If we get in here, there was no action in
  2554. * do_send_packet. So, we check if there is a
  2555. * packing buffer to be flushed here.
  2556. */
  2557. netif_stop_queue(queue->card->dev);
  2558. index = queue->next_buf_to_fill;
  2559. q_was_packing = queue->do_pack;
  2560. /* queue->do_pack may change */
  2561. barrier();
  2562. flush_cnt += qeth_switch_to_nonpacking_if_needed(queue);
  2563. if (!flush_cnt &&
  2564. !atomic_read(&queue->set_pci_flags_count))
  2565. flush_cnt +=
  2566. qeth_flush_buffers_on_no_pci(queue);
  2567. if (queue->card->options.performance_stats &&
  2568. q_was_packing)
  2569. queue->card->perf_stats.bufs_sent_pack +=
  2570. flush_cnt;
  2571. if (flush_cnt)
  2572. qeth_flush_buffers(queue, index, flush_cnt);
  2573. atomic_set(&queue->state, QETH_OUT_Q_UNLOCKED);
  2574. }
  2575. }
  2576. }
  2577. void qeth_qdio_output_handler(struct ccw_device *ccwdev,
  2578. unsigned int qdio_error, int __queue, int first_element,
  2579. int count, unsigned long card_ptr)
  2580. {
  2581. struct qeth_card *card = (struct qeth_card *) card_ptr;
  2582. struct qeth_qdio_out_q *queue = card->qdio.out_qs[__queue];
  2583. struct qeth_qdio_out_buffer *buffer;
  2584. int i;
  2585. QETH_DBF_TEXT(TRACE, 6, "qdouhdl");
  2586. if (qdio_error & QDIO_ERROR_ACTIVATE_CHECK_CONDITION) {
  2587. QETH_DBF_TEXT(TRACE, 2, "achkcond");
  2588. QETH_DBF_TEXT_(TRACE, 2, "%s", CARD_BUS_ID(card));
  2589. netif_stop_queue(card->dev);
  2590. qeth_schedule_recovery(card);
  2591. return;
  2592. }
  2593. if (card->options.performance_stats) {
  2594. card->perf_stats.outbound_handler_cnt++;
  2595. card->perf_stats.outbound_handler_start_time =
  2596. qeth_get_micros();
  2597. }
  2598. for (i = first_element; i < (first_element + count); ++i) {
  2599. buffer = &queue->bufs[i % QDIO_MAX_BUFFERS_PER_Q];
  2600. /*we only handle the KICK_IT error by doing a recovery */
  2601. if (qeth_handle_send_error(card, buffer, qdio_error)
  2602. == QETH_SEND_ERROR_KICK_IT){
  2603. netif_stop_queue(card->dev);
  2604. qeth_schedule_recovery(card);
  2605. return;
  2606. }
  2607. qeth_clear_output_buffer(queue, buffer);
  2608. }
  2609. atomic_sub(count, &queue->used_buffers);
  2610. /* check if we need to do something on this outbound queue */
  2611. if (card->info.type != QETH_CARD_TYPE_IQD)
  2612. qeth_check_outbound_queue(queue);
  2613. netif_wake_queue(queue->card->dev);
  2614. if (card->options.performance_stats)
  2615. card->perf_stats.outbound_handler_time += qeth_get_micros() -
  2616. card->perf_stats.outbound_handler_start_time;
  2617. }
  2618. EXPORT_SYMBOL_GPL(qeth_qdio_output_handler);
  2619. int qeth_get_cast_type(struct qeth_card *card, struct sk_buff *skb)
  2620. {
  2621. int cast_type = RTN_UNSPEC;
  2622. if (card->info.type == QETH_CARD_TYPE_OSN)
  2623. return cast_type;
  2624. if (skb->dst && skb->dst->neighbour) {
  2625. cast_type = skb->dst->neighbour->type;
  2626. if ((cast_type == RTN_BROADCAST) ||
  2627. (cast_type == RTN_MULTICAST) ||
  2628. (cast_type == RTN_ANYCAST))
  2629. return cast_type;
  2630. else
  2631. return RTN_UNSPEC;
  2632. }
  2633. /* try something else */
  2634. if (skb->protocol == ETH_P_IPV6)
  2635. return (skb_network_header(skb)[24] == 0xff) ?
  2636. RTN_MULTICAST : 0;
  2637. else if (skb->protocol == ETH_P_IP)
  2638. return ((skb_network_header(skb)[16] & 0xf0) == 0xe0) ?
  2639. RTN_MULTICAST : 0;
  2640. /* ... */
  2641. if (!memcmp(skb->data, skb->dev->broadcast, 6))
  2642. return RTN_BROADCAST;
  2643. else {
  2644. u16 hdr_mac;
  2645. hdr_mac = *((u16 *)skb->data);
  2646. /* tr multicast? */
  2647. switch (card->info.link_type) {
  2648. case QETH_LINK_TYPE_HSTR:
  2649. case QETH_LINK_TYPE_LANE_TR:
  2650. if ((hdr_mac == QETH_TR_MAC_NC) ||
  2651. (hdr_mac == QETH_TR_MAC_C))
  2652. return RTN_MULTICAST;
  2653. break;
  2654. /* eth or so multicast? */
  2655. default:
  2656. if ((hdr_mac == QETH_ETH_MAC_V4) ||
  2657. (hdr_mac == QETH_ETH_MAC_V6))
  2658. return RTN_MULTICAST;
  2659. }
  2660. }
  2661. return cast_type;
  2662. }
  2663. EXPORT_SYMBOL_GPL(qeth_get_cast_type);
  2664. int qeth_get_priority_queue(struct qeth_card *card, struct sk_buff *skb,
  2665. int ipv, int cast_type)
  2666. {
  2667. if (!ipv && (card->info.type == QETH_CARD_TYPE_OSAE))
  2668. return card->qdio.default_out_queue;
  2669. switch (card->qdio.no_out_queues) {
  2670. case 4:
  2671. if (cast_type && card->info.is_multicast_different)
  2672. return card->info.is_multicast_different &
  2673. (card->qdio.no_out_queues - 1);
  2674. if (card->qdio.do_prio_queueing && (ipv == 4)) {
  2675. const u8 tos = ip_hdr(skb)->tos;
  2676. if (card->qdio.do_prio_queueing ==
  2677. QETH_PRIO_Q_ING_TOS) {
  2678. if (tos & IP_TOS_NOTIMPORTANT)
  2679. return 3;
  2680. if (tos & IP_TOS_HIGHRELIABILITY)
  2681. return 2;
  2682. if (tos & IP_TOS_HIGHTHROUGHPUT)
  2683. return 1;
  2684. if (tos & IP_TOS_LOWDELAY)
  2685. return 0;
  2686. }
  2687. if (card->qdio.do_prio_queueing ==
  2688. QETH_PRIO_Q_ING_PREC)
  2689. return 3 - (tos >> 6);
  2690. } else if (card->qdio.do_prio_queueing && (ipv == 6)) {
  2691. /* TODO: IPv6!!! */
  2692. }
  2693. return card->qdio.default_out_queue;
  2694. case 1: /* fallthrough for single-out-queue 1920-device */
  2695. default:
  2696. return card->qdio.default_out_queue;
  2697. }
  2698. }
  2699. EXPORT_SYMBOL_GPL(qeth_get_priority_queue);
  2700. int qeth_get_elements_no(struct qeth_card *card, void *hdr,
  2701. struct sk_buff *skb, int elems)
  2702. {
  2703. int elements_needed = 0;
  2704. if (skb_shinfo(skb)->nr_frags > 0)
  2705. elements_needed = (skb_shinfo(skb)->nr_frags + 1);
  2706. if (elements_needed == 0)
  2707. elements_needed = 1 + (((((unsigned long) skb->data) %
  2708. PAGE_SIZE) + skb->len) >> PAGE_SHIFT);
  2709. if ((elements_needed + elems) > QETH_MAX_BUFFER_ELEMENTS(card)) {
  2710. QETH_DBF_MESSAGE(2, "Invalid size of IP packet "
  2711. "(Number=%d / Length=%d). Discarded.\n",
  2712. (elements_needed+elems), skb->len);
  2713. return 0;
  2714. }
  2715. return elements_needed;
  2716. }
  2717. EXPORT_SYMBOL_GPL(qeth_get_elements_no);
  2718. static inline void __qeth_fill_buffer(struct sk_buff *skb,
  2719. struct qdio_buffer *buffer, int is_tso, int *next_element_to_fill,
  2720. int offset)
  2721. {
  2722. int length = skb->len;
  2723. int length_here;
  2724. int element;
  2725. char *data;
  2726. int first_lap ;
  2727. element = *next_element_to_fill;
  2728. data = skb->data;
  2729. first_lap = (is_tso == 0 ? 1 : 0);
  2730. if (offset >= 0) {
  2731. data = skb->data + offset;
  2732. length -= offset;
  2733. first_lap = 0;
  2734. }
  2735. while (length > 0) {
  2736. /* length_here is the remaining amount of data in this page */
  2737. length_here = PAGE_SIZE - ((unsigned long) data % PAGE_SIZE);
  2738. if (length < length_here)
  2739. length_here = length;
  2740. buffer->element[element].addr = data;
  2741. buffer->element[element].length = length_here;
  2742. length -= length_here;
  2743. if (!length) {
  2744. if (first_lap)
  2745. buffer->element[element].flags = 0;
  2746. else
  2747. buffer->element[element].flags =
  2748. SBAL_FLAGS_LAST_FRAG;
  2749. } else {
  2750. if (first_lap)
  2751. buffer->element[element].flags =
  2752. SBAL_FLAGS_FIRST_FRAG;
  2753. else
  2754. buffer->element[element].flags =
  2755. SBAL_FLAGS_MIDDLE_FRAG;
  2756. }
  2757. data += length_here;
  2758. element++;
  2759. first_lap = 0;
  2760. }
  2761. *next_element_to_fill = element;
  2762. }
  2763. static inline int qeth_fill_buffer(struct qeth_qdio_out_q *queue,
  2764. struct qeth_qdio_out_buffer *buf, struct sk_buff *skb,
  2765. struct qeth_hdr *hdr, int offset, int hd_len)
  2766. {
  2767. struct qdio_buffer *buffer;
  2768. int flush_cnt = 0, hdr_len, large_send = 0;
  2769. buffer = buf->buffer;
  2770. atomic_inc(&skb->users);
  2771. skb_queue_tail(&buf->skb_list, skb);
  2772. /*check first on TSO ....*/
  2773. if (hdr->hdr.l3.id == QETH_HEADER_TYPE_TSO) {
  2774. int element = buf->next_element_to_fill;
  2775. hdr_len = sizeof(struct qeth_hdr_tso) +
  2776. ((struct qeth_hdr_tso *)hdr)->ext.dg_hdr_len;
  2777. /*fill first buffer entry only with header information */
  2778. buffer->element[element].addr = skb->data;
  2779. buffer->element[element].length = hdr_len;
  2780. buffer->element[element].flags = SBAL_FLAGS_FIRST_FRAG;
  2781. buf->next_element_to_fill++;
  2782. skb->data += hdr_len;
  2783. skb->len -= hdr_len;
  2784. large_send = 1;
  2785. }
  2786. if (offset >= 0) {
  2787. int element = buf->next_element_to_fill;
  2788. buffer->element[element].addr = hdr;
  2789. buffer->element[element].length = sizeof(struct qeth_hdr) +
  2790. hd_len;
  2791. buffer->element[element].flags = SBAL_FLAGS_FIRST_FRAG;
  2792. buf->is_header[element] = 1;
  2793. buf->next_element_to_fill++;
  2794. }
  2795. if (skb_shinfo(skb)->nr_frags == 0)
  2796. __qeth_fill_buffer(skb, buffer, large_send,
  2797. (int *)&buf->next_element_to_fill, offset);
  2798. else
  2799. __qeth_fill_buffer_frag(skb, buffer, large_send,
  2800. (int *)&buf->next_element_to_fill);
  2801. if (!queue->do_pack) {
  2802. QETH_DBF_TEXT(TRACE, 6, "fillbfnp");
  2803. /* set state to PRIMED -> will be flushed */
  2804. atomic_set(&buf->state, QETH_QDIO_BUF_PRIMED);
  2805. flush_cnt = 1;
  2806. } else {
  2807. QETH_DBF_TEXT(TRACE, 6, "fillbfpa");
  2808. if (queue->card->options.performance_stats)
  2809. queue->card->perf_stats.skbs_sent_pack++;
  2810. if (buf->next_element_to_fill >=
  2811. QETH_MAX_BUFFER_ELEMENTS(queue->card)) {
  2812. /*
  2813. * packed buffer if full -> set state PRIMED
  2814. * -> will be flushed
  2815. */
  2816. atomic_set(&buf->state, QETH_QDIO_BUF_PRIMED);
  2817. flush_cnt = 1;
  2818. }
  2819. }
  2820. return flush_cnt;
  2821. }
  2822. int qeth_do_send_packet_fast(struct qeth_card *card,
  2823. struct qeth_qdio_out_q *queue, struct sk_buff *skb,
  2824. struct qeth_hdr *hdr, int elements_needed,
  2825. struct qeth_eddp_context *ctx, int offset, int hd_len)
  2826. {
  2827. struct qeth_qdio_out_buffer *buffer;
  2828. int buffers_needed = 0;
  2829. int flush_cnt = 0;
  2830. int index;
  2831. /* spin until we get the queue ... */
  2832. while (atomic_cmpxchg(&queue->state, QETH_OUT_Q_UNLOCKED,
  2833. QETH_OUT_Q_LOCKED) != QETH_OUT_Q_UNLOCKED);
  2834. /* ... now we've got the queue */
  2835. index = queue->next_buf_to_fill;
  2836. buffer = &queue->bufs[queue->next_buf_to_fill];
  2837. /*
  2838. * check if buffer is empty to make sure that we do not 'overtake'
  2839. * ourselves and try to fill a buffer that is already primed
  2840. */
  2841. if (atomic_read(&buffer->state) != QETH_QDIO_BUF_EMPTY)
  2842. goto out;
  2843. if (ctx == NULL)
  2844. queue->next_buf_to_fill = (queue->next_buf_to_fill + 1) %
  2845. QDIO_MAX_BUFFERS_PER_Q;
  2846. else {
  2847. buffers_needed = qeth_eddp_check_buffers_for_context(queue,
  2848. ctx);
  2849. if (buffers_needed < 0)
  2850. goto out;
  2851. queue->next_buf_to_fill =
  2852. (queue->next_buf_to_fill + buffers_needed) %
  2853. QDIO_MAX_BUFFERS_PER_Q;
  2854. }
  2855. atomic_set(&queue->state, QETH_OUT_Q_UNLOCKED);
  2856. if (ctx == NULL) {
  2857. qeth_fill_buffer(queue, buffer, skb, hdr, offset, hd_len);
  2858. qeth_flush_buffers(queue, index, 1);
  2859. } else {
  2860. flush_cnt = qeth_eddp_fill_buffer(queue, ctx, index);
  2861. WARN_ON(buffers_needed != flush_cnt);
  2862. qeth_flush_buffers(queue, index, flush_cnt);
  2863. }
  2864. return 0;
  2865. out:
  2866. atomic_set(&queue->state, QETH_OUT_Q_UNLOCKED);
  2867. return -EBUSY;
  2868. }
  2869. EXPORT_SYMBOL_GPL(qeth_do_send_packet_fast);
  2870. int qeth_do_send_packet(struct qeth_card *card, struct qeth_qdio_out_q *queue,
  2871. struct sk_buff *skb, struct qeth_hdr *hdr,
  2872. int elements_needed, struct qeth_eddp_context *ctx)
  2873. {
  2874. struct qeth_qdio_out_buffer *buffer;
  2875. int start_index;
  2876. int flush_count = 0;
  2877. int do_pack = 0;
  2878. int tmp;
  2879. int rc = 0;
  2880. /* spin until we get the queue ... */
  2881. while (atomic_cmpxchg(&queue->state, QETH_OUT_Q_UNLOCKED,
  2882. QETH_OUT_Q_LOCKED) != QETH_OUT_Q_UNLOCKED);
  2883. start_index = queue->next_buf_to_fill;
  2884. buffer = &queue->bufs[queue->next_buf_to_fill];
  2885. /*
  2886. * check if buffer is empty to make sure that we do not 'overtake'
  2887. * ourselves and try to fill a buffer that is already primed
  2888. */
  2889. if (atomic_read(&buffer->state) != QETH_QDIO_BUF_EMPTY) {
  2890. atomic_set(&queue->state, QETH_OUT_Q_UNLOCKED);
  2891. return -EBUSY;
  2892. }
  2893. /* check if we need to switch packing state of this queue */
  2894. qeth_switch_to_packing_if_needed(queue);
  2895. if (queue->do_pack) {
  2896. do_pack = 1;
  2897. if (ctx == NULL) {
  2898. /* does packet fit in current buffer? */
  2899. if ((QETH_MAX_BUFFER_ELEMENTS(card) -
  2900. buffer->next_element_to_fill) < elements_needed) {
  2901. /* ... no -> set state PRIMED */
  2902. atomic_set(&buffer->state,
  2903. QETH_QDIO_BUF_PRIMED);
  2904. flush_count++;
  2905. queue->next_buf_to_fill =
  2906. (queue->next_buf_to_fill + 1) %
  2907. QDIO_MAX_BUFFERS_PER_Q;
  2908. buffer = &queue->bufs[queue->next_buf_to_fill];
  2909. /* we did a step forward, so check buffer state
  2910. * again */
  2911. if (atomic_read(&buffer->state) !=
  2912. QETH_QDIO_BUF_EMPTY){
  2913. qeth_flush_buffers(queue, start_index,
  2914. flush_count);
  2915. atomic_set(&queue->state,
  2916. QETH_OUT_Q_UNLOCKED);
  2917. return -EBUSY;
  2918. }
  2919. }
  2920. } else {
  2921. /* check if we have enough elements (including following
  2922. * free buffers) to handle eddp context */
  2923. if (qeth_eddp_check_buffers_for_context(queue, ctx)
  2924. < 0) {
  2925. rc = -EBUSY;
  2926. goto out;
  2927. }
  2928. }
  2929. }
  2930. if (ctx == NULL)
  2931. tmp = qeth_fill_buffer(queue, buffer, skb, hdr, -1, 0);
  2932. else {
  2933. tmp = qeth_eddp_fill_buffer(queue, ctx,
  2934. queue->next_buf_to_fill);
  2935. if (tmp < 0) {
  2936. rc = -EBUSY;
  2937. goto out;
  2938. }
  2939. }
  2940. queue->next_buf_to_fill = (queue->next_buf_to_fill + tmp) %
  2941. QDIO_MAX_BUFFERS_PER_Q;
  2942. flush_count += tmp;
  2943. out:
  2944. if (flush_count)
  2945. qeth_flush_buffers(queue, start_index, flush_count);
  2946. else if (!atomic_read(&queue->set_pci_flags_count))
  2947. atomic_xchg(&queue->state, QETH_OUT_Q_LOCKED_FLUSH);
  2948. /*
  2949. * queue->state will go from LOCKED -> UNLOCKED or from
  2950. * LOCKED_FLUSH -> LOCKED if output_handler wanted to 'notify' us
  2951. * (switch packing state or flush buffer to get another pci flag out).
  2952. * In that case we will enter this loop
  2953. */
  2954. while (atomic_dec_return(&queue->state)) {
  2955. flush_count = 0;
  2956. start_index = queue->next_buf_to_fill;
  2957. /* check if we can go back to non-packing state */
  2958. flush_count += qeth_switch_to_nonpacking_if_needed(queue);
  2959. /*
  2960. * check if we need to flush a packing buffer to get a pci
  2961. * flag out on the queue
  2962. */
  2963. if (!flush_count && !atomic_read(&queue->set_pci_flags_count))
  2964. flush_count += qeth_flush_buffers_on_no_pci(queue);
  2965. if (flush_count)
  2966. qeth_flush_buffers(queue, start_index, flush_count);
  2967. }
  2968. /* at this point the queue is UNLOCKED again */
  2969. if (queue->card->options.performance_stats && do_pack)
  2970. queue->card->perf_stats.bufs_sent_pack += flush_count;
  2971. return rc;
  2972. }
  2973. EXPORT_SYMBOL_GPL(qeth_do_send_packet);
  2974. static int qeth_setadp_promisc_mode_cb(struct qeth_card *card,
  2975. struct qeth_reply *reply, unsigned long data)
  2976. {
  2977. struct qeth_ipa_cmd *cmd;
  2978. struct qeth_ipacmd_setadpparms *setparms;
  2979. QETH_DBF_TEXT(TRACE, 4, "prmadpcb");
  2980. cmd = (struct qeth_ipa_cmd *) data;
  2981. setparms = &(cmd->data.setadapterparms);
  2982. qeth_default_setadapterparms_cb(card, reply, (unsigned long)cmd);
  2983. if (cmd->hdr.return_code) {
  2984. QETH_DBF_TEXT_(TRACE, 4, "prmrc%2.2x", cmd->hdr.return_code);
  2985. setparms->data.mode = SET_PROMISC_MODE_OFF;
  2986. }
  2987. card->info.promisc_mode = setparms->data.mode;
  2988. return 0;
  2989. }
  2990. void qeth_setadp_promisc_mode(struct qeth_card *card)
  2991. {
  2992. enum qeth_ipa_promisc_modes mode;
  2993. struct net_device *dev = card->dev;
  2994. struct qeth_cmd_buffer *iob;
  2995. struct qeth_ipa_cmd *cmd;
  2996. QETH_DBF_TEXT(TRACE, 4, "setprom");
  2997. if (((dev->flags & IFF_PROMISC) &&
  2998. (card->info.promisc_mode == SET_PROMISC_MODE_ON)) ||
  2999. (!(dev->flags & IFF_PROMISC) &&
  3000. (card->info.promisc_mode == SET_PROMISC_MODE_OFF)))
  3001. return;
  3002. mode = SET_PROMISC_MODE_OFF;
  3003. if (dev->flags & IFF_PROMISC)
  3004. mode = SET_PROMISC_MODE_ON;
  3005. QETH_DBF_TEXT_(TRACE, 4, "mode:%x", mode);
  3006. iob = qeth_get_adapter_cmd(card, IPA_SETADP_SET_PROMISC_MODE,
  3007. sizeof(struct qeth_ipacmd_setadpparms));
  3008. cmd = (struct qeth_ipa_cmd *)(iob->data + IPA_PDU_HEADER_SIZE);
  3009. cmd->data.setadapterparms.data.mode = mode;
  3010. qeth_send_ipa_cmd(card, iob, qeth_setadp_promisc_mode_cb, NULL);
  3011. }
  3012. EXPORT_SYMBOL_GPL(qeth_setadp_promisc_mode);
  3013. int qeth_change_mtu(struct net_device *dev, int new_mtu)
  3014. {
  3015. struct qeth_card *card;
  3016. char dbf_text[15];
  3017. card = dev->ml_priv;
  3018. QETH_DBF_TEXT(TRACE, 4, "chgmtu");
  3019. sprintf(dbf_text, "%8x", new_mtu);
  3020. QETH_DBF_TEXT(TRACE, 4, dbf_text);
  3021. if (new_mtu < 64)
  3022. return -EINVAL;
  3023. if (new_mtu > 65535)
  3024. return -EINVAL;
  3025. if ((!qeth_is_supported(card, IPA_IP_FRAGMENTATION)) &&
  3026. (!qeth_mtu_is_valid(card, new_mtu)))
  3027. return -EINVAL;
  3028. dev->mtu = new_mtu;
  3029. return 0;
  3030. }
  3031. EXPORT_SYMBOL_GPL(qeth_change_mtu);
  3032. struct net_device_stats *qeth_get_stats(struct net_device *dev)
  3033. {
  3034. struct qeth_card *card;
  3035. card = dev->ml_priv;
  3036. QETH_DBF_TEXT(TRACE, 5, "getstat");
  3037. return &card->stats;
  3038. }
  3039. EXPORT_SYMBOL_GPL(qeth_get_stats);
  3040. static int qeth_setadpparms_change_macaddr_cb(struct qeth_card *card,
  3041. struct qeth_reply *reply, unsigned long data)
  3042. {
  3043. struct qeth_ipa_cmd *cmd;
  3044. QETH_DBF_TEXT(TRACE, 4, "chgmaccb");
  3045. cmd = (struct qeth_ipa_cmd *) data;
  3046. if (!card->options.layer2 ||
  3047. !(card->info.mac_bits & QETH_LAYER2_MAC_READ)) {
  3048. memcpy(card->dev->dev_addr,
  3049. &cmd->data.setadapterparms.data.change_addr.addr,
  3050. OSA_ADDR_LEN);
  3051. card->info.mac_bits |= QETH_LAYER2_MAC_READ;
  3052. }
  3053. qeth_default_setadapterparms_cb(card, reply, (unsigned long) cmd);
  3054. return 0;
  3055. }
  3056. int qeth_setadpparms_change_macaddr(struct qeth_card *card)
  3057. {
  3058. int rc;
  3059. struct qeth_cmd_buffer *iob;
  3060. struct qeth_ipa_cmd *cmd;
  3061. QETH_DBF_TEXT(TRACE, 4, "chgmac");
  3062. iob = qeth_get_adapter_cmd(card, IPA_SETADP_ALTER_MAC_ADDRESS,
  3063. sizeof(struct qeth_ipacmd_setadpparms));
  3064. cmd = (struct qeth_ipa_cmd *)(iob->data+IPA_PDU_HEADER_SIZE);
  3065. cmd->data.setadapterparms.data.change_addr.cmd = CHANGE_ADDR_READ_MAC;
  3066. cmd->data.setadapterparms.data.change_addr.addr_size = OSA_ADDR_LEN;
  3067. memcpy(&cmd->data.setadapterparms.data.change_addr.addr,
  3068. card->dev->dev_addr, OSA_ADDR_LEN);
  3069. rc = qeth_send_ipa_cmd(card, iob, qeth_setadpparms_change_macaddr_cb,
  3070. NULL);
  3071. return rc;
  3072. }
  3073. EXPORT_SYMBOL_GPL(qeth_setadpparms_change_macaddr);
  3074. void qeth_tx_timeout(struct net_device *dev)
  3075. {
  3076. struct qeth_card *card;
  3077. card = dev->ml_priv;
  3078. card->stats.tx_errors++;
  3079. qeth_schedule_recovery(card);
  3080. }
  3081. EXPORT_SYMBOL_GPL(qeth_tx_timeout);
  3082. int qeth_mdio_read(struct net_device *dev, int phy_id, int regnum)
  3083. {
  3084. struct qeth_card *card = dev->ml_priv;
  3085. int rc = 0;
  3086. switch (regnum) {
  3087. case MII_BMCR: /* Basic mode control register */
  3088. rc = BMCR_FULLDPLX;
  3089. if ((card->info.link_type != QETH_LINK_TYPE_GBIT_ETH) &&
  3090. (card->info.link_type != QETH_LINK_TYPE_OSN) &&
  3091. (card->info.link_type != QETH_LINK_TYPE_10GBIT_ETH))
  3092. rc |= BMCR_SPEED100;
  3093. break;
  3094. case MII_BMSR: /* Basic mode status register */
  3095. rc = BMSR_ERCAP | BMSR_ANEGCOMPLETE | BMSR_LSTATUS |
  3096. BMSR_10HALF | BMSR_10FULL | BMSR_100HALF | BMSR_100FULL |
  3097. BMSR_100BASE4;
  3098. break;
  3099. case MII_PHYSID1: /* PHYS ID 1 */
  3100. rc = (dev->dev_addr[0] << 16) | (dev->dev_addr[1] << 8) |
  3101. dev->dev_addr[2];
  3102. rc = (rc >> 5) & 0xFFFF;
  3103. break;
  3104. case MII_PHYSID2: /* PHYS ID 2 */
  3105. rc = (dev->dev_addr[2] << 10) & 0xFFFF;
  3106. break;
  3107. case MII_ADVERTISE: /* Advertisement control reg */
  3108. rc = ADVERTISE_ALL;
  3109. break;
  3110. case MII_LPA: /* Link partner ability reg */
  3111. rc = LPA_10HALF | LPA_10FULL | LPA_100HALF | LPA_100FULL |
  3112. LPA_100BASE4 | LPA_LPACK;
  3113. break;
  3114. case MII_EXPANSION: /* Expansion register */
  3115. break;
  3116. case MII_DCOUNTER: /* disconnect counter */
  3117. break;
  3118. case MII_FCSCOUNTER: /* false carrier counter */
  3119. break;
  3120. case MII_NWAYTEST: /* N-way auto-neg test register */
  3121. break;
  3122. case MII_RERRCOUNTER: /* rx error counter */
  3123. rc = card->stats.rx_errors;
  3124. break;
  3125. case MII_SREVISION: /* silicon revision */
  3126. break;
  3127. case MII_RESV1: /* reserved 1 */
  3128. break;
  3129. case MII_LBRERROR: /* loopback, rx, bypass error */
  3130. break;
  3131. case MII_PHYADDR: /* physical address */
  3132. break;
  3133. case MII_RESV2: /* reserved 2 */
  3134. break;
  3135. case MII_TPISTATUS: /* TPI status for 10mbps */
  3136. break;
  3137. case MII_NCONFIG: /* network interface config */
  3138. break;
  3139. default:
  3140. break;
  3141. }
  3142. return rc;
  3143. }
  3144. EXPORT_SYMBOL_GPL(qeth_mdio_read);
  3145. static int qeth_send_ipa_snmp_cmd(struct qeth_card *card,
  3146. struct qeth_cmd_buffer *iob, int len,
  3147. int (*reply_cb)(struct qeth_card *, struct qeth_reply *,
  3148. unsigned long),
  3149. void *reply_param)
  3150. {
  3151. u16 s1, s2;
  3152. QETH_DBF_TEXT(TRACE, 4, "sendsnmp");
  3153. memcpy(iob->data, IPA_PDU_HEADER, IPA_PDU_HEADER_SIZE);
  3154. memcpy(QETH_IPA_CMD_DEST_ADDR(iob->data),
  3155. &card->token.ulp_connection_r, QETH_MPC_TOKEN_LENGTH);
  3156. /* adjust PDU length fields in IPA_PDU_HEADER */
  3157. s1 = (u32) IPA_PDU_HEADER_SIZE + len;
  3158. s2 = (u32) len;
  3159. memcpy(QETH_IPA_PDU_LEN_TOTAL(iob->data), &s1, 2);
  3160. memcpy(QETH_IPA_PDU_LEN_PDU1(iob->data), &s2, 2);
  3161. memcpy(QETH_IPA_PDU_LEN_PDU2(iob->data), &s2, 2);
  3162. memcpy(QETH_IPA_PDU_LEN_PDU3(iob->data), &s2, 2);
  3163. return qeth_send_control_data(card, IPA_PDU_HEADER_SIZE + len, iob,
  3164. reply_cb, reply_param);
  3165. }
  3166. static int qeth_snmp_command_cb(struct qeth_card *card,
  3167. struct qeth_reply *reply, unsigned long sdata)
  3168. {
  3169. struct qeth_ipa_cmd *cmd;
  3170. struct qeth_arp_query_info *qinfo;
  3171. struct qeth_snmp_cmd *snmp;
  3172. unsigned char *data;
  3173. __u16 data_len;
  3174. QETH_DBF_TEXT(TRACE, 3, "snpcmdcb");
  3175. cmd = (struct qeth_ipa_cmd *) sdata;
  3176. data = (unsigned char *)((char *)cmd - reply->offset);
  3177. qinfo = (struct qeth_arp_query_info *) reply->param;
  3178. snmp = &cmd->data.setadapterparms.data.snmp;
  3179. if (cmd->hdr.return_code) {
  3180. QETH_DBF_TEXT_(TRACE, 4, "scer1%i", cmd->hdr.return_code);
  3181. return 0;
  3182. }
  3183. if (cmd->data.setadapterparms.hdr.return_code) {
  3184. cmd->hdr.return_code =
  3185. cmd->data.setadapterparms.hdr.return_code;
  3186. QETH_DBF_TEXT_(TRACE, 4, "scer2%i", cmd->hdr.return_code);
  3187. return 0;
  3188. }
  3189. data_len = *((__u16 *)QETH_IPA_PDU_LEN_PDU1(data));
  3190. if (cmd->data.setadapterparms.hdr.seq_no == 1)
  3191. data_len -= (__u16)((char *)&snmp->data - (char *)cmd);
  3192. else
  3193. data_len -= (__u16)((char *)&snmp->request - (char *)cmd);
  3194. /* check if there is enough room in userspace */
  3195. if ((qinfo->udata_len - qinfo->udata_offset) < data_len) {
  3196. QETH_DBF_TEXT_(TRACE, 4, "scer3%i", -ENOMEM);
  3197. cmd->hdr.return_code = -ENOMEM;
  3198. return 0;
  3199. }
  3200. QETH_DBF_TEXT_(TRACE, 4, "snore%i",
  3201. cmd->data.setadapterparms.hdr.used_total);
  3202. QETH_DBF_TEXT_(TRACE, 4, "sseqn%i",
  3203. cmd->data.setadapterparms.hdr.seq_no);
  3204. /*copy entries to user buffer*/
  3205. if (cmd->data.setadapterparms.hdr.seq_no == 1) {
  3206. memcpy(qinfo->udata + qinfo->udata_offset,
  3207. (char *)snmp,
  3208. data_len + offsetof(struct qeth_snmp_cmd, data));
  3209. qinfo->udata_offset += offsetof(struct qeth_snmp_cmd, data);
  3210. } else {
  3211. memcpy(qinfo->udata + qinfo->udata_offset,
  3212. (char *)&snmp->request, data_len);
  3213. }
  3214. qinfo->udata_offset += data_len;
  3215. /* check if all replies received ... */
  3216. QETH_DBF_TEXT_(TRACE, 4, "srtot%i",
  3217. cmd->data.setadapterparms.hdr.used_total);
  3218. QETH_DBF_TEXT_(TRACE, 4, "srseq%i",
  3219. cmd->data.setadapterparms.hdr.seq_no);
  3220. if (cmd->data.setadapterparms.hdr.seq_no <
  3221. cmd->data.setadapterparms.hdr.used_total)
  3222. return 1;
  3223. return 0;
  3224. }
  3225. int qeth_snmp_command(struct qeth_card *card, char __user *udata)
  3226. {
  3227. struct qeth_cmd_buffer *iob;
  3228. struct qeth_ipa_cmd *cmd;
  3229. struct qeth_snmp_ureq *ureq;
  3230. int req_len;
  3231. struct qeth_arp_query_info qinfo = {0, };
  3232. int rc = 0;
  3233. QETH_DBF_TEXT(TRACE, 3, "snmpcmd");
  3234. if (card->info.guestlan)
  3235. return -EOPNOTSUPP;
  3236. if ((!qeth_adp_supported(card, IPA_SETADP_SET_SNMP_CONTROL)) &&
  3237. (!card->options.layer2)) {
  3238. return -EOPNOTSUPP;
  3239. }
  3240. /* skip 4 bytes (data_len struct member) to get req_len */
  3241. if (copy_from_user(&req_len, udata + sizeof(int), sizeof(int)))
  3242. return -EFAULT;
  3243. ureq = kmalloc(req_len+sizeof(struct qeth_snmp_ureq_hdr), GFP_KERNEL);
  3244. if (!ureq) {
  3245. QETH_DBF_TEXT(TRACE, 2, "snmpnome");
  3246. return -ENOMEM;
  3247. }
  3248. if (copy_from_user(ureq, udata,
  3249. req_len + sizeof(struct qeth_snmp_ureq_hdr))) {
  3250. kfree(ureq);
  3251. return -EFAULT;
  3252. }
  3253. qinfo.udata_len = ureq->hdr.data_len;
  3254. qinfo.udata = kzalloc(qinfo.udata_len, GFP_KERNEL);
  3255. if (!qinfo.udata) {
  3256. kfree(ureq);
  3257. return -ENOMEM;
  3258. }
  3259. qinfo.udata_offset = sizeof(struct qeth_snmp_ureq_hdr);
  3260. iob = qeth_get_adapter_cmd(card, IPA_SETADP_SET_SNMP_CONTROL,
  3261. QETH_SNMP_SETADP_CMDLENGTH + req_len);
  3262. cmd = (struct qeth_ipa_cmd *)(iob->data+IPA_PDU_HEADER_SIZE);
  3263. memcpy(&cmd->data.setadapterparms.data.snmp, &ureq->cmd, req_len);
  3264. rc = qeth_send_ipa_snmp_cmd(card, iob, QETH_SETADP_BASE_LEN + req_len,
  3265. qeth_snmp_command_cb, (void *)&qinfo);
  3266. if (rc)
  3267. QETH_DBF_MESSAGE(2, "SNMP command failed on %s: (0x%x)\n",
  3268. QETH_CARD_IFNAME(card), rc);
  3269. else {
  3270. if (copy_to_user(udata, qinfo.udata, qinfo.udata_len))
  3271. rc = -EFAULT;
  3272. }
  3273. kfree(ureq);
  3274. kfree(qinfo.udata);
  3275. return rc;
  3276. }
  3277. EXPORT_SYMBOL_GPL(qeth_snmp_command);
  3278. static inline int qeth_get_qdio_q_format(struct qeth_card *card)
  3279. {
  3280. switch (card->info.type) {
  3281. case QETH_CARD_TYPE_IQD:
  3282. return 2;
  3283. default:
  3284. return 0;
  3285. }
  3286. }
  3287. static int qeth_qdio_establish(struct qeth_card *card)
  3288. {
  3289. struct qdio_initialize init_data;
  3290. char *qib_param_field;
  3291. struct qdio_buffer **in_sbal_ptrs;
  3292. struct qdio_buffer **out_sbal_ptrs;
  3293. int i, j, k;
  3294. int rc = 0;
  3295. QETH_DBF_TEXT(SETUP, 2, "qdioest");
  3296. qib_param_field = kzalloc(QDIO_MAX_BUFFERS_PER_Q * sizeof(char),
  3297. GFP_KERNEL);
  3298. if (!qib_param_field)
  3299. return -ENOMEM;
  3300. qeth_create_qib_param_field(card, qib_param_field);
  3301. qeth_create_qib_param_field_blkt(card, qib_param_field);
  3302. in_sbal_ptrs = kmalloc(QDIO_MAX_BUFFERS_PER_Q * sizeof(void *),
  3303. GFP_KERNEL);
  3304. if (!in_sbal_ptrs) {
  3305. kfree(qib_param_field);
  3306. return -ENOMEM;
  3307. }
  3308. for (i = 0; i < QDIO_MAX_BUFFERS_PER_Q; ++i)
  3309. in_sbal_ptrs[i] = (struct qdio_buffer *)
  3310. virt_to_phys(card->qdio.in_q->bufs[i].buffer);
  3311. out_sbal_ptrs =
  3312. kmalloc(card->qdio.no_out_queues * QDIO_MAX_BUFFERS_PER_Q *
  3313. sizeof(void *), GFP_KERNEL);
  3314. if (!out_sbal_ptrs) {
  3315. kfree(in_sbal_ptrs);
  3316. kfree(qib_param_field);
  3317. return -ENOMEM;
  3318. }
  3319. for (i = 0, k = 0; i < card->qdio.no_out_queues; ++i)
  3320. for (j = 0; j < QDIO_MAX_BUFFERS_PER_Q; ++j, ++k) {
  3321. out_sbal_ptrs[k] = (struct qdio_buffer *)virt_to_phys(
  3322. card->qdio.out_qs[i]->bufs[j].buffer);
  3323. }
  3324. memset(&init_data, 0, sizeof(struct qdio_initialize));
  3325. init_data.cdev = CARD_DDEV(card);
  3326. init_data.q_format = qeth_get_qdio_q_format(card);
  3327. init_data.qib_param_field_format = 0;
  3328. init_data.qib_param_field = qib_param_field;
  3329. init_data.no_input_qs = 1;
  3330. init_data.no_output_qs = card->qdio.no_out_queues;
  3331. init_data.input_handler = card->discipline.input_handler;
  3332. init_data.output_handler = card->discipline.output_handler;
  3333. init_data.int_parm = (unsigned long) card;
  3334. init_data.flags = QDIO_INBOUND_0COPY_SBALS |
  3335. QDIO_OUTBOUND_0COPY_SBALS |
  3336. QDIO_USE_OUTBOUND_PCIS;
  3337. init_data.input_sbal_addr_array = (void **) in_sbal_ptrs;
  3338. init_data.output_sbal_addr_array = (void **) out_sbal_ptrs;
  3339. if (atomic_cmpxchg(&card->qdio.state, QETH_QDIO_ALLOCATED,
  3340. QETH_QDIO_ESTABLISHED) == QETH_QDIO_ALLOCATED) {
  3341. rc = qdio_initialize(&init_data);
  3342. if (rc)
  3343. atomic_set(&card->qdio.state, QETH_QDIO_ALLOCATED);
  3344. }
  3345. kfree(out_sbal_ptrs);
  3346. kfree(in_sbal_ptrs);
  3347. kfree(qib_param_field);
  3348. return rc;
  3349. }
  3350. static void qeth_core_free_card(struct qeth_card *card)
  3351. {
  3352. QETH_DBF_TEXT(SETUP, 2, "freecrd");
  3353. QETH_DBF_HEX(SETUP, 2, &card, sizeof(void *));
  3354. qeth_clean_channel(&card->read);
  3355. qeth_clean_channel(&card->write);
  3356. if (card->dev)
  3357. free_netdev(card->dev);
  3358. kfree(card->ip_tbd_list);
  3359. qeth_free_qdio_buffers(card);
  3360. kfree(card);
  3361. }
  3362. static struct ccw_device_id qeth_ids[] = {
  3363. {CCW_DEVICE(0x1731, 0x01), .driver_info = QETH_CARD_TYPE_OSAE},
  3364. {CCW_DEVICE(0x1731, 0x05), .driver_info = QETH_CARD_TYPE_IQD},
  3365. {CCW_DEVICE(0x1731, 0x06), .driver_info = QETH_CARD_TYPE_OSN},
  3366. {},
  3367. };
  3368. MODULE_DEVICE_TABLE(ccw, qeth_ids);
  3369. static struct ccw_driver qeth_ccw_driver = {
  3370. .name = "qeth",
  3371. .ids = qeth_ids,
  3372. .probe = ccwgroup_probe_ccwdev,
  3373. .remove = ccwgroup_remove_ccwdev,
  3374. };
  3375. static int qeth_core_driver_group(const char *buf, struct device *root_dev,
  3376. unsigned long driver_id)
  3377. {
  3378. return ccwgroup_create_from_string(root_dev, driver_id,
  3379. &qeth_ccw_driver, 3, buf);
  3380. }
  3381. int qeth_core_hardsetup_card(struct qeth_card *card)
  3382. {
  3383. struct qdio_ssqd_desc *ssqd;
  3384. int retries = 3;
  3385. int mpno = 0;
  3386. int rc;
  3387. QETH_DBF_TEXT(SETUP, 2, "hrdsetup");
  3388. atomic_set(&card->force_alloc_skb, 0);
  3389. retry:
  3390. if (retries < 3) {
  3391. PRINT_WARN("Retrying to do IDX activates.\n");
  3392. ccw_device_set_offline(CARD_DDEV(card));
  3393. ccw_device_set_offline(CARD_WDEV(card));
  3394. ccw_device_set_offline(CARD_RDEV(card));
  3395. ccw_device_set_online(CARD_RDEV(card));
  3396. ccw_device_set_online(CARD_WDEV(card));
  3397. ccw_device_set_online(CARD_DDEV(card));
  3398. }
  3399. rc = qeth_qdio_clear_card(card, card->info.type != QETH_CARD_TYPE_IQD);
  3400. if (rc == -ERESTARTSYS) {
  3401. QETH_DBF_TEXT(SETUP, 2, "break1");
  3402. return rc;
  3403. } else if (rc) {
  3404. QETH_DBF_TEXT_(SETUP, 2, "1err%d", rc);
  3405. if (--retries < 0)
  3406. goto out;
  3407. else
  3408. goto retry;
  3409. }
  3410. rc = qeth_get_unitaddr(card);
  3411. if (rc) {
  3412. QETH_DBF_TEXT_(SETUP, 2, "2err%d", rc);
  3413. return rc;
  3414. }
  3415. ssqd = kmalloc(sizeof(struct qdio_ssqd_desc), GFP_KERNEL);
  3416. if (!ssqd) {
  3417. rc = -ENOMEM;
  3418. goto out;
  3419. }
  3420. rc = qdio_get_ssqd_desc(CARD_DDEV(card), ssqd);
  3421. if (rc == 0)
  3422. mpno = ssqd->pcnt;
  3423. kfree(ssqd);
  3424. if (mpno)
  3425. mpno = min(mpno - 1, QETH_MAX_PORTNO);
  3426. if (card->info.portno > mpno) {
  3427. QETH_DBF_MESSAGE(2, "Device %s does not offer port number %d"
  3428. "\n.", CARD_BUS_ID(card), card->info.portno);
  3429. rc = -ENODEV;
  3430. goto out;
  3431. }
  3432. qeth_init_tokens(card);
  3433. qeth_init_func_level(card);
  3434. rc = qeth_idx_activate_channel(&card->read, qeth_idx_read_cb);
  3435. if (rc == -ERESTARTSYS) {
  3436. QETH_DBF_TEXT(SETUP, 2, "break2");
  3437. return rc;
  3438. } else if (rc) {
  3439. QETH_DBF_TEXT_(SETUP, 2, "3err%d", rc);
  3440. if (--retries < 0)
  3441. goto out;
  3442. else
  3443. goto retry;
  3444. }
  3445. rc = qeth_idx_activate_channel(&card->write, qeth_idx_write_cb);
  3446. if (rc == -ERESTARTSYS) {
  3447. QETH_DBF_TEXT(SETUP, 2, "break3");
  3448. return rc;
  3449. } else if (rc) {
  3450. QETH_DBF_TEXT_(SETUP, 2, "4err%d", rc);
  3451. if (--retries < 0)
  3452. goto out;
  3453. else
  3454. goto retry;
  3455. }
  3456. rc = qeth_mpc_initialize(card);
  3457. if (rc) {
  3458. QETH_DBF_TEXT_(SETUP, 2, "5err%d", rc);
  3459. goto out;
  3460. }
  3461. return 0;
  3462. out:
  3463. PRINT_ERR("Initialization in hardsetup failed! rc=%d\n", rc);
  3464. return rc;
  3465. }
  3466. EXPORT_SYMBOL_GPL(qeth_core_hardsetup_card);
  3467. static inline int qeth_create_skb_frag(struct qdio_buffer_element *element,
  3468. struct sk_buff **pskb, int offset, int *pfrag, int data_len)
  3469. {
  3470. struct page *page = virt_to_page(element->addr);
  3471. if (*pskb == NULL) {
  3472. /* the upper protocol layers assume that there is data in the
  3473. * skb itself. Copy a small amount (64 bytes) to make them
  3474. * happy. */
  3475. *pskb = dev_alloc_skb(64 + ETH_HLEN);
  3476. if (!(*pskb))
  3477. return -ENOMEM;
  3478. skb_reserve(*pskb, ETH_HLEN);
  3479. if (data_len <= 64) {
  3480. memcpy(skb_put(*pskb, data_len), element->addr + offset,
  3481. data_len);
  3482. } else {
  3483. get_page(page);
  3484. memcpy(skb_put(*pskb, 64), element->addr + offset, 64);
  3485. skb_fill_page_desc(*pskb, *pfrag, page, offset + 64,
  3486. data_len - 64);
  3487. (*pskb)->data_len += data_len - 64;
  3488. (*pskb)->len += data_len - 64;
  3489. (*pskb)->truesize += data_len - 64;
  3490. (*pfrag)++;
  3491. }
  3492. } else {
  3493. get_page(page);
  3494. skb_fill_page_desc(*pskb, *pfrag, page, offset, data_len);
  3495. (*pskb)->data_len += data_len;
  3496. (*pskb)->len += data_len;
  3497. (*pskb)->truesize += data_len;
  3498. (*pfrag)++;
  3499. }
  3500. return 0;
  3501. }
  3502. struct sk_buff *qeth_core_get_next_skb(struct qeth_card *card,
  3503. struct qdio_buffer *buffer,
  3504. struct qdio_buffer_element **__element, int *__offset,
  3505. struct qeth_hdr **hdr)
  3506. {
  3507. struct qdio_buffer_element *element = *__element;
  3508. int offset = *__offset;
  3509. struct sk_buff *skb = NULL;
  3510. int skb_len;
  3511. void *data_ptr;
  3512. int data_len;
  3513. int headroom = 0;
  3514. int use_rx_sg = 0;
  3515. int frag = 0;
  3516. /* qeth_hdr must not cross element boundaries */
  3517. if (element->length < offset + sizeof(struct qeth_hdr)) {
  3518. if (qeth_is_last_sbale(element))
  3519. return NULL;
  3520. element++;
  3521. offset = 0;
  3522. if (element->length < sizeof(struct qeth_hdr))
  3523. return NULL;
  3524. }
  3525. *hdr = element->addr + offset;
  3526. offset += sizeof(struct qeth_hdr);
  3527. if (card->options.layer2) {
  3528. if (card->info.type == QETH_CARD_TYPE_OSN) {
  3529. skb_len = (*hdr)->hdr.osn.pdu_length;
  3530. headroom = sizeof(struct qeth_hdr);
  3531. } else {
  3532. skb_len = (*hdr)->hdr.l2.pkt_length;
  3533. }
  3534. } else {
  3535. skb_len = (*hdr)->hdr.l3.length;
  3536. if ((card->info.link_type == QETH_LINK_TYPE_LANE_TR) ||
  3537. (card->info.link_type == QETH_LINK_TYPE_HSTR))
  3538. headroom = TR_HLEN;
  3539. else
  3540. headroom = ETH_HLEN;
  3541. }
  3542. if (!skb_len)
  3543. return NULL;
  3544. if ((skb_len >= card->options.rx_sg_cb) &&
  3545. (!(card->info.type == QETH_CARD_TYPE_OSN)) &&
  3546. (!atomic_read(&card->force_alloc_skb))) {
  3547. use_rx_sg = 1;
  3548. } else {
  3549. skb = dev_alloc_skb(skb_len + headroom);
  3550. if (!skb)
  3551. goto no_mem;
  3552. if (headroom)
  3553. skb_reserve(skb, headroom);
  3554. }
  3555. data_ptr = element->addr + offset;
  3556. while (skb_len) {
  3557. data_len = min(skb_len, (int)(element->length - offset));
  3558. if (data_len) {
  3559. if (use_rx_sg) {
  3560. if (qeth_create_skb_frag(element, &skb, offset,
  3561. &frag, data_len))
  3562. goto no_mem;
  3563. } else {
  3564. memcpy(skb_put(skb, data_len), data_ptr,
  3565. data_len);
  3566. }
  3567. }
  3568. skb_len -= data_len;
  3569. if (skb_len) {
  3570. if (qeth_is_last_sbale(element)) {
  3571. QETH_DBF_TEXT(TRACE, 4, "unexeob");
  3572. QETH_DBF_TEXT_(TRACE, 4, "%s",
  3573. CARD_BUS_ID(card));
  3574. QETH_DBF_TEXT(QERR, 2, "unexeob");
  3575. QETH_DBF_TEXT_(QERR, 2, "%s",
  3576. CARD_BUS_ID(card));
  3577. QETH_DBF_HEX(MISC, 4, buffer, sizeof(*buffer));
  3578. dev_kfree_skb_any(skb);
  3579. card->stats.rx_errors++;
  3580. return NULL;
  3581. }
  3582. element++;
  3583. offset = 0;
  3584. data_ptr = element->addr;
  3585. } else {
  3586. offset += data_len;
  3587. }
  3588. }
  3589. *__element = element;
  3590. *__offset = offset;
  3591. if (use_rx_sg && card->options.performance_stats) {
  3592. card->perf_stats.sg_skbs_rx++;
  3593. card->perf_stats.sg_frags_rx += skb_shinfo(skb)->nr_frags;
  3594. }
  3595. return skb;
  3596. no_mem:
  3597. if (net_ratelimit()) {
  3598. QETH_DBF_TEXT(TRACE, 2, "noskbmem");
  3599. QETH_DBF_TEXT_(TRACE, 2, "%s", CARD_BUS_ID(card));
  3600. }
  3601. card->stats.rx_dropped++;
  3602. return NULL;
  3603. }
  3604. EXPORT_SYMBOL_GPL(qeth_core_get_next_skb);
  3605. static void qeth_unregister_dbf_views(void)
  3606. {
  3607. int x;
  3608. for (x = 0; x < QETH_DBF_INFOS; x++) {
  3609. debug_unregister(qeth_dbf[x].id);
  3610. qeth_dbf[x].id = NULL;
  3611. }
  3612. }
  3613. void qeth_dbf_longtext(enum qeth_dbf_names dbf_nix, int level, char *fmt, ...)
  3614. {
  3615. char dbf_txt_buf[32];
  3616. va_list args;
  3617. if (level > (qeth_dbf[dbf_nix].id)->level)
  3618. return;
  3619. va_start(args, fmt);
  3620. vsnprintf(dbf_txt_buf, sizeof(dbf_txt_buf), fmt, args);
  3621. va_end(args);
  3622. debug_text_event(qeth_dbf[dbf_nix].id, level, dbf_txt_buf);
  3623. }
  3624. EXPORT_SYMBOL_GPL(qeth_dbf_longtext);
  3625. static int qeth_register_dbf_views(void)
  3626. {
  3627. int ret;
  3628. int x;
  3629. for (x = 0; x < QETH_DBF_INFOS; x++) {
  3630. /* register the areas */
  3631. qeth_dbf[x].id = debug_register(qeth_dbf[x].name,
  3632. qeth_dbf[x].pages,
  3633. qeth_dbf[x].areas,
  3634. qeth_dbf[x].len);
  3635. if (qeth_dbf[x].id == NULL) {
  3636. qeth_unregister_dbf_views();
  3637. return -ENOMEM;
  3638. }
  3639. /* register a view */
  3640. ret = debug_register_view(qeth_dbf[x].id, qeth_dbf[x].view);
  3641. if (ret) {
  3642. qeth_unregister_dbf_views();
  3643. return ret;
  3644. }
  3645. /* set a passing level */
  3646. debug_set_level(qeth_dbf[x].id, qeth_dbf[x].level);
  3647. }
  3648. return 0;
  3649. }
  3650. int qeth_core_load_discipline(struct qeth_card *card,
  3651. enum qeth_discipline_id discipline)
  3652. {
  3653. int rc = 0;
  3654. switch (discipline) {
  3655. case QETH_DISCIPLINE_LAYER3:
  3656. card->discipline.ccwgdriver = try_then_request_module(
  3657. symbol_get(qeth_l3_ccwgroup_driver),
  3658. "qeth_l3");
  3659. break;
  3660. case QETH_DISCIPLINE_LAYER2:
  3661. card->discipline.ccwgdriver = try_then_request_module(
  3662. symbol_get(qeth_l2_ccwgroup_driver),
  3663. "qeth_l2");
  3664. break;
  3665. }
  3666. if (!card->discipline.ccwgdriver) {
  3667. PRINT_ERR("Support for discipline %d not present\n",
  3668. discipline);
  3669. rc = -EINVAL;
  3670. }
  3671. return rc;
  3672. }
  3673. void qeth_core_free_discipline(struct qeth_card *card)
  3674. {
  3675. if (card->options.layer2)
  3676. symbol_put(qeth_l2_ccwgroup_driver);
  3677. else
  3678. symbol_put(qeth_l3_ccwgroup_driver);
  3679. card->discipline.ccwgdriver = NULL;
  3680. }
  3681. static int qeth_core_probe_device(struct ccwgroup_device *gdev)
  3682. {
  3683. struct qeth_card *card;
  3684. struct device *dev;
  3685. int rc;
  3686. unsigned long flags;
  3687. QETH_DBF_TEXT(SETUP, 2, "probedev");
  3688. dev = &gdev->dev;
  3689. if (!get_device(dev))
  3690. return -ENODEV;
  3691. QETH_DBF_TEXT_(SETUP, 2, "%s", dev_name(&gdev->dev));
  3692. card = qeth_alloc_card();
  3693. if (!card) {
  3694. QETH_DBF_TEXT_(SETUP, 2, "1err%d", -ENOMEM);
  3695. rc = -ENOMEM;
  3696. goto err_dev;
  3697. }
  3698. card->read.ccwdev = gdev->cdev[0];
  3699. card->write.ccwdev = gdev->cdev[1];
  3700. card->data.ccwdev = gdev->cdev[2];
  3701. dev_set_drvdata(&gdev->dev, card);
  3702. card->gdev = gdev;
  3703. gdev->cdev[0]->handler = qeth_irq;
  3704. gdev->cdev[1]->handler = qeth_irq;
  3705. gdev->cdev[2]->handler = qeth_irq;
  3706. rc = qeth_determine_card_type(card);
  3707. if (rc) {
  3708. QETH_DBF_TEXT_(SETUP, 2, "3err%d", rc);
  3709. goto err_card;
  3710. }
  3711. rc = qeth_setup_card(card);
  3712. if (rc) {
  3713. QETH_DBF_TEXT_(SETUP, 2, "2err%d", rc);
  3714. goto err_card;
  3715. }
  3716. if (card->info.type == QETH_CARD_TYPE_OSN) {
  3717. rc = qeth_core_create_osn_attributes(dev);
  3718. if (rc)
  3719. goto err_card;
  3720. rc = qeth_core_load_discipline(card, QETH_DISCIPLINE_LAYER2);
  3721. if (rc) {
  3722. qeth_core_remove_osn_attributes(dev);
  3723. goto err_card;
  3724. }
  3725. rc = card->discipline.ccwgdriver->probe(card->gdev);
  3726. if (rc) {
  3727. qeth_core_free_discipline(card);
  3728. qeth_core_remove_osn_attributes(dev);
  3729. goto err_card;
  3730. }
  3731. } else {
  3732. rc = qeth_core_create_device_attributes(dev);
  3733. if (rc)
  3734. goto err_card;
  3735. }
  3736. write_lock_irqsave(&qeth_core_card_list.rwlock, flags);
  3737. list_add_tail(&card->list, &qeth_core_card_list.list);
  3738. write_unlock_irqrestore(&qeth_core_card_list.rwlock, flags);
  3739. return 0;
  3740. err_card:
  3741. qeth_core_free_card(card);
  3742. err_dev:
  3743. put_device(dev);
  3744. return rc;
  3745. }
  3746. static void qeth_core_remove_device(struct ccwgroup_device *gdev)
  3747. {
  3748. unsigned long flags;
  3749. struct qeth_card *card = dev_get_drvdata(&gdev->dev);
  3750. QETH_DBF_TEXT(SETUP, 2, "removedv");
  3751. if (card->discipline.ccwgdriver) {
  3752. card->discipline.ccwgdriver->remove(gdev);
  3753. qeth_core_free_discipline(card);
  3754. }
  3755. if (card->info.type == QETH_CARD_TYPE_OSN) {
  3756. qeth_core_remove_osn_attributes(&gdev->dev);
  3757. } else {
  3758. qeth_core_remove_device_attributes(&gdev->dev);
  3759. }
  3760. write_lock_irqsave(&qeth_core_card_list.rwlock, flags);
  3761. list_del(&card->list);
  3762. write_unlock_irqrestore(&qeth_core_card_list.rwlock, flags);
  3763. qeth_core_free_card(card);
  3764. dev_set_drvdata(&gdev->dev, NULL);
  3765. put_device(&gdev->dev);
  3766. return;
  3767. }
  3768. static int qeth_core_set_online(struct ccwgroup_device *gdev)
  3769. {
  3770. struct qeth_card *card = dev_get_drvdata(&gdev->dev);
  3771. int rc = 0;
  3772. int def_discipline;
  3773. if (!card->discipline.ccwgdriver) {
  3774. if (card->info.type == QETH_CARD_TYPE_IQD)
  3775. def_discipline = QETH_DISCIPLINE_LAYER3;
  3776. else
  3777. def_discipline = QETH_DISCIPLINE_LAYER2;
  3778. rc = qeth_core_load_discipline(card, def_discipline);
  3779. if (rc)
  3780. goto err;
  3781. rc = card->discipline.ccwgdriver->probe(card->gdev);
  3782. if (rc)
  3783. goto err;
  3784. }
  3785. rc = card->discipline.ccwgdriver->set_online(gdev);
  3786. err:
  3787. return rc;
  3788. }
  3789. static int qeth_core_set_offline(struct ccwgroup_device *gdev)
  3790. {
  3791. struct qeth_card *card = dev_get_drvdata(&gdev->dev);
  3792. return card->discipline.ccwgdriver->set_offline(gdev);
  3793. }
  3794. static void qeth_core_shutdown(struct ccwgroup_device *gdev)
  3795. {
  3796. struct qeth_card *card = dev_get_drvdata(&gdev->dev);
  3797. if (card->discipline.ccwgdriver &&
  3798. card->discipline.ccwgdriver->shutdown)
  3799. card->discipline.ccwgdriver->shutdown(gdev);
  3800. }
  3801. static struct ccwgroup_driver qeth_core_ccwgroup_driver = {
  3802. .owner = THIS_MODULE,
  3803. .name = "qeth",
  3804. .driver_id = 0xD8C5E3C8,
  3805. .probe = qeth_core_probe_device,
  3806. .remove = qeth_core_remove_device,
  3807. .set_online = qeth_core_set_online,
  3808. .set_offline = qeth_core_set_offline,
  3809. .shutdown = qeth_core_shutdown,
  3810. };
  3811. static ssize_t
  3812. qeth_core_driver_group_store(struct device_driver *ddrv, const char *buf,
  3813. size_t count)
  3814. {
  3815. int err;
  3816. err = qeth_core_driver_group(buf, qeth_core_root_dev,
  3817. qeth_core_ccwgroup_driver.driver_id);
  3818. if (err)
  3819. return err;
  3820. else
  3821. return count;
  3822. }
  3823. static DRIVER_ATTR(group, 0200, NULL, qeth_core_driver_group_store);
  3824. static struct {
  3825. const char str[ETH_GSTRING_LEN];
  3826. } qeth_ethtool_stats_keys[] = {
  3827. /* 0 */{"rx skbs"},
  3828. {"rx buffers"},
  3829. {"tx skbs"},
  3830. {"tx buffers"},
  3831. {"tx skbs no packing"},
  3832. {"tx buffers no packing"},
  3833. {"tx skbs packing"},
  3834. {"tx buffers packing"},
  3835. {"tx sg skbs"},
  3836. {"tx sg frags"},
  3837. /* 10 */{"rx sg skbs"},
  3838. {"rx sg frags"},
  3839. {"rx sg page allocs"},
  3840. {"tx large kbytes"},
  3841. {"tx large count"},
  3842. {"tx pk state ch n->p"},
  3843. {"tx pk state ch p->n"},
  3844. {"tx pk watermark low"},
  3845. {"tx pk watermark high"},
  3846. {"queue 0 buffer usage"},
  3847. /* 20 */{"queue 1 buffer usage"},
  3848. {"queue 2 buffer usage"},
  3849. {"queue 3 buffer usage"},
  3850. {"rx handler time"},
  3851. {"rx handler count"},
  3852. {"rx do_QDIO time"},
  3853. {"rx do_QDIO count"},
  3854. {"tx handler time"},
  3855. {"tx handler count"},
  3856. {"tx time"},
  3857. /* 30 */{"tx count"},
  3858. {"tx do_QDIO time"},
  3859. {"tx do_QDIO count"},
  3860. };
  3861. int qeth_core_get_stats_count(struct net_device *dev)
  3862. {
  3863. return (sizeof(qeth_ethtool_stats_keys) / ETH_GSTRING_LEN);
  3864. }
  3865. EXPORT_SYMBOL_GPL(qeth_core_get_stats_count);
  3866. void qeth_core_get_ethtool_stats(struct net_device *dev,
  3867. struct ethtool_stats *stats, u64 *data)
  3868. {
  3869. struct qeth_card *card = dev->ml_priv;
  3870. data[0] = card->stats.rx_packets -
  3871. card->perf_stats.initial_rx_packets;
  3872. data[1] = card->perf_stats.bufs_rec;
  3873. data[2] = card->stats.tx_packets -
  3874. card->perf_stats.initial_tx_packets;
  3875. data[3] = card->perf_stats.bufs_sent;
  3876. data[4] = card->stats.tx_packets - card->perf_stats.initial_tx_packets
  3877. - card->perf_stats.skbs_sent_pack;
  3878. data[5] = card->perf_stats.bufs_sent - card->perf_stats.bufs_sent_pack;
  3879. data[6] = card->perf_stats.skbs_sent_pack;
  3880. data[7] = card->perf_stats.bufs_sent_pack;
  3881. data[8] = card->perf_stats.sg_skbs_sent;
  3882. data[9] = card->perf_stats.sg_frags_sent;
  3883. data[10] = card->perf_stats.sg_skbs_rx;
  3884. data[11] = card->perf_stats.sg_frags_rx;
  3885. data[12] = card->perf_stats.sg_alloc_page_rx;
  3886. data[13] = (card->perf_stats.large_send_bytes >> 10);
  3887. data[14] = card->perf_stats.large_send_cnt;
  3888. data[15] = card->perf_stats.sc_dp_p;
  3889. data[16] = card->perf_stats.sc_p_dp;
  3890. data[17] = QETH_LOW_WATERMARK_PACK;
  3891. data[18] = QETH_HIGH_WATERMARK_PACK;
  3892. data[19] = atomic_read(&card->qdio.out_qs[0]->used_buffers);
  3893. data[20] = (card->qdio.no_out_queues > 1) ?
  3894. atomic_read(&card->qdio.out_qs[1]->used_buffers) : 0;
  3895. data[21] = (card->qdio.no_out_queues > 2) ?
  3896. atomic_read(&card->qdio.out_qs[2]->used_buffers) : 0;
  3897. data[22] = (card->qdio.no_out_queues > 3) ?
  3898. atomic_read(&card->qdio.out_qs[3]->used_buffers) : 0;
  3899. data[23] = card->perf_stats.inbound_time;
  3900. data[24] = card->perf_stats.inbound_cnt;
  3901. data[25] = card->perf_stats.inbound_do_qdio_time;
  3902. data[26] = card->perf_stats.inbound_do_qdio_cnt;
  3903. data[27] = card->perf_stats.outbound_handler_time;
  3904. data[28] = card->perf_stats.outbound_handler_cnt;
  3905. data[29] = card->perf_stats.outbound_time;
  3906. data[30] = card->perf_stats.outbound_cnt;
  3907. data[31] = card->perf_stats.outbound_do_qdio_time;
  3908. data[32] = card->perf_stats.outbound_do_qdio_cnt;
  3909. }
  3910. EXPORT_SYMBOL_GPL(qeth_core_get_ethtool_stats);
  3911. void qeth_core_get_strings(struct net_device *dev, u32 stringset, u8 *data)
  3912. {
  3913. switch (stringset) {
  3914. case ETH_SS_STATS:
  3915. memcpy(data, &qeth_ethtool_stats_keys,
  3916. sizeof(qeth_ethtool_stats_keys));
  3917. break;
  3918. default:
  3919. WARN_ON(1);
  3920. break;
  3921. }
  3922. }
  3923. EXPORT_SYMBOL_GPL(qeth_core_get_strings);
  3924. void qeth_core_get_drvinfo(struct net_device *dev,
  3925. struct ethtool_drvinfo *info)
  3926. {
  3927. struct qeth_card *card = dev->ml_priv;
  3928. if (card->options.layer2)
  3929. strcpy(info->driver, "qeth_l2");
  3930. else
  3931. strcpy(info->driver, "qeth_l3");
  3932. strcpy(info->version, "1.0");
  3933. strcpy(info->fw_version, card->info.mcl_level);
  3934. sprintf(info->bus_info, "%s/%s/%s",
  3935. CARD_RDEV_ID(card),
  3936. CARD_WDEV_ID(card),
  3937. CARD_DDEV_ID(card));
  3938. }
  3939. EXPORT_SYMBOL_GPL(qeth_core_get_drvinfo);
  3940. int qeth_core_ethtool_get_settings(struct net_device *netdev,
  3941. struct ethtool_cmd *ecmd)
  3942. {
  3943. struct qeth_card *card = netdev->ml_priv;
  3944. enum qeth_link_types link_type;
  3945. if ((card->info.type == QETH_CARD_TYPE_IQD) || (card->info.guestlan))
  3946. link_type = QETH_LINK_TYPE_10GBIT_ETH;
  3947. else
  3948. link_type = card->info.link_type;
  3949. ecmd->transceiver = XCVR_INTERNAL;
  3950. ecmd->supported = SUPPORTED_Autoneg;
  3951. ecmd->advertising = ADVERTISED_Autoneg;
  3952. ecmd->duplex = DUPLEX_FULL;
  3953. ecmd->autoneg = AUTONEG_ENABLE;
  3954. switch (link_type) {
  3955. case QETH_LINK_TYPE_FAST_ETH:
  3956. case QETH_LINK_TYPE_LANE_ETH100:
  3957. ecmd->supported |= SUPPORTED_10baseT_Half |
  3958. SUPPORTED_10baseT_Full |
  3959. SUPPORTED_100baseT_Half |
  3960. SUPPORTED_100baseT_Full |
  3961. SUPPORTED_TP;
  3962. ecmd->advertising |= ADVERTISED_10baseT_Half |
  3963. ADVERTISED_10baseT_Full |
  3964. ADVERTISED_100baseT_Half |
  3965. ADVERTISED_100baseT_Full |
  3966. ADVERTISED_TP;
  3967. ecmd->speed = SPEED_100;
  3968. ecmd->port = PORT_TP;
  3969. break;
  3970. case QETH_LINK_TYPE_GBIT_ETH:
  3971. case QETH_LINK_TYPE_LANE_ETH1000:
  3972. ecmd->supported |= SUPPORTED_10baseT_Half |
  3973. SUPPORTED_10baseT_Full |
  3974. SUPPORTED_100baseT_Half |
  3975. SUPPORTED_100baseT_Full |
  3976. SUPPORTED_1000baseT_Half |
  3977. SUPPORTED_1000baseT_Full |
  3978. SUPPORTED_FIBRE;
  3979. ecmd->advertising |= ADVERTISED_10baseT_Half |
  3980. ADVERTISED_10baseT_Full |
  3981. ADVERTISED_100baseT_Half |
  3982. ADVERTISED_100baseT_Full |
  3983. ADVERTISED_1000baseT_Half |
  3984. ADVERTISED_1000baseT_Full |
  3985. ADVERTISED_FIBRE;
  3986. ecmd->speed = SPEED_1000;
  3987. ecmd->port = PORT_FIBRE;
  3988. break;
  3989. case QETH_LINK_TYPE_10GBIT_ETH:
  3990. ecmd->supported |= SUPPORTED_10baseT_Half |
  3991. SUPPORTED_10baseT_Full |
  3992. SUPPORTED_100baseT_Half |
  3993. SUPPORTED_100baseT_Full |
  3994. SUPPORTED_1000baseT_Half |
  3995. SUPPORTED_1000baseT_Full |
  3996. SUPPORTED_10000baseT_Full |
  3997. SUPPORTED_FIBRE;
  3998. ecmd->advertising |= ADVERTISED_10baseT_Half |
  3999. ADVERTISED_10baseT_Full |
  4000. ADVERTISED_100baseT_Half |
  4001. ADVERTISED_100baseT_Full |
  4002. ADVERTISED_1000baseT_Half |
  4003. ADVERTISED_1000baseT_Full |
  4004. ADVERTISED_10000baseT_Full |
  4005. ADVERTISED_FIBRE;
  4006. ecmd->speed = SPEED_10000;
  4007. ecmd->port = PORT_FIBRE;
  4008. break;
  4009. default:
  4010. ecmd->supported |= SUPPORTED_10baseT_Half |
  4011. SUPPORTED_10baseT_Full |
  4012. SUPPORTED_TP;
  4013. ecmd->advertising |= ADVERTISED_10baseT_Half |
  4014. ADVERTISED_10baseT_Full |
  4015. ADVERTISED_TP;
  4016. ecmd->speed = SPEED_10;
  4017. ecmd->port = PORT_TP;
  4018. }
  4019. return 0;
  4020. }
  4021. EXPORT_SYMBOL_GPL(qeth_core_ethtool_get_settings);
  4022. static int __init qeth_core_init(void)
  4023. {
  4024. int rc;
  4025. PRINT_INFO("loading core functions\n");
  4026. INIT_LIST_HEAD(&qeth_core_card_list.list);
  4027. rwlock_init(&qeth_core_card_list.rwlock);
  4028. rc = qeth_register_dbf_views();
  4029. if (rc)
  4030. goto out_err;
  4031. rc = ccw_driver_register(&qeth_ccw_driver);
  4032. if (rc)
  4033. goto ccw_err;
  4034. rc = ccwgroup_driver_register(&qeth_core_ccwgroup_driver);
  4035. if (rc)
  4036. goto ccwgroup_err;
  4037. rc = driver_create_file(&qeth_core_ccwgroup_driver.driver,
  4038. &driver_attr_group);
  4039. if (rc)
  4040. goto driver_err;
  4041. qeth_core_root_dev = s390_root_dev_register("qeth");
  4042. rc = IS_ERR(qeth_core_root_dev) ? PTR_ERR(qeth_core_root_dev) : 0;
  4043. if (rc)
  4044. goto register_err;
  4045. qeth_core_header_cache = kmem_cache_create("qeth_hdr",
  4046. sizeof(struct qeth_hdr) + ETH_HLEN, 64, 0, NULL);
  4047. if (!qeth_core_header_cache) {
  4048. rc = -ENOMEM;
  4049. goto slab_err;
  4050. }
  4051. return 0;
  4052. slab_err:
  4053. s390_root_dev_unregister(qeth_core_root_dev);
  4054. register_err:
  4055. driver_remove_file(&qeth_core_ccwgroup_driver.driver,
  4056. &driver_attr_group);
  4057. driver_err:
  4058. ccwgroup_driver_unregister(&qeth_core_ccwgroup_driver);
  4059. ccwgroup_err:
  4060. ccw_driver_unregister(&qeth_ccw_driver);
  4061. ccw_err:
  4062. qeth_unregister_dbf_views();
  4063. out_err:
  4064. PRINT_ERR("Initialization failed with code %d\n", rc);
  4065. return rc;
  4066. }
  4067. static void __exit qeth_core_exit(void)
  4068. {
  4069. s390_root_dev_unregister(qeth_core_root_dev);
  4070. driver_remove_file(&qeth_core_ccwgroup_driver.driver,
  4071. &driver_attr_group);
  4072. ccwgroup_driver_unregister(&qeth_core_ccwgroup_driver);
  4073. ccw_driver_unregister(&qeth_ccw_driver);
  4074. kmem_cache_destroy(qeth_core_header_cache);
  4075. qeth_unregister_dbf_views();
  4076. PRINT_INFO("core functions removed\n");
  4077. }
  4078. module_init(qeth_core_init);
  4079. module_exit(qeth_core_exit);
  4080. MODULE_AUTHOR("Frank Blaschka <frank.blaschka@de.ibm.com>");
  4081. MODULE_DESCRIPTION("qeth core functions");
  4082. MODULE_LICENSE("GPL");