rt2800pci.c 39 KB

1234567891011121314151617181920212223242526272829303132333435363738394041424344454647484950515253545556575859606162636465666768697071727374757677787980818283848586878889909192939495969798991001011021031041051061071081091101111121131141151161171181191201211221231241251261271281291301311321331341351361371381391401411421431441451461471481491501511521531541551561571581591601611621631641651661671681691701711721731741751761771781791801811821831841851861871881891901911921931941951961971981992002012022032042052062072082092102112122132142152162172182192202212222232242252262272282292302312322332342352362372382392402412422432442452462472482492502512522532542552562572582592602612622632642652662672682692702712722732742752762772782792802812822832842852862872882892902912922932942952962972982993003013023033043053063073083093103113123133143153163173183193203213223233243253263273283293303313323333343353363373383393403413423433443453463473483493503513523533543553563573583593603613623633643653663673683693703713723733743753763773783793803813823833843853863873883893903913923933943953963973983994004014024034044054064074084094104114124134144154164174184194204214224234244254264274284294304314324334344354364374384394404414424434444454464474484494504514524534544554564574584594604614624634644654664674684694704714724734744754764774784794804814824834844854864874884894904914924934944954964974984995005015025035045055065075085095105115125135145155165175185195205215225235245255265275285295305315325335345355365375385395405415425435445455465475485495505515525535545555565575585595605615625635645655665675685695705715725735745755765775785795805815825835845855865875885895905915925935945955965975985996006016026036046056066076086096106116126136146156166176186196206216226236246256266276286296306316326336346356366376386396406416426436446456466476486496506516526536546556566576586596606616626636646656666676686696706716726736746756766776786796806816826836846856866876886896906916926936946956966976986997007017027037047057067077087097107117127137147157167177187197207217227237247257267277287297307317327337347357367377387397407417427437447457467477487497507517527537547557567577587597607617627637647657667677687697707717727737747757767777787797807817827837847857867877887897907917927937947957967977987998008018028038048058068078088098108118128138148158168178188198208218228238248258268278288298308318328338348358368378388398408418428438448458468478488498508518528538548558568578588598608618628638648658668678688698708718728738748758768778788798808818828838848858868878888898908918928938948958968978988999009019029039049059069079089099109119129139149159169179189199209219229239249259269279289299309319329339349359369379389399409419429439449459469479489499509519529539549559569579589599609619629639649659669679689699709719729739749759769779789799809819829839849859869879889899909919929939949959969979989991000100110021003100410051006100710081009101010111012101310141015101610171018101910201021102210231024102510261027102810291030103110321033103410351036103710381039104010411042104310441045104610471048104910501051105210531054105510561057105810591060106110621063106410651066106710681069107010711072107310741075107610771078107910801081108210831084108510861087108810891090109110921093109410951096109710981099110011011102110311041105110611071108110911101111111211131114111511161117111811191120112111221123112411251126112711281129113011311132113311341135113611371138113911401141114211431144114511461147114811491150115111521153115411551156115711581159116011611162116311641165116611671168116911701171117211731174117511761177117811791180118111821183118411851186118711881189119011911192119311941195119611971198119912001201120212031204120512061207120812091210121112121213121412151216121712181219122012211222122312241225122612271228122912301231123212331234123512361237123812391240124112421243124412451246124712481249125012511252125312541255125612571258125912601261126212631264126512661267126812691270127112721273127412751276127712781279128012811282128312841285128612871288128912901291129212931294129512961297129812991300130113021303130413051306130713081309131013111312131313141315131613171318131913201321132213231324132513261327132813291330133113321333133413351336133713381339134013411342134313441345134613471348134913501351135213531354135513561357135813591360
  1. /*
  2. Copyright (C) 2009 - 2010 Ivo van Doorn <IvDoorn@gmail.com>
  3. Copyright (C) 2009 Alban Browaeys <prahal@yahoo.com>
  4. Copyright (C) 2009 Felix Fietkau <nbd@openwrt.org>
  5. Copyright (C) 2009 Luis Correia <luis.f.correia@gmail.com>
  6. Copyright (C) 2009 Mattias Nissler <mattias.nissler@gmx.de>
  7. Copyright (C) 2009 Mark Asselstine <asselsm@gmail.com>
  8. Copyright (C) 2009 Xose Vazquez Perez <xose.vazquez@gmail.com>
  9. Copyright (C) 2009 Bart Zolnierkiewicz <bzolnier@gmail.com>
  10. <http://rt2x00.serialmonkey.com>
  11. This program is free software; you can redistribute it and/or modify
  12. it under the terms of the GNU General Public License as published by
  13. the Free Software Foundation; either version 2 of the License, or
  14. (at your option) any later version.
  15. This program is distributed in the hope that it will be useful,
  16. but WITHOUT ANY WARRANTY; without even the implied warranty of
  17. MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  18. GNU General Public License for more details.
  19. You should have received a copy of the GNU General Public License
  20. along with this program; if not, write to the
  21. Free Software Foundation, Inc.,
  22. 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
  23. */
  24. /*
  25. Module: rt2800pci
  26. Abstract: rt2800pci device specific routines.
  27. Supported chipsets: RT2800E & RT2800ED.
  28. */
  29. #include <linux/delay.h>
  30. #include <linux/etherdevice.h>
  31. #include <linux/init.h>
  32. #include <linux/kernel.h>
  33. #include <linux/module.h>
  34. #include <linux/pci.h>
  35. #include <linux/platform_device.h>
  36. #include <linux/eeprom_93cx6.h>
  37. #include "rt2x00.h"
  38. #include "rt2x00mmio.h"
  39. #include "rt2x00pci.h"
  40. #include "rt2x00soc.h"
  41. #include "rt2800lib.h"
  42. #include "rt2800.h"
  43. #include "rt2800pci.h"
  44. /*
  45. * Allow hardware encryption to be disabled.
  46. */
  47. static bool modparam_nohwcrypt = false;
  48. module_param_named(nohwcrypt, modparam_nohwcrypt, bool, S_IRUGO);
  49. MODULE_PARM_DESC(nohwcrypt, "Disable hardware encryption.");
  50. static bool rt2800pci_hwcrypt_disabled(struct rt2x00_dev *rt2x00dev)
  51. {
  52. return modparam_nohwcrypt;
  53. }
  54. static void rt2800pci_mcu_status(struct rt2x00_dev *rt2x00dev, const u8 token)
  55. {
  56. unsigned int i;
  57. u32 reg;
  58. /*
  59. * SOC devices don't support MCU requests.
  60. */
  61. if (rt2x00_is_soc(rt2x00dev))
  62. return;
  63. for (i = 0; i < 200; i++) {
  64. rt2x00pci_register_read(rt2x00dev, H2M_MAILBOX_CID, &reg);
  65. if ((rt2x00_get_field32(reg, H2M_MAILBOX_CID_CMD0) == token) ||
  66. (rt2x00_get_field32(reg, H2M_MAILBOX_CID_CMD1) == token) ||
  67. (rt2x00_get_field32(reg, H2M_MAILBOX_CID_CMD2) == token) ||
  68. (rt2x00_get_field32(reg, H2M_MAILBOX_CID_CMD3) == token))
  69. break;
  70. udelay(REGISTER_BUSY_DELAY);
  71. }
  72. if (i == 200)
  73. ERROR(rt2x00dev, "MCU request failed, no response from hardware\n");
  74. rt2x00pci_register_write(rt2x00dev, H2M_MAILBOX_STATUS, ~0);
  75. rt2x00pci_register_write(rt2x00dev, H2M_MAILBOX_CID, ~0);
  76. }
  77. #if defined(CONFIG_SOC_RT288X) || defined(CONFIG_SOC_RT305X)
  78. static int rt2800pci_read_eeprom_soc(struct rt2x00_dev *rt2x00dev)
  79. {
  80. void __iomem *base_addr = ioremap(0x1F040000, EEPROM_SIZE);
  81. if (!base_addr)
  82. return -ENOMEM;
  83. memcpy_fromio(rt2x00dev->eeprom, base_addr, EEPROM_SIZE);
  84. iounmap(base_addr);
  85. return 0;
  86. }
  87. #else
  88. static inline int rt2800pci_read_eeprom_soc(struct rt2x00_dev *rt2x00dev)
  89. {
  90. return -ENOMEM;
  91. }
  92. #endif /* CONFIG_SOC_RT288X || CONFIG_SOC_RT305X */
  93. #ifdef CONFIG_PCI
  94. static void rt2800pci_eepromregister_read(struct eeprom_93cx6 *eeprom)
  95. {
  96. struct rt2x00_dev *rt2x00dev = eeprom->data;
  97. u32 reg;
  98. rt2x00pci_register_read(rt2x00dev, E2PROM_CSR, &reg);
  99. eeprom->reg_data_in = !!rt2x00_get_field32(reg, E2PROM_CSR_DATA_IN);
  100. eeprom->reg_data_out = !!rt2x00_get_field32(reg, E2PROM_CSR_DATA_OUT);
  101. eeprom->reg_data_clock =
  102. !!rt2x00_get_field32(reg, E2PROM_CSR_DATA_CLOCK);
  103. eeprom->reg_chip_select =
  104. !!rt2x00_get_field32(reg, E2PROM_CSR_CHIP_SELECT);
  105. }
  106. static void rt2800pci_eepromregister_write(struct eeprom_93cx6 *eeprom)
  107. {
  108. struct rt2x00_dev *rt2x00dev = eeprom->data;
  109. u32 reg = 0;
  110. rt2x00_set_field32(&reg, E2PROM_CSR_DATA_IN, !!eeprom->reg_data_in);
  111. rt2x00_set_field32(&reg, E2PROM_CSR_DATA_OUT, !!eeprom->reg_data_out);
  112. rt2x00_set_field32(&reg, E2PROM_CSR_DATA_CLOCK,
  113. !!eeprom->reg_data_clock);
  114. rt2x00_set_field32(&reg, E2PROM_CSR_CHIP_SELECT,
  115. !!eeprom->reg_chip_select);
  116. rt2x00pci_register_write(rt2x00dev, E2PROM_CSR, reg);
  117. }
  118. static int rt2800pci_read_eeprom_pci(struct rt2x00_dev *rt2x00dev)
  119. {
  120. struct eeprom_93cx6 eeprom;
  121. u32 reg;
  122. rt2x00pci_register_read(rt2x00dev, E2PROM_CSR, &reg);
  123. eeprom.data = rt2x00dev;
  124. eeprom.register_read = rt2800pci_eepromregister_read;
  125. eeprom.register_write = rt2800pci_eepromregister_write;
  126. switch (rt2x00_get_field32(reg, E2PROM_CSR_TYPE))
  127. {
  128. case 0:
  129. eeprom.width = PCI_EEPROM_WIDTH_93C46;
  130. break;
  131. case 1:
  132. eeprom.width = PCI_EEPROM_WIDTH_93C66;
  133. break;
  134. default:
  135. eeprom.width = PCI_EEPROM_WIDTH_93C86;
  136. break;
  137. }
  138. eeprom.reg_data_in = 0;
  139. eeprom.reg_data_out = 0;
  140. eeprom.reg_data_clock = 0;
  141. eeprom.reg_chip_select = 0;
  142. eeprom_93cx6_multiread(&eeprom, EEPROM_BASE, rt2x00dev->eeprom,
  143. EEPROM_SIZE / sizeof(u16));
  144. return 0;
  145. }
  146. static int rt2800pci_efuse_detect(struct rt2x00_dev *rt2x00dev)
  147. {
  148. return rt2800_efuse_detect(rt2x00dev);
  149. }
  150. static inline int rt2800pci_read_eeprom_efuse(struct rt2x00_dev *rt2x00dev)
  151. {
  152. return rt2800_read_eeprom_efuse(rt2x00dev);
  153. }
  154. #else
  155. static inline int rt2800pci_read_eeprom_pci(struct rt2x00_dev *rt2x00dev)
  156. {
  157. return -EOPNOTSUPP;
  158. }
  159. static inline int rt2800pci_efuse_detect(struct rt2x00_dev *rt2x00dev)
  160. {
  161. return 0;
  162. }
  163. static inline int rt2800pci_read_eeprom_efuse(struct rt2x00_dev *rt2x00dev)
  164. {
  165. return -EOPNOTSUPP;
  166. }
  167. #endif /* CONFIG_PCI */
  168. /*
  169. * Queue handlers.
  170. */
  171. static void rt2800pci_start_queue(struct data_queue *queue)
  172. {
  173. struct rt2x00_dev *rt2x00dev = queue->rt2x00dev;
  174. u32 reg;
  175. switch (queue->qid) {
  176. case QID_RX:
  177. rt2x00pci_register_read(rt2x00dev, MAC_SYS_CTRL, &reg);
  178. rt2x00_set_field32(&reg, MAC_SYS_CTRL_ENABLE_RX, 1);
  179. rt2x00pci_register_write(rt2x00dev, MAC_SYS_CTRL, reg);
  180. break;
  181. case QID_BEACON:
  182. rt2x00pci_register_read(rt2x00dev, BCN_TIME_CFG, &reg);
  183. rt2x00_set_field32(&reg, BCN_TIME_CFG_TSF_TICKING, 1);
  184. rt2x00_set_field32(&reg, BCN_TIME_CFG_TBTT_ENABLE, 1);
  185. rt2x00_set_field32(&reg, BCN_TIME_CFG_BEACON_GEN, 1);
  186. rt2x00pci_register_write(rt2x00dev, BCN_TIME_CFG, reg);
  187. rt2x00pci_register_read(rt2x00dev, INT_TIMER_EN, &reg);
  188. rt2x00_set_field32(&reg, INT_TIMER_EN_PRE_TBTT_TIMER, 1);
  189. rt2x00pci_register_write(rt2x00dev, INT_TIMER_EN, reg);
  190. break;
  191. default:
  192. break;
  193. }
  194. }
  195. static void rt2800pci_kick_queue(struct data_queue *queue)
  196. {
  197. struct rt2x00_dev *rt2x00dev = queue->rt2x00dev;
  198. struct queue_entry *entry;
  199. switch (queue->qid) {
  200. case QID_AC_VO:
  201. case QID_AC_VI:
  202. case QID_AC_BE:
  203. case QID_AC_BK:
  204. entry = rt2x00queue_get_entry(queue, Q_INDEX);
  205. rt2x00pci_register_write(rt2x00dev, TX_CTX_IDX(queue->qid),
  206. entry->entry_idx);
  207. break;
  208. case QID_MGMT:
  209. entry = rt2x00queue_get_entry(queue, Q_INDEX);
  210. rt2x00pci_register_write(rt2x00dev, TX_CTX_IDX(5),
  211. entry->entry_idx);
  212. break;
  213. default:
  214. break;
  215. }
  216. }
  217. static void rt2800pci_stop_queue(struct data_queue *queue)
  218. {
  219. struct rt2x00_dev *rt2x00dev = queue->rt2x00dev;
  220. u32 reg;
  221. switch (queue->qid) {
  222. case QID_RX:
  223. rt2x00pci_register_read(rt2x00dev, MAC_SYS_CTRL, &reg);
  224. rt2x00_set_field32(&reg, MAC_SYS_CTRL_ENABLE_RX, 0);
  225. rt2x00pci_register_write(rt2x00dev, MAC_SYS_CTRL, reg);
  226. break;
  227. case QID_BEACON:
  228. rt2x00pci_register_read(rt2x00dev, BCN_TIME_CFG, &reg);
  229. rt2x00_set_field32(&reg, BCN_TIME_CFG_TSF_TICKING, 0);
  230. rt2x00_set_field32(&reg, BCN_TIME_CFG_TBTT_ENABLE, 0);
  231. rt2x00_set_field32(&reg, BCN_TIME_CFG_BEACON_GEN, 0);
  232. rt2x00pci_register_write(rt2x00dev, BCN_TIME_CFG, reg);
  233. rt2x00pci_register_read(rt2x00dev, INT_TIMER_EN, &reg);
  234. rt2x00_set_field32(&reg, INT_TIMER_EN_PRE_TBTT_TIMER, 0);
  235. rt2x00pci_register_write(rt2x00dev, INT_TIMER_EN, reg);
  236. /*
  237. * Wait for current invocation to finish. The tasklet
  238. * won't be scheduled anymore afterwards since we disabled
  239. * the TBTT and PRE TBTT timer.
  240. */
  241. tasklet_kill(&rt2x00dev->tbtt_tasklet);
  242. tasklet_kill(&rt2x00dev->pretbtt_tasklet);
  243. break;
  244. default:
  245. break;
  246. }
  247. }
  248. /*
  249. * Firmware functions
  250. */
  251. static char *rt2800pci_get_firmware_name(struct rt2x00_dev *rt2x00dev)
  252. {
  253. /*
  254. * Chip rt3290 use specific 4KB firmware named rt3290.bin.
  255. */
  256. if (rt2x00_rt(rt2x00dev, RT3290))
  257. return FIRMWARE_RT3290;
  258. else
  259. return FIRMWARE_RT2860;
  260. }
  261. static int rt2800pci_write_firmware(struct rt2x00_dev *rt2x00dev,
  262. const u8 *data, const size_t len)
  263. {
  264. u32 reg;
  265. /*
  266. * enable Host program ram write selection
  267. */
  268. reg = 0;
  269. rt2x00_set_field32(&reg, PBF_SYS_CTRL_HOST_RAM_WRITE, 1);
  270. rt2x00pci_register_write(rt2x00dev, PBF_SYS_CTRL, reg);
  271. /*
  272. * Write firmware to device.
  273. */
  274. rt2x00pci_register_multiwrite(rt2x00dev, FIRMWARE_IMAGE_BASE,
  275. data, len);
  276. rt2x00pci_register_write(rt2x00dev, PBF_SYS_CTRL, 0x00000);
  277. rt2x00pci_register_write(rt2x00dev, PBF_SYS_CTRL, 0x00001);
  278. rt2x00pci_register_write(rt2x00dev, H2M_BBP_AGENT, 0);
  279. rt2x00pci_register_write(rt2x00dev, H2M_MAILBOX_CSR, 0);
  280. return 0;
  281. }
  282. /*
  283. * Initialization functions.
  284. */
  285. static bool rt2800pci_get_entry_state(struct queue_entry *entry)
  286. {
  287. struct queue_entry_priv_pci *entry_priv = entry->priv_data;
  288. u32 word;
  289. if (entry->queue->qid == QID_RX) {
  290. rt2x00_desc_read(entry_priv->desc, 1, &word);
  291. return (!rt2x00_get_field32(word, RXD_W1_DMA_DONE));
  292. } else {
  293. rt2x00_desc_read(entry_priv->desc, 1, &word);
  294. return (!rt2x00_get_field32(word, TXD_W1_DMA_DONE));
  295. }
  296. }
  297. static void rt2800pci_clear_entry(struct queue_entry *entry)
  298. {
  299. struct queue_entry_priv_pci *entry_priv = entry->priv_data;
  300. struct skb_frame_desc *skbdesc = get_skb_frame_desc(entry->skb);
  301. struct rt2x00_dev *rt2x00dev = entry->queue->rt2x00dev;
  302. u32 word;
  303. if (entry->queue->qid == QID_RX) {
  304. rt2x00_desc_read(entry_priv->desc, 0, &word);
  305. rt2x00_set_field32(&word, RXD_W0_SDP0, skbdesc->skb_dma);
  306. rt2x00_desc_write(entry_priv->desc, 0, word);
  307. rt2x00_desc_read(entry_priv->desc, 1, &word);
  308. rt2x00_set_field32(&word, RXD_W1_DMA_DONE, 0);
  309. rt2x00_desc_write(entry_priv->desc, 1, word);
  310. /*
  311. * Set RX IDX in register to inform hardware that we have
  312. * handled this entry and it is available for reuse again.
  313. */
  314. rt2x00pci_register_write(rt2x00dev, RX_CRX_IDX,
  315. entry->entry_idx);
  316. } else {
  317. rt2x00_desc_read(entry_priv->desc, 1, &word);
  318. rt2x00_set_field32(&word, TXD_W1_DMA_DONE, 1);
  319. rt2x00_desc_write(entry_priv->desc, 1, word);
  320. }
  321. }
  322. static int rt2800pci_init_queues(struct rt2x00_dev *rt2x00dev)
  323. {
  324. struct queue_entry_priv_pci *entry_priv;
  325. /*
  326. * Initialize registers.
  327. */
  328. entry_priv = rt2x00dev->tx[0].entries[0].priv_data;
  329. rt2x00pci_register_write(rt2x00dev, TX_BASE_PTR0, entry_priv->desc_dma);
  330. rt2x00pci_register_write(rt2x00dev, TX_MAX_CNT0,
  331. rt2x00dev->tx[0].limit);
  332. rt2x00pci_register_write(rt2x00dev, TX_CTX_IDX0, 0);
  333. rt2x00pci_register_write(rt2x00dev, TX_DTX_IDX0, 0);
  334. entry_priv = rt2x00dev->tx[1].entries[0].priv_data;
  335. rt2x00pci_register_write(rt2x00dev, TX_BASE_PTR1, entry_priv->desc_dma);
  336. rt2x00pci_register_write(rt2x00dev, TX_MAX_CNT1,
  337. rt2x00dev->tx[1].limit);
  338. rt2x00pci_register_write(rt2x00dev, TX_CTX_IDX1, 0);
  339. rt2x00pci_register_write(rt2x00dev, TX_DTX_IDX1, 0);
  340. entry_priv = rt2x00dev->tx[2].entries[0].priv_data;
  341. rt2x00pci_register_write(rt2x00dev, TX_BASE_PTR2, entry_priv->desc_dma);
  342. rt2x00pci_register_write(rt2x00dev, TX_MAX_CNT2,
  343. rt2x00dev->tx[2].limit);
  344. rt2x00pci_register_write(rt2x00dev, TX_CTX_IDX2, 0);
  345. rt2x00pci_register_write(rt2x00dev, TX_DTX_IDX2, 0);
  346. entry_priv = rt2x00dev->tx[3].entries[0].priv_data;
  347. rt2x00pci_register_write(rt2x00dev, TX_BASE_PTR3, entry_priv->desc_dma);
  348. rt2x00pci_register_write(rt2x00dev, TX_MAX_CNT3,
  349. rt2x00dev->tx[3].limit);
  350. rt2x00pci_register_write(rt2x00dev, TX_CTX_IDX3, 0);
  351. rt2x00pci_register_write(rt2x00dev, TX_DTX_IDX3, 0);
  352. rt2x00pci_register_write(rt2x00dev, TX_BASE_PTR4, 0);
  353. rt2x00pci_register_write(rt2x00dev, TX_MAX_CNT4, 0);
  354. rt2x00pci_register_write(rt2x00dev, TX_CTX_IDX4, 0);
  355. rt2x00pci_register_write(rt2x00dev, TX_DTX_IDX4, 0);
  356. rt2x00pci_register_write(rt2x00dev, TX_BASE_PTR5, 0);
  357. rt2x00pci_register_write(rt2x00dev, TX_MAX_CNT5, 0);
  358. rt2x00pci_register_write(rt2x00dev, TX_CTX_IDX5, 0);
  359. rt2x00pci_register_write(rt2x00dev, TX_DTX_IDX5, 0);
  360. entry_priv = rt2x00dev->rx->entries[0].priv_data;
  361. rt2x00pci_register_write(rt2x00dev, RX_BASE_PTR, entry_priv->desc_dma);
  362. rt2x00pci_register_write(rt2x00dev, RX_MAX_CNT,
  363. rt2x00dev->rx[0].limit);
  364. rt2x00pci_register_write(rt2x00dev, RX_CRX_IDX,
  365. rt2x00dev->rx[0].limit - 1);
  366. rt2x00pci_register_write(rt2x00dev, RX_DRX_IDX, 0);
  367. rt2800_disable_wpdma(rt2x00dev);
  368. rt2x00pci_register_write(rt2x00dev, DELAY_INT_CFG, 0);
  369. return 0;
  370. }
  371. /*
  372. * Device state switch handlers.
  373. */
  374. static void rt2800pci_toggle_irq(struct rt2x00_dev *rt2x00dev,
  375. enum dev_state state)
  376. {
  377. u32 reg;
  378. unsigned long flags;
  379. /*
  380. * When interrupts are being enabled, the interrupt registers
  381. * should clear the register to assure a clean state.
  382. */
  383. if (state == STATE_RADIO_IRQ_ON) {
  384. rt2x00pci_register_read(rt2x00dev, INT_SOURCE_CSR, &reg);
  385. rt2x00pci_register_write(rt2x00dev, INT_SOURCE_CSR, reg);
  386. }
  387. spin_lock_irqsave(&rt2x00dev->irqmask_lock, flags);
  388. reg = 0;
  389. if (state == STATE_RADIO_IRQ_ON) {
  390. rt2x00_set_field32(&reg, INT_MASK_CSR_RX_DONE, 1);
  391. rt2x00_set_field32(&reg, INT_MASK_CSR_TBTT, 1);
  392. rt2x00_set_field32(&reg, INT_MASK_CSR_PRE_TBTT, 1);
  393. rt2x00_set_field32(&reg, INT_MASK_CSR_TX_FIFO_STATUS, 1);
  394. rt2x00_set_field32(&reg, INT_MASK_CSR_AUTO_WAKEUP, 1);
  395. }
  396. rt2x00pci_register_write(rt2x00dev, INT_MASK_CSR, reg);
  397. spin_unlock_irqrestore(&rt2x00dev->irqmask_lock, flags);
  398. if (state == STATE_RADIO_IRQ_OFF) {
  399. /*
  400. * Wait for possibly running tasklets to finish.
  401. */
  402. tasklet_kill(&rt2x00dev->txstatus_tasklet);
  403. tasklet_kill(&rt2x00dev->rxdone_tasklet);
  404. tasklet_kill(&rt2x00dev->autowake_tasklet);
  405. tasklet_kill(&rt2x00dev->tbtt_tasklet);
  406. tasklet_kill(&rt2x00dev->pretbtt_tasklet);
  407. }
  408. }
  409. static int rt2800pci_init_registers(struct rt2x00_dev *rt2x00dev)
  410. {
  411. u32 reg;
  412. /*
  413. * Reset DMA indexes
  414. */
  415. rt2x00pci_register_read(rt2x00dev, WPDMA_RST_IDX, &reg);
  416. rt2x00_set_field32(&reg, WPDMA_RST_IDX_DTX_IDX0, 1);
  417. rt2x00_set_field32(&reg, WPDMA_RST_IDX_DTX_IDX1, 1);
  418. rt2x00_set_field32(&reg, WPDMA_RST_IDX_DTX_IDX2, 1);
  419. rt2x00_set_field32(&reg, WPDMA_RST_IDX_DTX_IDX3, 1);
  420. rt2x00_set_field32(&reg, WPDMA_RST_IDX_DTX_IDX4, 1);
  421. rt2x00_set_field32(&reg, WPDMA_RST_IDX_DTX_IDX5, 1);
  422. rt2x00_set_field32(&reg, WPDMA_RST_IDX_DRX_IDX0, 1);
  423. rt2x00pci_register_write(rt2x00dev, WPDMA_RST_IDX, reg);
  424. rt2x00pci_register_write(rt2x00dev, PBF_SYS_CTRL, 0x00000e1f);
  425. rt2x00pci_register_write(rt2x00dev, PBF_SYS_CTRL, 0x00000e00);
  426. if (rt2x00_is_pcie(rt2x00dev) &&
  427. (rt2x00_rt(rt2x00dev, RT3572) ||
  428. rt2x00_rt(rt2x00dev, RT5390) ||
  429. rt2x00_rt(rt2x00dev, RT5392))) {
  430. rt2x00pci_register_read(rt2x00dev, AUX_CTRL, &reg);
  431. rt2x00_set_field32(&reg, AUX_CTRL_FORCE_PCIE_CLK, 1);
  432. rt2x00_set_field32(&reg, AUX_CTRL_WAKE_PCIE_EN, 1);
  433. rt2x00pci_register_write(rt2x00dev, AUX_CTRL, reg);
  434. }
  435. rt2x00pci_register_write(rt2x00dev, PWR_PIN_CFG, 0x00000003);
  436. reg = 0;
  437. rt2x00_set_field32(&reg, MAC_SYS_CTRL_RESET_CSR, 1);
  438. rt2x00_set_field32(&reg, MAC_SYS_CTRL_RESET_BBP, 1);
  439. rt2x00pci_register_write(rt2x00dev, MAC_SYS_CTRL, reg);
  440. rt2x00pci_register_write(rt2x00dev, MAC_SYS_CTRL, 0x00000000);
  441. return 0;
  442. }
  443. static int rt2800pci_enable_radio(struct rt2x00_dev *rt2x00dev)
  444. {
  445. int retval;
  446. /* Wait for DMA, ignore error until we initialize queues. */
  447. rt2800_wait_wpdma_ready(rt2x00dev);
  448. if (unlikely(rt2800pci_init_queues(rt2x00dev)))
  449. return -EIO;
  450. retval = rt2800_enable_radio(rt2x00dev);
  451. if (retval)
  452. return retval;
  453. /* After resume MCU_BOOT_SIGNAL will trash these. */
  454. rt2x00pci_register_write(rt2x00dev, H2M_MAILBOX_STATUS, ~0);
  455. rt2x00pci_register_write(rt2x00dev, H2M_MAILBOX_CID, ~0);
  456. rt2800_mcu_request(rt2x00dev, MCU_SLEEP, TOKEN_RADIO_OFF, 0xff, 0x02);
  457. rt2800pci_mcu_status(rt2x00dev, TOKEN_RADIO_OFF);
  458. rt2800_mcu_request(rt2x00dev, MCU_WAKEUP, TOKEN_WAKEUP, 0, 0);
  459. rt2800pci_mcu_status(rt2x00dev, TOKEN_WAKEUP);
  460. return retval;
  461. }
  462. static void rt2800pci_disable_radio(struct rt2x00_dev *rt2x00dev)
  463. {
  464. if (rt2x00_is_soc(rt2x00dev)) {
  465. rt2800_disable_radio(rt2x00dev);
  466. rt2x00pci_register_write(rt2x00dev, PWR_PIN_CFG, 0);
  467. rt2x00pci_register_write(rt2x00dev, TX_PIN_CFG, 0);
  468. }
  469. }
  470. static int rt2800pci_set_state(struct rt2x00_dev *rt2x00dev,
  471. enum dev_state state)
  472. {
  473. if (state == STATE_AWAKE) {
  474. rt2800_mcu_request(rt2x00dev, MCU_WAKEUP, TOKEN_WAKEUP,
  475. 0, 0x02);
  476. rt2800pci_mcu_status(rt2x00dev, TOKEN_WAKEUP);
  477. } else if (state == STATE_SLEEP) {
  478. rt2x00pci_register_write(rt2x00dev, H2M_MAILBOX_STATUS,
  479. 0xffffffff);
  480. rt2x00pci_register_write(rt2x00dev, H2M_MAILBOX_CID,
  481. 0xffffffff);
  482. rt2800_mcu_request(rt2x00dev, MCU_SLEEP, TOKEN_SLEEP,
  483. 0xff, 0x01);
  484. }
  485. return 0;
  486. }
  487. static int rt2800pci_set_device_state(struct rt2x00_dev *rt2x00dev,
  488. enum dev_state state)
  489. {
  490. int retval = 0;
  491. switch (state) {
  492. case STATE_RADIO_ON:
  493. retval = rt2800pci_enable_radio(rt2x00dev);
  494. break;
  495. case STATE_RADIO_OFF:
  496. /*
  497. * After the radio has been disabled, the device should
  498. * be put to sleep for powersaving.
  499. */
  500. rt2800pci_disable_radio(rt2x00dev);
  501. rt2800pci_set_state(rt2x00dev, STATE_SLEEP);
  502. break;
  503. case STATE_RADIO_IRQ_ON:
  504. case STATE_RADIO_IRQ_OFF:
  505. rt2800pci_toggle_irq(rt2x00dev, state);
  506. break;
  507. case STATE_DEEP_SLEEP:
  508. case STATE_SLEEP:
  509. case STATE_STANDBY:
  510. case STATE_AWAKE:
  511. retval = rt2800pci_set_state(rt2x00dev, state);
  512. break;
  513. default:
  514. retval = -ENOTSUPP;
  515. break;
  516. }
  517. if (unlikely(retval))
  518. ERROR(rt2x00dev, "Device failed to enter state %d (%d).\n",
  519. state, retval);
  520. return retval;
  521. }
  522. /*
  523. * TX descriptor initialization
  524. */
  525. static __le32 *rt2800pci_get_txwi(struct queue_entry *entry)
  526. {
  527. return (__le32 *) entry->skb->data;
  528. }
  529. static void rt2800pci_write_tx_desc(struct queue_entry *entry,
  530. struct txentry_desc *txdesc)
  531. {
  532. struct skb_frame_desc *skbdesc = get_skb_frame_desc(entry->skb);
  533. struct queue_entry_priv_pci *entry_priv = entry->priv_data;
  534. __le32 *txd = entry_priv->desc;
  535. u32 word;
  536. /*
  537. * The buffers pointed by SD_PTR0/SD_LEN0 and SD_PTR1/SD_LEN1
  538. * must contains a TXWI structure + 802.11 header + padding + 802.11
  539. * data. We choose to have SD_PTR0/SD_LEN0 only contains TXWI and
  540. * SD_PTR1/SD_LEN1 contains 802.11 header + padding + 802.11
  541. * data. It means that LAST_SEC0 is always 0.
  542. */
  543. /*
  544. * Initialize TX descriptor
  545. */
  546. word = 0;
  547. rt2x00_set_field32(&word, TXD_W0_SD_PTR0, skbdesc->skb_dma);
  548. rt2x00_desc_write(txd, 0, word);
  549. word = 0;
  550. rt2x00_set_field32(&word, TXD_W1_SD_LEN1, entry->skb->len);
  551. rt2x00_set_field32(&word, TXD_W1_LAST_SEC1,
  552. !test_bit(ENTRY_TXD_MORE_FRAG, &txdesc->flags));
  553. rt2x00_set_field32(&word, TXD_W1_BURST,
  554. test_bit(ENTRY_TXD_BURST, &txdesc->flags));
  555. rt2x00_set_field32(&word, TXD_W1_SD_LEN0, TXWI_DESC_SIZE);
  556. rt2x00_set_field32(&word, TXD_W1_LAST_SEC0, 0);
  557. rt2x00_set_field32(&word, TXD_W1_DMA_DONE, 0);
  558. rt2x00_desc_write(txd, 1, word);
  559. word = 0;
  560. rt2x00_set_field32(&word, TXD_W2_SD_PTR1,
  561. skbdesc->skb_dma + TXWI_DESC_SIZE);
  562. rt2x00_desc_write(txd, 2, word);
  563. word = 0;
  564. rt2x00_set_field32(&word, TXD_W3_WIV,
  565. !test_bit(ENTRY_TXD_ENCRYPT_IV, &txdesc->flags));
  566. rt2x00_set_field32(&word, TXD_W3_QSEL, 2);
  567. rt2x00_desc_write(txd, 3, word);
  568. /*
  569. * Register descriptor details in skb frame descriptor.
  570. */
  571. skbdesc->desc = txd;
  572. skbdesc->desc_len = TXD_DESC_SIZE;
  573. }
  574. /*
  575. * RX control handlers
  576. */
  577. static void rt2800pci_fill_rxdone(struct queue_entry *entry,
  578. struct rxdone_entry_desc *rxdesc)
  579. {
  580. struct queue_entry_priv_pci *entry_priv = entry->priv_data;
  581. __le32 *rxd = entry_priv->desc;
  582. u32 word;
  583. rt2x00_desc_read(rxd, 3, &word);
  584. if (rt2x00_get_field32(word, RXD_W3_CRC_ERROR))
  585. rxdesc->flags |= RX_FLAG_FAILED_FCS_CRC;
  586. /*
  587. * Unfortunately we don't know the cipher type used during
  588. * decryption. This prevents us from correct providing
  589. * correct statistics through debugfs.
  590. */
  591. rxdesc->cipher_status = rt2x00_get_field32(word, RXD_W3_CIPHER_ERROR);
  592. if (rt2x00_get_field32(word, RXD_W3_DECRYPTED)) {
  593. /*
  594. * Hardware has stripped IV/EIV data from 802.11 frame during
  595. * decryption. Unfortunately the descriptor doesn't contain
  596. * any fields with the EIV/IV data either, so they can't
  597. * be restored by rt2x00lib.
  598. */
  599. rxdesc->flags |= RX_FLAG_IV_STRIPPED;
  600. /*
  601. * The hardware has already checked the Michael Mic and has
  602. * stripped it from the frame. Signal this to mac80211.
  603. */
  604. rxdesc->flags |= RX_FLAG_MMIC_STRIPPED;
  605. if (rxdesc->cipher_status == RX_CRYPTO_SUCCESS)
  606. rxdesc->flags |= RX_FLAG_DECRYPTED;
  607. else if (rxdesc->cipher_status == RX_CRYPTO_FAIL_MIC)
  608. rxdesc->flags |= RX_FLAG_MMIC_ERROR;
  609. }
  610. if (rt2x00_get_field32(word, RXD_W3_MY_BSS))
  611. rxdesc->dev_flags |= RXDONE_MY_BSS;
  612. if (rt2x00_get_field32(word, RXD_W3_L2PAD))
  613. rxdesc->dev_flags |= RXDONE_L2PAD;
  614. /*
  615. * Process the RXWI structure that is at the start of the buffer.
  616. */
  617. rt2800_process_rxwi(entry, rxdesc);
  618. /*
  619. * Remove RXWI descriptor from start of buffer.
  620. */
  621. skb_pull(entry->skb, RXWI_DESC_SIZE);
  622. }
  623. /*
  624. * Interrupt functions.
  625. */
  626. static void rt2800pci_wakeup(struct rt2x00_dev *rt2x00dev)
  627. {
  628. struct ieee80211_conf conf = { .flags = 0 };
  629. struct rt2x00lib_conf libconf = { .conf = &conf };
  630. rt2800_config(rt2x00dev, &libconf, IEEE80211_CONF_CHANGE_PS);
  631. }
  632. static bool rt2800pci_txdone_entry_check(struct queue_entry *entry, u32 status)
  633. {
  634. __le32 *txwi;
  635. u32 word;
  636. int wcid, tx_wcid;
  637. wcid = rt2x00_get_field32(status, TX_STA_FIFO_WCID);
  638. txwi = rt2800_drv_get_txwi(entry);
  639. rt2x00_desc_read(txwi, 1, &word);
  640. tx_wcid = rt2x00_get_field32(word, TXWI_W1_WIRELESS_CLI_ID);
  641. return (tx_wcid == wcid);
  642. }
  643. static bool rt2800pci_txdone_find_entry(struct queue_entry *entry, void *data)
  644. {
  645. u32 status = *(u32 *)data;
  646. /*
  647. * rt2800pci hardware might reorder frames when exchanging traffic
  648. * with multiple BA enabled STAs.
  649. *
  650. * For example, a tx queue
  651. * [ STA1 | STA2 | STA1 | STA2 ]
  652. * can result in tx status reports
  653. * [ STA1 | STA1 | STA2 | STA2 ]
  654. * when the hw decides to aggregate the frames for STA1 into one AMPDU.
  655. *
  656. * To mitigate this effect, associate the tx status to the first frame
  657. * in the tx queue with a matching wcid.
  658. */
  659. if (rt2800pci_txdone_entry_check(entry, status) &&
  660. !test_bit(ENTRY_DATA_STATUS_SET, &entry->flags)) {
  661. /*
  662. * Got a matching frame, associate the tx status with
  663. * the frame
  664. */
  665. entry->status = status;
  666. set_bit(ENTRY_DATA_STATUS_SET, &entry->flags);
  667. return true;
  668. }
  669. /* Check the next frame */
  670. return false;
  671. }
  672. static bool rt2800pci_txdone_match_first(struct queue_entry *entry, void *data)
  673. {
  674. u32 status = *(u32 *)data;
  675. /*
  676. * Find the first frame without tx status and assign this status to it
  677. * regardless if it matches or not.
  678. */
  679. if (!test_bit(ENTRY_DATA_STATUS_SET, &entry->flags)) {
  680. /*
  681. * Got a matching frame, associate the tx status with
  682. * the frame
  683. */
  684. entry->status = status;
  685. set_bit(ENTRY_DATA_STATUS_SET, &entry->flags);
  686. return true;
  687. }
  688. /* Check the next frame */
  689. return false;
  690. }
  691. static bool rt2800pci_txdone_release_entries(struct queue_entry *entry,
  692. void *data)
  693. {
  694. if (test_bit(ENTRY_DATA_STATUS_SET, &entry->flags)) {
  695. rt2800_txdone_entry(entry, entry->status,
  696. rt2800pci_get_txwi(entry));
  697. return false;
  698. }
  699. /* No more frames to release */
  700. return true;
  701. }
  702. static bool rt2800pci_txdone(struct rt2x00_dev *rt2x00dev)
  703. {
  704. struct data_queue *queue;
  705. u32 status;
  706. u8 qid;
  707. int max_tx_done = 16;
  708. while (kfifo_get(&rt2x00dev->txstatus_fifo, &status)) {
  709. qid = rt2x00_get_field32(status, TX_STA_FIFO_PID_QUEUE);
  710. if (unlikely(qid >= QID_RX)) {
  711. /*
  712. * Unknown queue, this shouldn't happen. Just drop
  713. * this tx status.
  714. */
  715. WARNING(rt2x00dev, "Got TX status report with "
  716. "unexpected pid %u, dropping\n", qid);
  717. break;
  718. }
  719. queue = rt2x00queue_get_tx_queue(rt2x00dev, qid);
  720. if (unlikely(queue == NULL)) {
  721. /*
  722. * The queue is NULL, this shouldn't happen. Stop
  723. * processing here and drop the tx status
  724. */
  725. WARNING(rt2x00dev, "Got TX status for an unavailable "
  726. "queue %u, dropping\n", qid);
  727. break;
  728. }
  729. if (unlikely(rt2x00queue_empty(queue))) {
  730. /*
  731. * The queue is empty. Stop processing here
  732. * and drop the tx status.
  733. */
  734. WARNING(rt2x00dev, "Got TX status for an empty "
  735. "queue %u, dropping\n", qid);
  736. break;
  737. }
  738. /*
  739. * Let's associate this tx status with the first
  740. * matching frame.
  741. */
  742. if (!rt2x00queue_for_each_entry(queue, Q_INDEX_DONE,
  743. Q_INDEX, &status,
  744. rt2800pci_txdone_find_entry)) {
  745. /*
  746. * We cannot match the tx status to any frame, so just
  747. * use the first one.
  748. */
  749. if (!rt2x00queue_for_each_entry(queue, Q_INDEX_DONE,
  750. Q_INDEX, &status,
  751. rt2800pci_txdone_match_first)) {
  752. WARNING(rt2x00dev, "No frame found for TX "
  753. "status on queue %u, dropping\n",
  754. qid);
  755. break;
  756. }
  757. }
  758. /*
  759. * Release all frames with a valid tx status.
  760. */
  761. rt2x00queue_for_each_entry(queue, Q_INDEX_DONE,
  762. Q_INDEX, NULL,
  763. rt2800pci_txdone_release_entries);
  764. if (--max_tx_done == 0)
  765. break;
  766. }
  767. return !max_tx_done;
  768. }
  769. static inline void rt2800pci_enable_interrupt(struct rt2x00_dev *rt2x00dev,
  770. struct rt2x00_field32 irq_field)
  771. {
  772. u32 reg;
  773. /*
  774. * Enable a single interrupt. The interrupt mask register
  775. * access needs locking.
  776. */
  777. spin_lock_irq(&rt2x00dev->irqmask_lock);
  778. rt2x00pci_register_read(rt2x00dev, INT_MASK_CSR, &reg);
  779. rt2x00_set_field32(&reg, irq_field, 1);
  780. rt2x00pci_register_write(rt2x00dev, INT_MASK_CSR, reg);
  781. spin_unlock_irq(&rt2x00dev->irqmask_lock);
  782. }
  783. static void rt2800pci_txstatus_tasklet(unsigned long data)
  784. {
  785. struct rt2x00_dev *rt2x00dev = (struct rt2x00_dev *)data;
  786. if (rt2800pci_txdone(rt2x00dev))
  787. tasklet_schedule(&rt2x00dev->txstatus_tasklet);
  788. /*
  789. * No need to enable the tx status interrupt here as we always
  790. * leave it enabled to minimize the possibility of a tx status
  791. * register overflow. See comment in interrupt handler.
  792. */
  793. }
  794. static void rt2800pci_pretbtt_tasklet(unsigned long data)
  795. {
  796. struct rt2x00_dev *rt2x00dev = (struct rt2x00_dev *)data;
  797. rt2x00lib_pretbtt(rt2x00dev);
  798. if (test_bit(DEVICE_STATE_ENABLED_RADIO, &rt2x00dev->flags))
  799. rt2800pci_enable_interrupt(rt2x00dev, INT_MASK_CSR_PRE_TBTT);
  800. }
  801. static void rt2800pci_tbtt_tasklet(unsigned long data)
  802. {
  803. struct rt2x00_dev *rt2x00dev = (struct rt2x00_dev *)data;
  804. struct rt2800_drv_data *drv_data = rt2x00dev->drv_data;
  805. u32 reg;
  806. rt2x00lib_beacondone(rt2x00dev);
  807. if (rt2x00dev->intf_ap_count) {
  808. /*
  809. * The rt2800pci hardware tbtt timer is off by 1us per tbtt
  810. * causing beacon skew and as a result causing problems with
  811. * some powersaving clients over time. Shorten the beacon
  812. * interval every 64 beacons by 64us to mitigate this effect.
  813. */
  814. if (drv_data->tbtt_tick == (BCN_TBTT_OFFSET - 2)) {
  815. rt2x00pci_register_read(rt2x00dev, BCN_TIME_CFG, &reg);
  816. rt2x00_set_field32(&reg, BCN_TIME_CFG_BEACON_INTERVAL,
  817. (rt2x00dev->beacon_int * 16) - 1);
  818. rt2x00pci_register_write(rt2x00dev, BCN_TIME_CFG, reg);
  819. } else if (drv_data->tbtt_tick == (BCN_TBTT_OFFSET - 1)) {
  820. rt2x00pci_register_read(rt2x00dev, BCN_TIME_CFG, &reg);
  821. rt2x00_set_field32(&reg, BCN_TIME_CFG_BEACON_INTERVAL,
  822. (rt2x00dev->beacon_int * 16));
  823. rt2x00pci_register_write(rt2x00dev, BCN_TIME_CFG, reg);
  824. }
  825. drv_data->tbtt_tick++;
  826. drv_data->tbtt_tick %= BCN_TBTT_OFFSET;
  827. }
  828. if (test_bit(DEVICE_STATE_ENABLED_RADIO, &rt2x00dev->flags))
  829. rt2800pci_enable_interrupt(rt2x00dev, INT_MASK_CSR_TBTT);
  830. }
  831. static void rt2800pci_rxdone_tasklet(unsigned long data)
  832. {
  833. struct rt2x00_dev *rt2x00dev = (struct rt2x00_dev *)data;
  834. if (rt2x00pci_rxdone(rt2x00dev))
  835. tasklet_schedule(&rt2x00dev->rxdone_tasklet);
  836. else if (test_bit(DEVICE_STATE_ENABLED_RADIO, &rt2x00dev->flags))
  837. rt2800pci_enable_interrupt(rt2x00dev, INT_MASK_CSR_RX_DONE);
  838. }
  839. static void rt2800pci_autowake_tasklet(unsigned long data)
  840. {
  841. struct rt2x00_dev *rt2x00dev = (struct rt2x00_dev *)data;
  842. rt2800pci_wakeup(rt2x00dev);
  843. if (test_bit(DEVICE_STATE_ENABLED_RADIO, &rt2x00dev->flags))
  844. rt2800pci_enable_interrupt(rt2x00dev, INT_MASK_CSR_AUTO_WAKEUP);
  845. }
  846. static void rt2800pci_txstatus_interrupt(struct rt2x00_dev *rt2x00dev)
  847. {
  848. u32 status;
  849. int i;
  850. /*
  851. * The TX_FIFO_STATUS interrupt needs special care. We should
  852. * read TX_STA_FIFO but we should do it immediately as otherwise
  853. * the register can overflow and we would lose status reports.
  854. *
  855. * Hence, read the TX_STA_FIFO register and copy all tx status
  856. * reports into a kernel FIFO which is handled in the txstatus
  857. * tasklet. We use a tasklet to process the tx status reports
  858. * because we can schedule the tasklet multiple times (when the
  859. * interrupt fires again during tx status processing).
  860. *
  861. * Furthermore we don't disable the TX_FIFO_STATUS
  862. * interrupt here but leave it enabled so that the TX_STA_FIFO
  863. * can also be read while the tx status tasklet gets executed.
  864. *
  865. * Since we have only one producer and one consumer we don't
  866. * need to lock the kfifo.
  867. */
  868. for (i = 0; i < rt2x00dev->ops->tx->entry_num; i++) {
  869. rt2x00pci_register_read(rt2x00dev, TX_STA_FIFO, &status);
  870. if (!rt2x00_get_field32(status, TX_STA_FIFO_VALID))
  871. break;
  872. if (!kfifo_put(&rt2x00dev->txstatus_fifo, &status)) {
  873. WARNING(rt2x00dev, "TX status FIFO overrun,"
  874. "drop tx status report.\n");
  875. break;
  876. }
  877. }
  878. /* Schedule the tasklet for processing the tx status. */
  879. tasklet_schedule(&rt2x00dev->txstatus_tasklet);
  880. }
  881. static irqreturn_t rt2800pci_interrupt(int irq, void *dev_instance)
  882. {
  883. struct rt2x00_dev *rt2x00dev = dev_instance;
  884. u32 reg, mask;
  885. /* Read status and ACK all interrupts */
  886. rt2x00pci_register_read(rt2x00dev, INT_SOURCE_CSR, &reg);
  887. rt2x00pci_register_write(rt2x00dev, INT_SOURCE_CSR, reg);
  888. if (!reg)
  889. return IRQ_NONE;
  890. if (!test_bit(DEVICE_STATE_ENABLED_RADIO, &rt2x00dev->flags))
  891. return IRQ_HANDLED;
  892. /*
  893. * Since INT_MASK_CSR and INT_SOURCE_CSR use the same bits
  894. * for interrupts and interrupt masks we can just use the value of
  895. * INT_SOURCE_CSR to create the interrupt mask.
  896. */
  897. mask = ~reg;
  898. if (rt2x00_get_field32(reg, INT_SOURCE_CSR_TX_FIFO_STATUS)) {
  899. rt2800pci_txstatus_interrupt(rt2x00dev);
  900. /*
  901. * Never disable the TX_FIFO_STATUS interrupt.
  902. */
  903. rt2x00_set_field32(&mask, INT_MASK_CSR_TX_FIFO_STATUS, 1);
  904. }
  905. if (rt2x00_get_field32(reg, INT_SOURCE_CSR_PRE_TBTT))
  906. tasklet_hi_schedule(&rt2x00dev->pretbtt_tasklet);
  907. if (rt2x00_get_field32(reg, INT_SOURCE_CSR_TBTT))
  908. tasklet_hi_schedule(&rt2x00dev->tbtt_tasklet);
  909. if (rt2x00_get_field32(reg, INT_SOURCE_CSR_RX_DONE))
  910. tasklet_schedule(&rt2x00dev->rxdone_tasklet);
  911. if (rt2x00_get_field32(reg, INT_SOURCE_CSR_AUTO_WAKEUP))
  912. tasklet_schedule(&rt2x00dev->autowake_tasklet);
  913. /*
  914. * Disable all interrupts for which a tasklet was scheduled right now,
  915. * the tasklet will reenable the appropriate interrupts.
  916. */
  917. spin_lock(&rt2x00dev->irqmask_lock);
  918. rt2x00pci_register_read(rt2x00dev, INT_MASK_CSR, &reg);
  919. reg &= mask;
  920. rt2x00pci_register_write(rt2x00dev, INT_MASK_CSR, reg);
  921. spin_unlock(&rt2x00dev->irqmask_lock);
  922. return IRQ_HANDLED;
  923. }
  924. /*
  925. * Device probe functions.
  926. */
  927. static int rt2800pci_read_eeprom(struct rt2x00_dev *rt2x00dev)
  928. {
  929. int retval;
  930. if (rt2x00_is_soc(rt2x00dev))
  931. retval = rt2800pci_read_eeprom_soc(rt2x00dev);
  932. else if (rt2800pci_efuse_detect(rt2x00dev))
  933. retval = rt2800pci_read_eeprom_efuse(rt2x00dev);
  934. else
  935. retval = rt2800pci_read_eeprom_pci(rt2x00dev);
  936. return retval;
  937. }
  938. static const struct ieee80211_ops rt2800pci_mac80211_ops = {
  939. .tx = rt2x00mac_tx,
  940. .start = rt2x00mac_start,
  941. .stop = rt2x00mac_stop,
  942. .add_interface = rt2x00mac_add_interface,
  943. .remove_interface = rt2x00mac_remove_interface,
  944. .config = rt2x00mac_config,
  945. .configure_filter = rt2x00mac_configure_filter,
  946. .set_key = rt2x00mac_set_key,
  947. .sw_scan_start = rt2x00mac_sw_scan_start,
  948. .sw_scan_complete = rt2x00mac_sw_scan_complete,
  949. .get_stats = rt2x00mac_get_stats,
  950. .get_tkip_seq = rt2800_get_tkip_seq,
  951. .set_rts_threshold = rt2800_set_rts_threshold,
  952. .sta_add = rt2x00mac_sta_add,
  953. .sta_remove = rt2x00mac_sta_remove,
  954. .bss_info_changed = rt2x00mac_bss_info_changed,
  955. .conf_tx = rt2800_conf_tx,
  956. .get_tsf = rt2800_get_tsf,
  957. .rfkill_poll = rt2x00mac_rfkill_poll,
  958. .ampdu_action = rt2800_ampdu_action,
  959. .flush = rt2x00mac_flush,
  960. .get_survey = rt2800_get_survey,
  961. .get_ringparam = rt2x00mac_get_ringparam,
  962. .tx_frames_pending = rt2x00mac_tx_frames_pending,
  963. };
  964. static const struct rt2800_ops rt2800pci_rt2800_ops = {
  965. .register_read = rt2x00pci_register_read,
  966. .register_read_lock = rt2x00pci_register_read, /* same for PCI */
  967. .register_write = rt2x00pci_register_write,
  968. .register_write_lock = rt2x00pci_register_write, /* same for PCI */
  969. .register_multiread = rt2x00pci_register_multiread,
  970. .register_multiwrite = rt2x00pci_register_multiwrite,
  971. .regbusy_read = rt2x00pci_regbusy_read,
  972. .read_eeprom = rt2800pci_read_eeprom,
  973. .hwcrypt_disabled = rt2800pci_hwcrypt_disabled,
  974. .drv_write_firmware = rt2800pci_write_firmware,
  975. .drv_init_registers = rt2800pci_init_registers,
  976. .drv_get_txwi = rt2800pci_get_txwi,
  977. };
  978. static const struct rt2x00lib_ops rt2800pci_rt2x00_ops = {
  979. .irq_handler = rt2800pci_interrupt,
  980. .txstatus_tasklet = rt2800pci_txstatus_tasklet,
  981. .pretbtt_tasklet = rt2800pci_pretbtt_tasklet,
  982. .tbtt_tasklet = rt2800pci_tbtt_tasklet,
  983. .rxdone_tasklet = rt2800pci_rxdone_tasklet,
  984. .autowake_tasklet = rt2800pci_autowake_tasklet,
  985. .probe_hw = rt2800_probe_hw,
  986. .get_firmware_name = rt2800pci_get_firmware_name,
  987. .check_firmware = rt2800_check_firmware,
  988. .load_firmware = rt2800_load_firmware,
  989. .initialize = rt2x00pci_initialize,
  990. .uninitialize = rt2x00pci_uninitialize,
  991. .get_entry_state = rt2800pci_get_entry_state,
  992. .clear_entry = rt2800pci_clear_entry,
  993. .set_device_state = rt2800pci_set_device_state,
  994. .rfkill_poll = rt2800_rfkill_poll,
  995. .link_stats = rt2800_link_stats,
  996. .reset_tuner = rt2800_reset_tuner,
  997. .link_tuner = rt2800_link_tuner,
  998. .gain_calibration = rt2800_gain_calibration,
  999. .vco_calibration = rt2800_vco_calibration,
  1000. .start_queue = rt2800pci_start_queue,
  1001. .kick_queue = rt2800pci_kick_queue,
  1002. .stop_queue = rt2800pci_stop_queue,
  1003. .flush_queue = rt2x00pci_flush_queue,
  1004. .write_tx_desc = rt2800pci_write_tx_desc,
  1005. .write_tx_data = rt2800_write_tx_data,
  1006. .write_beacon = rt2800_write_beacon,
  1007. .clear_beacon = rt2800_clear_beacon,
  1008. .fill_rxdone = rt2800pci_fill_rxdone,
  1009. .config_shared_key = rt2800_config_shared_key,
  1010. .config_pairwise_key = rt2800_config_pairwise_key,
  1011. .config_filter = rt2800_config_filter,
  1012. .config_intf = rt2800_config_intf,
  1013. .config_erp = rt2800_config_erp,
  1014. .config_ant = rt2800_config_ant,
  1015. .config = rt2800_config,
  1016. .sta_add = rt2800_sta_add,
  1017. .sta_remove = rt2800_sta_remove,
  1018. };
  1019. static const struct data_queue_desc rt2800pci_queue_rx = {
  1020. .entry_num = 128,
  1021. .data_size = AGGREGATION_SIZE,
  1022. .desc_size = RXD_DESC_SIZE,
  1023. .priv_size = sizeof(struct queue_entry_priv_pci),
  1024. };
  1025. static const struct data_queue_desc rt2800pci_queue_tx = {
  1026. .entry_num = 64,
  1027. .data_size = AGGREGATION_SIZE,
  1028. .desc_size = TXD_DESC_SIZE,
  1029. .priv_size = sizeof(struct queue_entry_priv_pci),
  1030. };
  1031. static const struct data_queue_desc rt2800pci_queue_bcn = {
  1032. .entry_num = 8,
  1033. .data_size = 0, /* No DMA required for beacons */
  1034. .desc_size = TXWI_DESC_SIZE,
  1035. .priv_size = sizeof(struct queue_entry_priv_pci),
  1036. };
  1037. static const struct rt2x00_ops rt2800pci_ops = {
  1038. .name = KBUILD_MODNAME,
  1039. .drv_data_size = sizeof(struct rt2800_drv_data),
  1040. .max_ap_intf = 8,
  1041. .eeprom_size = EEPROM_SIZE,
  1042. .rf_size = RF_SIZE,
  1043. .tx_queues = NUM_TX_QUEUES,
  1044. .extra_tx_headroom = TXWI_DESC_SIZE,
  1045. .rx = &rt2800pci_queue_rx,
  1046. .tx = &rt2800pci_queue_tx,
  1047. .bcn = &rt2800pci_queue_bcn,
  1048. .lib = &rt2800pci_rt2x00_ops,
  1049. .drv = &rt2800pci_rt2800_ops,
  1050. .hw = &rt2800pci_mac80211_ops,
  1051. #ifdef CONFIG_RT2X00_LIB_DEBUGFS
  1052. .debugfs = &rt2800_rt2x00debug,
  1053. #endif /* CONFIG_RT2X00_LIB_DEBUGFS */
  1054. };
  1055. /*
  1056. * RT2800pci module information.
  1057. */
  1058. #ifdef CONFIG_PCI
  1059. static DEFINE_PCI_DEVICE_TABLE(rt2800pci_device_table) = {
  1060. { PCI_DEVICE(0x1814, 0x0601) },
  1061. { PCI_DEVICE(0x1814, 0x0681) },
  1062. { PCI_DEVICE(0x1814, 0x0701) },
  1063. { PCI_DEVICE(0x1814, 0x0781) },
  1064. { PCI_DEVICE(0x1814, 0x3090) },
  1065. { PCI_DEVICE(0x1814, 0x3091) },
  1066. { PCI_DEVICE(0x1814, 0x3092) },
  1067. { PCI_DEVICE(0x1432, 0x7708) },
  1068. { PCI_DEVICE(0x1432, 0x7727) },
  1069. { PCI_DEVICE(0x1432, 0x7728) },
  1070. { PCI_DEVICE(0x1432, 0x7738) },
  1071. { PCI_DEVICE(0x1432, 0x7748) },
  1072. { PCI_DEVICE(0x1432, 0x7758) },
  1073. { PCI_DEVICE(0x1432, 0x7768) },
  1074. { PCI_DEVICE(0x1462, 0x891a) },
  1075. { PCI_DEVICE(0x1a3b, 0x1059) },
  1076. #ifdef CONFIG_RT2800PCI_RT3290
  1077. { PCI_DEVICE(0x1814, 0x3290) },
  1078. #endif
  1079. #ifdef CONFIG_RT2800PCI_RT33XX
  1080. { PCI_DEVICE(0x1814, 0x3390) },
  1081. #endif
  1082. #ifdef CONFIG_RT2800PCI_RT35XX
  1083. { PCI_DEVICE(0x1432, 0x7711) },
  1084. { PCI_DEVICE(0x1432, 0x7722) },
  1085. { PCI_DEVICE(0x1814, 0x3060) },
  1086. { PCI_DEVICE(0x1814, 0x3062) },
  1087. { PCI_DEVICE(0x1814, 0x3562) },
  1088. { PCI_DEVICE(0x1814, 0x3592) },
  1089. { PCI_DEVICE(0x1814, 0x3593) },
  1090. { PCI_DEVICE(0x1814, 0x359f) },
  1091. #endif
  1092. #ifdef CONFIG_RT2800PCI_RT53XX
  1093. { PCI_DEVICE(0x1814, 0x5360) },
  1094. { PCI_DEVICE(0x1814, 0x5362) },
  1095. { PCI_DEVICE(0x1814, 0x5390) },
  1096. { PCI_DEVICE(0x1814, 0x5392) },
  1097. { PCI_DEVICE(0x1814, 0x539a) },
  1098. { PCI_DEVICE(0x1814, 0x539b) },
  1099. { PCI_DEVICE(0x1814, 0x539f) },
  1100. #endif
  1101. { 0, }
  1102. };
  1103. #endif /* CONFIG_PCI */
  1104. MODULE_AUTHOR(DRV_PROJECT);
  1105. MODULE_VERSION(DRV_VERSION);
  1106. MODULE_DESCRIPTION("Ralink RT2800 PCI & PCMCIA Wireless LAN driver.");
  1107. MODULE_SUPPORTED_DEVICE("Ralink RT2860 PCI & PCMCIA chipset based cards");
  1108. #ifdef CONFIG_PCI
  1109. MODULE_FIRMWARE(FIRMWARE_RT2860);
  1110. MODULE_DEVICE_TABLE(pci, rt2800pci_device_table);
  1111. #endif /* CONFIG_PCI */
  1112. MODULE_LICENSE("GPL");
  1113. #if defined(CONFIG_SOC_RT288X) || defined(CONFIG_SOC_RT305X)
  1114. static int rt2800soc_probe(struct platform_device *pdev)
  1115. {
  1116. return rt2x00soc_probe(pdev, &rt2800pci_ops);
  1117. }
  1118. static struct platform_driver rt2800soc_driver = {
  1119. .driver = {
  1120. .name = "rt2800_wmac",
  1121. .owner = THIS_MODULE,
  1122. .mod_name = KBUILD_MODNAME,
  1123. },
  1124. .probe = rt2800soc_probe,
  1125. .remove = rt2x00soc_remove,
  1126. .suspend = rt2x00soc_suspend,
  1127. .resume = rt2x00soc_resume,
  1128. };
  1129. #endif /* CONFIG_SOC_RT288X || CONFIG_SOC_RT305X */
  1130. #ifdef CONFIG_PCI
  1131. static int rt2800pci_probe(struct pci_dev *pci_dev,
  1132. const struct pci_device_id *id)
  1133. {
  1134. return rt2x00pci_probe(pci_dev, &rt2800pci_ops);
  1135. }
  1136. static struct pci_driver rt2800pci_driver = {
  1137. .name = KBUILD_MODNAME,
  1138. .id_table = rt2800pci_device_table,
  1139. .probe = rt2800pci_probe,
  1140. .remove = rt2x00pci_remove,
  1141. .suspend = rt2x00pci_suspend,
  1142. .resume = rt2x00pci_resume,
  1143. };
  1144. #endif /* CONFIG_PCI */
  1145. static int __init rt2800pci_init(void)
  1146. {
  1147. int ret = 0;
  1148. #if defined(CONFIG_SOC_RT288X) || defined(CONFIG_SOC_RT305X)
  1149. ret = platform_driver_register(&rt2800soc_driver);
  1150. if (ret)
  1151. return ret;
  1152. #endif
  1153. #ifdef CONFIG_PCI
  1154. ret = pci_register_driver(&rt2800pci_driver);
  1155. if (ret) {
  1156. #if defined(CONFIG_SOC_RT288X) || defined(CONFIG_SOC_RT305X)
  1157. platform_driver_unregister(&rt2800soc_driver);
  1158. #endif
  1159. return ret;
  1160. }
  1161. #endif
  1162. return ret;
  1163. }
  1164. static void __exit rt2800pci_exit(void)
  1165. {
  1166. #ifdef CONFIG_PCI
  1167. pci_unregister_driver(&rt2800pci_driver);
  1168. #endif
  1169. #if defined(CONFIG_SOC_RT288X) || defined(CONFIG_SOC_RT305X)
  1170. platform_driver_unregister(&rt2800soc_driver);
  1171. #endif
  1172. }
  1173. module_init(rt2800pci_init);
  1174. module_exit(rt2800pci_exit);