main.c 58 KB

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  1. /*
  2. * Copyright (c) 2008-2011 Atheros Communications Inc.
  3. *
  4. * Permission to use, copy, modify, and/or distribute this software for any
  5. * purpose with or without fee is hereby granted, provided that the above
  6. * copyright notice and this permission notice appear in all copies.
  7. *
  8. * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
  9. * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
  10. * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
  11. * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
  12. * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
  13. * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
  14. * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
  15. */
  16. #include <linux/nl80211.h>
  17. #include <linux/delay.h>
  18. #include "ath9k.h"
  19. #include "btcoex.h"
  20. static void ath9k_set_assoc_state(struct ath_softc *sc,
  21. struct ieee80211_vif *vif);
  22. u8 ath9k_parse_mpdudensity(u8 mpdudensity)
  23. {
  24. /*
  25. * 802.11n D2.0 defined values for "Minimum MPDU Start Spacing":
  26. * 0 for no restriction
  27. * 1 for 1/4 us
  28. * 2 for 1/2 us
  29. * 3 for 1 us
  30. * 4 for 2 us
  31. * 5 for 4 us
  32. * 6 for 8 us
  33. * 7 for 16 us
  34. */
  35. switch (mpdudensity) {
  36. case 0:
  37. return 0;
  38. case 1:
  39. case 2:
  40. case 3:
  41. /* Our lower layer calculations limit our precision to
  42. 1 microsecond */
  43. return 1;
  44. case 4:
  45. return 2;
  46. case 5:
  47. return 4;
  48. case 6:
  49. return 8;
  50. case 7:
  51. return 16;
  52. default:
  53. return 0;
  54. }
  55. }
  56. static bool ath9k_has_pending_frames(struct ath_softc *sc, struct ath_txq *txq)
  57. {
  58. bool pending = false;
  59. spin_lock_bh(&txq->axq_lock);
  60. if (txq->axq_depth || !list_empty(&txq->axq_acq))
  61. pending = true;
  62. spin_unlock_bh(&txq->axq_lock);
  63. return pending;
  64. }
  65. static bool ath9k_setpower(struct ath_softc *sc, enum ath9k_power_mode mode)
  66. {
  67. unsigned long flags;
  68. bool ret;
  69. spin_lock_irqsave(&sc->sc_pm_lock, flags);
  70. ret = ath9k_hw_setpower(sc->sc_ah, mode);
  71. spin_unlock_irqrestore(&sc->sc_pm_lock, flags);
  72. return ret;
  73. }
  74. void ath9k_ps_wakeup(struct ath_softc *sc)
  75. {
  76. struct ath_common *common = ath9k_hw_common(sc->sc_ah);
  77. unsigned long flags;
  78. enum ath9k_power_mode power_mode;
  79. spin_lock_irqsave(&sc->sc_pm_lock, flags);
  80. if (++sc->ps_usecount != 1)
  81. goto unlock;
  82. power_mode = sc->sc_ah->power_mode;
  83. ath9k_hw_setpower(sc->sc_ah, ATH9K_PM_AWAKE);
  84. /*
  85. * While the hardware is asleep, the cycle counters contain no
  86. * useful data. Better clear them now so that they don't mess up
  87. * survey data results.
  88. */
  89. if (power_mode != ATH9K_PM_AWAKE) {
  90. spin_lock(&common->cc_lock);
  91. ath_hw_cycle_counters_update(common);
  92. memset(&common->cc_survey, 0, sizeof(common->cc_survey));
  93. memset(&common->cc_ani, 0, sizeof(common->cc_ani));
  94. spin_unlock(&common->cc_lock);
  95. }
  96. unlock:
  97. spin_unlock_irqrestore(&sc->sc_pm_lock, flags);
  98. }
  99. void ath9k_ps_restore(struct ath_softc *sc)
  100. {
  101. struct ath_common *common = ath9k_hw_common(sc->sc_ah);
  102. enum ath9k_power_mode mode;
  103. unsigned long flags;
  104. bool reset;
  105. spin_lock_irqsave(&sc->sc_pm_lock, flags);
  106. if (--sc->ps_usecount != 0)
  107. goto unlock;
  108. if (sc->ps_idle) {
  109. ath9k_hw_setrxabort(sc->sc_ah, 1);
  110. ath9k_hw_stopdmarecv(sc->sc_ah, &reset);
  111. mode = ATH9K_PM_FULL_SLEEP;
  112. } else if (sc->ps_enabled &&
  113. !(sc->ps_flags & (PS_WAIT_FOR_BEACON |
  114. PS_WAIT_FOR_CAB |
  115. PS_WAIT_FOR_PSPOLL_DATA |
  116. PS_WAIT_FOR_TX_ACK |
  117. PS_WAIT_FOR_ANI))) {
  118. mode = ATH9K_PM_NETWORK_SLEEP;
  119. if (ath9k_hw_btcoex_is_enabled(sc->sc_ah))
  120. ath9k_btcoex_stop_gen_timer(sc);
  121. } else {
  122. goto unlock;
  123. }
  124. spin_lock(&common->cc_lock);
  125. ath_hw_cycle_counters_update(common);
  126. spin_unlock(&common->cc_lock);
  127. ath9k_hw_setpower(sc->sc_ah, mode);
  128. unlock:
  129. spin_unlock_irqrestore(&sc->sc_pm_lock, flags);
  130. }
  131. static void __ath_cancel_work(struct ath_softc *sc)
  132. {
  133. cancel_work_sync(&sc->paprd_work);
  134. cancel_work_sync(&sc->hw_check_work);
  135. cancel_delayed_work_sync(&sc->tx_complete_work);
  136. cancel_delayed_work_sync(&sc->hw_pll_work);
  137. #ifdef CONFIG_ATH9K_BTCOEX_SUPPORT
  138. if (ath9k_hw_mci_is_enabled(sc->sc_ah))
  139. cancel_work_sync(&sc->mci_work);
  140. #endif
  141. }
  142. static void ath_cancel_work(struct ath_softc *sc)
  143. {
  144. __ath_cancel_work(sc);
  145. cancel_work_sync(&sc->hw_reset_work);
  146. }
  147. static void ath_restart_work(struct ath_softc *sc)
  148. {
  149. ieee80211_queue_delayed_work(sc->hw, &sc->tx_complete_work, 0);
  150. if (AR_SREV_9340(sc->sc_ah) || AR_SREV_9485(sc->sc_ah) ||
  151. AR_SREV_9550(sc->sc_ah))
  152. ieee80211_queue_delayed_work(sc->hw, &sc->hw_pll_work,
  153. msecs_to_jiffies(ATH_PLL_WORK_INTERVAL));
  154. ath_start_rx_poll(sc, 3);
  155. ath_start_ani(sc);
  156. }
  157. static bool ath_prepare_reset(struct ath_softc *sc)
  158. {
  159. struct ath_hw *ah = sc->sc_ah;
  160. bool ret = true;
  161. ieee80211_stop_queues(sc->hw);
  162. sc->hw_busy_count = 0;
  163. ath_stop_ani(sc);
  164. del_timer_sync(&sc->rx_poll_timer);
  165. ath9k_debug_samp_bb_mac(sc);
  166. ath9k_hw_disable_interrupts(ah);
  167. if (!ath_drain_all_txq(sc))
  168. ret = false;
  169. if (!ath_stoprecv(sc))
  170. ret = false;
  171. return ret;
  172. }
  173. static bool ath_complete_reset(struct ath_softc *sc, bool start)
  174. {
  175. struct ath_hw *ah = sc->sc_ah;
  176. struct ath_common *common = ath9k_hw_common(ah);
  177. unsigned long flags;
  178. if (ath_startrecv(sc) != 0) {
  179. ath_err(common, "Unable to restart recv logic\n");
  180. return false;
  181. }
  182. ath9k_cmn_update_txpow(ah, sc->curtxpow,
  183. sc->config.txpowlimit, &sc->curtxpow);
  184. clear_bit(SC_OP_HW_RESET, &sc->sc_flags);
  185. ath9k_hw_set_interrupts(ah);
  186. ath9k_hw_enable_interrupts(ah);
  187. if (!(sc->hw->conf.flags & IEEE80211_CONF_OFFCHANNEL) && start) {
  188. if (!test_bit(SC_OP_BEACONS, &sc->sc_flags))
  189. goto work;
  190. ath9k_set_beacon(sc);
  191. if (ah->opmode == NL80211_IFTYPE_STATION &&
  192. test_bit(SC_OP_PRIM_STA_VIF, &sc->sc_flags)) {
  193. spin_lock_irqsave(&sc->sc_pm_lock, flags);
  194. sc->ps_flags |= PS_BEACON_SYNC | PS_WAIT_FOR_BEACON;
  195. spin_unlock_irqrestore(&sc->sc_pm_lock, flags);
  196. }
  197. work:
  198. ath_restart_work(sc);
  199. }
  200. if ((ah->caps.hw_caps & ATH9K_HW_CAP_ANT_DIV_COMB) && sc->ant_rx != 3)
  201. ath_ant_comb_update(sc);
  202. ieee80211_wake_queues(sc->hw);
  203. return true;
  204. }
  205. static int ath_reset_internal(struct ath_softc *sc, struct ath9k_channel *hchan)
  206. {
  207. struct ath_hw *ah = sc->sc_ah;
  208. struct ath_common *common = ath9k_hw_common(ah);
  209. struct ath9k_hw_cal_data *caldata = NULL;
  210. bool fastcc = true;
  211. int r;
  212. __ath_cancel_work(sc);
  213. tasklet_disable(&sc->intr_tq);
  214. spin_lock_bh(&sc->sc_pcu_lock);
  215. if (!(sc->hw->conf.flags & IEEE80211_CONF_OFFCHANNEL)) {
  216. fastcc = false;
  217. caldata = &sc->caldata;
  218. }
  219. if (!hchan) {
  220. fastcc = false;
  221. hchan = ah->curchan;
  222. }
  223. if (!ath_prepare_reset(sc))
  224. fastcc = false;
  225. ath_dbg(common, CONFIG, "Reset to %u MHz, HT40: %d fastcc: %d\n",
  226. hchan->channel, IS_CHAN_HT40(hchan), fastcc);
  227. r = ath9k_hw_reset(ah, hchan, caldata, fastcc);
  228. if (r) {
  229. ath_err(common,
  230. "Unable to reset channel, reset status %d\n", r);
  231. ath9k_hw_enable_interrupts(ah);
  232. ath9k_queue_reset(sc, RESET_TYPE_BB_HANG);
  233. goto out;
  234. }
  235. if (ath9k_hw_mci_is_enabled(sc->sc_ah) &&
  236. (sc->hw->conf.flags & IEEE80211_CONF_OFFCHANNEL))
  237. ath9k_mci_set_txpower(sc, true, false);
  238. if (!ath_complete_reset(sc, true))
  239. r = -EIO;
  240. out:
  241. spin_unlock_bh(&sc->sc_pcu_lock);
  242. tasklet_enable(&sc->intr_tq);
  243. return r;
  244. }
  245. /*
  246. * Set/change channels. If the channel is really being changed, it's done
  247. * by reseting the chip. To accomplish this we must first cleanup any pending
  248. * DMA, then restart stuff.
  249. */
  250. static int ath_set_channel(struct ath_softc *sc, struct ieee80211_hw *hw,
  251. struct ath9k_channel *hchan)
  252. {
  253. int r;
  254. if (test_bit(SC_OP_INVALID, &sc->sc_flags))
  255. return -EIO;
  256. r = ath_reset_internal(sc, hchan);
  257. return r;
  258. }
  259. static void ath_node_attach(struct ath_softc *sc, struct ieee80211_sta *sta,
  260. struct ieee80211_vif *vif)
  261. {
  262. struct ath_node *an;
  263. an = (struct ath_node *)sta->drv_priv;
  264. an->sc = sc;
  265. an->sta = sta;
  266. an->vif = vif;
  267. ath_tx_node_init(sc, an);
  268. if (sta->ht_cap.ht_supported) {
  269. an->maxampdu = 1 << (IEEE80211_HT_MAX_AMPDU_FACTOR +
  270. sta->ht_cap.ampdu_factor);
  271. an->mpdudensity = ath9k_parse_mpdudensity(sta->ht_cap.ampdu_density);
  272. }
  273. }
  274. static void ath_node_detach(struct ath_softc *sc, struct ieee80211_sta *sta)
  275. {
  276. struct ath_node *an = (struct ath_node *)sta->drv_priv;
  277. ath_tx_node_cleanup(sc, an);
  278. }
  279. void ath9k_tasklet(unsigned long data)
  280. {
  281. struct ath_softc *sc = (struct ath_softc *)data;
  282. struct ath_hw *ah = sc->sc_ah;
  283. struct ath_common *common = ath9k_hw_common(ah);
  284. enum ath_reset_type type;
  285. unsigned long flags;
  286. u32 status = sc->intrstatus;
  287. u32 rxmask;
  288. ath9k_ps_wakeup(sc);
  289. spin_lock(&sc->sc_pcu_lock);
  290. if ((status & ATH9K_INT_FATAL) ||
  291. (status & ATH9K_INT_BB_WATCHDOG)) {
  292. if (status & ATH9K_INT_FATAL)
  293. type = RESET_TYPE_FATAL_INT;
  294. else
  295. type = RESET_TYPE_BB_WATCHDOG;
  296. ath9k_queue_reset(sc, type);
  297. goto out;
  298. }
  299. spin_lock_irqsave(&sc->sc_pm_lock, flags);
  300. if ((status & ATH9K_INT_TSFOOR) && sc->ps_enabled) {
  301. /*
  302. * TSF sync does not look correct; remain awake to sync with
  303. * the next Beacon.
  304. */
  305. ath_dbg(common, PS, "TSFOOR - Sync with next Beacon\n");
  306. sc->ps_flags |= PS_WAIT_FOR_BEACON | PS_BEACON_SYNC;
  307. }
  308. spin_unlock_irqrestore(&sc->sc_pm_lock, flags);
  309. if (ah->caps.hw_caps & ATH9K_HW_CAP_EDMA)
  310. rxmask = (ATH9K_INT_RXHP | ATH9K_INT_RXLP | ATH9K_INT_RXEOL |
  311. ATH9K_INT_RXORN);
  312. else
  313. rxmask = (ATH9K_INT_RX | ATH9K_INT_RXEOL | ATH9K_INT_RXORN);
  314. if (status & rxmask) {
  315. /* Check for high priority Rx first */
  316. if ((ah->caps.hw_caps & ATH9K_HW_CAP_EDMA) &&
  317. (status & ATH9K_INT_RXHP))
  318. ath_rx_tasklet(sc, 0, true);
  319. ath_rx_tasklet(sc, 0, false);
  320. }
  321. if (status & ATH9K_INT_TX) {
  322. if (ah->caps.hw_caps & ATH9K_HW_CAP_EDMA)
  323. ath_tx_edma_tasklet(sc);
  324. else
  325. ath_tx_tasklet(sc);
  326. }
  327. ath9k_btcoex_handle_interrupt(sc, status);
  328. out:
  329. /* re-enable hardware interrupt */
  330. ath9k_hw_enable_interrupts(ah);
  331. spin_unlock(&sc->sc_pcu_lock);
  332. ath9k_ps_restore(sc);
  333. }
  334. irqreturn_t ath_isr(int irq, void *dev)
  335. {
  336. #define SCHED_INTR ( \
  337. ATH9K_INT_FATAL | \
  338. ATH9K_INT_BB_WATCHDOG | \
  339. ATH9K_INT_RXORN | \
  340. ATH9K_INT_RXEOL | \
  341. ATH9K_INT_RX | \
  342. ATH9K_INT_RXLP | \
  343. ATH9K_INT_RXHP | \
  344. ATH9K_INT_TX | \
  345. ATH9K_INT_BMISS | \
  346. ATH9K_INT_CST | \
  347. ATH9K_INT_TSFOOR | \
  348. ATH9K_INT_GENTIMER | \
  349. ATH9K_INT_MCI)
  350. struct ath_softc *sc = dev;
  351. struct ath_hw *ah = sc->sc_ah;
  352. struct ath_common *common = ath9k_hw_common(ah);
  353. enum ath9k_int status;
  354. bool sched = false;
  355. /*
  356. * The hardware is not ready/present, don't
  357. * touch anything. Note this can happen early
  358. * on if the IRQ is shared.
  359. */
  360. if (test_bit(SC_OP_INVALID, &sc->sc_flags))
  361. return IRQ_NONE;
  362. /* shared irq, not for us */
  363. if (!ath9k_hw_intrpend(ah))
  364. return IRQ_NONE;
  365. if (test_bit(SC_OP_HW_RESET, &sc->sc_flags)) {
  366. ath9k_hw_kill_interrupts(ah);
  367. return IRQ_HANDLED;
  368. }
  369. /*
  370. * Figure out the reason(s) for the interrupt. Note
  371. * that the hal returns a pseudo-ISR that may include
  372. * bits we haven't explicitly enabled so we mask the
  373. * value to insure we only process bits we requested.
  374. */
  375. ath9k_hw_getisr(ah, &status); /* NB: clears ISR too */
  376. status &= ah->imask; /* discard unasked-for bits */
  377. /*
  378. * If there are no status bits set, then this interrupt was not
  379. * for me (should have been caught above).
  380. */
  381. if (!status)
  382. return IRQ_NONE;
  383. /* Cache the status */
  384. sc->intrstatus = status;
  385. if (status & SCHED_INTR)
  386. sched = true;
  387. /*
  388. * If a FATAL or RXORN interrupt is received, we have to reset the
  389. * chip immediately.
  390. */
  391. if ((status & ATH9K_INT_FATAL) || ((status & ATH9K_INT_RXORN) &&
  392. !(ah->caps.hw_caps & ATH9K_HW_CAP_EDMA)))
  393. goto chip_reset;
  394. if ((ah->caps.hw_caps & ATH9K_HW_CAP_EDMA) &&
  395. (status & ATH9K_INT_BB_WATCHDOG)) {
  396. spin_lock(&common->cc_lock);
  397. ath_hw_cycle_counters_update(common);
  398. ar9003_hw_bb_watchdog_dbg_info(ah);
  399. spin_unlock(&common->cc_lock);
  400. goto chip_reset;
  401. }
  402. #ifdef CONFIG_PM_SLEEP
  403. if (status & ATH9K_INT_BMISS) {
  404. if (atomic_read(&sc->wow_sleep_proc_intr) == 0) {
  405. ath_dbg(common, ANY, "during WoW we got a BMISS\n");
  406. atomic_inc(&sc->wow_got_bmiss_intr);
  407. atomic_dec(&sc->wow_sleep_proc_intr);
  408. }
  409. }
  410. #endif
  411. if (status & ATH9K_INT_SWBA)
  412. tasklet_schedule(&sc->bcon_tasklet);
  413. if (status & ATH9K_INT_TXURN)
  414. ath9k_hw_updatetxtriglevel(ah, true);
  415. if (status & ATH9K_INT_RXEOL) {
  416. ah->imask &= ~(ATH9K_INT_RXEOL | ATH9K_INT_RXORN);
  417. ath9k_hw_set_interrupts(ah);
  418. }
  419. if (!(ah->caps.hw_caps & ATH9K_HW_CAP_AUTOSLEEP))
  420. if (status & ATH9K_INT_TIM_TIMER) {
  421. if (ATH_DBG_WARN_ON_ONCE(sc->ps_idle))
  422. goto chip_reset;
  423. /* Clear RxAbort bit so that we can
  424. * receive frames */
  425. ath9k_setpower(sc, ATH9K_PM_AWAKE);
  426. spin_lock(&sc->sc_pm_lock);
  427. ath9k_hw_setrxabort(sc->sc_ah, 0);
  428. sc->ps_flags |= PS_WAIT_FOR_BEACON;
  429. spin_unlock(&sc->sc_pm_lock);
  430. }
  431. chip_reset:
  432. ath_debug_stat_interrupt(sc, status);
  433. if (sched) {
  434. /* turn off every interrupt */
  435. ath9k_hw_disable_interrupts(ah);
  436. tasklet_schedule(&sc->intr_tq);
  437. }
  438. return IRQ_HANDLED;
  439. #undef SCHED_INTR
  440. }
  441. static int ath_reset(struct ath_softc *sc)
  442. {
  443. int i, r;
  444. ath9k_ps_wakeup(sc);
  445. r = ath_reset_internal(sc, NULL);
  446. for (i = 0; i < ATH9K_NUM_TX_QUEUES; i++) {
  447. if (!ATH_TXQ_SETUP(sc, i))
  448. continue;
  449. spin_lock_bh(&sc->tx.txq[i].axq_lock);
  450. ath_txq_schedule(sc, &sc->tx.txq[i]);
  451. spin_unlock_bh(&sc->tx.txq[i].axq_lock);
  452. }
  453. ath9k_ps_restore(sc);
  454. return r;
  455. }
  456. void ath9k_queue_reset(struct ath_softc *sc, enum ath_reset_type type)
  457. {
  458. #ifdef CONFIG_ATH9K_DEBUGFS
  459. RESET_STAT_INC(sc, type);
  460. #endif
  461. set_bit(SC_OP_HW_RESET, &sc->sc_flags);
  462. ieee80211_queue_work(sc->hw, &sc->hw_reset_work);
  463. }
  464. void ath_reset_work(struct work_struct *work)
  465. {
  466. struct ath_softc *sc = container_of(work, struct ath_softc, hw_reset_work);
  467. ath_reset(sc);
  468. }
  469. /**********************/
  470. /* mac80211 callbacks */
  471. /**********************/
  472. static int ath9k_start(struct ieee80211_hw *hw)
  473. {
  474. struct ath_softc *sc = hw->priv;
  475. struct ath_hw *ah = sc->sc_ah;
  476. struct ath_common *common = ath9k_hw_common(ah);
  477. struct ieee80211_channel *curchan = hw->conf.channel;
  478. struct ath9k_channel *init_channel;
  479. int r;
  480. ath_dbg(common, CONFIG,
  481. "Starting driver with initial channel: %d MHz\n",
  482. curchan->center_freq);
  483. ath9k_ps_wakeup(sc);
  484. mutex_lock(&sc->mutex);
  485. init_channel = ath9k_cmn_get_curchannel(hw, ah);
  486. /* Reset SERDES registers */
  487. ath9k_hw_configpcipowersave(ah, false);
  488. /*
  489. * The basic interface to setting the hardware in a good
  490. * state is ``reset''. On return the hardware is known to
  491. * be powered up and with interrupts disabled. This must
  492. * be followed by initialization of the appropriate bits
  493. * and then setup of the interrupt mask.
  494. */
  495. spin_lock_bh(&sc->sc_pcu_lock);
  496. atomic_set(&ah->intr_ref_cnt, -1);
  497. r = ath9k_hw_reset(ah, init_channel, ah->caldata, false);
  498. if (r) {
  499. ath_err(common,
  500. "Unable to reset hardware; reset status %d (freq %u MHz)\n",
  501. r, curchan->center_freq);
  502. ah->reset_power_on = false;
  503. }
  504. /* Setup our intr mask. */
  505. ah->imask = ATH9K_INT_TX | ATH9K_INT_RXEOL |
  506. ATH9K_INT_RXORN | ATH9K_INT_FATAL |
  507. ATH9K_INT_GLOBAL;
  508. if (ah->caps.hw_caps & ATH9K_HW_CAP_EDMA)
  509. ah->imask |= ATH9K_INT_RXHP |
  510. ATH9K_INT_RXLP |
  511. ATH9K_INT_BB_WATCHDOG;
  512. else
  513. ah->imask |= ATH9K_INT_RX;
  514. ah->imask |= ATH9K_INT_GTT;
  515. if (ah->caps.hw_caps & ATH9K_HW_CAP_HT)
  516. ah->imask |= ATH9K_INT_CST;
  517. ath_mci_enable(sc);
  518. clear_bit(SC_OP_INVALID, &sc->sc_flags);
  519. sc->sc_ah->is_monitoring = false;
  520. if (!ath_complete_reset(sc, false))
  521. ah->reset_power_on = false;
  522. if (ah->led_pin >= 0) {
  523. ath9k_hw_cfg_output(ah, ah->led_pin,
  524. AR_GPIO_OUTPUT_MUX_AS_OUTPUT);
  525. ath9k_hw_set_gpio(ah, ah->led_pin, 0);
  526. }
  527. /*
  528. * Reset key cache to sane defaults (all entries cleared) instead of
  529. * semi-random values after suspend/resume.
  530. */
  531. ath9k_cmn_init_crypto(sc->sc_ah);
  532. spin_unlock_bh(&sc->sc_pcu_lock);
  533. mutex_unlock(&sc->mutex);
  534. ath9k_ps_restore(sc);
  535. return 0;
  536. }
  537. static void ath9k_tx(struct ieee80211_hw *hw,
  538. struct ieee80211_tx_control *control,
  539. struct sk_buff *skb)
  540. {
  541. struct ath_softc *sc = hw->priv;
  542. struct ath_common *common = ath9k_hw_common(sc->sc_ah);
  543. struct ath_tx_control txctl;
  544. struct ieee80211_hdr *hdr = (struct ieee80211_hdr *) skb->data;
  545. unsigned long flags;
  546. if (sc->ps_enabled) {
  547. /*
  548. * mac80211 does not set PM field for normal data frames, so we
  549. * need to update that based on the current PS mode.
  550. */
  551. if (ieee80211_is_data(hdr->frame_control) &&
  552. !ieee80211_is_nullfunc(hdr->frame_control) &&
  553. !ieee80211_has_pm(hdr->frame_control)) {
  554. ath_dbg(common, PS,
  555. "Add PM=1 for a TX frame while in PS mode\n");
  556. hdr->frame_control |= cpu_to_le16(IEEE80211_FCTL_PM);
  557. }
  558. }
  559. if (unlikely(sc->sc_ah->power_mode == ATH9K_PM_NETWORK_SLEEP)) {
  560. /*
  561. * We are using PS-Poll and mac80211 can request TX while in
  562. * power save mode. Need to wake up hardware for the TX to be
  563. * completed and if needed, also for RX of buffered frames.
  564. */
  565. ath9k_ps_wakeup(sc);
  566. spin_lock_irqsave(&sc->sc_pm_lock, flags);
  567. if (!(sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_AUTOSLEEP))
  568. ath9k_hw_setrxabort(sc->sc_ah, 0);
  569. if (ieee80211_is_pspoll(hdr->frame_control)) {
  570. ath_dbg(common, PS,
  571. "Sending PS-Poll to pick a buffered frame\n");
  572. sc->ps_flags |= PS_WAIT_FOR_PSPOLL_DATA;
  573. } else {
  574. ath_dbg(common, PS, "Wake up to complete TX\n");
  575. sc->ps_flags |= PS_WAIT_FOR_TX_ACK;
  576. }
  577. /*
  578. * The actual restore operation will happen only after
  579. * the ps_flags bit is cleared. We are just dropping
  580. * the ps_usecount here.
  581. */
  582. spin_unlock_irqrestore(&sc->sc_pm_lock, flags);
  583. ath9k_ps_restore(sc);
  584. }
  585. /*
  586. * Cannot tx while the hardware is in full sleep, it first needs a full
  587. * chip reset to recover from that
  588. */
  589. if (unlikely(sc->sc_ah->power_mode == ATH9K_PM_FULL_SLEEP)) {
  590. ath_err(common, "TX while HW is in FULL_SLEEP mode\n");
  591. goto exit;
  592. }
  593. memset(&txctl, 0, sizeof(struct ath_tx_control));
  594. txctl.txq = sc->tx.txq_map[skb_get_queue_mapping(skb)];
  595. txctl.sta = control->sta;
  596. ath_dbg(common, XMIT, "transmitting packet, skb: %p\n", skb);
  597. if (ath_tx_start(hw, skb, &txctl) != 0) {
  598. ath_dbg(common, XMIT, "TX failed\n");
  599. TX_STAT_INC(txctl.txq->axq_qnum, txfailed);
  600. goto exit;
  601. }
  602. return;
  603. exit:
  604. ieee80211_free_txskb(hw, skb);
  605. }
  606. static void ath9k_stop(struct ieee80211_hw *hw)
  607. {
  608. struct ath_softc *sc = hw->priv;
  609. struct ath_hw *ah = sc->sc_ah;
  610. struct ath_common *common = ath9k_hw_common(ah);
  611. bool prev_idle;
  612. mutex_lock(&sc->mutex);
  613. ath_cancel_work(sc);
  614. del_timer_sync(&sc->rx_poll_timer);
  615. if (test_bit(SC_OP_INVALID, &sc->sc_flags)) {
  616. ath_dbg(common, ANY, "Device not present\n");
  617. mutex_unlock(&sc->mutex);
  618. return;
  619. }
  620. /* Ensure HW is awake when we try to shut it down. */
  621. ath9k_ps_wakeup(sc);
  622. spin_lock_bh(&sc->sc_pcu_lock);
  623. /* prevent tasklets to enable interrupts once we disable them */
  624. ah->imask &= ~ATH9K_INT_GLOBAL;
  625. /* make sure h/w will not generate any interrupt
  626. * before setting the invalid flag. */
  627. ath9k_hw_disable_interrupts(ah);
  628. spin_unlock_bh(&sc->sc_pcu_lock);
  629. /* we can now sync irq and kill any running tasklets, since we already
  630. * disabled interrupts and not holding a spin lock */
  631. synchronize_irq(sc->irq);
  632. tasklet_kill(&sc->intr_tq);
  633. tasklet_kill(&sc->bcon_tasklet);
  634. prev_idle = sc->ps_idle;
  635. sc->ps_idle = true;
  636. spin_lock_bh(&sc->sc_pcu_lock);
  637. if (ah->led_pin >= 0) {
  638. ath9k_hw_set_gpio(ah, ah->led_pin, 1);
  639. ath9k_hw_cfg_gpio_input(ah, ah->led_pin);
  640. }
  641. ath_prepare_reset(sc);
  642. if (sc->rx.frag) {
  643. dev_kfree_skb_any(sc->rx.frag);
  644. sc->rx.frag = NULL;
  645. }
  646. if (!ah->curchan)
  647. ah->curchan = ath9k_cmn_get_curchannel(hw, ah);
  648. ath9k_hw_reset(ah, ah->curchan, ah->caldata, false);
  649. ath9k_hw_phy_disable(ah);
  650. ath9k_hw_configpcipowersave(ah, true);
  651. spin_unlock_bh(&sc->sc_pcu_lock);
  652. ath9k_ps_restore(sc);
  653. set_bit(SC_OP_INVALID, &sc->sc_flags);
  654. sc->ps_idle = prev_idle;
  655. mutex_unlock(&sc->mutex);
  656. ath_dbg(common, CONFIG, "Driver halt\n");
  657. }
  658. bool ath9k_uses_beacons(int type)
  659. {
  660. switch (type) {
  661. case NL80211_IFTYPE_AP:
  662. case NL80211_IFTYPE_ADHOC:
  663. case NL80211_IFTYPE_MESH_POINT:
  664. return true;
  665. default:
  666. return false;
  667. }
  668. }
  669. static void ath9k_vif_iter(void *data, u8 *mac, struct ieee80211_vif *vif)
  670. {
  671. struct ath9k_vif_iter_data *iter_data = data;
  672. int i;
  673. if (iter_data->hw_macaddr)
  674. for (i = 0; i < ETH_ALEN; i++)
  675. iter_data->mask[i] &=
  676. ~(iter_data->hw_macaddr[i] ^ mac[i]);
  677. switch (vif->type) {
  678. case NL80211_IFTYPE_AP:
  679. iter_data->naps++;
  680. break;
  681. case NL80211_IFTYPE_STATION:
  682. iter_data->nstations++;
  683. break;
  684. case NL80211_IFTYPE_ADHOC:
  685. iter_data->nadhocs++;
  686. break;
  687. case NL80211_IFTYPE_MESH_POINT:
  688. iter_data->nmeshes++;
  689. break;
  690. case NL80211_IFTYPE_WDS:
  691. iter_data->nwds++;
  692. break;
  693. default:
  694. break;
  695. }
  696. }
  697. static void ath9k_sta_vif_iter(void *data, u8 *mac, struct ieee80211_vif *vif)
  698. {
  699. struct ath_softc *sc = data;
  700. struct ath_vif *avp = (void *)vif->drv_priv;
  701. if (vif->type != NL80211_IFTYPE_STATION)
  702. return;
  703. if (avp->primary_sta_vif)
  704. ath9k_set_assoc_state(sc, vif);
  705. }
  706. /* Called with sc->mutex held. */
  707. void ath9k_calculate_iter_data(struct ieee80211_hw *hw,
  708. struct ieee80211_vif *vif,
  709. struct ath9k_vif_iter_data *iter_data)
  710. {
  711. struct ath_softc *sc = hw->priv;
  712. struct ath_hw *ah = sc->sc_ah;
  713. struct ath_common *common = ath9k_hw_common(ah);
  714. /*
  715. * Use the hardware MAC address as reference, the hardware uses it
  716. * together with the BSSID mask when matching addresses.
  717. */
  718. memset(iter_data, 0, sizeof(*iter_data));
  719. iter_data->hw_macaddr = common->macaddr;
  720. memset(&iter_data->mask, 0xff, ETH_ALEN);
  721. if (vif)
  722. ath9k_vif_iter(iter_data, vif->addr, vif);
  723. /* Get list of all active MAC addresses */
  724. ieee80211_iterate_active_interfaces_atomic(
  725. sc->hw, IEEE80211_IFACE_ITER_RESUME_ALL,
  726. ath9k_vif_iter, iter_data);
  727. }
  728. /* Called with sc->mutex held. */
  729. static void ath9k_calculate_summary_state(struct ieee80211_hw *hw,
  730. struct ieee80211_vif *vif)
  731. {
  732. struct ath_softc *sc = hw->priv;
  733. struct ath_hw *ah = sc->sc_ah;
  734. struct ath_common *common = ath9k_hw_common(ah);
  735. struct ath9k_vif_iter_data iter_data;
  736. enum nl80211_iftype old_opmode = ah->opmode;
  737. ath9k_calculate_iter_data(hw, vif, &iter_data);
  738. memcpy(common->bssidmask, iter_data.mask, ETH_ALEN);
  739. ath_hw_setbssidmask(common);
  740. if (iter_data.naps > 0) {
  741. ath9k_hw_set_tsfadjust(ah, true);
  742. ah->opmode = NL80211_IFTYPE_AP;
  743. } else {
  744. ath9k_hw_set_tsfadjust(ah, false);
  745. if (iter_data.nmeshes)
  746. ah->opmode = NL80211_IFTYPE_MESH_POINT;
  747. else if (iter_data.nwds)
  748. ah->opmode = NL80211_IFTYPE_AP;
  749. else if (iter_data.nadhocs)
  750. ah->opmode = NL80211_IFTYPE_ADHOC;
  751. else
  752. ah->opmode = NL80211_IFTYPE_STATION;
  753. }
  754. ath9k_hw_setopmode(ah);
  755. if ((iter_data.nstations + iter_data.nadhocs + iter_data.nmeshes) > 0)
  756. ah->imask |= ATH9K_INT_TSFOOR;
  757. else
  758. ah->imask &= ~ATH9K_INT_TSFOOR;
  759. ath9k_hw_set_interrupts(ah);
  760. /*
  761. * If we are changing the opmode to STATION,
  762. * a beacon sync needs to be done.
  763. */
  764. if (ah->opmode == NL80211_IFTYPE_STATION &&
  765. old_opmode == NL80211_IFTYPE_AP &&
  766. test_bit(SC_OP_PRIM_STA_VIF, &sc->sc_flags)) {
  767. ieee80211_iterate_active_interfaces_atomic(
  768. sc->hw, IEEE80211_IFACE_ITER_RESUME_ALL,
  769. ath9k_sta_vif_iter, sc);
  770. }
  771. }
  772. static int ath9k_add_interface(struct ieee80211_hw *hw,
  773. struct ieee80211_vif *vif)
  774. {
  775. struct ath_softc *sc = hw->priv;
  776. struct ath_hw *ah = sc->sc_ah;
  777. struct ath_common *common = ath9k_hw_common(ah);
  778. mutex_lock(&sc->mutex);
  779. ath_dbg(common, CONFIG, "Attach a VIF of type: %d\n", vif->type);
  780. sc->nvifs++;
  781. ath9k_ps_wakeup(sc);
  782. ath9k_calculate_summary_state(hw, vif);
  783. ath9k_ps_restore(sc);
  784. if (ath9k_uses_beacons(vif->type))
  785. ath9k_beacon_assign_slot(sc, vif);
  786. mutex_unlock(&sc->mutex);
  787. return 0;
  788. }
  789. static int ath9k_change_interface(struct ieee80211_hw *hw,
  790. struct ieee80211_vif *vif,
  791. enum nl80211_iftype new_type,
  792. bool p2p)
  793. {
  794. struct ath_softc *sc = hw->priv;
  795. struct ath_common *common = ath9k_hw_common(sc->sc_ah);
  796. ath_dbg(common, CONFIG, "Change Interface\n");
  797. mutex_lock(&sc->mutex);
  798. if (ath9k_uses_beacons(vif->type))
  799. ath9k_beacon_remove_slot(sc, vif);
  800. vif->type = new_type;
  801. vif->p2p = p2p;
  802. ath9k_ps_wakeup(sc);
  803. ath9k_calculate_summary_state(hw, vif);
  804. ath9k_ps_restore(sc);
  805. if (ath9k_uses_beacons(vif->type))
  806. ath9k_beacon_assign_slot(sc, vif);
  807. mutex_unlock(&sc->mutex);
  808. return 0;
  809. }
  810. static void ath9k_remove_interface(struct ieee80211_hw *hw,
  811. struct ieee80211_vif *vif)
  812. {
  813. struct ath_softc *sc = hw->priv;
  814. struct ath_common *common = ath9k_hw_common(sc->sc_ah);
  815. ath_dbg(common, CONFIG, "Detach Interface\n");
  816. mutex_lock(&sc->mutex);
  817. sc->nvifs--;
  818. if (ath9k_uses_beacons(vif->type))
  819. ath9k_beacon_remove_slot(sc, vif);
  820. ath9k_ps_wakeup(sc);
  821. ath9k_calculate_summary_state(hw, NULL);
  822. ath9k_ps_restore(sc);
  823. mutex_unlock(&sc->mutex);
  824. }
  825. static void ath9k_enable_ps(struct ath_softc *sc)
  826. {
  827. struct ath_hw *ah = sc->sc_ah;
  828. struct ath_common *common = ath9k_hw_common(ah);
  829. sc->ps_enabled = true;
  830. if (!(ah->caps.hw_caps & ATH9K_HW_CAP_AUTOSLEEP)) {
  831. if ((ah->imask & ATH9K_INT_TIM_TIMER) == 0) {
  832. ah->imask |= ATH9K_INT_TIM_TIMER;
  833. ath9k_hw_set_interrupts(ah);
  834. }
  835. ath9k_hw_setrxabort(ah, 1);
  836. }
  837. ath_dbg(common, PS, "PowerSave enabled\n");
  838. }
  839. static void ath9k_disable_ps(struct ath_softc *sc)
  840. {
  841. struct ath_hw *ah = sc->sc_ah;
  842. struct ath_common *common = ath9k_hw_common(ah);
  843. sc->ps_enabled = false;
  844. ath9k_hw_setpower(ah, ATH9K_PM_AWAKE);
  845. if (!(ah->caps.hw_caps & ATH9K_HW_CAP_AUTOSLEEP)) {
  846. ath9k_hw_setrxabort(ah, 0);
  847. sc->ps_flags &= ~(PS_WAIT_FOR_BEACON |
  848. PS_WAIT_FOR_CAB |
  849. PS_WAIT_FOR_PSPOLL_DATA |
  850. PS_WAIT_FOR_TX_ACK);
  851. if (ah->imask & ATH9K_INT_TIM_TIMER) {
  852. ah->imask &= ~ATH9K_INT_TIM_TIMER;
  853. ath9k_hw_set_interrupts(ah);
  854. }
  855. }
  856. ath_dbg(common, PS, "PowerSave disabled\n");
  857. }
  858. void ath9k_spectral_scan_trigger(struct ieee80211_hw *hw)
  859. {
  860. struct ath_softc *sc = hw->priv;
  861. struct ath_hw *ah = sc->sc_ah;
  862. struct ath_common *common = ath9k_hw_common(ah);
  863. u32 rxfilter;
  864. if (!ath9k_hw_ops(ah)->spectral_scan_trigger) {
  865. ath_err(common, "spectrum analyzer not implemented on this hardware\n");
  866. return;
  867. }
  868. ath9k_ps_wakeup(sc);
  869. rxfilter = ath9k_hw_getrxfilter(ah);
  870. ath9k_hw_setrxfilter(ah, rxfilter |
  871. ATH9K_RX_FILTER_PHYRADAR |
  872. ATH9K_RX_FILTER_PHYERR);
  873. /* TODO: usually this should not be neccesary, but for some reason
  874. * (or in some mode?) the trigger must be called after the
  875. * configuration, otherwise the register will have its values reset
  876. * (on my ar9220 to value 0x01002310)
  877. */
  878. ath9k_spectral_scan_config(hw, sc->spectral_mode);
  879. ath9k_hw_ops(ah)->spectral_scan_trigger(ah);
  880. ath9k_ps_restore(sc);
  881. }
  882. int ath9k_spectral_scan_config(struct ieee80211_hw *hw,
  883. enum spectral_mode spectral_mode)
  884. {
  885. struct ath_softc *sc = hw->priv;
  886. struct ath_hw *ah = sc->sc_ah;
  887. struct ath_common *common = ath9k_hw_common(ah);
  888. if (!ath9k_hw_ops(ah)->spectral_scan_trigger) {
  889. ath_err(common, "spectrum analyzer not implemented on this hardware\n");
  890. return -1;
  891. }
  892. switch (spectral_mode) {
  893. case SPECTRAL_DISABLED:
  894. sc->spec_config.enabled = 0;
  895. break;
  896. case SPECTRAL_BACKGROUND:
  897. /* send endless samples.
  898. * TODO: is this really useful for "background"?
  899. */
  900. sc->spec_config.endless = 1;
  901. sc->spec_config.enabled = 1;
  902. break;
  903. case SPECTRAL_CHANSCAN:
  904. case SPECTRAL_MANUAL:
  905. sc->spec_config.endless = 0;
  906. sc->spec_config.enabled = 1;
  907. break;
  908. default:
  909. return -1;
  910. }
  911. ath9k_ps_wakeup(sc);
  912. ath9k_hw_ops(ah)->spectral_scan_config(ah, &sc->spec_config);
  913. ath9k_ps_restore(sc);
  914. sc->spectral_mode = spectral_mode;
  915. return 0;
  916. }
  917. static int ath9k_config(struct ieee80211_hw *hw, u32 changed)
  918. {
  919. struct ath_softc *sc = hw->priv;
  920. struct ath_hw *ah = sc->sc_ah;
  921. struct ath_common *common = ath9k_hw_common(ah);
  922. struct ieee80211_conf *conf = &hw->conf;
  923. bool reset_channel = false;
  924. ath9k_ps_wakeup(sc);
  925. mutex_lock(&sc->mutex);
  926. if (changed & IEEE80211_CONF_CHANGE_IDLE) {
  927. sc->ps_idle = !!(conf->flags & IEEE80211_CONF_IDLE);
  928. if (sc->ps_idle) {
  929. ath_cancel_work(sc);
  930. ath9k_stop_btcoex(sc);
  931. } else {
  932. ath9k_start_btcoex(sc);
  933. /*
  934. * The chip needs a reset to properly wake up from
  935. * full sleep
  936. */
  937. reset_channel = ah->chip_fullsleep;
  938. }
  939. }
  940. /*
  941. * We just prepare to enable PS. We have to wait until our AP has
  942. * ACK'd our null data frame to disable RX otherwise we'll ignore
  943. * those ACKs and end up retransmitting the same null data frames.
  944. * IEEE80211_CONF_CHANGE_PS is only passed by mac80211 for STA mode.
  945. */
  946. if (changed & IEEE80211_CONF_CHANGE_PS) {
  947. unsigned long flags;
  948. spin_lock_irqsave(&sc->sc_pm_lock, flags);
  949. if (conf->flags & IEEE80211_CONF_PS)
  950. ath9k_enable_ps(sc);
  951. else
  952. ath9k_disable_ps(sc);
  953. spin_unlock_irqrestore(&sc->sc_pm_lock, flags);
  954. }
  955. if (changed & IEEE80211_CONF_CHANGE_MONITOR) {
  956. if (conf->flags & IEEE80211_CONF_MONITOR) {
  957. ath_dbg(common, CONFIG, "Monitor mode is enabled\n");
  958. sc->sc_ah->is_monitoring = true;
  959. } else {
  960. ath_dbg(common, CONFIG, "Monitor mode is disabled\n");
  961. sc->sc_ah->is_monitoring = false;
  962. }
  963. }
  964. if ((changed & IEEE80211_CONF_CHANGE_CHANNEL) || reset_channel) {
  965. struct ieee80211_channel *curchan = hw->conf.channel;
  966. int pos = curchan->hw_value;
  967. int old_pos = -1;
  968. unsigned long flags;
  969. if (ah->curchan)
  970. old_pos = ah->curchan - &ah->channels[0];
  971. ath_dbg(common, CONFIG, "Set channel: %d MHz type: %d\n",
  972. curchan->center_freq, conf->channel_type);
  973. /* update survey stats for the old channel before switching */
  974. spin_lock_irqsave(&common->cc_lock, flags);
  975. ath_update_survey_stats(sc);
  976. spin_unlock_irqrestore(&common->cc_lock, flags);
  977. /*
  978. * Preserve the current channel values, before updating
  979. * the same channel
  980. */
  981. if (ah->curchan && (old_pos == pos))
  982. ath9k_hw_getnf(ah, ah->curchan);
  983. ath9k_cmn_update_ichannel(&sc->sc_ah->channels[pos],
  984. curchan, conf->channel_type);
  985. /*
  986. * If the operating channel changes, change the survey in-use flags
  987. * along with it.
  988. * Reset the survey data for the new channel, unless we're switching
  989. * back to the operating channel from an off-channel operation.
  990. */
  991. if (!(hw->conf.flags & IEEE80211_CONF_OFFCHANNEL) &&
  992. sc->cur_survey != &sc->survey[pos]) {
  993. if (sc->cur_survey)
  994. sc->cur_survey->filled &= ~SURVEY_INFO_IN_USE;
  995. sc->cur_survey = &sc->survey[pos];
  996. memset(sc->cur_survey, 0, sizeof(struct survey_info));
  997. sc->cur_survey->filled |= SURVEY_INFO_IN_USE;
  998. } else if (!(sc->survey[pos].filled & SURVEY_INFO_IN_USE)) {
  999. memset(&sc->survey[pos], 0, sizeof(struct survey_info));
  1000. }
  1001. if (ath_set_channel(sc, hw, &sc->sc_ah->channels[pos]) < 0) {
  1002. ath_err(common, "Unable to set channel\n");
  1003. mutex_unlock(&sc->mutex);
  1004. ath9k_ps_restore(sc);
  1005. return -EINVAL;
  1006. }
  1007. /*
  1008. * The most recent snapshot of channel->noisefloor for the old
  1009. * channel is only available after the hardware reset. Copy it to
  1010. * the survey stats now.
  1011. */
  1012. if (old_pos >= 0)
  1013. ath_update_survey_nf(sc, old_pos);
  1014. /*
  1015. * Enable radar pulse detection if on a DFS channel. Spectral
  1016. * scanning and radar detection can not be used concurrently.
  1017. */
  1018. if (hw->conf.radar_enabled) {
  1019. u32 rxfilter;
  1020. /* set HW specific DFS configuration */
  1021. ath9k_hw_set_radar_params(ah);
  1022. rxfilter = ath9k_hw_getrxfilter(ah);
  1023. rxfilter |= ATH9K_RX_FILTER_PHYRADAR |
  1024. ATH9K_RX_FILTER_PHYERR;
  1025. ath9k_hw_setrxfilter(ah, rxfilter);
  1026. ath_dbg(common, DFS, "DFS enabled at freq %d\n",
  1027. curchan->center_freq);
  1028. } else {
  1029. /* perform spectral scan if requested. */
  1030. if (sc->scanning &&
  1031. sc->spectral_mode == SPECTRAL_CHANSCAN)
  1032. ath9k_spectral_scan_trigger(hw);
  1033. }
  1034. }
  1035. if (changed & IEEE80211_CONF_CHANGE_POWER) {
  1036. ath_dbg(common, CONFIG, "Set power: %d\n", conf->power_level);
  1037. sc->config.txpowlimit = 2 * conf->power_level;
  1038. ath9k_cmn_update_txpow(ah, sc->curtxpow,
  1039. sc->config.txpowlimit, &sc->curtxpow);
  1040. }
  1041. mutex_unlock(&sc->mutex);
  1042. ath9k_ps_restore(sc);
  1043. return 0;
  1044. }
  1045. #define SUPPORTED_FILTERS \
  1046. (FIF_PROMISC_IN_BSS | \
  1047. FIF_ALLMULTI | \
  1048. FIF_CONTROL | \
  1049. FIF_PSPOLL | \
  1050. FIF_OTHER_BSS | \
  1051. FIF_BCN_PRBRESP_PROMISC | \
  1052. FIF_PROBE_REQ | \
  1053. FIF_FCSFAIL)
  1054. /* FIXME: sc->sc_full_reset ? */
  1055. static void ath9k_configure_filter(struct ieee80211_hw *hw,
  1056. unsigned int changed_flags,
  1057. unsigned int *total_flags,
  1058. u64 multicast)
  1059. {
  1060. struct ath_softc *sc = hw->priv;
  1061. u32 rfilt;
  1062. changed_flags &= SUPPORTED_FILTERS;
  1063. *total_flags &= SUPPORTED_FILTERS;
  1064. sc->rx.rxfilter = *total_flags;
  1065. ath9k_ps_wakeup(sc);
  1066. rfilt = ath_calcrxfilter(sc);
  1067. ath9k_hw_setrxfilter(sc->sc_ah, rfilt);
  1068. ath9k_ps_restore(sc);
  1069. ath_dbg(ath9k_hw_common(sc->sc_ah), CONFIG, "Set HW RX filter: 0x%x\n",
  1070. rfilt);
  1071. }
  1072. static int ath9k_sta_add(struct ieee80211_hw *hw,
  1073. struct ieee80211_vif *vif,
  1074. struct ieee80211_sta *sta)
  1075. {
  1076. struct ath_softc *sc = hw->priv;
  1077. struct ath_common *common = ath9k_hw_common(sc->sc_ah);
  1078. struct ath_node *an = (struct ath_node *) sta->drv_priv;
  1079. struct ieee80211_key_conf ps_key = { };
  1080. ath_node_attach(sc, sta, vif);
  1081. if (vif->type != NL80211_IFTYPE_AP &&
  1082. vif->type != NL80211_IFTYPE_AP_VLAN)
  1083. return 0;
  1084. an->ps_key = ath_key_config(common, vif, sta, &ps_key);
  1085. return 0;
  1086. }
  1087. static void ath9k_del_ps_key(struct ath_softc *sc,
  1088. struct ieee80211_vif *vif,
  1089. struct ieee80211_sta *sta)
  1090. {
  1091. struct ath_common *common = ath9k_hw_common(sc->sc_ah);
  1092. struct ath_node *an = (struct ath_node *) sta->drv_priv;
  1093. struct ieee80211_key_conf ps_key = { .hw_key_idx = an->ps_key };
  1094. if (!an->ps_key)
  1095. return;
  1096. ath_key_delete(common, &ps_key);
  1097. }
  1098. static int ath9k_sta_remove(struct ieee80211_hw *hw,
  1099. struct ieee80211_vif *vif,
  1100. struct ieee80211_sta *sta)
  1101. {
  1102. struct ath_softc *sc = hw->priv;
  1103. ath9k_del_ps_key(sc, vif, sta);
  1104. ath_node_detach(sc, sta);
  1105. return 0;
  1106. }
  1107. static void ath9k_sta_notify(struct ieee80211_hw *hw,
  1108. struct ieee80211_vif *vif,
  1109. enum sta_notify_cmd cmd,
  1110. struct ieee80211_sta *sta)
  1111. {
  1112. struct ath_softc *sc = hw->priv;
  1113. struct ath_node *an = (struct ath_node *) sta->drv_priv;
  1114. if (!sta->ht_cap.ht_supported)
  1115. return;
  1116. switch (cmd) {
  1117. case STA_NOTIFY_SLEEP:
  1118. an->sleeping = true;
  1119. ath_tx_aggr_sleep(sta, sc, an);
  1120. break;
  1121. case STA_NOTIFY_AWAKE:
  1122. an->sleeping = false;
  1123. ath_tx_aggr_wakeup(sc, an);
  1124. break;
  1125. }
  1126. }
  1127. static int ath9k_conf_tx(struct ieee80211_hw *hw,
  1128. struct ieee80211_vif *vif, u16 queue,
  1129. const struct ieee80211_tx_queue_params *params)
  1130. {
  1131. struct ath_softc *sc = hw->priv;
  1132. struct ath_common *common = ath9k_hw_common(sc->sc_ah);
  1133. struct ath_txq *txq;
  1134. struct ath9k_tx_queue_info qi;
  1135. int ret = 0;
  1136. if (queue >= IEEE80211_NUM_ACS)
  1137. return 0;
  1138. txq = sc->tx.txq_map[queue];
  1139. ath9k_ps_wakeup(sc);
  1140. mutex_lock(&sc->mutex);
  1141. memset(&qi, 0, sizeof(struct ath9k_tx_queue_info));
  1142. qi.tqi_aifs = params->aifs;
  1143. qi.tqi_cwmin = params->cw_min;
  1144. qi.tqi_cwmax = params->cw_max;
  1145. qi.tqi_burstTime = params->txop * 32;
  1146. ath_dbg(common, CONFIG,
  1147. "Configure tx [queue/halq] [%d/%d], aifs: %d, cw_min: %d, cw_max: %d, txop: %d\n",
  1148. queue, txq->axq_qnum, params->aifs, params->cw_min,
  1149. params->cw_max, params->txop);
  1150. ath_update_max_aggr_framelen(sc, queue, qi.tqi_burstTime);
  1151. ret = ath_txq_update(sc, txq->axq_qnum, &qi);
  1152. if (ret)
  1153. ath_err(common, "TXQ Update failed\n");
  1154. mutex_unlock(&sc->mutex);
  1155. ath9k_ps_restore(sc);
  1156. return ret;
  1157. }
  1158. static int ath9k_set_key(struct ieee80211_hw *hw,
  1159. enum set_key_cmd cmd,
  1160. struct ieee80211_vif *vif,
  1161. struct ieee80211_sta *sta,
  1162. struct ieee80211_key_conf *key)
  1163. {
  1164. struct ath_softc *sc = hw->priv;
  1165. struct ath_common *common = ath9k_hw_common(sc->sc_ah);
  1166. int ret = 0;
  1167. if (ath9k_modparam_nohwcrypt)
  1168. return -ENOSPC;
  1169. if ((vif->type == NL80211_IFTYPE_ADHOC ||
  1170. vif->type == NL80211_IFTYPE_MESH_POINT) &&
  1171. (key->cipher == WLAN_CIPHER_SUITE_TKIP ||
  1172. key->cipher == WLAN_CIPHER_SUITE_CCMP) &&
  1173. !(key->flags & IEEE80211_KEY_FLAG_PAIRWISE)) {
  1174. /*
  1175. * For now, disable hw crypto for the RSN IBSS group keys. This
  1176. * could be optimized in the future to use a modified key cache
  1177. * design to support per-STA RX GTK, but until that gets
  1178. * implemented, use of software crypto for group addressed
  1179. * frames is a acceptable to allow RSN IBSS to be used.
  1180. */
  1181. return -EOPNOTSUPP;
  1182. }
  1183. mutex_lock(&sc->mutex);
  1184. ath9k_ps_wakeup(sc);
  1185. ath_dbg(common, CONFIG, "Set HW Key\n");
  1186. switch (cmd) {
  1187. case SET_KEY:
  1188. if (sta)
  1189. ath9k_del_ps_key(sc, vif, sta);
  1190. ret = ath_key_config(common, vif, sta, key);
  1191. if (ret >= 0) {
  1192. key->hw_key_idx = ret;
  1193. /* push IV and Michael MIC generation to stack */
  1194. key->flags |= IEEE80211_KEY_FLAG_GENERATE_IV;
  1195. if (key->cipher == WLAN_CIPHER_SUITE_TKIP)
  1196. key->flags |= IEEE80211_KEY_FLAG_GENERATE_MMIC;
  1197. if (sc->sc_ah->sw_mgmt_crypto &&
  1198. key->cipher == WLAN_CIPHER_SUITE_CCMP)
  1199. key->flags |= IEEE80211_KEY_FLAG_SW_MGMT_TX;
  1200. ret = 0;
  1201. }
  1202. break;
  1203. case DISABLE_KEY:
  1204. ath_key_delete(common, key);
  1205. break;
  1206. default:
  1207. ret = -EINVAL;
  1208. }
  1209. ath9k_ps_restore(sc);
  1210. mutex_unlock(&sc->mutex);
  1211. return ret;
  1212. }
  1213. static void ath9k_set_assoc_state(struct ath_softc *sc,
  1214. struct ieee80211_vif *vif)
  1215. {
  1216. struct ath_common *common = ath9k_hw_common(sc->sc_ah);
  1217. struct ath_vif *avp = (void *)vif->drv_priv;
  1218. struct ieee80211_bss_conf *bss_conf = &vif->bss_conf;
  1219. unsigned long flags;
  1220. set_bit(SC_OP_PRIM_STA_VIF, &sc->sc_flags);
  1221. avp->primary_sta_vif = true;
  1222. /*
  1223. * Set the AID, BSSID and do beacon-sync only when
  1224. * the HW opmode is STATION.
  1225. *
  1226. * But the primary bit is set above in any case.
  1227. */
  1228. if (sc->sc_ah->opmode != NL80211_IFTYPE_STATION)
  1229. return;
  1230. memcpy(common->curbssid, bss_conf->bssid, ETH_ALEN);
  1231. common->curaid = bss_conf->aid;
  1232. ath9k_hw_write_associd(sc->sc_ah);
  1233. sc->last_rssi = ATH_RSSI_DUMMY_MARKER;
  1234. sc->sc_ah->stats.avgbrssi = ATH_RSSI_DUMMY_MARKER;
  1235. spin_lock_irqsave(&sc->sc_pm_lock, flags);
  1236. sc->ps_flags |= PS_BEACON_SYNC | PS_WAIT_FOR_BEACON;
  1237. spin_unlock_irqrestore(&sc->sc_pm_lock, flags);
  1238. if (ath9k_hw_mci_is_enabled(sc->sc_ah))
  1239. ath9k_mci_update_wlan_channels(sc, false);
  1240. ath_dbg(common, CONFIG,
  1241. "Primary Station interface: %pM, BSSID: %pM\n",
  1242. vif->addr, common->curbssid);
  1243. }
  1244. static void ath9k_bss_assoc_iter(void *data, u8 *mac, struct ieee80211_vif *vif)
  1245. {
  1246. struct ath_softc *sc = data;
  1247. struct ieee80211_bss_conf *bss_conf = &vif->bss_conf;
  1248. if (test_bit(SC_OP_PRIM_STA_VIF, &sc->sc_flags))
  1249. return;
  1250. if (bss_conf->assoc)
  1251. ath9k_set_assoc_state(sc, vif);
  1252. }
  1253. static void ath9k_bss_info_changed(struct ieee80211_hw *hw,
  1254. struct ieee80211_vif *vif,
  1255. struct ieee80211_bss_conf *bss_conf,
  1256. u32 changed)
  1257. {
  1258. #define CHECK_ANI \
  1259. (BSS_CHANGED_ASSOC | \
  1260. BSS_CHANGED_IBSS | \
  1261. BSS_CHANGED_BEACON_ENABLED)
  1262. struct ath_softc *sc = hw->priv;
  1263. struct ath_hw *ah = sc->sc_ah;
  1264. struct ath_common *common = ath9k_hw_common(ah);
  1265. struct ath_vif *avp = (void *)vif->drv_priv;
  1266. int slottime;
  1267. ath9k_ps_wakeup(sc);
  1268. mutex_lock(&sc->mutex);
  1269. if (changed & BSS_CHANGED_ASSOC) {
  1270. ath_dbg(common, CONFIG, "BSSID %pM Changed ASSOC %d\n",
  1271. bss_conf->bssid, bss_conf->assoc);
  1272. if (avp->primary_sta_vif && !bss_conf->assoc) {
  1273. clear_bit(SC_OP_PRIM_STA_VIF, &sc->sc_flags);
  1274. avp->primary_sta_vif = false;
  1275. if (ah->opmode == NL80211_IFTYPE_STATION)
  1276. clear_bit(SC_OP_BEACONS, &sc->sc_flags);
  1277. }
  1278. ieee80211_iterate_active_interfaces_atomic(
  1279. sc->hw, IEEE80211_IFACE_ITER_RESUME_ALL,
  1280. ath9k_bss_assoc_iter, sc);
  1281. if (!test_bit(SC_OP_PRIM_STA_VIF, &sc->sc_flags) &&
  1282. ah->opmode == NL80211_IFTYPE_STATION) {
  1283. memset(common->curbssid, 0, ETH_ALEN);
  1284. common->curaid = 0;
  1285. ath9k_hw_write_associd(sc->sc_ah);
  1286. if (ath9k_hw_mci_is_enabled(sc->sc_ah))
  1287. ath9k_mci_update_wlan_channels(sc, true);
  1288. }
  1289. }
  1290. if (changed & BSS_CHANGED_IBSS) {
  1291. memcpy(common->curbssid, bss_conf->bssid, ETH_ALEN);
  1292. common->curaid = bss_conf->aid;
  1293. ath9k_hw_write_associd(sc->sc_ah);
  1294. }
  1295. if ((changed & BSS_CHANGED_BEACON_ENABLED) ||
  1296. (changed & BSS_CHANGED_BEACON_INT)) {
  1297. if (ah->opmode == NL80211_IFTYPE_AP &&
  1298. bss_conf->enable_beacon)
  1299. ath9k_set_tsfadjust(sc, vif);
  1300. if (ath9k_allow_beacon_config(sc, vif))
  1301. ath9k_beacon_config(sc, vif, changed);
  1302. }
  1303. if (changed & BSS_CHANGED_ERP_SLOT) {
  1304. if (bss_conf->use_short_slot)
  1305. slottime = 9;
  1306. else
  1307. slottime = 20;
  1308. if (vif->type == NL80211_IFTYPE_AP) {
  1309. /*
  1310. * Defer update, so that connected stations can adjust
  1311. * their settings at the same time.
  1312. * See beacon.c for more details
  1313. */
  1314. sc->beacon.slottime = slottime;
  1315. sc->beacon.updateslot = UPDATE;
  1316. } else {
  1317. ah->slottime = slottime;
  1318. ath9k_hw_init_global_settings(ah);
  1319. }
  1320. }
  1321. if (changed & CHECK_ANI)
  1322. ath_check_ani(sc);
  1323. mutex_unlock(&sc->mutex);
  1324. ath9k_ps_restore(sc);
  1325. #undef CHECK_ANI
  1326. }
  1327. static u64 ath9k_get_tsf(struct ieee80211_hw *hw, struct ieee80211_vif *vif)
  1328. {
  1329. struct ath_softc *sc = hw->priv;
  1330. u64 tsf;
  1331. mutex_lock(&sc->mutex);
  1332. ath9k_ps_wakeup(sc);
  1333. tsf = ath9k_hw_gettsf64(sc->sc_ah);
  1334. ath9k_ps_restore(sc);
  1335. mutex_unlock(&sc->mutex);
  1336. return tsf;
  1337. }
  1338. static void ath9k_set_tsf(struct ieee80211_hw *hw,
  1339. struct ieee80211_vif *vif,
  1340. u64 tsf)
  1341. {
  1342. struct ath_softc *sc = hw->priv;
  1343. mutex_lock(&sc->mutex);
  1344. ath9k_ps_wakeup(sc);
  1345. ath9k_hw_settsf64(sc->sc_ah, tsf);
  1346. ath9k_ps_restore(sc);
  1347. mutex_unlock(&sc->mutex);
  1348. }
  1349. static void ath9k_reset_tsf(struct ieee80211_hw *hw, struct ieee80211_vif *vif)
  1350. {
  1351. struct ath_softc *sc = hw->priv;
  1352. mutex_lock(&sc->mutex);
  1353. ath9k_ps_wakeup(sc);
  1354. ath9k_hw_reset_tsf(sc->sc_ah);
  1355. ath9k_ps_restore(sc);
  1356. mutex_unlock(&sc->mutex);
  1357. }
  1358. static int ath9k_ampdu_action(struct ieee80211_hw *hw,
  1359. struct ieee80211_vif *vif,
  1360. enum ieee80211_ampdu_mlme_action action,
  1361. struct ieee80211_sta *sta,
  1362. u16 tid, u16 *ssn, u8 buf_size)
  1363. {
  1364. struct ath_softc *sc = hw->priv;
  1365. int ret = 0;
  1366. local_bh_disable();
  1367. switch (action) {
  1368. case IEEE80211_AMPDU_RX_START:
  1369. break;
  1370. case IEEE80211_AMPDU_RX_STOP:
  1371. break;
  1372. case IEEE80211_AMPDU_TX_START:
  1373. ath9k_ps_wakeup(sc);
  1374. ret = ath_tx_aggr_start(sc, sta, tid, ssn);
  1375. if (!ret)
  1376. ieee80211_start_tx_ba_cb_irqsafe(vif, sta->addr, tid);
  1377. ath9k_ps_restore(sc);
  1378. break;
  1379. case IEEE80211_AMPDU_TX_STOP_CONT:
  1380. case IEEE80211_AMPDU_TX_STOP_FLUSH:
  1381. case IEEE80211_AMPDU_TX_STOP_FLUSH_CONT:
  1382. ath9k_ps_wakeup(sc);
  1383. ath_tx_aggr_stop(sc, sta, tid);
  1384. ieee80211_stop_tx_ba_cb_irqsafe(vif, sta->addr, tid);
  1385. ath9k_ps_restore(sc);
  1386. break;
  1387. case IEEE80211_AMPDU_TX_OPERATIONAL:
  1388. ath9k_ps_wakeup(sc);
  1389. ath_tx_aggr_resume(sc, sta, tid);
  1390. ath9k_ps_restore(sc);
  1391. break;
  1392. default:
  1393. ath_err(ath9k_hw_common(sc->sc_ah), "Unknown AMPDU action\n");
  1394. }
  1395. local_bh_enable();
  1396. return ret;
  1397. }
  1398. static int ath9k_get_survey(struct ieee80211_hw *hw, int idx,
  1399. struct survey_info *survey)
  1400. {
  1401. struct ath_softc *sc = hw->priv;
  1402. struct ath_common *common = ath9k_hw_common(sc->sc_ah);
  1403. struct ieee80211_supported_band *sband;
  1404. struct ieee80211_channel *chan;
  1405. unsigned long flags;
  1406. int pos;
  1407. spin_lock_irqsave(&common->cc_lock, flags);
  1408. if (idx == 0)
  1409. ath_update_survey_stats(sc);
  1410. sband = hw->wiphy->bands[IEEE80211_BAND_2GHZ];
  1411. if (sband && idx >= sband->n_channels) {
  1412. idx -= sband->n_channels;
  1413. sband = NULL;
  1414. }
  1415. if (!sband)
  1416. sband = hw->wiphy->bands[IEEE80211_BAND_5GHZ];
  1417. if (!sband || idx >= sband->n_channels) {
  1418. spin_unlock_irqrestore(&common->cc_lock, flags);
  1419. return -ENOENT;
  1420. }
  1421. chan = &sband->channels[idx];
  1422. pos = chan->hw_value;
  1423. memcpy(survey, &sc->survey[pos], sizeof(*survey));
  1424. survey->channel = chan;
  1425. spin_unlock_irqrestore(&common->cc_lock, flags);
  1426. return 0;
  1427. }
  1428. static void ath9k_set_coverage_class(struct ieee80211_hw *hw, u8 coverage_class)
  1429. {
  1430. struct ath_softc *sc = hw->priv;
  1431. struct ath_hw *ah = sc->sc_ah;
  1432. mutex_lock(&sc->mutex);
  1433. ah->coverage_class = coverage_class;
  1434. ath9k_ps_wakeup(sc);
  1435. ath9k_hw_init_global_settings(ah);
  1436. ath9k_ps_restore(sc);
  1437. mutex_unlock(&sc->mutex);
  1438. }
  1439. static void ath9k_flush(struct ieee80211_hw *hw, u32 queues, bool drop)
  1440. {
  1441. struct ath_softc *sc = hw->priv;
  1442. struct ath_hw *ah = sc->sc_ah;
  1443. struct ath_common *common = ath9k_hw_common(ah);
  1444. int timeout = 200; /* ms */
  1445. int i, j;
  1446. bool drain_txq;
  1447. mutex_lock(&sc->mutex);
  1448. cancel_delayed_work_sync(&sc->tx_complete_work);
  1449. if (ah->ah_flags & AH_UNPLUGGED) {
  1450. ath_dbg(common, ANY, "Device has been unplugged!\n");
  1451. mutex_unlock(&sc->mutex);
  1452. return;
  1453. }
  1454. if (test_bit(SC_OP_INVALID, &sc->sc_flags)) {
  1455. ath_dbg(common, ANY, "Device not present\n");
  1456. mutex_unlock(&sc->mutex);
  1457. return;
  1458. }
  1459. for (j = 0; j < timeout; j++) {
  1460. bool npend = false;
  1461. if (j)
  1462. usleep_range(1000, 2000);
  1463. for (i = 0; i < ATH9K_NUM_TX_QUEUES; i++) {
  1464. if (!ATH_TXQ_SETUP(sc, i))
  1465. continue;
  1466. npend = ath9k_has_pending_frames(sc, &sc->tx.txq[i]);
  1467. if (npend)
  1468. break;
  1469. }
  1470. if (!npend)
  1471. break;
  1472. }
  1473. if (drop) {
  1474. ath9k_ps_wakeup(sc);
  1475. spin_lock_bh(&sc->sc_pcu_lock);
  1476. drain_txq = ath_drain_all_txq(sc);
  1477. spin_unlock_bh(&sc->sc_pcu_lock);
  1478. if (!drain_txq)
  1479. ath_reset(sc);
  1480. ath9k_ps_restore(sc);
  1481. ieee80211_wake_queues(hw);
  1482. }
  1483. ieee80211_queue_delayed_work(hw, &sc->tx_complete_work, 0);
  1484. mutex_unlock(&sc->mutex);
  1485. }
  1486. static bool ath9k_tx_frames_pending(struct ieee80211_hw *hw)
  1487. {
  1488. struct ath_softc *sc = hw->priv;
  1489. int i;
  1490. for (i = 0; i < ATH9K_NUM_TX_QUEUES; i++) {
  1491. if (!ATH_TXQ_SETUP(sc, i))
  1492. continue;
  1493. if (ath9k_has_pending_frames(sc, &sc->tx.txq[i]))
  1494. return true;
  1495. }
  1496. return false;
  1497. }
  1498. static int ath9k_tx_last_beacon(struct ieee80211_hw *hw)
  1499. {
  1500. struct ath_softc *sc = hw->priv;
  1501. struct ath_hw *ah = sc->sc_ah;
  1502. struct ieee80211_vif *vif;
  1503. struct ath_vif *avp;
  1504. struct ath_buf *bf;
  1505. struct ath_tx_status ts;
  1506. bool edma = !!(ah->caps.hw_caps & ATH9K_HW_CAP_EDMA);
  1507. int status;
  1508. vif = sc->beacon.bslot[0];
  1509. if (!vif)
  1510. return 0;
  1511. if (!vif->bss_conf.enable_beacon)
  1512. return 0;
  1513. avp = (void *)vif->drv_priv;
  1514. if (!sc->beacon.tx_processed && !edma) {
  1515. tasklet_disable(&sc->bcon_tasklet);
  1516. bf = avp->av_bcbuf;
  1517. if (!bf || !bf->bf_mpdu)
  1518. goto skip;
  1519. status = ath9k_hw_txprocdesc(ah, bf->bf_desc, &ts);
  1520. if (status == -EINPROGRESS)
  1521. goto skip;
  1522. sc->beacon.tx_processed = true;
  1523. sc->beacon.tx_last = !(ts.ts_status & ATH9K_TXERR_MASK);
  1524. skip:
  1525. tasklet_enable(&sc->bcon_tasklet);
  1526. }
  1527. return sc->beacon.tx_last;
  1528. }
  1529. static int ath9k_get_stats(struct ieee80211_hw *hw,
  1530. struct ieee80211_low_level_stats *stats)
  1531. {
  1532. struct ath_softc *sc = hw->priv;
  1533. struct ath_hw *ah = sc->sc_ah;
  1534. struct ath9k_mib_stats *mib_stats = &ah->ah_mibStats;
  1535. stats->dot11ACKFailureCount = mib_stats->ackrcv_bad;
  1536. stats->dot11RTSFailureCount = mib_stats->rts_bad;
  1537. stats->dot11FCSErrorCount = mib_stats->fcs_bad;
  1538. stats->dot11RTSSuccessCount = mib_stats->rts_good;
  1539. return 0;
  1540. }
  1541. static u32 fill_chainmask(u32 cap, u32 new)
  1542. {
  1543. u32 filled = 0;
  1544. int i;
  1545. for (i = 0; cap && new; i++, cap >>= 1) {
  1546. if (!(cap & BIT(0)))
  1547. continue;
  1548. if (new & BIT(0))
  1549. filled |= BIT(i);
  1550. new >>= 1;
  1551. }
  1552. return filled;
  1553. }
  1554. static bool validate_antenna_mask(struct ath_hw *ah, u32 val)
  1555. {
  1556. if (AR_SREV_9300_20_OR_LATER(ah))
  1557. return true;
  1558. switch (val & 0x7) {
  1559. case 0x1:
  1560. case 0x3:
  1561. case 0x7:
  1562. return true;
  1563. case 0x2:
  1564. return (ah->caps.rx_chainmask == 1);
  1565. default:
  1566. return false;
  1567. }
  1568. }
  1569. static int ath9k_set_antenna(struct ieee80211_hw *hw, u32 tx_ant, u32 rx_ant)
  1570. {
  1571. struct ath_softc *sc = hw->priv;
  1572. struct ath_hw *ah = sc->sc_ah;
  1573. if (ah->caps.rx_chainmask != 1)
  1574. rx_ant |= tx_ant;
  1575. if (!validate_antenna_mask(ah, rx_ant) || !tx_ant)
  1576. return -EINVAL;
  1577. sc->ant_rx = rx_ant;
  1578. sc->ant_tx = tx_ant;
  1579. if (ah->caps.rx_chainmask == 1)
  1580. return 0;
  1581. /* AR9100 runs into calibration issues if not all rx chains are enabled */
  1582. if (AR_SREV_9100(ah))
  1583. ah->rxchainmask = 0x7;
  1584. else
  1585. ah->rxchainmask = fill_chainmask(ah->caps.rx_chainmask, rx_ant);
  1586. ah->txchainmask = fill_chainmask(ah->caps.tx_chainmask, tx_ant);
  1587. ath9k_reload_chainmask_settings(sc);
  1588. return 0;
  1589. }
  1590. static int ath9k_get_antenna(struct ieee80211_hw *hw, u32 *tx_ant, u32 *rx_ant)
  1591. {
  1592. struct ath_softc *sc = hw->priv;
  1593. *tx_ant = sc->ant_tx;
  1594. *rx_ant = sc->ant_rx;
  1595. return 0;
  1596. }
  1597. #ifdef CONFIG_PM_SLEEP
  1598. static void ath9k_wow_map_triggers(struct ath_softc *sc,
  1599. struct cfg80211_wowlan *wowlan,
  1600. u32 *wow_triggers)
  1601. {
  1602. if (wowlan->disconnect)
  1603. *wow_triggers |= AH_WOW_LINK_CHANGE |
  1604. AH_WOW_BEACON_MISS;
  1605. if (wowlan->magic_pkt)
  1606. *wow_triggers |= AH_WOW_MAGIC_PATTERN_EN;
  1607. if (wowlan->n_patterns)
  1608. *wow_triggers |= AH_WOW_USER_PATTERN_EN;
  1609. sc->wow_enabled = *wow_triggers;
  1610. }
  1611. static void ath9k_wow_add_disassoc_deauth_pattern(struct ath_softc *sc)
  1612. {
  1613. struct ath_hw *ah = sc->sc_ah;
  1614. struct ath_common *common = ath9k_hw_common(ah);
  1615. struct ath9k_hw_capabilities *pcaps = &ah->caps;
  1616. int pattern_count = 0;
  1617. int i, byte_cnt;
  1618. u8 dis_deauth_pattern[MAX_PATTERN_SIZE];
  1619. u8 dis_deauth_mask[MAX_PATTERN_SIZE];
  1620. memset(dis_deauth_pattern, 0, MAX_PATTERN_SIZE);
  1621. memset(dis_deauth_mask, 0, MAX_PATTERN_SIZE);
  1622. /*
  1623. * Create Dissassociate / Deauthenticate packet filter
  1624. *
  1625. * 2 bytes 2 byte 6 bytes 6 bytes 6 bytes
  1626. * +--------------+----------+---------+--------+--------+----
  1627. * + Frame Control+ Duration + DA + SA + BSSID +
  1628. * +--------------+----------+---------+--------+--------+----
  1629. *
  1630. * The above is the management frame format for disassociate/
  1631. * deauthenticate pattern, from this we need to match the first byte
  1632. * of 'Frame Control' and DA, SA, and BSSID fields
  1633. * (skipping 2nd byte of FC and Duration feild.
  1634. *
  1635. * Disassociate pattern
  1636. * --------------------
  1637. * Frame control = 00 00 1010
  1638. * DA, SA, BSSID = x:x:x:x:x:x
  1639. * Pattern will be A0000000 | x:x:x:x:x:x | x:x:x:x:x:x
  1640. * | x:x:x:x:x:x -- 22 bytes
  1641. *
  1642. * Deauthenticate pattern
  1643. * ----------------------
  1644. * Frame control = 00 00 1100
  1645. * DA, SA, BSSID = x:x:x:x:x:x
  1646. * Pattern will be C0000000 | x:x:x:x:x:x | x:x:x:x:x:x
  1647. * | x:x:x:x:x:x -- 22 bytes
  1648. */
  1649. /* Create Disassociate Pattern first */
  1650. byte_cnt = 0;
  1651. /* Fill out the mask with all FF's */
  1652. for (i = 0; i < MAX_PATTERN_MASK_SIZE; i++)
  1653. dis_deauth_mask[i] = 0xff;
  1654. /* copy the first byte of frame control field */
  1655. dis_deauth_pattern[byte_cnt] = 0xa0;
  1656. byte_cnt++;
  1657. /* skip 2nd byte of frame control and Duration field */
  1658. byte_cnt += 3;
  1659. /*
  1660. * need not match the destination mac address, it can be a broadcast
  1661. * mac address or an unicast to this station
  1662. */
  1663. byte_cnt += 6;
  1664. /* copy the source mac address */
  1665. memcpy((dis_deauth_pattern + byte_cnt), common->curbssid, ETH_ALEN);
  1666. byte_cnt += 6;
  1667. /* copy the bssid, its same as the source mac address */
  1668. memcpy((dis_deauth_pattern + byte_cnt), common->curbssid, ETH_ALEN);
  1669. /* Create Disassociate pattern mask */
  1670. if (pcaps->hw_caps & ATH9K_HW_WOW_PATTERN_MATCH_EXACT) {
  1671. if (pcaps->hw_caps & ATH9K_HW_WOW_PATTERN_MATCH_DWORD) {
  1672. /*
  1673. * for AR9280, because of hardware limitation, the
  1674. * first 4 bytes have to be matched for all patterns.
  1675. * the mask for disassociation and de-auth pattern
  1676. * matching need to enable the first 4 bytes.
  1677. * also the duration field needs to be filled.
  1678. */
  1679. dis_deauth_mask[0] = 0xf0;
  1680. /*
  1681. * fill in duration field
  1682. FIXME: what is the exact value ?
  1683. */
  1684. dis_deauth_pattern[2] = 0xff;
  1685. dis_deauth_pattern[3] = 0xff;
  1686. } else {
  1687. dis_deauth_mask[0] = 0xfe;
  1688. }
  1689. dis_deauth_mask[1] = 0x03;
  1690. dis_deauth_mask[2] = 0xc0;
  1691. } else {
  1692. dis_deauth_mask[0] = 0xef;
  1693. dis_deauth_mask[1] = 0x3f;
  1694. dis_deauth_mask[2] = 0x00;
  1695. dis_deauth_mask[3] = 0xfc;
  1696. }
  1697. ath_dbg(common, WOW, "Adding disassoc/deauth patterns for WoW\n");
  1698. ath9k_hw_wow_apply_pattern(ah, dis_deauth_pattern, dis_deauth_mask,
  1699. pattern_count, byte_cnt);
  1700. pattern_count++;
  1701. /*
  1702. * for de-authenticate pattern, only the first byte of the frame
  1703. * control field gets changed from 0xA0 to 0xC0
  1704. */
  1705. dis_deauth_pattern[0] = 0xC0;
  1706. ath9k_hw_wow_apply_pattern(ah, dis_deauth_pattern, dis_deauth_mask,
  1707. pattern_count, byte_cnt);
  1708. }
  1709. static void ath9k_wow_add_pattern(struct ath_softc *sc,
  1710. struct cfg80211_wowlan *wowlan)
  1711. {
  1712. struct ath_hw *ah = sc->sc_ah;
  1713. struct ath9k_wow_pattern *wow_pattern = NULL;
  1714. struct cfg80211_wowlan_trig_pkt_pattern *patterns = wowlan->patterns;
  1715. int mask_len;
  1716. s8 i = 0;
  1717. if (!wowlan->n_patterns)
  1718. return;
  1719. /*
  1720. * Add the new user configured patterns
  1721. */
  1722. for (i = 0; i < wowlan->n_patterns; i++) {
  1723. wow_pattern = kzalloc(sizeof(*wow_pattern), GFP_KERNEL);
  1724. if (!wow_pattern)
  1725. return;
  1726. /*
  1727. * TODO: convert the generic user space pattern to
  1728. * appropriate chip specific/802.11 pattern.
  1729. */
  1730. mask_len = DIV_ROUND_UP(wowlan->patterns[i].pattern_len, 8);
  1731. memset(wow_pattern->pattern_bytes, 0, MAX_PATTERN_SIZE);
  1732. memset(wow_pattern->mask_bytes, 0, MAX_PATTERN_SIZE);
  1733. memcpy(wow_pattern->pattern_bytes, patterns[i].pattern,
  1734. patterns[i].pattern_len);
  1735. memcpy(wow_pattern->mask_bytes, patterns[i].mask, mask_len);
  1736. wow_pattern->pattern_len = patterns[i].pattern_len;
  1737. /*
  1738. * just need to take care of deauth and disssoc pattern,
  1739. * make sure we don't overwrite them.
  1740. */
  1741. ath9k_hw_wow_apply_pattern(ah, wow_pattern->pattern_bytes,
  1742. wow_pattern->mask_bytes,
  1743. i + 2,
  1744. wow_pattern->pattern_len);
  1745. kfree(wow_pattern);
  1746. }
  1747. }
  1748. static int ath9k_suspend(struct ieee80211_hw *hw,
  1749. struct cfg80211_wowlan *wowlan)
  1750. {
  1751. struct ath_softc *sc = hw->priv;
  1752. struct ath_hw *ah = sc->sc_ah;
  1753. struct ath_common *common = ath9k_hw_common(ah);
  1754. u32 wow_triggers_enabled = 0;
  1755. int ret = 0;
  1756. mutex_lock(&sc->mutex);
  1757. ath_cancel_work(sc);
  1758. ath_stop_ani(sc);
  1759. del_timer_sync(&sc->rx_poll_timer);
  1760. if (test_bit(SC_OP_INVALID, &sc->sc_flags)) {
  1761. ath_dbg(common, ANY, "Device not present\n");
  1762. ret = -EINVAL;
  1763. goto fail_wow;
  1764. }
  1765. if (WARN_ON(!wowlan)) {
  1766. ath_dbg(common, WOW, "None of the WoW triggers enabled\n");
  1767. ret = -EINVAL;
  1768. goto fail_wow;
  1769. }
  1770. if (!device_can_wakeup(sc->dev)) {
  1771. ath_dbg(common, WOW, "device_can_wakeup failed, WoW is not enabled\n");
  1772. ret = 1;
  1773. goto fail_wow;
  1774. }
  1775. /*
  1776. * none of the sta vifs are associated
  1777. * and we are not currently handling multivif
  1778. * cases, for instance we have to seperately
  1779. * configure 'keep alive frame' for each
  1780. * STA.
  1781. */
  1782. if (!test_bit(SC_OP_PRIM_STA_VIF, &sc->sc_flags)) {
  1783. ath_dbg(common, WOW, "None of the STA vifs are associated\n");
  1784. ret = 1;
  1785. goto fail_wow;
  1786. }
  1787. if (sc->nvifs > 1) {
  1788. ath_dbg(common, WOW, "WoW for multivif is not yet supported\n");
  1789. ret = 1;
  1790. goto fail_wow;
  1791. }
  1792. ath9k_wow_map_triggers(sc, wowlan, &wow_triggers_enabled);
  1793. ath_dbg(common, WOW, "WoW triggers enabled 0x%x\n",
  1794. wow_triggers_enabled);
  1795. ath9k_ps_wakeup(sc);
  1796. ath9k_stop_btcoex(sc);
  1797. /*
  1798. * Enable wake up on recieving disassoc/deauth
  1799. * frame by default.
  1800. */
  1801. ath9k_wow_add_disassoc_deauth_pattern(sc);
  1802. if (wow_triggers_enabled & AH_WOW_USER_PATTERN_EN)
  1803. ath9k_wow_add_pattern(sc, wowlan);
  1804. spin_lock_bh(&sc->sc_pcu_lock);
  1805. /*
  1806. * To avoid false wake, we enable beacon miss interrupt only
  1807. * when we go to sleep. We save the current interrupt mask
  1808. * so we can restore it after the system wakes up
  1809. */
  1810. sc->wow_intr_before_sleep = ah->imask;
  1811. ah->imask &= ~ATH9K_INT_GLOBAL;
  1812. ath9k_hw_disable_interrupts(ah);
  1813. ah->imask = ATH9K_INT_BMISS | ATH9K_INT_GLOBAL;
  1814. ath9k_hw_set_interrupts(ah);
  1815. ath9k_hw_enable_interrupts(ah);
  1816. spin_unlock_bh(&sc->sc_pcu_lock);
  1817. /*
  1818. * we can now sync irq and kill any running tasklets, since we already
  1819. * disabled interrupts and not holding a spin lock
  1820. */
  1821. synchronize_irq(sc->irq);
  1822. tasklet_kill(&sc->intr_tq);
  1823. ath9k_hw_wow_enable(ah, wow_triggers_enabled);
  1824. ath9k_ps_restore(sc);
  1825. ath_dbg(common, ANY, "WoW enabled in ath9k\n");
  1826. atomic_inc(&sc->wow_sleep_proc_intr);
  1827. fail_wow:
  1828. mutex_unlock(&sc->mutex);
  1829. return ret;
  1830. }
  1831. static int ath9k_resume(struct ieee80211_hw *hw)
  1832. {
  1833. struct ath_softc *sc = hw->priv;
  1834. struct ath_hw *ah = sc->sc_ah;
  1835. struct ath_common *common = ath9k_hw_common(ah);
  1836. u32 wow_status;
  1837. mutex_lock(&sc->mutex);
  1838. ath9k_ps_wakeup(sc);
  1839. spin_lock_bh(&sc->sc_pcu_lock);
  1840. ath9k_hw_disable_interrupts(ah);
  1841. ah->imask = sc->wow_intr_before_sleep;
  1842. ath9k_hw_set_interrupts(ah);
  1843. ath9k_hw_enable_interrupts(ah);
  1844. spin_unlock_bh(&sc->sc_pcu_lock);
  1845. wow_status = ath9k_hw_wow_wakeup(ah);
  1846. if (atomic_read(&sc->wow_got_bmiss_intr) == 0) {
  1847. /*
  1848. * some devices may not pick beacon miss
  1849. * as the reason they woke up so we add
  1850. * that here for that shortcoming.
  1851. */
  1852. wow_status |= AH_WOW_BEACON_MISS;
  1853. atomic_dec(&sc->wow_got_bmiss_intr);
  1854. ath_dbg(common, ANY, "Beacon miss interrupt picked up during WoW sleep\n");
  1855. }
  1856. atomic_dec(&sc->wow_sleep_proc_intr);
  1857. if (wow_status) {
  1858. ath_dbg(common, ANY, "Waking up due to WoW triggers %s with WoW status = %x\n",
  1859. ath9k_hw_wow_event_to_string(wow_status), wow_status);
  1860. }
  1861. ath_restart_work(sc);
  1862. ath9k_start_btcoex(sc);
  1863. ath9k_ps_restore(sc);
  1864. mutex_unlock(&sc->mutex);
  1865. return 0;
  1866. }
  1867. static void ath9k_set_wakeup(struct ieee80211_hw *hw, bool enabled)
  1868. {
  1869. struct ath_softc *sc = hw->priv;
  1870. mutex_lock(&sc->mutex);
  1871. device_init_wakeup(sc->dev, 1);
  1872. device_set_wakeup_enable(sc->dev, enabled);
  1873. mutex_unlock(&sc->mutex);
  1874. }
  1875. #endif
  1876. static void ath9k_sw_scan_start(struct ieee80211_hw *hw)
  1877. {
  1878. struct ath_softc *sc = hw->priv;
  1879. sc->scanning = 1;
  1880. }
  1881. static void ath9k_sw_scan_complete(struct ieee80211_hw *hw)
  1882. {
  1883. struct ath_softc *sc = hw->priv;
  1884. sc->scanning = 0;
  1885. }
  1886. struct ieee80211_ops ath9k_ops = {
  1887. .tx = ath9k_tx,
  1888. .start = ath9k_start,
  1889. .stop = ath9k_stop,
  1890. .add_interface = ath9k_add_interface,
  1891. .change_interface = ath9k_change_interface,
  1892. .remove_interface = ath9k_remove_interface,
  1893. .config = ath9k_config,
  1894. .configure_filter = ath9k_configure_filter,
  1895. .sta_add = ath9k_sta_add,
  1896. .sta_remove = ath9k_sta_remove,
  1897. .sta_notify = ath9k_sta_notify,
  1898. .conf_tx = ath9k_conf_tx,
  1899. .bss_info_changed = ath9k_bss_info_changed,
  1900. .set_key = ath9k_set_key,
  1901. .get_tsf = ath9k_get_tsf,
  1902. .set_tsf = ath9k_set_tsf,
  1903. .reset_tsf = ath9k_reset_tsf,
  1904. .ampdu_action = ath9k_ampdu_action,
  1905. .get_survey = ath9k_get_survey,
  1906. .rfkill_poll = ath9k_rfkill_poll_state,
  1907. .set_coverage_class = ath9k_set_coverage_class,
  1908. .flush = ath9k_flush,
  1909. .tx_frames_pending = ath9k_tx_frames_pending,
  1910. .tx_last_beacon = ath9k_tx_last_beacon,
  1911. .get_stats = ath9k_get_stats,
  1912. .set_antenna = ath9k_set_antenna,
  1913. .get_antenna = ath9k_get_antenna,
  1914. #ifdef CONFIG_PM_SLEEP
  1915. .suspend = ath9k_suspend,
  1916. .resume = ath9k_resume,
  1917. .set_wakeup = ath9k_set_wakeup,
  1918. #endif
  1919. #ifdef CONFIG_ATH9K_DEBUGFS
  1920. .get_et_sset_count = ath9k_get_et_sset_count,
  1921. .get_et_stats = ath9k_get_et_stats,
  1922. .get_et_strings = ath9k_get_et_strings,
  1923. #endif
  1924. #if defined(CONFIG_MAC80211_DEBUGFS) && defined(CONFIG_ATH9K_DEBUGFS)
  1925. .sta_add_debugfs = ath9k_sta_add_debugfs,
  1926. .sta_remove_debugfs = ath9k_sta_remove_debugfs,
  1927. #endif
  1928. .sw_scan_start = ath9k_sw_scan_start,
  1929. .sw_scan_complete = ath9k_sw_scan_complete,
  1930. };