qlge_main.c 132 KB

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  1. /*
  2. * QLogic qlge NIC HBA Driver
  3. * Copyright (c) 2003-2008 QLogic Corporation
  4. * See LICENSE.qlge for copyright and licensing details.
  5. * Author: Linux qlge network device driver by
  6. * Ron Mercer <ron.mercer@qlogic.com>
  7. */
  8. #include <linux/kernel.h>
  9. #include <linux/init.h>
  10. #include <linux/bitops.h>
  11. #include <linux/types.h>
  12. #include <linux/module.h>
  13. #include <linux/list.h>
  14. #include <linux/pci.h>
  15. #include <linux/dma-mapping.h>
  16. #include <linux/pagemap.h>
  17. #include <linux/sched.h>
  18. #include <linux/slab.h>
  19. #include <linux/dmapool.h>
  20. #include <linux/mempool.h>
  21. #include <linux/spinlock.h>
  22. #include <linux/kthread.h>
  23. #include <linux/interrupt.h>
  24. #include <linux/errno.h>
  25. #include <linux/ioport.h>
  26. #include <linux/in.h>
  27. #include <linux/ip.h>
  28. #include <linux/ipv6.h>
  29. #include <net/ipv6.h>
  30. #include <linux/tcp.h>
  31. #include <linux/udp.h>
  32. #include <linux/if_arp.h>
  33. #include <linux/if_ether.h>
  34. #include <linux/netdevice.h>
  35. #include <linux/etherdevice.h>
  36. #include <linux/ethtool.h>
  37. #include <linux/if_vlan.h>
  38. #include <linux/skbuff.h>
  39. #include <linux/delay.h>
  40. #include <linux/mm.h>
  41. #include <linux/vmalloc.h>
  42. #include <linux/prefetch.h>
  43. #include <net/ip6_checksum.h>
  44. #include "qlge.h"
  45. char qlge_driver_name[] = DRV_NAME;
  46. const char qlge_driver_version[] = DRV_VERSION;
  47. MODULE_AUTHOR("Ron Mercer <ron.mercer@qlogic.com>");
  48. MODULE_DESCRIPTION(DRV_STRING " ");
  49. MODULE_LICENSE("GPL");
  50. MODULE_VERSION(DRV_VERSION);
  51. static const u32 default_msg =
  52. NETIF_MSG_DRV | NETIF_MSG_PROBE | NETIF_MSG_LINK |
  53. /* NETIF_MSG_TIMER | */
  54. NETIF_MSG_IFDOWN |
  55. NETIF_MSG_IFUP |
  56. NETIF_MSG_RX_ERR |
  57. NETIF_MSG_TX_ERR |
  58. /* NETIF_MSG_TX_QUEUED | */
  59. /* NETIF_MSG_INTR | NETIF_MSG_TX_DONE | NETIF_MSG_RX_STATUS | */
  60. /* NETIF_MSG_PKTDATA | */
  61. NETIF_MSG_HW | NETIF_MSG_WOL | 0;
  62. static int debug = -1; /* defaults above */
  63. module_param(debug, int, 0664);
  64. MODULE_PARM_DESC(debug, "Debug level (0=none,...,16=all)");
  65. #define MSIX_IRQ 0
  66. #define MSI_IRQ 1
  67. #define LEG_IRQ 2
  68. static int qlge_irq_type = MSIX_IRQ;
  69. module_param(qlge_irq_type, int, 0664);
  70. MODULE_PARM_DESC(qlge_irq_type, "0 = MSI-X, 1 = MSI, 2 = Legacy.");
  71. static int qlge_mpi_coredump;
  72. module_param(qlge_mpi_coredump, int, 0);
  73. MODULE_PARM_DESC(qlge_mpi_coredump,
  74. "Option to enable MPI firmware dump. "
  75. "Default is OFF - Do Not allocate memory. ");
  76. static int qlge_force_coredump;
  77. module_param(qlge_force_coredump, int, 0);
  78. MODULE_PARM_DESC(qlge_force_coredump,
  79. "Option to allow force of firmware core dump. "
  80. "Default is OFF - Do not allow.");
  81. static DEFINE_PCI_DEVICE_TABLE(qlge_pci_tbl) = {
  82. {PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, QLGE_DEVICE_ID_8012)},
  83. {PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, QLGE_DEVICE_ID_8000)},
  84. /* required last entry */
  85. {0,}
  86. };
  87. MODULE_DEVICE_TABLE(pci, qlge_pci_tbl);
  88. static int ql_wol(struct ql_adapter *qdev);
  89. static void qlge_set_multicast_list(struct net_device *ndev);
  90. /* This hardware semaphore causes exclusive access to
  91. * resources shared between the NIC driver, MPI firmware,
  92. * FCOE firmware and the FC driver.
  93. */
  94. static int ql_sem_trylock(struct ql_adapter *qdev, u32 sem_mask)
  95. {
  96. u32 sem_bits = 0;
  97. switch (sem_mask) {
  98. case SEM_XGMAC0_MASK:
  99. sem_bits = SEM_SET << SEM_XGMAC0_SHIFT;
  100. break;
  101. case SEM_XGMAC1_MASK:
  102. sem_bits = SEM_SET << SEM_XGMAC1_SHIFT;
  103. break;
  104. case SEM_ICB_MASK:
  105. sem_bits = SEM_SET << SEM_ICB_SHIFT;
  106. break;
  107. case SEM_MAC_ADDR_MASK:
  108. sem_bits = SEM_SET << SEM_MAC_ADDR_SHIFT;
  109. break;
  110. case SEM_FLASH_MASK:
  111. sem_bits = SEM_SET << SEM_FLASH_SHIFT;
  112. break;
  113. case SEM_PROBE_MASK:
  114. sem_bits = SEM_SET << SEM_PROBE_SHIFT;
  115. break;
  116. case SEM_RT_IDX_MASK:
  117. sem_bits = SEM_SET << SEM_RT_IDX_SHIFT;
  118. break;
  119. case SEM_PROC_REG_MASK:
  120. sem_bits = SEM_SET << SEM_PROC_REG_SHIFT;
  121. break;
  122. default:
  123. netif_alert(qdev, probe, qdev->ndev, "bad Semaphore mask!.\n");
  124. return -EINVAL;
  125. }
  126. ql_write32(qdev, SEM, sem_bits | sem_mask);
  127. return !(ql_read32(qdev, SEM) & sem_bits);
  128. }
  129. int ql_sem_spinlock(struct ql_adapter *qdev, u32 sem_mask)
  130. {
  131. unsigned int wait_count = 30;
  132. do {
  133. if (!ql_sem_trylock(qdev, sem_mask))
  134. return 0;
  135. udelay(100);
  136. } while (--wait_count);
  137. return -ETIMEDOUT;
  138. }
  139. void ql_sem_unlock(struct ql_adapter *qdev, u32 sem_mask)
  140. {
  141. ql_write32(qdev, SEM, sem_mask);
  142. ql_read32(qdev, SEM); /* flush */
  143. }
  144. /* This function waits for a specific bit to come ready
  145. * in a given register. It is used mostly by the initialize
  146. * process, but is also used in kernel thread API such as
  147. * netdev->set_multi, netdev->set_mac_address, netdev->vlan_rx_add_vid.
  148. */
  149. int ql_wait_reg_rdy(struct ql_adapter *qdev, u32 reg, u32 bit, u32 err_bit)
  150. {
  151. u32 temp;
  152. int count = UDELAY_COUNT;
  153. while (count) {
  154. temp = ql_read32(qdev, reg);
  155. /* check for errors */
  156. if (temp & err_bit) {
  157. netif_alert(qdev, probe, qdev->ndev,
  158. "register 0x%.08x access error, value = 0x%.08x!.\n",
  159. reg, temp);
  160. return -EIO;
  161. } else if (temp & bit)
  162. return 0;
  163. udelay(UDELAY_DELAY);
  164. count--;
  165. }
  166. netif_alert(qdev, probe, qdev->ndev,
  167. "Timed out waiting for reg %x to come ready.\n", reg);
  168. return -ETIMEDOUT;
  169. }
  170. /* The CFG register is used to download TX and RX control blocks
  171. * to the chip. This function waits for an operation to complete.
  172. */
  173. static int ql_wait_cfg(struct ql_adapter *qdev, u32 bit)
  174. {
  175. int count = UDELAY_COUNT;
  176. u32 temp;
  177. while (count) {
  178. temp = ql_read32(qdev, CFG);
  179. if (temp & CFG_LE)
  180. return -EIO;
  181. if (!(temp & bit))
  182. return 0;
  183. udelay(UDELAY_DELAY);
  184. count--;
  185. }
  186. return -ETIMEDOUT;
  187. }
  188. /* Used to issue init control blocks to hw. Maps control block,
  189. * sets address, triggers download, waits for completion.
  190. */
  191. int ql_write_cfg(struct ql_adapter *qdev, void *ptr, int size, u32 bit,
  192. u16 q_id)
  193. {
  194. u64 map;
  195. int status = 0;
  196. int direction;
  197. u32 mask;
  198. u32 value;
  199. direction =
  200. (bit & (CFG_LRQ | CFG_LR | CFG_LCQ)) ? PCI_DMA_TODEVICE :
  201. PCI_DMA_FROMDEVICE;
  202. map = pci_map_single(qdev->pdev, ptr, size, direction);
  203. if (pci_dma_mapping_error(qdev->pdev, map)) {
  204. netif_err(qdev, ifup, qdev->ndev, "Couldn't map DMA area.\n");
  205. return -ENOMEM;
  206. }
  207. status = ql_sem_spinlock(qdev, SEM_ICB_MASK);
  208. if (status)
  209. return status;
  210. status = ql_wait_cfg(qdev, bit);
  211. if (status) {
  212. netif_err(qdev, ifup, qdev->ndev,
  213. "Timed out waiting for CFG to come ready.\n");
  214. goto exit;
  215. }
  216. ql_write32(qdev, ICB_L, (u32) map);
  217. ql_write32(qdev, ICB_H, (u32) (map >> 32));
  218. mask = CFG_Q_MASK | (bit << 16);
  219. value = bit | (q_id << CFG_Q_SHIFT);
  220. ql_write32(qdev, CFG, (mask | value));
  221. /*
  222. * Wait for the bit to clear after signaling hw.
  223. */
  224. status = ql_wait_cfg(qdev, bit);
  225. exit:
  226. ql_sem_unlock(qdev, SEM_ICB_MASK); /* does flush too */
  227. pci_unmap_single(qdev->pdev, map, size, direction);
  228. return status;
  229. }
  230. /* Get a specific MAC address from the CAM. Used for debug and reg dump. */
  231. int ql_get_mac_addr_reg(struct ql_adapter *qdev, u32 type, u16 index,
  232. u32 *value)
  233. {
  234. u32 offset = 0;
  235. int status;
  236. switch (type) {
  237. case MAC_ADDR_TYPE_MULTI_MAC:
  238. case MAC_ADDR_TYPE_CAM_MAC:
  239. {
  240. status =
  241. ql_wait_reg_rdy(qdev,
  242. MAC_ADDR_IDX, MAC_ADDR_MW, 0);
  243. if (status)
  244. goto exit;
  245. ql_write32(qdev, MAC_ADDR_IDX, (offset++) | /* offset */
  246. (index << MAC_ADDR_IDX_SHIFT) | /* index */
  247. MAC_ADDR_ADR | MAC_ADDR_RS | type); /* type */
  248. status =
  249. ql_wait_reg_rdy(qdev,
  250. MAC_ADDR_IDX, MAC_ADDR_MR, 0);
  251. if (status)
  252. goto exit;
  253. *value++ = ql_read32(qdev, MAC_ADDR_DATA);
  254. status =
  255. ql_wait_reg_rdy(qdev,
  256. MAC_ADDR_IDX, MAC_ADDR_MW, 0);
  257. if (status)
  258. goto exit;
  259. ql_write32(qdev, MAC_ADDR_IDX, (offset++) | /* offset */
  260. (index << MAC_ADDR_IDX_SHIFT) | /* index */
  261. MAC_ADDR_ADR | MAC_ADDR_RS | type); /* type */
  262. status =
  263. ql_wait_reg_rdy(qdev,
  264. MAC_ADDR_IDX, MAC_ADDR_MR, 0);
  265. if (status)
  266. goto exit;
  267. *value++ = ql_read32(qdev, MAC_ADDR_DATA);
  268. if (type == MAC_ADDR_TYPE_CAM_MAC) {
  269. status =
  270. ql_wait_reg_rdy(qdev,
  271. MAC_ADDR_IDX, MAC_ADDR_MW, 0);
  272. if (status)
  273. goto exit;
  274. ql_write32(qdev, MAC_ADDR_IDX, (offset++) | /* offset */
  275. (index << MAC_ADDR_IDX_SHIFT) | /* index */
  276. MAC_ADDR_ADR | MAC_ADDR_RS | type); /* type */
  277. status =
  278. ql_wait_reg_rdy(qdev, MAC_ADDR_IDX,
  279. MAC_ADDR_MR, 0);
  280. if (status)
  281. goto exit;
  282. *value++ = ql_read32(qdev, MAC_ADDR_DATA);
  283. }
  284. break;
  285. }
  286. case MAC_ADDR_TYPE_VLAN:
  287. case MAC_ADDR_TYPE_MULTI_FLTR:
  288. default:
  289. netif_crit(qdev, ifup, qdev->ndev,
  290. "Address type %d not yet supported.\n", type);
  291. status = -EPERM;
  292. }
  293. exit:
  294. return status;
  295. }
  296. /* Set up a MAC, multicast or VLAN address for the
  297. * inbound frame matching.
  298. */
  299. static int ql_set_mac_addr_reg(struct ql_adapter *qdev, u8 *addr, u32 type,
  300. u16 index)
  301. {
  302. u32 offset = 0;
  303. int status = 0;
  304. switch (type) {
  305. case MAC_ADDR_TYPE_MULTI_MAC:
  306. {
  307. u32 upper = (addr[0] << 8) | addr[1];
  308. u32 lower = (addr[2] << 24) | (addr[3] << 16) |
  309. (addr[4] << 8) | (addr[5]);
  310. status =
  311. ql_wait_reg_rdy(qdev,
  312. MAC_ADDR_IDX, MAC_ADDR_MW, 0);
  313. if (status)
  314. goto exit;
  315. ql_write32(qdev, MAC_ADDR_IDX, (offset++) |
  316. (index << MAC_ADDR_IDX_SHIFT) |
  317. type | MAC_ADDR_E);
  318. ql_write32(qdev, MAC_ADDR_DATA, lower);
  319. status =
  320. ql_wait_reg_rdy(qdev,
  321. MAC_ADDR_IDX, MAC_ADDR_MW, 0);
  322. if (status)
  323. goto exit;
  324. ql_write32(qdev, MAC_ADDR_IDX, (offset++) |
  325. (index << MAC_ADDR_IDX_SHIFT) |
  326. type | MAC_ADDR_E);
  327. ql_write32(qdev, MAC_ADDR_DATA, upper);
  328. status =
  329. ql_wait_reg_rdy(qdev,
  330. MAC_ADDR_IDX, MAC_ADDR_MW, 0);
  331. if (status)
  332. goto exit;
  333. break;
  334. }
  335. case MAC_ADDR_TYPE_CAM_MAC:
  336. {
  337. u32 cam_output;
  338. u32 upper = (addr[0] << 8) | addr[1];
  339. u32 lower =
  340. (addr[2] << 24) | (addr[3] << 16) | (addr[4] << 8) |
  341. (addr[5]);
  342. status =
  343. ql_wait_reg_rdy(qdev,
  344. MAC_ADDR_IDX, MAC_ADDR_MW, 0);
  345. if (status)
  346. goto exit;
  347. ql_write32(qdev, MAC_ADDR_IDX, (offset++) | /* offset */
  348. (index << MAC_ADDR_IDX_SHIFT) | /* index */
  349. type); /* type */
  350. ql_write32(qdev, MAC_ADDR_DATA, lower);
  351. status =
  352. ql_wait_reg_rdy(qdev,
  353. MAC_ADDR_IDX, MAC_ADDR_MW, 0);
  354. if (status)
  355. goto exit;
  356. ql_write32(qdev, MAC_ADDR_IDX, (offset++) | /* offset */
  357. (index << MAC_ADDR_IDX_SHIFT) | /* index */
  358. type); /* type */
  359. ql_write32(qdev, MAC_ADDR_DATA, upper);
  360. status =
  361. ql_wait_reg_rdy(qdev,
  362. MAC_ADDR_IDX, MAC_ADDR_MW, 0);
  363. if (status)
  364. goto exit;
  365. ql_write32(qdev, MAC_ADDR_IDX, (offset) | /* offset */
  366. (index << MAC_ADDR_IDX_SHIFT) | /* index */
  367. type); /* type */
  368. /* This field should also include the queue id
  369. and possibly the function id. Right now we hardcode
  370. the route field to NIC core.
  371. */
  372. cam_output = (CAM_OUT_ROUTE_NIC |
  373. (qdev->
  374. func << CAM_OUT_FUNC_SHIFT) |
  375. (0 << CAM_OUT_CQ_ID_SHIFT));
  376. if (qdev->ndev->features & NETIF_F_HW_VLAN_CTAG_RX)
  377. cam_output |= CAM_OUT_RV;
  378. /* route to NIC core */
  379. ql_write32(qdev, MAC_ADDR_DATA, cam_output);
  380. break;
  381. }
  382. case MAC_ADDR_TYPE_VLAN:
  383. {
  384. u32 enable_bit = *((u32 *) &addr[0]);
  385. /* For VLAN, the addr actually holds a bit that
  386. * either enables or disables the vlan id we are
  387. * addressing. It's either MAC_ADDR_E on or off.
  388. * That's bit-27 we're talking about.
  389. */
  390. status =
  391. ql_wait_reg_rdy(qdev,
  392. MAC_ADDR_IDX, MAC_ADDR_MW, 0);
  393. if (status)
  394. goto exit;
  395. ql_write32(qdev, MAC_ADDR_IDX, offset | /* offset */
  396. (index << MAC_ADDR_IDX_SHIFT) | /* index */
  397. type | /* type */
  398. enable_bit); /* enable/disable */
  399. break;
  400. }
  401. case MAC_ADDR_TYPE_MULTI_FLTR:
  402. default:
  403. netif_crit(qdev, ifup, qdev->ndev,
  404. "Address type %d not yet supported.\n", type);
  405. status = -EPERM;
  406. }
  407. exit:
  408. return status;
  409. }
  410. /* Set or clear MAC address in hardware. We sometimes
  411. * have to clear it to prevent wrong frame routing
  412. * especially in a bonding environment.
  413. */
  414. static int ql_set_mac_addr(struct ql_adapter *qdev, int set)
  415. {
  416. int status;
  417. char zero_mac_addr[ETH_ALEN];
  418. char *addr;
  419. if (set) {
  420. addr = &qdev->current_mac_addr[0];
  421. netif_printk(qdev, ifup, KERN_DEBUG, qdev->ndev,
  422. "Set Mac addr %pM\n", addr);
  423. } else {
  424. memset(zero_mac_addr, 0, ETH_ALEN);
  425. addr = &zero_mac_addr[0];
  426. netif_printk(qdev, ifup, KERN_DEBUG, qdev->ndev,
  427. "Clearing MAC address\n");
  428. }
  429. status = ql_sem_spinlock(qdev, SEM_MAC_ADDR_MASK);
  430. if (status)
  431. return status;
  432. status = ql_set_mac_addr_reg(qdev, (u8 *) addr,
  433. MAC_ADDR_TYPE_CAM_MAC, qdev->func * MAX_CQ);
  434. ql_sem_unlock(qdev, SEM_MAC_ADDR_MASK);
  435. if (status)
  436. netif_err(qdev, ifup, qdev->ndev,
  437. "Failed to init mac address.\n");
  438. return status;
  439. }
  440. void ql_link_on(struct ql_adapter *qdev)
  441. {
  442. netif_err(qdev, link, qdev->ndev, "Link is up.\n");
  443. netif_carrier_on(qdev->ndev);
  444. ql_set_mac_addr(qdev, 1);
  445. }
  446. void ql_link_off(struct ql_adapter *qdev)
  447. {
  448. netif_err(qdev, link, qdev->ndev, "Link is down.\n");
  449. netif_carrier_off(qdev->ndev);
  450. ql_set_mac_addr(qdev, 0);
  451. }
  452. /* Get a specific frame routing value from the CAM.
  453. * Used for debug and reg dump.
  454. */
  455. int ql_get_routing_reg(struct ql_adapter *qdev, u32 index, u32 *value)
  456. {
  457. int status = 0;
  458. status = ql_wait_reg_rdy(qdev, RT_IDX, RT_IDX_MW, 0);
  459. if (status)
  460. goto exit;
  461. ql_write32(qdev, RT_IDX,
  462. RT_IDX_TYPE_NICQ | RT_IDX_RS | (index << RT_IDX_IDX_SHIFT));
  463. status = ql_wait_reg_rdy(qdev, RT_IDX, RT_IDX_MR, 0);
  464. if (status)
  465. goto exit;
  466. *value = ql_read32(qdev, RT_DATA);
  467. exit:
  468. return status;
  469. }
  470. /* The NIC function for this chip has 16 routing indexes. Each one can be used
  471. * to route different frame types to various inbound queues. We send broadcast/
  472. * multicast/error frames to the default queue for slow handling,
  473. * and CAM hit/RSS frames to the fast handling queues.
  474. */
  475. static int ql_set_routing_reg(struct ql_adapter *qdev, u32 index, u32 mask,
  476. int enable)
  477. {
  478. int status = -EINVAL; /* Return error if no mask match. */
  479. u32 value = 0;
  480. switch (mask) {
  481. case RT_IDX_CAM_HIT:
  482. {
  483. value = RT_IDX_DST_CAM_Q | /* dest */
  484. RT_IDX_TYPE_NICQ | /* type */
  485. (RT_IDX_CAM_HIT_SLOT << RT_IDX_IDX_SHIFT);/* index */
  486. break;
  487. }
  488. case RT_IDX_VALID: /* Promiscuous Mode frames. */
  489. {
  490. value = RT_IDX_DST_DFLT_Q | /* dest */
  491. RT_IDX_TYPE_NICQ | /* type */
  492. (RT_IDX_PROMISCUOUS_SLOT << RT_IDX_IDX_SHIFT);/* index */
  493. break;
  494. }
  495. case RT_IDX_ERR: /* Pass up MAC,IP,TCP/UDP error frames. */
  496. {
  497. value = RT_IDX_DST_DFLT_Q | /* dest */
  498. RT_IDX_TYPE_NICQ | /* type */
  499. (RT_IDX_ALL_ERR_SLOT << RT_IDX_IDX_SHIFT);/* index */
  500. break;
  501. }
  502. case RT_IDX_IP_CSUM_ERR: /* Pass up IP CSUM error frames. */
  503. {
  504. value = RT_IDX_DST_DFLT_Q | /* dest */
  505. RT_IDX_TYPE_NICQ | /* type */
  506. (RT_IDX_IP_CSUM_ERR_SLOT <<
  507. RT_IDX_IDX_SHIFT); /* index */
  508. break;
  509. }
  510. case RT_IDX_TU_CSUM_ERR: /* Pass up TCP/UDP CSUM error frames. */
  511. {
  512. value = RT_IDX_DST_DFLT_Q | /* dest */
  513. RT_IDX_TYPE_NICQ | /* type */
  514. (RT_IDX_TCP_UDP_CSUM_ERR_SLOT <<
  515. RT_IDX_IDX_SHIFT); /* index */
  516. break;
  517. }
  518. case RT_IDX_BCAST: /* Pass up Broadcast frames to default Q. */
  519. {
  520. value = RT_IDX_DST_DFLT_Q | /* dest */
  521. RT_IDX_TYPE_NICQ | /* type */
  522. (RT_IDX_BCAST_SLOT << RT_IDX_IDX_SHIFT);/* index */
  523. break;
  524. }
  525. case RT_IDX_MCAST: /* Pass up All Multicast frames. */
  526. {
  527. value = RT_IDX_DST_DFLT_Q | /* dest */
  528. RT_IDX_TYPE_NICQ | /* type */
  529. (RT_IDX_ALLMULTI_SLOT << RT_IDX_IDX_SHIFT);/* index */
  530. break;
  531. }
  532. case RT_IDX_MCAST_MATCH: /* Pass up matched Multicast frames. */
  533. {
  534. value = RT_IDX_DST_DFLT_Q | /* dest */
  535. RT_IDX_TYPE_NICQ | /* type */
  536. (RT_IDX_MCAST_MATCH_SLOT << RT_IDX_IDX_SHIFT);/* index */
  537. break;
  538. }
  539. case RT_IDX_RSS_MATCH: /* Pass up matched RSS frames. */
  540. {
  541. value = RT_IDX_DST_RSS | /* dest */
  542. RT_IDX_TYPE_NICQ | /* type */
  543. (RT_IDX_RSS_MATCH_SLOT << RT_IDX_IDX_SHIFT);/* index */
  544. break;
  545. }
  546. case 0: /* Clear the E-bit on an entry. */
  547. {
  548. value = RT_IDX_DST_DFLT_Q | /* dest */
  549. RT_IDX_TYPE_NICQ | /* type */
  550. (index << RT_IDX_IDX_SHIFT);/* index */
  551. break;
  552. }
  553. default:
  554. netif_err(qdev, ifup, qdev->ndev,
  555. "Mask type %d not yet supported.\n", mask);
  556. status = -EPERM;
  557. goto exit;
  558. }
  559. if (value) {
  560. status = ql_wait_reg_rdy(qdev, RT_IDX, RT_IDX_MW, 0);
  561. if (status)
  562. goto exit;
  563. value |= (enable ? RT_IDX_E : 0);
  564. ql_write32(qdev, RT_IDX, value);
  565. ql_write32(qdev, RT_DATA, enable ? mask : 0);
  566. }
  567. exit:
  568. return status;
  569. }
  570. static void ql_enable_interrupts(struct ql_adapter *qdev)
  571. {
  572. ql_write32(qdev, INTR_EN, (INTR_EN_EI << 16) | INTR_EN_EI);
  573. }
  574. static void ql_disable_interrupts(struct ql_adapter *qdev)
  575. {
  576. ql_write32(qdev, INTR_EN, (INTR_EN_EI << 16));
  577. }
  578. /* If we're running with multiple MSI-X vectors then we enable on the fly.
  579. * Otherwise, we may have multiple outstanding workers and don't want to
  580. * enable until the last one finishes. In this case, the irq_cnt gets
  581. * incremented every time we queue a worker and decremented every time
  582. * a worker finishes. Once it hits zero we enable the interrupt.
  583. */
  584. u32 ql_enable_completion_interrupt(struct ql_adapter *qdev, u32 intr)
  585. {
  586. u32 var = 0;
  587. unsigned long hw_flags = 0;
  588. struct intr_context *ctx = qdev->intr_context + intr;
  589. if (likely(test_bit(QL_MSIX_ENABLED, &qdev->flags) && intr)) {
  590. /* Always enable if we're MSIX multi interrupts and
  591. * it's not the default (zeroeth) interrupt.
  592. */
  593. ql_write32(qdev, INTR_EN,
  594. ctx->intr_en_mask);
  595. var = ql_read32(qdev, STS);
  596. return var;
  597. }
  598. spin_lock_irqsave(&qdev->hw_lock, hw_flags);
  599. if (atomic_dec_and_test(&ctx->irq_cnt)) {
  600. ql_write32(qdev, INTR_EN,
  601. ctx->intr_en_mask);
  602. var = ql_read32(qdev, STS);
  603. }
  604. spin_unlock_irqrestore(&qdev->hw_lock, hw_flags);
  605. return var;
  606. }
  607. static u32 ql_disable_completion_interrupt(struct ql_adapter *qdev, u32 intr)
  608. {
  609. u32 var = 0;
  610. struct intr_context *ctx;
  611. /* HW disables for us if we're MSIX multi interrupts and
  612. * it's not the default (zeroeth) interrupt.
  613. */
  614. if (likely(test_bit(QL_MSIX_ENABLED, &qdev->flags) && intr))
  615. return 0;
  616. ctx = qdev->intr_context + intr;
  617. spin_lock(&qdev->hw_lock);
  618. if (!atomic_read(&ctx->irq_cnt)) {
  619. ql_write32(qdev, INTR_EN,
  620. ctx->intr_dis_mask);
  621. var = ql_read32(qdev, STS);
  622. }
  623. atomic_inc(&ctx->irq_cnt);
  624. spin_unlock(&qdev->hw_lock);
  625. return var;
  626. }
  627. static void ql_enable_all_completion_interrupts(struct ql_adapter *qdev)
  628. {
  629. int i;
  630. for (i = 0; i < qdev->intr_count; i++) {
  631. /* The enable call does a atomic_dec_and_test
  632. * and enables only if the result is zero.
  633. * So we precharge it here.
  634. */
  635. if (unlikely(!test_bit(QL_MSIX_ENABLED, &qdev->flags) ||
  636. i == 0))
  637. atomic_set(&qdev->intr_context[i].irq_cnt, 1);
  638. ql_enable_completion_interrupt(qdev, i);
  639. }
  640. }
  641. static int ql_validate_flash(struct ql_adapter *qdev, u32 size, const char *str)
  642. {
  643. int status, i;
  644. u16 csum = 0;
  645. __le16 *flash = (__le16 *)&qdev->flash;
  646. status = strncmp((char *)&qdev->flash, str, 4);
  647. if (status) {
  648. netif_err(qdev, ifup, qdev->ndev, "Invalid flash signature.\n");
  649. return status;
  650. }
  651. for (i = 0; i < size; i++)
  652. csum += le16_to_cpu(*flash++);
  653. if (csum)
  654. netif_err(qdev, ifup, qdev->ndev,
  655. "Invalid flash checksum, csum = 0x%.04x.\n", csum);
  656. return csum;
  657. }
  658. static int ql_read_flash_word(struct ql_adapter *qdev, int offset, __le32 *data)
  659. {
  660. int status = 0;
  661. /* wait for reg to come ready */
  662. status = ql_wait_reg_rdy(qdev,
  663. FLASH_ADDR, FLASH_ADDR_RDY, FLASH_ADDR_ERR);
  664. if (status)
  665. goto exit;
  666. /* set up for reg read */
  667. ql_write32(qdev, FLASH_ADDR, FLASH_ADDR_R | offset);
  668. /* wait for reg to come ready */
  669. status = ql_wait_reg_rdy(qdev,
  670. FLASH_ADDR, FLASH_ADDR_RDY, FLASH_ADDR_ERR);
  671. if (status)
  672. goto exit;
  673. /* This data is stored on flash as an array of
  674. * __le32. Since ql_read32() returns cpu endian
  675. * we need to swap it back.
  676. */
  677. *data = cpu_to_le32(ql_read32(qdev, FLASH_DATA));
  678. exit:
  679. return status;
  680. }
  681. static int ql_get_8000_flash_params(struct ql_adapter *qdev)
  682. {
  683. u32 i, size;
  684. int status;
  685. __le32 *p = (__le32 *)&qdev->flash;
  686. u32 offset;
  687. u8 mac_addr[6];
  688. /* Get flash offset for function and adjust
  689. * for dword access.
  690. */
  691. if (!qdev->port)
  692. offset = FUNC0_FLASH_OFFSET / sizeof(u32);
  693. else
  694. offset = FUNC1_FLASH_OFFSET / sizeof(u32);
  695. if (ql_sem_spinlock(qdev, SEM_FLASH_MASK))
  696. return -ETIMEDOUT;
  697. size = sizeof(struct flash_params_8000) / sizeof(u32);
  698. for (i = 0; i < size; i++, p++) {
  699. status = ql_read_flash_word(qdev, i+offset, p);
  700. if (status) {
  701. netif_err(qdev, ifup, qdev->ndev,
  702. "Error reading flash.\n");
  703. goto exit;
  704. }
  705. }
  706. status = ql_validate_flash(qdev,
  707. sizeof(struct flash_params_8000) / sizeof(u16),
  708. "8000");
  709. if (status) {
  710. netif_err(qdev, ifup, qdev->ndev, "Invalid flash.\n");
  711. status = -EINVAL;
  712. goto exit;
  713. }
  714. /* Extract either manufacturer or BOFM modified
  715. * MAC address.
  716. */
  717. if (qdev->flash.flash_params_8000.data_type1 == 2)
  718. memcpy(mac_addr,
  719. qdev->flash.flash_params_8000.mac_addr1,
  720. qdev->ndev->addr_len);
  721. else
  722. memcpy(mac_addr,
  723. qdev->flash.flash_params_8000.mac_addr,
  724. qdev->ndev->addr_len);
  725. if (!is_valid_ether_addr(mac_addr)) {
  726. netif_err(qdev, ifup, qdev->ndev, "Invalid MAC address.\n");
  727. status = -EINVAL;
  728. goto exit;
  729. }
  730. memcpy(qdev->ndev->dev_addr,
  731. mac_addr,
  732. qdev->ndev->addr_len);
  733. exit:
  734. ql_sem_unlock(qdev, SEM_FLASH_MASK);
  735. return status;
  736. }
  737. static int ql_get_8012_flash_params(struct ql_adapter *qdev)
  738. {
  739. int i;
  740. int status;
  741. __le32 *p = (__le32 *)&qdev->flash;
  742. u32 offset = 0;
  743. u32 size = sizeof(struct flash_params_8012) / sizeof(u32);
  744. /* Second function's parameters follow the first
  745. * function's.
  746. */
  747. if (qdev->port)
  748. offset = size;
  749. if (ql_sem_spinlock(qdev, SEM_FLASH_MASK))
  750. return -ETIMEDOUT;
  751. for (i = 0; i < size; i++, p++) {
  752. status = ql_read_flash_word(qdev, i+offset, p);
  753. if (status) {
  754. netif_err(qdev, ifup, qdev->ndev,
  755. "Error reading flash.\n");
  756. goto exit;
  757. }
  758. }
  759. status = ql_validate_flash(qdev,
  760. sizeof(struct flash_params_8012) / sizeof(u16),
  761. "8012");
  762. if (status) {
  763. netif_err(qdev, ifup, qdev->ndev, "Invalid flash.\n");
  764. status = -EINVAL;
  765. goto exit;
  766. }
  767. if (!is_valid_ether_addr(qdev->flash.flash_params_8012.mac_addr)) {
  768. status = -EINVAL;
  769. goto exit;
  770. }
  771. memcpy(qdev->ndev->dev_addr,
  772. qdev->flash.flash_params_8012.mac_addr,
  773. qdev->ndev->addr_len);
  774. exit:
  775. ql_sem_unlock(qdev, SEM_FLASH_MASK);
  776. return status;
  777. }
  778. /* xgmac register are located behind the xgmac_addr and xgmac_data
  779. * register pair. Each read/write requires us to wait for the ready
  780. * bit before reading/writing the data.
  781. */
  782. static int ql_write_xgmac_reg(struct ql_adapter *qdev, u32 reg, u32 data)
  783. {
  784. int status;
  785. /* wait for reg to come ready */
  786. status = ql_wait_reg_rdy(qdev,
  787. XGMAC_ADDR, XGMAC_ADDR_RDY, XGMAC_ADDR_XME);
  788. if (status)
  789. return status;
  790. /* write the data to the data reg */
  791. ql_write32(qdev, XGMAC_DATA, data);
  792. /* trigger the write */
  793. ql_write32(qdev, XGMAC_ADDR, reg);
  794. return status;
  795. }
  796. /* xgmac register are located behind the xgmac_addr and xgmac_data
  797. * register pair. Each read/write requires us to wait for the ready
  798. * bit before reading/writing the data.
  799. */
  800. int ql_read_xgmac_reg(struct ql_adapter *qdev, u32 reg, u32 *data)
  801. {
  802. int status = 0;
  803. /* wait for reg to come ready */
  804. status = ql_wait_reg_rdy(qdev,
  805. XGMAC_ADDR, XGMAC_ADDR_RDY, XGMAC_ADDR_XME);
  806. if (status)
  807. goto exit;
  808. /* set up for reg read */
  809. ql_write32(qdev, XGMAC_ADDR, reg | XGMAC_ADDR_R);
  810. /* wait for reg to come ready */
  811. status = ql_wait_reg_rdy(qdev,
  812. XGMAC_ADDR, XGMAC_ADDR_RDY, XGMAC_ADDR_XME);
  813. if (status)
  814. goto exit;
  815. /* get the data */
  816. *data = ql_read32(qdev, XGMAC_DATA);
  817. exit:
  818. return status;
  819. }
  820. /* This is used for reading the 64-bit statistics regs. */
  821. int ql_read_xgmac_reg64(struct ql_adapter *qdev, u32 reg, u64 *data)
  822. {
  823. int status = 0;
  824. u32 hi = 0;
  825. u32 lo = 0;
  826. status = ql_read_xgmac_reg(qdev, reg, &lo);
  827. if (status)
  828. goto exit;
  829. status = ql_read_xgmac_reg(qdev, reg + 4, &hi);
  830. if (status)
  831. goto exit;
  832. *data = (u64) lo | ((u64) hi << 32);
  833. exit:
  834. return status;
  835. }
  836. static int ql_8000_port_initialize(struct ql_adapter *qdev)
  837. {
  838. int status;
  839. /*
  840. * Get MPI firmware version for driver banner
  841. * and ethool info.
  842. */
  843. status = ql_mb_about_fw(qdev);
  844. if (status)
  845. goto exit;
  846. status = ql_mb_get_fw_state(qdev);
  847. if (status)
  848. goto exit;
  849. /* Wake up a worker to get/set the TX/RX frame sizes. */
  850. queue_delayed_work(qdev->workqueue, &qdev->mpi_port_cfg_work, 0);
  851. exit:
  852. return status;
  853. }
  854. /* Take the MAC Core out of reset.
  855. * Enable statistics counting.
  856. * Take the transmitter/receiver out of reset.
  857. * This functionality may be done in the MPI firmware at a
  858. * later date.
  859. */
  860. static int ql_8012_port_initialize(struct ql_adapter *qdev)
  861. {
  862. int status = 0;
  863. u32 data;
  864. if (ql_sem_trylock(qdev, qdev->xg_sem_mask)) {
  865. /* Another function has the semaphore, so
  866. * wait for the port init bit to come ready.
  867. */
  868. netif_info(qdev, link, qdev->ndev,
  869. "Another function has the semaphore, so wait for the port init bit to come ready.\n");
  870. status = ql_wait_reg_rdy(qdev, STS, qdev->port_init, 0);
  871. if (status) {
  872. netif_crit(qdev, link, qdev->ndev,
  873. "Port initialize timed out.\n");
  874. }
  875. return status;
  876. }
  877. netif_info(qdev, link, qdev->ndev, "Got xgmac semaphore!.\n");
  878. /* Set the core reset. */
  879. status = ql_read_xgmac_reg(qdev, GLOBAL_CFG, &data);
  880. if (status)
  881. goto end;
  882. data |= GLOBAL_CFG_RESET;
  883. status = ql_write_xgmac_reg(qdev, GLOBAL_CFG, data);
  884. if (status)
  885. goto end;
  886. /* Clear the core reset and turn on jumbo for receiver. */
  887. data &= ~GLOBAL_CFG_RESET; /* Clear core reset. */
  888. data |= GLOBAL_CFG_JUMBO; /* Turn on jumbo. */
  889. data |= GLOBAL_CFG_TX_STAT_EN;
  890. data |= GLOBAL_CFG_RX_STAT_EN;
  891. status = ql_write_xgmac_reg(qdev, GLOBAL_CFG, data);
  892. if (status)
  893. goto end;
  894. /* Enable transmitter, and clear it's reset. */
  895. status = ql_read_xgmac_reg(qdev, TX_CFG, &data);
  896. if (status)
  897. goto end;
  898. data &= ~TX_CFG_RESET; /* Clear the TX MAC reset. */
  899. data |= TX_CFG_EN; /* Enable the transmitter. */
  900. status = ql_write_xgmac_reg(qdev, TX_CFG, data);
  901. if (status)
  902. goto end;
  903. /* Enable receiver and clear it's reset. */
  904. status = ql_read_xgmac_reg(qdev, RX_CFG, &data);
  905. if (status)
  906. goto end;
  907. data &= ~RX_CFG_RESET; /* Clear the RX MAC reset. */
  908. data |= RX_CFG_EN; /* Enable the receiver. */
  909. status = ql_write_xgmac_reg(qdev, RX_CFG, data);
  910. if (status)
  911. goto end;
  912. /* Turn on jumbo. */
  913. status =
  914. ql_write_xgmac_reg(qdev, MAC_TX_PARAMS, MAC_TX_PARAMS_JUMBO | (0x2580 << 16));
  915. if (status)
  916. goto end;
  917. status =
  918. ql_write_xgmac_reg(qdev, MAC_RX_PARAMS, 0x2580);
  919. if (status)
  920. goto end;
  921. /* Signal to the world that the port is enabled. */
  922. ql_write32(qdev, STS, ((qdev->port_init << 16) | qdev->port_init));
  923. end:
  924. ql_sem_unlock(qdev, qdev->xg_sem_mask);
  925. return status;
  926. }
  927. static inline unsigned int ql_lbq_block_size(struct ql_adapter *qdev)
  928. {
  929. return PAGE_SIZE << qdev->lbq_buf_order;
  930. }
  931. /* Get the next large buffer. */
  932. static struct bq_desc *ql_get_curr_lbuf(struct rx_ring *rx_ring)
  933. {
  934. struct bq_desc *lbq_desc = &rx_ring->lbq[rx_ring->lbq_curr_idx];
  935. rx_ring->lbq_curr_idx++;
  936. if (rx_ring->lbq_curr_idx == rx_ring->lbq_len)
  937. rx_ring->lbq_curr_idx = 0;
  938. rx_ring->lbq_free_cnt++;
  939. return lbq_desc;
  940. }
  941. static struct bq_desc *ql_get_curr_lchunk(struct ql_adapter *qdev,
  942. struct rx_ring *rx_ring)
  943. {
  944. struct bq_desc *lbq_desc = ql_get_curr_lbuf(rx_ring);
  945. pci_dma_sync_single_for_cpu(qdev->pdev,
  946. dma_unmap_addr(lbq_desc, mapaddr),
  947. rx_ring->lbq_buf_size,
  948. PCI_DMA_FROMDEVICE);
  949. /* If it's the last chunk of our master page then
  950. * we unmap it.
  951. */
  952. if ((lbq_desc->p.pg_chunk.offset + rx_ring->lbq_buf_size)
  953. == ql_lbq_block_size(qdev))
  954. pci_unmap_page(qdev->pdev,
  955. lbq_desc->p.pg_chunk.map,
  956. ql_lbq_block_size(qdev),
  957. PCI_DMA_FROMDEVICE);
  958. return lbq_desc;
  959. }
  960. /* Get the next small buffer. */
  961. static struct bq_desc *ql_get_curr_sbuf(struct rx_ring *rx_ring)
  962. {
  963. struct bq_desc *sbq_desc = &rx_ring->sbq[rx_ring->sbq_curr_idx];
  964. rx_ring->sbq_curr_idx++;
  965. if (rx_ring->sbq_curr_idx == rx_ring->sbq_len)
  966. rx_ring->sbq_curr_idx = 0;
  967. rx_ring->sbq_free_cnt++;
  968. return sbq_desc;
  969. }
  970. /* Update an rx ring index. */
  971. static void ql_update_cq(struct rx_ring *rx_ring)
  972. {
  973. rx_ring->cnsmr_idx++;
  974. rx_ring->curr_entry++;
  975. if (unlikely(rx_ring->cnsmr_idx == rx_ring->cq_len)) {
  976. rx_ring->cnsmr_idx = 0;
  977. rx_ring->curr_entry = rx_ring->cq_base;
  978. }
  979. }
  980. static void ql_write_cq_idx(struct rx_ring *rx_ring)
  981. {
  982. ql_write_db_reg(rx_ring->cnsmr_idx, rx_ring->cnsmr_idx_db_reg);
  983. }
  984. static int ql_get_next_chunk(struct ql_adapter *qdev, struct rx_ring *rx_ring,
  985. struct bq_desc *lbq_desc)
  986. {
  987. if (!rx_ring->pg_chunk.page) {
  988. u64 map;
  989. rx_ring->pg_chunk.page = alloc_pages(__GFP_COLD | __GFP_COMP |
  990. GFP_ATOMIC,
  991. qdev->lbq_buf_order);
  992. if (unlikely(!rx_ring->pg_chunk.page)) {
  993. netif_err(qdev, drv, qdev->ndev,
  994. "page allocation failed.\n");
  995. return -ENOMEM;
  996. }
  997. rx_ring->pg_chunk.offset = 0;
  998. map = pci_map_page(qdev->pdev, rx_ring->pg_chunk.page,
  999. 0, ql_lbq_block_size(qdev),
  1000. PCI_DMA_FROMDEVICE);
  1001. if (pci_dma_mapping_error(qdev->pdev, map)) {
  1002. __free_pages(rx_ring->pg_chunk.page,
  1003. qdev->lbq_buf_order);
  1004. netif_err(qdev, drv, qdev->ndev,
  1005. "PCI mapping failed.\n");
  1006. return -ENOMEM;
  1007. }
  1008. rx_ring->pg_chunk.map = map;
  1009. rx_ring->pg_chunk.va = page_address(rx_ring->pg_chunk.page);
  1010. }
  1011. /* Copy the current master pg_chunk info
  1012. * to the current descriptor.
  1013. */
  1014. lbq_desc->p.pg_chunk = rx_ring->pg_chunk;
  1015. /* Adjust the master page chunk for next
  1016. * buffer get.
  1017. */
  1018. rx_ring->pg_chunk.offset += rx_ring->lbq_buf_size;
  1019. if (rx_ring->pg_chunk.offset == ql_lbq_block_size(qdev)) {
  1020. rx_ring->pg_chunk.page = NULL;
  1021. lbq_desc->p.pg_chunk.last_flag = 1;
  1022. } else {
  1023. rx_ring->pg_chunk.va += rx_ring->lbq_buf_size;
  1024. get_page(rx_ring->pg_chunk.page);
  1025. lbq_desc->p.pg_chunk.last_flag = 0;
  1026. }
  1027. return 0;
  1028. }
  1029. /* Process (refill) a large buffer queue. */
  1030. static void ql_update_lbq(struct ql_adapter *qdev, struct rx_ring *rx_ring)
  1031. {
  1032. u32 clean_idx = rx_ring->lbq_clean_idx;
  1033. u32 start_idx = clean_idx;
  1034. struct bq_desc *lbq_desc;
  1035. u64 map;
  1036. int i;
  1037. while (rx_ring->lbq_free_cnt > 32) {
  1038. for (i = (rx_ring->lbq_clean_idx % 16); i < 16; i++) {
  1039. netif_printk(qdev, rx_status, KERN_DEBUG, qdev->ndev,
  1040. "lbq: try cleaning clean_idx = %d.\n",
  1041. clean_idx);
  1042. lbq_desc = &rx_ring->lbq[clean_idx];
  1043. if (ql_get_next_chunk(qdev, rx_ring, lbq_desc)) {
  1044. rx_ring->lbq_clean_idx = clean_idx;
  1045. netif_err(qdev, ifup, qdev->ndev,
  1046. "Could not get a page chunk, i=%d, clean_idx =%d .\n",
  1047. i, clean_idx);
  1048. return;
  1049. }
  1050. map = lbq_desc->p.pg_chunk.map +
  1051. lbq_desc->p.pg_chunk.offset;
  1052. dma_unmap_addr_set(lbq_desc, mapaddr, map);
  1053. dma_unmap_len_set(lbq_desc, maplen,
  1054. rx_ring->lbq_buf_size);
  1055. *lbq_desc->addr = cpu_to_le64(map);
  1056. pci_dma_sync_single_for_device(qdev->pdev, map,
  1057. rx_ring->lbq_buf_size,
  1058. PCI_DMA_FROMDEVICE);
  1059. clean_idx++;
  1060. if (clean_idx == rx_ring->lbq_len)
  1061. clean_idx = 0;
  1062. }
  1063. rx_ring->lbq_clean_idx = clean_idx;
  1064. rx_ring->lbq_prod_idx += 16;
  1065. if (rx_ring->lbq_prod_idx == rx_ring->lbq_len)
  1066. rx_ring->lbq_prod_idx = 0;
  1067. rx_ring->lbq_free_cnt -= 16;
  1068. }
  1069. if (start_idx != clean_idx) {
  1070. netif_printk(qdev, rx_status, KERN_DEBUG, qdev->ndev,
  1071. "lbq: updating prod idx = %d.\n",
  1072. rx_ring->lbq_prod_idx);
  1073. ql_write_db_reg(rx_ring->lbq_prod_idx,
  1074. rx_ring->lbq_prod_idx_db_reg);
  1075. }
  1076. }
  1077. /* Process (refill) a small buffer queue. */
  1078. static void ql_update_sbq(struct ql_adapter *qdev, struct rx_ring *rx_ring)
  1079. {
  1080. u32 clean_idx = rx_ring->sbq_clean_idx;
  1081. u32 start_idx = clean_idx;
  1082. struct bq_desc *sbq_desc;
  1083. u64 map;
  1084. int i;
  1085. while (rx_ring->sbq_free_cnt > 16) {
  1086. for (i = (rx_ring->sbq_clean_idx % 16); i < 16; i++) {
  1087. sbq_desc = &rx_ring->sbq[clean_idx];
  1088. netif_printk(qdev, rx_status, KERN_DEBUG, qdev->ndev,
  1089. "sbq: try cleaning clean_idx = %d.\n",
  1090. clean_idx);
  1091. if (sbq_desc->p.skb == NULL) {
  1092. netif_printk(qdev, rx_status, KERN_DEBUG,
  1093. qdev->ndev,
  1094. "sbq: getting new skb for index %d.\n",
  1095. sbq_desc->index);
  1096. sbq_desc->p.skb =
  1097. netdev_alloc_skb(qdev->ndev,
  1098. SMALL_BUFFER_SIZE);
  1099. if (sbq_desc->p.skb == NULL) {
  1100. rx_ring->sbq_clean_idx = clean_idx;
  1101. return;
  1102. }
  1103. skb_reserve(sbq_desc->p.skb, QLGE_SB_PAD);
  1104. map = pci_map_single(qdev->pdev,
  1105. sbq_desc->p.skb->data,
  1106. rx_ring->sbq_buf_size,
  1107. PCI_DMA_FROMDEVICE);
  1108. if (pci_dma_mapping_error(qdev->pdev, map)) {
  1109. netif_err(qdev, ifup, qdev->ndev,
  1110. "PCI mapping failed.\n");
  1111. rx_ring->sbq_clean_idx = clean_idx;
  1112. dev_kfree_skb_any(sbq_desc->p.skb);
  1113. sbq_desc->p.skb = NULL;
  1114. return;
  1115. }
  1116. dma_unmap_addr_set(sbq_desc, mapaddr, map);
  1117. dma_unmap_len_set(sbq_desc, maplen,
  1118. rx_ring->sbq_buf_size);
  1119. *sbq_desc->addr = cpu_to_le64(map);
  1120. }
  1121. clean_idx++;
  1122. if (clean_idx == rx_ring->sbq_len)
  1123. clean_idx = 0;
  1124. }
  1125. rx_ring->sbq_clean_idx = clean_idx;
  1126. rx_ring->sbq_prod_idx += 16;
  1127. if (rx_ring->sbq_prod_idx == rx_ring->sbq_len)
  1128. rx_ring->sbq_prod_idx = 0;
  1129. rx_ring->sbq_free_cnt -= 16;
  1130. }
  1131. if (start_idx != clean_idx) {
  1132. netif_printk(qdev, rx_status, KERN_DEBUG, qdev->ndev,
  1133. "sbq: updating prod idx = %d.\n",
  1134. rx_ring->sbq_prod_idx);
  1135. ql_write_db_reg(rx_ring->sbq_prod_idx,
  1136. rx_ring->sbq_prod_idx_db_reg);
  1137. }
  1138. }
  1139. static void ql_update_buffer_queues(struct ql_adapter *qdev,
  1140. struct rx_ring *rx_ring)
  1141. {
  1142. ql_update_sbq(qdev, rx_ring);
  1143. ql_update_lbq(qdev, rx_ring);
  1144. }
  1145. /* Unmaps tx buffers. Can be called from send() if a pci mapping
  1146. * fails at some stage, or from the interrupt when a tx completes.
  1147. */
  1148. static void ql_unmap_send(struct ql_adapter *qdev,
  1149. struct tx_ring_desc *tx_ring_desc, int mapped)
  1150. {
  1151. int i;
  1152. for (i = 0; i < mapped; i++) {
  1153. if (i == 0 || (i == 7 && mapped > 7)) {
  1154. /*
  1155. * Unmap the skb->data area, or the
  1156. * external sglist (AKA the Outbound
  1157. * Address List (OAL)).
  1158. * If its the zeroeth element, then it's
  1159. * the skb->data area. If it's the 7th
  1160. * element and there is more than 6 frags,
  1161. * then its an OAL.
  1162. */
  1163. if (i == 7) {
  1164. netif_printk(qdev, tx_done, KERN_DEBUG,
  1165. qdev->ndev,
  1166. "unmapping OAL area.\n");
  1167. }
  1168. pci_unmap_single(qdev->pdev,
  1169. dma_unmap_addr(&tx_ring_desc->map[i],
  1170. mapaddr),
  1171. dma_unmap_len(&tx_ring_desc->map[i],
  1172. maplen),
  1173. PCI_DMA_TODEVICE);
  1174. } else {
  1175. netif_printk(qdev, tx_done, KERN_DEBUG, qdev->ndev,
  1176. "unmapping frag %d.\n", i);
  1177. pci_unmap_page(qdev->pdev,
  1178. dma_unmap_addr(&tx_ring_desc->map[i],
  1179. mapaddr),
  1180. dma_unmap_len(&tx_ring_desc->map[i],
  1181. maplen), PCI_DMA_TODEVICE);
  1182. }
  1183. }
  1184. }
  1185. /* Map the buffers for this transmit. This will return
  1186. * NETDEV_TX_BUSY or NETDEV_TX_OK based on success.
  1187. */
  1188. static int ql_map_send(struct ql_adapter *qdev,
  1189. struct ob_mac_iocb_req *mac_iocb_ptr,
  1190. struct sk_buff *skb, struct tx_ring_desc *tx_ring_desc)
  1191. {
  1192. int len = skb_headlen(skb);
  1193. dma_addr_t map;
  1194. int frag_idx, err, map_idx = 0;
  1195. struct tx_buf_desc *tbd = mac_iocb_ptr->tbd;
  1196. int frag_cnt = skb_shinfo(skb)->nr_frags;
  1197. if (frag_cnt) {
  1198. netif_printk(qdev, tx_queued, KERN_DEBUG, qdev->ndev,
  1199. "frag_cnt = %d.\n", frag_cnt);
  1200. }
  1201. /*
  1202. * Map the skb buffer first.
  1203. */
  1204. map = pci_map_single(qdev->pdev, skb->data, len, PCI_DMA_TODEVICE);
  1205. err = pci_dma_mapping_error(qdev->pdev, map);
  1206. if (err) {
  1207. netif_err(qdev, tx_queued, qdev->ndev,
  1208. "PCI mapping failed with error: %d\n", err);
  1209. return NETDEV_TX_BUSY;
  1210. }
  1211. tbd->len = cpu_to_le32(len);
  1212. tbd->addr = cpu_to_le64(map);
  1213. dma_unmap_addr_set(&tx_ring_desc->map[map_idx], mapaddr, map);
  1214. dma_unmap_len_set(&tx_ring_desc->map[map_idx], maplen, len);
  1215. map_idx++;
  1216. /*
  1217. * This loop fills the remainder of the 8 address descriptors
  1218. * in the IOCB. If there are more than 7 fragments, then the
  1219. * eighth address desc will point to an external list (OAL).
  1220. * When this happens, the remainder of the frags will be stored
  1221. * in this list.
  1222. */
  1223. for (frag_idx = 0; frag_idx < frag_cnt; frag_idx++, map_idx++) {
  1224. skb_frag_t *frag = &skb_shinfo(skb)->frags[frag_idx];
  1225. tbd++;
  1226. if (frag_idx == 6 && frag_cnt > 7) {
  1227. /* Let's tack on an sglist.
  1228. * Our control block will now
  1229. * look like this:
  1230. * iocb->seg[0] = skb->data
  1231. * iocb->seg[1] = frag[0]
  1232. * iocb->seg[2] = frag[1]
  1233. * iocb->seg[3] = frag[2]
  1234. * iocb->seg[4] = frag[3]
  1235. * iocb->seg[5] = frag[4]
  1236. * iocb->seg[6] = frag[5]
  1237. * iocb->seg[7] = ptr to OAL (external sglist)
  1238. * oal->seg[0] = frag[6]
  1239. * oal->seg[1] = frag[7]
  1240. * oal->seg[2] = frag[8]
  1241. * oal->seg[3] = frag[9]
  1242. * oal->seg[4] = frag[10]
  1243. * etc...
  1244. */
  1245. /* Tack on the OAL in the eighth segment of IOCB. */
  1246. map = pci_map_single(qdev->pdev, &tx_ring_desc->oal,
  1247. sizeof(struct oal),
  1248. PCI_DMA_TODEVICE);
  1249. err = pci_dma_mapping_error(qdev->pdev, map);
  1250. if (err) {
  1251. netif_err(qdev, tx_queued, qdev->ndev,
  1252. "PCI mapping outbound address list with error: %d\n",
  1253. err);
  1254. goto map_error;
  1255. }
  1256. tbd->addr = cpu_to_le64(map);
  1257. /*
  1258. * The length is the number of fragments
  1259. * that remain to be mapped times the length
  1260. * of our sglist (OAL).
  1261. */
  1262. tbd->len =
  1263. cpu_to_le32((sizeof(struct tx_buf_desc) *
  1264. (frag_cnt - frag_idx)) | TX_DESC_C);
  1265. dma_unmap_addr_set(&tx_ring_desc->map[map_idx], mapaddr,
  1266. map);
  1267. dma_unmap_len_set(&tx_ring_desc->map[map_idx], maplen,
  1268. sizeof(struct oal));
  1269. tbd = (struct tx_buf_desc *)&tx_ring_desc->oal;
  1270. map_idx++;
  1271. }
  1272. map = skb_frag_dma_map(&qdev->pdev->dev, frag, 0, skb_frag_size(frag),
  1273. DMA_TO_DEVICE);
  1274. err = dma_mapping_error(&qdev->pdev->dev, map);
  1275. if (err) {
  1276. netif_err(qdev, tx_queued, qdev->ndev,
  1277. "PCI mapping frags failed with error: %d.\n",
  1278. err);
  1279. goto map_error;
  1280. }
  1281. tbd->addr = cpu_to_le64(map);
  1282. tbd->len = cpu_to_le32(skb_frag_size(frag));
  1283. dma_unmap_addr_set(&tx_ring_desc->map[map_idx], mapaddr, map);
  1284. dma_unmap_len_set(&tx_ring_desc->map[map_idx], maplen,
  1285. skb_frag_size(frag));
  1286. }
  1287. /* Save the number of segments we've mapped. */
  1288. tx_ring_desc->map_cnt = map_idx;
  1289. /* Terminate the last segment. */
  1290. tbd->len = cpu_to_le32(le32_to_cpu(tbd->len) | TX_DESC_E);
  1291. return NETDEV_TX_OK;
  1292. map_error:
  1293. /*
  1294. * If the first frag mapping failed, then i will be zero.
  1295. * This causes the unmap of the skb->data area. Otherwise
  1296. * we pass in the number of frags that mapped successfully
  1297. * so they can be umapped.
  1298. */
  1299. ql_unmap_send(qdev, tx_ring_desc, map_idx);
  1300. return NETDEV_TX_BUSY;
  1301. }
  1302. /* Categorizing receive firmware frame errors */
  1303. static void ql_categorize_rx_err(struct ql_adapter *qdev, u8 rx_err)
  1304. {
  1305. struct nic_stats *stats = &qdev->nic_stats;
  1306. stats->rx_err_count++;
  1307. switch (rx_err & IB_MAC_IOCB_RSP_ERR_MASK) {
  1308. case IB_MAC_IOCB_RSP_ERR_CODE_ERR:
  1309. stats->rx_code_err++;
  1310. break;
  1311. case IB_MAC_IOCB_RSP_ERR_OVERSIZE:
  1312. stats->rx_oversize_err++;
  1313. break;
  1314. case IB_MAC_IOCB_RSP_ERR_UNDERSIZE:
  1315. stats->rx_undersize_err++;
  1316. break;
  1317. case IB_MAC_IOCB_RSP_ERR_PREAMBLE:
  1318. stats->rx_preamble_err++;
  1319. break;
  1320. case IB_MAC_IOCB_RSP_ERR_FRAME_LEN:
  1321. stats->rx_frame_len_err++;
  1322. break;
  1323. case IB_MAC_IOCB_RSP_ERR_CRC:
  1324. stats->rx_crc_err++;
  1325. default:
  1326. break;
  1327. }
  1328. }
  1329. /* Process an inbound completion from an rx ring. */
  1330. static void ql_process_mac_rx_gro_page(struct ql_adapter *qdev,
  1331. struct rx_ring *rx_ring,
  1332. struct ib_mac_iocb_rsp *ib_mac_rsp,
  1333. u32 length,
  1334. u16 vlan_id)
  1335. {
  1336. struct sk_buff *skb;
  1337. struct bq_desc *lbq_desc = ql_get_curr_lchunk(qdev, rx_ring);
  1338. struct napi_struct *napi = &rx_ring->napi;
  1339. napi->dev = qdev->ndev;
  1340. skb = napi_get_frags(napi);
  1341. if (!skb) {
  1342. netif_err(qdev, drv, qdev->ndev,
  1343. "Couldn't get an skb, exiting.\n");
  1344. rx_ring->rx_dropped++;
  1345. put_page(lbq_desc->p.pg_chunk.page);
  1346. return;
  1347. }
  1348. prefetch(lbq_desc->p.pg_chunk.va);
  1349. __skb_fill_page_desc(skb, skb_shinfo(skb)->nr_frags,
  1350. lbq_desc->p.pg_chunk.page,
  1351. lbq_desc->p.pg_chunk.offset,
  1352. length);
  1353. skb->len += length;
  1354. skb->data_len += length;
  1355. skb->truesize += length;
  1356. skb_shinfo(skb)->nr_frags++;
  1357. rx_ring->rx_packets++;
  1358. rx_ring->rx_bytes += length;
  1359. skb->ip_summed = CHECKSUM_UNNECESSARY;
  1360. skb_record_rx_queue(skb, rx_ring->cq_id);
  1361. if (vlan_id != 0xffff)
  1362. __vlan_hwaccel_put_tag(skb, htons(ETH_P_8021Q), vlan_id);
  1363. napi_gro_frags(napi);
  1364. }
  1365. /* Process an inbound completion from an rx ring. */
  1366. static void ql_process_mac_rx_page(struct ql_adapter *qdev,
  1367. struct rx_ring *rx_ring,
  1368. struct ib_mac_iocb_rsp *ib_mac_rsp,
  1369. u32 length,
  1370. u16 vlan_id)
  1371. {
  1372. struct net_device *ndev = qdev->ndev;
  1373. struct sk_buff *skb = NULL;
  1374. void *addr;
  1375. struct bq_desc *lbq_desc = ql_get_curr_lchunk(qdev, rx_ring);
  1376. struct napi_struct *napi = &rx_ring->napi;
  1377. skb = netdev_alloc_skb(ndev, length);
  1378. if (!skb) {
  1379. rx_ring->rx_dropped++;
  1380. put_page(lbq_desc->p.pg_chunk.page);
  1381. return;
  1382. }
  1383. addr = lbq_desc->p.pg_chunk.va;
  1384. prefetch(addr);
  1385. /* The max framesize filter on this chip is set higher than
  1386. * MTU since FCoE uses 2k frames.
  1387. */
  1388. if (skb->len > ndev->mtu + ETH_HLEN) {
  1389. netif_err(qdev, drv, qdev->ndev,
  1390. "Segment too small, dropping.\n");
  1391. rx_ring->rx_dropped++;
  1392. goto err_out;
  1393. }
  1394. memcpy(skb_put(skb, ETH_HLEN), addr, ETH_HLEN);
  1395. netif_printk(qdev, rx_status, KERN_DEBUG, qdev->ndev,
  1396. "%d bytes of headers and data in large. Chain page to new skb and pull tail.\n",
  1397. length);
  1398. skb_fill_page_desc(skb, 0, lbq_desc->p.pg_chunk.page,
  1399. lbq_desc->p.pg_chunk.offset+ETH_HLEN,
  1400. length-ETH_HLEN);
  1401. skb->len += length-ETH_HLEN;
  1402. skb->data_len += length-ETH_HLEN;
  1403. skb->truesize += length-ETH_HLEN;
  1404. rx_ring->rx_packets++;
  1405. rx_ring->rx_bytes += skb->len;
  1406. skb->protocol = eth_type_trans(skb, ndev);
  1407. skb_checksum_none_assert(skb);
  1408. if ((ndev->features & NETIF_F_RXCSUM) &&
  1409. !(ib_mac_rsp->flags1 & IB_MAC_CSUM_ERR_MASK)) {
  1410. /* TCP frame. */
  1411. if (ib_mac_rsp->flags2 & IB_MAC_IOCB_RSP_T) {
  1412. netif_printk(qdev, rx_status, KERN_DEBUG, qdev->ndev,
  1413. "TCP checksum done!\n");
  1414. skb->ip_summed = CHECKSUM_UNNECESSARY;
  1415. } else if ((ib_mac_rsp->flags2 & IB_MAC_IOCB_RSP_U) &&
  1416. (ib_mac_rsp->flags3 & IB_MAC_IOCB_RSP_V4)) {
  1417. /* Unfragmented ipv4 UDP frame. */
  1418. struct iphdr *iph =
  1419. (struct iphdr *) ((u8 *)addr + ETH_HLEN);
  1420. if (!(iph->frag_off &
  1421. htons(IP_MF|IP_OFFSET))) {
  1422. skb->ip_summed = CHECKSUM_UNNECESSARY;
  1423. netif_printk(qdev, rx_status, KERN_DEBUG,
  1424. qdev->ndev,
  1425. "UDP checksum done!\n");
  1426. }
  1427. }
  1428. }
  1429. skb_record_rx_queue(skb, rx_ring->cq_id);
  1430. if (vlan_id != 0xffff)
  1431. __vlan_hwaccel_put_tag(skb, htons(ETH_P_8021Q), vlan_id);
  1432. if (skb->ip_summed == CHECKSUM_UNNECESSARY)
  1433. napi_gro_receive(napi, skb);
  1434. else
  1435. netif_receive_skb(skb);
  1436. return;
  1437. err_out:
  1438. dev_kfree_skb_any(skb);
  1439. put_page(lbq_desc->p.pg_chunk.page);
  1440. }
  1441. /* Process an inbound completion from an rx ring. */
  1442. static void ql_process_mac_rx_skb(struct ql_adapter *qdev,
  1443. struct rx_ring *rx_ring,
  1444. struct ib_mac_iocb_rsp *ib_mac_rsp,
  1445. u32 length,
  1446. u16 vlan_id)
  1447. {
  1448. struct net_device *ndev = qdev->ndev;
  1449. struct sk_buff *skb = NULL;
  1450. struct sk_buff *new_skb = NULL;
  1451. struct bq_desc *sbq_desc = ql_get_curr_sbuf(rx_ring);
  1452. skb = sbq_desc->p.skb;
  1453. /* Allocate new_skb and copy */
  1454. new_skb = netdev_alloc_skb(qdev->ndev, length + NET_IP_ALIGN);
  1455. if (new_skb == NULL) {
  1456. rx_ring->rx_dropped++;
  1457. return;
  1458. }
  1459. skb_reserve(new_skb, NET_IP_ALIGN);
  1460. memcpy(skb_put(new_skb, length), skb->data, length);
  1461. skb = new_skb;
  1462. /* loopback self test for ethtool */
  1463. if (test_bit(QL_SELFTEST, &qdev->flags)) {
  1464. ql_check_lb_frame(qdev, skb);
  1465. dev_kfree_skb_any(skb);
  1466. return;
  1467. }
  1468. /* The max framesize filter on this chip is set higher than
  1469. * MTU since FCoE uses 2k frames.
  1470. */
  1471. if (skb->len > ndev->mtu + ETH_HLEN) {
  1472. dev_kfree_skb_any(skb);
  1473. rx_ring->rx_dropped++;
  1474. return;
  1475. }
  1476. prefetch(skb->data);
  1477. if (ib_mac_rsp->flags1 & IB_MAC_IOCB_RSP_M_MASK) {
  1478. netif_printk(qdev, rx_status, KERN_DEBUG, qdev->ndev,
  1479. "%s Multicast.\n",
  1480. (ib_mac_rsp->flags1 & IB_MAC_IOCB_RSP_M_MASK) ==
  1481. IB_MAC_IOCB_RSP_M_HASH ? "Hash" :
  1482. (ib_mac_rsp->flags1 & IB_MAC_IOCB_RSP_M_MASK) ==
  1483. IB_MAC_IOCB_RSP_M_REG ? "Registered" :
  1484. (ib_mac_rsp->flags1 & IB_MAC_IOCB_RSP_M_MASK) ==
  1485. IB_MAC_IOCB_RSP_M_PROM ? "Promiscuous" : "");
  1486. }
  1487. if (ib_mac_rsp->flags2 & IB_MAC_IOCB_RSP_P)
  1488. netif_printk(qdev, rx_status, KERN_DEBUG, qdev->ndev,
  1489. "Promiscuous Packet.\n");
  1490. rx_ring->rx_packets++;
  1491. rx_ring->rx_bytes += skb->len;
  1492. skb->protocol = eth_type_trans(skb, ndev);
  1493. skb_checksum_none_assert(skb);
  1494. /* If rx checksum is on, and there are no
  1495. * csum or frame errors.
  1496. */
  1497. if ((ndev->features & NETIF_F_RXCSUM) &&
  1498. !(ib_mac_rsp->flags1 & IB_MAC_CSUM_ERR_MASK)) {
  1499. /* TCP frame. */
  1500. if (ib_mac_rsp->flags2 & IB_MAC_IOCB_RSP_T) {
  1501. netif_printk(qdev, rx_status, KERN_DEBUG, qdev->ndev,
  1502. "TCP checksum done!\n");
  1503. skb->ip_summed = CHECKSUM_UNNECESSARY;
  1504. } else if ((ib_mac_rsp->flags2 & IB_MAC_IOCB_RSP_U) &&
  1505. (ib_mac_rsp->flags3 & IB_MAC_IOCB_RSP_V4)) {
  1506. /* Unfragmented ipv4 UDP frame. */
  1507. struct iphdr *iph = (struct iphdr *) skb->data;
  1508. if (!(iph->frag_off &
  1509. htons(IP_MF|IP_OFFSET))) {
  1510. skb->ip_summed = CHECKSUM_UNNECESSARY;
  1511. netif_printk(qdev, rx_status, KERN_DEBUG,
  1512. qdev->ndev,
  1513. "UDP checksum done!\n");
  1514. }
  1515. }
  1516. }
  1517. skb_record_rx_queue(skb, rx_ring->cq_id);
  1518. if (vlan_id != 0xffff)
  1519. __vlan_hwaccel_put_tag(skb, htons(ETH_P_8021Q), vlan_id);
  1520. if (skb->ip_summed == CHECKSUM_UNNECESSARY)
  1521. napi_gro_receive(&rx_ring->napi, skb);
  1522. else
  1523. netif_receive_skb(skb);
  1524. }
  1525. static void ql_realign_skb(struct sk_buff *skb, int len)
  1526. {
  1527. void *temp_addr = skb->data;
  1528. /* Undo the skb_reserve(skb,32) we did before
  1529. * giving to hardware, and realign data on
  1530. * a 2-byte boundary.
  1531. */
  1532. skb->data -= QLGE_SB_PAD - NET_IP_ALIGN;
  1533. skb->tail -= QLGE_SB_PAD - NET_IP_ALIGN;
  1534. skb_copy_to_linear_data(skb, temp_addr,
  1535. (unsigned int)len);
  1536. }
  1537. /*
  1538. * This function builds an skb for the given inbound
  1539. * completion. It will be rewritten for readability in the near
  1540. * future, but for not it works well.
  1541. */
  1542. static struct sk_buff *ql_build_rx_skb(struct ql_adapter *qdev,
  1543. struct rx_ring *rx_ring,
  1544. struct ib_mac_iocb_rsp *ib_mac_rsp)
  1545. {
  1546. struct bq_desc *lbq_desc;
  1547. struct bq_desc *sbq_desc;
  1548. struct sk_buff *skb = NULL;
  1549. u32 length = le32_to_cpu(ib_mac_rsp->data_len);
  1550. u32 hdr_len = le32_to_cpu(ib_mac_rsp->hdr_len);
  1551. /*
  1552. * Handle the header buffer if present.
  1553. */
  1554. if (ib_mac_rsp->flags4 & IB_MAC_IOCB_RSP_HV &&
  1555. ib_mac_rsp->flags4 & IB_MAC_IOCB_RSP_HS) {
  1556. netif_printk(qdev, rx_status, KERN_DEBUG, qdev->ndev,
  1557. "Header of %d bytes in small buffer.\n", hdr_len);
  1558. /*
  1559. * Headers fit nicely into a small buffer.
  1560. */
  1561. sbq_desc = ql_get_curr_sbuf(rx_ring);
  1562. pci_unmap_single(qdev->pdev,
  1563. dma_unmap_addr(sbq_desc, mapaddr),
  1564. dma_unmap_len(sbq_desc, maplen),
  1565. PCI_DMA_FROMDEVICE);
  1566. skb = sbq_desc->p.skb;
  1567. ql_realign_skb(skb, hdr_len);
  1568. skb_put(skb, hdr_len);
  1569. sbq_desc->p.skb = NULL;
  1570. }
  1571. /*
  1572. * Handle the data buffer(s).
  1573. */
  1574. if (unlikely(!length)) { /* Is there data too? */
  1575. netif_printk(qdev, rx_status, KERN_DEBUG, qdev->ndev,
  1576. "No Data buffer in this packet.\n");
  1577. return skb;
  1578. }
  1579. if (ib_mac_rsp->flags3 & IB_MAC_IOCB_RSP_DS) {
  1580. if (ib_mac_rsp->flags4 & IB_MAC_IOCB_RSP_HS) {
  1581. netif_printk(qdev, rx_status, KERN_DEBUG, qdev->ndev,
  1582. "Headers in small, data of %d bytes in small, combine them.\n",
  1583. length);
  1584. /*
  1585. * Data is less than small buffer size so it's
  1586. * stuffed in a small buffer.
  1587. * For this case we append the data
  1588. * from the "data" small buffer to the "header" small
  1589. * buffer.
  1590. */
  1591. sbq_desc = ql_get_curr_sbuf(rx_ring);
  1592. pci_dma_sync_single_for_cpu(qdev->pdev,
  1593. dma_unmap_addr
  1594. (sbq_desc, mapaddr),
  1595. dma_unmap_len
  1596. (sbq_desc, maplen),
  1597. PCI_DMA_FROMDEVICE);
  1598. memcpy(skb_put(skb, length),
  1599. sbq_desc->p.skb->data, length);
  1600. pci_dma_sync_single_for_device(qdev->pdev,
  1601. dma_unmap_addr
  1602. (sbq_desc,
  1603. mapaddr),
  1604. dma_unmap_len
  1605. (sbq_desc,
  1606. maplen),
  1607. PCI_DMA_FROMDEVICE);
  1608. } else {
  1609. netif_printk(qdev, rx_status, KERN_DEBUG, qdev->ndev,
  1610. "%d bytes in a single small buffer.\n",
  1611. length);
  1612. sbq_desc = ql_get_curr_sbuf(rx_ring);
  1613. skb = sbq_desc->p.skb;
  1614. ql_realign_skb(skb, length);
  1615. skb_put(skb, length);
  1616. pci_unmap_single(qdev->pdev,
  1617. dma_unmap_addr(sbq_desc,
  1618. mapaddr),
  1619. dma_unmap_len(sbq_desc,
  1620. maplen),
  1621. PCI_DMA_FROMDEVICE);
  1622. sbq_desc->p.skb = NULL;
  1623. }
  1624. } else if (ib_mac_rsp->flags3 & IB_MAC_IOCB_RSP_DL) {
  1625. if (ib_mac_rsp->flags4 & IB_MAC_IOCB_RSP_HS) {
  1626. netif_printk(qdev, rx_status, KERN_DEBUG, qdev->ndev,
  1627. "Header in small, %d bytes in large. Chain large to small!\n",
  1628. length);
  1629. /*
  1630. * The data is in a single large buffer. We
  1631. * chain it to the header buffer's skb and let
  1632. * it rip.
  1633. */
  1634. lbq_desc = ql_get_curr_lchunk(qdev, rx_ring);
  1635. netif_printk(qdev, rx_status, KERN_DEBUG, qdev->ndev,
  1636. "Chaining page at offset = %d, for %d bytes to skb.\n",
  1637. lbq_desc->p.pg_chunk.offset, length);
  1638. skb_fill_page_desc(skb, 0, lbq_desc->p.pg_chunk.page,
  1639. lbq_desc->p.pg_chunk.offset,
  1640. length);
  1641. skb->len += length;
  1642. skb->data_len += length;
  1643. skb->truesize += length;
  1644. } else {
  1645. /*
  1646. * The headers and data are in a single large buffer. We
  1647. * copy it to a new skb and let it go. This can happen with
  1648. * jumbo mtu on a non-TCP/UDP frame.
  1649. */
  1650. lbq_desc = ql_get_curr_lchunk(qdev, rx_ring);
  1651. skb = netdev_alloc_skb(qdev->ndev, length);
  1652. if (skb == NULL) {
  1653. netif_printk(qdev, probe, KERN_DEBUG, qdev->ndev,
  1654. "No skb available, drop the packet.\n");
  1655. return NULL;
  1656. }
  1657. pci_unmap_page(qdev->pdev,
  1658. dma_unmap_addr(lbq_desc,
  1659. mapaddr),
  1660. dma_unmap_len(lbq_desc, maplen),
  1661. PCI_DMA_FROMDEVICE);
  1662. skb_reserve(skb, NET_IP_ALIGN);
  1663. netif_printk(qdev, rx_status, KERN_DEBUG, qdev->ndev,
  1664. "%d bytes of headers and data in large. Chain page to new skb and pull tail.\n",
  1665. length);
  1666. skb_fill_page_desc(skb, 0,
  1667. lbq_desc->p.pg_chunk.page,
  1668. lbq_desc->p.pg_chunk.offset,
  1669. length);
  1670. skb->len += length;
  1671. skb->data_len += length;
  1672. skb->truesize += length;
  1673. length -= length;
  1674. __pskb_pull_tail(skb,
  1675. (ib_mac_rsp->flags2 & IB_MAC_IOCB_RSP_V) ?
  1676. VLAN_ETH_HLEN : ETH_HLEN);
  1677. }
  1678. } else {
  1679. /*
  1680. * The data is in a chain of large buffers
  1681. * pointed to by a small buffer. We loop
  1682. * thru and chain them to the our small header
  1683. * buffer's skb.
  1684. * frags: There are 18 max frags and our small
  1685. * buffer will hold 32 of them. The thing is,
  1686. * we'll use 3 max for our 9000 byte jumbo
  1687. * frames. If the MTU goes up we could
  1688. * eventually be in trouble.
  1689. */
  1690. int size, i = 0;
  1691. sbq_desc = ql_get_curr_sbuf(rx_ring);
  1692. pci_unmap_single(qdev->pdev,
  1693. dma_unmap_addr(sbq_desc, mapaddr),
  1694. dma_unmap_len(sbq_desc, maplen),
  1695. PCI_DMA_FROMDEVICE);
  1696. if (!(ib_mac_rsp->flags4 & IB_MAC_IOCB_RSP_HS)) {
  1697. /*
  1698. * This is an non TCP/UDP IP frame, so
  1699. * the headers aren't split into a small
  1700. * buffer. We have to use the small buffer
  1701. * that contains our sg list as our skb to
  1702. * send upstairs. Copy the sg list here to
  1703. * a local buffer and use it to find the
  1704. * pages to chain.
  1705. */
  1706. netif_printk(qdev, rx_status, KERN_DEBUG, qdev->ndev,
  1707. "%d bytes of headers & data in chain of large.\n",
  1708. length);
  1709. skb = sbq_desc->p.skb;
  1710. sbq_desc->p.skb = NULL;
  1711. skb_reserve(skb, NET_IP_ALIGN);
  1712. }
  1713. while (length > 0) {
  1714. lbq_desc = ql_get_curr_lchunk(qdev, rx_ring);
  1715. size = (length < rx_ring->lbq_buf_size) ? length :
  1716. rx_ring->lbq_buf_size;
  1717. netif_printk(qdev, rx_status, KERN_DEBUG, qdev->ndev,
  1718. "Adding page %d to skb for %d bytes.\n",
  1719. i, size);
  1720. skb_fill_page_desc(skb, i,
  1721. lbq_desc->p.pg_chunk.page,
  1722. lbq_desc->p.pg_chunk.offset,
  1723. size);
  1724. skb->len += size;
  1725. skb->data_len += size;
  1726. skb->truesize += size;
  1727. length -= size;
  1728. i++;
  1729. }
  1730. __pskb_pull_tail(skb, (ib_mac_rsp->flags2 & IB_MAC_IOCB_RSP_V) ?
  1731. VLAN_ETH_HLEN : ETH_HLEN);
  1732. }
  1733. return skb;
  1734. }
  1735. /* Process an inbound completion from an rx ring. */
  1736. static void ql_process_mac_split_rx_intr(struct ql_adapter *qdev,
  1737. struct rx_ring *rx_ring,
  1738. struct ib_mac_iocb_rsp *ib_mac_rsp,
  1739. u16 vlan_id)
  1740. {
  1741. struct net_device *ndev = qdev->ndev;
  1742. struct sk_buff *skb = NULL;
  1743. QL_DUMP_IB_MAC_RSP(ib_mac_rsp);
  1744. skb = ql_build_rx_skb(qdev, rx_ring, ib_mac_rsp);
  1745. if (unlikely(!skb)) {
  1746. netif_printk(qdev, rx_status, KERN_DEBUG, qdev->ndev,
  1747. "No skb available, drop packet.\n");
  1748. rx_ring->rx_dropped++;
  1749. return;
  1750. }
  1751. /* The max framesize filter on this chip is set higher than
  1752. * MTU since FCoE uses 2k frames.
  1753. */
  1754. if (skb->len > ndev->mtu + ETH_HLEN) {
  1755. dev_kfree_skb_any(skb);
  1756. rx_ring->rx_dropped++;
  1757. return;
  1758. }
  1759. /* loopback self test for ethtool */
  1760. if (test_bit(QL_SELFTEST, &qdev->flags)) {
  1761. ql_check_lb_frame(qdev, skb);
  1762. dev_kfree_skb_any(skb);
  1763. return;
  1764. }
  1765. prefetch(skb->data);
  1766. if (ib_mac_rsp->flags1 & IB_MAC_IOCB_RSP_M_MASK) {
  1767. netif_printk(qdev, rx_status, KERN_DEBUG, qdev->ndev, "%s Multicast.\n",
  1768. (ib_mac_rsp->flags1 & IB_MAC_IOCB_RSP_M_MASK) ==
  1769. IB_MAC_IOCB_RSP_M_HASH ? "Hash" :
  1770. (ib_mac_rsp->flags1 & IB_MAC_IOCB_RSP_M_MASK) ==
  1771. IB_MAC_IOCB_RSP_M_REG ? "Registered" :
  1772. (ib_mac_rsp->flags1 & IB_MAC_IOCB_RSP_M_MASK) ==
  1773. IB_MAC_IOCB_RSP_M_PROM ? "Promiscuous" : "");
  1774. rx_ring->rx_multicast++;
  1775. }
  1776. if (ib_mac_rsp->flags2 & IB_MAC_IOCB_RSP_P) {
  1777. netif_printk(qdev, rx_status, KERN_DEBUG, qdev->ndev,
  1778. "Promiscuous Packet.\n");
  1779. }
  1780. skb->protocol = eth_type_trans(skb, ndev);
  1781. skb_checksum_none_assert(skb);
  1782. /* If rx checksum is on, and there are no
  1783. * csum or frame errors.
  1784. */
  1785. if ((ndev->features & NETIF_F_RXCSUM) &&
  1786. !(ib_mac_rsp->flags1 & IB_MAC_CSUM_ERR_MASK)) {
  1787. /* TCP frame. */
  1788. if (ib_mac_rsp->flags2 & IB_MAC_IOCB_RSP_T) {
  1789. netif_printk(qdev, rx_status, KERN_DEBUG, qdev->ndev,
  1790. "TCP checksum done!\n");
  1791. skb->ip_summed = CHECKSUM_UNNECESSARY;
  1792. } else if ((ib_mac_rsp->flags2 & IB_MAC_IOCB_RSP_U) &&
  1793. (ib_mac_rsp->flags3 & IB_MAC_IOCB_RSP_V4)) {
  1794. /* Unfragmented ipv4 UDP frame. */
  1795. struct iphdr *iph = (struct iphdr *) skb->data;
  1796. if (!(iph->frag_off &
  1797. htons(IP_MF|IP_OFFSET))) {
  1798. skb->ip_summed = CHECKSUM_UNNECESSARY;
  1799. netif_printk(qdev, rx_status, KERN_DEBUG, qdev->ndev,
  1800. "TCP checksum done!\n");
  1801. }
  1802. }
  1803. }
  1804. rx_ring->rx_packets++;
  1805. rx_ring->rx_bytes += skb->len;
  1806. skb_record_rx_queue(skb, rx_ring->cq_id);
  1807. if ((ib_mac_rsp->flags2 & IB_MAC_IOCB_RSP_V) && (vlan_id != 0))
  1808. __vlan_hwaccel_put_tag(skb, htons(ETH_P_8021Q), vlan_id);
  1809. if (skb->ip_summed == CHECKSUM_UNNECESSARY)
  1810. napi_gro_receive(&rx_ring->napi, skb);
  1811. else
  1812. netif_receive_skb(skb);
  1813. }
  1814. /* Process an inbound completion from an rx ring. */
  1815. static unsigned long ql_process_mac_rx_intr(struct ql_adapter *qdev,
  1816. struct rx_ring *rx_ring,
  1817. struct ib_mac_iocb_rsp *ib_mac_rsp)
  1818. {
  1819. u32 length = le32_to_cpu(ib_mac_rsp->data_len);
  1820. u16 vlan_id = (ib_mac_rsp->flags2 & IB_MAC_IOCB_RSP_V) ?
  1821. ((le16_to_cpu(ib_mac_rsp->vlan_id) &
  1822. IB_MAC_IOCB_RSP_VLAN_MASK)) : 0xffff;
  1823. QL_DUMP_IB_MAC_RSP(ib_mac_rsp);
  1824. /* Frame error, so drop the packet. */
  1825. if (ib_mac_rsp->flags2 & IB_MAC_IOCB_RSP_ERR_MASK) {
  1826. ql_categorize_rx_err(qdev, ib_mac_rsp->flags2);
  1827. return (unsigned long)length;
  1828. }
  1829. if (ib_mac_rsp->flags4 & IB_MAC_IOCB_RSP_HV) {
  1830. /* The data and headers are split into
  1831. * separate buffers.
  1832. */
  1833. ql_process_mac_split_rx_intr(qdev, rx_ring, ib_mac_rsp,
  1834. vlan_id);
  1835. } else if (ib_mac_rsp->flags3 & IB_MAC_IOCB_RSP_DS) {
  1836. /* The data fit in a single small buffer.
  1837. * Allocate a new skb, copy the data and
  1838. * return the buffer to the free pool.
  1839. */
  1840. ql_process_mac_rx_skb(qdev, rx_ring, ib_mac_rsp,
  1841. length, vlan_id);
  1842. } else if ((ib_mac_rsp->flags3 & IB_MAC_IOCB_RSP_DL) &&
  1843. !(ib_mac_rsp->flags1 & IB_MAC_CSUM_ERR_MASK) &&
  1844. (ib_mac_rsp->flags2 & IB_MAC_IOCB_RSP_T)) {
  1845. /* TCP packet in a page chunk that's been checksummed.
  1846. * Tack it on to our GRO skb and let it go.
  1847. */
  1848. ql_process_mac_rx_gro_page(qdev, rx_ring, ib_mac_rsp,
  1849. length, vlan_id);
  1850. } else if (ib_mac_rsp->flags3 & IB_MAC_IOCB_RSP_DL) {
  1851. /* Non-TCP packet in a page chunk. Allocate an
  1852. * skb, tack it on frags, and send it up.
  1853. */
  1854. ql_process_mac_rx_page(qdev, rx_ring, ib_mac_rsp,
  1855. length, vlan_id);
  1856. } else {
  1857. /* Non-TCP/UDP large frames that span multiple buffers
  1858. * can be processed corrrectly by the split frame logic.
  1859. */
  1860. ql_process_mac_split_rx_intr(qdev, rx_ring, ib_mac_rsp,
  1861. vlan_id);
  1862. }
  1863. return (unsigned long)length;
  1864. }
  1865. /* Process an outbound completion from an rx ring. */
  1866. static void ql_process_mac_tx_intr(struct ql_adapter *qdev,
  1867. struct ob_mac_iocb_rsp *mac_rsp)
  1868. {
  1869. struct tx_ring *tx_ring;
  1870. struct tx_ring_desc *tx_ring_desc;
  1871. QL_DUMP_OB_MAC_RSP(mac_rsp);
  1872. tx_ring = &qdev->tx_ring[mac_rsp->txq_idx];
  1873. tx_ring_desc = &tx_ring->q[mac_rsp->tid];
  1874. ql_unmap_send(qdev, tx_ring_desc, tx_ring_desc->map_cnt);
  1875. tx_ring->tx_bytes += (tx_ring_desc->skb)->len;
  1876. tx_ring->tx_packets++;
  1877. dev_kfree_skb(tx_ring_desc->skb);
  1878. tx_ring_desc->skb = NULL;
  1879. if (unlikely(mac_rsp->flags1 & (OB_MAC_IOCB_RSP_E |
  1880. OB_MAC_IOCB_RSP_S |
  1881. OB_MAC_IOCB_RSP_L |
  1882. OB_MAC_IOCB_RSP_P | OB_MAC_IOCB_RSP_B))) {
  1883. if (mac_rsp->flags1 & OB_MAC_IOCB_RSP_E) {
  1884. netif_warn(qdev, tx_done, qdev->ndev,
  1885. "Total descriptor length did not match transfer length.\n");
  1886. }
  1887. if (mac_rsp->flags1 & OB_MAC_IOCB_RSP_S) {
  1888. netif_warn(qdev, tx_done, qdev->ndev,
  1889. "Frame too short to be valid, not sent.\n");
  1890. }
  1891. if (mac_rsp->flags1 & OB_MAC_IOCB_RSP_L) {
  1892. netif_warn(qdev, tx_done, qdev->ndev,
  1893. "Frame too long, but sent anyway.\n");
  1894. }
  1895. if (mac_rsp->flags1 & OB_MAC_IOCB_RSP_B) {
  1896. netif_warn(qdev, tx_done, qdev->ndev,
  1897. "PCI backplane error. Frame not sent.\n");
  1898. }
  1899. }
  1900. atomic_inc(&tx_ring->tx_count);
  1901. }
  1902. /* Fire up a handler to reset the MPI processor. */
  1903. void ql_queue_fw_error(struct ql_adapter *qdev)
  1904. {
  1905. ql_link_off(qdev);
  1906. queue_delayed_work(qdev->workqueue, &qdev->mpi_reset_work, 0);
  1907. }
  1908. void ql_queue_asic_error(struct ql_adapter *qdev)
  1909. {
  1910. ql_link_off(qdev);
  1911. ql_disable_interrupts(qdev);
  1912. /* Clear adapter up bit to signal the recovery
  1913. * process that it shouldn't kill the reset worker
  1914. * thread
  1915. */
  1916. clear_bit(QL_ADAPTER_UP, &qdev->flags);
  1917. /* Set asic recovery bit to indicate reset process that we are
  1918. * in fatal error recovery process rather than normal close
  1919. */
  1920. set_bit(QL_ASIC_RECOVERY, &qdev->flags);
  1921. queue_delayed_work(qdev->workqueue, &qdev->asic_reset_work, 0);
  1922. }
  1923. static void ql_process_chip_ae_intr(struct ql_adapter *qdev,
  1924. struct ib_ae_iocb_rsp *ib_ae_rsp)
  1925. {
  1926. switch (ib_ae_rsp->event) {
  1927. case MGMT_ERR_EVENT:
  1928. netif_err(qdev, rx_err, qdev->ndev,
  1929. "Management Processor Fatal Error.\n");
  1930. ql_queue_fw_error(qdev);
  1931. return;
  1932. case CAM_LOOKUP_ERR_EVENT:
  1933. netdev_err(qdev->ndev, "Multiple CAM hits lookup occurred.\n");
  1934. netdev_err(qdev->ndev, "This event shouldn't occur.\n");
  1935. ql_queue_asic_error(qdev);
  1936. return;
  1937. case SOFT_ECC_ERROR_EVENT:
  1938. netdev_err(qdev->ndev, "Soft ECC error detected.\n");
  1939. ql_queue_asic_error(qdev);
  1940. break;
  1941. case PCI_ERR_ANON_BUF_RD:
  1942. netdev_err(qdev->ndev, "PCI error occurred when reading "
  1943. "anonymous buffers from rx_ring %d.\n",
  1944. ib_ae_rsp->q_id);
  1945. ql_queue_asic_error(qdev);
  1946. break;
  1947. default:
  1948. netif_err(qdev, drv, qdev->ndev, "Unexpected event %d.\n",
  1949. ib_ae_rsp->event);
  1950. ql_queue_asic_error(qdev);
  1951. break;
  1952. }
  1953. }
  1954. static int ql_clean_outbound_rx_ring(struct rx_ring *rx_ring)
  1955. {
  1956. struct ql_adapter *qdev = rx_ring->qdev;
  1957. u32 prod = ql_read_sh_reg(rx_ring->prod_idx_sh_reg);
  1958. struct ob_mac_iocb_rsp *net_rsp = NULL;
  1959. int count = 0;
  1960. struct tx_ring *tx_ring;
  1961. /* While there are entries in the completion queue. */
  1962. while (prod != rx_ring->cnsmr_idx) {
  1963. netif_printk(qdev, rx_status, KERN_DEBUG, qdev->ndev,
  1964. "cq_id = %d, prod = %d, cnsmr = %d.\n.",
  1965. rx_ring->cq_id, prod, rx_ring->cnsmr_idx);
  1966. net_rsp = (struct ob_mac_iocb_rsp *)rx_ring->curr_entry;
  1967. rmb();
  1968. switch (net_rsp->opcode) {
  1969. case OPCODE_OB_MAC_TSO_IOCB:
  1970. case OPCODE_OB_MAC_IOCB:
  1971. ql_process_mac_tx_intr(qdev, net_rsp);
  1972. break;
  1973. default:
  1974. netif_printk(qdev, rx_status, KERN_DEBUG, qdev->ndev,
  1975. "Hit default case, not handled! dropping the packet, opcode = %x.\n",
  1976. net_rsp->opcode);
  1977. }
  1978. count++;
  1979. ql_update_cq(rx_ring);
  1980. prod = ql_read_sh_reg(rx_ring->prod_idx_sh_reg);
  1981. }
  1982. if (!net_rsp)
  1983. return 0;
  1984. ql_write_cq_idx(rx_ring);
  1985. tx_ring = &qdev->tx_ring[net_rsp->txq_idx];
  1986. if (__netif_subqueue_stopped(qdev->ndev, tx_ring->wq_id)) {
  1987. if ((atomic_read(&tx_ring->tx_count) > (tx_ring->wq_len / 4)))
  1988. /*
  1989. * The queue got stopped because the tx_ring was full.
  1990. * Wake it up, because it's now at least 25% empty.
  1991. */
  1992. netif_wake_subqueue(qdev->ndev, tx_ring->wq_id);
  1993. }
  1994. return count;
  1995. }
  1996. static int ql_clean_inbound_rx_ring(struct rx_ring *rx_ring, int budget)
  1997. {
  1998. struct ql_adapter *qdev = rx_ring->qdev;
  1999. u32 prod = ql_read_sh_reg(rx_ring->prod_idx_sh_reg);
  2000. struct ql_net_rsp_iocb *net_rsp;
  2001. int count = 0;
  2002. /* While there are entries in the completion queue. */
  2003. while (prod != rx_ring->cnsmr_idx) {
  2004. netif_printk(qdev, rx_status, KERN_DEBUG, qdev->ndev,
  2005. "cq_id = %d, prod = %d, cnsmr = %d.\n.",
  2006. rx_ring->cq_id, prod, rx_ring->cnsmr_idx);
  2007. net_rsp = rx_ring->curr_entry;
  2008. rmb();
  2009. switch (net_rsp->opcode) {
  2010. case OPCODE_IB_MAC_IOCB:
  2011. ql_process_mac_rx_intr(qdev, rx_ring,
  2012. (struct ib_mac_iocb_rsp *)
  2013. net_rsp);
  2014. break;
  2015. case OPCODE_IB_AE_IOCB:
  2016. ql_process_chip_ae_intr(qdev, (struct ib_ae_iocb_rsp *)
  2017. net_rsp);
  2018. break;
  2019. default:
  2020. netif_printk(qdev, rx_status, KERN_DEBUG, qdev->ndev,
  2021. "Hit default case, not handled! dropping the packet, opcode = %x.\n",
  2022. net_rsp->opcode);
  2023. break;
  2024. }
  2025. count++;
  2026. ql_update_cq(rx_ring);
  2027. prod = ql_read_sh_reg(rx_ring->prod_idx_sh_reg);
  2028. if (count == budget)
  2029. break;
  2030. }
  2031. ql_update_buffer_queues(qdev, rx_ring);
  2032. ql_write_cq_idx(rx_ring);
  2033. return count;
  2034. }
  2035. static int ql_napi_poll_msix(struct napi_struct *napi, int budget)
  2036. {
  2037. struct rx_ring *rx_ring = container_of(napi, struct rx_ring, napi);
  2038. struct ql_adapter *qdev = rx_ring->qdev;
  2039. struct rx_ring *trx_ring;
  2040. int i, work_done = 0;
  2041. struct intr_context *ctx = &qdev->intr_context[rx_ring->cq_id];
  2042. netif_printk(qdev, rx_status, KERN_DEBUG, qdev->ndev,
  2043. "Enter, NAPI POLL cq_id = %d.\n", rx_ring->cq_id);
  2044. /* Service the TX rings first. They start
  2045. * right after the RSS rings. */
  2046. for (i = qdev->rss_ring_count; i < qdev->rx_ring_count; i++) {
  2047. trx_ring = &qdev->rx_ring[i];
  2048. /* If this TX completion ring belongs to this vector and
  2049. * it's not empty then service it.
  2050. */
  2051. if ((ctx->irq_mask & (1 << trx_ring->cq_id)) &&
  2052. (ql_read_sh_reg(trx_ring->prod_idx_sh_reg) !=
  2053. trx_ring->cnsmr_idx)) {
  2054. netif_printk(qdev, intr, KERN_DEBUG, qdev->ndev,
  2055. "%s: Servicing TX completion ring %d.\n",
  2056. __func__, trx_ring->cq_id);
  2057. ql_clean_outbound_rx_ring(trx_ring);
  2058. }
  2059. }
  2060. /*
  2061. * Now service the RSS ring if it's active.
  2062. */
  2063. if (ql_read_sh_reg(rx_ring->prod_idx_sh_reg) !=
  2064. rx_ring->cnsmr_idx) {
  2065. netif_printk(qdev, intr, KERN_DEBUG, qdev->ndev,
  2066. "%s: Servicing RX completion ring %d.\n",
  2067. __func__, rx_ring->cq_id);
  2068. work_done = ql_clean_inbound_rx_ring(rx_ring, budget);
  2069. }
  2070. if (work_done < budget) {
  2071. napi_complete(napi);
  2072. ql_enable_completion_interrupt(qdev, rx_ring->irq);
  2073. }
  2074. return work_done;
  2075. }
  2076. static void qlge_vlan_mode(struct net_device *ndev, netdev_features_t features)
  2077. {
  2078. struct ql_adapter *qdev = netdev_priv(ndev);
  2079. if (features & NETIF_F_HW_VLAN_CTAG_RX) {
  2080. ql_write32(qdev, NIC_RCV_CFG, NIC_RCV_CFG_VLAN_MASK |
  2081. NIC_RCV_CFG_VLAN_MATCH_AND_NON);
  2082. } else {
  2083. ql_write32(qdev, NIC_RCV_CFG, NIC_RCV_CFG_VLAN_MASK);
  2084. }
  2085. }
  2086. static netdev_features_t qlge_fix_features(struct net_device *ndev,
  2087. netdev_features_t features)
  2088. {
  2089. /*
  2090. * Since there is no support for separate rx/tx vlan accel
  2091. * enable/disable make sure tx flag is always in same state as rx.
  2092. */
  2093. if (features & NETIF_F_HW_VLAN_CTAG_RX)
  2094. features |= NETIF_F_HW_VLAN_CTAG_TX;
  2095. else
  2096. features &= ~NETIF_F_HW_VLAN_CTAG_TX;
  2097. return features;
  2098. }
  2099. static int qlge_set_features(struct net_device *ndev,
  2100. netdev_features_t features)
  2101. {
  2102. netdev_features_t changed = ndev->features ^ features;
  2103. if (changed & NETIF_F_HW_VLAN_CTAG_RX)
  2104. qlge_vlan_mode(ndev, features);
  2105. return 0;
  2106. }
  2107. static int __qlge_vlan_rx_add_vid(struct ql_adapter *qdev, u16 vid)
  2108. {
  2109. u32 enable_bit = MAC_ADDR_E;
  2110. int err;
  2111. err = ql_set_mac_addr_reg(qdev, (u8 *) &enable_bit,
  2112. MAC_ADDR_TYPE_VLAN, vid);
  2113. if (err)
  2114. netif_err(qdev, ifup, qdev->ndev,
  2115. "Failed to init vlan address.\n");
  2116. return err;
  2117. }
  2118. static int qlge_vlan_rx_add_vid(struct net_device *ndev, __be16 proto, u16 vid)
  2119. {
  2120. struct ql_adapter *qdev = netdev_priv(ndev);
  2121. int status;
  2122. int err;
  2123. status = ql_sem_spinlock(qdev, SEM_MAC_ADDR_MASK);
  2124. if (status)
  2125. return status;
  2126. err = __qlge_vlan_rx_add_vid(qdev, vid);
  2127. set_bit(vid, qdev->active_vlans);
  2128. ql_sem_unlock(qdev, SEM_MAC_ADDR_MASK);
  2129. return err;
  2130. }
  2131. static int __qlge_vlan_rx_kill_vid(struct ql_adapter *qdev, u16 vid)
  2132. {
  2133. u32 enable_bit = 0;
  2134. int err;
  2135. err = ql_set_mac_addr_reg(qdev, (u8 *) &enable_bit,
  2136. MAC_ADDR_TYPE_VLAN, vid);
  2137. if (err)
  2138. netif_err(qdev, ifup, qdev->ndev,
  2139. "Failed to clear vlan address.\n");
  2140. return err;
  2141. }
  2142. static int qlge_vlan_rx_kill_vid(struct net_device *ndev, __be16 proto, u16 vid)
  2143. {
  2144. struct ql_adapter *qdev = netdev_priv(ndev);
  2145. int status;
  2146. int err;
  2147. status = ql_sem_spinlock(qdev, SEM_MAC_ADDR_MASK);
  2148. if (status)
  2149. return status;
  2150. err = __qlge_vlan_rx_kill_vid(qdev, vid);
  2151. clear_bit(vid, qdev->active_vlans);
  2152. ql_sem_unlock(qdev, SEM_MAC_ADDR_MASK);
  2153. return err;
  2154. }
  2155. static void qlge_restore_vlan(struct ql_adapter *qdev)
  2156. {
  2157. int status;
  2158. u16 vid;
  2159. status = ql_sem_spinlock(qdev, SEM_MAC_ADDR_MASK);
  2160. if (status)
  2161. return;
  2162. for_each_set_bit(vid, qdev->active_vlans, VLAN_N_VID)
  2163. __qlge_vlan_rx_add_vid(qdev, vid);
  2164. ql_sem_unlock(qdev, SEM_MAC_ADDR_MASK);
  2165. }
  2166. /* MSI-X Multiple Vector Interrupt Handler for inbound completions. */
  2167. static irqreturn_t qlge_msix_rx_isr(int irq, void *dev_id)
  2168. {
  2169. struct rx_ring *rx_ring = dev_id;
  2170. napi_schedule(&rx_ring->napi);
  2171. return IRQ_HANDLED;
  2172. }
  2173. /* This handles a fatal error, MPI activity, and the default
  2174. * rx_ring in an MSI-X multiple vector environment.
  2175. * In MSI/Legacy environment it also process the rest of
  2176. * the rx_rings.
  2177. */
  2178. static irqreturn_t qlge_isr(int irq, void *dev_id)
  2179. {
  2180. struct rx_ring *rx_ring = dev_id;
  2181. struct ql_adapter *qdev = rx_ring->qdev;
  2182. struct intr_context *intr_context = &qdev->intr_context[0];
  2183. u32 var;
  2184. int work_done = 0;
  2185. spin_lock(&qdev->hw_lock);
  2186. if (atomic_read(&qdev->intr_context[0].irq_cnt)) {
  2187. netif_printk(qdev, intr, KERN_DEBUG, qdev->ndev,
  2188. "Shared Interrupt, Not ours!\n");
  2189. spin_unlock(&qdev->hw_lock);
  2190. return IRQ_NONE;
  2191. }
  2192. spin_unlock(&qdev->hw_lock);
  2193. var = ql_disable_completion_interrupt(qdev, intr_context->intr);
  2194. /*
  2195. * Check for fatal error.
  2196. */
  2197. if (var & STS_FE) {
  2198. ql_queue_asic_error(qdev);
  2199. netdev_err(qdev->ndev, "Got fatal error, STS = %x.\n", var);
  2200. var = ql_read32(qdev, ERR_STS);
  2201. netdev_err(qdev->ndev, "Resetting chip. "
  2202. "Error Status Register = 0x%x\n", var);
  2203. return IRQ_HANDLED;
  2204. }
  2205. /*
  2206. * Check MPI processor activity.
  2207. */
  2208. if ((var & STS_PI) &&
  2209. (ql_read32(qdev, INTR_MASK) & INTR_MASK_PI)) {
  2210. /*
  2211. * We've got an async event or mailbox completion.
  2212. * Handle it and clear the source of the interrupt.
  2213. */
  2214. netif_err(qdev, intr, qdev->ndev,
  2215. "Got MPI processor interrupt.\n");
  2216. ql_disable_completion_interrupt(qdev, intr_context->intr);
  2217. ql_write32(qdev, INTR_MASK, (INTR_MASK_PI << 16));
  2218. queue_delayed_work_on(smp_processor_id(),
  2219. qdev->workqueue, &qdev->mpi_work, 0);
  2220. work_done++;
  2221. }
  2222. /*
  2223. * Get the bit-mask that shows the active queues for this
  2224. * pass. Compare it to the queues that this irq services
  2225. * and call napi if there's a match.
  2226. */
  2227. var = ql_read32(qdev, ISR1);
  2228. if (var & intr_context->irq_mask) {
  2229. netif_info(qdev, intr, qdev->ndev,
  2230. "Waking handler for rx_ring[0].\n");
  2231. ql_disable_completion_interrupt(qdev, intr_context->intr);
  2232. napi_schedule(&rx_ring->napi);
  2233. work_done++;
  2234. }
  2235. ql_enable_completion_interrupt(qdev, intr_context->intr);
  2236. return work_done ? IRQ_HANDLED : IRQ_NONE;
  2237. }
  2238. static int ql_tso(struct sk_buff *skb, struct ob_mac_tso_iocb_req *mac_iocb_ptr)
  2239. {
  2240. if (skb_is_gso(skb)) {
  2241. int err;
  2242. if (skb_header_cloned(skb)) {
  2243. err = pskb_expand_head(skb, 0, 0, GFP_ATOMIC);
  2244. if (err)
  2245. return err;
  2246. }
  2247. mac_iocb_ptr->opcode = OPCODE_OB_MAC_TSO_IOCB;
  2248. mac_iocb_ptr->flags3 |= OB_MAC_TSO_IOCB_IC;
  2249. mac_iocb_ptr->frame_len = cpu_to_le32((u32) skb->len);
  2250. mac_iocb_ptr->total_hdrs_len =
  2251. cpu_to_le16(skb_transport_offset(skb) + tcp_hdrlen(skb));
  2252. mac_iocb_ptr->net_trans_offset =
  2253. cpu_to_le16(skb_network_offset(skb) |
  2254. skb_transport_offset(skb)
  2255. << OB_MAC_TRANSPORT_HDR_SHIFT);
  2256. mac_iocb_ptr->mss = cpu_to_le16(skb_shinfo(skb)->gso_size);
  2257. mac_iocb_ptr->flags2 |= OB_MAC_TSO_IOCB_LSO;
  2258. if (likely(skb->protocol == htons(ETH_P_IP))) {
  2259. struct iphdr *iph = ip_hdr(skb);
  2260. iph->check = 0;
  2261. mac_iocb_ptr->flags1 |= OB_MAC_TSO_IOCB_IP4;
  2262. tcp_hdr(skb)->check = ~csum_tcpudp_magic(iph->saddr,
  2263. iph->daddr, 0,
  2264. IPPROTO_TCP,
  2265. 0);
  2266. } else if (skb->protocol == htons(ETH_P_IPV6)) {
  2267. mac_iocb_ptr->flags1 |= OB_MAC_TSO_IOCB_IP6;
  2268. tcp_hdr(skb)->check =
  2269. ~csum_ipv6_magic(&ipv6_hdr(skb)->saddr,
  2270. &ipv6_hdr(skb)->daddr,
  2271. 0, IPPROTO_TCP, 0);
  2272. }
  2273. return 1;
  2274. }
  2275. return 0;
  2276. }
  2277. static void ql_hw_csum_setup(struct sk_buff *skb,
  2278. struct ob_mac_tso_iocb_req *mac_iocb_ptr)
  2279. {
  2280. int len;
  2281. struct iphdr *iph = ip_hdr(skb);
  2282. __sum16 *check;
  2283. mac_iocb_ptr->opcode = OPCODE_OB_MAC_TSO_IOCB;
  2284. mac_iocb_ptr->frame_len = cpu_to_le32((u32) skb->len);
  2285. mac_iocb_ptr->net_trans_offset =
  2286. cpu_to_le16(skb_network_offset(skb) |
  2287. skb_transport_offset(skb) << OB_MAC_TRANSPORT_HDR_SHIFT);
  2288. mac_iocb_ptr->flags1 |= OB_MAC_TSO_IOCB_IP4;
  2289. len = (ntohs(iph->tot_len) - (iph->ihl << 2));
  2290. if (likely(iph->protocol == IPPROTO_TCP)) {
  2291. check = &(tcp_hdr(skb)->check);
  2292. mac_iocb_ptr->flags2 |= OB_MAC_TSO_IOCB_TC;
  2293. mac_iocb_ptr->total_hdrs_len =
  2294. cpu_to_le16(skb_transport_offset(skb) +
  2295. (tcp_hdr(skb)->doff << 2));
  2296. } else {
  2297. check = &(udp_hdr(skb)->check);
  2298. mac_iocb_ptr->flags2 |= OB_MAC_TSO_IOCB_UC;
  2299. mac_iocb_ptr->total_hdrs_len =
  2300. cpu_to_le16(skb_transport_offset(skb) +
  2301. sizeof(struct udphdr));
  2302. }
  2303. *check = ~csum_tcpudp_magic(iph->saddr,
  2304. iph->daddr, len, iph->protocol, 0);
  2305. }
  2306. static netdev_tx_t qlge_send(struct sk_buff *skb, struct net_device *ndev)
  2307. {
  2308. struct tx_ring_desc *tx_ring_desc;
  2309. struct ob_mac_iocb_req *mac_iocb_ptr;
  2310. struct ql_adapter *qdev = netdev_priv(ndev);
  2311. int tso;
  2312. struct tx_ring *tx_ring;
  2313. u32 tx_ring_idx = (u32) skb->queue_mapping;
  2314. tx_ring = &qdev->tx_ring[tx_ring_idx];
  2315. if (skb_padto(skb, ETH_ZLEN))
  2316. return NETDEV_TX_OK;
  2317. if (unlikely(atomic_read(&tx_ring->tx_count) < 2)) {
  2318. netif_info(qdev, tx_queued, qdev->ndev,
  2319. "%s: BUG! shutting down tx queue %d due to lack of resources.\n",
  2320. __func__, tx_ring_idx);
  2321. netif_stop_subqueue(ndev, tx_ring->wq_id);
  2322. tx_ring->tx_errors++;
  2323. return NETDEV_TX_BUSY;
  2324. }
  2325. tx_ring_desc = &tx_ring->q[tx_ring->prod_idx];
  2326. mac_iocb_ptr = tx_ring_desc->queue_entry;
  2327. memset((void *)mac_iocb_ptr, 0, sizeof(*mac_iocb_ptr));
  2328. mac_iocb_ptr->opcode = OPCODE_OB_MAC_IOCB;
  2329. mac_iocb_ptr->tid = tx_ring_desc->index;
  2330. /* We use the upper 32-bits to store the tx queue for this IO.
  2331. * When we get the completion we can use it to establish the context.
  2332. */
  2333. mac_iocb_ptr->txq_idx = tx_ring_idx;
  2334. tx_ring_desc->skb = skb;
  2335. mac_iocb_ptr->frame_len = cpu_to_le16((u16) skb->len);
  2336. if (vlan_tx_tag_present(skb)) {
  2337. netif_printk(qdev, tx_queued, KERN_DEBUG, qdev->ndev,
  2338. "Adding a vlan tag %d.\n", vlan_tx_tag_get(skb));
  2339. mac_iocb_ptr->flags3 |= OB_MAC_IOCB_V;
  2340. mac_iocb_ptr->vlan_tci = cpu_to_le16(vlan_tx_tag_get(skb));
  2341. }
  2342. tso = ql_tso(skb, (struct ob_mac_tso_iocb_req *)mac_iocb_ptr);
  2343. if (tso < 0) {
  2344. dev_kfree_skb_any(skb);
  2345. return NETDEV_TX_OK;
  2346. } else if (unlikely(!tso) && (skb->ip_summed == CHECKSUM_PARTIAL)) {
  2347. ql_hw_csum_setup(skb,
  2348. (struct ob_mac_tso_iocb_req *)mac_iocb_ptr);
  2349. }
  2350. if (ql_map_send(qdev, mac_iocb_ptr, skb, tx_ring_desc) !=
  2351. NETDEV_TX_OK) {
  2352. netif_err(qdev, tx_queued, qdev->ndev,
  2353. "Could not map the segments.\n");
  2354. tx_ring->tx_errors++;
  2355. return NETDEV_TX_BUSY;
  2356. }
  2357. QL_DUMP_OB_MAC_IOCB(mac_iocb_ptr);
  2358. tx_ring->prod_idx++;
  2359. if (tx_ring->prod_idx == tx_ring->wq_len)
  2360. tx_ring->prod_idx = 0;
  2361. wmb();
  2362. ql_write_db_reg(tx_ring->prod_idx, tx_ring->prod_idx_db_reg);
  2363. netif_printk(qdev, tx_queued, KERN_DEBUG, qdev->ndev,
  2364. "tx queued, slot %d, len %d\n",
  2365. tx_ring->prod_idx, skb->len);
  2366. atomic_dec(&tx_ring->tx_count);
  2367. if (unlikely(atomic_read(&tx_ring->tx_count) < 2)) {
  2368. netif_stop_subqueue(ndev, tx_ring->wq_id);
  2369. if ((atomic_read(&tx_ring->tx_count) > (tx_ring->wq_len / 4)))
  2370. /*
  2371. * The queue got stopped because the tx_ring was full.
  2372. * Wake it up, because it's now at least 25% empty.
  2373. */
  2374. netif_wake_subqueue(qdev->ndev, tx_ring->wq_id);
  2375. }
  2376. return NETDEV_TX_OK;
  2377. }
  2378. static void ql_free_shadow_space(struct ql_adapter *qdev)
  2379. {
  2380. if (qdev->rx_ring_shadow_reg_area) {
  2381. pci_free_consistent(qdev->pdev,
  2382. PAGE_SIZE,
  2383. qdev->rx_ring_shadow_reg_area,
  2384. qdev->rx_ring_shadow_reg_dma);
  2385. qdev->rx_ring_shadow_reg_area = NULL;
  2386. }
  2387. if (qdev->tx_ring_shadow_reg_area) {
  2388. pci_free_consistent(qdev->pdev,
  2389. PAGE_SIZE,
  2390. qdev->tx_ring_shadow_reg_area,
  2391. qdev->tx_ring_shadow_reg_dma);
  2392. qdev->tx_ring_shadow_reg_area = NULL;
  2393. }
  2394. }
  2395. static int ql_alloc_shadow_space(struct ql_adapter *qdev)
  2396. {
  2397. qdev->rx_ring_shadow_reg_area =
  2398. pci_alloc_consistent(qdev->pdev,
  2399. PAGE_SIZE, &qdev->rx_ring_shadow_reg_dma);
  2400. if (qdev->rx_ring_shadow_reg_area == NULL) {
  2401. netif_err(qdev, ifup, qdev->ndev,
  2402. "Allocation of RX shadow space failed.\n");
  2403. return -ENOMEM;
  2404. }
  2405. memset(qdev->rx_ring_shadow_reg_area, 0, PAGE_SIZE);
  2406. qdev->tx_ring_shadow_reg_area =
  2407. pci_alloc_consistent(qdev->pdev, PAGE_SIZE,
  2408. &qdev->tx_ring_shadow_reg_dma);
  2409. if (qdev->tx_ring_shadow_reg_area == NULL) {
  2410. netif_err(qdev, ifup, qdev->ndev,
  2411. "Allocation of TX shadow space failed.\n");
  2412. goto err_wqp_sh_area;
  2413. }
  2414. memset(qdev->tx_ring_shadow_reg_area, 0, PAGE_SIZE);
  2415. return 0;
  2416. err_wqp_sh_area:
  2417. pci_free_consistent(qdev->pdev,
  2418. PAGE_SIZE,
  2419. qdev->rx_ring_shadow_reg_area,
  2420. qdev->rx_ring_shadow_reg_dma);
  2421. return -ENOMEM;
  2422. }
  2423. static void ql_init_tx_ring(struct ql_adapter *qdev, struct tx_ring *tx_ring)
  2424. {
  2425. struct tx_ring_desc *tx_ring_desc;
  2426. int i;
  2427. struct ob_mac_iocb_req *mac_iocb_ptr;
  2428. mac_iocb_ptr = tx_ring->wq_base;
  2429. tx_ring_desc = tx_ring->q;
  2430. for (i = 0; i < tx_ring->wq_len; i++) {
  2431. tx_ring_desc->index = i;
  2432. tx_ring_desc->skb = NULL;
  2433. tx_ring_desc->queue_entry = mac_iocb_ptr;
  2434. mac_iocb_ptr++;
  2435. tx_ring_desc++;
  2436. }
  2437. atomic_set(&tx_ring->tx_count, tx_ring->wq_len);
  2438. }
  2439. static void ql_free_tx_resources(struct ql_adapter *qdev,
  2440. struct tx_ring *tx_ring)
  2441. {
  2442. if (tx_ring->wq_base) {
  2443. pci_free_consistent(qdev->pdev, tx_ring->wq_size,
  2444. tx_ring->wq_base, tx_ring->wq_base_dma);
  2445. tx_ring->wq_base = NULL;
  2446. }
  2447. kfree(tx_ring->q);
  2448. tx_ring->q = NULL;
  2449. }
  2450. static int ql_alloc_tx_resources(struct ql_adapter *qdev,
  2451. struct tx_ring *tx_ring)
  2452. {
  2453. tx_ring->wq_base =
  2454. pci_alloc_consistent(qdev->pdev, tx_ring->wq_size,
  2455. &tx_ring->wq_base_dma);
  2456. if ((tx_ring->wq_base == NULL) ||
  2457. tx_ring->wq_base_dma & WQ_ADDR_ALIGN)
  2458. goto pci_alloc_err;
  2459. tx_ring->q =
  2460. kmalloc(tx_ring->wq_len * sizeof(struct tx_ring_desc), GFP_KERNEL);
  2461. if (tx_ring->q == NULL)
  2462. goto err;
  2463. return 0;
  2464. err:
  2465. pci_free_consistent(qdev->pdev, tx_ring->wq_size,
  2466. tx_ring->wq_base, tx_ring->wq_base_dma);
  2467. tx_ring->wq_base = NULL;
  2468. pci_alloc_err:
  2469. netif_err(qdev, ifup, qdev->ndev, "tx_ring alloc failed.\n");
  2470. return -ENOMEM;
  2471. }
  2472. static void ql_free_lbq_buffers(struct ql_adapter *qdev, struct rx_ring *rx_ring)
  2473. {
  2474. struct bq_desc *lbq_desc;
  2475. uint32_t curr_idx, clean_idx;
  2476. curr_idx = rx_ring->lbq_curr_idx;
  2477. clean_idx = rx_ring->lbq_clean_idx;
  2478. while (curr_idx != clean_idx) {
  2479. lbq_desc = &rx_ring->lbq[curr_idx];
  2480. if (lbq_desc->p.pg_chunk.last_flag) {
  2481. pci_unmap_page(qdev->pdev,
  2482. lbq_desc->p.pg_chunk.map,
  2483. ql_lbq_block_size(qdev),
  2484. PCI_DMA_FROMDEVICE);
  2485. lbq_desc->p.pg_chunk.last_flag = 0;
  2486. }
  2487. put_page(lbq_desc->p.pg_chunk.page);
  2488. lbq_desc->p.pg_chunk.page = NULL;
  2489. if (++curr_idx == rx_ring->lbq_len)
  2490. curr_idx = 0;
  2491. }
  2492. }
  2493. static void ql_free_sbq_buffers(struct ql_adapter *qdev, struct rx_ring *rx_ring)
  2494. {
  2495. int i;
  2496. struct bq_desc *sbq_desc;
  2497. for (i = 0; i < rx_ring->sbq_len; i++) {
  2498. sbq_desc = &rx_ring->sbq[i];
  2499. if (sbq_desc == NULL) {
  2500. netif_err(qdev, ifup, qdev->ndev,
  2501. "sbq_desc %d is NULL.\n", i);
  2502. return;
  2503. }
  2504. if (sbq_desc->p.skb) {
  2505. pci_unmap_single(qdev->pdev,
  2506. dma_unmap_addr(sbq_desc, mapaddr),
  2507. dma_unmap_len(sbq_desc, maplen),
  2508. PCI_DMA_FROMDEVICE);
  2509. dev_kfree_skb(sbq_desc->p.skb);
  2510. sbq_desc->p.skb = NULL;
  2511. }
  2512. }
  2513. }
  2514. /* Free all large and small rx buffers associated
  2515. * with the completion queues for this device.
  2516. */
  2517. static void ql_free_rx_buffers(struct ql_adapter *qdev)
  2518. {
  2519. int i;
  2520. struct rx_ring *rx_ring;
  2521. for (i = 0; i < qdev->rx_ring_count; i++) {
  2522. rx_ring = &qdev->rx_ring[i];
  2523. if (rx_ring->lbq)
  2524. ql_free_lbq_buffers(qdev, rx_ring);
  2525. if (rx_ring->sbq)
  2526. ql_free_sbq_buffers(qdev, rx_ring);
  2527. }
  2528. }
  2529. static void ql_alloc_rx_buffers(struct ql_adapter *qdev)
  2530. {
  2531. struct rx_ring *rx_ring;
  2532. int i;
  2533. for (i = 0; i < qdev->rx_ring_count; i++) {
  2534. rx_ring = &qdev->rx_ring[i];
  2535. if (rx_ring->type != TX_Q)
  2536. ql_update_buffer_queues(qdev, rx_ring);
  2537. }
  2538. }
  2539. static void ql_init_lbq_ring(struct ql_adapter *qdev,
  2540. struct rx_ring *rx_ring)
  2541. {
  2542. int i;
  2543. struct bq_desc *lbq_desc;
  2544. __le64 *bq = rx_ring->lbq_base;
  2545. memset(rx_ring->lbq, 0, rx_ring->lbq_len * sizeof(struct bq_desc));
  2546. for (i = 0; i < rx_ring->lbq_len; i++) {
  2547. lbq_desc = &rx_ring->lbq[i];
  2548. memset(lbq_desc, 0, sizeof(*lbq_desc));
  2549. lbq_desc->index = i;
  2550. lbq_desc->addr = bq;
  2551. bq++;
  2552. }
  2553. }
  2554. static void ql_init_sbq_ring(struct ql_adapter *qdev,
  2555. struct rx_ring *rx_ring)
  2556. {
  2557. int i;
  2558. struct bq_desc *sbq_desc;
  2559. __le64 *bq = rx_ring->sbq_base;
  2560. memset(rx_ring->sbq, 0, rx_ring->sbq_len * sizeof(struct bq_desc));
  2561. for (i = 0; i < rx_ring->sbq_len; i++) {
  2562. sbq_desc = &rx_ring->sbq[i];
  2563. memset(sbq_desc, 0, sizeof(*sbq_desc));
  2564. sbq_desc->index = i;
  2565. sbq_desc->addr = bq;
  2566. bq++;
  2567. }
  2568. }
  2569. static void ql_free_rx_resources(struct ql_adapter *qdev,
  2570. struct rx_ring *rx_ring)
  2571. {
  2572. /* Free the small buffer queue. */
  2573. if (rx_ring->sbq_base) {
  2574. pci_free_consistent(qdev->pdev,
  2575. rx_ring->sbq_size,
  2576. rx_ring->sbq_base, rx_ring->sbq_base_dma);
  2577. rx_ring->sbq_base = NULL;
  2578. }
  2579. /* Free the small buffer queue control blocks. */
  2580. kfree(rx_ring->sbq);
  2581. rx_ring->sbq = NULL;
  2582. /* Free the large buffer queue. */
  2583. if (rx_ring->lbq_base) {
  2584. pci_free_consistent(qdev->pdev,
  2585. rx_ring->lbq_size,
  2586. rx_ring->lbq_base, rx_ring->lbq_base_dma);
  2587. rx_ring->lbq_base = NULL;
  2588. }
  2589. /* Free the large buffer queue control blocks. */
  2590. kfree(rx_ring->lbq);
  2591. rx_ring->lbq = NULL;
  2592. /* Free the rx queue. */
  2593. if (rx_ring->cq_base) {
  2594. pci_free_consistent(qdev->pdev,
  2595. rx_ring->cq_size,
  2596. rx_ring->cq_base, rx_ring->cq_base_dma);
  2597. rx_ring->cq_base = NULL;
  2598. }
  2599. }
  2600. /* Allocate queues and buffers for this completions queue based
  2601. * on the values in the parameter structure. */
  2602. static int ql_alloc_rx_resources(struct ql_adapter *qdev,
  2603. struct rx_ring *rx_ring)
  2604. {
  2605. /*
  2606. * Allocate the completion queue for this rx_ring.
  2607. */
  2608. rx_ring->cq_base =
  2609. pci_alloc_consistent(qdev->pdev, rx_ring->cq_size,
  2610. &rx_ring->cq_base_dma);
  2611. if (rx_ring->cq_base == NULL) {
  2612. netif_err(qdev, ifup, qdev->ndev, "rx_ring alloc failed.\n");
  2613. return -ENOMEM;
  2614. }
  2615. if (rx_ring->sbq_len) {
  2616. /*
  2617. * Allocate small buffer queue.
  2618. */
  2619. rx_ring->sbq_base =
  2620. pci_alloc_consistent(qdev->pdev, rx_ring->sbq_size,
  2621. &rx_ring->sbq_base_dma);
  2622. if (rx_ring->sbq_base == NULL) {
  2623. netif_err(qdev, ifup, qdev->ndev,
  2624. "Small buffer queue allocation failed.\n");
  2625. goto err_mem;
  2626. }
  2627. /*
  2628. * Allocate small buffer queue control blocks.
  2629. */
  2630. rx_ring->sbq = kmalloc_array(rx_ring->sbq_len,
  2631. sizeof(struct bq_desc),
  2632. GFP_KERNEL);
  2633. if (rx_ring->sbq == NULL)
  2634. goto err_mem;
  2635. ql_init_sbq_ring(qdev, rx_ring);
  2636. }
  2637. if (rx_ring->lbq_len) {
  2638. /*
  2639. * Allocate large buffer queue.
  2640. */
  2641. rx_ring->lbq_base =
  2642. pci_alloc_consistent(qdev->pdev, rx_ring->lbq_size,
  2643. &rx_ring->lbq_base_dma);
  2644. if (rx_ring->lbq_base == NULL) {
  2645. netif_err(qdev, ifup, qdev->ndev,
  2646. "Large buffer queue allocation failed.\n");
  2647. goto err_mem;
  2648. }
  2649. /*
  2650. * Allocate large buffer queue control blocks.
  2651. */
  2652. rx_ring->lbq = kmalloc_array(rx_ring->lbq_len,
  2653. sizeof(struct bq_desc),
  2654. GFP_KERNEL);
  2655. if (rx_ring->lbq == NULL)
  2656. goto err_mem;
  2657. ql_init_lbq_ring(qdev, rx_ring);
  2658. }
  2659. return 0;
  2660. err_mem:
  2661. ql_free_rx_resources(qdev, rx_ring);
  2662. return -ENOMEM;
  2663. }
  2664. static void ql_tx_ring_clean(struct ql_adapter *qdev)
  2665. {
  2666. struct tx_ring *tx_ring;
  2667. struct tx_ring_desc *tx_ring_desc;
  2668. int i, j;
  2669. /*
  2670. * Loop through all queues and free
  2671. * any resources.
  2672. */
  2673. for (j = 0; j < qdev->tx_ring_count; j++) {
  2674. tx_ring = &qdev->tx_ring[j];
  2675. for (i = 0; i < tx_ring->wq_len; i++) {
  2676. tx_ring_desc = &tx_ring->q[i];
  2677. if (tx_ring_desc && tx_ring_desc->skb) {
  2678. netif_err(qdev, ifdown, qdev->ndev,
  2679. "Freeing lost SKB %p, from queue %d, index %d.\n",
  2680. tx_ring_desc->skb, j,
  2681. tx_ring_desc->index);
  2682. ql_unmap_send(qdev, tx_ring_desc,
  2683. tx_ring_desc->map_cnt);
  2684. dev_kfree_skb(tx_ring_desc->skb);
  2685. tx_ring_desc->skb = NULL;
  2686. }
  2687. }
  2688. }
  2689. }
  2690. static void ql_free_mem_resources(struct ql_adapter *qdev)
  2691. {
  2692. int i;
  2693. for (i = 0; i < qdev->tx_ring_count; i++)
  2694. ql_free_tx_resources(qdev, &qdev->tx_ring[i]);
  2695. for (i = 0; i < qdev->rx_ring_count; i++)
  2696. ql_free_rx_resources(qdev, &qdev->rx_ring[i]);
  2697. ql_free_shadow_space(qdev);
  2698. }
  2699. static int ql_alloc_mem_resources(struct ql_adapter *qdev)
  2700. {
  2701. int i;
  2702. /* Allocate space for our shadow registers and such. */
  2703. if (ql_alloc_shadow_space(qdev))
  2704. return -ENOMEM;
  2705. for (i = 0; i < qdev->rx_ring_count; i++) {
  2706. if (ql_alloc_rx_resources(qdev, &qdev->rx_ring[i]) != 0) {
  2707. netif_err(qdev, ifup, qdev->ndev,
  2708. "RX resource allocation failed.\n");
  2709. goto err_mem;
  2710. }
  2711. }
  2712. /* Allocate tx queue resources */
  2713. for (i = 0; i < qdev->tx_ring_count; i++) {
  2714. if (ql_alloc_tx_resources(qdev, &qdev->tx_ring[i]) != 0) {
  2715. netif_err(qdev, ifup, qdev->ndev,
  2716. "TX resource allocation failed.\n");
  2717. goto err_mem;
  2718. }
  2719. }
  2720. return 0;
  2721. err_mem:
  2722. ql_free_mem_resources(qdev);
  2723. return -ENOMEM;
  2724. }
  2725. /* Set up the rx ring control block and pass it to the chip.
  2726. * The control block is defined as
  2727. * "Completion Queue Initialization Control Block", or cqicb.
  2728. */
  2729. static int ql_start_rx_ring(struct ql_adapter *qdev, struct rx_ring *rx_ring)
  2730. {
  2731. struct cqicb *cqicb = &rx_ring->cqicb;
  2732. void *shadow_reg = qdev->rx_ring_shadow_reg_area +
  2733. (rx_ring->cq_id * RX_RING_SHADOW_SPACE);
  2734. u64 shadow_reg_dma = qdev->rx_ring_shadow_reg_dma +
  2735. (rx_ring->cq_id * RX_RING_SHADOW_SPACE);
  2736. void __iomem *doorbell_area =
  2737. qdev->doorbell_area + (DB_PAGE_SIZE * (128 + rx_ring->cq_id));
  2738. int err = 0;
  2739. u16 bq_len;
  2740. u64 tmp;
  2741. __le64 *base_indirect_ptr;
  2742. int page_entries;
  2743. /* Set up the shadow registers for this ring. */
  2744. rx_ring->prod_idx_sh_reg = shadow_reg;
  2745. rx_ring->prod_idx_sh_reg_dma = shadow_reg_dma;
  2746. *rx_ring->prod_idx_sh_reg = 0;
  2747. shadow_reg += sizeof(u64);
  2748. shadow_reg_dma += sizeof(u64);
  2749. rx_ring->lbq_base_indirect = shadow_reg;
  2750. rx_ring->lbq_base_indirect_dma = shadow_reg_dma;
  2751. shadow_reg += (sizeof(u64) * MAX_DB_PAGES_PER_BQ(rx_ring->lbq_len));
  2752. shadow_reg_dma += (sizeof(u64) * MAX_DB_PAGES_PER_BQ(rx_ring->lbq_len));
  2753. rx_ring->sbq_base_indirect = shadow_reg;
  2754. rx_ring->sbq_base_indirect_dma = shadow_reg_dma;
  2755. /* PCI doorbell mem area + 0x00 for consumer index register */
  2756. rx_ring->cnsmr_idx_db_reg = (u32 __iomem *) doorbell_area;
  2757. rx_ring->cnsmr_idx = 0;
  2758. rx_ring->curr_entry = rx_ring->cq_base;
  2759. /* PCI doorbell mem area + 0x04 for valid register */
  2760. rx_ring->valid_db_reg = doorbell_area + 0x04;
  2761. /* PCI doorbell mem area + 0x18 for large buffer consumer */
  2762. rx_ring->lbq_prod_idx_db_reg = (u32 __iomem *) (doorbell_area + 0x18);
  2763. /* PCI doorbell mem area + 0x1c */
  2764. rx_ring->sbq_prod_idx_db_reg = (u32 __iomem *) (doorbell_area + 0x1c);
  2765. memset((void *)cqicb, 0, sizeof(struct cqicb));
  2766. cqicb->msix_vect = rx_ring->irq;
  2767. bq_len = (rx_ring->cq_len == 65536) ? 0 : (u16) rx_ring->cq_len;
  2768. cqicb->len = cpu_to_le16(bq_len | LEN_V | LEN_CPP_CONT);
  2769. cqicb->addr = cpu_to_le64(rx_ring->cq_base_dma);
  2770. cqicb->prod_idx_addr = cpu_to_le64(rx_ring->prod_idx_sh_reg_dma);
  2771. /*
  2772. * Set up the control block load flags.
  2773. */
  2774. cqicb->flags = FLAGS_LC | /* Load queue base address */
  2775. FLAGS_LV | /* Load MSI-X vector */
  2776. FLAGS_LI; /* Load irq delay values */
  2777. if (rx_ring->lbq_len) {
  2778. cqicb->flags |= FLAGS_LL; /* Load lbq values */
  2779. tmp = (u64)rx_ring->lbq_base_dma;
  2780. base_indirect_ptr = rx_ring->lbq_base_indirect;
  2781. page_entries = 0;
  2782. do {
  2783. *base_indirect_ptr = cpu_to_le64(tmp);
  2784. tmp += DB_PAGE_SIZE;
  2785. base_indirect_ptr++;
  2786. page_entries++;
  2787. } while (page_entries < MAX_DB_PAGES_PER_BQ(rx_ring->lbq_len));
  2788. cqicb->lbq_addr =
  2789. cpu_to_le64(rx_ring->lbq_base_indirect_dma);
  2790. bq_len = (rx_ring->lbq_buf_size == 65536) ? 0 :
  2791. (u16) rx_ring->lbq_buf_size;
  2792. cqicb->lbq_buf_size = cpu_to_le16(bq_len);
  2793. bq_len = (rx_ring->lbq_len == 65536) ? 0 :
  2794. (u16) rx_ring->lbq_len;
  2795. cqicb->lbq_len = cpu_to_le16(bq_len);
  2796. rx_ring->lbq_prod_idx = 0;
  2797. rx_ring->lbq_curr_idx = 0;
  2798. rx_ring->lbq_clean_idx = 0;
  2799. rx_ring->lbq_free_cnt = rx_ring->lbq_len;
  2800. }
  2801. if (rx_ring->sbq_len) {
  2802. cqicb->flags |= FLAGS_LS; /* Load sbq values */
  2803. tmp = (u64)rx_ring->sbq_base_dma;
  2804. base_indirect_ptr = rx_ring->sbq_base_indirect;
  2805. page_entries = 0;
  2806. do {
  2807. *base_indirect_ptr = cpu_to_le64(tmp);
  2808. tmp += DB_PAGE_SIZE;
  2809. base_indirect_ptr++;
  2810. page_entries++;
  2811. } while (page_entries < MAX_DB_PAGES_PER_BQ(rx_ring->sbq_len));
  2812. cqicb->sbq_addr =
  2813. cpu_to_le64(rx_ring->sbq_base_indirect_dma);
  2814. cqicb->sbq_buf_size =
  2815. cpu_to_le16((u16)(rx_ring->sbq_buf_size));
  2816. bq_len = (rx_ring->sbq_len == 65536) ? 0 :
  2817. (u16) rx_ring->sbq_len;
  2818. cqicb->sbq_len = cpu_to_le16(bq_len);
  2819. rx_ring->sbq_prod_idx = 0;
  2820. rx_ring->sbq_curr_idx = 0;
  2821. rx_ring->sbq_clean_idx = 0;
  2822. rx_ring->sbq_free_cnt = rx_ring->sbq_len;
  2823. }
  2824. switch (rx_ring->type) {
  2825. case TX_Q:
  2826. cqicb->irq_delay = cpu_to_le16(qdev->tx_coalesce_usecs);
  2827. cqicb->pkt_delay = cpu_to_le16(qdev->tx_max_coalesced_frames);
  2828. break;
  2829. case RX_Q:
  2830. /* Inbound completion handling rx_rings run in
  2831. * separate NAPI contexts.
  2832. */
  2833. netif_napi_add(qdev->ndev, &rx_ring->napi, ql_napi_poll_msix,
  2834. 64);
  2835. cqicb->irq_delay = cpu_to_le16(qdev->rx_coalesce_usecs);
  2836. cqicb->pkt_delay = cpu_to_le16(qdev->rx_max_coalesced_frames);
  2837. break;
  2838. default:
  2839. netif_printk(qdev, ifup, KERN_DEBUG, qdev->ndev,
  2840. "Invalid rx_ring->type = %d.\n", rx_ring->type);
  2841. }
  2842. err = ql_write_cfg(qdev, cqicb, sizeof(struct cqicb),
  2843. CFG_LCQ, rx_ring->cq_id);
  2844. if (err) {
  2845. netif_err(qdev, ifup, qdev->ndev, "Failed to load CQICB.\n");
  2846. return err;
  2847. }
  2848. return err;
  2849. }
  2850. static int ql_start_tx_ring(struct ql_adapter *qdev, struct tx_ring *tx_ring)
  2851. {
  2852. struct wqicb *wqicb = (struct wqicb *)tx_ring;
  2853. void __iomem *doorbell_area =
  2854. qdev->doorbell_area + (DB_PAGE_SIZE * tx_ring->wq_id);
  2855. void *shadow_reg = qdev->tx_ring_shadow_reg_area +
  2856. (tx_ring->wq_id * sizeof(u64));
  2857. u64 shadow_reg_dma = qdev->tx_ring_shadow_reg_dma +
  2858. (tx_ring->wq_id * sizeof(u64));
  2859. int err = 0;
  2860. /*
  2861. * Assign doorbell registers for this tx_ring.
  2862. */
  2863. /* TX PCI doorbell mem area for tx producer index */
  2864. tx_ring->prod_idx_db_reg = (u32 __iomem *) doorbell_area;
  2865. tx_ring->prod_idx = 0;
  2866. /* TX PCI doorbell mem area + 0x04 */
  2867. tx_ring->valid_db_reg = doorbell_area + 0x04;
  2868. /*
  2869. * Assign shadow registers for this tx_ring.
  2870. */
  2871. tx_ring->cnsmr_idx_sh_reg = shadow_reg;
  2872. tx_ring->cnsmr_idx_sh_reg_dma = shadow_reg_dma;
  2873. wqicb->len = cpu_to_le16(tx_ring->wq_len | Q_LEN_V | Q_LEN_CPP_CONT);
  2874. wqicb->flags = cpu_to_le16(Q_FLAGS_LC |
  2875. Q_FLAGS_LB | Q_FLAGS_LI | Q_FLAGS_LO);
  2876. wqicb->cq_id_rss = cpu_to_le16(tx_ring->cq_id);
  2877. wqicb->rid = 0;
  2878. wqicb->addr = cpu_to_le64(tx_ring->wq_base_dma);
  2879. wqicb->cnsmr_idx_addr = cpu_to_le64(tx_ring->cnsmr_idx_sh_reg_dma);
  2880. ql_init_tx_ring(qdev, tx_ring);
  2881. err = ql_write_cfg(qdev, wqicb, sizeof(*wqicb), CFG_LRQ,
  2882. (u16) tx_ring->wq_id);
  2883. if (err) {
  2884. netif_err(qdev, ifup, qdev->ndev, "Failed to load tx_ring.\n");
  2885. return err;
  2886. }
  2887. return err;
  2888. }
  2889. static void ql_disable_msix(struct ql_adapter *qdev)
  2890. {
  2891. if (test_bit(QL_MSIX_ENABLED, &qdev->flags)) {
  2892. pci_disable_msix(qdev->pdev);
  2893. clear_bit(QL_MSIX_ENABLED, &qdev->flags);
  2894. kfree(qdev->msi_x_entry);
  2895. qdev->msi_x_entry = NULL;
  2896. } else if (test_bit(QL_MSI_ENABLED, &qdev->flags)) {
  2897. pci_disable_msi(qdev->pdev);
  2898. clear_bit(QL_MSI_ENABLED, &qdev->flags);
  2899. }
  2900. }
  2901. /* We start by trying to get the number of vectors
  2902. * stored in qdev->intr_count. If we don't get that
  2903. * many then we reduce the count and try again.
  2904. */
  2905. static void ql_enable_msix(struct ql_adapter *qdev)
  2906. {
  2907. int i, err;
  2908. /* Get the MSIX vectors. */
  2909. if (qlge_irq_type == MSIX_IRQ) {
  2910. /* Try to alloc space for the msix struct,
  2911. * if it fails then go to MSI/legacy.
  2912. */
  2913. qdev->msi_x_entry = kcalloc(qdev->intr_count,
  2914. sizeof(struct msix_entry),
  2915. GFP_KERNEL);
  2916. if (!qdev->msi_x_entry) {
  2917. qlge_irq_type = MSI_IRQ;
  2918. goto msi;
  2919. }
  2920. for (i = 0; i < qdev->intr_count; i++)
  2921. qdev->msi_x_entry[i].entry = i;
  2922. /* Loop to get our vectors. We start with
  2923. * what we want and settle for what we get.
  2924. */
  2925. do {
  2926. err = pci_enable_msix(qdev->pdev,
  2927. qdev->msi_x_entry, qdev->intr_count);
  2928. if (err > 0)
  2929. qdev->intr_count = err;
  2930. } while (err > 0);
  2931. if (err < 0) {
  2932. kfree(qdev->msi_x_entry);
  2933. qdev->msi_x_entry = NULL;
  2934. netif_warn(qdev, ifup, qdev->ndev,
  2935. "MSI-X Enable failed, trying MSI.\n");
  2936. qdev->intr_count = 1;
  2937. qlge_irq_type = MSI_IRQ;
  2938. } else if (err == 0) {
  2939. set_bit(QL_MSIX_ENABLED, &qdev->flags);
  2940. netif_info(qdev, ifup, qdev->ndev,
  2941. "MSI-X Enabled, got %d vectors.\n",
  2942. qdev->intr_count);
  2943. return;
  2944. }
  2945. }
  2946. msi:
  2947. qdev->intr_count = 1;
  2948. if (qlge_irq_type == MSI_IRQ) {
  2949. if (!pci_enable_msi(qdev->pdev)) {
  2950. set_bit(QL_MSI_ENABLED, &qdev->flags);
  2951. netif_info(qdev, ifup, qdev->ndev,
  2952. "Running with MSI interrupts.\n");
  2953. return;
  2954. }
  2955. }
  2956. qlge_irq_type = LEG_IRQ;
  2957. netif_printk(qdev, ifup, KERN_DEBUG, qdev->ndev,
  2958. "Running with legacy interrupts.\n");
  2959. }
  2960. /* Each vector services 1 RSS ring and and 1 or more
  2961. * TX completion rings. This function loops through
  2962. * the TX completion rings and assigns the vector that
  2963. * will service it. An example would be if there are
  2964. * 2 vectors (so 2 RSS rings) and 8 TX completion rings.
  2965. * This would mean that vector 0 would service RSS ring 0
  2966. * and TX completion rings 0,1,2 and 3. Vector 1 would
  2967. * service RSS ring 1 and TX completion rings 4,5,6 and 7.
  2968. */
  2969. static void ql_set_tx_vect(struct ql_adapter *qdev)
  2970. {
  2971. int i, j, vect;
  2972. u32 tx_rings_per_vector = qdev->tx_ring_count / qdev->intr_count;
  2973. if (likely(test_bit(QL_MSIX_ENABLED, &qdev->flags))) {
  2974. /* Assign irq vectors to TX rx_rings.*/
  2975. for (vect = 0, j = 0, i = qdev->rss_ring_count;
  2976. i < qdev->rx_ring_count; i++) {
  2977. if (j == tx_rings_per_vector) {
  2978. vect++;
  2979. j = 0;
  2980. }
  2981. qdev->rx_ring[i].irq = vect;
  2982. j++;
  2983. }
  2984. } else {
  2985. /* For single vector all rings have an irq
  2986. * of zero.
  2987. */
  2988. for (i = 0; i < qdev->rx_ring_count; i++)
  2989. qdev->rx_ring[i].irq = 0;
  2990. }
  2991. }
  2992. /* Set the interrupt mask for this vector. Each vector
  2993. * will service 1 RSS ring and 1 or more TX completion
  2994. * rings. This function sets up a bit mask per vector
  2995. * that indicates which rings it services.
  2996. */
  2997. static void ql_set_irq_mask(struct ql_adapter *qdev, struct intr_context *ctx)
  2998. {
  2999. int j, vect = ctx->intr;
  3000. u32 tx_rings_per_vector = qdev->tx_ring_count / qdev->intr_count;
  3001. if (likely(test_bit(QL_MSIX_ENABLED, &qdev->flags))) {
  3002. /* Add the RSS ring serviced by this vector
  3003. * to the mask.
  3004. */
  3005. ctx->irq_mask = (1 << qdev->rx_ring[vect].cq_id);
  3006. /* Add the TX ring(s) serviced by this vector
  3007. * to the mask. */
  3008. for (j = 0; j < tx_rings_per_vector; j++) {
  3009. ctx->irq_mask |=
  3010. (1 << qdev->rx_ring[qdev->rss_ring_count +
  3011. (vect * tx_rings_per_vector) + j].cq_id);
  3012. }
  3013. } else {
  3014. /* For single vector we just shift each queue's
  3015. * ID into the mask.
  3016. */
  3017. for (j = 0; j < qdev->rx_ring_count; j++)
  3018. ctx->irq_mask |= (1 << qdev->rx_ring[j].cq_id);
  3019. }
  3020. }
  3021. /*
  3022. * Here we build the intr_context structures based on
  3023. * our rx_ring count and intr vector count.
  3024. * The intr_context structure is used to hook each vector
  3025. * to possibly different handlers.
  3026. */
  3027. static void ql_resolve_queues_to_irqs(struct ql_adapter *qdev)
  3028. {
  3029. int i = 0;
  3030. struct intr_context *intr_context = &qdev->intr_context[0];
  3031. if (likely(test_bit(QL_MSIX_ENABLED, &qdev->flags))) {
  3032. /* Each rx_ring has it's
  3033. * own intr_context since we have separate
  3034. * vectors for each queue.
  3035. */
  3036. for (i = 0; i < qdev->intr_count; i++, intr_context++) {
  3037. qdev->rx_ring[i].irq = i;
  3038. intr_context->intr = i;
  3039. intr_context->qdev = qdev;
  3040. /* Set up this vector's bit-mask that indicates
  3041. * which queues it services.
  3042. */
  3043. ql_set_irq_mask(qdev, intr_context);
  3044. /*
  3045. * We set up each vectors enable/disable/read bits so
  3046. * there's no bit/mask calculations in the critical path.
  3047. */
  3048. intr_context->intr_en_mask =
  3049. INTR_EN_TYPE_MASK | INTR_EN_INTR_MASK |
  3050. INTR_EN_TYPE_ENABLE | INTR_EN_IHD_MASK | INTR_EN_IHD
  3051. | i;
  3052. intr_context->intr_dis_mask =
  3053. INTR_EN_TYPE_MASK | INTR_EN_INTR_MASK |
  3054. INTR_EN_TYPE_DISABLE | INTR_EN_IHD_MASK |
  3055. INTR_EN_IHD | i;
  3056. intr_context->intr_read_mask =
  3057. INTR_EN_TYPE_MASK | INTR_EN_INTR_MASK |
  3058. INTR_EN_TYPE_READ | INTR_EN_IHD_MASK | INTR_EN_IHD |
  3059. i;
  3060. if (i == 0) {
  3061. /* The first vector/queue handles
  3062. * broadcast/multicast, fatal errors,
  3063. * and firmware events. This in addition
  3064. * to normal inbound NAPI processing.
  3065. */
  3066. intr_context->handler = qlge_isr;
  3067. sprintf(intr_context->name, "%s-rx-%d",
  3068. qdev->ndev->name, i);
  3069. } else {
  3070. /*
  3071. * Inbound queues handle unicast frames only.
  3072. */
  3073. intr_context->handler = qlge_msix_rx_isr;
  3074. sprintf(intr_context->name, "%s-rx-%d",
  3075. qdev->ndev->name, i);
  3076. }
  3077. }
  3078. } else {
  3079. /*
  3080. * All rx_rings use the same intr_context since
  3081. * there is only one vector.
  3082. */
  3083. intr_context->intr = 0;
  3084. intr_context->qdev = qdev;
  3085. /*
  3086. * We set up each vectors enable/disable/read bits so
  3087. * there's no bit/mask calculations in the critical path.
  3088. */
  3089. intr_context->intr_en_mask =
  3090. INTR_EN_TYPE_MASK | INTR_EN_INTR_MASK | INTR_EN_TYPE_ENABLE;
  3091. intr_context->intr_dis_mask =
  3092. INTR_EN_TYPE_MASK | INTR_EN_INTR_MASK |
  3093. INTR_EN_TYPE_DISABLE;
  3094. intr_context->intr_read_mask =
  3095. INTR_EN_TYPE_MASK | INTR_EN_INTR_MASK | INTR_EN_TYPE_READ;
  3096. /*
  3097. * Single interrupt means one handler for all rings.
  3098. */
  3099. intr_context->handler = qlge_isr;
  3100. sprintf(intr_context->name, "%s-single_irq", qdev->ndev->name);
  3101. /* Set up this vector's bit-mask that indicates
  3102. * which queues it services. In this case there is
  3103. * a single vector so it will service all RSS and
  3104. * TX completion rings.
  3105. */
  3106. ql_set_irq_mask(qdev, intr_context);
  3107. }
  3108. /* Tell the TX completion rings which MSIx vector
  3109. * they will be using.
  3110. */
  3111. ql_set_tx_vect(qdev);
  3112. }
  3113. static void ql_free_irq(struct ql_adapter *qdev)
  3114. {
  3115. int i;
  3116. struct intr_context *intr_context = &qdev->intr_context[0];
  3117. for (i = 0; i < qdev->intr_count; i++, intr_context++) {
  3118. if (intr_context->hooked) {
  3119. if (test_bit(QL_MSIX_ENABLED, &qdev->flags)) {
  3120. free_irq(qdev->msi_x_entry[i].vector,
  3121. &qdev->rx_ring[i]);
  3122. } else {
  3123. free_irq(qdev->pdev->irq, &qdev->rx_ring[0]);
  3124. }
  3125. }
  3126. }
  3127. ql_disable_msix(qdev);
  3128. }
  3129. static int ql_request_irq(struct ql_adapter *qdev)
  3130. {
  3131. int i;
  3132. int status = 0;
  3133. struct pci_dev *pdev = qdev->pdev;
  3134. struct intr_context *intr_context = &qdev->intr_context[0];
  3135. ql_resolve_queues_to_irqs(qdev);
  3136. for (i = 0; i < qdev->intr_count; i++, intr_context++) {
  3137. atomic_set(&intr_context->irq_cnt, 0);
  3138. if (test_bit(QL_MSIX_ENABLED, &qdev->flags)) {
  3139. status = request_irq(qdev->msi_x_entry[i].vector,
  3140. intr_context->handler,
  3141. 0,
  3142. intr_context->name,
  3143. &qdev->rx_ring[i]);
  3144. if (status) {
  3145. netif_err(qdev, ifup, qdev->ndev,
  3146. "Failed request for MSIX interrupt %d.\n",
  3147. i);
  3148. goto err_irq;
  3149. }
  3150. } else {
  3151. netif_printk(qdev, ifup, KERN_DEBUG, qdev->ndev,
  3152. "trying msi or legacy interrupts.\n");
  3153. netif_printk(qdev, ifup, KERN_DEBUG, qdev->ndev,
  3154. "%s: irq = %d.\n", __func__, pdev->irq);
  3155. netif_printk(qdev, ifup, KERN_DEBUG, qdev->ndev,
  3156. "%s: context->name = %s.\n", __func__,
  3157. intr_context->name);
  3158. netif_printk(qdev, ifup, KERN_DEBUG, qdev->ndev,
  3159. "%s: dev_id = 0x%p.\n", __func__,
  3160. &qdev->rx_ring[0]);
  3161. status =
  3162. request_irq(pdev->irq, qlge_isr,
  3163. test_bit(QL_MSI_ENABLED,
  3164. &qdev->
  3165. flags) ? 0 : IRQF_SHARED,
  3166. intr_context->name, &qdev->rx_ring[0]);
  3167. if (status)
  3168. goto err_irq;
  3169. netif_err(qdev, ifup, qdev->ndev,
  3170. "Hooked intr %d, queue type %s, with name %s.\n",
  3171. i,
  3172. qdev->rx_ring[0].type == DEFAULT_Q ?
  3173. "DEFAULT_Q" :
  3174. qdev->rx_ring[0].type == TX_Q ? "TX_Q" :
  3175. qdev->rx_ring[0].type == RX_Q ? "RX_Q" : "",
  3176. intr_context->name);
  3177. }
  3178. intr_context->hooked = 1;
  3179. }
  3180. return status;
  3181. err_irq:
  3182. netif_err(qdev, ifup, qdev->ndev, "Failed to get the interrupts!!!/n");
  3183. ql_free_irq(qdev);
  3184. return status;
  3185. }
  3186. static int ql_start_rss(struct ql_adapter *qdev)
  3187. {
  3188. static const u8 init_hash_seed[] = {
  3189. 0x6d, 0x5a, 0x56, 0xda, 0x25, 0x5b, 0x0e, 0xc2,
  3190. 0x41, 0x67, 0x25, 0x3d, 0x43, 0xa3, 0x8f, 0xb0,
  3191. 0xd0, 0xca, 0x2b, 0xcb, 0xae, 0x7b, 0x30, 0xb4,
  3192. 0x77, 0xcb, 0x2d, 0xa3, 0x80, 0x30, 0xf2, 0x0c,
  3193. 0x6a, 0x42, 0xb7, 0x3b, 0xbe, 0xac, 0x01, 0xfa
  3194. };
  3195. struct ricb *ricb = &qdev->ricb;
  3196. int status = 0;
  3197. int i;
  3198. u8 *hash_id = (u8 *) ricb->hash_cq_id;
  3199. memset((void *)ricb, 0, sizeof(*ricb));
  3200. ricb->base_cq = RSS_L4K;
  3201. ricb->flags =
  3202. (RSS_L6K | RSS_LI | RSS_LB | RSS_LM | RSS_RT4 | RSS_RT6);
  3203. ricb->mask = cpu_to_le16((u16)(0x3ff));
  3204. /*
  3205. * Fill out the Indirection Table.
  3206. */
  3207. for (i = 0; i < 1024; i++)
  3208. hash_id[i] = (i & (qdev->rss_ring_count - 1));
  3209. memcpy((void *)&ricb->ipv6_hash_key[0], init_hash_seed, 40);
  3210. memcpy((void *)&ricb->ipv4_hash_key[0], init_hash_seed, 16);
  3211. status = ql_write_cfg(qdev, ricb, sizeof(*ricb), CFG_LR, 0);
  3212. if (status) {
  3213. netif_err(qdev, ifup, qdev->ndev, "Failed to load RICB.\n");
  3214. return status;
  3215. }
  3216. return status;
  3217. }
  3218. static int ql_clear_routing_entries(struct ql_adapter *qdev)
  3219. {
  3220. int i, status = 0;
  3221. status = ql_sem_spinlock(qdev, SEM_RT_IDX_MASK);
  3222. if (status)
  3223. return status;
  3224. /* Clear all the entries in the routing table. */
  3225. for (i = 0; i < 16; i++) {
  3226. status = ql_set_routing_reg(qdev, i, 0, 0);
  3227. if (status) {
  3228. netif_err(qdev, ifup, qdev->ndev,
  3229. "Failed to init routing register for CAM packets.\n");
  3230. break;
  3231. }
  3232. }
  3233. ql_sem_unlock(qdev, SEM_RT_IDX_MASK);
  3234. return status;
  3235. }
  3236. /* Initialize the frame-to-queue routing. */
  3237. static int ql_route_initialize(struct ql_adapter *qdev)
  3238. {
  3239. int status = 0;
  3240. /* Clear all the entries in the routing table. */
  3241. status = ql_clear_routing_entries(qdev);
  3242. if (status)
  3243. return status;
  3244. status = ql_sem_spinlock(qdev, SEM_RT_IDX_MASK);
  3245. if (status)
  3246. return status;
  3247. status = ql_set_routing_reg(qdev, RT_IDX_IP_CSUM_ERR_SLOT,
  3248. RT_IDX_IP_CSUM_ERR, 1);
  3249. if (status) {
  3250. netif_err(qdev, ifup, qdev->ndev,
  3251. "Failed to init routing register "
  3252. "for IP CSUM error packets.\n");
  3253. goto exit;
  3254. }
  3255. status = ql_set_routing_reg(qdev, RT_IDX_TCP_UDP_CSUM_ERR_SLOT,
  3256. RT_IDX_TU_CSUM_ERR, 1);
  3257. if (status) {
  3258. netif_err(qdev, ifup, qdev->ndev,
  3259. "Failed to init routing register "
  3260. "for TCP/UDP CSUM error packets.\n");
  3261. goto exit;
  3262. }
  3263. status = ql_set_routing_reg(qdev, RT_IDX_BCAST_SLOT, RT_IDX_BCAST, 1);
  3264. if (status) {
  3265. netif_err(qdev, ifup, qdev->ndev,
  3266. "Failed to init routing register for broadcast packets.\n");
  3267. goto exit;
  3268. }
  3269. /* If we have more than one inbound queue, then turn on RSS in the
  3270. * routing block.
  3271. */
  3272. if (qdev->rss_ring_count > 1) {
  3273. status = ql_set_routing_reg(qdev, RT_IDX_RSS_MATCH_SLOT,
  3274. RT_IDX_RSS_MATCH, 1);
  3275. if (status) {
  3276. netif_err(qdev, ifup, qdev->ndev,
  3277. "Failed to init routing register for MATCH RSS packets.\n");
  3278. goto exit;
  3279. }
  3280. }
  3281. status = ql_set_routing_reg(qdev, RT_IDX_CAM_HIT_SLOT,
  3282. RT_IDX_CAM_HIT, 1);
  3283. if (status)
  3284. netif_err(qdev, ifup, qdev->ndev,
  3285. "Failed to init routing register for CAM packets.\n");
  3286. exit:
  3287. ql_sem_unlock(qdev, SEM_RT_IDX_MASK);
  3288. return status;
  3289. }
  3290. int ql_cam_route_initialize(struct ql_adapter *qdev)
  3291. {
  3292. int status, set;
  3293. /* If check if the link is up and use to
  3294. * determine if we are setting or clearing
  3295. * the MAC address in the CAM.
  3296. */
  3297. set = ql_read32(qdev, STS);
  3298. set &= qdev->port_link_up;
  3299. status = ql_set_mac_addr(qdev, set);
  3300. if (status) {
  3301. netif_err(qdev, ifup, qdev->ndev, "Failed to init mac address.\n");
  3302. return status;
  3303. }
  3304. status = ql_route_initialize(qdev);
  3305. if (status)
  3306. netif_err(qdev, ifup, qdev->ndev, "Failed to init routing table.\n");
  3307. return status;
  3308. }
  3309. static int ql_adapter_initialize(struct ql_adapter *qdev)
  3310. {
  3311. u32 value, mask;
  3312. int i;
  3313. int status = 0;
  3314. /*
  3315. * Set up the System register to halt on errors.
  3316. */
  3317. value = SYS_EFE | SYS_FAE;
  3318. mask = value << 16;
  3319. ql_write32(qdev, SYS, mask | value);
  3320. /* Set the default queue, and VLAN behavior. */
  3321. value = NIC_RCV_CFG_DFQ | NIC_RCV_CFG_RV;
  3322. mask = NIC_RCV_CFG_DFQ_MASK | (NIC_RCV_CFG_RV << 16);
  3323. ql_write32(qdev, NIC_RCV_CFG, (mask | value));
  3324. /* Set the MPI interrupt to enabled. */
  3325. ql_write32(qdev, INTR_MASK, (INTR_MASK_PI << 16) | INTR_MASK_PI);
  3326. /* Enable the function, set pagesize, enable error checking. */
  3327. value = FSC_FE | FSC_EPC_INBOUND | FSC_EPC_OUTBOUND |
  3328. FSC_EC | FSC_VM_PAGE_4K;
  3329. value |= SPLT_SETTING;
  3330. /* Set/clear header splitting. */
  3331. mask = FSC_VM_PAGESIZE_MASK |
  3332. FSC_DBL_MASK | FSC_DBRST_MASK | (value << 16);
  3333. ql_write32(qdev, FSC, mask | value);
  3334. ql_write32(qdev, SPLT_HDR, SPLT_LEN);
  3335. /* Set RX packet routing to use port/pci function on which the
  3336. * packet arrived on in addition to usual frame routing.
  3337. * This is helpful on bonding where both interfaces can have
  3338. * the same MAC address.
  3339. */
  3340. ql_write32(qdev, RST_FO, RST_FO_RR_MASK | RST_FO_RR_RCV_FUNC_CQ);
  3341. /* Reroute all packets to our Interface.
  3342. * They may have been routed to MPI firmware
  3343. * due to WOL.
  3344. */
  3345. value = ql_read32(qdev, MGMT_RCV_CFG);
  3346. value &= ~MGMT_RCV_CFG_RM;
  3347. mask = 0xffff0000;
  3348. /* Sticky reg needs clearing due to WOL. */
  3349. ql_write32(qdev, MGMT_RCV_CFG, mask);
  3350. ql_write32(qdev, MGMT_RCV_CFG, mask | value);
  3351. /* Default WOL is enable on Mezz cards */
  3352. if (qdev->pdev->subsystem_device == 0x0068 ||
  3353. qdev->pdev->subsystem_device == 0x0180)
  3354. qdev->wol = WAKE_MAGIC;
  3355. /* Start up the rx queues. */
  3356. for (i = 0; i < qdev->rx_ring_count; i++) {
  3357. status = ql_start_rx_ring(qdev, &qdev->rx_ring[i]);
  3358. if (status) {
  3359. netif_err(qdev, ifup, qdev->ndev,
  3360. "Failed to start rx ring[%d].\n", i);
  3361. return status;
  3362. }
  3363. }
  3364. /* If there is more than one inbound completion queue
  3365. * then download a RICB to configure RSS.
  3366. */
  3367. if (qdev->rss_ring_count > 1) {
  3368. status = ql_start_rss(qdev);
  3369. if (status) {
  3370. netif_err(qdev, ifup, qdev->ndev, "Failed to start RSS.\n");
  3371. return status;
  3372. }
  3373. }
  3374. /* Start up the tx queues. */
  3375. for (i = 0; i < qdev->tx_ring_count; i++) {
  3376. status = ql_start_tx_ring(qdev, &qdev->tx_ring[i]);
  3377. if (status) {
  3378. netif_err(qdev, ifup, qdev->ndev,
  3379. "Failed to start tx ring[%d].\n", i);
  3380. return status;
  3381. }
  3382. }
  3383. /* Initialize the port and set the max framesize. */
  3384. status = qdev->nic_ops->port_initialize(qdev);
  3385. if (status)
  3386. netif_err(qdev, ifup, qdev->ndev, "Failed to start port.\n");
  3387. /* Set up the MAC address and frame routing filter. */
  3388. status = ql_cam_route_initialize(qdev);
  3389. if (status) {
  3390. netif_err(qdev, ifup, qdev->ndev,
  3391. "Failed to init CAM/Routing tables.\n");
  3392. return status;
  3393. }
  3394. /* Start NAPI for the RSS queues. */
  3395. for (i = 0; i < qdev->rss_ring_count; i++)
  3396. napi_enable(&qdev->rx_ring[i].napi);
  3397. return status;
  3398. }
  3399. /* Issue soft reset to chip. */
  3400. static int ql_adapter_reset(struct ql_adapter *qdev)
  3401. {
  3402. u32 value;
  3403. int status = 0;
  3404. unsigned long end_jiffies;
  3405. /* Clear all the entries in the routing table. */
  3406. status = ql_clear_routing_entries(qdev);
  3407. if (status) {
  3408. netif_err(qdev, ifup, qdev->ndev, "Failed to clear routing bits.\n");
  3409. return status;
  3410. }
  3411. end_jiffies = jiffies +
  3412. max((unsigned long)1, usecs_to_jiffies(30));
  3413. /* Check if bit is set then skip the mailbox command and
  3414. * clear the bit, else we are in normal reset process.
  3415. */
  3416. if (!test_bit(QL_ASIC_RECOVERY, &qdev->flags)) {
  3417. /* Stop management traffic. */
  3418. ql_mb_set_mgmnt_traffic_ctl(qdev, MB_SET_MPI_TFK_STOP);
  3419. /* Wait for the NIC and MGMNT FIFOs to empty. */
  3420. ql_wait_fifo_empty(qdev);
  3421. } else
  3422. clear_bit(QL_ASIC_RECOVERY, &qdev->flags);
  3423. ql_write32(qdev, RST_FO, (RST_FO_FR << 16) | RST_FO_FR);
  3424. do {
  3425. value = ql_read32(qdev, RST_FO);
  3426. if ((value & RST_FO_FR) == 0)
  3427. break;
  3428. cpu_relax();
  3429. } while (time_before(jiffies, end_jiffies));
  3430. if (value & RST_FO_FR) {
  3431. netif_err(qdev, ifdown, qdev->ndev,
  3432. "ETIMEDOUT!!! errored out of resetting the chip!\n");
  3433. status = -ETIMEDOUT;
  3434. }
  3435. /* Resume management traffic. */
  3436. ql_mb_set_mgmnt_traffic_ctl(qdev, MB_SET_MPI_TFK_RESUME);
  3437. return status;
  3438. }
  3439. static void ql_display_dev_info(struct net_device *ndev)
  3440. {
  3441. struct ql_adapter *qdev = netdev_priv(ndev);
  3442. netif_info(qdev, probe, qdev->ndev,
  3443. "Function #%d, Port %d, NIC Roll %d, NIC Rev = %d, "
  3444. "XG Roll = %d, XG Rev = %d.\n",
  3445. qdev->func,
  3446. qdev->port,
  3447. qdev->chip_rev_id & 0x0000000f,
  3448. qdev->chip_rev_id >> 4 & 0x0000000f,
  3449. qdev->chip_rev_id >> 8 & 0x0000000f,
  3450. qdev->chip_rev_id >> 12 & 0x0000000f);
  3451. netif_info(qdev, probe, qdev->ndev,
  3452. "MAC address %pM\n", ndev->dev_addr);
  3453. }
  3454. static int ql_wol(struct ql_adapter *qdev)
  3455. {
  3456. int status = 0;
  3457. u32 wol = MB_WOL_DISABLE;
  3458. /* The CAM is still intact after a reset, but if we
  3459. * are doing WOL, then we may need to program the
  3460. * routing regs. We would also need to issue the mailbox
  3461. * commands to instruct the MPI what to do per the ethtool
  3462. * settings.
  3463. */
  3464. if (qdev->wol & (WAKE_ARP | WAKE_MAGICSECURE | WAKE_PHY | WAKE_UCAST |
  3465. WAKE_MCAST | WAKE_BCAST)) {
  3466. netif_err(qdev, ifdown, qdev->ndev,
  3467. "Unsupported WOL parameter. qdev->wol = 0x%x.\n",
  3468. qdev->wol);
  3469. return -EINVAL;
  3470. }
  3471. if (qdev->wol & WAKE_MAGIC) {
  3472. status = ql_mb_wol_set_magic(qdev, 1);
  3473. if (status) {
  3474. netif_err(qdev, ifdown, qdev->ndev,
  3475. "Failed to set magic packet on %s.\n",
  3476. qdev->ndev->name);
  3477. return status;
  3478. } else
  3479. netif_info(qdev, drv, qdev->ndev,
  3480. "Enabled magic packet successfully on %s.\n",
  3481. qdev->ndev->name);
  3482. wol |= MB_WOL_MAGIC_PKT;
  3483. }
  3484. if (qdev->wol) {
  3485. wol |= MB_WOL_MODE_ON;
  3486. status = ql_mb_wol_mode(qdev, wol);
  3487. netif_err(qdev, drv, qdev->ndev,
  3488. "WOL %s (wol code 0x%x) on %s\n",
  3489. (status == 0) ? "Successfully set" : "Failed",
  3490. wol, qdev->ndev->name);
  3491. }
  3492. return status;
  3493. }
  3494. static void ql_cancel_all_work_sync(struct ql_adapter *qdev)
  3495. {
  3496. /* Don't kill the reset worker thread if we
  3497. * are in the process of recovery.
  3498. */
  3499. if (test_bit(QL_ADAPTER_UP, &qdev->flags))
  3500. cancel_delayed_work_sync(&qdev->asic_reset_work);
  3501. cancel_delayed_work_sync(&qdev->mpi_reset_work);
  3502. cancel_delayed_work_sync(&qdev->mpi_work);
  3503. cancel_delayed_work_sync(&qdev->mpi_idc_work);
  3504. cancel_delayed_work_sync(&qdev->mpi_core_to_log);
  3505. cancel_delayed_work_sync(&qdev->mpi_port_cfg_work);
  3506. }
  3507. static int ql_adapter_down(struct ql_adapter *qdev)
  3508. {
  3509. int i, status = 0;
  3510. ql_link_off(qdev);
  3511. ql_cancel_all_work_sync(qdev);
  3512. for (i = 0; i < qdev->rss_ring_count; i++)
  3513. napi_disable(&qdev->rx_ring[i].napi);
  3514. clear_bit(QL_ADAPTER_UP, &qdev->flags);
  3515. ql_disable_interrupts(qdev);
  3516. ql_tx_ring_clean(qdev);
  3517. /* Call netif_napi_del() from common point.
  3518. */
  3519. for (i = 0; i < qdev->rss_ring_count; i++)
  3520. netif_napi_del(&qdev->rx_ring[i].napi);
  3521. status = ql_adapter_reset(qdev);
  3522. if (status)
  3523. netif_err(qdev, ifdown, qdev->ndev, "reset(func #%d) FAILED!\n",
  3524. qdev->func);
  3525. ql_free_rx_buffers(qdev);
  3526. return status;
  3527. }
  3528. static int ql_adapter_up(struct ql_adapter *qdev)
  3529. {
  3530. int err = 0;
  3531. err = ql_adapter_initialize(qdev);
  3532. if (err) {
  3533. netif_info(qdev, ifup, qdev->ndev, "Unable to initialize adapter.\n");
  3534. goto err_init;
  3535. }
  3536. set_bit(QL_ADAPTER_UP, &qdev->flags);
  3537. ql_alloc_rx_buffers(qdev);
  3538. /* If the port is initialized and the
  3539. * link is up the turn on the carrier.
  3540. */
  3541. if ((ql_read32(qdev, STS) & qdev->port_init) &&
  3542. (ql_read32(qdev, STS) & qdev->port_link_up))
  3543. ql_link_on(qdev);
  3544. /* Restore rx mode. */
  3545. clear_bit(QL_ALLMULTI, &qdev->flags);
  3546. clear_bit(QL_PROMISCUOUS, &qdev->flags);
  3547. qlge_set_multicast_list(qdev->ndev);
  3548. /* Restore vlan setting. */
  3549. qlge_restore_vlan(qdev);
  3550. ql_enable_interrupts(qdev);
  3551. ql_enable_all_completion_interrupts(qdev);
  3552. netif_tx_start_all_queues(qdev->ndev);
  3553. return 0;
  3554. err_init:
  3555. ql_adapter_reset(qdev);
  3556. return err;
  3557. }
  3558. static void ql_release_adapter_resources(struct ql_adapter *qdev)
  3559. {
  3560. ql_free_mem_resources(qdev);
  3561. ql_free_irq(qdev);
  3562. }
  3563. static int ql_get_adapter_resources(struct ql_adapter *qdev)
  3564. {
  3565. int status = 0;
  3566. if (ql_alloc_mem_resources(qdev)) {
  3567. netif_err(qdev, ifup, qdev->ndev, "Unable to allocate memory.\n");
  3568. return -ENOMEM;
  3569. }
  3570. status = ql_request_irq(qdev);
  3571. return status;
  3572. }
  3573. static int qlge_close(struct net_device *ndev)
  3574. {
  3575. struct ql_adapter *qdev = netdev_priv(ndev);
  3576. /* If we hit pci_channel_io_perm_failure
  3577. * failure condition, then we already
  3578. * brought the adapter down.
  3579. */
  3580. if (test_bit(QL_EEH_FATAL, &qdev->flags)) {
  3581. netif_err(qdev, drv, qdev->ndev, "EEH fatal did unload.\n");
  3582. clear_bit(QL_EEH_FATAL, &qdev->flags);
  3583. return 0;
  3584. }
  3585. /*
  3586. * Wait for device to recover from a reset.
  3587. * (Rarely happens, but possible.)
  3588. */
  3589. while (!test_bit(QL_ADAPTER_UP, &qdev->flags))
  3590. msleep(1);
  3591. ql_adapter_down(qdev);
  3592. ql_release_adapter_resources(qdev);
  3593. return 0;
  3594. }
  3595. static int ql_configure_rings(struct ql_adapter *qdev)
  3596. {
  3597. int i;
  3598. struct rx_ring *rx_ring;
  3599. struct tx_ring *tx_ring;
  3600. int cpu_cnt = min(MAX_CPUS, (int)num_online_cpus());
  3601. unsigned int lbq_buf_len = (qdev->ndev->mtu > 1500) ?
  3602. LARGE_BUFFER_MAX_SIZE : LARGE_BUFFER_MIN_SIZE;
  3603. qdev->lbq_buf_order = get_order(lbq_buf_len);
  3604. /* In a perfect world we have one RSS ring for each CPU
  3605. * and each has it's own vector. To do that we ask for
  3606. * cpu_cnt vectors. ql_enable_msix() will adjust the
  3607. * vector count to what we actually get. We then
  3608. * allocate an RSS ring for each.
  3609. * Essentially, we are doing min(cpu_count, msix_vector_count).
  3610. */
  3611. qdev->intr_count = cpu_cnt;
  3612. ql_enable_msix(qdev);
  3613. /* Adjust the RSS ring count to the actual vector count. */
  3614. qdev->rss_ring_count = qdev->intr_count;
  3615. qdev->tx_ring_count = cpu_cnt;
  3616. qdev->rx_ring_count = qdev->tx_ring_count + qdev->rss_ring_count;
  3617. for (i = 0; i < qdev->tx_ring_count; i++) {
  3618. tx_ring = &qdev->tx_ring[i];
  3619. memset((void *)tx_ring, 0, sizeof(*tx_ring));
  3620. tx_ring->qdev = qdev;
  3621. tx_ring->wq_id = i;
  3622. tx_ring->wq_len = qdev->tx_ring_size;
  3623. tx_ring->wq_size =
  3624. tx_ring->wq_len * sizeof(struct ob_mac_iocb_req);
  3625. /*
  3626. * The completion queue ID for the tx rings start
  3627. * immediately after the rss rings.
  3628. */
  3629. tx_ring->cq_id = qdev->rss_ring_count + i;
  3630. }
  3631. for (i = 0; i < qdev->rx_ring_count; i++) {
  3632. rx_ring = &qdev->rx_ring[i];
  3633. memset((void *)rx_ring, 0, sizeof(*rx_ring));
  3634. rx_ring->qdev = qdev;
  3635. rx_ring->cq_id = i;
  3636. rx_ring->cpu = i % cpu_cnt; /* CPU to run handler on. */
  3637. if (i < qdev->rss_ring_count) {
  3638. /*
  3639. * Inbound (RSS) queues.
  3640. */
  3641. rx_ring->cq_len = qdev->rx_ring_size;
  3642. rx_ring->cq_size =
  3643. rx_ring->cq_len * sizeof(struct ql_net_rsp_iocb);
  3644. rx_ring->lbq_len = NUM_LARGE_BUFFERS;
  3645. rx_ring->lbq_size =
  3646. rx_ring->lbq_len * sizeof(__le64);
  3647. rx_ring->lbq_buf_size = (u16)lbq_buf_len;
  3648. rx_ring->sbq_len = NUM_SMALL_BUFFERS;
  3649. rx_ring->sbq_size =
  3650. rx_ring->sbq_len * sizeof(__le64);
  3651. rx_ring->sbq_buf_size = SMALL_BUF_MAP_SIZE;
  3652. rx_ring->type = RX_Q;
  3653. } else {
  3654. /*
  3655. * Outbound queue handles outbound completions only.
  3656. */
  3657. /* outbound cq is same size as tx_ring it services. */
  3658. rx_ring->cq_len = qdev->tx_ring_size;
  3659. rx_ring->cq_size =
  3660. rx_ring->cq_len * sizeof(struct ql_net_rsp_iocb);
  3661. rx_ring->lbq_len = 0;
  3662. rx_ring->lbq_size = 0;
  3663. rx_ring->lbq_buf_size = 0;
  3664. rx_ring->sbq_len = 0;
  3665. rx_ring->sbq_size = 0;
  3666. rx_ring->sbq_buf_size = 0;
  3667. rx_ring->type = TX_Q;
  3668. }
  3669. }
  3670. return 0;
  3671. }
  3672. static int qlge_open(struct net_device *ndev)
  3673. {
  3674. int err = 0;
  3675. struct ql_adapter *qdev = netdev_priv(ndev);
  3676. err = ql_adapter_reset(qdev);
  3677. if (err)
  3678. return err;
  3679. err = ql_configure_rings(qdev);
  3680. if (err)
  3681. return err;
  3682. err = ql_get_adapter_resources(qdev);
  3683. if (err)
  3684. goto error_up;
  3685. err = ql_adapter_up(qdev);
  3686. if (err)
  3687. goto error_up;
  3688. return err;
  3689. error_up:
  3690. ql_release_adapter_resources(qdev);
  3691. return err;
  3692. }
  3693. static int ql_change_rx_buffers(struct ql_adapter *qdev)
  3694. {
  3695. struct rx_ring *rx_ring;
  3696. int i, status;
  3697. u32 lbq_buf_len;
  3698. /* Wait for an outstanding reset to complete. */
  3699. if (!test_bit(QL_ADAPTER_UP, &qdev->flags)) {
  3700. int i = 3;
  3701. while (i-- && !test_bit(QL_ADAPTER_UP, &qdev->flags)) {
  3702. netif_err(qdev, ifup, qdev->ndev,
  3703. "Waiting for adapter UP...\n");
  3704. ssleep(1);
  3705. }
  3706. if (!i) {
  3707. netif_err(qdev, ifup, qdev->ndev,
  3708. "Timed out waiting for adapter UP\n");
  3709. return -ETIMEDOUT;
  3710. }
  3711. }
  3712. status = ql_adapter_down(qdev);
  3713. if (status)
  3714. goto error;
  3715. /* Get the new rx buffer size. */
  3716. lbq_buf_len = (qdev->ndev->mtu > 1500) ?
  3717. LARGE_BUFFER_MAX_SIZE : LARGE_BUFFER_MIN_SIZE;
  3718. qdev->lbq_buf_order = get_order(lbq_buf_len);
  3719. for (i = 0; i < qdev->rss_ring_count; i++) {
  3720. rx_ring = &qdev->rx_ring[i];
  3721. /* Set the new size. */
  3722. rx_ring->lbq_buf_size = lbq_buf_len;
  3723. }
  3724. status = ql_adapter_up(qdev);
  3725. if (status)
  3726. goto error;
  3727. return status;
  3728. error:
  3729. netif_alert(qdev, ifup, qdev->ndev,
  3730. "Driver up/down cycle failed, closing device.\n");
  3731. set_bit(QL_ADAPTER_UP, &qdev->flags);
  3732. dev_close(qdev->ndev);
  3733. return status;
  3734. }
  3735. static int qlge_change_mtu(struct net_device *ndev, int new_mtu)
  3736. {
  3737. struct ql_adapter *qdev = netdev_priv(ndev);
  3738. int status;
  3739. if (ndev->mtu == 1500 && new_mtu == 9000) {
  3740. netif_err(qdev, ifup, qdev->ndev, "Changing to jumbo MTU.\n");
  3741. } else if (ndev->mtu == 9000 && new_mtu == 1500) {
  3742. netif_err(qdev, ifup, qdev->ndev, "Changing to normal MTU.\n");
  3743. } else
  3744. return -EINVAL;
  3745. queue_delayed_work(qdev->workqueue,
  3746. &qdev->mpi_port_cfg_work, 3*HZ);
  3747. ndev->mtu = new_mtu;
  3748. if (!netif_running(qdev->ndev)) {
  3749. return 0;
  3750. }
  3751. status = ql_change_rx_buffers(qdev);
  3752. if (status) {
  3753. netif_err(qdev, ifup, qdev->ndev,
  3754. "Changing MTU failed.\n");
  3755. }
  3756. return status;
  3757. }
  3758. static struct net_device_stats *qlge_get_stats(struct net_device
  3759. *ndev)
  3760. {
  3761. struct ql_adapter *qdev = netdev_priv(ndev);
  3762. struct rx_ring *rx_ring = &qdev->rx_ring[0];
  3763. struct tx_ring *tx_ring = &qdev->tx_ring[0];
  3764. unsigned long pkts, mcast, dropped, errors, bytes;
  3765. int i;
  3766. /* Get RX stats. */
  3767. pkts = mcast = dropped = errors = bytes = 0;
  3768. for (i = 0; i < qdev->rss_ring_count; i++, rx_ring++) {
  3769. pkts += rx_ring->rx_packets;
  3770. bytes += rx_ring->rx_bytes;
  3771. dropped += rx_ring->rx_dropped;
  3772. errors += rx_ring->rx_errors;
  3773. mcast += rx_ring->rx_multicast;
  3774. }
  3775. ndev->stats.rx_packets = pkts;
  3776. ndev->stats.rx_bytes = bytes;
  3777. ndev->stats.rx_dropped = dropped;
  3778. ndev->stats.rx_errors = errors;
  3779. ndev->stats.multicast = mcast;
  3780. /* Get TX stats. */
  3781. pkts = errors = bytes = 0;
  3782. for (i = 0; i < qdev->tx_ring_count; i++, tx_ring++) {
  3783. pkts += tx_ring->tx_packets;
  3784. bytes += tx_ring->tx_bytes;
  3785. errors += tx_ring->tx_errors;
  3786. }
  3787. ndev->stats.tx_packets = pkts;
  3788. ndev->stats.tx_bytes = bytes;
  3789. ndev->stats.tx_errors = errors;
  3790. return &ndev->stats;
  3791. }
  3792. static void qlge_set_multicast_list(struct net_device *ndev)
  3793. {
  3794. struct ql_adapter *qdev = netdev_priv(ndev);
  3795. struct netdev_hw_addr *ha;
  3796. int i, status;
  3797. status = ql_sem_spinlock(qdev, SEM_RT_IDX_MASK);
  3798. if (status)
  3799. return;
  3800. /*
  3801. * Set or clear promiscuous mode if a
  3802. * transition is taking place.
  3803. */
  3804. if (ndev->flags & IFF_PROMISC) {
  3805. if (!test_bit(QL_PROMISCUOUS, &qdev->flags)) {
  3806. if (ql_set_routing_reg
  3807. (qdev, RT_IDX_PROMISCUOUS_SLOT, RT_IDX_VALID, 1)) {
  3808. netif_err(qdev, hw, qdev->ndev,
  3809. "Failed to set promiscuous mode.\n");
  3810. } else {
  3811. set_bit(QL_PROMISCUOUS, &qdev->flags);
  3812. }
  3813. }
  3814. } else {
  3815. if (test_bit(QL_PROMISCUOUS, &qdev->flags)) {
  3816. if (ql_set_routing_reg
  3817. (qdev, RT_IDX_PROMISCUOUS_SLOT, RT_IDX_VALID, 0)) {
  3818. netif_err(qdev, hw, qdev->ndev,
  3819. "Failed to clear promiscuous mode.\n");
  3820. } else {
  3821. clear_bit(QL_PROMISCUOUS, &qdev->flags);
  3822. }
  3823. }
  3824. }
  3825. /*
  3826. * Set or clear all multicast mode if a
  3827. * transition is taking place.
  3828. */
  3829. if ((ndev->flags & IFF_ALLMULTI) ||
  3830. (netdev_mc_count(ndev) > MAX_MULTICAST_ENTRIES)) {
  3831. if (!test_bit(QL_ALLMULTI, &qdev->flags)) {
  3832. if (ql_set_routing_reg
  3833. (qdev, RT_IDX_ALLMULTI_SLOT, RT_IDX_MCAST, 1)) {
  3834. netif_err(qdev, hw, qdev->ndev,
  3835. "Failed to set all-multi mode.\n");
  3836. } else {
  3837. set_bit(QL_ALLMULTI, &qdev->flags);
  3838. }
  3839. }
  3840. } else {
  3841. if (test_bit(QL_ALLMULTI, &qdev->flags)) {
  3842. if (ql_set_routing_reg
  3843. (qdev, RT_IDX_ALLMULTI_SLOT, RT_IDX_MCAST, 0)) {
  3844. netif_err(qdev, hw, qdev->ndev,
  3845. "Failed to clear all-multi mode.\n");
  3846. } else {
  3847. clear_bit(QL_ALLMULTI, &qdev->flags);
  3848. }
  3849. }
  3850. }
  3851. if (!netdev_mc_empty(ndev)) {
  3852. status = ql_sem_spinlock(qdev, SEM_MAC_ADDR_MASK);
  3853. if (status)
  3854. goto exit;
  3855. i = 0;
  3856. netdev_for_each_mc_addr(ha, ndev) {
  3857. if (ql_set_mac_addr_reg(qdev, (u8 *) ha->addr,
  3858. MAC_ADDR_TYPE_MULTI_MAC, i)) {
  3859. netif_err(qdev, hw, qdev->ndev,
  3860. "Failed to loadmulticast address.\n");
  3861. ql_sem_unlock(qdev, SEM_MAC_ADDR_MASK);
  3862. goto exit;
  3863. }
  3864. i++;
  3865. }
  3866. ql_sem_unlock(qdev, SEM_MAC_ADDR_MASK);
  3867. if (ql_set_routing_reg
  3868. (qdev, RT_IDX_MCAST_MATCH_SLOT, RT_IDX_MCAST_MATCH, 1)) {
  3869. netif_err(qdev, hw, qdev->ndev,
  3870. "Failed to set multicast match mode.\n");
  3871. } else {
  3872. set_bit(QL_ALLMULTI, &qdev->flags);
  3873. }
  3874. }
  3875. exit:
  3876. ql_sem_unlock(qdev, SEM_RT_IDX_MASK);
  3877. }
  3878. static int qlge_set_mac_address(struct net_device *ndev, void *p)
  3879. {
  3880. struct ql_adapter *qdev = netdev_priv(ndev);
  3881. struct sockaddr *addr = p;
  3882. int status;
  3883. if (!is_valid_ether_addr(addr->sa_data))
  3884. return -EADDRNOTAVAIL;
  3885. memcpy(ndev->dev_addr, addr->sa_data, ndev->addr_len);
  3886. /* Update local copy of current mac address. */
  3887. memcpy(qdev->current_mac_addr, ndev->dev_addr, ndev->addr_len);
  3888. status = ql_sem_spinlock(qdev, SEM_MAC_ADDR_MASK);
  3889. if (status)
  3890. return status;
  3891. status = ql_set_mac_addr_reg(qdev, (u8 *) ndev->dev_addr,
  3892. MAC_ADDR_TYPE_CAM_MAC, qdev->func * MAX_CQ);
  3893. if (status)
  3894. netif_err(qdev, hw, qdev->ndev, "Failed to load MAC address.\n");
  3895. ql_sem_unlock(qdev, SEM_MAC_ADDR_MASK);
  3896. return status;
  3897. }
  3898. static void qlge_tx_timeout(struct net_device *ndev)
  3899. {
  3900. struct ql_adapter *qdev = netdev_priv(ndev);
  3901. ql_queue_asic_error(qdev);
  3902. }
  3903. static void ql_asic_reset_work(struct work_struct *work)
  3904. {
  3905. struct ql_adapter *qdev =
  3906. container_of(work, struct ql_adapter, asic_reset_work.work);
  3907. int status;
  3908. rtnl_lock();
  3909. status = ql_adapter_down(qdev);
  3910. if (status)
  3911. goto error;
  3912. status = ql_adapter_up(qdev);
  3913. if (status)
  3914. goto error;
  3915. /* Restore rx mode. */
  3916. clear_bit(QL_ALLMULTI, &qdev->flags);
  3917. clear_bit(QL_PROMISCUOUS, &qdev->flags);
  3918. qlge_set_multicast_list(qdev->ndev);
  3919. rtnl_unlock();
  3920. return;
  3921. error:
  3922. netif_alert(qdev, ifup, qdev->ndev,
  3923. "Driver up/down cycle failed, closing device\n");
  3924. set_bit(QL_ADAPTER_UP, &qdev->flags);
  3925. dev_close(qdev->ndev);
  3926. rtnl_unlock();
  3927. }
  3928. static const struct nic_operations qla8012_nic_ops = {
  3929. .get_flash = ql_get_8012_flash_params,
  3930. .port_initialize = ql_8012_port_initialize,
  3931. };
  3932. static const struct nic_operations qla8000_nic_ops = {
  3933. .get_flash = ql_get_8000_flash_params,
  3934. .port_initialize = ql_8000_port_initialize,
  3935. };
  3936. /* Find the pcie function number for the other NIC
  3937. * on this chip. Since both NIC functions share a
  3938. * common firmware we have the lowest enabled function
  3939. * do any common work. Examples would be resetting
  3940. * after a fatal firmware error, or doing a firmware
  3941. * coredump.
  3942. */
  3943. static int ql_get_alt_pcie_func(struct ql_adapter *qdev)
  3944. {
  3945. int status = 0;
  3946. u32 temp;
  3947. u32 nic_func1, nic_func2;
  3948. status = ql_read_mpi_reg(qdev, MPI_TEST_FUNC_PORT_CFG,
  3949. &temp);
  3950. if (status)
  3951. return status;
  3952. nic_func1 = ((temp >> MPI_TEST_NIC1_FUNC_SHIFT) &
  3953. MPI_TEST_NIC_FUNC_MASK);
  3954. nic_func2 = ((temp >> MPI_TEST_NIC2_FUNC_SHIFT) &
  3955. MPI_TEST_NIC_FUNC_MASK);
  3956. if (qdev->func == nic_func1)
  3957. qdev->alt_func = nic_func2;
  3958. else if (qdev->func == nic_func2)
  3959. qdev->alt_func = nic_func1;
  3960. else
  3961. status = -EIO;
  3962. return status;
  3963. }
  3964. static int ql_get_board_info(struct ql_adapter *qdev)
  3965. {
  3966. int status;
  3967. qdev->func =
  3968. (ql_read32(qdev, STS) & STS_FUNC_ID_MASK) >> STS_FUNC_ID_SHIFT;
  3969. if (qdev->func > 3)
  3970. return -EIO;
  3971. status = ql_get_alt_pcie_func(qdev);
  3972. if (status)
  3973. return status;
  3974. qdev->port = (qdev->func < qdev->alt_func) ? 0 : 1;
  3975. if (qdev->port) {
  3976. qdev->xg_sem_mask = SEM_XGMAC1_MASK;
  3977. qdev->port_link_up = STS_PL1;
  3978. qdev->port_init = STS_PI1;
  3979. qdev->mailbox_in = PROC_ADDR_MPI_RISC | PROC_ADDR_FUNC2_MBI;
  3980. qdev->mailbox_out = PROC_ADDR_MPI_RISC | PROC_ADDR_FUNC2_MBO;
  3981. } else {
  3982. qdev->xg_sem_mask = SEM_XGMAC0_MASK;
  3983. qdev->port_link_up = STS_PL0;
  3984. qdev->port_init = STS_PI0;
  3985. qdev->mailbox_in = PROC_ADDR_MPI_RISC | PROC_ADDR_FUNC0_MBI;
  3986. qdev->mailbox_out = PROC_ADDR_MPI_RISC | PROC_ADDR_FUNC0_MBO;
  3987. }
  3988. qdev->chip_rev_id = ql_read32(qdev, REV_ID);
  3989. qdev->device_id = qdev->pdev->device;
  3990. if (qdev->device_id == QLGE_DEVICE_ID_8012)
  3991. qdev->nic_ops = &qla8012_nic_ops;
  3992. else if (qdev->device_id == QLGE_DEVICE_ID_8000)
  3993. qdev->nic_ops = &qla8000_nic_ops;
  3994. return status;
  3995. }
  3996. static void ql_release_all(struct pci_dev *pdev)
  3997. {
  3998. struct net_device *ndev = pci_get_drvdata(pdev);
  3999. struct ql_adapter *qdev = netdev_priv(ndev);
  4000. if (qdev->workqueue) {
  4001. destroy_workqueue(qdev->workqueue);
  4002. qdev->workqueue = NULL;
  4003. }
  4004. if (qdev->reg_base)
  4005. iounmap(qdev->reg_base);
  4006. if (qdev->doorbell_area)
  4007. iounmap(qdev->doorbell_area);
  4008. vfree(qdev->mpi_coredump);
  4009. pci_release_regions(pdev);
  4010. pci_set_drvdata(pdev, NULL);
  4011. }
  4012. static int ql_init_device(struct pci_dev *pdev, struct net_device *ndev,
  4013. int cards_found)
  4014. {
  4015. struct ql_adapter *qdev = netdev_priv(ndev);
  4016. int err = 0;
  4017. memset((void *)qdev, 0, sizeof(*qdev));
  4018. err = pci_enable_device(pdev);
  4019. if (err) {
  4020. dev_err(&pdev->dev, "PCI device enable failed.\n");
  4021. return err;
  4022. }
  4023. qdev->ndev = ndev;
  4024. qdev->pdev = pdev;
  4025. pci_set_drvdata(pdev, ndev);
  4026. /* Set PCIe read request size */
  4027. err = pcie_set_readrq(pdev, 4096);
  4028. if (err) {
  4029. dev_err(&pdev->dev, "Set readrq failed.\n");
  4030. goto err_out1;
  4031. }
  4032. err = pci_request_regions(pdev, DRV_NAME);
  4033. if (err) {
  4034. dev_err(&pdev->dev, "PCI region request failed.\n");
  4035. return err;
  4036. }
  4037. pci_set_master(pdev);
  4038. if (!pci_set_dma_mask(pdev, DMA_BIT_MASK(64))) {
  4039. set_bit(QL_DMA64, &qdev->flags);
  4040. err = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(64));
  4041. } else {
  4042. err = pci_set_dma_mask(pdev, DMA_BIT_MASK(32));
  4043. if (!err)
  4044. err = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(32));
  4045. }
  4046. if (err) {
  4047. dev_err(&pdev->dev, "No usable DMA configuration.\n");
  4048. goto err_out2;
  4049. }
  4050. /* Set PCIe reset type for EEH to fundamental. */
  4051. pdev->needs_freset = 1;
  4052. pci_save_state(pdev);
  4053. qdev->reg_base =
  4054. ioremap_nocache(pci_resource_start(pdev, 1),
  4055. pci_resource_len(pdev, 1));
  4056. if (!qdev->reg_base) {
  4057. dev_err(&pdev->dev, "Register mapping failed.\n");
  4058. err = -ENOMEM;
  4059. goto err_out2;
  4060. }
  4061. qdev->doorbell_area_size = pci_resource_len(pdev, 3);
  4062. qdev->doorbell_area =
  4063. ioremap_nocache(pci_resource_start(pdev, 3),
  4064. pci_resource_len(pdev, 3));
  4065. if (!qdev->doorbell_area) {
  4066. dev_err(&pdev->dev, "Doorbell register mapping failed.\n");
  4067. err = -ENOMEM;
  4068. goto err_out2;
  4069. }
  4070. err = ql_get_board_info(qdev);
  4071. if (err) {
  4072. dev_err(&pdev->dev, "Register access failed.\n");
  4073. err = -EIO;
  4074. goto err_out2;
  4075. }
  4076. qdev->msg_enable = netif_msg_init(debug, default_msg);
  4077. spin_lock_init(&qdev->hw_lock);
  4078. spin_lock_init(&qdev->stats_lock);
  4079. if (qlge_mpi_coredump) {
  4080. qdev->mpi_coredump =
  4081. vmalloc(sizeof(struct ql_mpi_coredump));
  4082. if (qdev->mpi_coredump == NULL) {
  4083. err = -ENOMEM;
  4084. goto err_out2;
  4085. }
  4086. if (qlge_force_coredump)
  4087. set_bit(QL_FRC_COREDUMP, &qdev->flags);
  4088. }
  4089. /* make sure the EEPROM is good */
  4090. err = qdev->nic_ops->get_flash(qdev);
  4091. if (err) {
  4092. dev_err(&pdev->dev, "Invalid FLASH.\n");
  4093. goto err_out2;
  4094. }
  4095. /* Keep local copy of current mac address. */
  4096. memcpy(qdev->current_mac_addr, ndev->dev_addr, ndev->addr_len);
  4097. /* Set up the default ring sizes. */
  4098. qdev->tx_ring_size = NUM_TX_RING_ENTRIES;
  4099. qdev->rx_ring_size = NUM_RX_RING_ENTRIES;
  4100. /* Set up the coalescing parameters. */
  4101. qdev->rx_coalesce_usecs = DFLT_COALESCE_WAIT;
  4102. qdev->tx_coalesce_usecs = DFLT_COALESCE_WAIT;
  4103. qdev->rx_max_coalesced_frames = DFLT_INTER_FRAME_WAIT;
  4104. qdev->tx_max_coalesced_frames = DFLT_INTER_FRAME_WAIT;
  4105. /*
  4106. * Set up the operating parameters.
  4107. */
  4108. qdev->workqueue = create_singlethread_workqueue(ndev->name);
  4109. INIT_DELAYED_WORK(&qdev->asic_reset_work, ql_asic_reset_work);
  4110. INIT_DELAYED_WORK(&qdev->mpi_reset_work, ql_mpi_reset_work);
  4111. INIT_DELAYED_WORK(&qdev->mpi_work, ql_mpi_work);
  4112. INIT_DELAYED_WORK(&qdev->mpi_port_cfg_work, ql_mpi_port_cfg_work);
  4113. INIT_DELAYED_WORK(&qdev->mpi_idc_work, ql_mpi_idc_work);
  4114. INIT_DELAYED_WORK(&qdev->mpi_core_to_log, ql_mpi_core_to_log);
  4115. init_completion(&qdev->ide_completion);
  4116. mutex_init(&qdev->mpi_mutex);
  4117. if (!cards_found) {
  4118. dev_info(&pdev->dev, "%s\n", DRV_STRING);
  4119. dev_info(&pdev->dev, "Driver name: %s, Version: %s.\n",
  4120. DRV_NAME, DRV_VERSION);
  4121. }
  4122. return 0;
  4123. err_out2:
  4124. ql_release_all(pdev);
  4125. err_out1:
  4126. pci_disable_device(pdev);
  4127. return err;
  4128. }
  4129. static const struct net_device_ops qlge_netdev_ops = {
  4130. .ndo_open = qlge_open,
  4131. .ndo_stop = qlge_close,
  4132. .ndo_start_xmit = qlge_send,
  4133. .ndo_change_mtu = qlge_change_mtu,
  4134. .ndo_get_stats = qlge_get_stats,
  4135. .ndo_set_rx_mode = qlge_set_multicast_list,
  4136. .ndo_set_mac_address = qlge_set_mac_address,
  4137. .ndo_validate_addr = eth_validate_addr,
  4138. .ndo_tx_timeout = qlge_tx_timeout,
  4139. .ndo_fix_features = qlge_fix_features,
  4140. .ndo_set_features = qlge_set_features,
  4141. .ndo_vlan_rx_add_vid = qlge_vlan_rx_add_vid,
  4142. .ndo_vlan_rx_kill_vid = qlge_vlan_rx_kill_vid,
  4143. };
  4144. static void ql_timer(unsigned long data)
  4145. {
  4146. struct ql_adapter *qdev = (struct ql_adapter *)data;
  4147. u32 var = 0;
  4148. var = ql_read32(qdev, STS);
  4149. if (pci_channel_offline(qdev->pdev)) {
  4150. netif_err(qdev, ifup, qdev->ndev, "EEH STS = 0x%.08x.\n", var);
  4151. return;
  4152. }
  4153. mod_timer(&qdev->timer, jiffies + (5*HZ));
  4154. }
  4155. static int qlge_probe(struct pci_dev *pdev,
  4156. const struct pci_device_id *pci_entry)
  4157. {
  4158. struct net_device *ndev = NULL;
  4159. struct ql_adapter *qdev = NULL;
  4160. static int cards_found = 0;
  4161. int err = 0;
  4162. ndev = alloc_etherdev_mq(sizeof(struct ql_adapter),
  4163. min(MAX_CPUS, netif_get_num_default_rss_queues()));
  4164. if (!ndev)
  4165. return -ENOMEM;
  4166. err = ql_init_device(pdev, ndev, cards_found);
  4167. if (err < 0) {
  4168. free_netdev(ndev);
  4169. return err;
  4170. }
  4171. qdev = netdev_priv(ndev);
  4172. SET_NETDEV_DEV(ndev, &pdev->dev);
  4173. ndev->hw_features = NETIF_F_SG | NETIF_F_IP_CSUM |
  4174. NETIF_F_TSO | NETIF_F_TSO_ECN |
  4175. NETIF_F_HW_VLAN_CTAG_TX | NETIF_F_RXCSUM;
  4176. ndev->features = ndev->hw_features |
  4177. NETIF_F_HW_VLAN_CTAG_RX | NETIF_F_HW_VLAN_CTAG_FILTER;
  4178. ndev->vlan_features = ndev->hw_features;
  4179. if (test_bit(QL_DMA64, &qdev->flags))
  4180. ndev->features |= NETIF_F_HIGHDMA;
  4181. /*
  4182. * Set up net_device structure.
  4183. */
  4184. ndev->tx_queue_len = qdev->tx_ring_size;
  4185. ndev->irq = pdev->irq;
  4186. ndev->netdev_ops = &qlge_netdev_ops;
  4187. SET_ETHTOOL_OPS(ndev, &qlge_ethtool_ops);
  4188. ndev->watchdog_timeo = 10 * HZ;
  4189. err = register_netdev(ndev);
  4190. if (err) {
  4191. dev_err(&pdev->dev, "net device registration failed.\n");
  4192. ql_release_all(pdev);
  4193. pci_disable_device(pdev);
  4194. return err;
  4195. }
  4196. /* Start up the timer to trigger EEH if
  4197. * the bus goes dead
  4198. */
  4199. init_timer_deferrable(&qdev->timer);
  4200. qdev->timer.data = (unsigned long)qdev;
  4201. qdev->timer.function = ql_timer;
  4202. qdev->timer.expires = jiffies + (5*HZ);
  4203. add_timer(&qdev->timer);
  4204. ql_link_off(qdev);
  4205. ql_display_dev_info(ndev);
  4206. atomic_set(&qdev->lb_count, 0);
  4207. cards_found++;
  4208. return 0;
  4209. }
  4210. netdev_tx_t ql_lb_send(struct sk_buff *skb, struct net_device *ndev)
  4211. {
  4212. return qlge_send(skb, ndev);
  4213. }
  4214. int ql_clean_lb_rx_ring(struct rx_ring *rx_ring, int budget)
  4215. {
  4216. return ql_clean_inbound_rx_ring(rx_ring, budget);
  4217. }
  4218. static void qlge_remove(struct pci_dev *pdev)
  4219. {
  4220. struct net_device *ndev = pci_get_drvdata(pdev);
  4221. struct ql_adapter *qdev = netdev_priv(ndev);
  4222. del_timer_sync(&qdev->timer);
  4223. ql_cancel_all_work_sync(qdev);
  4224. unregister_netdev(ndev);
  4225. ql_release_all(pdev);
  4226. pci_disable_device(pdev);
  4227. free_netdev(ndev);
  4228. }
  4229. /* Clean up resources without touching hardware. */
  4230. static void ql_eeh_close(struct net_device *ndev)
  4231. {
  4232. int i;
  4233. struct ql_adapter *qdev = netdev_priv(ndev);
  4234. if (netif_carrier_ok(ndev)) {
  4235. netif_carrier_off(ndev);
  4236. netif_stop_queue(ndev);
  4237. }
  4238. /* Disabling the timer */
  4239. del_timer_sync(&qdev->timer);
  4240. ql_cancel_all_work_sync(qdev);
  4241. for (i = 0; i < qdev->rss_ring_count; i++)
  4242. netif_napi_del(&qdev->rx_ring[i].napi);
  4243. clear_bit(QL_ADAPTER_UP, &qdev->flags);
  4244. ql_tx_ring_clean(qdev);
  4245. ql_free_rx_buffers(qdev);
  4246. ql_release_adapter_resources(qdev);
  4247. }
  4248. /*
  4249. * This callback is called by the PCI subsystem whenever
  4250. * a PCI bus error is detected.
  4251. */
  4252. static pci_ers_result_t qlge_io_error_detected(struct pci_dev *pdev,
  4253. enum pci_channel_state state)
  4254. {
  4255. struct net_device *ndev = pci_get_drvdata(pdev);
  4256. struct ql_adapter *qdev = netdev_priv(ndev);
  4257. switch (state) {
  4258. case pci_channel_io_normal:
  4259. return PCI_ERS_RESULT_CAN_RECOVER;
  4260. case pci_channel_io_frozen:
  4261. netif_device_detach(ndev);
  4262. if (netif_running(ndev))
  4263. ql_eeh_close(ndev);
  4264. pci_disable_device(pdev);
  4265. return PCI_ERS_RESULT_NEED_RESET;
  4266. case pci_channel_io_perm_failure:
  4267. dev_err(&pdev->dev,
  4268. "%s: pci_channel_io_perm_failure.\n", __func__);
  4269. ql_eeh_close(ndev);
  4270. set_bit(QL_EEH_FATAL, &qdev->flags);
  4271. return PCI_ERS_RESULT_DISCONNECT;
  4272. }
  4273. /* Request a slot reset. */
  4274. return PCI_ERS_RESULT_NEED_RESET;
  4275. }
  4276. /*
  4277. * This callback is called after the PCI buss has been reset.
  4278. * Basically, this tries to restart the card from scratch.
  4279. * This is a shortened version of the device probe/discovery code,
  4280. * it resembles the first-half of the () routine.
  4281. */
  4282. static pci_ers_result_t qlge_io_slot_reset(struct pci_dev *pdev)
  4283. {
  4284. struct net_device *ndev = pci_get_drvdata(pdev);
  4285. struct ql_adapter *qdev = netdev_priv(ndev);
  4286. pdev->error_state = pci_channel_io_normal;
  4287. pci_restore_state(pdev);
  4288. if (pci_enable_device(pdev)) {
  4289. netif_err(qdev, ifup, qdev->ndev,
  4290. "Cannot re-enable PCI device after reset.\n");
  4291. return PCI_ERS_RESULT_DISCONNECT;
  4292. }
  4293. pci_set_master(pdev);
  4294. if (ql_adapter_reset(qdev)) {
  4295. netif_err(qdev, drv, qdev->ndev, "reset FAILED!\n");
  4296. set_bit(QL_EEH_FATAL, &qdev->flags);
  4297. return PCI_ERS_RESULT_DISCONNECT;
  4298. }
  4299. return PCI_ERS_RESULT_RECOVERED;
  4300. }
  4301. static void qlge_io_resume(struct pci_dev *pdev)
  4302. {
  4303. struct net_device *ndev = pci_get_drvdata(pdev);
  4304. struct ql_adapter *qdev = netdev_priv(ndev);
  4305. int err = 0;
  4306. if (netif_running(ndev)) {
  4307. err = qlge_open(ndev);
  4308. if (err) {
  4309. netif_err(qdev, ifup, qdev->ndev,
  4310. "Device initialization failed after reset.\n");
  4311. return;
  4312. }
  4313. } else {
  4314. netif_err(qdev, ifup, qdev->ndev,
  4315. "Device was not running prior to EEH.\n");
  4316. }
  4317. mod_timer(&qdev->timer, jiffies + (5*HZ));
  4318. netif_device_attach(ndev);
  4319. }
  4320. static const struct pci_error_handlers qlge_err_handler = {
  4321. .error_detected = qlge_io_error_detected,
  4322. .slot_reset = qlge_io_slot_reset,
  4323. .resume = qlge_io_resume,
  4324. };
  4325. static int qlge_suspend(struct pci_dev *pdev, pm_message_t state)
  4326. {
  4327. struct net_device *ndev = pci_get_drvdata(pdev);
  4328. struct ql_adapter *qdev = netdev_priv(ndev);
  4329. int err;
  4330. netif_device_detach(ndev);
  4331. del_timer_sync(&qdev->timer);
  4332. if (netif_running(ndev)) {
  4333. err = ql_adapter_down(qdev);
  4334. if (!err)
  4335. return err;
  4336. }
  4337. ql_wol(qdev);
  4338. err = pci_save_state(pdev);
  4339. if (err)
  4340. return err;
  4341. pci_disable_device(pdev);
  4342. pci_set_power_state(pdev, pci_choose_state(pdev, state));
  4343. return 0;
  4344. }
  4345. #ifdef CONFIG_PM
  4346. static int qlge_resume(struct pci_dev *pdev)
  4347. {
  4348. struct net_device *ndev = pci_get_drvdata(pdev);
  4349. struct ql_adapter *qdev = netdev_priv(ndev);
  4350. int err;
  4351. pci_set_power_state(pdev, PCI_D0);
  4352. pci_restore_state(pdev);
  4353. err = pci_enable_device(pdev);
  4354. if (err) {
  4355. netif_err(qdev, ifup, qdev->ndev, "Cannot enable PCI device from suspend\n");
  4356. return err;
  4357. }
  4358. pci_set_master(pdev);
  4359. pci_enable_wake(pdev, PCI_D3hot, 0);
  4360. pci_enable_wake(pdev, PCI_D3cold, 0);
  4361. if (netif_running(ndev)) {
  4362. err = ql_adapter_up(qdev);
  4363. if (err)
  4364. return err;
  4365. }
  4366. mod_timer(&qdev->timer, jiffies + (5*HZ));
  4367. netif_device_attach(ndev);
  4368. return 0;
  4369. }
  4370. #endif /* CONFIG_PM */
  4371. static void qlge_shutdown(struct pci_dev *pdev)
  4372. {
  4373. qlge_suspend(pdev, PMSG_SUSPEND);
  4374. }
  4375. static struct pci_driver qlge_driver = {
  4376. .name = DRV_NAME,
  4377. .id_table = qlge_pci_tbl,
  4378. .probe = qlge_probe,
  4379. .remove = qlge_remove,
  4380. #ifdef CONFIG_PM
  4381. .suspend = qlge_suspend,
  4382. .resume = qlge_resume,
  4383. #endif
  4384. .shutdown = qlge_shutdown,
  4385. .err_handler = &qlge_err_handler
  4386. };
  4387. static int __init qlge_init_module(void)
  4388. {
  4389. return pci_register_driver(&qlge_driver);
  4390. }
  4391. static void __exit qlge_exit(void)
  4392. {
  4393. pci_unregister_driver(&qlge_driver);
  4394. }
  4395. module_init(qlge_init_module);
  4396. module_exit(qlge_exit);