qla_isr.c 81 KB

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  1. /*
  2. * QLogic Fibre Channel HBA Driver
  3. * Copyright (c) 2003-2013 QLogic Corporation
  4. *
  5. * See LICENSE.qla2xxx for copyright and licensing details.
  6. */
  7. #include "qla_def.h"
  8. #include "qla_target.h"
  9. #include <linux/delay.h>
  10. #include <linux/slab.h>
  11. #include <scsi/scsi_tcq.h>
  12. #include <scsi/scsi_bsg_fc.h>
  13. #include <scsi/scsi_eh.h>
  14. #include "qla_target.h"
  15. static void qla2x00_mbx_completion(scsi_qla_host_t *, uint16_t);
  16. static void qla2x00_process_completed_request(struct scsi_qla_host *,
  17. struct req_que *, uint32_t);
  18. static void qla2x00_status_entry(scsi_qla_host_t *, struct rsp_que *, void *);
  19. static void qla2x00_status_cont_entry(struct rsp_que *, sts_cont_entry_t *);
  20. static void qla2x00_error_entry(scsi_qla_host_t *, struct rsp_que *,
  21. sts_entry_t *);
  22. /**
  23. * qla2100_intr_handler() - Process interrupts for the ISP2100 and ISP2200.
  24. * @irq:
  25. * @dev_id: SCSI driver HA context
  26. *
  27. * Called by system whenever the host adapter generates an interrupt.
  28. *
  29. * Returns handled flag.
  30. */
  31. irqreturn_t
  32. qla2100_intr_handler(int irq, void *dev_id)
  33. {
  34. scsi_qla_host_t *vha;
  35. struct qla_hw_data *ha;
  36. struct device_reg_2xxx __iomem *reg;
  37. int status;
  38. unsigned long iter;
  39. uint16_t hccr;
  40. uint16_t mb[4];
  41. struct rsp_que *rsp;
  42. unsigned long flags;
  43. rsp = (struct rsp_que *) dev_id;
  44. if (!rsp) {
  45. ql_log(ql_log_info, NULL, 0x505d,
  46. "%s: NULL response queue pointer.\n", __func__);
  47. return (IRQ_NONE);
  48. }
  49. ha = rsp->hw;
  50. reg = &ha->iobase->isp;
  51. status = 0;
  52. spin_lock_irqsave(&ha->hardware_lock, flags);
  53. vha = pci_get_drvdata(ha->pdev);
  54. for (iter = 50; iter--; ) {
  55. hccr = RD_REG_WORD(&reg->hccr);
  56. if (hccr & HCCR_RISC_PAUSE) {
  57. if (pci_channel_offline(ha->pdev))
  58. break;
  59. /*
  60. * Issue a "HARD" reset in order for the RISC interrupt
  61. * bit to be cleared. Schedule a big hammer to get
  62. * out of the RISC PAUSED state.
  63. */
  64. WRT_REG_WORD(&reg->hccr, HCCR_RESET_RISC);
  65. RD_REG_WORD(&reg->hccr);
  66. ha->isp_ops->fw_dump(vha, 1);
  67. set_bit(ISP_ABORT_NEEDED, &vha->dpc_flags);
  68. break;
  69. } else if ((RD_REG_WORD(&reg->istatus) & ISR_RISC_INT) == 0)
  70. break;
  71. if (RD_REG_WORD(&reg->semaphore) & BIT_0) {
  72. WRT_REG_WORD(&reg->hccr, HCCR_CLR_RISC_INT);
  73. RD_REG_WORD(&reg->hccr);
  74. /* Get mailbox data. */
  75. mb[0] = RD_MAILBOX_REG(ha, reg, 0);
  76. if (mb[0] > 0x3fff && mb[0] < 0x8000) {
  77. qla2x00_mbx_completion(vha, mb[0]);
  78. status |= MBX_INTERRUPT;
  79. } else if (mb[0] > 0x7fff && mb[0] < 0xc000) {
  80. mb[1] = RD_MAILBOX_REG(ha, reg, 1);
  81. mb[2] = RD_MAILBOX_REG(ha, reg, 2);
  82. mb[3] = RD_MAILBOX_REG(ha, reg, 3);
  83. qla2x00_async_event(vha, rsp, mb);
  84. } else {
  85. /*EMPTY*/
  86. ql_dbg(ql_dbg_async, vha, 0x5025,
  87. "Unrecognized interrupt type (%d).\n",
  88. mb[0]);
  89. }
  90. /* Release mailbox registers. */
  91. WRT_REG_WORD(&reg->semaphore, 0);
  92. RD_REG_WORD(&reg->semaphore);
  93. } else {
  94. qla2x00_process_response_queue(rsp);
  95. WRT_REG_WORD(&reg->hccr, HCCR_CLR_RISC_INT);
  96. RD_REG_WORD(&reg->hccr);
  97. }
  98. }
  99. spin_unlock_irqrestore(&ha->hardware_lock, flags);
  100. if (test_bit(MBX_INTR_WAIT, &ha->mbx_cmd_flags) &&
  101. (status & MBX_INTERRUPT) && ha->flags.mbox_int) {
  102. set_bit(MBX_INTERRUPT, &ha->mbx_cmd_flags);
  103. complete(&ha->mbx_intr_comp);
  104. }
  105. return (IRQ_HANDLED);
  106. }
  107. /**
  108. * qla2300_intr_handler() - Process interrupts for the ISP23xx and ISP63xx.
  109. * @irq:
  110. * @dev_id: SCSI driver HA context
  111. *
  112. * Called by system whenever the host adapter generates an interrupt.
  113. *
  114. * Returns handled flag.
  115. */
  116. irqreturn_t
  117. qla2300_intr_handler(int irq, void *dev_id)
  118. {
  119. scsi_qla_host_t *vha;
  120. struct device_reg_2xxx __iomem *reg;
  121. int status;
  122. unsigned long iter;
  123. uint32_t stat;
  124. uint16_t hccr;
  125. uint16_t mb[4];
  126. struct rsp_que *rsp;
  127. struct qla_hw_data *ha;
  128. unsigned long flags;
  129. rsp = (struct rsp_que *) dev_id;
  130. if (!rsp) {
  131. ql_log(ql_log_info, NULL, 0x5058,
  132. "%s: NULL response queue pointer.\n", __func__);
  133. return (IRQ_NONE);
  134. }
  135. ha = rsp->hw;
  136. reg = &ha->iobase->isp;
  137. status = 0;
  138. spin_lock_irqsave(&ha->hardware_lock, flags);
  139. vha = pci_get_drvdata(ha->pdev);
  140. for (iter = 50; iter--; ) {
  141. stat = RD_REG_DWORD(&reg->u.isp2300.host_status);
  142. if (stat & HSR_RISC_PAUSED) {
  143. if (unlikely(pci_channel_offline(ha->pdev)))
  144. break;
  145. hccr = RD_REG_WORD(&reg->hccr);
  146. if (hccr & (BIT_15 | BIT_13 | BIT_11 | BIT_8))
  147. ql_log(ql_log_warn, vha, 0x5026,
  148. "Parity error -- HCCR=%x, Dumping "
  149. "firmware.\n", hccr);
  150. else
  151. ql_log(ql_log_warn, vha, 0x5027,
  152. "RISC paused -- HCCR=%x, Dumping "
  153. "firmware.\n", hccr);
  154. /*
  155. * Issue a "HARD" reset in order for the RISC
  156. * interrupt bit to be cleared. Schedule a big
  157. * hammer to get out of the RISC PAUSED state.
  158. */
  159. WRT_REG_WORD(&reg->hccr, HCCR_RESET_RISC);
  160. RD_REG_WORD(&reg->hccr);
  161. ha->isp_ops->fw_dump(vha, 1);
  162. set_bit(ISP_ABORT_NEEDED, &vha->dpc_flags);
  163. break;
  164. } else if ((stat & HSR_RISC_INT) == 0)
  165. break;
  166. switch (stat & 0xff) {
  167. case 0x1:
  168. case 0x2:
  169. case 0x10:
  170. case 0x11:
  171. qla2x00_mbx_completion(vha, MSW(stat));
  172. status |= MBX_INTERRUPT;
  173. /* Release mailbox registers. */
  174. WRT_REG_WORD(&reg->semaphore, 0);
  175. break;
  176. case 0x12:
  177. mb[0] = MSW(stat);
  178. mb[1] = RD_MAILBOX_REG(ha, reg, 1);
  179. mb[2] = RD_MAILBOX_REG(ha, reg, 2);
  180. mb[3] = RD_MAILBOX_REG(ha, reg, 3);
  181. qla2x00_async_event(vha, rsp, mb);
  182. break;
  183. case 0x13:
  184. qla2x00_process_response_queue(rsp);
  185. break;
  186. case 0x15:
  187. mb[0] = MBA_CMPLT_1_16BIT;
  188. mb[1] = MSW(stat);
  189. qla2x00_async_event(vha, rsp, mb);
  190. break;
  191. case 0x16:
  192. mb[0] = MBA_SCSI_COMPLETION;
  193. mb[1] = MSW(stat);
  194. mb[2] = RD_MAILBOX_REG(ha, reg, 2);
  195. qla2x00_async_event(vha, rsp, mb);
  196. break;
  197. default:
  198. ql_dbg(ql_dbg_async, vha, 0x5028,
  199. "Unrecognized interrupt type (%d).\n", stat & 0xff);
  200. break;
  201. }
  202. WRT_REG_WORD(&reg->hccr, HCCR_CLR_RISC_INT);
  203. RD_REG_WORD_RELAXED(&reg->hccr);
  204. }
  205. spin_unlock_irqrestore(&ha->hardware_lock, flags);
  206. if (test_bit(MBX_INTR_WAIT, &ha->mbx_cmd_flags) &&
  207. (status & MBX_INTERRUPT) && ha->flags.mbox_int) {
  208. set_bit(MBX_INTERRUPT, &ha->mbx_cmd_flags);
  209. complete(&ha->mbx_intr_comp);
  210. }
  211. return (IRQ_HANDLED);
  212. }
  213. /**
  214. * qla2x00_mbx_completion() - Process mailbox command completions.
  215. * @ha: SCSI driver HA context
  216. * @mb0: Mailbox0 register
  217. */
  218. static void
  219. qla2x00_mbx_completion(scsi_qla_host_t *vha, uint16_t mb0)
  220. {
  221. uint16_t cnt;
  222. uint32_t mboxes;
  223. uint16_t __iomem *wptr;
  224. struct qla_hw_data *ha = vha->hw;
  225. struct device_reg_2xxx __iomem *reg = &ha->iobase->isp;
  226. /* Read all mbox registers? */
  227. mboxes = (1 << ha->mbx_count) - 1;
  228. if (!ha->mcp)
  229. ql_dbg(ql_dbg_async, vha, 0x5001, "MBX pointer ERROR.\n");
  230. else
  231. mboxes = ha->mcp->in_mb;
  232. /* Load return mailbox registers. */
  233. ha->flags.mbox_int = 1;
  234. ha->mailbox_out[0] = mb0;
  235. mboxes >>= 1;
  236. wptr = (uint16_t __iomem *)MAILBOX_REG(ha, reg, 1);
  237. for (cnt = 1; cnt < ha->mbx_count; cnt++) {
  238. if (IS_QLA2200(ha) && cnt == 8)
  239. wptr = (uint16_t __iomem *)MAILBOX_REG(ha, reg, 8);
  240. if ((cnt == 4 || cnt == 5) && (mboxes & BIT_0))
  241. ha->mailbox_out[cnt] = qla2x00_debounce_register(wptr);
  242. else if (mboxes & BIT_0)
  243. ha->mailbox_out[cnt] = RD_REG_WORD(wptr);
  244. wptr++;
  245. mboxes >>= 1;
  246. }
  247. }
  248. static void
  249. qla81xx_idc_event(scsi_qla_host_t *vha, uint16_t aen, uint16_t descr)
  250. {
  251. static char *event[] =
  252. { "Complete", "Request Notification", "Time Extension" };
  253. int rval;
  254. struct device_reg_24xx __iomem *reg24 = &vha->hw->iobase->isp24;
  255. uint16_t __iomem *wptr;
  256. uint16_t cnt, timeout, mb[QLA_IDC_ACK_REGS];
  257. /* Seed data -- mailbox1 -> mailbox7. */
  258. wptr = (uint16_t __iomem *)&reg24->mailbox1;
  259. for (cnt = 0; cnt < QLA_IDC_ACK_REGS; cnt++, wptr++)
  260. mb[cnt] = RD_REG_WORD(wptr);
  261. ql_dbg(ql_dbg_async, vha, 0x5021,
  262. "Inter-Driver Communication %s -- "
  263. "%04x %04x %04x %04x %04x %04x %04x.\n",
  264. event[aen & 0xff], mb[0], mb[1], mb[2], mb[3],
  265. mb[4], mb[5], mb[6]);
  266. if ((aen == MBA_IDC_COMPLETE && mb[1] >> 15)) {
  267. vha->hw->flags.idc_compl_status = 1;
  268. if (vha->hw->notify_dcbx_comp)
  269. complete(&vha->hw->dcbx_comp);
  270. }
  271. /* Acknowledgement needed? [Notify && non-zero timeout]. */
  272. timeout = (descr >> 8) & 0xf;
  273. if (aen != MBA_IDC_NOTIFY || !timeout)
  274. return;
  275. ql_dbg(ql_dbg_async, vha, 0x5022,
  276. "%lu Inter-Driver Communication %s -- ACK timeout=%d.\n",
  277. vha->host_no, event[aen & 0xff], timeout);
  278. rval = qla2x00_post_idc_ack_work(vha, mb);
  279. if (rval != QLA_SUCCESS)
  280. ql_log(ql_log_warn, vha, 0x5023,
  281. "IDC failed to post ACK.\n");
  282. }
  283. #define LS_UNKNOWN 2
  284. const char *
  285. qla2x00_get_link_speed_str(struct qla_hw_data *ha, uint16_t speed)
  286. {
  287. static const char * const link_speeds[] = {
  288. "1", "2", "?", "4", "8", "16", "10"
  289. };
  290. if (IS_QLA2100(ha) || IS_QLA2200(ha))
  291. return link_speeds[0];
  292. else if (speed == 0x13)
  293. return link_speeds[6];
  294. else if (speed < 6)
  295. return link_speeds[speed];
  296. else
  297. return link_speeds[LS_UNKNOWN];
  298. }
  299. static void
  300. qla83xx_handle_8200_aen(scsi_qla_host_t *vha, uint16_t *mb)
  301. {
  302. struct qla_hw_data *ha = vha->hw;
  303. /*
  304. * 8200 AEN Interpretation:
  305. * mb[0] = AEN code
  306. * mb[1] = AEN Reason code
  307. * mb[2] = LSW of Peg-Halt Status-1 Register
  308. * mb[6] = MSW of Peg-Halt Status-1 Register
  309. * mb[3] = LSW of Peg-Halt Status-2 register
  310. * mb[7] = MSW of Peg-Halt Status-2 register
  311. * mb[4] = IDC Device-State Register value
  312. * mb[5] = IDC Driver-Presence Register value
  313. */
  314. ql_dbg(ql_dbg_async, vha, 0x506b, "AEN Code: mb[0] = 0x%x AEN reason: "
  315. "mb[1] = 0x%x PH-status1: mb[2] = 0x%x PH-status1: mb[6] = 0x%x.\n",
  316. mb[0], mb[1], mb[2], mb[6]);
  317. ql_dbg(ql_dbg_async, vha, 0x506c, "PH-status2: mb[3] = 0x%x "
  318. "PH-status2: mb[7] = 0x%x Device-State: mb[4] = 0x%x "
  319. "Drv-Presence: mb[5] = 0x%x.\n", mb[3], mb[7], mb[4], mb[5]);
  320. if (mb[1] & (IDC_PEG_HALT_STATUS_CHANGE | IDC_NIC_FW_REPORTED_FAILURE |
  321. IDC_HEARTBEAT_FAILURE)) {
  322. ha->flags.nic_core_hung = 1;
  323. ql_log(ql_log_warn, vha, 0x5060,
  324. "83XX: F/W Error Reported: Check if reset required.\n");
  325. if (mb[1] & IDC_PEG_HALT_STATUS_CHANGE) {
  326. uint32_t protocol_engine_id, fw_err_code, err_level;
  327. /*
  328. * IDC_PEG_HALT_STATUS_CHANGE interpretation:
  329. * - PEG-Halt Status-1 Register:
  330. * (LSW = mb[2], MSW = mb[6])
  331. * Bits 0-7 = protocol-engine ID
  332. * Bits 8-28 = f/w error code
  333. * Bits 29-31 = Error-level
  334. * Error-level 0x1 = Non-Fatal error
  335. * Error-level 0x2 = Recoverable Fatal error
  336. * Error-level 0x4 = UnRecoverable Fatal error
  337. * - PEG-Halt Status-2 Register:
  338. * (LSW = mb[3], MSW = mb[7])
  339. */
  340. protocol_engine_id = (mb[2] & 0xff);
  341. fw_err_code = (((mb[2] & 0xff00) >> 8) |
  342. ((mb[6] & 0x1fff) << 8));
  343. err_level = ((mb[6] & 0xe000) >> 13);
  344. ql_log(ql_log_warn, vha, 0x5061, "PegHalt Status-1 "
  345. "Register: protocol_engine_id=0x%x "
  346. "fw_err_code=0x%x err_level=0x%x.\n",
  347. protocol_engine_id, fw_err_code, err_level);
  348. ql_log(ql_log_warn, vha, 0x5062, "PegHalt Status-2 "
  349. "Register: 0x%x%x.\n", mb[7], mb[3]);
  350. if (err_level == ERR_LEVEL_NON_FATAL) {
  351. ql_log(ql_log_warn, vha, 0x5063,
  352. "Not a fatal error, f/w has recovered "
  353. "iteself.\n");
  354. } else if (err_level == ERR_LEVEL_RECOVERABLE_FATAL) {
  355. ql_log(ql_log_fatal, vha, 0x5064,
  356. "Recoverable Fatal error: Chip reset "
  357. "required.\n");
  358. qla83xx_schedule_work(vha,
  359. QLA83XX_NIC_CORE_RESET);
  360. } else if (err_level == ERR_LEVEL_UNRECOVERABLE_FATAL) {
  361. ql_log(ql_log_fatal, vha, 0x5065,
  362. "Unrecoverable Fatal error: Set FAILED "
  363. "state, reboot required.\n");
  364. qla83xx_schedule_work(vha,
  365. QLA83XX_NIC_CORE_UNRECOVERABLE);
  366. }
  367. }
  368. if (mb[1] & IDC_NIC_FW_REPORTED_FAILURE) {
  369. uint16_t peg_fw_state, nw_interface_link_up;
  370. uint16_t nw_interface_signal_detect, sfp_status;
  371. uint16_t htbt_counter, htbt_monitor_enable;
  372. uint16_t sfp_additonal_info, sfp_multirate;
  373. uint16_t sfp_tx_fault, link_speed, dcbx_status;
  374. /*
  375. * IDC_NIC_FW_REPORTED_FAILURE interpretation:
  376. * - PEG-to-FC Status Register:
  377. * (LSW = mb[2], MSW = mb[6])
  378. * Bits 0-7 = Peg-Firmware state
  379. * Bit 8 = N/W Interface Link-up
  380. * Bit 9 = N/W Interface signal detected
  381. * Bits 10-11 = SFP Status
  382. * SFP Status 0x0 = SFP+ transceiver not expected
  383. * SFP Status 0x1 = SFP+ transceiver not present
  384. * SFP Status 0x2 = SFP+ transceiver invalid
  385. * SFP Status 0x3 = SFP+ transceiver present and
  386. * valid
  387. * Bits 12-14 = Heartbeat Counter
  388. * Bit 15 = Heartbeat Monitor Enable
  389. * Bits 16-17 = SFP Additional Info
  390. * SFP info 0x0 = Unregocnized transceiver for
  391. * Ethernet
  392. * SFP info 0x1 = SFP+ brand validation failed
  393. * SFP info 0x2 = SFP+ speed validation failed
  394. * SFP info 0x3 = SFP+ access error
  395. * Bit 18 = SFP Multirate
  396. * Bit 19 = SFP Tx Fault
  397. * Bits 20-22 = Link Speed
  398. * Bits 23-27 = Reserved
  399. * Bits 28-30 = DCBX Status
  400. * DCBX Status 0x0 = DCBX Disabled
  401. * DCBX Status 0x1 = DCBX Enabled
  402. * DCBX Status 0x2 = DCBX Exchange error
  403. * Bit 31 = Reserved
  404. */
  405. peg_fw_state = (mb[2] & 0x00ff);
  406. nw_interface_link_up = ((mb[2] & 0x0100) >> 8);
  407. nw_interface_signal_detect = ((mb[2] & 0x0200) >> 9);
  408. sfp_status = ((mb[2] & 0x0c00) >> 10);
  409. htbt_counter = ((mb[2] & 0x7000) >> 12);
  410. htbt_monitor_enable = ((mb[2] & 0x8000) >> 15);
  411. sfp_additonal_info = (mb[6] & 0x0003);
  412. sfp_multirate = ((mb[6] & 0x0004) >> 2);
  413. sfp_tx_fault = ((mb[6] & 0x0008) >> 3);
  414. link_speed = ((mb[6] & 0x0070) >> 4);
  415. dcbx_status = ((mb[6] & 0x7000) >> 12);
  416. ql_log(ql_log_warn, vha, 0x5066,
  417. "Peg-to-Fc Status Register:\n"
  418. "peg_fw_state=0x%x, nw_interface_link_up=0x%x, "
  419. "nw_interface_signal_detect=0x%x"
  420. "\nsfp_statis=0x%x.\n ", peg_fw_state,
  421. nw_interface_link_up, nw_interface_signal_detect,
  422. sfp_status);
  423. ql_log(ql_log_warn, vha, 0x5067,
  424. "htbt_counter=0x%x, htbt_monitor_enable=0x%x, "
  425. "sfp_additonal_info=0x%x, sfp_multirate=0x%x.\n ",
  426. htbt_counter, htbt_monitor_enable,
  427. sfp_additonal_info, sfp_multirate);
  428. ql_log(ql_log_warn, vha, 0x5068,
  429. "sfp_tx_fault=0x%x, link_state=0x%x, "
  430. "dcbx_status=0x%x.\n", sfp_tx_fault, link_speed,
  431. dcbx_status);
  432. qla83xx_schedule_work(vha, QLA83XX_NIC_CORE_RESET);
  433. }
  434. if (mb[1] & IDC_HEARTBEAT_FAILURE) {
  435. ql_log(ql_log_warn, vha, 0x5069,
  436. "Heartbeat Failure encountered, chip reset "
  437. "required.\n");
  438. qla83xx_schedule_work(vha, QLA83XX_NIC_CORE_RESET);
  439. }
  440. }
  441. if (mb[1] & IDC_DEVICE_STATE_CHANGE) {
  442. ql_log(ql_log_info, vha, 0x506a,
  443. "IDC Device-State changed = 0x%x.\n", mb[4]);
  444. qla83xx_schedule_work(vha, MBA_IDC_AEN);
  445. }
  446. }
  447. int
  448. qla2x00_is_a_vp_did(scsi_qla_host_t *vha, uint32_t rscn_entry)
  449. {
  450. struct qla_hw_data *ha = vha->hw;
  451. scsi_qla_host_t *vp;
  452. uint32_t vp_did;
  453. unsigned long flags;
  454. int ret = 0;
  455. if (!ha->num_vhosts)
  456. return ret;
  457. spin_lock_irqsave(&ha->vport_slock, flags);
  458. list_for_each_entry(vp, &ha->vp_list, list) {
  459. vp_did = vp->d_id.b24;
  460. if (vp_did == rscn_entry) {
  461. ret = 1;
  462. break;
  463. }
  464. }
  465. spin_unlock_irqrestore(&ha->vport_slock, flags);
  466. return ret;
  467. }
  468. /**
  469. * qla2x00_async_event() - Process aynchronous events.
  470. * @ha: SCSI driver HA context
  471. * @mb: Mailbox registers (0 - 3)
  472. */
  473. void
  474. qla2x00_async_event(scsi_qla_host_t *vha, struct rsp_que *rsp, uint16_t *mb)
  475. {
  476. uint16_t handle_cnt;
  477. uint16_t cnt, mbx;
  478. uint32_t handles[5];
  479. struct qla_hw_data *ha = vha->hw;
  480. struct device_reg_2xxx __iomem *reg = &ha->iobase->isp;
  481. struct device_reg_24xx __iomem *reg24 = &ha->iobase->isp24;
  482. struct device_reg_82xx __iomem *reg82 = &ha->iobase->isp82;
  483. uint32_t rscn_entry, host_pid;
  484. unsigned long flags;
  485. /* Setup to process RIO completion. */
  486. handle_cnt = 0;
  487. if (IS_CNA_CAPABLE(ha))
  488. goto skip_rio;
  489. switch (mb[0]) {
  490. case MBA_SCSI_COMPLETION:
  491. handles[0] = le32_to_cpu((uint32_t)((mb[2] << 16) | mb[1]));
  492. handle_cnt = 1;
  493. break;
  494. case MBA_CMPLT_1_16BIT:
  495. handles[0] = mb[1];
  496. handle_cnt = 1;
  497. mb[0] = MBA_SCSI_COMPLETION;
  498. break;
  499. case MBA_CMPLT_2_16BIT:
  500. handles[0] = mb[1];
  501. handles[1] = mb[2];
  502. handle_cnt = 2;
  503. mb[0] = MBA_SCSI_COMPLETION;
  504. break;
  505. case MBA_CMPLT_3_16BIT:
  506. handles[0] = mb[1];
  507. handles[1] = mb[2];
  508. handles[2] = mb[3];
  509. handle_cnt = 3;
  510. mb[0] = MBA_SCSI_COMPLETION;
  511. break;
  512. case MBA_CMPLT_4_16BIT:
  513. handles[0] = mb[1];
  514. handles[1] = mb[2];
  515. handles[2] = mb[3];
  516. handles[3] = (uint32_t)RD_MAILBOX_REG(ha, reg, 6);
  517. handle_cnt = 4;
  518. mb[0] = MBA_SCSI_COMPLETION;
  519. break;
  520. case MBA_CMPLT_5_16BIT:
  521. handles[0] = mb[1];
  522. handles[1] = mb[2];
  523. handles[2] = mb[3];
  524. handles[3] = (uint32_t)RD_MAILBOX_REG(ha, reg, 6);
  525. handles[4] = (uint32_t)RD_MAILBOX_REG(ha, reg, 7);
  526. handle_cnt = 5;
  527. mb[0] = MBA_SCSI_COMPLETION;
  528. break;
  529. case MBA_CMPLT_2_32BIT:
  530. handles[0] = le32_to_cpu((uint32_t)((mb[2] << 16) | mb[1]));
  531. handles[1] = le32_to_cpu(
  532. ((uint32_t)(RD_MAILBOX_REG(ha, reg, 7) << 16)) |
  533. RD_MAILBOX_REG(ha, reg, 6));
  534. handle_cnt = 2;
  535. mb[0] = MBA_SCSI_COMPLETION;
  536. break;
  537. default:
  538. break;
  539. }
  540. skip_rio:
  541. switch (mb[0]) {
  542. case MBA_SCSI_COMPLETION: /* Fast Post */
  543. if (!vha->flags.online)
  544. break;
  545. for (cnt = 0; cnt < handle_cnt; cnt++)
  546. qla2x00_process_completed_request(vha, rsp->req,
  547. handles[cnt]);
  548. break;
  549. case MBA_RESET: /* Reset */
  550. ql_dbg(ql_dbg_async, vha, 0x5002,
  551. "Asynchronous RESET.\n");
  552. set_bit(RESET_MARKER_NEEDED, &vha->dpc_flags);
  553. break;
  554. case MBA_SYSTEM_ERR: /* System Error */
  555. mbx = (IS_QLA81XX(ha) || IS_QLA83XX(ha)) ?
  556. RD_REG_WORD(&reg24->mailbox7) : 0;
  557. ql_log(ql_log_warn, vha, 0x5003,
  558. "ISP System Error - mbx1=%xh mbx2=%xh mbx3=%xh "
  559. "mbx7=%xh.\n", mb[1], mb[2], mb[3], mbx);
  560. ha->isp_ops->fw_dump(vha, 1);
  561. if (IS_FWI2_CAPABLE(ha)) {
  562. if (mb[1] == 0 && mb[2] == 0) {
  563. ql_log(ql_log_fatal, vha, 0x5004,
  564. "Unrecoverable Hardware Error: adapter "
  565. "marked OFFLINE!\n");
  566. vha->flags.online = 0;
  567. vha->device_flags |= DFLG_DEV_FAILED;
  568. } else {
  569. /* Check to see if MPI timeout occurred */
  570. if ((mbx & MBX_3) && (ha->flags.port0))
  571. set_bit(MPI_RESET_NEEDED,
  572. &vha->dpc_flags);
  573. set_bit(ISP_ABORT_NEEDED, &vha->dpc_flags);
  574. }
  575. } else if (mb[1] == 0) {
  576. ql_log(ql_log_fatal, vha, 0x5005,
  577. "Unrecoverable Hardware Error: adapter marked "
  578. "OFFLINE!\n");
  579. vha->flags.online = 0;
  580. vha->device_flags |= DFLG_DEV_FAILED;
  581. } else
  582. set_bit(ISP_ABORT_NEEDED, &vha->dpc_flags);
  583. break;
  584. case MBA_REQ_TRANSFER_ERR: /* Request Transfer Error */
  585. ql_log(ql_log_warn, vha, 0x5006,
  586. "ISP Request Transfer Error (%x).\n", mb[1]);
  587. set_bit(ISP_ABORT_NEEDED, &vha->dpc_flags);
  588. break;
  589. case MBA_RSP_TRANSFER_ERR: /* Response Transfer Error */
  590. ql_log(ql_log_warn, vha, 0x5007,
  591. "ISP Response Transfer Error.\n");
  592. set_bit(ISP_ABORT_NEEDED, &vha->dpc_flags);
  593. break;
  594. case MBA_WAKEUP_THRES: /* Request Queue Wake-up */
  595. ql_dbg(ql_dbg_async, vha, 0x5008,
  596. "Asynchronous WAKEUP_THRES.\n");
  597. break;
  598. case MBA_LIP_OCCURRED: /* Loop Initialization Procedure */
  599. ql_dbg(ql_dbg_async, vha, 0x5009,
  600. "LIP occurred (%x).\n", mb[1]);
  601. if (atomic_read(&vha->loop_state) != LOOP_DOWN) {
  602. atomic_set(&vha->loop_state, LOOP_DOWN);
  603. atomic_set(&vha->loop_down_timer, LOOP_DOWN_TIME);
  604. qla2x00_mark_all_devices_lost(vha, 1);
  605. }
  606. if (vha->vp_idx) {
  607. atomic_set(&vha->vp_state, VP_FAILED);
  608. fc_vport_set_state(vha->fc_vport, FC_VPORT_FAILED);
  609. }
  610. set_bit(REGISTER_FC4_NEEDED, &vha->dpc_flags);
  611. set_bit(REGISTER_FDMI_NEEDED, &vha->dpc_flags);
  612. vha->flags.management_server_logged_in = 0;
  613. qla2x00_post_aen_work(vha, FCH_EVT_LIP, mb[1]);
  614. break;
  615. case MBA_LOOP_UP: /* Loop Up Event */
  616. if (IS_QLA2100(ha) || IS_QLA2200(ha))
  617. ha->link_data_rate = PORT_SPEED_1GB;
  618. else
  619. ha->link_data_rate = mb[1];
  620. ql_dbg(ql_dbg_async, vha, 0x500a,
  621. "LOOP UP detected (%s Gbps).\n",
  622. qla2x00_get_link_speed_str(ha, ha->link_data_rate));
  623. vha->flags.management_server_logged_in = 0;
  624. qla2x00_post_aen_work(vha, FCH_EVT_LINKUP, ha->link_data_rate);
  625. break;
  626. case MBA_LOOP_DOWN: /* Loop Down Event */
  627. mbx = (IS_QLA81XX(ha) || IS_QLA8031(ha))
  628. ? RD_REG_WORD(&reg24->mailbox4) : 0;
  629. mbx = IS_QLA82XX(ha) ? RD_REG_WORD(&reg82->mailbox_out[4]) : mbx;
  630. ql_dbg(ql_dbg_async, vha, 0x500b,
  631. "LOOP DOWN detected (%x %x %x %x).\n",
  632. mb[1], mb[2], mb[3], mbx);
  633. if (atomic_read(&vha->loop_state) != LOOP_DOWN) {
  634. atomic_set(&vha->loop_state, LOOP_DOWN);
  635. atomic_set(&vha->loop_down_timer, LOOP_DOWN_TIME);
  636. vha->device_flags |= DFLG_NO_CABLE;
  637. qla2x00_mark_all_devices_lost(vha, 1);
  638. }
  639. if (vha->vp_idx) {
  640. atomic_set(&vha->vp_state, VP_FAILED);
  641. fc_vport_set_state(vha->fc_vport, FC_VPORT_FAILED);
  642. }
  643. vha->flags.management_server_logged_in = 0;
  644. ha->link_data_rate = PORT_SPEED_UNKNOWN;
  645. qla2x00_post_aen_work(vha, FCH_EVT_LINKDOWN, 0);
  646. break;
  647. case MBA_LIP_RESET: /* LIP reset occurred */
  648. ql_dbg(ql_dbg_async, vha, 0x500c,
  649. "LIP reset occurred (%x).\n", mb[1]);
  650. if (atomic_read(&vha->loop_state) != LOOP_DOWN) {
  651. atomic_set(&vha->loop_state, LOOP_DOWN);
  652. atomic_set(&vha->loop_down_timer, LOOP_DOWN_TIME);
  653. qla2x00_mark_all_devices_lost(vha, 1);
  654. }
  655. if (vha->vp_idx) {
  656. atomic_set(&vha->vp_state, VP_FAILED);
  657. fc_vport_set_state(vha->fc_vport, FC_VPORT_FAILED);
  658. }
  659. set_bit(RESET_MARKER_NEEDED, &vha->dpc_flags);
  660. ha->operating_mode = LOOP;
  661. vha->flags.management_server_logged_in = 0;
  662. qla2x00_post_aen_work(vha, FCH_EVT_LIPRESET, mb[1]);
  663. break;
  664. /* case MBA_DCBX_COMPLETE: */
  665. case MBA_POINT_TO_POINT: /* Point-to-Point */
  666. if (IS_QLA2100(ha))
  667. break;
  668. if (IS_QLA81XX(ha) || IS_QLA82XX(ha) || IS_QLA8031(ha)) {
  669. ql_dbg(ql_dbg_async, vha, 0x500d,
  670. "DCBX Completed -- %04x %04x %04x.\n",
  671. mb[1], mb[2], mb[3]);
  672. if (ha->notify_dcbx_comp)
  673. complete(&ha->dcbx_comp);
  674. } else
  675. ql_dbg(ql_dbg_async, vha, 0x500e,
  676. "Asynchronous P2P MODE received.\n");
  677. /*
  678. * Until there's a transition from loop down to loop up, treat
  679. * this as loop down only.
  680. */
  681. if (atomic_read(&vha->loop_state) != LOOP_DOWN) {
  682. atomic_set(&vha->loop_state, LOOP_DOWN);
  683. if (!atomic_read(&vha->loop_down_timer))
  684. atomic_set(&vha->loop_down_timer,
  685. LOOP_DOWN_TIME);
  686. qla2x00_mark_all_devices_lost(vha, 1);
  687. }
  688. if (vha->vp_idx) {
  689. atomic_set(&vha->vp_state, VP_FAILED);
  690. fc_vport_set_state(vha->fc_vport, FC_VPORT_FAILED);
  691. }
  692. if (!(test_bit(ABORT_ISP_ACTIVE, &vha->dpc_flags)))
  693. set_bit(RESET_MARKER_NEEDED, &vha->dpc_flags);
  694. set_bit(REGISTER_FC4_NEEDED, &vha->dpc_flags);
  695. set_bit(REGISTER_FDMI_NEEDED, &vha->dpc_flags);
  696. ha->flags.gpsc_supported = 1;
  697. vha->flags.management_server_logged_in = 0;
  698. break;
  699. case MBA_CHG_IN_CONNECTION: /* Change in connection mode */
  700. if (IS_QLA2100(ha))
  701. break;
  702. ql_dbg(ql_dbg_async, vha, 0x500f,
  703. "Configuration change detected: value=%x.\n", mb[1]);
  704. if (atomic_read(&vha->loop_state) != LOOP_DOWN) {
  705. atomic_set(&vha->loop_state, LOOP_DOWN);
  706. if (!atomic_read(&vha->loop_down_timer))
  707. atomic_set(&vha->loop_down_timer,
  708. LOOP_DOWN_TIME);
  709. qla2x00_mark_all_devices_lost(vha, 1);
  710. }
  711. if (vha->vp_idx) {
  712. atomic_set(&vha->vp_state, VP_FAILED);
  713. fc_vport_set_state(vha->fc_vport, FC_VPORT_FAILED);
  714. }
  715. set_bit(LOOP_RESYNC_NEEDED, &vha->dpc_flags);
  716. set_bit(LOCAL_LOOP_UPDATE, &vha->dpc_flags);
  717. break;
  718. case MBA_PORT_UPDATE: /* Port database update */
  719. /*
  720. * Handle only global and vn-port update events
  721. *
  722. * Relevant inputs:
  723. * mb[1] = N_Port handle of changed port
  724. * OR 0xffff for global event
  725. * mb[2] = New login state
  726. * 7 = Port logged out
  727. * mb[3] = LSB is vp_idx, 0xff = all vps
  728. *
  729. * Skip processing if:
  730. * Event is global, vp_idx is NOT all vps,
  731. * vp_idx does not match
  732. * Event is not global, vp_idx does not match
  733. */
  734. if (IS_QLA2XXX_MIDTYPE(ha) &&
  735. ((mb[1] == 0xffff && (mb[3] & 0xff) != 0xff) ||
  736. (mb[1] != 0xffff)) && vha->vp_idx != (mb[3] & 0xff))
  737. break;
  738. /* Global event -- port logout or port unavailable. */
  739. if (mb[1] == 0xffff && mb[2] == 0x7) {
  740. ql_dbg(ql_dbg_async, vha, 0x5010,
  741. "Port unavailable %04x %04x %04x.\n",
  742. mb[1], mb[2], mb[3]);
  743. ql_log(ql_log_warn, vha, 0x505e,
  744. "Link is offline.\n");
  745. if (atomic_read(&vha->loop_state) != LOOP_DOWN) {
  746. atomic_set(&vha->loop_state, LOOP_DOWN);
  747. atomic_set(&vha->loop_down_timer,
  748. LOOP_DOWN_TIME);
  749. vha->device_flags |= DFLG_NO_CABLE;
  750. qla2x00_mark_all_devices_lost(vha, 1);
  751. }
  752. if (vha->vp_idx) {
  753. atomic_set(&vha->vp_state, VP_FAILED);
  754. fc_vport_set_state(vha->fc_vport,
  755. FC_VPORT_FAILED);
  756. qla2x00_mark_all_devices_lost(vha, 1);
  757. }
  758. vha->flags.management_server_logged_in = 0;
  759. ha->link_data_rate = PORT_SPEED_UNKNOWN;
  760. break;
  761. }
  762. /*
  763. * If PORT UPDATE is global (received LIP_OCCURRED/LIP_RESET
  764. * event etc. earlier indicating loop is down) then process
  765. * it. Otherwise ignore it and Wait for RSCN to come in.
  766. */
  767. atomic_set(&vha->loop_down_timer, 0);
  768. if (mb[1] != 0xffff || (mb[2] != 0x6 && mb[2] != 0x4)) {
  769. ql_dbg(ql_dbg_async, vha, 0x5011,
  770. "Asynchronous PORT UPDATE ignored %04x/%04x/%04x.\n",
  771. mb[1], mb[2], mb[3]);
  772. qlt_async_event(mb[0], vha, mb);
  773. break;
  774. }
  775. ql_dbg(ql_dbg_async, vha, 0x5012,
  776. "Port database changed %04x %04x %04x.\n",
  777. mb[1], mb[2], mb[3]);
  778. ql_log(ql_log_warn, vha, 0x505f,
  779. "Link is operational (%s Gbps).\n",
  780. qla2x00_get_link_speed_str(ha, ha->link_data_rate));
  781. /*
  782. * Mark all devices as missing so we will login again.
  783. */
  784. atomic_set(&vha->loop_state, LOOP_UP);
  785. qla2x00_mark_all_devices_lost(vha, 1);
  786. if (vha->vp_idx == 0 && !qla_ini_mode_enabled(vha))
  787. set_bit(SCR_PENDING, &vha->dpc_flags);
  788. set_bit(LOOP_RESYNC_NEEDED, &vha->dpc_flags);
  789. set_bit(LOCAL_LOOP_UPDATE, &vha->dpc_flags);
  790. qlt_async_event(mb[0], vha, mb);
  791. break;
  792. case MBA_RSCN_UPDATE: /* State Change Registration */
  793. /* Check if the Vport has issued a SCR */
  794. if (vha->vp_idx && test_bit(VP_SCR_NEEDED, &vha->vp_flags))
  795. break;
  796. /* Only handle SCNs for our Vport index. */
  797. if (ha->flags.npiv_supported && vha->vp_idx != (mb[3] & 0xff))
  798. break;
  799. ql_dbg(ql_dbg_async, vha, 0x5013,
  800. "RSCN database changed -- %04x %04x %04x.\n",
  801. mb[1], mb[2], mb[3]);
  802. rscn_entry = ((mb[1] & 0xff) << 16) | mb[2];
  803. host_pid = (vha->d_id.b.domain << 16) | (vha->d_id.b.area << 8)
  804. | vha->d_id.b.al_pa;
  805. if (rscn_entry == host_pid) {
  806. ql_dbg(ql_dbg_async, vha, 0x5014,
  807. "Ignoring RSCN update to local host "
  808. "port ID (%06x).\n", host_pid);
  809. break;
  810. }
  811. /* Ignore reserved bits from RSCN-payload. */
  812. rscn_entry = ((mb[1] & 0x3ff) << 16) | mb[2];
  813. /* Skip RSCNs for virtual ports on the same physical port */
  814. if (qla2x00_is_a_vp_did(vha, rscn_entry))
  815. break;
  816. atomic_set(&vha->loop_down_timer, 0);
  817. vha->flags.management_server_logged_in = 0;
  818. set_bit(LOOP_RESYNC_NEEDED, &vha->dpc_flags);
  819. set_bit(RSCN_UPDATE, &vha->dpc_flags);
  820. qla2x00_post_aen_work(vha, FCH_EVT_RSCN, rscn_entry);
  821. break;
  822. /* case MBA_RIO_RESPONSE: */
  823. case MBA_ZIO_RESPONSE:
  824. ql_dbg(ql_dbg_async, vha, 0x5015,
  825. "[R|Z]IO update completion.\n");
  826. if (IS_FWI2_CAPABLE(ha))
  827. qla24xx_process_response_queue(vha, rsp);
  828. else
  829. qla2x00_process_response_queue(rsp);
  830. break;
  831. case MBA_DISCARD_RND_FRAME:
  832. ql_dbg(ql_dbg_async, vha, 0x5016,
  833. "Discard RND Frame -- %04x %04x %04x.\n",
  834. mb[1], mb[2], mb[3]);
  835. break;
  836. case MBA_TRACE_NOTIFICATION:
  837. ql_dbg(ql_dbg_async, vha, 0x5017,
  838. "Trace Notification -- %04x %04x.\n", mb[1], mb[2]);
  839. break;
  840. case MBA_ISP84XX_ALERT:
  841. ql_dbg(ql_dbg_async, vha, 0x5018,
  842. "ISP84XX Alert Notification -- %04x %04x %04x.\n",
  843. mb[1], mb[2], mb[3]);
  844. spin_lock_irqsave(&ha->cs84xx->access_lock, flags);
  845. switch (mb[1]) {
  846. case A84_PANIC_RECOVERY:
  847. ql_log(ql_log_info, vha, 0x5019,
  848. "Alert 84XX: panic recovery %04x %04x.\n",
  849. mb[2], mb[3]);
  850. break;
  851. case A84_OP_LOGIN_COMPLETE:
  852. ha->cs84xx->op_fw_version = mb[3] << 16 | mb[2];
  853. ql_log(ql_log_info, vha, 0x501a,
  854. "Alert 84XX: firmware version %x.\n",
  855. ha->cs84xx->op_fw_version);
  856. break;
  857. case A84_DIAG_LOGIN_COMPLETE:
  858. ha->cs84xx->diag_fw_version = mb[3] << 16 | mb[2];
  859. ql_log(ql_log_info, vha, 0x501b,
  860. "Alert 84XX: diagnostic firmware version %x.\n",
  861. ha->cs84xx->diag_fw_version);
  862. break;
  863. case A84_GOLD_LOGIN_COMPLETE:
  864. ha->cs84xx->diag_fw_version = mb[3] << 16 | mb[2];
  865. ha->cs84xx->fw_update = 1;
  866. ql_log(ql_log_info, vha, 0x501c,
  867. "Alert 84XX: gold firmware version %x.\n",
  868. ha->cs84xx->gold_fw_version);
  869. break;
  870. default:
  871. ql_log(ql_log_warn, vha, 0x501d,
  872. "Alert 84xx: Invalid Alert %04x %04x %04x.\n",
  873. mb[1], mb[2], mb[3]);
  874. }
  875. spin_unlock_irqrestore(&ha->cs84xx->access_lock, flags);
  876. break;
  877. case MBA_DCBX_START:
  878. ql_dbg(ql_dbg_async, vha, 0x501e,
  879. "DCBX Started -- %04x %04x %04x.\n",
  880. mb[1], mb[2], mb[3]);
  881. break;
  882. case MBA_DCBX_PARAM_UPDATE:
  883. ql_dbg(ql_dbg_async, vha, 0x501f,
  884. "DCBX Parameters Updated -- %04x %04x %04x.\n",
  885. mb[1], mb[2], mb[3]);
  886. break;
  887. case MBA_FCF_CONF_ERR:
  888. ql_dbg(ql_dbg_async, vha, 0x5020,
  889. "FCF Configuration Error -- %04x %04x %04x.\n",
  890. mb[1], mb[2], mb[3]);
  891. break;
  892. case MBA_IDC_NOTIFY:
  893. if (IS_QLA8031(vha->hw)) {
  894. mb[4] = RD_REG_WORD(&reg24->mailbox4);
  895. if (((mb[2] & 0x7fff) == MBC_PORT_RESET ||
  896. (mb[2] & 0x7fff) == MBC_SET_PORT_CONFIG) &&
  897. (mb[4] & INTERNAL_LOOPBACK_MASK) != 0) {
  898. set_bit(ISP_QUIESCE_NEEDED, &vha->dpc_flags);
  899. /*
  900. * Extend loop down timer since port is active.
  901. */
  902. if (atomic_read(&vha->loop_state) == LOOP_DOWN)
  903. atomic_set(&vha->loop_down_timer,
  904. LOOP_DOWN_TIME);
  905. qla2xxx_wake_dpc(vha);
  906. }
  907. }
  908. case MBA_IDC_COMPLETE:
  909. case MBA_IDC_TIME_EXT:
  910. if (IS_QLA81XX(vha->hw) || IS_QLA8031(vha->hw))
  911. qla81xx_idc_event(vha, mb[0], mb[1]);
  912. break;
  913. case MBA_IDC_AEN:
  914. mb[4] = RD_REG_WORD(&reg24->mailbox4);
  915. mb[5] = RD_REG_WORD(&reg24->mailbox5);
  916. mb[6] = RD_REG_WORD(&reg24->mailbox6);
  917. mb[7] = RD_REG_WORD(&reg24->mailbox7);
  918. qla83xx_handle_8200_aen(vha, mb);
  919. break;
  920. default:
  921. ql_dbg(ql_dbg_async, vha, 0x5057,
  922. "Unknown AEN:%04x %04x %04x %04x\n",
  923. mb[0], mb[1], mb[2], mb[3]);
  924. }
  925. qlt_async_event(mb[0], vha, mb);
  926. if (!vha->vp_idx && ha->num_vhosts)
  927. qla2x00_alert_all_vps(rsp, mb);
  928. }
  929. /**
  930. * qla2x00_process_completed_request() - Process a Fast Post response.
  931. * @ha: SCSI driver HA context
  932. * @index: SRB index
  933. */
  934. static void
  935. qla2x00_process_completed_request(struct scsi_qla_host *vha,
  936. struct req_que *req, uint32_t index)
  937. {
  938. srb_t *sp;
  939. struct qla_hw_data *ha = vha->hw;
  940. /* Validate handle. */
  941. if (index >= req->num_outstanding_cmds) {
  942. ql_log(ql_log_warn, vha, 0x3014,
  943. "Invalid SCSI command index (%x).\n", index);
  944. if (IS_QLA82XX(ha))
  945. set_bit(FCOE_CTX_RESET_NEEDED, &vha->dpc_flags);
  946. else
  947. set_bit(ISP_ABORT_NEEDED, &vha->dpc_flags);
  948. return;
  949. }
  950. sp = req->outstanding_cmds[index];
  951. if (sp) {
  952. /* Free outstanding command slot. */
  953. req->outstanding_cmds[index] = NULL;
  954. /* Save ISP completion status */
  955. sp->done(ha, sp, DID_OK << 16);
  956. } else {
  957. ql_log(ql_log_warn, vha, 0x3016, "Invalid SCSI SRB.\n");
  958. if (IS_QLA82XX(ha))
  959. set_bit(FCOE_CTX_RESET_NEEDED, &vha->dpc_flags);
  960. else
  961. set_bit(ISP_ABORT_NEEDED, &vha->dpc_flags);
  962. }
  963. }
  964. static srb_t *
  965. qla2x00_get_sp_from_handle(scsi_qla_host_t *vha, const char *func,
  966. struct req_que *req, void *iocb)
  967. {
  968. struct qla_hw_data *ha = vha->hw;
  969. sts_entry_t *pkt = iocb;
  970. srb_t *sp = NULL;
  971. uint16_t index;
  972. index = LSW(pkt->handle);
  973. if (index >= req->num_outstanding_cmds) {
  974. ql_log(ql_log_warn, vha, 0x5031,
  975. "Invalid command index (%x).\n", index);
  976. if (IS_QLA82XX(ha))
  977. set_bit(FCOE_CTX_RESET_NEEDED, &vha->dpc_flags);
  978. else
  979. set_bit(ISP_ABORT_NEEDED, &vha->dpc_flags);
  980. goto done;
  981. }
  982. sp = req->outstanding_cmds[index];
  983. if (!sp) {
  984. ql_log(ql_log_warn, vha, 0x5032,
  985. "Invalid completion handle (%x) -- timed-out.\n", index);
  986. return sp;
  987. }
  988. if (sp->handle != index) {
  989. ql_log(ql_log_warn, vha, 0x5033,
  990. "SRB handle (%x) mismatch %x.\n", sp->handle, index);
  991. return NULL;
  992. }
  993. req->outstanding_cmds[index] = NULL;
  994. done:
  995. return sp;
  996. }
  997. static void
  998. qla2x00_mbx_iocb_entry(scsi_qla_host_t *vha, struct req_que *req,
  999. struct mbx_entry *mbx)
  1000. {
  1001. const char func[] = "MBX-IOCB";
  1002. const char *type;
  1003. fc_port_t *fcport;
  1004. srb_t *sp;
  1005. struct srb_iocb *lio;
  1006. uint16_t *data;
  1007. uint16_t status;
  1008. sp = qla2x00_get_sp_from_handle(vha, func, req, mbx);
  1009. if (!sp)
  1010. return;
  1011. lio = &sp->u.iocb_cmd;
  1012. type = sp->name;
  1013. fcport = sp->fcport;
  1014. data = lio->u.logio.data;
  1015. data[0] = MBS_COMMAND_ERROR;
  1016. data[1] = lio->u.logio.flags & SRB_LOGIN_RETRIED ?
  1017. QLA_LOGIO_LOGIN_RETRIED : 0;
  1018. if (mbx->entry_status) {
  1019. ql_dbg(ql_dbg_async, vha, 0x5043,
  1020. "Async-%s error entry - hdl=%x portid=%02x%02x%02x "
  1021. "entry-status=%x status=%x state-flag=%x "
  1022. "status-flags=%x.\n", type, sp->handle,
  1023. fcport->d_id.b.domain, fcport->d_id.b.area,
  1024. fcport->d_id.b.al_pa, mbx->entry_status,
  1025. le16_to_cpu(mbx->status), le16_to_cpu(mbx->state_flags),
  1026. le16_to_cpu(mbx->status_flags));
  1027. ql_dump_buffer(ql_dbg_async + ql_dbg_buffer, vha, 0x5029,
  1028. (uint8_t *)mbx, sizeof(*mbx));
  1029. goto logio_done;
  1030. }
  1031. status = le16_to_cpu(mbx->status);
  1032. if (status == 0x30 && sp->type == SRB_LOGIN_CMD &&
  1033. le16_to_cpu(mbx->mb0) == MBS_COMMAND_COMPLETE)
  1034. status = 0;
  1035. if (!status && le16_to_cpu(mbx->mb0) == MBS_COMMAND_COMPLETE) {
  1036. ql_dbg(ql_dbg_async, vha, 0x5045,
  1037. "Async-%s complete - hdl=%x portid=%02x%02x%02x mbx1=%x.\n",
  1038. type, sp->handle, fcport->d_id.b.domain,
  1039. fcport->d_id.b.area, fcport->d_id.b.al_pa,
  1040. le16_to_cpu(mbx->mb1));
  1041. data[0] = MBS_COMMAND_COMPLETE;
  1042. if (sp->type == SRB_LOGIN_CMD) {
  1043. fcport->port_type = FCT_TARGET;
  1044. if (le16_to_cpu(mbx->mb1) & BIT_0)
  1045. fcport->port_type = FCT_INITIATOR;
  1046. else if (le16_to_cpu(mbx->mb1) & BIT_1)
  1047. fcport->flags |= FCF_FCP2_DEVICE;
  1048. }
  1049. goto logio_done;
  1050. }
  1051. data[0] = le16_to_cpu(mbx->mb0);
  1052. switch (data[0]) {
  1053. case MBS_PORT_ID_USED:
  1054. data[1] = le16_to_cpu(mbx->mb1);
  1055. break;
  1056. case MBS_LOOP_ID_USED:
  1057. break;
  1058. default:
  1059. data[0] = MBS_COMMAND_ERROR;
  1060. break;
  1061. }
  1062. ql_log(ql_log_warn, vha, 0x5046,
  1063. "Async-%s failed - hdl=%x portid=%02x%02x%02x status=%x "
  1064. "mb0=%x mb1=%x mb2=%x mb6=%x mb7=%x.\n", type, sp->handle,
  1065. fcport->d_id.b.domain, fcport->d_id.b.area, fcport->d_id.b.al_pa,
  1066. status, le16_to_cpu(mbx->mb0), le16_to_cpu(mbx->mb1),
  1067. le16_to_cpu(mbx->mb2), le16_to_cpu(mbx->mb6),
  1068. le16_to_cpu(mbx->mb7));
  1069. logio_done:
  1070. sp->done(vha, sp, 0);
  1071. }
  1072. static void
  1073. qla2x00_ct_entry(scsi_qla_host_t *vha, struct req_que *req,
  1074. sts_entry_t *pkt, int iocb_type)
  1075. {
  1076. const char func[] = "CT_IOCB";
  1077. const char *type;
  1078. srb_t *sp;
  1079. struct fc_bsg_job *bsg_job;
  1080. uint16_t comp_status;
  1081. int res;
  1082. sp = qla2x00_get_sp_from_handle(vha, func, req, pkt);
  1083. if (!sp)
  1084. return;
  1085. bsg_job = sp->u.bsg_job;
  1086. type = "ct pass-through";
  1087. comp_status = le16_to_cpu(pkt->comp_status);
  1088. /* return FC_CTELS_STATUS_OK and leave the decoding of the ELS/CT
  1089. * fc payload to the caller
  1090. */
  1091. bsg_job->reply->reply_data.ctels_reply.status = FC_CTELS_STATUS_OK;
  1092. bsg_job->reply_len = sizeof(struct fc_bsg_reply);
  1093. if (comp_status != CS_COMPLETE) {
  1094. if (comp_status == CS_DATA_UNDERRUN) {
  1095. res = DID_OK << 16;
  1096. bsg_job->reply->reply_payload_rcv_len =
  1097. le16_to_cpu(((sts_entry_t *)pkt)->rsp_info_len);
  1098. ql_log(ql_log_warn, vha, 0x5048,
  1099. "CT pass-through-%s error "
  1100. "comp_status-status=0x%x total_byte = 0x%x.\n",
  1101. type, comp_status,
  1102. bsg_job->reply->reply_payload_rcv_len);
  1103. } else {
  1104. ql_log(ql_log_warn, vha, 0x5049,
  1105. "CT pass-through-%s error "
  1106. "comp_status-status=0x%x.\n", type, comp_status);
  1107. res = DID_ERROR << 16;
  1108. bsg_job->reply->reply_payload_rcv_len = 0;
  1109. }
  1110. ql_dump_buffer(ql_dbg_async + ql_dbg_buffer, vha, 0x5035,
  1111. (uint8_t *)pkt, sizeof(*pkt));
  1112. } else {
  1113. res = DID_OK << 16;
  1114. bsg_job->reply->reply_payload_rcv_len =
  1115. bsg_job->reply_payload.payload_len;
  1116. bsg_job->reply_len = 0;
  1117. }
  1118. sp->done(vha, sp, res);
  1119. }
  1120. static void
  1121. qla24xx_els_ct_entry(scsi_qla_host_t *vha, struct req_que *req,
  1122. struct sts_entry_24xx *pkt, int iocb_type)
  1123. {
  1124. const char func[] = "ELS_CT_IOCB";
  1125. const char *type;
  1126. srb_t *sp;
  1127. struct fc_bsg_job *bsg_job;
  1128. uint16_t comp_status;
  1129. uint32_t fw_status[3];
  1130. uint8_t* fw_sts_ptr;
  1131. int res;
  1132. sp = qla2x00_get_sp_from_handle(vha, func, req, pkt);
  1133. if (!sp)
  1134. return;
  1135. bsg_job = sp->u.bsg_job;
  1136. type = NULL;
  1137. switch (sp->type) {
  1138. case SRB_ELS_CMD_RPT:
  1139. case SRB_ELS_CMD_HST:
  1140. type = "els";
  1141. break;
  1142. case SRB_CT_CMD:
  1143. type = "ct pass-through";
  1144. break;
  1145. default:
  1146. ql_dbg(ql_dbg_user, vha, 0x503e,
  1147. "Unrecognized SRB: (%p) type=%d.\n", sp, sp->type);
  1148. return;
  1149. }
  1150. comp_status = fw_status[0] = le16_to_cpu(pkt->comp_status);
  1151. fw_status[1] = le16_to_cpu(((struct els_sts_entry_24xx*)pkt)->error_subcode_1);
  1152. fw_status[2] = le16_to_cpu(((struct els_sts_entry_24xx*)pkt)->error_subcode_2);
  1153. /* return FC_CTELS_STATUS_OK and leave the decoding of the ELS/CT
  1154. * fc payload to the caller
  1155. */
  1156. bsg_job->reply->reply_data.ctels_reply.status = FC_CTELS_STATUS_OK;
  1157. bsg_job->reply_len = sizeof(struct fc_bsg_reply) + sizeof(fw_status);
  1158. if (comp_status != CS_COMPLETE) {
  1159. if (comp_status == CS_DATA_UNDERRUN) {
  1160. res = DID_OK << 16;
  1161. bsg_job->reply->reply_payload_rcv_len =
  1162. le16_to_cpu(((struct els_sts_entry_24xx *)pkt)->total_byte_count);
  1163. ql_dbg(ql_dbg_user, vha, 0x503f,
  1164. "ELS-CT pass-through-%s error hdl=%x comp_status-status=0x%x "
  1165. "error subcode 1=0x%x error subcode 2=0x%x total_byte = 0x%x.\n",
  1166. type, sp->handle, comp_status, fw_status[1], fw_status[2],
  1167. le16_to_cpu(((struct els_sts_entry_24xx *)
  1168. pkt)->total_byte_count));
  1169. fw_sts_ptr = ((uint8_t*)bsg_job->req->sense) + sizeof(struct fc_bsg_reply);
  1170. memcpy( fw_sts_ptr, fw_status, sizeof(fw_status));
  1171. }
  1172. else {
  1173. ql_dbg(ql_dbg_user, vha, 0x5040,
  1174. "ELS-CT pass-through-%s error hdl=%x comp_status-status=0x%x "
  1175. "error subcode 1=0x%x error subcode 2=0x%x.\n",
  1176. type, sp->handle, comp_status,
  1177. le16_to_cpu(((struct els_sts_entry_24xx *)
  1178. pkt)->error_subcode_1),
  1179. le16_to_cpu(((struct els_sts_entry_24xx *)
  1180. pkt)->error_subcode_2));
  1181. res = DID_ERROR << 16;
  1182. bsg_job->reply->reply_payload_rcv_len = 0;
  1183. fw_sts_ptr = ((uint8_t*)bsg_job->req->sense) + sizeof(struct fc_bsg_reply);
  1184. memcpy( fw_sts_ptr, fw_status, sizeof(fw_status));
  1185. }
  1186. ql_dump_buffer(ql_dbg_user + ql_dbg_buffer, vha, 0x5056,
  1187. (uint8_t *)pkt, sizeof(*pkt));
  1188. }
  1189. else {
  1190. res = DID_OK << 16;
  1191. bsg_job->reply->reply_payload_rcv_len = bsg_job->reply_payload.payload_len;
  1192. bsg_job->reply_len = 0;
  1193. }
  1194. sp->done(vha, sp, res);
  1195. }
  1196. static void
  1197. qla24xx_logio_entry(scsi_qla_host_t *vha, struct req_que *req,
  1198. struct logio_entry_24xx *logio)
  1199. {
  1200. const char func[] = "LOGIO-IOCB";
  1201. const char *type;
  1202. fc_port_t *fcport;
  1203. srb_t *sp;
  1204. struct srb_iocb *lio;
  1205. uint16_t *data;
  1206. uint32_t iop[2];
  1207. sp = qla2x00_get_sp_from_handle(vha, func, req, logio);
  1208. if (!sp)
  1209. return;
  1210. lio = &sp->u.iocb_cmd;
  1211. type = sp->name;
  1212. fcport = sp->fcport;
  1213. data = lio->u.logio.data;
  1214. data[0] = MBS_COMMAND_ERROR;
  1215. data[1] = lio->u.logio.flags & SRB_LOGIN_RETRIED ?
  1216. QLA_LOGIO_LOGIN_RETRIED : 0;
  1217. if (logio->entry_status) {
  1218. ql_log(ql_log_warn, fcport->vha, 0x5034,
  1219. "Async-%s error entry - hdl=%x"
  1220. "portid=%02x%02x%02x entry-status=%x.\n",
  1221. type, sp->handle, fcport->d_id.b.domain,
  1222. fcport->d_id.b.area, fcport->d_id.b.al_pa,
  1223. logio->entry_status);
  1224. ql_dump_buffer(ql_dbg_async + ql_dbg_buffer, vha, 0x504d,
  1225. (uint8_t *)logio, sizeof(*logio));
  1226. goto logio_done;
  1227. }
  1228. if (le16_to_cpu(logio->comp_status) == CS_COMPLETE) {
  1229. ql_dbg(ql_dbg_async, fcport->vha, 0x5036,
  1230. "Async-%s complete - hdl=%x portid=%02x%02x%02x "
  1231. "iop0=%x.\n", type, sp->handle, fcport->d_id.b.domain,
  1232. fcport->d_id.b.area, fcport->d_id.b.al_pa,
  1233. le32_to_cpu(logio->io_parameter[0]));
  1234. data[0] = MBS_COMMAND_COMPLETE;
  1235. if (sp->type != SRB_LOGIN_CMD)
  1236. goto logio_done;
  1237. iop[0] = le32_to_cpu(logio->io_parameter[0]);
  1238. if (iop[0] & BIT_4) {
  1239. fcport->port_type = FCT_TARGET;
  1240. if (iop[0] & BIT_8)
  1241. fcport->flags |= FCF_FCP2_DEVICE;
  1242. } else if (iop[0] & BIT_5)
  1243. fcport->port_type = FCT_INITIATOR;
  1244. if (iop[0] & BIT_7)
  1245. fcport->flags |= FCF_CONF_COMP_SUPPORTED;
  1246. if (logio->io_parameter[7] || logio->io_parameter[8])
  1247. fcport->supported_classes |= FC_COS_CLASS2;
  1248. if (logio->io_parameter[9] || logio->io_parameter[10])
  1249. fcport->supported_classes |= FC_COS_CLASS3;
  1250. goto logio_done;
  1251. }
  1252. iop[0] = le32_to_cpu(logio->io_parameter[0]);
  1253. iop[1] = le32_to_cpu(logio->io_parameter[1]);
  1254. switch (iop[0]) {
  1255. case LSC_SCODE_PORTID_USED:
  1256. data[0] = MBS_PORT_ID_USED;
  1257. data[1] = LSW(iop[1]);
  1258. break;
  1259. case LSC_SCODE_NPORT_USED:
  1260. data[0] = MBS_LOOP_ID_USED;
  1261. break;
  1262. default:
  1263. data[0] = MBS_COMMAND_ERROR;
  1264. break;
  1265. }
  1266. ql_dbg(ql_dbg_async, fcport->vha, 0x5037,
  1267. "Async-%s failed - hdl=%x portid=%02x%02x%02x comp=%x "
  1268. "iop0=%x iop1=%x.\n", type, sp->handle, fcport->d_id.b.domain,
  1269. fcport->d_id.b.area, fcport->d_id.b.al_pa,
  1270. le16_to_cpu(logio->comp_status),
  1271. le32_to_cpu(logio->io_parameter[0]),
  1272. le32_to_cpu(logio->io_parameter[1]));
  1273. logio_done:
  1274. sp->done(vha, sp, 0);
  1275. }
  1276. static void
  1277. qla24xx_tm_iocb_entry(scsi_qla_host_t *vha, struct req_que *req,
  1278. struct tsk_mgmt_entry *tsk)
  1279. {
  1280. const char func[] = "TMF-IOCB";
  1281. const char *type;
  1282. fc_port_t *fcport;
  1283. srb_t *sp;
  1284. struct srb_iocb *iocb;
  1285. struct sts_entry_24xx *sts = (struct sts_entry_24xx *)tsk;
  1286. int error = 1;
  1287. sp = qla2x00_get_sp_from_handle(vha, func, req, tsk);
  1288. if (!sp)
  1289. return;
  1290. iocb = &sp->u.iocb_cmd;
  1291. type = sp->name;
  1292. fcport = sp->fcport;
  1293. if (sts->entry_status) {
  1294. ql_log(ql_log_warn, fcport->vha, 0x5038,
  1295. "Async-%s error - hdl=%x entry-status(%x).\n",
  1296. type, sp->handle, sts->entry_status);
  1297. } else if (sts->comp_status != __constant_cpu_to_le16(CS_COMPLETE)) {
  1298. ql_log(ql_log_warn, fcport->vha, 0x5039,
  1299. "Async-%s error - hdl=%x completion status(%x).\n",
  1300. type, sp->handle, sts->comp_status);
  1301. } else if (!(le16_to_cpu(sts->scsi_status) &
  1302. SS_RESPONSE_INFO_LEN_VALID)) {
  1303. ql_log(ql_log_warn, fcport->vha, 0x503a,
  1304. "Async-%s error - hdl=%x no response info(%x).\n",
  1305. type, sp->handle, sts->scsi_status);
  1306. } else if (le32_to_cpu(sts->rsp_data_len) < 4) {
  1307. ql_log(ql_log_warn, fcport->vha, 0x503b,
  1308. "Async-%s error - hdl=%x not enough response(%d).\n",
  1309. type, sp->handle, sts->rsp_data_len);
  1310. } else if (sts->data[3]) {
  1311. ql_log(ql_log_warn, fcport->vha, 0x503c,
  1312. "Async-%s error - hdl=%x response(%x).\n",
  1313. type, sp->handle, sts->data[3]);
  1314. } else {
  1315. error = 0;
  1316. }
  1317. if (error) {
  1318. iocb->u.tmf.data = error;
  1319. ql_dump_buffer(ql_dbg_async + ql_dbg_buffer, vha, 0x5055,
  1320. (uint8_t *)sts, sizeof(*sts));
  1321. }
  1322. sp->done(vha, sp, 0);
  1323. }
  1324. /**
  1325. * qla2x00_process_response_queue() - Process response queue entries.
  1326. * @ha: SCSI driver HA context
  1327. */
  1328. void
  1329. qla2x00_process_response_queue(struct rsp_que *rsp)
  1330. {
  1331. struct scsi_qla_host *vha;
  1332. struct qla_hw_data *ha = rsp->hw;
  1333. struct device_reg_2xxx __iomem *reg = &ha->iobase->isp;
  1334. sts_entry_t *pkt;
  1335. uint16_t handle_cnt;
  1336. uint16_t cnt;
  1337. vha = pci_get_drvdata(ha->pdev);
  1338. if (!vha->flags.online)
  1339. return;
  1340. while (rsp->ring_ptr->signature != RESPONSE_PROCESSED) {
  1341. pkt = (sts_entry_t *)rsp->ring_ptr;
  1342. rsp->ring_index++;
  1343. if (rsp->ring_index == rsp->length) {
  1344. rsp->ring_index = 0;
  1345. rsp->ring_ptr = rsp->ring;
  1346. } else {
  1347. rsp->ring_ptr++;
  1348. }
  1349. if (pkt->entry_status != 0) {
  1350. qla2x00_error_entry(vha, rsp, pkt);
  1351. ((response_t *)pkt)->signature = RESPONSE_PROCESSED;
  1352. wmb();
  1353. continue;
  1354. }
  1355. switch (pkt->entry_type) {
  1356. case STATUS_TYPE:
  1357. qla2x00_status_entry(vha, rsp, pkt);
  1358. break;
  1359. case STATUS_TYPE_21:
  1360. handle_cnt = ((sts21_entry_t *)pkt)->handle_count;
  1361. for (cnt = 0; cnt < handle_cnt; cnt++) {
  1362. qla2x00_process_completed_request(vha, rsp->req,
  1363. ((sts21_entry_t *)pkt)->handle[cnt]);
  1364. }
  1365. break;
  1366. case STATUS_TYPE_22:
  1367. handle_cnt = ((sts22_entry_t *)pkt)->handle_count;
  1368. for (cnt = 0; cnt < handle_cnt; cnt++) {
  1369. qla2x00_process_completed_request(vha, rsp->req,
  1370. ((sts22_entry_t *)pkt)->handle[cnt]);
  1371. }
  1372. break;
  1373. case STATUS_CONT_TYPE:
  1374. qla2x00_status_cont_entry(rsp, (sts_cont_entry_t *)pkt);
  1375. break;
  1376. case MBX_IOCB_TYPE:
  1377. qla2x00_mbx_iocb_entry(vha, rsp->req,
  1378. (struct mbx_entry *)pkt);
  1379. break;
  1380. case CT_IOCB_TYPE:
  1381. qla2x00_ct_entry(vha, rsp->req, pkt, CT_IOCB_TYPE);
  1382. break;
  1383. default:
  1384. /* Type Not Supported. */
  1385. ql_log(ql_log_warn, vha, 0x504a,
  1386. "Received unknown response pkt type %x "
  1387. "entry status=%x.\n",
  1388. pkt->entry_type, pkt->entry_status);
  1389. break;
  1390. }
  1391. ((response_t *)pkt)->signature = RESPONSE_PROCESSED;
  1392. wmb();
  1393. }
  1394. /* Adjust ring index */
  1395. WRT_REG_WORD(ISP_RSP_Q_OUT(ha, reg), rsp->ring_index);
  1396. }
  1397. static inline void
  1398. qla2x00_handle_sense(srb_t *sp, uint8_t *sense_data, uint32_t par_sense_len,
  1399. uint32_t sense_len, struct rsp_que *rsp, int res)
  1400. {
  1401. struct scsi_qla_host *vha = sp->fcport->vha;
  1402. struct scsi_cmnd *cp = GET_CMD_SP(sp);
  1403. uint32_t track_sense_len;
  1404. if (sense_len >= SCSI_SENSE_BUFFERSIZE)
  1405. sense_len = SCSI_SENSE_BUFFERSIZE;
  1406. SET_CMD_SENSE_LEN(sp, sense_len);
  1407. SET_CMD_SENSE_PTR(sp, cp->sense_buffer);
  1408. track_sense_len = sense_len;
  1409. if (sense_len > par_sense_len)
  1410. sense_len = par_sense_len;
  1411. memcpy(cp->sense_buffer, sense_data, sense_len);
  1412. SET_CMD_SENSE_PTR(sp, cp->sense_buffer + sense_len);
  1413. track_sense_len -= sense_len;
  1414. SET_CMD_SENSE_LEN(sp, track_sense_len);
  1415. if (track_sense_len != 0) {
  1416. rsp->status_srb = sp;
  1417. cp->result = res;
  1418. }
  1419. if (sense_len) {
  1420. ql_dbg(ql_dbg_io + ql_dbg_buffer, vha, 0x301c,
  1421. "Check condition Sense data, nexus%ld:%d:%d cmd=%p.\n",
  1422. sp->fcport->vha->host_no, cp->device->id, cp->device->lun,
  1423. cp);
  1424. ql_dump_buffer(ql_dbg_io + ql_dbg_buffer, vha, 0x302b,
  1425. cp->sense_buffer, sense_len);
  1426. }
  1427. }
  1428. struct scsi_dif_tuple {
  1429. __be16 guard; /* Checksum */
  1430. __be16 app_tag; /* APPL identifier */
  1431. __be32 ref_tag; /* Target LBA or indirect LBA */
  1432. };
  1433. /*
  1434. * Checks the guard or meta-data for the type of error
  1435. * detected by the HBA. In case of errors, we set the
  1436. * ASC/ASCQ fields in the sense buffer with ILLEGAL_REQUEST
  1437. * to indicate to the kernel that the HBA detected error.
  1438. */
  1439. static inline int
  1440. qla2x00_handle_dif_error(srb_t *sp, struct sts_entry_24xx *sts24)
  1441. {
  1442. struct scsi_qla_host *vha = sp->fcport->vha;
  1443. struct scsi_cmnd *cmd = GET_CMD_SP(sp);
  1444. uint8_t *ap = &sts24->data[12];
  1445. uint8_t *ep = &sts24->data[20];
  1446. uint32_t e_ref_tag, a_ref_tag;
  1447. uint16_t e_app_tag, a_app_tag;
  1448. uint16_t e_guard, a_guard;
  1449. /*
  1450. * swab32 of the "data" field in the beginning of qla2x00_status_entry()
  1451. * would make guard field appear at offset 2
  1452. */
  1453. a_guard = le16_to_cpu(*(uint16_t *)(ap + 2));
  1454. a_app_tag = le16_to_cpu(*(uint16_t *)(ap + 0));
  1455. a_ref_tag = le32_to_cpu(*(uint32_t *)(ap + 4));
  1456. e_guard = le16_to_cpu(*(uint16_t *)(ep + 2));
  1457. e_app_tag = le16_to_cpu(*(uint16_t *)(ep + 0));
  1458. e_ref_tag = le32_to_cpu(*(uint32_t *)(ep + 4));
  1459. ql_dbg(ql_dbg_io, vha, 0x3023,
  1460. "iocb(s) %p Returned STATUS.\n", sts24);
  1461. ql_dbg(ql_dbg_io, vha, 0x3024,
  1462. "DIF ERROR in cmd 0x%x lba 0x%llx act ref"
  1463. " tag=0x%x, exp ref_tag=0x%x, act app tag=0x%x, exp app"
  1464. " tag=0x%x, act guard=0x%x, exp guard=0x%x.\n",
  1465. cmd->cmnd[0], (u64)scsi_get_lba(cmd), a_ref_tag, e_ref_tag,
  1466. a_app_tag, e_app_tag, a_guard, e_guard);
  1467. /*
  1468. * Ignore sector if:
  1469. * For type 3: ref & app tag is all 'f's
  1470. * For type 0,1,2: app tag is all 'f's
  1471. */
  1472. if ((a_app_tag == 0xffff) &&
  1473. ((scsi_get_prot_type(cmd) != SCSI_PROT_DIF_TYPE3) ||
  1474. (a_ref_tag == 0xffffffff))) {
  1475. uint32_t blocks_done, resid;
  1476. sector_t lba_s = scsi_get_lba(cmd);
  1477. /* 2TB boundary case covered automatically with this */
  1478. blocks_done = e_ref_tag - (uint32_t)lba_s + 1;
  1479. resid = scsi_bufflen(cmd) - (blocks_done *
  1480. cmd->device->sector_size);
  1481. scsi_set_resid(cmd, resid);
  1482. cmd->result = DID_OK << 16;
  1483. /* Update protection tag */
  1484. if (scsi_prot_sg_count(cmd)) {
  1485. uint32_t i, j = 0, k = 0, num_ent;
  1486. struct scatterlist *sg;
  1487. struct sd_dif_tuple *spt;
  1488. /* Patch the corresponding protection tags */
  1489. scsi_for_each_prot_sg(cmd, sg,
  1490. scsi_prot_sg_count(cmd), i) {
  1491. num_ent = sg_dma_len(sg) / 8;
  1492. if (k + num_ent < blocks_done) {
  1493. k += num_ent;
  1494. continue;
  1495. }
  1496. j = blocks_done - k - 1;
  1497. k = blocks_done;
  1498. break;
  1499. }
  1500. if (k != blocks_done) {
  1501. ql_log(ql_log_warn, vha, 0x302f,
  1502. "unexpected tag values tag:lba=%x:%llx)\n",
  1503. e_ref_tag, (unsigned long long)lba_s);
  1504. return 1;
  1505. }
  1506. spt = page_address(sg_page(sg)) + sg->offset;
  1507. spt += j;
  1508. spt->app_tag = 0xffff;
  1509. if (scsi_get_prot_type(cmd) == SCSI_PROT_DIF_TYPE3)
  1510. spt->ref_tag = 0xffffffff;
  1511. }
  1512. return 0;
  1513. }
  1514. /* check guard */
  1515. if (e_guard != a_guard) {
  1516. scsi_build_sense_buffer(1, cmd->sense_buffer, ILLEGAL_REQUEST,
  1517. 0x10, 0x1);
  1518. set_driver_byte(cmd, DRIVER_SENSE);
  1519. set_host_byte(cmd, DID_ABORT);
  1520. cmd->result |= SAM_STAT_CHECK_CONDITION << 1;
  1521. return 1;
  1522. }
  1523. /* check ref tag */
  1524. if (e_ref_tag != a_ref_tag) {
  1525. scsi_build_sense_buffer(1, cmd->sense_buffer, ILLEGAL_REQUEST,
  1526. 0x10, 0x3);
  1527. set_driver_byte(cmd, DRIVER_SENSE);
  1528. set_host_byte(cmd, DID_ABORT);
  1529. cmd->result |= SAM_STAT_CHECK_CONDITION << 1;
  1530. return 1;
  1531. }
  1532. /* check appl tag */
  1533. if (e_app_tag != a_app_tag) {
  1534. scsi_build_sense_buffer(1, cmd->sense_buffer, ILLEGAL_REQUEST,
  1535. 0x10, 0x2);
  1536. set_driver_byte(cmd, DRIVER_SENSE);
  1537. set_host_byte(cmd, DID_ABORT);
  1538. cmd->result |= SAM_STAT_CHECK_CONDITION << 1;
  1539. return 1;
  1540. }
  1541. return 1;
  1542. }
  1543. static void
  1544. qla25xx_process_bidir_status_iocb(scsi_qla_host_t *vha, void *pkt,
  1545. struct req_que *req, uint32_t index)
  1546. {
  1547. struct qla_hw_data *ha = vha->hw;
  1548. srb_t *sp;
  1549. uint16_t comp_status;
  1550. uint16_t scsi_status;
  1551. uint16_t thread_id;
  1552. uint32_t rval = EXT_STATUS_OK;
  1553. struct fc_bsg_job *bsg_job = NULL;
  1554. sts_entry_t *sts;
  1555. struct sts_entry_24xx *sts24;
  1556. sts = (sts_entry_t *) pkt;
  1557. sts24 = (struct sts_entry_24xx *) pkt;
  1558. /* Validate handle. */
  1559. if (index >= req->num_outstanding_cmds) {
  1560. ql_log(ql_log_warn, vha, 0x70af,
  1561. "Invalid SCSI completion handle 0x%x.\n", index);
  1562. set_bit(ISP_ABORT_NEEDED, &vha->dpc_flags);
  1563. return;
  1564. }
  1565. sp = req->outstanding_cmds[index];
  1566. if (sp) {
  1567. /* Free outstanding command slot. */
  1568. req->outstanding_cmds[index] = NULL;
  1569. bsg_job = sp->u.bsg_job;
  1570. } else {
  1571. ql_log(ql_log_warn, vha, 0x70b0,
  1572. "Req:%d: Invalid ISP SCSI completion handle(0x%x)\n",
  1573. req->id, index);
  1574. set_bit(ISP_ABORT_NEEDED, &vha->dpc_flags);
  1575. return;
  1576. }
  1577. if (IS_FWI2_CAPABLE(ha)) {
  1578. comp_status = le16_to_cpu(sts24->comp_status);
  1579. scsi_status = le16_to_cpu(sts24->scsi_status) & SS_MASK;
  1580. } else {
  1581. comp_status = le16_to_cpu(sts->comp_status);
  1582. scsi_status = le16_to_cpu(sts->scsi_status) & SS_MASK;
  1583. }
  1584. thread_id = bsg_job->request->rqst_data.h_vendor.vendor_cmd[1];
  1585. switch (comp_status) {
  1586. case CS_COMPLETE:
  1587. if (scsi_status == 0) {
  1588. bsg_job->reply->reply_payload_rcv_len =
  1589. bsg_job->reply_payload.payload_len;
  1590. rval = EXT_STATUS_OK;
  1591. }
  1592. goto done;
  1593. case CS_DATA_OVERRUN:
  1594. ql_dbg(ql_dbg_user, vha, 0x70b1,
  1595. "Command completed with date overrun thread_id=%d\n",
  1596. thread_id);
  1597. rval = EXT_STATUS_DATA_OVERRUN;
  1598. break;
  1599. case CS_DATA_UNDERRUN:
  1600. ql_dbg(ql_dbg_user, vha, 0x70b2,
  1601. "Command completed with date underrun thread_id=%d\n",
  1602. thread_id);
  1603. rval = EXT_STATUS_DATA_UNDERRUN;
  1604. break;
  1605. case CS_BIDIR_RD_OVERRUN:
  1606. ql_dbg(ql_dbg_user, vha, 0x70b3,
  1607. "Command completed with read data overrun thread_id=%d\n",
  1608. thread_id);
  1609. rval = EXT_STATUS_DATA_OVERRUN;
  1610. break;
  1611. case CS_BIDIR_RD_WR_OVERRUN:
  1612. ql_dbg(ql_dbg_user, vha, 0x70b4,
  1613. "Command completed with read and write data overrun "
  1614. "thread_id=%d\n", thread_id);
  1615. rval = EXT_STATUS_DATA_OVERRUN;
  1616. break;
  1617. case CS_BIDIR_RD_OVERRUN_WR_UNDERRUN:
  1618. ql_dbg(ql_dbg_user, vha, 0x70b5,
  1619. "Command completed with read data over and write data "
  1620. "underrun thread_id=%d\n", thread_id);
  1621. rval = EXT_STATUS_DATA_OVERRUN;
  1622. break;
  1623. case CS_BIDIR_RD_UNDERRUN:
  1624. ql_dbg(ql_dbg_user, vha, 0x70b6,
  1625. "Command completed with read data data underrun "
  1626. "thread_id=%d\n", thread_id);
  1627. rval = EXT_STATUS_DATA_UNDERRUN;
  1628. break;
  1629. case CS_BIDIR_RD_UNDERRUN_WR_OVERRUN:
  1630. ql_dbg(ql_dbg_user, vha, 0x70b7,
  1631. "Command completed with read data under and write data "
  1632. "overrun thread_id=%d\n", thread_id);
  1633. rval = EXT_STATUS_DATA_UNDERRUN;
  1634. break;
  1635. case CS_BIDIR_RD_WR_UNDERRUN:
  1636. ql_dbg(ql_dbg_user, vha, 0x70b8,
  1637. "Command completed with read and write data underrun "
  1638. "thread_id=%d\n", thread_id);
  1639. rval = EXT_STATUS_DATA_UNDERRUN;
  1640. break;
  1641. case CS_BIDIR_DMA:
  1642. ql_dbg(ql_dbg_user, vha, 0x70b9,
  1643. "Command completed with data DMA error thread_id=%d\n",
  1644. thread_id);
  1645. rval = EXT_STATUS_DMA_ERR;
  1646. break;
  1647. case CS_TIMEOUT:
  1648. ql_dbg(ql_dbg_user, vha, 0x70ba,
  1649. "Command completed with timeout thread_id=%d\n",
  1650. thread_id);
  1651. rval = EXT_STATUS_TIMEOUT;
  1652. break;
  1653. default:
  1654. ql_dbg(ql_dbg_user, vha, 0x70bb,
  1655. "Command completed with completion status=0x%x "
  1656. "thread_id=%d\n", comp_status, thread_id);
  1657. rval = EXT_STATUS_ERR;
  1658. break;
  1659. }
  1660. bsg_job->reply->reply_payload_rcv_len = 0;
  1661. done:
  1662. /* Return the vendor specific reply to API */
  1663. bsg_job->reply->reply_data.vendor_reply.vendor_rsp[0] = rval;
  1664. bsg_job->reply_len = sizeof(struct fc_bsg_reply);
  1665. /* Always return DID_OK, bsg will send the vendor specific response
  1666. * in this case only */
  1667. sp->done(vha, sp, (DID_OK << 6));
  1668. }
  1669. /**
  1670. * qla2x00_status_entry() - Process a Status IOCB entry.
  1671. * @ha: SCSI driver HA context
  1672. * @pkt: Entry pointer
  1673. */
  1674. static void
  1675. qla2x00_status_entry(scsi_qla_host_t *vha, struct rsp_que *rsp, void *pkt)
  1676. {
  1677. srb_t *sp;
  1678. fc_port_t *fcport;
  1679. struct scsi_cmnd *cp;
  1680. sts_entry_t *sts;
  1681. struct sts_entry_24xx *sts24;
  1682. uint16_t comp_status;
  1683. uint16_t scsi_status;
  1684. uint16_t ox_id;
  1685. uint8_t lscsi_status;
  1686. int32_t resid;
  1687. uint32_t sense_len, par_sense_len, rsp_info_len, resid_len,
  1688. fw_resid_len;
  1689. uint8_t *rsp_info, *sense_data;
  1690. struct qla_hw_data *ha = vha->hw;
  1691. uint32_t handle;
  1692. uint16_t que;
  1693. struct req_que *req;
  1694. int logit = 1;
  1695. int res = 0;
  1696. uint16_t state_flags = 0;
  1697. sts = (sts_entry_t *) pkt;
  1698. sts24 = (struct sts_entry_24xx *) pkt;
  1699. if (IS_FWI2_CAPABLE(ha)) {
  1700. comp_status = le16_to_cpu(sts24->comp_status);
  1701. scsi_status = le16_to_cpu(sts24->scsi_status) & SS_MASK;
  1702. state_flags = le16_to_cpu(sts24->state_flags);
  1703. } else {
  1704. comp_status = le16_to_cpu(sts->comp_status);
  1705. scsi_status = le16_to_cpu(sts->scsi_status) & SS_MASK;
  1706. }
  1707. handle = (uint32_t) LSW(sts->handle);
  1708. que = MSW(sts->handle);
  1709. req = ha->req_q_map[que];
  1710. /* Validate handle. */
  1711. if (handle < req->num_outstanding_cmds)
  1712. sp = req->outstanding_cmds[handle];
  1713. else
  1714. sp = NULL;
  1715. if (sp == NULL) {
  1716. ql_dbg(ql_dbg_io, vha, 0x3017,
  1717. "Invalid status handle (0x%x).\n", sts->handle);
  1718. if (IS_QLA82XX(ha))
  1719. set_bit(FCOE_CTX_RESET_NEEDED, &vha->dpc_flags);
  1720. else
  1721. set_bit(ISP_ABORT_NEEDED, &vha->dpc_flags);
  1722. qla2xxx_wake_dpc(vha);
  1723. return;
  1724. }
  1725. if (unlikely((state_flags & BIT_1) && (sp->type == SRB_BIDI_CMD))) {
  1726. qla25xx_process_bidir_status_iocb(vha, pkt, req, handle);
  1727. return;
  1728. }
  1729. /* Fast path completion. */
  1730. if (comp_status == CS_COMPLETE && scsi_status == 0) {
  1731. qla2x00_do_host_ramp_up(vha);
  1732. qla2x00_process_completed_request(vha, req, handle);
  1733. return;
  1734. }
  1735. req->outstanding_cmds[handle] = NULL;
  1736. cp = GET_CMD_SP(sp);
  1737. if (cp == NULL) {
  1738. ql_dbg(ql_dbg_io, vha, 0x3018,
  1739. "Command already returned (0x%x/%p).\n",
  1740. sts->handle, sp);
  1741. return;
  1742. }
  1743. lscsi_status = scsi_status & STATUS_MASK;
  1744. fcport = sp->fcport;
  1745. ox_id = 0;
  1746. sense_len = par_sense_len = rsp_info_len = resid_len =
  1747. fw_resid_len = 0;
  1748. if (IS_FWI2_CAPABLE(ha)) {
  1749. if (scsi_status & SS_SENSE_LEN_VALID)
  1750. sense_len = le32_to_cpu(sts24->sense_len);
  1751. if (scsi_status & SS_RESPONSE_INFO_LEN_VALID)
  1752. rsp_info_len = le32_to_cpu(sts24->rsp_data_len);
  1753. if (scsi_status & (SS_RESIDUAL_UNDER | SS_RESIDUAL_OVER))
  1754. resid_len = le32_to_cpu(sts24->rsp_residual_count);
  1755. if (comp_status == CS_DATA_UNDERRUN)
  1756. fw_resid_len = le32_to_cpu(sts24->residual_len);
  1757. rsp_info = sts24->data;
  1758. sense_data = sts24->data;
  1759. host_to_fcp_swap(sts24->data, sizeof(sts24->data));
  1760. ox_id = le16_to_cpu(sts24->ox_id);
  1761. par_sense_len = sizeof(sts24->data);
  1762. } else {
  1763. if (scsi_status & SS_SENSE_LEN_VALID)
  1764. sense_len = le16_to_cpu(sts->req_sense_length);
  1765. if (scsi_status & SS_RESPONSE_INFO_LEN_VALID)
  1766. rsp_info_len = le16_to_cpu(sts->rsp_info_len);
  1767. resid_len = le32_to_cpu(sts->residual_length);
  1768. rsp_info = sts->rsp_info;
  1769. sense_data = sts->req_sense_data;
  1770. par_sense_len = sizeof(sts->req_sense_data);
  1771. }
  1772. /* Check for any FCP transport errors. */
  1773. if (scsi_status & SS_RESPONSE_INFO_LEN_VALID) {
  1774. /* Sense data lies beyond any FCP RESPONSE data. */
  1775. if (IS_FWI2_CAPABLE(ha)) {
  1776. sense_data += rsp_info_len;
  1777. par_sense_len -= rsp_info_len;
  1778. }
  1779. if (rsp_info_len > 3 && rsp_info[3]) {
  1780. ql_dbg(ql_dbg_io, fcport->vha, 0x3019,
  1781. "FCP I/O protocol failure (0x%x/0x%x).\n",
  1782. rsp_info_len, rsp_info[3]);
  1783. res = DID_BUS_BUSY << 16;
  1784. goto out;
  1785. }
  1786. }
  1787. /* Check for overrun. */
  1788. if (IS_FWI2_CAPABLE(ha) && comp_status == CS_COMPLETE &&
  1789. scsi_status & SS_RESIDUAL_OVER)
  1790. comp_status = CS_DATA_OVERRUN;
  1791. /*
  1792. * Based on Host and scsi status generate status code for Linux
  1793. */
  1794. switch (comp_status) {
  1795. case CS_COMPLETE:
  1796. case CS_QUEUE_FULL:
  1797. if (scsi_status == 0) {
  1798. res = DID_OK << 16;
  1799. break;
  1800. }
  1801. if (scsi_status & (SS_RESIDUAL_UNDER | SS_RESIDUAL_OVER)) {
  1802. resid = resid_len;
  1803. scsi_set_resid(cp, resid);
  1804. if (!lscsi_status &&
  1805. ((unsigned)(scsi_bufflen(cp) - resid) <
  1806. cp->underflow)) {
  1807. ql_dbg(ql_dbg_io, fcport->vha, 0x301a,
  1808. "Mid-layer underflow "
  1809. "detected (0x%x of 0x%x bytes).\n",
  1810. resid, scsi_bufflen(cp));
  1811. res = DID_ERROR << 16;
  1812. break;
  1813. }
  1814. }
  1815. res = DID_OK << 16 | lscsi_status;
  1816. if (lscsi_status == SAM_STAT_TASK_SET_FULL) {
  1817. ql_dbg(ql_dbg_io, fcport->vha, 0x301b,
  1818. "QUEUE FULL detected.\n");
  1819. break;
  1820. }
  1821. logit = 0;
  1822. if (lscsi_status != SS_CHECK_CONDITION)
  1823. break;
  1824. memset(cp->sense_buffer, 0, SCSI_SENSE_BUFFERSIZE);
  1825. if (!(scsi_status & SS_SENSE_LEN_VALID))
  1826. break;
  1827. qla2x00_handle_sense(sp, sense_data, par_sense_len, sense_len,
  1828. rsp, res);
  1829. break;
  1830. case CS_DATA_UNDERRUN:
  1831. /* Use F/W calculated residual length. */
  1832. resid = IS_FWI2_CAPABLE(ha) ? fw_resid_len : resid_len;
  1833. scsi_set_resid(cp, resid);
  1834. if (scsi_status & SS_RESIDUAL_UNDER) {
  1835. if (IS_FWI2_CAPABLE(ha) && fw_resid_len != resid_len) {
  1836. ql_dbg(ql_dbg_io, fcport->vha, 0x301d,
  1837. "Dropped frame(s) detected "
  1838. "(0x%x of 0x%x bytes).\n",
  1839. resid, scsi_bufflen(cp));
  1840. res = DID_ERROR << 16 | lscsi_status;
  1841. goto check_scsi_status;
  1842. }
  1843. if (!lscsi_status &&
  1844. ((unsigned)(scsi_bufflen(cp) - resid) <
  1845. cp->underflow)) {
  1846. ql_dbg(ql_dbg_io, fcport->vha, 0x301e,
  1847. "Mid-layer underflow "
  1848. "detected (0x%x of 0x%x bytes).\n",
  1849. resid, scsi_bufflen(cp));
  1850. res = DID_ERROR << 16;
  1851. break;
  1852. }
  1853. } else if (lscsi_status != SAM_STAT_TASK_SET_FULL &&
  1854. lscsi_status != SAM_STAT_BUSY) {
  1855. /*
  1856. * scsi status of task set and busy are considered to be
  1857. * task not completed.
  1858. */
  1859. ql_dbg(ql_dbg_io, fcport->vha, 0x301f,
  1860. "Dropped frame(s) detected (0x%x "
  1861. "of 0x%x bytes).\n", resid,
  1862. scsi_bufflen(cp));
  1863. res = DID_ERROR << 16 | lscsi_status;
  1864. goto check_scsi_status;
  1865. } else {
  1866. ql_dbg(ql_dbg_io, fcport->vha, 0x3030,
  1867. "scsi_status: 0x%x, lscsi_status: 0x%x\n",
  1868. scsi_status, lscsi_status);
  1869. }
  1870. res = DID_OK << 16 | lscsi_status;
  1871. logit = 0;
  1872. check_scsi_status:
  1873. /*
  1874. * Check to see if SCSI Status is non zero. If so report SCSI
  1875. * Status.
  1876. */
  1877. if (lscsi_status != 0) {
  1878. if (lscsi_status == SAM_STAT_TASK_SET_FULL) {
  1879. ql_dbg(ql_dbg_io, fcport->vha, 0x3020,
  1880. "QUEUE FULL detected.\n");
  1881. logit = 1;
  1882. break;
  1883. }
  1884. if (lscsi_status != SS_CHECK_CONDITION)
  1885. break;
  1886. memset(cp->sense_buffer, 0, SCSI_SENSE_BUFFERSIZE);
  1887. if (!(scsi_status & SS_SENSE_LEN_VALID))
  1888. break;
  1889. qla2x00_handle_sense(sp, sense_data, par_sense_len,
  1890. sense_len, rsp, res);
  1891. }
  1892. break;
  1893. case CS_PORT_LOGGED_OUT:
  1894. case CS_PORT_CONFIG_CHG:
  1895. case CS_PORT_BUSY:
  1896. case CS_INCOMPLETE:
  1897. case CS_PORT_UNAVAILABLE:
  1898. case CS_TIMEOUT:
  1899. case CS_RESET:
  1900. /*
  1901. * We are going to have the fc class block the rport
  1902. * while we try to recover so instruct the mid layer
  1903. * to requeue until the class decides how to handle this.
  1904. */
  1905. res = DID_TRANSPORT_DISRUPTED << 16;
  1906. if (comp_status == CS_TIMEOUT) {
  1907. if (IS_FWI2_CAPABLE(ha))
  1908. break;
  1909. else if ((le16_to_cpu(sts->status_flags) &
  1910. SF_LOGOUT_SENT) == 0)
  1911. break;
  1912. }
  1913. ql_dbg(ql_dbg_io, fcport->vha, 0x3021,
  1914. "Port down status: port-state=0x%x.\n",
  1915. atomic_read(&fcport->state));
  1916. if (atomic_read(&fcport->state) == FCS_ONLINE)
  1917. qla2x00_mark_device_lost(fcport->vha, fcport, 1, 1);
  1918. break;
  1919. case CS_ABORTED:
  1920. res = DID_RESET << 16;
  1921. break;
  1922. case CS_DIF_ERROR:
  1923. logit = qla2x00_handle_dif_error(sp, sts24);
  1924. res = cp->result;
  1925. break;
  1926. case CS_TRANSPORT:
  1927. res = DID_ERROR << 16;
  1928. if (!IS_PI_SPLIT_DET_CAPABLE(ha))
  1929. break;
  1930. if (state_flags & BIT_4)
  1931. scmd_printk(KERN_WARNING, cp,
  1932. "Unsupported device '%s' found.\n",
  1933. cp->device->vendor);
  1934. break;
  1935. default:
  1936. res = DID_ERROR << 16;
  1937. break;
  1938. }
  1939. out:
  1940. if (logit)
  1941. ql_dbg(ql_dbg_io, fcport->vha, 0x3022,
  1942. "FCP command status: 0x%x-0x%x (0x%x) "
  1943. "nexus=%ld:%d:%d portid=%02x%02x%02x oxid=0x%x "
  1944. "cdb=%02x%02x%02x%02x%02x%02x%02x%02x%02x%02x len=0x%x "
  1945. "rsp_info=0x%x resid=0x%x fw_resid=0x%x.\n",
  1946. comp_status, scsi_status, res, vha->host_no,
  1947. cp->device->id, cp->device->lun, fcport->d_id.b.domain,
  1948. fcport->d_id.b.area, fcport->d_id.b.al_pa, ox_id,
  1949. cp->cmnd[0], cp->cmnd[1], cp->cmnd[2], cp->cmnd[3],
  1950. cp->cmnd[4], cp->cmnd[5], cp->cmnd[6], cp->cmnd[7],
  1951. cp->cmnd[8], cp->cmnd[9], scsi_bufflen(cp), rsp_info_len,
  1952. resid_len, fw_resid_len);
  1953. if (!res)
  1954. qla2x00_do_host_ramp_up(vha);
  1955. if (rsp->status_srb == NULL)
  1956. sp->done(ha, sp, res);
  1957. }
  1958. /**
  1959. * qla2x00_status_cont_entry() - Process a Status Continuations entry.
  1960. * @ha: SCSI driver HA context
  1961. * @pkt: Entry pointer
  1962. *
  1963. * Extended sense data.
  1964. */
  1965. static void
  1966. qla2x00_status_cont_entry(struct rsp_que *rsp, sts_cont_entry_t *pkt)
  1967. {
  1968. uint8_t sense_sz = 0;
  1969. struct qla_hw_data *ha = rsp->hw;
  1970. struct scsi_qla_host *vha = pci_get_drvdata(ha->pdev);
  1971. srb_t *sp = rsp->status_srb;
  1972. struct scsi_cmnd *cp;
  1973. uint32_t sense_len;
  1974. uint8_t *sense_ptr;
  1975. if (!sp || !GET_CMD_SENSE_LEN(sp))
  1976. return;
  1977. sense_len = GET_CMD_SENSE_LEN(sp);
  1978. sense_ptr = GET_CMD_SENSE_PTR(sp);
  1979. cp = GET_CMD_SP(sp);
  1980. if (cp == NULL) {
  1981. ql_log(ql_log_warn, vha, 0x3025,
  1982. "cmd is NULL: already returned to OS (sp=%p).\n", sp);
  1983. rsp->status_srb = NULL;
  1984. return;
  1985. }
  1986. if (sense_len > sizeof(pkt->data))
  1987. sense_sz = sizeof(pkt->data);
  1988. else
  1989. sense_sz = sense_len;
  1990. /* Move sense data. */
  1991. if (IS_FWI2_CAPABLE(ha))
  1992. host_to_fcp_swap(pkt->data, sizeof(pkt->data));
  1993. memcpy(sense_ptr, pkt->data, sense_sz);
  1994. ql_dump_buffer(ql_dbg_io + ql_dbg_buffer, vha, 0x302c,
  1995. sense_ptr, sense_sz);
  1996. sense_len -= sense_sz;
  1997. sense_ptr += sense_sz;
  1998. SET_CMD_SENSE_PTR(sp, sense_ptr);
  1999. SET_CMD_SENSE_LEN(sp, sense_len);
  2000. /* Place command on done queue. */
  2001. if (sense_len == 0) {
  2002. rsp->status_srb = NULL;
  2003. sp->done(ha, sp, cp->result);
  2004. }
  2005. }
  2006. /**
  2007. * qla2x00_error_entry() - Process an error entry.
  2008. * @ha: SCSI driver HA context
  2009. * @pkt: Entry pointer
  2010. */
  2011. static void
  2012. qla2x00_error_entry(scsi_qla_host_t *vha, struct rsp_que *rsp, sts_entry_t *pkt)
  2013. {
  2014. srb_t *sp;
  2015. struct qla_hw_data *ha = vha->hw;
  2016. const char func[] = "ERROR-IOCB";
  2017. uint16_t que = MSW(pkt->handle);
  2018. struct req_que *req = NULL;
  2019. int res = DID_ERROR << 16;
  2020. ql_dbg(ql_dbg_async, vha, 0x502a,
  2021. "type of error status in response: 0x%x\n", pkt->entry_status);
  2022. if (que >= ha->max_req_queues || !ha->req_q_map[que])
  2023. goto fatal;
  2024. req = ha->req_q_map[que];
  2025. if (pkt->entry_status & RF_BUSY)
  2026. res = DID_BUS_BUSY << 16;
  2027. sp = qla2x00_get_sp_from_handle(vha, func, req, pkt);
  2028. if (sp) {
  2029. sp->done(ha, sp, res);
  2030. return;
  2031. }
  2032. fatal:
  2033. ql_log(ql_log_warn, vha, 0x5030,
  2034. "Error entry - invalid handle/queue.\n");
  2035. if (IS_QLA82XX(ha))
  2036. set_bit(FCOE_CTX_RESET_NEEDED, &vha->dpc_flags);
  2037. else
  2038. set_bit(ISP_ABORT_NEEDED, &vha->dpc_flags);
  2039. qla2xxx_wake_dpc(vha);
  2040. }
  2041. /**
  2042. * qla24xx_mbx_completion() - Process mailbox command completions.
  2043. * @ha: SCSI driver HA context
  2044. * @mb0: Mailbox0 register
  2045. */
  2046. static void
  2047. qla24xx_mbx_completion(scsi_qla_host_t *vha, uint16_t mb0)
  2048. {
  2049. uint16_t cnt;
  2050. uint32_t mboxes;
  2051. uint16_t __iomem *wptr;
  2052. struct qla_hw_data *ha = vha->hw;
  2053. struct device_reg_24xx __iomem *reg = &ha->iobase->isp24;
  2054. /* Read all mbox registers? */
  2055. mboxes = (1 << ha->mbx_count) - 1;
  2056. if (!ha->mcp)
  2057. ql_dbg(ql_dbg_async, vha, 0x504e, "MBX pointer ERROR.\n");
  2058. else
  2059. mboxes = ha->mcp->in_mb;
  2060. /* Load return mailbox registers. */
  2061. ha->flags.mbox_int = 1;
  2062. ha->mailbox_out[0] = mb0;
  2063. mboxes >>= 1;
  2064. wptr = (uint16_t __iomem *)&reg->mailbox1;
  2065. for (cnt = 1; cnt < ha->mbx_count; cnt++) {
  2066. if (mboxes & BIT_0)
  2067. ha->mailbox_out[cnt] = RD_REG_WORD(wptr);
  2068. mboxes >>= 1;
  2069. wptr++;
  2070. }
  2071. }
  2072. /**
  2073. * qla24xx_process_response_queue() - Process response queue entries.
  2074. * @ha: SCSI driver HA context
  2075. */
  2076. void qla24xx_process_response_queue(struct scsi_qla_host *vha,
  2077. struct rsp_que *rsp)
  2078. {
  2079. struct sts_entry_24xx *pkt;
  2080. struct qla_hw_data *ha = vha->hw;
  2081. if (!vha->flags.online)
  2082. return;
  2083. while (rsp->ring_ptr->signature != RESPONSE_PROCESSED) {
  2084. pkt = (struct sts_entry_24xx *)rsp->ring_ptr;
  2085. rsp->ring_index++;
  2086. if (rsp->ring_index == rsp->length) {
  2087. rsp->ring_index = 0;
  2088. rsp->ring_ptr = rsp->ring;
  2089. } else {
  2090. rsp->ring_ptr++;
  2091. }
  2092. if (pkt->entry_status != 0) {
  2093. qla2x00_error_entry(vha, rsp, (sts_entry_t *) pkt);
  2094. (void)qlt_24xx_process_response_error(vha, pkt);
  2095. ((response_t *)pkt)->signature = RESPONSE_PROCESSED;
  2096. wmb();
  2097. continue;
  2098. }
  2099. switch (pkt->entry_type) {
  2100. case STATUS_TYPE:
  2101. qla2x00_status_entry(vha, rsp, pkt);
  2102. break;
  2103. case STATUS_CONT_TYPE:
  2104. qla2x00_status_cont_entry(rsp, (sts_cont_entry_t *)pkt);
  2105. break;
  2106. case VP_RPT_ID_IOCB_TYPE:
  2107. qla24xx_report_id_acquisition(vha,
  2108. (struct vp_rpt_id_entry_24xx *)pkt);
  2109. break;
  2110. case LOGINOUT_PORT_IOCB_TYPE:
  2111. qla24xx_logio_entry(vha, rsp->req,
  2112. (struct logio_entry_24xx *)pkt);
  2113. break;
  2114. case TSK_MGMT_IOCB_TYPE:
  2115. qla24xx_tm_iocb_entry(vha, rsp->req,
  2116. (struct tsk_mgmt_entry *)pkt);
  2117. break;
  2118. case CT_IOCB_TYPE:
  2119. qla24xx_els_ct_entry(vha, rsp->req, pkt, CT_IOCB_TYPE);
  2120. break;
  2121. case ELS_IOCB_TYPE:
  2122. qla24xx_els_ct_entry(vha, rsp->req, pkt, ELS_IOCB_TYPE);
  2123. break;
  2124. case ABTS_RECV_24XX:
  2125. /* ensure that the ATIO queue is empty */
  2126. qlt_24xx_process_atio_queue(vha);
  2127. case ABTS_RESP_24XX:
  2128. case CTIO_TYPE7:
  2129. case NOTIFY_ACK_TYPE:
  2130. qlt_response_pkt_all_vps(vha, (response_t *)pkt);
  2131. break;
  2132. case MARKER_TYPE:
  2133. /* Do nothing in this case, this check is to prevent it
  2134. * from falling into default case
  2135. */
  2136. break;
  2137. default:
  2138. /* Type Not Supported. */
  2139. ql_dbg(ql_dbg_async, vha, 0x5042,
  2140. "Received unknown response pkt type %x "
  2141. "entry status=%x.\n",
  2142. pkt->entry_type, pkt->entry_status);
  2143. break;
  2144. }
  2145. ((response_t *)pkt)->signature = RESPONSE_PROCESSED;
  2146. wmb();
  2147. }
  2148. /* Adjust ring index */
  2149. if (IS_QLA82XX(ha)) {
  2150. struct device_reg_82xx __iomem *reg = &ha->iobase->isp82;
  2151. WRT_REG_DWORD(&reg->rsp_q_out[0], rsp->ring_index);
  2152. } else
  2153. WRT_REG_DWORD(rsp->rsp_q_out, rsp->ring_index);
  2154. }
  2155. static void
  2156. qla2xxx_check_risc_status(scsi_qla_host_t *vha)
  2157. {
  2158. int rval;
  2159. uint32_t cnt;
  2160. struct qla_hw_data *ha = vha->hw;
  2161. struct device_reg_24xx __iomem *reg = &ha->iobase->isp24;
  2162. if (!IS_QLA25XX(ha) && !IS_QLA81XX(ha) && !IS_QLA83XX(ha))
  2163. return;
  2164. rval = QLA_SUCCESS;
  2165. WRT_REG_DWORD(&reg->iobase_addr, 0x7C00);
  2166. RD_REG_DWORD(&reg->iobase_addr);
  2167. WRT_REG_DWORD(&reg->iobase_window, 0x0001);
  2168. for (cnt = 10000; (RD_REG_DWORD(&reg->iobase_window) & BIT_0) == 0 &&
  2169. rval == QLA_SUCCESS; cnt--) {
  2170. if (cnt) {
  2171. WRT_REG_DWORD(&reg->iobase_window, 0x0001);
  2172. udelay(10);
  2173. } else
  2174. rval = QLA_FUNCTION_TIMEOUT;
  2175. }
  2176. if (rval == QLA_SUCCESS)
  2177. goto next_test;
  2178. WRT_REG_DWORD(&reg->iobase_window, 0x0003);
  2179. for (cnt = 100; (RD_REG_DWORD(&reg->iobase_window) & BIT_0) == 0 &&
  2180. rval == QLA_SUCCESS; cnt--) {
  2181. if (cnt) {
  2182. WRT_REG_DWORD(&reg->iobase_window, 0x0003);
  2183. udelay(10);
  2184. } else
  2185. rval = QLA_FUNCTION_TIMEOUT;
  2186. }
  2187. if (rval != QLA_SUCCESS)
  2188. goto done;
  2189. next_test:
  2190. if (RD_REG_DWORD(&reg->iobase_c8) & BIT_3)
  2191. ql_log(ql_log_info, vha, 0x504c,
  2192. "Additional code -- 0x55AA.\n");
  2193. done:
  2194. WRT_REG_DWORD(&reg->iobase_window, 0x0000);
  2195. RD_REG_DWORD(&reg->iobase_window);
  2196. }
  2197. /**
  2198. * qla24xx_intr_handler() - Process interrupts for the ISP23xx and ISP24xx.
  2199. * @irq:
  2200. * @dev_id: SCSI driver HA context
  2201. *
  2202. * Called by system whenever the host adapter generates an interrupt.
  2203. *
  2204. * Returns handled flag.
  2205. */
  2206. irqreturn_t
  2207. qla24xx_intr_handler(int irq, void *dev_id)
  2208. {
  2209. scsi_qla_host_t *vha;
  2210. struct qla_hw_data *ha;
  2211. struct device_reg_24xx __iomem *reg;
  2212. int status;
  2213. unsigned long iter;
  2214. uint32_t stat;
  2215. uint32_t hccr;
  2216. uint16_t mb[8];
  2217. struct rsp_que *rsp;
  2218. unsigned long flags;
  2219. rsp = (struct rsp_que *) dev_id;
  2220. if (!rsp) {
  2221. ql_log(ql_log_info, NULL, 0x5059,
  2222. "%s: NULL response queue pointer.\n", __func__);
  2223. return IRQ_NONE;
  2224. }
  2225. ha = rsp->hw;
  2226. reg = &ha->iobase->isp24;
  2227. status = 0;
  2228. if (unlikely(pci_channel_offline(ha->pdev)))
  2229. return IRQ_HANDLED;
  2230. spin_lock_irqsave(&ha->hardware_lock, flags);
  2231. vha = pci_get_drvdata(ha->pdev);
  2232. for (iter = 50; iter--; ) {
  2233. stat = RD_REG_DWORD(&reg->host_status);
  2234. if (stat & HSRX_RISC_PAUSED) {
  2235. if (unlikely(pci_channel_offline(ha->pdev)))
  2236. break;
  2237. hccr = RD_REG_DWORD(&reg->hccr);
  2238. ql_log(ql_log_warn, vha, 0x504b,
  2239. "RISC paused -- HCCR=%x, Dumping firmware.\n",
  2240. hccr);
  2241. qla2xxx_check_risc_status(vha);
  2242. ha->isp_ops->fw_dump(vha, 1);
  2243. set_bit(ISP_ABORT_NEEDED, &vha->dpc_flags);
  2244. break;
  2245. } else if ((stat & HSRX_RISC_INT) == 0)
  2246. break;
  2247. switch (stat & 0xff) {
  2248. case INTR_ROM_MB_SUCCESS:
  2249. case INTR_ROM_MB_FAILED:
  2250. case INTR_MB_SUCCESS:
  2251. case INTR_MB_FAILED:
  2252. qla24xx_mbx_completion(vha, MSW(stat));
  2253. status |= MBX_INTERRUPT;
  2254. break;
  2255. case INTR_ASYNC_EVENT:
  2256. mb[0] = MSW(stat);
  2257. mb[1] = RD_REG_WORD(&reg->mailbox1);
  2258. mb[2] = RD_REG_WORD(&reg->mailbox2);
  2259. mb[3] = RD_REG_WORD(&reg->mailbox3);
  2260. qla2x00_async_event(vha, rsp, mb);
  2261. break;
  2262. case INTR_RSP_QUE_UPDATE:
  2263. case INTR_RSP_QUE_UPDATE_83XX:
  2264. qla24xx_process_response_queue(vha, rsp);
  2265. break;
  2266. case INTR_ATIO_QUE_UPDATE:
  2267. qlt_24xx_process_atio_queue(vha);
  2268. break;
  2269. case INTR_ATIO_RSP_QUE_UPDATE:
  2270. qlt_24xx_process_atio_queue(vha);
  2271. qla24xx_process_response_queue(vha, rsp);
  2272. break;
  2273. default:
  2274. ql_dbg(ql_dbg_async, vha, 0x504f,
  2275. "Unrecognized interrupt type (%d).\n", stat * 0xff);
  2276. break;
  2277. }
  2278. WRT_REG_DWORD(&reg->hccr, HCCRX_CLR_RISC_INT);
  2279. RD_REG_DWORD_RELAXED(&reg->hccr);
  2280. if (unlikely(IS_QLA83XX(ha) && (ha->pdev->revision == 1)))
  2281. ndelay(3500);
  2282. }
  2283. spin_unlock_irqrestore(&ha->hardware_lock, flags);
  2284. if (test_bit(MBX_INTR_WAIT, &ha->mbx_cmd_flags) &&
  2285. (status & MBX_INTERRUPT) && ha->flags.mbox_int) {
  2286. set_bit(MBX_INTERRUPT, &ha->mbx_cmd_flags);
  2287. complete(&ha->mbx_intr_comp);
  2288. }
  2289. return IRQ_HANDLED;
  2290. }
  2291. static irqreturn_t
  2292. qla24xx_msix_rsp_q(int irq, void *dev_id)
  2293. {
  2294. struct qla_hw_data *ha;
  2295. struct rsp_que *rsp;
  2296. struct device_reg_24xx __iomem *reg;
  2297. struct scsi_qla_host *vha;
  2298. unsigned long flags;
  2299. rsp = (struct rsp_que *) dev_id;
  2300. if (!rsp) {
  2301. ql_log(ql_log_info, NULL, 0x505a,
  2302. "%s: NULL response queue pointer.\n", __func__);
  2303. return IRQ_NONE;
  2304. }
  2305. ha = rsp->hw;
  2306. reg = &ha->iobase->isp24;
  2307. spin_lock_irqsave(&ha->hardware_lock, flags);
  2308. vha = pci_get_drvdata(ha->pdev);
  2309. qla24xx_process_response_queue(vha, rsp);
  2310. if (!ha->flags.disable_msix_handshake) {
  2311. WRT_REG_DWORD(&reg->hccr, HCCRX_CLR_RISC_INT);
  2312. RD_REG_DWORD_RELAXED(&reg->hccr);
  2313. }
  2314. spin_unlock_irqrestore(&ha->hardware_lock, flags);
  2315. return IRQ_HANDLED;
  2316. }
  2317. static irqreturn_t
  2318. qla25xx_msix_rsp_q(int irq, void *dev_id)
  2319. {
  2320. struct qla_hw_data *ha;
  2321. struct rsp_que *rsp;
  2322. struct device_reg_24xx __iomem *reg;
  2323. unsigned long flags;
  2324. rsp = (struct rsp_que *) dev_id;
  2325. if (!rsp) {
  2326. ql_log(ql_log_info, NULL, 0x505b,
  2327. "%s: NULL response queue pointer.\n", __func__);
  2328. return IRQ_NONE;
  2329. }
  2330. ha = rsp->hw;
  2331. /* Clear the interrupt, if enabled, for this response queue */
  2332. if (!ha->flags.disable_msix_handshake) {
  2333. reg = &ha->iobase->isp24;
  2334. spin_lock_irqsave(&ha->hardware_lock, flags);
  2335. WRT_REG_DWORD(&reg->hccr, HCCRX_CLR_RISC_INT);
  2336. RD_REG_DWORD_RELAXED(&reg->hccr);
  2337. spin_unlock_irqrestore(&ha->hardware_lock, flags);
  2338. }
  2339. queue_work_on((int) (rsp->id - 1), ha->wq, &rsp->q_work);
  2340. return IRQ_HANDLED;
  2341. }
  2342. static irqreturn_t
  2343. qla24xx_msix_default(int irq, void *dev_id)
  2344. {
  2345. scsi_qla_host_t *vha;
  2346. struct qla_hw_data *ha;
  2347. struct rsp_que *rsp;
  2348. struct device_reg_24xx __iomem *reg;
  2349. int status;
  2350. uint32_t stat;
  2351. uint32_t hccr;
  2352. uint16_t mb[8];
  2353. unsigned long flags;
  2354. rsp = (struct rsp_que *) dev_id;
  2355. if (!rsp) {
  2356. ql_log(ql_log_info, NULL, 0x505c,
  2357. "%s: NULL response queue pointer.\n", __func__);
  2358. return IRQ_NONE;
  2359. }
  2360. ha = rsp->hw;
  2361. reg = &ha->iobase->isp24;
  2362. status = 0;
  2363. spin_lock_irqsave(&ha->hardware_lock, flags);
  2364. vha = pci_get_drvdata(ha->pdev);
  2365. do {
  2366. stat = RD_REG_DWORD(&reg->host_status);
  2367. if (stat & HSRX_RISC_PAUSED) {
  2368. if (unlikely(pci_channel_offline(ha->pdev)))
  2369. break;
  2370. hccr = RD_REG_DWORD(&reg->hccr);
  2371. ql_log(ql_log_info, vha, 0x5050,
  2372. "RISC paused -- HCCR=%x, Dumping firmware.\n",
  2373. hccr);
  2374. qla2xxx_check_risc_status(vha);
  2375. ha->isp_ops->fw_dump(vha, 1);
  2376. set_bit(ISP_ABORT_NEEDED, &vha->dpc_flags);
  2377. break;
  2378. } else if ((stat & HSRX_RISC_INT) == 0)
  2379. break;
  2380. switch (stat & 0xff) {
  2381. case INTR_ROM_MB_SUCCESS:
  2382. case INTR_ROM_MB_FAILED:
  2383. case INTR_MB_SUCCESS:
  2384. case INTR_MB_FAILED:
  2385. qla24xx_mbx_completion(vha, MSW(stat));
  2386. status |= MBX_INTERRUPT;
  2387. break;
  2388. case INTR_ASYNC_EVENT:
  2389. mb[0] = MSW(stat);
  2390. mb[1] = RD_REG_WORD(&reg->mailbox1);
  2391. mb[2] = RD_REG_WORD(&reg->mailbox2);
  2392. mb[3] = RD_REG_WORD(&reg->mailbox3);
  2393. qla2x00_async_event(vha, rsp, mb);
  2394. break;
  2395. case INTR_RSP_QUE_UPDATE:
  2396. case INTR_RSP_QUE_UPDATE_83XX:
  2397. qla24xx_process_response_queue(vha, rsp);
  2398. break;
  2399. case INTR_ATIO_QUE_UPDATE:
  2400. qlt_24xx_process_atio_queue(vha);
  2401. break;
  2402. case INTR_ATIO_RSP_QUE_UPDATE:
  2403. qlt_24xx_process_atio_queue(vha);
  2404. qla24xx_process_response_queue(vha, rsp);
  2405. break;
  2406. default:
  2407. ql_dbg(ql_dbg_async, vha, 0x5051,
  2408. "Unrecognized interrupt type (%d).\n", stat & 0xff);
  2409. break;
  2410. }
  2411. WRT_REG_DWORD(&reg->hccr, HCCRX_CLR_RISC_INT);
  2412. } while (0);
  2413. spin_unlock_irqrestore(&ha->hardware_lock, flags);
  2414. if (test_bit(MBX_INTR_WAIT, &ha->mbx_cmd_flags) &&
  2415. (status & MBX_INTERRUPT) && ha->flags.mbox_int) {
  2416. set_bit(MBX_INTERRUPT, &ha->mbx_cmd_flags);
  2417. complete(&ha->mbx_intr_comp);
  2418. }
  2419. return IRQ_HANDLED;
  2420. }
  2421. /* Interrupt handling helpers. */
  2422. struct qla_init_msix_entry {
  2423. const char *name;
  2424. irq_handler_t handler;
  2425. };
  2426. static struct qla_init_msix_entry msix_entries[3] = {
  2427. { "qla2xxx (default)", qla24xx_msix_default },
  2428. { "qla2xxx (rsp_q)", qla24xx_msix_rsp_q },
  2429. { "qla2xxx (multiq)", qla25xx_msix_rsp_q },
  2430. };
  2431. static struct qla_init_msix_entry qla82xx_msix_entries[2] = {
  2432. { "qla2xxx (default)", qla82xx_msix_default },
  2433. { "qla2xxx (rsp_q)", qla82xx_msix_rsp_q },
  2434. };
  2435. static struct qla_init_msix_entry qla83xx_msix_entries[3] = {
  2436. { "qla2xxx (default)", qla24xx_msix_default },
  2437. { "qla2xxx (rsp_q)", qla24xx_msix_rsp_q },
  2438. { "qla2xxx (atio_q)", qla83xx_msix_atio_q },
  2439. };
  2440. static void
  2441. qla24xx_disable_msix(struct qla_hw_data *ha)
  2442. {
  2443. int i;
  2444. struct qla_msix_entry *qentry;
  2445. scsi_qla_host_t *vha = pci_get_drvdata(ha->pdev);
  2446. for (i = 0; i < ha->msix_count; i++) {
  2447. qentry = &ha->msix_entries[i];
  2448. if (qentry->have_irq)
  2449. free_irq(qentry->vector, qentry->rsp);
  2450. }
  2451. pci_disable_msix(ha->pdev);
  2452. kfree(ha->msix_entries);
  2453. ha->msix_entries = NULL;
  2454. ha->flags.msix_enabled = 0;
  2455. ql_dbg(ql_dbg_init, vha, 0x0042,
  2456. "Disabled the MSI.\n");
  2457. }
  2458. static int
  2459. qla24xx_enable_msix(struct qla_hw_data *ha, struct rsp_que *rsp)
  2460. {
  2461. #define MIN_MSIX_COUNT 2
  2462. int i, ret;
  2463. struct msix_entry *entries;
  2464. struct qla_msix_entry *qentry;
  2465. scsi_qla_host_t *vha = pci_get_drvdata(ha->pdev);
  2466. entries = kzalloc(sizeof(struct msix_entry) * ha->msix_count,
  2467. GFP_KERNEL);
  2468. if (!entries) {
  2469. ql_log(ql_log_warn, vha, 0x00bc,
  2470. "Failed to allocate memory for msix_entry.\n");
  2471. return -ENOMEM;
  2472. }
  2473. for (i = 0; i < ha->msix_count; i++)
  2474. entries[i].entry = i;
  2475. ret = pci_enable_msix(ha->pdev, entries, ha->msix_count);
  2476. if (ret) {
  2477. if (ret < MIN_MSIX_COUNT)
  2478. goto msix_failed;
  2479. ql_log(ql_log_warn, vha, 0x00c6,
  2480. "MSI-X: Failed to enable support "
  2481. "-- %d/%d\n Retry with %d vectors.\n",
  2482. ha->msix_count, ret, ret);
  2483. ha->msix_count = ret;
  2484. ret = pci_enable_msix(ha->pdev, entries, ha->msix_count);
  2485. if (ret) {
  2486. msix_failed:
  2487. ql_log(ql_log_fatal, vha, 0x00c7,
  2488. "MSI-X: Failed to enable support, "
  2489. "giving up -- %d/%d.\n",
  2490. ha->msix_count, ret);
  2491. goto msix_out;
  2492. }
  2493. ha->max_rsp_queues = ha->msix_count - 1;
  2494. }
  2495. ha->msix_entries = kzalloc(sizeof(struct qla_msix_entry) *
  2496. ha->msix_count, GFP_KERNEL);
  2497. if (!ha->msix_entries) {
  2498. ql_log(ql_log_fatal, vha, 0x00c8,
  2499. "Failed to allocate memory for ha->msix_entries.\n");
  2500. ret = -ENOMEM;
  2501. goto msix_out;
  2502. }
  2503. ha->flags.msix_enabled = 1;
  2504. for (i = 0; i < ha->msix_count; i++) {
  2505. qentry = &ha->msix_entries[i];
  2506. qentry->vector = entries[i].vector;
  2507. qentry->entry = entries[i].entry;
  2508. qentry->have_irq = 0;
  2509. qentry->rsp = NULL;
  2510. }
  2511. /* Enable MSI-X vectors for the base queue */
  2512. for (i = 0; i < ha->msix_count; i++) {
  2513. qentry = &ha->msix_entries[i];
  2514. if (QLA_TGT_MODE_ENABLED() && IS_ATIO_MSIX_CAPABLE(ha)) {
  2515. ret = request_irq(qentry->vector,
  2516. qla83xx_msix_entries[i].handler,
  2517. 0, qla83xx_msix_entries[i].name, rsp);
  2518. } else if (IS_QLA82XX(ha)) {
  2519. ret = request_irq(qentry->vector,
  2520. qla82xx_msix_entries[i].handler,
  2521. 0, qla82xx_msix_entries[i].name, rsp);
  2522. } else {
  2523. ret = request_irq(qentry->vector,
  2524. msix_entries[i].handler,
  2525. 0, msix_entries[i].name, rsp);
  2526. }
  2527. if (ret) {
  2528. ql_log(ql_log_fatal, vha, 0x00cb,
  2529. "MSI-X: unable to register handler -- %x/%d.\n",
  2530. qentry->vector, ret);
  2531. qla24xx_disable_msix(ha);
  2532. ha->mqenable = 0;
  2533. goto msix_out;
  2534. }
  2535. qentry->have_irq = 1;
  2536. qentry->rsp = rsp;
  2537. rsp->msix = qentry;
  2538. }
  2539. /* Enable MSI-X vector for response queue update for queue 0 */
  2540. if (IS_QLA83XX(ha)) {
  2541. if (ha->msixbase && ha->mqiobase &&
  2542. (ha->max_rsp_queues > 1 || ha->max_req_queues > 1))
  2543. ha->mqenable = 1;
  2544. } else
  2545. if (ha->mqiobase
  2546. && (ha->max_rsp_queues > 1 || ha->max_req_queues > 1))
  2547. ha->mqenable = 1;
  2548. ql_dbg(ql_dbg_multiq, vha, 0xc005,
  2549. "mqiobase=%p, max_rsp_queues=%d, max_req_queues=%d.\n",
  2550. ha->mqiobase, ha->max_rsp_queues, ha->max_req_queues);
  2551. ql_dbg(ql_dbg_init, vha, 0x0055,
  2552. "mqiobase=%p, max_rsp_queues=%d, max_req_queues=%d.\n",
  2553. ha->mqiobase, ha->max_rsp_queues, ha->max_req_queues);
  2554. msix_out:
  2555. kfree(entries);
  2556. return ret;
  2557. }
  2558. int
  2559. qla2x00_request_irqs(struct qla_hw_data *ha, struct rsp_que *rsp)
  2560. {
  2561. int ret;
  2562. device_reg_t __iomem *reg = ha->iobase;
  2563. scsi_qla_host_t *vha = pci_get_drvdata(ha->pdev);
  2564. /* If possible, enable MSI-X. */
  2565. if (!IS_QLA2432(ha) && !IS_QLA2532(ha) && !IS_QLA8432(ha) &&
  2566. !IS_CNA_CAPABLE(ha) && !IS_QLA2031(ha))
  2567. goto skip_msi;
  2568. if (ha->pdev->subsystem_vendor == PCI_VENDOR_ID_HP &&
  2569. (ha->pdev->subsystem_device == 0x7040 ||
  2570. ha->pdev->subsystem_device == 0x7041 ||
  2571. ha->pdev->subsystem_device == 0x1705)) {
  2572. ql_log(ql_log_warn, vha, 0x0034,
  2573. "MSI-X: Unsupported ISP 2432 SSVID/SSDID (0x%X,0x%X).\n",
  2574. ha->pdev->subsystem_vendor,
  2575. ha->pdev->subsystem_device);
  2576. goto skip_msi;
  2577. }
  2578. if (IS_QLA2432(ha) && (ha->pdev->revision < QLA_MSIX_CHIP_REV_24XX)) {
  2579. ql_log(ql_log_warn, vha, 0x0035,
  2580. "MSI-X; Unsupported ISP2432 (0x%X, 0x%X).\n",
  2581. ha->pdev->revision, QLA_MSIX_CHIP_REV_24XX);
  2582. goto skip_msix;
  2583. }
  2584. ret = qla24xx_enable_msix(ha, rsp);
  2585. if (!ret) {
  2586. ql_dbg(ql_dbg_init, vha, 0x0036,
  2587. "MSI-X: Enabled (0x%X, 0x%X).\n",
  2588. ha->chip_revision, ha->fw_attributes);
  2589. goto clear_risc_ints;
  2590. }
  2591. ql_log(ql_log_info, vha, 0x0037,
  2592. "MSI-X Falling back-to MSI mode -%d.\n", ret);
  2593. skip_msix:
  2594. if (!IS_QLA24XX(ha) && !IS_QLA2532(ha) && !IS_QLA8432(ha) &&
  2595. !IS_QLA8001(ha) && !IS_QLA82XX(ha))
  2596. goto skip_msi;
  2597. ret = pci_enable_msi(ha->pdev);
  2598. if (!ret) {
  2599. ql_dbg(ql_dbg_init, vha, 0x0038,
  2600. "MSI: Enabled.\n");
  2601. ha->flags.msi_enabled = 1;
  2602. } else
  2603. ql_log(ql_log_warn, vha, 0x0039,
  2604. "MSI-X; Falling back-to INTa mode -- %d.\n", ret);
  2605. /* Skip INTx on ISP82xx. */
  2606. if (!ha->flags.msi_enabled && IS_QLA82XX(ha))
  2607. return QLA_FUNCTION_FAILED;
  2608. skip_msi:
  2609. ret = request_irq(ha->pdev->irq, ha->isp_ops->intr_handler,
  2610. ha->flags.msi_enabled ? 0 : IRQF_SHARED,
  2611. QLA2XXX_DRIVER_NAME, rsp);
  2612. if (ret) {
  2613. ql_log(ql_log_warn, vha, 0x003a,
  2614. "Failed to reserve interrupt %d already in use.\n",
  2615. ha->pdev->irq);
  2616. goto fail;
  2617. } else if (!ha->flags.msi_enabled)
  2618. ql_dbg(ql_dbg_init, vha, 0x0125,
  2619. "INTa mode: Enabled.\n");
  2620. clear_risc_ints:
  2621. spin_lock_irq(&ha->hardware_lock);
  2622. if (!IS_FWI2_CAPABLE(ha))
  2623. WRT_REG_WORD(&reg->isp.semaphore, 0);
  2624. spin_unlock_irq(&ha->hardware_lock);
  2625. fail:
  2626. return ret;
  2627. }
  2628. void
  2629. qla2x00_free_irqs(scsi_qla_host_t *vha)
  2630. {
  2631. struct qla_hw_data *ha = vha->hw;
  2632. struct rsp_que *rsp;
  2633. /*
  2634. * We need to check that ha->rsp_q_map is valid in case we are called
  2635. * from a probe failure context.
  2636. */
  2637. if (!ha->rsp_q_map || !ha->rsp_q_map[0])
  2638. return;
  2639. rsp = ha->rsp_q_map[0];
  2640. if (ha->flags.msix_enabled)
  2641. qla24xx_disable_msix(ha);
  2642. else if (ha->flags.msi_enabled) {
  2643. free_irq(ha->pdev->irq, rsp);
  2644. pci_disable_msi(ha->pdev);
  2645. } else
  2646. free_irq(ha->pdev->irq, rsp);
  2647. }
  2648. int qla25xx_request_irq(struct rsp_que *rsp)
  2649. {
  2650. struct qla_hw_data *ha = rsp->hw;
  2651. struct qla_init_msix_entry *intr = &msix_entries[2];
  2652. struct qla_msix_entry *msix = rsp->msix;
  2653. scsi_qla_host_t *vha = pci_get_drvdata(ha->pdev);
  2654. int ret;
  2655. ret = request_irq(msix->vector, intr->handler, 0, intr->name, rsp);
  2656. if (ret) {
  2657. ql_log(ql_log_fatal, vha, 0x00e6,
  2658. "MSI-X: Unable to register handler -- %x/%d.\n",
  2659. msix->vector, ret);
  2660. return ret;
  2661. }
  2662. msix->have_irq = 1;
  2663. msix->rsp = rsp;
  2664. return ret;
  2665. }