core.c 12 KB

123456789101112131415161718192021222324252627282930313233343536373839404142434445464748495051525354555657585960616263646566676869707172737475767778798081828384858687888990919293949596979899100101102103104105106107108109110111112113114115116117118119120121122123124125126127128129130131132133134135136137138139140141142143144145146147148149150151152153154155156157158159160161162163164165166167168169170171172173174175176177178179180181182183184185186187188189190191192193194195196197198199200201202203204205206207208209210211212213214215216217218219220221222223224225226227228229230231232233234235236237238239240241242243244245246247248249250251252253254255256257258259260261262263264265266267268269270271272273274275276277278279280281282283284285286287288289290291292293294295296297298299300301302303304305306307308309310311312313314315316317318319320321322323324325326327328329330331332333334335336337338339340341342343344345346347348349350351352353354355356357358359360361362363364365366367368369370371372373374375376377378379380381382383384385386387388389390391392393394395396397398399400401402403404405406407408409410411412413414415416417418419420421422423424425426427428429430431432433434435436437438439440441442443444445446447448449450451452453454455456457458459460461462463464465466467468469470471472473474475476477478479480481482483484485486487488489490491492493494495496497498499500501502503504505506507508509510511512513514515516517518519520521522523524525526527528529530531532533534535536
  1. /*
  2. * core.c - ChipIdea USB IP core family device controller
  3. *
  4. * Copyright (C) 2008 Chipidea - MIPS Technologies, Inc. All rights reserved.
  5. *
  6. * Author: David Lopo
  7. *
  8. * This program is free software; you can redistribute it and/or modify
  9. * it under the terms of the GNU General Public License version 2 as
  10. * published by the Free Software Foundation.
  11. */
  12. /*
  13. * Description: ChipIdea USB IP core family device controller
  14. *
  15. * This driver is composed of several blocks:
  16. * - HW: hardware interface
  17. * - DBG: debug facilities (optional)
  18. * - UTIL: utilities
  19. * - ISR: interrupts handling
  20. * - ENDPT: endpoint operations (Gadget API)
  21. * - GADGET: gadget operations (Gadget API)
  22. * - BUS: bus glue code, bus abstraction layer
  23. *
  24. * Compile Options
  25. * - CONFIG_USB_GADGET_DEBUG_FILES: enable debug facilities
  26. * - STALL_IN: non-empty bulk-in pipes cannot be halted
  27. * if defined mass storage compliance succeeds but with warnings
  28. * => case 4: Hi > Dn
  29. * => case 5: Hi > Di
  30. * => case 8: Hi <> Do
  31. * if undefined usbtest 13 fails
  32. * - TRACE: enable function tracing (depends on DEBUG)
  33. *
  34. * Main Features
  35. * - Chapter 9 & Mass Storage Compliance with Gadget File Storage
  36. * - Chapter 9 Compliance with Gadget Zero (STALL_IN undefined)
  37. * - Normal & LPM support
  38. *
  39. * USBTEST Report
  40. * - OK: 0-12, 13 (STALL_IN defined) & 14
  41. * - Not Supported: 15 & 16 (ISO)
  42. *
  43. * TODO List
  44. * - OTG
  45. * - Isochronous & Interrupt Traffic
  46. * - Handle requests which spawns into several TDs
  47. * - GET_STATUS(device) - always reports 0
  48. * - Gadget API (majority of optional features)
  49. * - Suspend & Remote Wakeup
  50. */
  51. #include <linux/delay.h>
  52. #include <linux/device.h>
  53. #include <linux/dma-mapping.h>
  54. #include <linux/platform_device.h>
  55. #include <linux/module.h>
  56. #include <linux/idr.h>
  57. #include <linux/interrupt.h>
  58. #include <linux/io.h>
  59. #include <linux/kernel.h>
  60. #include <linux/slab.h>
  61. #include <linux/pm_runtime.h>
  62. #include <linux/usb/ch9.h>
  63. #include <linux/usb/gadget.h>
  64. #include <linux/usb/otg.h>
  65. #include <linux/usb/chipidea.h>
  66. #include "ci.h"
  67. #include "udc.h"
  68. #include "bits.h"
  69. #include "host.h"
  70. #include "debug.h"
  71. /* Controller register map */
  72. static uintptr_t ci_regs_nolpm[] = {
  73. [CAP_CAPLENGTH] = 0x000UL,
  74. [CAP_HCCPARAMS] = 0x008UL,
  75. [CAP_DCCPARAMS] = 0x024UL,
  76. [CAP_TESTMODE] = 0x038UL,
  77. [OP_USBCMD] = 0x000UL,
  78. [OP_USBSTS] = 0x004UL,
  79. [OP_USBINTR] = 0x008UL,
  80. [OP_DEVICEADDR] = 0x014UL,
  81. [OP_ENDPTLISTADDR] = 0x018UL,
  82. [OP_PORTSC] = 0x044UL,
  83. [OP_DEVLC] = 0x084UL,
  84. [OP_OTGSC] = 0x064UL,
  85. [OP_USBMODE] = 0x068UL,
  86. [OP_ENDPTSETUPSTAT] = 0x06CUL,
  87. [OP_ENDPTPRIME] = 0x070UL,
  88. [OP_ENDPTFLUSH] = 0x074UL,
  89. [OP_ENDPTSTAT] = 0x078UL,
  90. [OP_ENDPTCOMPLETE] = 0x07CUL,
  91. [OP_ENDPTCTRL] = 0x080UL,
  92. };
  93. static uintptr_t ci_regs_lpm[] = {
  94. [CAP_CAPLENGTH] = 0x000UL,
  95. [CAP_HCCPARAMS] = 0x008UL,
  96. [CAP_DCCPARAMS] = 0x024UL,
  97. [CAP_TESTMODE] = 0x0FCUL,
  98. [OP_USBCMD] = 0x000UL,
  99. [OP_USBSTS] = 0x004UL,
  100. [OP_USBINTR] = 0x008UL,
  101. [OP_DEVICEADDR] = 0x014UL,
  102. [OP_ENDPTLISTADDR] = 0x018UL,
  103. [OP_PORTSC] = 0x044UL,
  104. [OP_DEVLC] = 0x084UL,
  105. [OP_OTGSC] = 0x0C4UL,
  106. [OP_USBMODE] = 0x0C8UL,
  107. [OP_ENDPTSETUPSTAT] = 0x0D8UL,
  108. [OP_ENDPTPRIME] = 0x0DCUL,
  109. [OP_ENDPTFLUSH] = 0x0E0UL,
  110. [OP_ENDPTSTAT] = 0x0E4UL,
  111. [OP_ENDPTCOMPLETE] = 0x0E8UL,
  112. [OP_ENDPTCTRL] = 0x0ECUL,
  113. };
  114. static int hw_alloc_regmap(struct ci13xxx *ci, bool is_lpm)
  115. {
  116. int i;
  117. kfree(ci->hw_bank.regmap);
  118. ci->hw_bank.regmap = kzalloc((OP_LAST + 1) * sizeof(void *),
  119. GFP_KERNEL);
  120. if (!ci->hw_bank.regmap)
  121. return -ENOMEM;
  122. for (i = 0; i < OP_ENDPTCTRL; i++)
  123. ci->hw_bank.regmap[i] =
  124. (i <= CAP_LAST ? ci->hw_bank.cap : ci->hw_bank.op) +
  125. (is_lpm ? ci_regs_lpm[i] : ci_regs_nolpm[i]);
  126. for (; i <= OP_LAST; i++)
  127. ci->hw_bank.regmap[i] = ci->hw_bank.op +
  128. 4 * (i - OP_ENDPTCTRL) +
  129. (is_lpm
  130. ? ci_regs_lpm[OP_ENDPTCTRL]
  131. : ci_regs_nolpm[OP_ENDPTCTRL]);
  132. return 0;
  133. }
  134. /**
  135. * hw_port_test_set: writes port test mode (execute without interruption)
  136. * @mode: new value
  137. *
  138. * This function returns an error code
  139. */
  140. int hw_port_test_set(struct ci13xxx *ci, u8 mode)
  141. {
  142. const u8 TEST_MODE_MAX = 7;
  143. if (mode > TEST_MODE_MAX)
  144. return -EINVAL;
  145. hw_write(ci, OP_PORTSC, PORTSC_PTC, mode << ffs_nr(PORTSC_PTC));
  146. return 0;
  147. }
  148. /**
  149. * hw_port_test_get: reads port test mode value
  150. *
  151. * This function returns port test mode value
  152. */
  153. u8 hw_port_test_get(struct ci13xxx *ci)
  154. {
  155. return hw_read(ci, OP_PORTSC, PORTSC_PTC) >> ffs_nr(PORTSC_PTC);
  156. }
  157. static int hw_device_init(struct ci13xxx *ci, void __iomem *base)
  158. {
  159. u32 reg;
  160. /* bank is a module variable */
  161. ci->hw_bank.abs = base;
  162. ci->hw_bank.cap = ci->hw_bank.abs;
  163. ci->hw_bank.cap += ci->platdata->capoffset;
  164. ci->hw_bank.op = ci->hw_bank.cap + ioread8(ci->hw_bank.cap);
  165. hw_alloc_regmap(ci, false);
  166. reg = hw_read(ci, CAP_HCCPARAMS, HCCPARAMS_LEN) >>
  167. ffs_nr(HCCPARAMS_LEN);
  168. ci->hw_bank.lpm = reg;
  169. hw_alloc_regmap(ci, !!reg);
  170. ci->hw_bank.size = ci->hw_bank.op - ci->hw_bank.abs;
  171. ci->hw_bank.size += OP_LAST;
  172. ci->hw_bank.size /= sizeof(u32);
  173. reg = hw_read(ci, CAP_DCCPARAMS, DCCPARAMS_DEN) >>
  174. ffs_nr(DCCPARAMS_DEN);
  175. ci->hw_ep_max = reg * 2; /* cache hw ENDPT_MAX */
  176. if (ci->hw_ep_max > ENDPT_MAX)
  177. return -ENODEV;
  178. dev_dbg(ci->dev, "ChipIdea HDRC found, lpm: %d; cap: %p op: %p\n",
  179. ci->hw_bank.lpm, ci->hw_bank.cap, ci->hw_bank.op);
  180. /* setup lock mode ? */
  181. /* ENDPTSETUPSTAT is '0' by default */
  182. /* HCSPARAMS.bf.ppc SHOULD BE zero for device */
  183. return 0;
  184. }
  185. /**
  186. * hw_device_reset: resets chip (execute without interruption)
  187. * @ci: the controller
  188. *
  189. * This function returns an error code
  190. */
  191. int hw_device_reset(struct ci13xxx *ci, u32 mode)
  192. {
  193. /* should flush & stop before reset */
  194. hw_write(ci, OP_ENDPTFLUSH, ~0, ~0);
  195. hw_write(ci, OP_USBCMD, USBCMD_RS, 0);
  196. hw_write(ci, OP_USBCMD, USBCMD_RST, USBCMD_RST);
  197. while (hw_read(ci, OP_USBCMD, USBCMD_RST))
  198. udelay(10); /* not RTOS friendly */
  199. if (ci->platdata->notify_event)
  200. ci->platdata->notify_event(ci,
  201. CI13XXX_CONTROLLER_RESET_EVENT);
  202. if (ci->platdata->flags & CI13XXX_DISABLE_STREAMING)
  203. hw_write(ci, OP_USBMODE, USBMODE_CI_SDIS, USBMODE_CI_SDIS);
  204. /* USBMODE should be configured step by step */
  205. hw_write(ci, OP_USBMODE, USBMODE_CM, USBMODE_CM_IDLE);
  206. hw_write(ci, OP_USBMODE, USBMODE_CM, mode);
  207. /* HW >= 2.3 */
  208. hw_write(ci, OP_USBMODE, USBMODE_SLOM, USBMODE_SLOM);
  209. if (hw_read(ci, OP_USBMODE, USBMODE_CM) != mode) {
  210. pr_err("cannot enter in %s mode", ci_role(ci)->name);
  211. pr_err("lpm = %i", ci->hw_bank.lpm);
  212. return -ENODEV;
  213. }
  214. return 0;
  215. }
  216. /**
  217. * ci_otg_role - pick role based on ID pin state
  218. * @ci: the controller
  219. */
  220. static enum ci_role ci_otg_role(struct ci13xxx *ci)
  221. {
  222. u32 sts = hw_read(ci, OP_OTGSC, ~0);
  223. enum ci_role role = sts & OTGSC_ID
  224. ? CI_ROLE_GADGET
  225. : CI_ROLE_HOST;
  226. return role;
  227. }
  228. /**
  229. * ci_role_work - perform role changing based on ID pin
  230. * @work: work struct
  231. */
  232. static void ci_role_work(struct work_struct *work)
  233. {
  234. struct ci13xxx *ci = container_of(work, struct ci13xxx, work);
  235. enum ci_role role = ci_otg_role(ci);
  236. if (role != ci->role) {
  237. dev_dbg(ci->dev, "switching from %s to %s\n",
  238. ci_role(ci)->name, ci->roles[role]->name);
  239. ci_role_stop(ci);
  240. ci_role_start(ci, role);
  241. enable_irq(ci->irq);
  242. }
  243. }
  244. static ssize_t show_role(struct device *dev, struct device_attribute *attr,
  245. char *buf)
  246. {
  247. struct ci13xxx *ci = dev_get_drvdata(dev);
  248. return sprintf(buf, "%s\n", ci_role(ci)->name);
  249. }
  250. static ssize_t store_role(struct device *dev, struct device_attribute *attr,
  251. const char *buf, size_t count)
  252. {
  253. struct ci13xxx *ci = dev_get_drvdata(dev);
  254. enum ci_role role;
  255. int ret;
  256. for (role = CI_ROLE_HOST; role < CI_ROLE_END; role++)
  257. if (ci->roles[role] && !strcmp(buf, ci->roles[role]->name))
  258. break;
  259. if (role == CI_ROLE_END || role == ci->role)
  260. return -EINVAL;
  261. ci_role_stop(ci);
  262. ret = ci_role_start(ci, role);
  263. if (ret)
  264. return ret;
  265. return count;
  266. }
  267. static DEVICE_ATTR(role, S_IRUSR | S_IWUSR, show_role, store_role);
  268. static irqreturn_t ci_irq(int irq, void *data)
  269. {
  270. struct ci13xxx *ci = data;
  271. irqreturn_t ret = IRQ_NONE;
  272. u32 otgsc = 0;
  273. if (ci->is_otg)
  274. otgsc = hw_read(ci, OP_OTGSC, ~0);
  275. if (ci->role != CI_ROLE_END)
  276. ret = ci_role(ci)->irq(ci);
  277. if (ci->is_otg && (otgsc & OTGSC_IDIS)) {
  278. hw_write(ci, OP_OTGSC, OTGSC_IDIS, OTGSC_IDIS);
  279. disable_irq_nosync(ci->irq);
  280. queue_work(ci->wq, &ci->work);
  281. ret = IRQ_HANDLED;
  282. }
  283. return ret;
  284. }
  285. static DEFINE_IDA(ci_ida);
  286. struct platform_device *ci13xxx_add_device(struct device *dev,
  287. struct resource *res, int nres,
  288. struct ci13xxx_platform_data *platdata)
  289. {
  290. struct platform_device *pdev;
  291. int id, ret;
  292. id = ida_simple_get(&ci_ida, 0, 0, GFP_KERNEL);
  293. if (id < 0)
  294. return ERR_PTR(id);
  295. pdev = platform_device_alloc("ci_hdrc", id);
  296. if (!pdev) {
  297. ret = -ENOMEM;
  298. goto put_id;
  299. }
  300. pdev->dev.parent = dev;
  301. pdev->dev.dma_mask = dev->dma_mask;
  302. pdev->dev.dma_parms = dev->dma_parms;
  303. dma_set_coherent_mask(&pdev->dev, dev->coherent_dma_mask);
  304. ret = platform_device_add_resources(pdev, res, nres);
  305. if (ret)
  306. goto err;
  307. ret = platform_device_add_data(pdev, platdata, sizeof(*platdata));
  308. if (ret)
  309. goto err;
  310. ret = platform_device_add(pdev);
  311. if (ret)
  312. goto err;
  313. return pdev;
  314. err:
  315. platform_device_put(pdev);
  316. put_id:
  317. ida_simple_remove(&ci_ida, id);
  318. return ERR_PTR(ret);
  319. }
  320. EXPORT_SYMBOL_GPL(ci13xxx_add_device);
  321. void ci13xxx_remove_device(struct platform_device *pdev)
  322. {
  323. int id = pdev->id;
  324. platform_device_unregister(pdev);
  325. ida_simple_remove(&ci_ida, id);
  326. }
  327. EXPORT_SYMBOL_GPL(ci13xxx_remove_device);
  328. static int ci_hdrc_probe(struct platform_device *pdev)
  329. {
  330. struct device *dev = &pdev->dev;
  331. struct ci13xxx *ci;
  332. struct resource *res;
  333. void __iomem *base;
  334. int ret;
  335. if (!dev->platform_data) {
  336. dev_err(dev, "platform data missing\n");
  337. return -ENODEV;
  338. }
  339. res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
  340. if (!res) {
  341. dev_err(dev, "missing resource\n");
  342. return -ENODEV;
  343. }
  344. base = devm_request_and_ioremap(dev, res);
  345. if (!base) {
  346. dev_err(dev, "can't request and ioremap resource\n");
  347. return -ENOMEM;
  348. }
  349. ci = devm_kzalloc(dev, sizeof(*ci), GFP_KERNEL);
  350. if (!ci) {
  351. dev_err(dev, "can't allocate device\n");
  352. return -ENOMEM;
  353. }
  354. ci->dev = dev;
  355. ci->platdata = dev->platform_data;
  356. if (ci->platdata->phy)
  357. ci->transceiver = ci->platdata->phy;
  358. else
  359. ci->global_phy = true;
  360. ret = hw_device_init(ci, base);
  361. if (ret < 0) {
  362. dev_err(dev, "can't initialize hardware\n");
  363. return -ENODEV;
  364. }
  365. ci->hw_bank.phys = res->start;
  366. ci->irq = platform_get_irq(pdev, 0);
  367. if (ci->irq < 0) {
  368. dev_err(dev, "missing IRQ\n");
  369. return -ENODEV;
  370. }
  371. INIT_WORK(&ci->work, ci_role_work);
  372. ci->wq = create_singlethread_workqueue("ci_otg");
  373. if (!ci->wq) {
  374. dev_err(dev, "can't create workqueue\n");
  375. return -ENODEV;
  376. }
  377. /* initialize role(s) before the interrupt is requested */
  378. ret = ci_hdrc_host_init(ci);
  379. if (ret)
  380. dev_info(dev, "doesn't support host\n");
  381. ret = ci_hdrc_gadget_init(ci);
  382. if (ret)
  383. dev_info(dev, "doesn't support gadget\n");
  384. if (!ci->roles[CI_ROLE_HOST] && !ci->roles[CI_ROLE_GADGET]) {
  385. dev_err(dev, "no supported roles\n");
  386. ret = -ENODEV;
  387. goto rm_wq;
  388. }
  389. if (ci->roles[CI_ROLE_HOST] && ci->roles[CI_ROLE_GADGET]) {
  390. ci->is_otg = true;
  391. /* ID pin needs 1ms debouce time, we delay 2ms for safe */
  392. mdelay(2);
  393. ci->role = ci_otg_role(ci);
  394. } else {
  395. ci->role = ci->roles[CI_ROLE_HOST]
  396. ? CI_ROLE_HOST
  397. : CI_ROLE_GADGET;
  398. }
  399. ret = ci_role_start(ci, ci->role);
  400. if (ret) {
  401. dev_err(dev, "can't start %s role\n", ci_role(ci)->name);
  402. ret = -ENODEV;
  403. goto rm_wq;
  404. }
  405. platform_set_drvdata(pdev, ci);
  406. ret = request_irq(ci->irq, ci_irq, IRQF_SHARED, ci->platdata->name,
  407. ci);
  408. if (ret)
  409. goto stop;
  410. ret = device_create_file(dev, &dev_attr_role);
  411. if (ret)
  412. goto rm_attr;
  413. if (ci->is_otg)
  414. hw_write(ci, OP_OTGSC, OTGSC_IDIE, OTGSC_IDIE);
  415. return ret;
  416. rm_attr:
  417. device_remove_file(dev, &dev_attr_role);
  418. stop:
  419. ci_role_stop(ci);
  420. rm_wq:
  421. flush_workqueue(ci->wq);
  422. destroy_workqueue(ci->wq);
  423. return ret;
  424. }
  425. static int ci_hdrc_remove(struct platform_device *pdev)
  426. {
  427. struct ci13xxx *ci = platform_get_drvdata(pdev);
  428. flush_workqueue(ci->wq);
  429. destroy_workqueue(ci->wq);
  430. device_remove_file(ci->dev, &dev_attr_role);
  431. free_irq(ci->irq, ci);
  432. ci_role_stop(ci);
  433. return 0;
  434. }
  435. static struct platform_driver ci_hdrc_driver = {
  436. .probe = ci_hdrc_probe,
  437. .remove = ci_hdrc_remove,
  438. .driver = {
  439. .name = "ci_hdrc",
  440. },
  441. };
  442. module_platform_driver(ci_hdrc_driver);
  443. MODULE_ALIAS("platform:ci_hdrc");
  444. MODULE_ALIAS("platform:ci13xxx");
  445. MODULE_LICENSE("GPL v2");
  446. MODULE_AUTHOR("David Lopo <dlopo@chipidea.mips.com>");
  447. MODULE_DESCRIPTION("ChipIdea HDRC Driver");