ipr.h 35 KB

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  1. /*
  2. * ipr.h -- driver for IBM Power Linux RAID adapters
  3. *
  4. * Written By: Brian King <brking@us.ibm.com>, IBM Corporation
  5. *
  6. * Copyright (C) 2003, 2004 IBM Corporation
  7. *
  8. * This program is free software; you can redistribute it and/or modify
  9. * it under the terms of the GNU General Public License as published by
  10. * the Free Software Foundation; either version 2 of the License, or
  11. * (at your option) any later version.
  12. *
  13. * This program is distributed in the hope that it will be useful,
  14. * but WITHOUT ANY WARRANTY; without even the implied warranty of
  15. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  16. * GNU General Public License for more details.
  17. *
  18. * You should have received a copy of the GNU General Public License
  19. * along with this program; if not, write to the Free Software
  20. * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
  21. *
  22. * Alan Cox <alan@redhat.com> - Removed several careless u32/dma_addr_t errors
  23. * that broke 64bit platforms.
  24. */
  25. #ifndef _IPR_H
  26. #define _IPR_H
  27. #include <linux/types.h>
  28. #include <linux/completion.h>
  29. #include <linux/list.h>
  30. #include <linux/kref.h>
  31. #include <scsi/scsi.h>
  32. #include <scsi/scsi_cmnd.h>
  33. /*
  34. * Literals
  35. */
  36. #define IPR_DRIVER_VERSION "2.1.3"
  37. #define IPR_DRIVER_DATE "(March 29, 2006)"
  38. /*
  39. * IPR_MAX_CMD_PER_LUN: This defines the maximum number of outstanding
  40. * ops per device for devices not running tagged command queuing.
  41. * This can be adjusted at runtime through sysfs device attributes.
  42. */
  43. #define IPR_MAX_CMD_PER_LUN 6
  44. /*
  45. * IPR_NUM_BASE_CMD_BLKS: This defines the maximum number of
  46. * ops the mid-layer can send to the adapter.
  47. */
  48. #define IPR_NUM_BASE_CMD_BLKS 100
  49. #define IPR_SUBS_DEV_ID_2780 0x0264
  50. #define IPR_SUBS_DEV_ID_5702 0x0266
  51. #define IPR_SUBS_DEV_ID_5703 0x0278
  52. #define IPR_SUBS_DEV_ID_572E 0x028D
  53. #define IPR_SUBS_DEV_ID_573E 0x02D3
  54. #define IPR_SUBS_DEV_ID_573D 0x02D4
  55. #define IPR_SUBS_DEV_ID_571A 0x02C0
  56. #define IPR_SUBS_DEV_ID_571B 0x02BE
  57. #define IPR_SUBS_DEV_ID_571E 0x02BF
  58. #define IPR_SUBS_DEV_ID_571F 0x02D5
  59. #define IPR_SUBS_DEV_ID_572A 0x02C1
  60. #define IPR_SUBS_DEV_ID_572B 0x02C2
  61. #define IPR_SUBS_DEV_ID_575B 0x030D
  62. #define IPR_NAME "ipr"
  63. /*
  64. * Return codes
  65. */
  66. #define IPR_RC_JOB_CONTINUE 1
  67. #define IPR_RC_JOB_RETURN 2
  68. /*
  69. * IOASCs
  70. */
  71. #define IPR_IOASC_NR_INIT_CMD_REQUIRED 0x02040200
  72. #define IPR_IOASC_SYNC_REQUIRED 0x023f0000
  73. #define IPR_IOASC_MED_DO_NOT_REALLOC 0x03110C00
  74. #define IPR_IOASC_HW_SEL_TIMEOUT 0x04050000
  75. #define IPR_IOASC_HW_DEV_BUS_STATUS 0x04448500
  76. #define IPR_IOASC_IOASC_MASK 0xFFFFFF00
  77. #define IPR_IOASC_SCSI_STATUS_MASK 0x000000FF
  78. #define IPR_IOASC_IR_INVALID_REQ_TYPE_OR_PKT 0x05240000
  79. #define IPR_IOASC_IR_RESOURCE_HANDLE 0x05250000
  80. #define IPR_IOASC_IR_NO_CMDS_TO_2ND_IOA 0x05258100
  81. #define IPR_IOASA_IR_DUAL_IOA_DISABLED 0x052C8000
  82. #define IPR_IOASC_BUS_WAS_RESET 0x06290000
  83. #define IPR_IOASC_BUS_WAS_RESET_BY_OTHER 0x06298000
  84. #define IPR_IOASC_ABORTED_CMD_TERM_BY_HOST 0x0B5A0000
  85. #define IPR_FIRST_DRIVER_IOASC 0x10000000
  86. #define IPR_IOASC_IOA_WAS_RESET 0x10000001
  87. #define IPR_IOASC_PCI_ACCESS_ERROR 0x10000002
  88. #define IPR_NUM_LOG_HCAMS 2
  89. #define IPR_NUM_CFG_CHG_HCAMS 2
  90. #define IPR_NUM_HCAMS (IPR_NUM_LOG_HCAMS + IPR_NUM_CFG_CHG_HCAMS)
  91. #define IPR_MAX_NUM_TARGETS_PER_BUS 256
  92. #define IPR_MAX_NUM_LUNS_PER_TARGET 256
  93. #define IPR_MAX_NUM_VSET_LUNS_PER_TARGET 8
  94. #define IPR_VSET_BUS 0xff
  95. #define IPR_IOA_BUS 0xff
  96. #define IPR_IOA_TARGET 0xff
  97. #define IPR_IOA_LUN 0xff
  98. #define IPR_MAX_NUM_BUSES 8
  99. #define IPR_MAX_BUS_TO_SCAN IPR_MAX_NUM_BUSES
  100. #define IPR_NUM_RESET_RELOAD_RETRIES 3
  101. /* We need resources for HCAMS, IOA reset, IOA bringdown, and ERP */
  102. #define IPR_NUM_INTERNAL_CMD_BLKS (IPR_NUM_HCAMS + \
  103. ((IPR_NUM_RESET_RELOAD_RETRIES + 1) * 2) + 3)
  104. #define IPR_MAX_COMMANDS IPR_NUM_BASE_CMD_BLKS
  105. #define IPR_NUM_CMD_BLKS (IPR_NUM_BASE_CMD_BLKS + \
  106. IPR_NUM_INTERNAL_CMD_BLKS)
  107. #define IPR_MAX_PHYSICAL_DEVS 192
  108. #define IPR_MAX_SGLIST 64
  109. #define IPR_IOA_MAX_SECTORS 32767
  110. #define IPR_VSET_MAX_SECTORS 512
  111. #define IPR_MAX_CDB_LEN 16
  112. #define IPR_DEFAULT_BUS_WIDTH 16
  113. #define IPR_80MBs_SCSI_RATE ((80 * 10) / (IPR_DEFAULT_BUS_WIDTH / 8))
  114. #define IPR_U160_SCSI_RATE ((160 * 10) / (IPR_DEFAULT_BUS_WIDTH / 8))
  115. #define IPR_U320_SCSI_RATE ((320 * 10) / (IPR_DEFAULT_BUS_WIDTH / 8))
  116. #define IPR_MAX_SCSI_RATE(width) ((320 * 10) / ((width) / 8))
  117. #define IPR_IOA_RES_HANDLE 0xffffffff
  118. #define IPR_INVALID_RES_HANDLE 0
  119. #define IPR_IOA_RES_ADDR 0x00ffffff
  120. /*
  121. * Adapter Commands
  122. */
  123. #define IPR_QUERY_RSRC_STATE 0xC2
  124. #define IPR_RESET_DEVICE 0xC3
  125. #define IPR_RESET_TYPE_SELECT 0x80
  126. #define IPR_LUN_RESET 0x40
  127. #define IPR_TARGET_RESET 0x20
  128. #define IPR_BUS_RESET 0x10
  129. #define IPR_ID_HOST_RR_Q 0xC4
  130. #define IPR_QUERY_IOA_CONFIG 0xC5
  131. #define IPR_CANCEL_ALL_REQUESTS 0xCE
  132. #define IPR_HOST_CONTROLLED_ASYNC 0xCF
  133. #define IPR_HCAM_CDB_OP_CODE_CONFIG_CHANGE 0x01
  134. #define IPR_HCAM_CDB_OP_CODE_LOG_DATA 0x02
  135. #define IPR_SET_SUPPORTED_DEVICES 0xFB
  136. #define IPR_IOA_SHUTDOWN 0xF7
  137. #define IPR_WR_BUF_DOWNLOAD_AND_SAVE 0x05
  138. /*
  139. * Timeouts
  140. */
  141. #define IPR_SHUTDOWN_TIMEOUT (ipr_fastfail ? 60 * HZ : 10 * 60 * HZ)
  142. #define IPR_VSET_RW_TIMEOUT (ipr_fastfail ? 30 * HZ : 2 * 60 * HZ)
  143. #define IPR_ABBREV_SHUTDOWN_TIMEOUT (10 * HZ)
  144. #define IPR_DEVICE_RESET_TIMEOUT (ipr_fastfail ? 10 * HZ : 30 * HZ)
  145. #define IPR_CANCEL_ALL_TIMEOUT (ipr_fastfail ? 10 * HZ : 30 * HZ)
  146. #define IPR_ABORT_TASK_TIMEOUT (ipr_fastfail ? 10 * HZ : 30 * HZ)
  147. #define IPR_INTERNAL_TIMEOUT (ipr_fastfail ? 10 * HZ : 30 * HZ)
  148. #define IPR_WRITE_BUFFER_TIMEOUT (10 * 60 * HZ)
  149. #define IPR_SET_SUP_DEVICE_TIMEOUT (2 * 60 * HZ)
  150. #define IPR_REQUEST_SENSE_TIMEOUT (10 * HZ)
  151. #define IPR_OPERATIONAL_TIMEOUT (5 * 60)
  152. #define IPR_WAIT_FOR_RESET_TIMEOUT (2 * HZ)
  153. #define IPR_CHECK_FOR_RESET_TIMEOUT (HZ / 10)
  154. #define IPR_WAIT_FOR_BIST_TIMEOUT (2 * HZ)
  155. #define IPR_DUMP_TIMEOUT (15 * HZ)
  156. /*
  157. * SCSI Literals
  158. */
  159. #define IPR_VENDOR_ID_LEN 8
  160. #define IPR_PROD_ID_LEN 16
  161. #define IPR_SERIAL_NUM_LEN 8
  162. /*
  163. * Hardware literals
  164. */
  165. #define IPR_FMT2_MBX_ADDR_MASK 0x0fffffff
  166. #define IPR_FMT2_MBX_BAR_SEL_MASK 0xf0000000
  167. #define IPR_FMT2_MKR_BAR_SEL_SHIFT 28
  168. #define IPR_GET_FMT2_BAR_SEL(mbx) \
  169. (((mbx) & IPR_FMT2_MBX_BAR_SEL_MASK) >> IPR_FMT2_MKR_BAR_SEL_SHIFT)
  170. #define IPR_SDT_FMT2_BAR0_SEL 0x0
  171. #define IPR_SDT_FMT2_BAR1_SEL 0x1
  172. #define IPR_SDT_FMT2_BAR2_SEL 0x2
  173. #define IPR_SDT_FMT2_BAR3_SEL 0x3
  174. #define IPR_SDT_FMT2_BAR4_SEL 0x4
  175. #define IPR_SDT_FMT2_BAR5_SEL 0x5
  176. #define IPR_SDT_FMT2_EXP_ROM_SEL 0x8
  177. #define IPR_FMT2_SDT_READY_TO_USE 0xC4D4E3F2
  178. #define IPR_DOORBELL 0x82800000
  179. #define IPR_RUNTIME_RESET 0x40000000
  180. #define IPR_PCII_IOA_TRANS_TO_OPER (0x80000000 >> 0)
  181. #define IPR_PCII_IOARCB_XFER_FAILED (0x80000000 >> 3)
  182. #define IPR_PCII_IOA_UNIT_CHECKED (0x80000000 >> 4)
  183. #define IPR_PCII_NO_HOST_RRQ (0x80000000 >> 5)
  184. #define IPR_PCII_CRITICAL_OPERATION (0x80000000 >> 6)
  185. #define IPR_PCII_IO_DEBUG_ACKNOWLEDGE (0x80000000 >> 7)
  186. #define IPR_PCII_IOARRIN_LOST (0x80000000 >> 27)
  187. #define IPR_PCII_MMIO_ERROR (0x80000000 >> 28)
  188. #define IPR_PCII_PROC_ERR_STATE (0x80000000 >> 29)
  189. #define IPR_PCII_HRRQ_UPDATED (0x80000000 >> 30)
  190. #define IPR_PCII_CORE_ISSUED_RST_REQ (0x80000000 >> 31)
  191. #define IPR_PCII_ERROR_INTERRUPTS \
  192. (IPR_PCII_IOARCB_XFER_FAILED | IPR_PCII_IOA_UNIT_CHECKED | \
  193. IPR_PCII_NO_HOST_RRQ | IPR_PCII_IOARRIN_LOST | IPR_PCII_MMIO_ERROR)
  194. #define IPR_PCII_OPER_INTERRUPTS \
  195. (IPR_PCII_ERROR_INTERRUPTS | IPR_PCII_HRRQ_UPDATED | IPR_PCII_IOA_TRANS_TO_OPER)
  196. #define IPR_UPROCI_RESET_ALERT (0x80000000 >> 7)
  197. #define IPR_UPROCI_IO_DEBUG_ALERT (0x80000000 >> 9)
  198. #define IPR_LDUMP_MAX_LONG_ACK_DELAY_IN_USEC 200000 /* 200 ms */
  199. #define IPR_LDUMP_MAX_SHORT_ACK_DELAY_IN_USEC 200000 /* 200 ms */
  200. /*
  201. * Dump literals
  202. */
  203. #define IPR_MAX_IOA_DUMP_SIZE (4 * 1024 * 1024)
  204. #define IPR_NUM_SDT_ENTRIES 511
  205. #define IPR_MAX_NUM_DUMP_PAGES ((IPR_MAX_IOA_DUMP_SIZE / PAGE_SIZE) + 1)
  206. /*
  207. * Misc literals
  208. */
  209. #define IPR_NUM_IOADL_ENTRIES IPR_MAX_SGLIST
  210. /*
  211. * Adapter interface types
  212. */
  213. struct ipr_res_addr {
  214. u8 reserved;
  215. u8 bus;
  216. u8 target;
  217. u8 lun;
  218. #define IPR_GET_PHYS_LOC(res_addr) \
  219. (((res_addr).bus << 16) | ((res_addr).target << 8) | (res_addr).lun)
  220. }__attribute__((packed, aligned (4)));
  221. struct ipr_std_inq_vpids {
  222. u8 vendor_id[IPR_VENDOR_ID_LEN];
  223. u8 product_id[IPR_PROD_ID_LEN];
  224. }__attribute__((packed));
  225. struct ipr_vpd {
  226. struct ipr_std_inq_vpids vpids;
  227. u8 sn[IPR_SERIAL_NUM_LEN];
  228. }__attribute__((packed));
  229. struct ipr_ext_vpd {
  230. struct ipr_vpd vpd;
  231. __be32 wwid[2];
  232. }__attribute__((packed));
  233. struct ipr_std_inq_data {
  234. u8 peri_qual_dev_type;
  235. #define IPR_STD_INQ_PERI_QUAL(peri) ((peri) >> 5)
  236. #define IPR_STD_INQ_PERI_DEV_TYPE(peri) ((peri) & 0x1F)
  237. u8 removeable_medium_rsvd;
  238. #define IPR_STD_INQ_REMOVEABLE_MEDIUM 0x80
  239. #define IPR_IS_DASD_DEVICE(std_inq) \
  240. ((IPR_STD_INQ_PERI_DEV_TYPE((std_inq).peri_qual_dev_type) == TYPE_DISK) && \
  241. !(((std_inq).removeable_medium_rsvd) & IPR_STD_INQ_REMOVEABLE_MEDIUM))
  242. #define IPR_IS_SES_DEVICE(std_inq) \
  243. (IPR_STD_INQ_PERI_DEV_TYPE((std_inq).peri_qual_dev_type) == TYPE_ENCLOSURE)
  244. u8 version;
  245. u8 aen_naca_fmt;
  246. u8 additional_len;
  247. u8 sccs_rsvd;
  248. u8 bq_enc_multi;
  249. u8 sync_cmdq_flags;
  250. struct ipr_std_inq_vpids vpids;
  251. u8 ros_rsvd_ram_rsvd[4];
  252. u8 serial_num[IPR_SERIAL_NUM_LEN];
  253. }__attribute__ ((packed));
  254. struct ipr_config_table_entry {
  255. u8 service_level;
  256. u8 array_id;
  257. u8 flags;
  258. #define IPR_IS_IOA_RESOURCE 0x80
  259. #define IPR_IS_ARRAY_MEMBER 0x20
  260. #define IPR_IS_HOT_SPARE 0x10
  261. u8 rsvd_subtype;
  262. #define IPR_RES_SUBTYPE(res) (((res)->cfgte.rsvd_subtype) & 0x0f)
  263. #define IPR_SUBTYPE_AF_DASD 0
  264. #define IPR_SUBTYPE_GENERIC_SCSI 1
  265. #define IPR_SUBTYPE_VOLUME_SET 2
  266. #define IPR_QUEUEING_MODEL(res) ((((res)->cfgte.flags) & 0x70) >> 4)
  267. #define IPR_QUEUE_FROZEN_MODEL 0
  268. #define IPR_QUEUE_NACA_MODEL 1
  269. struct ipr_res_addr res_addr;
  270. __be32 res_handle;
  271. __be32 reserved4[2];
  272. struct ipr_std_inq_data std_inq_data;
  273. }__attribute__ ((packed, aligned (4)));
  274. struct ipr_config_table_hdr {
  275. u8 num_entries;
  276. u8 flags;
  277. #define IPR_UCODE_DOWNLOAD_REQ 0x10
  278. __be16 reserved;
  279. }__attribute__((packed, aligned (4)));
  280. struct ipr_config_table {
  281. struct ipr_config_table_hdr hdr;
  282. struct ipr_config_table_entry dev[IPR_MAX_PHYSICAL_DEVS];
  283. }__attribute__((packed, aligned (4)));
  284. struct ipr_hostrcb_cfg_ch_not {
  285. struct ipr_config_table_entry cfgte;
  286. u8 reserved[936];
  287. }__attribute__((packed, aligned (4)));
  288. struct ipr_supported_device {
  289. __be16 data_length;
  290. u8 reserved;
  291. u8 num_records;
  292. struct ipr_std_inq_vpids vpids;
  293. u8 reserved2[16];
  294. }__attribute__((packed, aligned (4)));
  295. /* Command packet structure */
  296. struct ipr_cmd_pkt {
  297. __be16 reserved; /* Reserved by IOA */
  298. u8 request_type;
  299. #define IPR_RQTYPE_SCSICDB 0x00
  300. #define IPR_RQTYPE_IOACMD 0x01
  301. #define IPR_RQTYPE_HCAM 0x02
  302. u8 luntar_luntrn;
  303. u8 flags_hi;
  304. #define IPR_FLAGS_HI_WRITE_NOT_READ 0x80
  305. #define IPR_FLAGS_HI_NO_ULEN_CHK 0x20
  306. #define IPR_FLAGS_HI_SYNC_OVERRIDE 0x10
  307. #define IPR_FLAGS_HI_SYNC_COMPLETE 0x08
  308. #define IPR_FLAGS_HI_NO_LINK_DESC 0x04
  309. u8 flags_lo;
  310. #define IPR_FLAGS_LO_ALIGNED_BFR 0x20
  311. #define IPR_FLAGS_LO_DELAY_AFTER_RST 0x10
  312. #define IPR_FLAGS_LO_UNTAGGED_TASK 0x00
  313. #define IPR_FLAGS_LO_SIMPLE_TASK 0x02
  314. #define IPR_FLAGS_LO_ORDERED_TASK 0x04
  315. #define IPR_FLAGS_LO_HEAD_OF_Q_TASK 0x06
  316. #define IPR_FLAGS_LO_ACA_TASK 0x08
  317. u8 cdb[16];
  318. __be16 timeout;
  319. }__attribute__ ((packed, aligned(4)));
  320. /* IOA Request Control Block 128 bytes */
  321. struct ipr_ioarcb {
  322. __be32 ioarcb_host_pci_addr;
  323. __be32 reserved;
  324. __be32 res_handle;
  325. __be32 host_response_handle;
  326. __be32 reserved1;
  327. __be32 reserved2;
  328. __be32 reserved3;
  329. __be32 write_data_transfer_length;
  330. __be32 read_data_transfer_length;
  331. __be32 write_ioadl_addr;
  332. __be32 write_ioadl_len;
  333. __be32 read_ioadl_addr;
  334. __be32 read_ioadl_len;
  335. __be32 ioasa_host_pci_addr;
  336. __be16 ioasa_len;
  337. __be16 reserved4;
  338. struct ipr_cmd_pkt cmd_pkt;
  339. __be32 add_cmd_parms_len;
  340. __be32 add_cmd_parms[10];
  341. }__attribute__((packed, aligned (4)));
  342. struct ipr_ioadl_desc {
  343. __be32 flags_and_data_len;
  344. #define IPR_IOADL_FLAGS_MASK 0xff000000
  345. #define IPR_IOADL_GET_FLAGS(x) (be32_to_cpu(x) & IPR_IOADL_FLAGS_MASK)
  346. #define IPR_IOADL_DATA_LEN_MASK 0x00ffffff
  347. #define IPR_IOADL_GET_DATA_LEN(x) (be32_to_cpu(x) & IPR_IOADL_DATA_LEN_MASK)
  348. #define IPR_IOADL_FLAGS_READ 0x48000000
  349. #define IPR_IOADL_FLAGS_READ_LAST 0x49000000
  350. #define IPR_IOADL_FLAGS_WRITE 0x68000000
  351. #define IPR_IOADL_FLAGS_WRITE_LAST 0x69000000
  352. #define IPR_IOADL_FLAGS_LAST 0x01000000
  353. __be32 address;
  354. }__attribute__((packed, aligned (8)));
  355. struct ipr_ioasa_vset {
  356. __be32 failing_lba_hi;
  357. __be32 failing_lba_lo;
  358. __be32 reserved;
  359. }__attribute__((packed, aligned (4)));
  360. struct ipr_ioasa_af_dasd {
  361. __be32 failing_lba;
  362. __be32 reserved[2];
  363. }__attribute__((packed, aligned (4)));
  364. struct ipr_ioasa_gpdd {
  365. u8 end_state;
  366. u8 bus_phase;
  367. __be16 reserved;
  368. __be32 ioa_data[2];
  369. }__attribute__((packed, aligned (4)));
  370. struct ipr_auto_sense {
  371. __be16 auto_sense_len;
  372. __be16 ioa_data_len;
  373. __be32 data[SCSI_SENSE_BUFFERSIZE/sizeof(__be32)];
  374. };
  375. struct ipr_ioasa {
  376. __be32 ioasc;
  377. #define IPR_IOASC_SENSE_KEY(ioasc) ((ioasc) >> 24)
  378. #define IPR_IOASC_SENSE_CODE(ioasc) (((ioasc) & 0x00ff0000) >> 16)
  379. #define IPR_IOASC_SENSE_QUAL(ioasc) (((ioasc) & 0x0000ff00) >> 8)
  380. #define IPR_IOASC_SENSE_STATUS(ioasc) ((ioasc) & 0x000000ff)
  381. __be16 ret_stat_len; /* Length of the returned IOASA */
  382. __be16 avail_stat_len; /* Total Length of status available. */
  383. __be32 residual_data_len; /* number of bytes in the host data */
  384. /* buffers that were not used by the IOARCB command. */
  385. __be32 ilid;
  386. #define IPR_NO_ILID 0
  387. #define IPR_DRIVER_ILID 0xffffffff
  388. __be32 fd_ioasc;
  389. __be32 fd_phys_locator;
  390. __be32 fd_res_handle;
  391. __be32 ioasc_specific; /* status code specific field */
  392. #define IPR_ADDITIONAL_STATUS_FMT 0x80000000
  393. #define IPR_AUTOSENSE_VALID 0x40000000
  394. #define IPR_IOASC_SPECIFIC_MASK 0x00ffffff
  395. #define IPR_FIELD_POINTER_VALID (0x80000000 >> 8)
  396. #define IPR_FIELD_POINTER_MASK 0x0000ffff
  397. union {
  398. struct ipr_ioasa_vset vset;
  399. struct ipr_ioasa_af_dasd dasd;
  400. struct ipr_ioasa_gpdd gpdd;
  401. } u;
  402. struct ipr_auto_sense auto_sense;
  403. }__attribute__((packed, aligned (4)));
  404. struct ipr_mode_parm_hdr {
  405. u8 length;
  406. u8 medium_type;
  407. u8 device_spec_parms;
  408. u8 block_desc_len;
  409. }__attribute__((packed));
  410. struct ipr_mode_pages {
  411. struct ipr_mode_parm_hdr hdr;
  412. u8 data[255 - sizeof(struct ipr_mode_parm_hdr)];
  413. }__attribute__((packed));
  414. struct ipr_mode_page_hdr {
  415. u8 ps_page_code;
  416. #define IPR_MODE_PAGE_PS 0x80
  417. #define IPR_GET_MODE_PAGE_CODE(hdr) ((hdr)->ps_page_code & 0x3F)
  418. u8 page_length;
  419. }__attribute__ ((packed));
  420. struct ipr_dev_bus_entry {
  421. struct ipr_res_addr res_addr;
  422. u8 flags;
  423. #define IPR_SCSI_ATTR_ENABLE_QAS 0x80
  424. #define IPR_SCSI_ATTR_DISABLE_QAS 0x40
  425. #define IPR_SCSI_ATTR_QAS_MASK 0xC0
  426. #define IPR_SCSI_ATTR_ENABLE_TM 0x20
  427. #define IPR_SCSI_ATTR_NO_TERM_PWR 0x10
  428. #define IPR_SCSI_ATTR_TM_SUPPORTED 0x08
  429. #define IPR_SCSI_ATTR_LVD_TO_SE_NOT_ALLOWED 0x04
  430. u8 scsi_id;
  431. u8 bus_width;
  432. u8 extended_reset_delay;
  433. #define IPR_EXTENDED_RESET_DELAY 7
  434. __be32 max_xfer_rate;
  435. u8 spinup_delay;
  436. u8 reserved3;
  437. __be16 reserved4;
  438. }__attribute__((packed, aligned (4)));
  439. struct ipr_mode_page28 {
  440. struct ipr_mode_page_hdr hdr;
  441. u8 num_entries;
  442. u8 entry_length;
  443. struct ipr_dev_bus_entry bus[0];
  444. }__attribute__((packed));
  445. struct ipr_ioa_vpd {
  446. struct ipr_std_inq_data std_inq_data;
  447. u8 ascii_part_num[12];
  448. u8 reserved[40];
  449. u8 ascii_plant_code[4];
  450. }__attribute__((packed));
  451. struct ipr_inquiry_page3 {
  452. u8 peri_qual_dev_type;
  453. u8 page_code;
  454. u8 reserved1;
  455. u8 page_length;
  456. u8 ascii_len;
  457. u8 reserved2[3];
  458. u8 load_id[4];
  459. u8 major_release;
  460. u8 card_type;
  461. u8 minor_release[2];
  462. u8 ptf_number[4];
  463. u8 patch_number[4];
  464. }__attribute__((packed));
  465. #define IPR_INQUIRY_PAGE0_ENTRIES 20
  466. struct ipr_inquiry_page0 {
  467. u8 peri_qual_dev_type;
  468. u8 page_code;
  469. u8 reserved1;
  470. u8 len;
  471. u8 page[IPR_INQUIRY_PAGE0_ENTRIES];
  472. }__attribute__((packed));
  473. struct ipr_hostrcb_device_data_entry {
  474. struct ipr_vpd vpd;
  475. struct ipr_res_addr dev_res_addr;
  476. struct ipr_vpd new_vpd;
  477. struct ipr_vpd ioa_last_with_dev_vpd;
  478. struct ipr_vpd cfc_last_with_dev_vpd;
  479. __be32 ioa_data[5];
  480. }__attribute__((packed, aligned (4)));
  481. struct ipr_hostrcb_device_data_entry_enhanced {
  482. struct ipr_ext_vpd vpd;
  483. u8 ccin[4];
  484. struct ipr_res_addr dev_res_addr;
  485. struct ipr_ext_vpd new_vpd;
  486. u8 new_ccin[4];
  487. struct ipr_ext_vpd ioa_last_with_dev_vpd;
  488. struct ipr_ext_vpd cfc_last_with_dev_vpd;
  489. }__attribute__((packed, aligned (4)));
  490. struct ipr_hostrcb_array_data_entry {
  491. struct ipr_vpd vpd;
  492. struct ipr_res_addr expected_dev_res_addr;
  493. struct ipr_res_addr dev_res_addr;
  494. }__attribute__((packed, aligned (4)));
  495. struct ipr_hostrcb_array_data_entry_enhanced {
  496. struct ipr_ext_vpd vpd;
  497. u8 ccin[4];
  498. struct ipr_res_addr expected_dev_res_addr;
  499. struct ipr_res_addr dev_res_addr;
  500. }__attribute__((packed, aligned (4)));
  501. struct ipr_hostrcb_type_ff_error {
  502. __be32 ioa_data[502];
  503. }__attribute__((packed, aligned (4)));
  504. struct ipr_hostrcb_type_01_error {
  505. __be32 seek_counter;
  506. __be32 read_counter;
  507. u8 sense_data[32];
  508. __be32 ioa_data[236];
  509. }__attribute__((packed, aligned (4)));
  510. struct ipr_hostrcb_type_02_error {
  511. struct ipr_vpd ioa_vpd;
  512. struct ipr_vpd cfc_vpd;
  513. struct ipr_vpd ioa_last_attached_to_cfc_vpd;
  514. struct ipr_vpd cfc_last_attached_to_ioa_vpd;
  515. __be32 ioa_data[3];
  516. }__attribute__((packed, aligned (4)));
  517. struct ipr_hostrcb_type_12_error {
  518. struct ipr_ext_vpd ioa_vpd;
  519. struct ipr_ext_vpd cfc_vpd;
  520. struct ipr_ext_vpd ioa_last_attached_to_cfc_vpd;
  521. struct ipr_ext_vpd cfc_last_attached_to_ioa_vpd;
  522. __be32 ioa_data[3];
  523. }__attribute__((packed, aligned (4)));
  524. struct ipr_hostrcb_type_03_error {
  525. struct ipr_vpd ioa_vpd;
  526. struct ipr_vpd cfc_vpd;
  527. __be32 errors_detected;
  528. __be32 errors_logged;
  529. u8 ioa_data[12];
  530. struct ipr_hostrcb_device_data_entry dev[3];
  531. }__attribute__((packed, aligned (4)));
  532. struct ipr_hostrcb_type_13_error {
  533. struct ipr_ext_vpd ioa_vpd;
  534. struct ipr_ext_vpd cfc_vpd;
  535. __be32 errors_detected;
  536. __be32 errors_logged;
  537. struct ipr_hostrcb_device_data_entry_enhanced dev[3];
  538. }__attribute__((packed, aligned (4)));
  539. struct ipr_hostrcb_type_04_error {
  540. struct ipr_vpd ioa_vpd;
  541. struct ipr_vpd cfc_vpd;
  542. u8 ioa_data[12];
  543. struct ipr_hostrcb_array_data_entry array_member[10];
  544. __be32 exposed_mode_adn;
  545. __be32 array_id;
  546. struct ipr_vpd incomp_dev_vpd;
  547. __be32 ioa_data2;
  548. struct ipr_hostrcb_array_data_entry array_member2[8];
  549. struct ipr_res_addr last_func_vset_res_addr;
  550. u8 vset_serial_num[IPR_SERIAL_NUM_LEN];
  551. u8 protection_level[8];
  552. }__attribute__((packed, aligned (4)));
  553. struct ipr_hostrcb_type_14_error {
  554. struct ipr_ext_vpd ioa_vpd;
  555. struct ipr_ext_vpd cfc_vpd;
  556. __be32 exposed_mode_adn;
  557. __be32 array_id;
  558. struct ipr_res_addr last_func_vset_res_addr;
  559. u8 vset_serial_num[IPR_SERIAL_NUM_LEN];
  560. u8 protection_level[8];
  561. __be32 num_entries;
  562. struct ipr_hostrcb_array_data_entry_enhanced array_member[18];
  563. }__attribute__((packed, aligned (4)));
  564. struct ipr_hostrcb_type_07_error {
  565. u8 failure_reason[64];
  566. struct ipr_vpd vpd;
  567. u32 data[222];
  568. }__attribute__((packed, aligned (4)));
  569. struct ipr_hostrcb_type_17_error {
  570. u8 failure_reason[64];
  571. struct ipr_ext_vpd vpd;
  572. u32 data[476];
  573. }__attribute__((packed, aligned (4)));
  574. struct ipr_hostrcb_error {
  575. __be32 failing_dev_ioasc;
  576. struct ipr_res_addr failing_dev_res_addr;
  577. __be32 failing_dev_res_handle;
  578. __be32 prc;
  579. union {
  580. struct ipr_hostrcb_type_ff_error type_ff_error;
  581. struct ipr_hostrcb_type_01_error type_01_error;
  582. struct ipr_hostrcb_type_02_error type_02_error;
  583. struct ipr_hostrcb_type_03_error type_03_error;
  584. struct ipr_hostrcb_type_04_error type_04_error;
  585. struct ipr_hostrcb_type_07_error type_07_error;
  586. struct ipr_hostrcb_type_12_error type_12_error;
  587. struct ipr_hostrcb_type_13_error type_13_error;
  588. struct ipr_hostrcb_type_14_error type_14_error;
  589. struct ipr_hostrcb_type_17_error type_17_error;
  590. } u;
  591. }__attribute__((packed, aligned (4)));
  592. struct ipr_hostrcb_raw {
  593. __be32 data[sizeof(struct ipr_hostrcb_error)/sizeof(__be32)];
  594. }__attribute__((packed, aligned (4)));
  595. struct ipr_hcam {
  596. u8 op_code;
  597. #define IPR_HOST_RCB_OP_CODE_CONFIG_CHANGE 0xE1
  598. #define IPR_HOST_RCB_OP_CODE_LOG_DATA 0xE2
  599. u8 notify_type;
  600. #define IPR_HOST_RCB_NOTIF_TYPE_EXISTING_CHANGED 0x00
  601. #define IPR_HOST_RCB_NOTIF_TYPE_NEW_ENTRY 0x01
  602. #define IPR_HOST_RCB_NOTIF_TYPE_REM_ENTRY 0x02
  603. #define IPR_HOST_RCB_NOTIF_TYPE_ERROR_LOG_ENTRY 0x10
  604. #define IPR_HOST_RCB_NOTIF_TYPE_INFORMATION_ENTRY 0x11
  605. u8 notifications_lost;
  606. #define IPR_HOST_RCB_NO_NOTIFICATIONS_LOST 0
  607. #define IPR_HOST_RCB_NOTIFICATIONS_LOST 0x80
  608. u8 flags;
  609. #define IPR_HOSTRCB_INTERNAL_OPER 0x80
  610. #define IPR_HOSTRCB_ERR_RESP_SENT 0x40
  611. u8 overlay_id;
  612. #define IPR_HOST_RCB_OVERLAY_ID_1 0x01
  613. #define IPR_HOST_RCB_OVERLAY_ID_2 0x02
  614. #define IPR_HOST_RCB_OVERLAY_ID_3 0x03
  615. #define IPR_HOST_RCB_OVERLAY_ID_4 0x04
  616. #define IPR_HOST_RCB_OVERLAY_ID_6 0x06
  617. #define IPR_HOST_RCB_OVERLAY_ID_7 0x07
  618. #define IPR_HOST_RCB_OVERLAY_ID_12 0x12
  619. #define IPR_HOST_RCB_OVERLAY_ID_13 0x13
  620. #define IPR_HOST_RCB_OVERLAY_ID_14 0x14
  621. #define IPR_HOST_RCB_OVERLAY_ID_16 0x16
  622. #define IPR_HOST_RCB_OVERLAY_ID_17 0x17
  623. #define IPR_HOST_RCB_OVERLAY_ID_DEFAULT 0xFF
  624. u8 reserved1[3];
  625. __be32 ilid;
  626. __be32 time_since_last_ioa_reset;
  627. __be32 reserved2;
  628. __be32 length;
  629. union {
  630. struct ipr_hostrcb_error error;
  631. struct ipr_hostrcb_cfg_ch_not ccn;
  632. struct ipr_hostrcb_raw raw;
  633. } u;
  634. }__attribute__((packed, aligned (4)));
  635. struct ipr_hostrcb {
  636. struct ipr_hcam hcam;
  637. dma_addr_t hostrcb_dma;
  638. struct list_head queue;
  639. };
  640. /* IPR smart dump table structures */
  641. struct ipr_sdt_entry {
  642. __be32 bar_str_offset;
  643. __be32 end_offset;
  644. u8 entry_byte;
  645. u8 reserved[3];
  646. u8 flags;
  647. #define IPR_SDT_ENDIAN 0x80
  648. #define IPR_SDT_VALID_ENTRY 0x20
  649. u8 resv;
  650. __be16 priority;
  651. }__attribute__((packed, aligned (4)));
  652. struct ipr_sdt_header {
  653. __be32 state;
  654. __be32 num_entries;
  655. __be32 num_entries_used;
  656. __be32 dump_size;
  657. }__attribute__((packed, aligned (4)));
  658. struct ipr_sdt {
  659. struct ipr_sdt_header hdr;
  660. struct ipr_sdt_entry entry[IPR_NUM_SDT_ENTRIES];
  661. }__attribute__((packed, aligned (4)));
  662. struct ipr_uc_sdt {
  663. struct ipr_sdt_header hdr;
  664. struct ipr_sdt_entry entry[1];
  665. }__attribute__((packed, aligned (4)));
  666. /*
  667. * Driver types
  668. */
  669. struct ipr_bus_attributes {
  670. u8 bus;
  671. u8 qas_enabled;
  672. u8 bus_width;
  673. u8 reserved;
  674. u32 max_xfer_rate;
  675. };
  676. struct ipr_resource_entry {
  677. struct ipr_config_table_entry cfgte;
  678. u8 needs_sync_complete:1;
  679. u8 in_erp:1;
  680. u8 add_to_ml:1;
  681. u8 del_from_ml:1;
  682. u8 resetting_device:1;
  683. struct scsi_device *sdev;
  684. struct list_head queue;
  685. };
  686. struct ipr_resource_hdr {
  687. u16 num_entries;
  688. u16 reserved;
  689. };
  690. struct ipr_resource_table {
  691. struct ipr_resource_hdr hdr;
  692. struct ipr_resource_entry dev[IPR_MAX_PHYSICAL_DEVS];
  693. };
  694. struct ipr_misc_cbs {
  695. struct ipr_ioa_vpd ioa_vpd;
  696. struct ipr_inquiry_page0 page0_data;
  697. struct ipr_inquiry_page3 page3_data;
  698. struct ipr_mode_pages mode_pages;
  699. struct ipr_supported_device supp_dev;
  700. };
  701. struct ipr_interrupt_offsets {
  702. unsigned long set_interrupt_mask_reg;
  703. unsigned long clr_interrupt_mask_reg;
  704. unsigned long sense_interrupt_mask_reg;
  705. unsigned long clr_interrupt_reg;
  706. unsigned long sense_interrupt_reg;
  707. unsigned long ioarrin_reg;
  708. unsigned long sense_uproc_interrupt_reg;
  709. unsigned long set_uproc_interrupt_reg;
  710. unsigned long clr_uproc_interrupt_reg;
  711. };
  712. struct ipr_interrupts {
  713. void __iomem *set_interrupt_mask_reg;
  714. void __iomem *clr_interrupt_mask_reg;
  715. void __iomem *sense_interrupt_mask_reg;
  716. void __iomem *clr_interrupt_reg;
  717. void __iomem *sense_interrupt_reg;
  718. void __iomem *ioarrin_reg;
  719. void __iomem *sense_uproc_interrupt_reg;
  720. void __iomem *set_uproc_interrupt_reg;
  721. void __iomem *clr_uproc_interrupt_reg;
  722. };
  723. struct ipr_chip_cfg_t {
  724. u32 mailbox;
  725. u8 cache_line_size;
  726. struct ipr_interrupt_offsets regs;
  727. };
  728. struct ipr_chip_t {
  729. u16 vendor;
  730. u16 device;
  731. const struct ipr_chip_cfg_t *cfg;
  732. };
  733. enum ipr_shutdown_type {
  734. IPR_SHUTDOWN_NORMAL = 0x00,
  735. IPR_SHUTDOWN_PREPARE_FOR_NORMAL = 0x40,
  736. IPR_SHUTDOWN_ABBREV = 0x80,
  737. IPR_SHUTDOWN_NONE = 0x100
  738. };
  739. struct ipr_trace_entry {
  740. u32 time;
  741. u8 op_code;
  742. u8 type;
  743. #define IPR_TRACE_START 0x00
  744. #define IPR_TRACE_FINISH 0xff
  745. u16 cmd_index;
  746. __be32 res_handle;
  747. union {
  748. u32 ioasc;
  749. u32 add_data;
  750. u32 res_addr;
  751. } u;
  752. };
  753. struct ipr_sglist {
  754. u32 order;
  755. u32 num_sg;
  756. u32 num_dma_sg;
  757. u32 buffer_len;
  758. struct scatterlist scatterlist[1];
  759. };
  760. enum ipr_sdt_state {
  761. INACTIVE,
  762. WAIT_FOR_DUMP,
  763. GET_DUMP,
  764. ABORT_DUMP,
  765. DUMP_OBTAINED
  766. };
  767. enum ipr_cache_state {
  768. CACHE_NONE,
  769. CACHE_DISABLED,
  770. CACHE_ENABLED,
  771. CACHE_INVALID
  772. };
  773. /* Per-controller data */
  774. struct ipr_ioa_cfg {
  775. char eye_catcher[8];
  776. #define IPR_EYECATCHER "iprcfg"
  777. struct list_head queue;
  778. u8 allow_interrupts:1;
  779. u8 in_reset_reload:1;
  780. u8 in_ioa_bringdown:1;
  781. u8 ioa_unit_checked:1;
  782. u8 ioa_is_dead:1;
  783. u8 dump_taken:1;
  784. u8 allow_cmds:1;
  785. u8 allow_ml_add_del:1;
  786. u8 needs_hard_reset:1;
  787. enum ipr_cache_state cache_state;
  788. u16 type; /* CCIN of the card */
  789. u8 log_level;
  790. #define IPR_MAX_LOG_LEVEL 4
  791. #define IPR_DEFAULT_LOG_LEVEL 2
  792. #define IPR_NUM_TRACE_INDEX_BITS 8
  793. #define IPR_NUM_TRACE_ENTRIES (1 << IPR_NUM_TRACE_INDEX_BITS)
  794. #define IPR_TRACE_SIZE (sizeof(struct ipr_trace_entry) * IPR_NUM_TRACE_ENTRIES)
  795. char trace_start[8];
  796. #define IPR_TRACE_START_LABEL "trace"
  797. struct ipr_trace_entry *trace;
  798. u32 trace_index:IPR_NUM_TRACE_INDEX_BITS;
  799. /*
  800. * Queue for free command blocks
  801. */
  802. char ipr_free_label[8];
  803. #define IPR_FREEQ_LABEL "free-q"
  804. struct list_head free_q;
  805. /*
  806. * Queue for command blocks outstanding to the adapter
  807. */
  808. char ipr_pending_label[8];
  809. #define IPR_PENDQ_LABEL "pend-q"
  810. struct list_head pending_q;
  811. char cfg_table_start[8];
  812. #define IPR_CFG_TBL_START "cfg"
  813. struct ipr_config_table *cfg_table;
  814. dma_addr_t cfg_table_dma;
  815. char resource_table_label[8];
  816. #define IPR_RES_TABLE_LABEL "res_tbl"
  817. struct ipr_resource_entry *res_entries;
  818. struct list_head free_res_q;
  819. struct list_head used_res_q;
  820. char ipr_hcam_label[8];
  821. #define IPR_HCAM_LABEL "hcams"
  822. struct ipr_hostrcb *hostrcb[IPR_NUM_HCAMS];
  823. dma_addr_t hostrcb_dma[IPR_NUM_HCAMS];
  824. struct list_head hostrcb_free_q;
  825. struct list_head hostrcb_pending_q;
  826. __be32 *host_rrq;
  827. dma_addr_t host_rrq_dma;
  828. #define IPR_HRRQ_REQ_RESP_HANDLE_MASK 0xfffffffc
  829. #define IPR_HRRQ_RESP_BIT_SET 0x00000002
  830. #define IPR_HRRQ_TOGGLE_BIT 0x00000001
  831. #define IPR_HRRQ_REQ_RESP_HANDLE_SHIFT 2
  832. volatile __be32 *hrrq_start;
  833. volatile __be32 *hrrq_end;
  834. volatile __be32 *hrrq_curr;
  835. volatile u32 toggle_bit;
  836. struct ipr_bus_attributes bus_attr[IPR_MAX_NUM_BUSES];
  837. const struct ipr_chip_cfg_t *chip_cfg;
  838. void __iomem *hdw_dma_regs; /* iomapped PCI memory space */
  839. unsigned long hdw_dma_regs_pci; /* raw PCI memory space */
  840. void __iomem *ioa_mailbox;
  841. struct ipr_interrupts regs;
  842. u16 saved_pcix_cmd_reg;
  843. u16 reset_retries;
  844. u32 errors_logged;
  845. u32 doorbell;
  846. struct Scsi_Host *host;
  847. struct pci_dev *pdev;
  848. struct ipr_sglist *ucode_sglist;
  849. u8 saved_mode_page_len;
  850. struct work_struct work_q;
  851. wait_queue_head_t reset_wait_q;
  852. struct ipr_dump *dump;
  853. enum ipr_sdt_state sdt_state;
  854. struct ipr_misc_cbs *vpd_cbs;
  855. dma_addr_t vpd_cbs_dma;
  856. struct pci_pool *ipr_cmd_pool;
  857. struct ipr_cmnd *reset_cmd;
  858. char ipr_cmd_label[8];
  859. #define IPR_CMD_LABEL "ipr_cmnd"
  860. struct ipr_cmnd *ipr_cmnd_list[IPR_NUM_CMD_BLKS];
  861. u32 ipr_cmnd_list_dma[IPR_NUM_CMD_BLKS];
  862. };
  863. struct ipr_cmnd {
  864. struct ipr_ioarcb ioarcb;
  865. struct ipr_ioasa ioasa;
  866. struct ipr_ioadl_desc ioadl[IPR_NUM_IOADL_ENTRIES];
  867. struct list_head queue;
  868. struct scsi_cmnd *scsi_cmd;
  869. struct completion completion;
  870. struct timer_list timer;
  871. void (*done) (struct ipr_cmnd *);
  872. int (*job_step) (struct ipr_cmnd *);
  873. int (*job_step_failed) (struct ipr_cmnd *);
  874. u16 cmd_index;
  875. u8 sense_buffer[SCSI_SENSE_BUFFERSIZE];
  876. dma_addr_t sense_buffer_dma;
  877. unsigned short dma_use_sg;
  878. dma_addr_t dma_handle;
  879. struct ipr_cmnd *sibling;
  880. union {
  881. enum ipr_shutdown_type shutdown_type;
  882. struct ipr_hostrcb *hostrcb;
  883. unsigned long time_left;
  884. unsigned long scratch;
  885. struct ipr_resource_entry *res;
  886. struct scsi_device *sdev;
  887. } u;
  888. struct ipr_ioa_cfg *ioa_cfg;
  889. };
  890. struct ipr_ses_table_entry {
  891. char product_id[17];
  892. char compare_product_id_byte[17];
  893. u32 max_bus_speed_limit; /* MB/sec limit for this backplane */
  894. };
  895. struct ipr_dump_header {
  896. u32 eye_catcher;
  897. #define IPR_DUMP_EYE_CATCHER 0xC5D4E3F2
  898. u32 len;
  899. u32 num_entries;
  900. u32 first_entry_offset;
  901. u32 status;
  902. #define IPR_DUMP_STATUS_SUCCESS 0
  903. #define IPR_DUMP_STATUS_QUAL_SUCCESS 2
  904. #define IPR_DUMP_STATUS_FAILED 0xffffffff
  905. u32 os;
  906. #define IPR_DUMP_OS_LINUX 0x4C4E5558
  907. u32 driver_name;
  908. #define IPR_DUMP_DRIVER_NAME 0x49505232
  909. }__attribute__((packed, aligned (4)));
  910. struct ipr_dump_entry_header {
  911. u32 eye_catcher;
  912. #define IPR_DUMP_EYE_CATCHER 0xC5D4E3F2
  913. u32 len;
  914. u32 num_elems;
  915. u32 offset;
  916. u32 data_type;
  917. #define IPR_DUMP_DATA_TYPE_ASCII 0x41534349
  918. #define IPR_DUMP_DATA_TYPE_BINARY 0x42494E41
  919. u32 id;
  920. #define IPR_DUMP_IOA_DUMP_ID 0x494F4131
  921. #define IPR_DUMP_LOCATION_ID 0x4C4F4341
  922. #define IPR_DUMP_TRACE_ID 0x54524143
  923. #define IPR_DUMP_DRIVER_VERSION_ID 0x44525652
  924. #define IPR_DUMP_DRIVER_TYPE_ID 0x54595045
  925. #define IPR_DUMP_IOA_CTRL_BLK 0x494F4342
  926. #define IPR_DUMP_PEND_OPS 0x414F5053
  927. u32 status;
  928. }__attribute__((packed, aligned (4)));
  929. struct ipr_dump_location_entry {
  930. struct ipr_dump_entry_header hdr;
  931. u8 location[BUS_ID_SIZE];
  932. }__attribute__((packed));
  933. struct ipr_dump_trace_entry {
  934. struct ipr_dump_entry_header hdr;
  935. u32 trace[IPR_TRACE_SIZE / sizeof(u32)];
  936. }__attribute__((packed, aligned (4)));
  937. struct ipr_dump_version_entry {
  938. struct ipr_dump_entry_header hdr;
  939. u8 version[sizeof(IPR_DRIVER_VERSION)];
  940. };
  941. struct ipr_dump_ioa_type_entry {
  942. struct ipr_dump_entry_header hdr;
  943. u32 type;
  944. u32 fw_version;
  945. };
  946. struct ipr_driver_dump {
  947. struct ipr_dump_header hdr;
  948. struct ipr_dump_version_entry version_entry;
  949. struct ipr_dump_location_entry location_entry;
  950. struct ipr_dump_ioa_type_entry ioa_type_entry;
  951. struct ipr_dump_trace_entry trace_entry;
  952. }__attribute__((packed));
  953. struct ipr_ioa_dump {
  954. struct ipr_dump_entry_header hdr;
  955. struct ipr_sdt sdt;
  956. __be32 *ioa_data[IPR_MAX_NUM_DUMP_PAGES];
  957. u32 reserved;
  958. u32 next_page_index;
  959. u32 page_offset;
  960. u32 format;
  961. #define IPR_SDT_FMT2 2
  962. #define IPR_SDT_UNKNOWN 3
  963. }__attribute__((packed, aligned (4)));
  964. struct ipr_dump {
  965. struct kref kref;
  966. struct ipr_ioa_cfg *ioa_cfg;
  967. struct ipr_driver_dump driver_dump;
  968. struct ipr_ioa_dump ioa_dump;
  969. };
  970. struct ipr_error_table_t {
  971. u32 ioasc;
  972. int log_ioasa;
  973. int log_hcam;
  974. char *error;
  975. };
  976. struct ipr_software_inq_lid_info {
  977. __be32 load_id;
  978. __be32 timestamp[3];
  979. }__attribute__((packed, aligned (4)));
  980. struct ipr_ucode_image_header {
  981. __be32 header_length;
  982. __be32 lid_table_offset;
  983. u8 major_release;
  984. u8 card_type;
  985. u8 minor_release[2];
  986. u8 reserved[20];
  987. char eyecatcher[16];
  988. __be32 num_lids;
  989. struct ipr_software_inq_lid_info lid[1];
  990. }__attribute__((packed, aligned (4)));
  991. /*
  992. * Macros
  993. */
  994. #define IPR_DBG_CMD(CMD) if (ipr_debug) { CMD; }
  995. #ifdef CONFIG_SCSI_IPR_TRACE
  996. #define ipr_create_trace_file(kobj, attr) sysfs_create_bin_file(kobj, attr)
  997. #define ipr_remove_trace_file(kobj, attr) sysfs_remove_bin_file(kobj, attr)
  998. #else
  999. #define ipr_create_trace_file(kobj, attr) 0
  1000. #define ipr_remove_trace_file(kobj, attr) do { } while(0)
  1001. #endif
  1002. #ifdef CONFIG_SCSI_IPR_DUMP
  1003. #define ipr_create_dump_file(kobj, attr) sysfs_create_bin_file(kobj, attr)
  1004. #define ipr_remove_dump_file(kobj, attr) sysfs_remove_bin_file(kobj, attr)
  1005. #else
  1006. #define ipr_create_dump_file(kobj, attr) 0
  1007. #define ipr_remove_dump_file(kobj, attr) do { } while(0)
  1008. #endif
  1009. /*
  1010. * Error logging macros
  1011. */
  1012. #define ipr_err(...) printk(KERN_ERR IPR_NAME ": "__VA_ARGS__)
  1013. #define ipr_info(...) printk(KERN_INFO IPR_NAME ": "__VA_ARGS__)
  1014. #define ipr_dbg(...) IPR_DBG_CMD(printk(KERN_INFO IPR_NAME ": "__VA_ARGS__))
  1015. #define ipr_ra_printk(level, ioa_cfg, ra, fmt, ...) \
  1016. printk(level IPR_NAME ": %d:%d:%d:%d: " fmt, (ioa_cfg)->host->host_no, \
  1017. (ra).bus, (ra).target, (ra).lun, ##__VA_ARGS__)
  1018. #define ipr_ra_err(ioa_cfg, ra, fmt, ...) \
  1019. ipr_ra_printk(KERN_ERR, ioa_cfg, ra, fmt, ##__VA_ARGS__)
  1020. #define ipr_res_err(ioa_cfg, res, fmt, ...) \
  1021. ipr_ra_err(ioa_cfg, (res)->cfgte.res_addr, fmt, ##__VA_ARGS__)
  1022. #define ipr_phys_res_err(ioa_cfg, res, fmt, ...) \
  1023. { \
  1024. if ((res).bus >= IPR_MAX_NUM_BUSES) { \
  1025. ipr_err(fmt": unknown\n", ##__VA_ARGS__); \
  1026. } else { \
  1027. ipr_err(fmt": %d:%d:%d:%d\n", \
  1028. ##__VA_ARGS__, (ioa_cfg)->host->host_no, \
  1029. (res).bus, (res).target, (res).lun); \
  1030. } \
  1031. }
  1032. #define ipr_trace ipr_dbg("%s: %s: Line: %d\n",\
  1033. __FILE__, __FUNCTION__, __LINE__)
  1034. #define ENTER IPR_DBG_CMD(printk(KERN_INFO IPR_NAME": Entering %s\n", __FUNCTION__))
  1035. #define LEAVE IPR_DBG_CMD(printk(KERN_INFO IPR_NAME": Leaving %s\n", __FUNCTION__))
  1036. #define ipr_err_separator \
  1037. ipr_err("----------------------------------------------------------\n")
  1038. /*
  1039. * Inlines
  1040. */
  1041. /**
  1042. * ipr_is_ioa_resource - Determine if a resource is the IOA
  1043. * @res: resource entry struct
  1044. *
  1045. * Return value:
  1046. * 1 if IOA / 0 if not IOA
  1047. **/
  1048. static inline int ipr_is_ioa_resource(struct ipr_resource_entry *res)
  1049. {
  1050. return (res->cfgte.flags & IPR_IS_IOA_RESOURCE) ? 1 : 0;
  1051. }
  1052. /**
  1053. * ipr_is_af_dasd_device - Determine if a resource is an AF DASD
  1054. * @res: resource entry struct
  1055. *
  1056. * Return value:
  1057. * 1 if AF DASD / 0 if not AF DASD
  1058. **/
  1059. static inline int ipr_is_af_dasd_device(struct ipr_resource_entry *res)
  1060. {
  1061. if (IPR_IS_DASD_DEVICE(res->cfgte.std_inq_data) &&
  1062. !ipr_is_ioa_resource(res) &&
  1063. IPR_RES_SUBTYPE(res) == IPR_SUBTYPE_AF_DASD)
  1064. return 1;
  1065. else
  1066. return 0;
  1067. }
  1068. /**
  1069. * ipr_is_vset_device - Determine if a resource is a VSET
  1070. * @res: resource entry struct
  1071. *
  1072. * Return value:
  1073. * 1 if VSET / 0 if not VSET
  1074. **/
  1075. static inline int ipr_is_vset_device(struct ipr_resource_entry *res)
  1076. {
  1077. if (IPR_IS_DASD_DEVICE(res->cfgte.std_inq_data) &&
  1078. !ipr_is_ioa_resource(res) &&
  1079. IPR_RES_SUBTYPE(res) == IPR_SUBTYPE_VOLUME_SET)
  1080. return 1;
  1081. else
  1082. return 0;
  1083. }
  1084. /**
  1085. * ipr_is_gscsi - Determine if a resource is a generic scsi resource
  1086. * @res: resource entry struct
  1087. *
  1088. * Return value:
  1089. * 1 if GSCSI / 0 if not GSCSI
  1090. **/
  1091. static inline int ipr_is_gscsi(struct ipr_resource_entry *res)
  1092. {
  1093. if (!ipr_is_ioa_resource(res) &&
  1094. IPR_RES_SUBTYPE(res) == IPR_SUBTYPE_GENERIC_SCSI)
  1095. return 1;
  1096. else
  1097. return 0;
  1098. }
  1099. /**
  1100. * ipr_is_scsi_disk - Determine if a resource is a SCSI disk
  1101. * @res: resource entry struct
  1102. *
  1103. * Return value:
  1104. * 1 if SCSI disk / 0 if not SCSI disk
  1105. **/
  1106. static inline int ipr_is_scsi_disk(struct ipr_resource_entry *res)
  1107. {
  1108. if (ipr_is_af_dasd_device(res) ||
  1109. (ipr_is_gscsi(res) && IPR_IS_DASD_DEVICE(res->cfgte.std_inq_data)))
  1110. return 1;
  1111. else
  1112. return 0;
  1113. }
  1114. /**
  1115. * ipr_is_naca_model - Determine if a resource is using NACA queueing model
  1116. * @res: resource entry struct
  1117. *
  1118. * Return value:
  1119. * 1 if NACA queueing model / 0 if not NACA queueing model
  1120. **/
  1121. static inline int ipr_is_naca_model(struct ipr_resource_entry *res)
  1122. {
  1123. if (ipr_is_gscsi(res) && IPR_QUEUEING_MODEL(res) == IPR_QUEUE_NACA_MODEL)
  1124. return 1;
  1125. return 0;
  1126. }
  1127. /**
  1128. * ipr_is_device - Determine if resource address is that of a device
  1129. * @res_addr: resource address struct
  1130. *
  1131. * Return value:
  1132. * 1 if AF / 0 if not AF
  1133. **/
  1134. static inline int ipr_is_device(struct ipr_res_addr *res_addr)
  1135. {
  1136. if ((res_addr->bus < IPR_MAX_NUM_BUSES) &&
  1137. (res_addr->target < (IPR_MAX_NUM_TARGETS_PER_BUS - 1)))
  1138. return 1;
  1139. return 0;
  1140. }
  1141. /**
  1142. * ipr_sdt_is_fmt2 - Determine if a SDT address is in format 2
  1143. * @sdt_word: SDT address
  1144. *
  1145. * Return value:
  1146. * 1 if format 2 / 0 if not
  1147. **/
  1148. static inline int ipr_sdt_is_fmt2(u32 sdt_word)
  1149. {
  1150. u32 bar_sel = IPR_GET_FMT2_BAR_SEL(sdt_word);
  1151. switch (bar_sel) {
  1152. case IPR_SDT_FMT2_BAR0_SEL:
  1153. case IPR_SDT_FMT2_BAR1_SEL:
  1154. case IPR_SDT_FMT2_BAR2_SEL:
  1155. case IPR_SDT_FMT2_BAR3_SEL:
  1156. case IPR_SDT_FMT2_BAR4_SEL:
  1157. case IPR_SDT_FMT2_BAR5_SEL:
  1158. case IPR_SDT_FMT2_EXP_ROM_SEL:
  1159. return 1;
  1160. };
  1161. return 0;
  1162. }
  1163. #endif