cpuidle44xx.c 6.1 KB

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  1. /*
  2. * OMAP4 CPU idle Routines
  3. *
  4. * Copyright (C) 2011 Texas Instruments, Inc.
  5. * Santosh Shilimkar <santosh.shilimkar@ti.com>
  6. * Rajendra Nayak <rnayak@ti.com>
  7. *
  8. * This program is free software; you can redistribute it and/or modify
  9. * it under the terms of the GNU General Public License version 2 as
  10. * published by the Free Software Foundation.
  11. */
  12. #include <linux/sched.h>
  13. #include <linux/cpuidle.h>
  14. #include <linux/cpu_pm.h>
  15. #include <linux/export.h>
  16. #include <linux/clockchips.h>
  17. #include <asm/proc-fns.h>
  18. #include "common.h"
  19. #include "pm.h"
  20. #include "prm.h"
  21. #include "clockdomain.h"
  22. /* Machine specific information */
  23. struct omap4_idle_statedata {
  24. u32 cpu_state;
  25. u32 mpu_logic_state;
  26. u32 mpu_state;
  27. };
  28. static struct omap4_idle_statedata omap4_idle_data[] = {
  29. {
  30. .cpu_state = PWRDM_POWER_ON,
  31. .mpu_state = PWRDM_POWER_ON,
  32. .mpu_logic_state = PWRDM_POWER_RET,
  33. },
  34. {
  35. .cpu_state = PWRDM_POWER_OFF,
  36. .mpu_state = PWRDM_POWER_RET,
  37. .mpu_logic_state = PWRDM_POWER_RET,
  38. },
  39. {
  40. .cpu_state = PWRDM_POWER_OFF,
  41. .mpu_state = PWRDM_POWER_RET,
  42. .mpu_logic_state = PWRDM_POWER_OFF,
  43. },
  44. };
  45. static struct powerdomain *mpu_pd, *cpu_pd[NR_CPUS];
  46. static struct clockdomain *cpu_clkdm[NR_CPUS];
  47. static atomic_t abort_barrier;
  48. static bool cpu_done[NR_CPUS];
  49. /* Private functions */
  50. /**
  51. * omap4_enter_idle_coupled_[simple/coupled] - OMAP4 cpuidle entry functions
  52. * @dev: cpuidle device
  53. * @drv: cpuidle driver
  54. * @index: the index of state to be entered
  55. *
  56. * Called from the CPUidle framework to program the device to the
  57. * specified low power state selected by the governor.
  58. * Returns the amount of time spent in the low power state.
  59. */
  60. static int omap4_enter_idle_simple(struct cpuidle_device *dev,
  61. struct cpuidle_driver *drv,
  62. int index)
  63. {
  64. omap_do_wfi();
  65. return index;
  66. }
  67. static int omap4_enter_idle_coupled(struct cpuidle_device *dev,
  68. struct cpuidle_driver *drv,
  69. int index)
  70. {
  71. struct omap4_idle_statedata *cx = &omap4_idle_data[index];
  72. int cpu_id = smp_processor_id();
  73. /*
  74. * CPU0 has to wait and stay ON until CPU1 is OFF state.
  75. * This is necessary to honour hardware recommondation
  76. * of triggeing all the possible low power modes once CPU1 is
  77. * out of coherency and in OFF mode.
  78. */
  79. if (dev->cpu == 0 && cpumask_test_cpu(1, cpu_online_mask)) {
  80. while (pwrdm_read_pwrst(cpu_pd[1]) != PWRDM_POWER_OFF) {
  81. cpu_relax();
  82. /*
  83. * CPU1 could have already entered & exited idle
  84. * without hitting off because of a wakeup
  85. * or a failed attempt to hit off mode. Check for
  86. * that here, otherwise we could spin forever
  87. * waiting for CPU1 off.
  88. */
  89. if (cpu_done[1])
  90. goto fail;
  91. }
  92. }
  93. clockevents_notify(CLOCK_EVT_NOTIFY_BROADCAST_ENTER, &cpu_id);
  94. /*
  95. * Call idle CPU PM enter notifier chain so that
  96. * VFP and per CPU interrupt context is saved.
  97. */
  98. cpu_pm_enter();
  99. if (dev->cpu == 0) {
  100. pwrdm_set_logic_retst(mpu_pd, cx->mpu_logic_state);
  101. omap_set_pwrdm_state(mpu_pd, cx->mpu_state);
  102. /*
  103. * Call idle CPU cluster PM enter notifier chain
  104. * to save GIC and wakeupgen context.
  105. */
  106. if ((cx->mpu_state == PWRDM_POWER_RET) &&
  107. (cx->mpu_logic_state == PWRDM_POWER_OFF))
  108. cpu_cluster_pm_enter();
  109. }
  110. omap4_enter_lowpower(dev->cpu, cx->cpu_state);
  111. cpu_done[dev->cpu] = true;
  112. /* Wakeup CPU1 only if it is not offlined */
  113. if (dev->cpu == 0 && cpumask_test_cpu(1, cpu_online_mask)) {
  114. clkdm_wakeup(cpu_clkdm[1]);
  115. clkdm_allow_idle(cpu_clkdm[1]);
  116. }
  117. /*
  118. * Call idle CPU PM exit notifier chain to restore
  119. * VFP and per CPU IRQ context.
  120. */
  121. cpu_pm_exit();
  122. /*
  123. * Call idle CPU cluster PM exit notifier chain
  124. * to restore GIC and wakeupgen context.
  125. */
  126. if (omap4_mpuss_read_prev_context_state())
  127. cpu_cluster_pm_exit();
  128. clockevents_notify(CLOCK_EVT_NOTIFY_BROADCAST_EXIT, &cpu_id);
  129. fail:
  130. cpuidle_coupled_parallel_barrier(dev, &abort_barrier);
  131. cpu_done[dev->cpu] = false;
  132. return index;
  133. }
  134. /*
  135. * For each cpu, setup the broadcast timer because local timers
  136. * stops for the states above C1.
  137. */
  138. static void omap_setup_broadcast_timer(void *arg)
  139. {
  140. int cpu = smp_processor_id();
  141. clockevents_notify(CLOCK_EVT_NOTIFY_BROADCAST_ON, &cpu);
  142. }
  143. static DEFINE_PER_CPU(struct cpuidle_device, omap4_idle_dev);
  144. static struct cpuidle_driver omap4_idle_driver = {
  145. .name = "omap4_idle",
  146. .owner = THIS_MODULE,
  147. .en_core_tk_irqen = 1,
  148. .states = {
  149. {
  150. /* C1 - CPU0 ON + CPU1 ON + MPU ON */
  151. .exit_latency = 2 + 2,
  152. .target_residency = 5,
  153. .flags = CPUIDLE_FLAG_TIME_VALID,
  154. .enter = omap4_enter_idle_simple,
  155. .name = "C1",
  156. .desc = "MPUSS ON"
  157. },
  158. {
  159. /* C2 - CPU0 OFF + CPU1 OFF + MPU CSWR */
  160. .exit_latency = 328 + 440,
  161. .target_residency = 960,
  162. .flags = CPUIDLE_FLAG_TIME_VALID | CPUIDLE_FLAG_COUPLED,
  163. .enter = omap4_enter_idle_coupled,
  164. .name = "C2",
  165. .desc = "MPUSS CSWR",
  166. },
  167. {
  168. /* C3 - CPU0 OFF + CPU1 OFF + MPU OSWR */
  169. .exit_latency = 460 + 518,
  170. .target_residency = 1100,
  171. .flags = CPUIDLE_FLAG_TIME_VALID | CPUIDLE_FLAG_COUPLED,
  172. .enter = omap4_enter_idle_coupled,
  173. .name = "C3",
  174. .desc = "MPUSS OSWR",
  175. },
  176. },
  177. .state_count = ARRAY_SIZE(omap4_idle_data),
  178. .safe_state_index = 0,
  179. };
  180. /* Public functions */
  181. /**
  182. * omap4_idle_init - Init routine for OMAP4 idle
  183. *
  184. * Registers the OMAP4 specific cpuidle driver to the cpuidle
  185. * framework with the valid set of states.
  186. */
  187. int __init omap4_idle_init(void)
  188. {
  189. struct cpuidle_device *dev;
  190. unsigned int cpu_id = 0;
  191. mpu_pd = pwrdm_lookup("mpu_pwrdm");
  192. cpu_pd[0] = pwrdm_lookup("cpu0_pwrdm");
  193. cpu_pd[1] = pwrdm_lookup("cpu1_pwrdm");
  194. if ((!mpu_pd) || (!cpu_pd[0]) || (!cpu_pd[1]))
  195. return -ENODEV;
  196. cpu_clkdm[0] = clkdm_lookup("mpu0_clkdm");
  197. cpu_clkdm[1] = clkdm_lookup("mpu1_clkdm");
  198. if (!cpu_clkdm[0] || !cpu_clkdm[1])
  199. return -ENODEV;
  200. /* Configure the broadcast timer on each cpu */
  201. on_each_cpu(omap_setup_broadcast_timer, NULL, 1);
  202. for_each_cpu(cpu_id, cpu_online_mask) {
  203. dev = &per_cpu(omap4_idle_dev, cpu_id);
  204. dev->cpu = cpu_id;
  205. #ifdef CONFIG_ARCH_NEEDS_CPU_IDLE_COUPLED
  206. dev->coupled_cpus = *cpu_online_mask;
  207. #endif
  208. cpuidle_register_driver(&omap4_idle_driver);
  209. if (cpuidle_register_device(dev)) {
  210. pr_err("%s: CPUidle register failed\n", __func__);
  211. return -EIO;
  212. }
  213. }
  214. return 0;
  215. }