sdhci.c 33 KB

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  1. /*
  2. * linux/drivers/mmc/sdhci.c - Secure Digital Host Controller Interface driver
  3. *
  4. * Copyright (C) 2005-2006 Pierre Ossman, All Rights Reserved.
  5. *
  6. * This program is free software; you can redistribute it and/or modify
  7. * it under the terms of the GNU General Public License version 2 as
  8. * published by the Free Software Foundation.
  9. */
  10. #include <linux/delay.h>
  11. #include <linux/highmem.h>
  12. #include <linux/pci.h>
  13. #include <linux/dma-mapping.h>
  14. #include <linux/mmc/host.h>
  15. #include <linux/mmc/protocol.h>
  16. #include <asm/scatterlist.h>
  17. #include "sdhci.h"
  18. #define DRIVER_NAME "sdhci"
  19. #define DRIVER_VERSION "0.11"
  20. #define BUGMAIL "<sdhci-devel@list.drzeus.cx>"
  21. #define DBG(f, x...) \
  22. pr_debug(DRIVER_NAME " [%s()]: " f, __func__,## x)
  23. static const struct pci_device_id pci_ids[] __devinitdata = {
  24. /* handle any SD host controller */
  25. {PCI_DEVICE_CLASS((PCI_CLASS_SYSTEM_SDHCI << 8), 0xFFFF00)},
  26. { /* end: all zeroes */ },
  27. };
  28. MODULE_DEVICE_TABLE(pci, pci_ids);
  29. static void sdhci_prepare_data(struct sdhci_host *, struct mmc_data *);
  30. static void sdhci_finish_data(struct sdhci_host *);
  31. static void sdhci_send_command(struct sdhci_host *, struct mmc_command *);
  32. static void sdhci_finish_command(struct sdhci_host *);
  33. static void sdhci_dumpregs(struct sdhci_host *host)
  34. {
  35. printk(KERN_DEBUG DRIVER_NAME ": ============== REGISTER DUMP ==============\n");
  36. printk(KERN_DEBUG DRIVER_NAME ": Sys addr: 0x%08x | Version: 0x%08x\n",
  37. readl(host->ioaddr + SDHCI_DMA_ADDRESS),
  38. readw(host->ioaddr + SDHCI_HOST_VERSION));
  39. printk(KERN_DEBUG DRIVER_NAME ": Blk size: 0x%08x | Blk cnt: 0x%08x\n",
  40. readw(host->ioaddr + SDHCI_BLOCK_SIZE),
  41. readw(host->ioaddr + SDHCI_BLOCK_COUNT));
  42. printk(KERN_DEBUG DRIVER_NAME ": Argument: 0x%08x | Trn mode: 0x%08x\n",
  43. readl(host->ioaddr + SDHCI_ARGUMENT),
  44. readw(host->ioaddr + SDHCI_TRANSFER_MODE));
  45. printk(KERN_DEBUG DRIVER_NAME ": Present: 0x%08x | Host ctl: 0x%08x\n",
  46. readl(host->ioaddr + SDHCI_PRESENT_STATE),
  47. readb(host->ioaddr + SDHCI_HOST_CONTROL));
  48. printk(KERN_DEBUG DRIVER_NAME ": Power: 0x%08x | Blk gap: 0x%08x\n",
  49. readb(host->ioaddr + SDHCI_POWER_CONTROL),
  50. readb(host->ioaddr + SDHCI_BLOCK_GAP_CONTROL));
  51. printk(KERN_DEBUG DRIVER_NAME ": Wake-up: 0x%08x | Clock: 0x%08x\n",
  52. readb(host->ioaddr + SDHCI_WALK_UP_CONTROL),
  53. readw(host->ioaddr + SDHCI_CLOCK_CONTROL));
  54. printk(KERN_DEBUG DRIVER_NAME ": Timeout: 0x%08x | Int stat: 0x%08x\n",
  55. readb(host->ioaddr + SDHCI_TIMEOUT_CONTROL),
  56. readl(host->ioaddr + SDHCI_INT_STATUS));
  57. printk(KERN_DEBUG DRIVER_NAME ": Int enab: 0x%08x | Sig enab: 0x%08x\n",
  58. readl(host->ioaddr + SDHCI_INT_ENABLE),
  59. readl(host->ioaddr + SDHCI_SIGNAL_ENABLE));
  60. printk(KERN_DEBUG DRIVER_NAME ": AC12 err: 0x%08x | Slot int: 0x%08x\n",
  61. readw(host->ioaddr + SDHCI_ACMD12_ERR),
  62. readw(host->ioaddr + SDHCI_SLOT_INT_STATUS));
  63. printk(KERN_DEBUG DRIVER_NAME ": Caps: 0x%08x | Max curr: 0x%08x\n",
  64. readl(host->ioaddr + SDHCI_CAPABILITIES),
  65. readl(host->ioaddr + SDHCI_MAX_CURRENT));
  66. printk(KERN_DEBUG DRIVER_NAME ": ===========================================\n");
  67. }
  68. /*****************************************************************************\
  69. * *
  70. * Low level functions *
  71. * *
  72. \*****************************************************************************/
  73. static void sdhci_reset(struct sdhci_host *host, u8 mask)
  74. {
  75. unsigned long timeout;
  76. writeb(mask, host->ioaddr + SDHCI_SOFTWARE_RESET);
  77. if (mask & SDHCI_RESET_ALL)
  78. host->clock = 0;
  79. /* Wait max 100 ms */
  80. timeout = 100;
  81. /* hw clears the bit when it's done */
  82. while (readb(host->ioaddr + SDHCI_SOFTWARE_RESET) & mask) {
  83. if (timeout == 0) {
  84. printk(KERN_ERR "%s: Reset 0x%x never completed. "
  85. "Please report this to " BUGMAIL ".\n",
  86. mmc_hostname(host->mmc), (int)mask);
  87. sdhci_dumpregs(host);
  88. return;
  89. }
  90. timeout--;
  91. mdelay(1);
  92. }
  93. }
  94. static void sdhci_init(struct sdhci_host *host)
  95. {
  96. u32 intmask;
  97. sdhci_reset(host, SDHCI_RESET_ALL);
  98. intmask = SDHCI_INT_BUS_POWER | SDHCI_INT_DATA_END_BIT |
  99. SDHCI_INT_DATA_CRC | SDHCI_INT_DATA_TIMEOUT | SDHCI_INT_INDEX |
  100. SDHCI_INT_END_BIT | SDHCI_INT_CRC | SDHCI_INT_TIMEOUT |
  101. SDHCI_INT_CARD_REMOVE | SDHCI_INT_CARD_INSERT |
  102. SDHCI_INT_DATA_AVAIL | SDHCI_INT_SPACE_AVAIL |
  103. SDHCI_INT_DMA_END | SDHCI_INT_DATA_END | SDHCI_INT_RESPONSE;
  104. writel(intmask, host->ioaddr + SDHCI_INT_ENABLE);
  105. writel(intmask, host->ioaddr + SDHCI_SIGNAL_ENABLE);
  106. }
  107. static void sdhci_activate_led(struct sdhci_host *host)
  108. {
  109. u8 ctrl;
  110. ctrl = readb(host->ioaddr + SDHCI_HOST_CONTROL);
  111. ctrl |= SDHCI_CTRL_LED;
  112. writeb(ctrl, host->ioaddr + SDHCI_HOST_CONTROL);
  113. }
  114. static void sdhci_deactivate_led(struct sdhci_host *host)
  115. {
  116. u8 ctrl;
  117. ctrl = readb(host->ioaddr + SDHCI_HOST_CONTROL);
  118. ctrl &= ~SDHCI_CTRL_LED;
  119. writeb(ctrl, host->ioaddr + SDHCI_HOST_CONTROL);
  120. }
  121. /*****************************************************************************\
  122. * *
  123. * Core functions *
  124. * *
  125. \*****************************************************************************/
  126. static inline char* sdhci_kmap_sg(struct sdhci_host* host)
  127. {
  128. host->mapped_sg = kmap_atomic(host->cur_sg->page, KM_BIO_SRC_IRQ);
  129. return host->mapped_sg + host->cur_sg->offset;
  130. }
  131. static inline void sdhci_kunmap_sg(struct sdhci_host* host)
  132. {
  133. kunmap_atomic(host->mapped_sg, KM_BIO_SRC_IRQ);
  134. }
  135. static inline int sdhci_next_sg(struct sdhci_host* host)
  136. {
  137. /*
  138. * Skip to next SG entry.
  139. */
  140. host->cur_sg++;
  141. host->num_sg--;
  142. /*
  143. * Any entries left?
  144. */
  145. if (host->num_sg > 0) {
  146. host->offset = 0;
  147. host->remain = host->cur_sg->length;
  148. }
  149. return host->num_sg;
  150. }
  151. static void sdhci_read_block_pio(struct sdhci_host *host)
  152. {
  153. int blksize, chunk_remain;
  154. u32 data;
  155. char *buffer;
  156. int size;
  157. DBG("PIO reading\n");
  158. blksize = host->data->blksz;
  159. chunk_remain = 0;
  160. data = 0;
  161. buffer = sdhci_kmap_sg(host) + host->offset;
  162. while (blksize) {
  163. if (chunk_remain == 0) {
  164. data = readl(host->ioaddr + SDHCI_BUFFER);
  165. chunk_remain = min(blksize, 4);
  166. }
  167. size = min(host->size, host->remain);
  168. size = min(size, chunk_remain);
  169. chunk_remain -= size;
  170. blksize -= size;
  171. host->offset += size;
  172. host->remain -= size;
  173. host->size -= size;
  174. while (size) {
  175. *buffer = data & 0xFF;
  176. buffer++;
  177. data >>= 8;
  178. size--;
  179. }
  180. if (host->remain == 0) {
  181. sdhci_kunmap_sg(host);
  182. if (sdhci_next_sg(host) == 0) {
  183. BUG_ON(blksize != 0);
  184. return;
  185. }
  186. buffer = sdhci_kmap_sg(host);
  187. }
  188. }
  189. sdhci_kunmap_sg(host);
  190. }
  191. static void sdhci_write_block_pio(struct sdhci_host *host)
  192. {
  193. int blksize, chunk_remain;
  194. u32 data;
  195. char *buffer;
  196. int bytes, size;
  197. DBG("PIO writing\n");
  198. blksize = host->data->blksz;
  199. chunk_remain = 4;
  200. data = 0;
  201. bytes = 0;
  202. buffer = sdhci_kmap_sg(host) + host->offset;
  203. while (blksize) {
  204. size = min(host->size, host->remain);
  205. size = min(size, chunk_remain);
  206. chunk_remain -= size;
  207. blksize -= size;
  208. host->offset += size;
  209. host->remain -= size;
  210. host->size -= size;
  211. while (size) {
  212. data >>= 8;
  213. data |= (u32)*buffer << 24;
  214. buffer++;
  215. size--;
  216. }
  217. if (chunk_remain == 0) {
  218. writel(data, host->ioaddr + SDHCI_BUFFER);
  219. chunk_remain = min(blksize, 4);
  220. }
  221. if (host->remain == 0) {
  222. sdhci_kunmap_sg(host);
  223. if (sdhci_next_sg(host) == 0) {
  224. BUG_ON(blksize != 0);
  225. return;
  226. }
  227. buffer = sdhci_kmap_sg(host);
  228. }
  229. }
  230. sdhci_kunmap_sg(host);
  231. }
  232. static void sdhci_transfer_pio(struct sdhci_host *host)
  233. {
  234. u32 mask;
  235. BUG_ON(!host->data);
  236. if (host->size == 0)
  237. return;
  238. if (host->data->flags & MMC_DATA_READ)
  239. mask = SDHCI_DATA_AVAILABLE;
  240. else
  241. mask = SDHCI_SPACE_AVAILABLE;
  242. while (readl(host->ioaddr + SDHCI_PRESENT_STATE) & mask) {
  243. if (host->data->flags & MMC_DATA_READ)
  244. sdhci_read_block_pio(host);
  245. else
  246. sdhci_write_block_pio(host);
  247. if (host->size == 0)
  248. break;
  249. BUG_ON(host->num_sg == 0);
  250. }
  251. DBG("PIO transfer complete.\n");
  252. }
  253. static void sdhci_prepare_data(struct sdhci_host *host, struct mmc_data *data)
  254. {
  255. u8 count;
  256. unsigned target_timeout, current_timeout;
  257. WARN_ON(host->data);
  258. if (data == NULL)
  259. return;
  260. DBG("blksz %04x blks %04x flags %08x\n",
  261. data->blksz, data->blocks, data->flags);
  262. DBG("tsac %d ms nsac %d clk\n",
  263. data->timeout_ns / 1000000, data->timeout_clks);
  264. /* Sanity checks */
  265. BUG_ON(data->blksz * data->blocks > 524288);
  266. /* timeout in us */
  267. target_timeout = data->timeout_ns / 1000 +
  268. data->timeout_clks / host->clock;
  269. /*
  270. * Figure out needed cycles.
  271. * We do this in steps in order to fit inside a 32 bit int.
  272. * The first step is the minimum timeout, which will have a
  273. * minimum resolution of 6 bits:
  274. * (1) 2^13*1000 > 2^22,
  275. * (2) host->timeout_clk < 2^16
  276. * =>
  277. * (1) / (2) > 2^6
  278. */
  279. count = 0;
  280. current_timeout = (1 << 13) * 1000 / host->timeout_clk;
  281. while (current_timeout < target_timeout) {
  282. count++;
  283. current_timeout <<= 1;
  284. if (count >= 0xF)
  285. break;
  286. }
  287. if (count >= 0xF) {
  288. printk(KERN_WARNING "%s: Too large timeout requested!\n",
  289. mmc_hostname(host->mmc));
  290. count = 0xE;
  291. }
  292. writeb(count, host->ioaddr + SDHCI_TIMEOUT_CONTROL);
  293. if (host->flags & SDHCI_USE_DMA) {
  294. int count;
  295. count = pci_map_sg(host->chip->pdev, data->sg, data->sg_len,
  296. (data->flags & MMC_DATA_READ)?PCI_DMA_FROMDEVICE:PCI_DMA_TODEVICE);
  297. BUG_ON(count != 1);
  298. writel(sg_dma_address(data->sg), host->ioaddr + SDHCI_DMA_ADDRESS);
  299. } else {
  300. host->size = data->blksz * data->blocks;
  301. host->cur_sg = data->sg;
  302. host->num_sg = data->sg_len;
  303. host->offset = 0;
  304. host->remain = host->cur_sg->length;
  305. }
  306. /* We do not handle DMA boundaries, so set it to max (512 KiB) */
  307. writew(SDHCI_MAKE_BLKSZ(7, data->blksz),
  308. host->ioaddr + SDHCI_BLOCK_SIZE);
  309. writew(data->blocks, host->ioaddr + SDHCI_BLOCK_COUNT);
  310. }
  311. static void sdhci_set_transfer_mode(struct sdhci_host *host,
  312. struct mmc_data *data)
  313. {
  314. u16 mode;
  315. WARN_ON(host->data);
  316. if (data == NULL)
  317. return;
  318. mode = SDHCI_TRNS_BLK_CNT_EN;
  319. if (data->blocks > 1)
  320. mode |= SDHCI_TRNS_MULTI;
  321. if (data->flags & MMC_DATA_READ)
  322. mode |= SDHCI_TRNS_READ;
  323. if (host->flags & SDHCI_USE_DMA)
  324. mode |= SDHCI_TRNS_DMA;
  325. writew(mode, host->ioaddr + SDHCI_TRANSFER_MODE);
  326. }
  327. static void sdhci_finish_data(struct sdhci_host *host)
  328. {
  329. struct mmc_data *data;
  330. u16 blocks;
  331. BUG_ON(!host->data);
  332. data = host->data;
  333. host->data = NULL;
  334. if (host->flags & SDHCI_USE_DMA) {
  335. pci_unmap_sg(host->chip->pdev, data->sg, data->sg_len,
  336. (data->flags & MMC_DATA_READ)?PCI_DMA_FROMDEVICE:PCI_DMA_TODEVICE);
  337. }
  338. /*
  339. * Controller doesn't count down when in single block mode.
  340. */
  341. if ((data->blocks == 1) && (data->error == MMC_ERR_NONE))
  342. blocks = 0;
  343. else
  344. blocks = readw(host->ioaddr + SDHCI_BLOCK_COUNT);
  345. data->bytes_xfered = data->blksz * (data->blocks - blocks);
  346. if ((data->error == MMC_ERR_NONE) && blocks) {
  347. printk(KERN_ERR "%s: Controller signalled completion even "
  348. "though there were blocks left. Please report this "
  349. "to " BUGMAIL ".\n", mmc_hostname(host->mmc));
  350. data->error = MMC_ERR_FAILED;
  351. }
  352. if (host->size != 0) {
  353. printk(KERN_ERR "%s: %d bytes were left untransferred. "
  354. "Please report this to " BUGMAIL ".\n",
  355. mmc_hostname(host->mmc), host->size);
  356. data->error = MMC_ERR_FAILED;
  357. }
  358. DBG("Ending data transfer (%d bytes)\n", data->bytes_xfered);
  359. if (data->stop) {
  360. /*
  361. * The controller needs a reset of internal state machines
  362. * upon error conditions.
  363. */
  364. if (data->error != MMC_ERR_NONE) {
  365. sdhci_reset(host, SDHCI_RESET_CMD);
  366. sdhci_reset(host, SDHCI_RESET_DATA);
  367. }
  368. sdhci_send_command(host, data->stop);
  369. } else
  370. tasklet_schedule(&host->finish_tasklet);
  371. }
  372. static void sdhci_send_command(struct sdhci_host *host, struct mmc_command *cmd)
  373. {
  374. int flags;
  375. unsigned long timeout;
  376. WARN_ON(host->cmd);
  377. DBG("Sending cmd (%x)\n", cmd->opcode);
  378. /* Wait max 10 ms */
  379. timeout = 10;
  380. while (readl(host->ioaddr + SDHCI_PRESENT_STATE) &
  381. (SDHCI_CMD_INHIBIT | SDHCI_DATA_INHIBIT)) {
  382. if (timeout == 0) {
  383. printk(KERN_ERR "%s: Controller never released "
  384. "inhibit bits. Please report this to "
  385. BUGMAIL ".\n", mmc_hostname(host->mmc));
  386. sdhci_dumpregs(host);
  387. cmd->error = MMC_ERR_FAILED;
  388. tasklet_schedule(&host->finish_tasklet);
  389. return;
  390. }
  391. timeout--;
  392. mdelay(1);
  393. }
  394. mod_timer(&host->timer, jiffies + 10 * HZ);
  395. host->cmd = cmd;
  396. sdhci_prepare_data(host, cmd->data);
  397. writel(cmd->arg, host->ioaddr + SDHCI_ARGUMENT);
  398. sdhci_set_transfer_mode(host, cmd->data);
  399. if ((cmd->flags & MMC_RSP_136) && (cmd->flags & MMC_RSP_BUSY)) {
  400. printk(KERN_ERR "%s: Unsupported response type! "
  401. "Please report this to " BUGMAIL ".\n",
  402. mmc_hostname(host->mmc));
  403. cmd->error = MMC_ERR_INVALID;
  404. tasklet_schedule(&host->finish_tasklet);
  405. return;
  406. }
  407. if (!(cmd->flags & MMC_RSP_PRESENT))
  408. flags = SDHCI_CMD_RESP_NONE;
  409. else if (cmd->flags & MMC_RSP_136)
  410. flags = SDHCI_CMD_RESP_LONG;
  411. else if (cmd->flags & MMC_RSP_BUSY)
  412. flags = SDHCI_CMD_RESP_SHORT_BUSY;
  413. else
  414. flags = SDHCI_CMD_RESP_SHORT;
  415. if (cmd->flags & MMC_RSP_CRC)
  416. flags |= SDHCI_CMD_CRC;
  417. if (cmd->flags & MMC_RSP_OPCODE)
  418. flags |= SDHCI_CMD_INDEX;
  419. if (cmd->data)
  420. flags |= SDHCI_CMD_DATA;
  421. writel(SDHCI_MAKE_CMD(cmd->opcode, flags),
  422. host->ioaddr + SDHCI_COMMAND);
  423. }
  424. static void sdhci_finish_command(struct sdhci_host *host)
  425. {
  426. int i;
  427. BUG_ON(host->cmd == NULL);
  428. if (host->cmd->flags & MMC_RSP_PRESENT) {
  429. if (host->cmd->flags & MMC_RSP_136) {
  430. /* CRC is stripped so we need to do some shifting. */
  431. for (i = 0;i < 4;i++) {
  432. host->cmd->resp[i] = readl(host->ioaddr +
  433. SDHCI_RESPONSE + (3-i)*4) << 8;
  434. if (i != 3)
  435. host->cmd->resp[i] |=
  436. readb(host->ioaddr +
  437. SDHCI_RESPONSE + (3-i)*4-1);
  438. }
  439. } else {
  440. host->cmd->resp[0] = readl(host->ioaddr + SDHCI_RESPONSE);
  441. }
  442. }
  443. host->cmd->error = MMC_ERR_NONE;
  444. DBG("Ending cmd (%x)\n", host->cmd->opcode);
  445. if (host->cmd->data)
  446. host->data = host->cmd->data;
  447. else
  448. tasklet_schedule(&host->finish_tasklet);
  449. host->cmd = NULL;
  450. }
  451. static void sdhci_set_clock(struct sdhci_host *host, unsigned int clock)
  452. {
  453. int div;
  454. u16 clk;
  455. unsigned long timeout;
  456. if (clock == host->clock)
  457. return;
  458. writew(0, host->ioaddr + SDHCI_CLOCK_CONTROL);
  459. if (clock == 0)
  460. goto out;
  461. for (div = 1;div < 256;div *= 2) {
  462. if ((host->max_clk / div) <= clock)
  463. break;
  464. }
  465. div >>= 1;
  466. clk = div << SDHCI_DIVIDER_SHIFT;
  467. clk |= SDHCI_CLOCK_INT_EN;
  468. writew(clk, host->ioaddr + SDHCI_CLOCK_CONTROL);
  469. /* Wait max 10 ms */
  470. timeout = 10;
  471. while (!((clk = readw(host->ioaddr + SDHCI_CLOCK_CONTROL))
  472. & SDHCI_CLOCK_INT_STABLE)) {
  473. if (timeout == 0) {
  474. printk(KERN_ERR "%s: Internal clock never stabilised. "
  475. "Please report this to " BUGMAIL ".\n",
  476. mmc_hostname(host->mmc));
  477. sdhci_dumpregs(host);
  478. return;
  479. }
  480. timeout--;
  481. mdelay(1);
  482. }
  483. clk |= SDHCI_CLOCK_CARD_EN;
  484. writew(clk, host->ioaddr + SDHCI_CLOCK_CONTROL);
  485. out:
  486. host->clock = clock;
  487. }
  488. static void sdhci_set_power(struct sdhci_host *host, unsigned short power)
  489. {
  490. u8 pwr;
  491. if (host->power == power)
  492. return;
  493. writeb(0, host->ioaddr + SDHCI_POWER_CONTROL);
  494. if (power == (unsigned short)-1)
  495. goto out;
  496. pwr = SDHCI_POWER_ON;
  497. switch (power) {
  498. case MMC_VDD_170:
  499. case MMC_VDD_180:
  500. case MMC_VDD_190:
  501. pwr |= SDHCI_POWER_180;
  502. break;
  503. case MMC_VDD_290:
  504. case MMC_VDD_300:
  505. case MMC_VDD_310:
  506. pwr |= SDHCI_POWER_300;
  507. break;
  508. case MMC_VDD_320:
  509. case MMC_VDD_330:
  510. case MMC_VDD_340:
  511. pwr |= SDHCI_POWER_330;
  512. break;
  513. default:
  514. BUG();
  515. }
  516. writeb(pwr, host->ioaddr + SDHCI_POWER_CONTROL);
  517. out:
  518. host->power = power;
  519. }
  520. /*****************************************************************************\
  521. * *
  522. * MMC callbacks *
  523. * *
  524. \*****************************************************************************/
  525. static void sdhci_request(struct mmc_host *mmc, struct mmc_request *mrq)
  526. {
  527. struct sdhci_host *host;
  528. unsigned long flags;
  529. host = mmc_priv(mmc);
  530. spin_lock_irqsave(&host->lock, flags);
  531. WARN_ON(host->mrq != NULL);
  532. sdhci_activate_led(host);
  533. host->mrq = mrq;
  534. if (!(readl(host->ioaddr + SDHCI_PRESENT_STATE) & SDHCI_CARD_PRESENT)) {
  535. host->mrq->cmd->error = MMC_ERR_TIMEOUT;
  536. tasklet_schedule(&host->finish_tasklet);
  537. } else
  538. sdhci_send_command(host, mrq->cmd);
  539. spin_unlock_irqrestore(&host->lock, flags);
  540. }
  541. static void sdhci_set_ios(struct mmc_host *mmc, struct mmc_ios *ios)
  542. {
  543. struct sdhci_host *host;
  544. unsigned long flags;
  545. u8 ctrl;
  546. host = mmc_priv(mmc);
  547. spin_lock_irqsave(&host->lock, flags);
  548. /*
  549. * Reset the chip on each power off.
  550. * Should clear out any weird states.
  551. */
  552. if (ios->power_mode == MMC_POWER_OFF) {
  553. writel(0, host->ioaddr + SDHCI_SIGNAL_ENABLE);
  554. sdhci_init(host);
  555. }
  556. sdhci_set_clock(host, ios->clock);
  557. if (ios->power_mode == MMC_POWER_OFF)
  558. sdhci_set_power(host, -1);
  559. else
  560. sdhci_set_power(host, ios->vdd);
  561. ctrl = readb(host->ioaddr + SDHCI_HOST_CONTROL);
  562. if (ios->bus_width == MMC_BUS_WIDTH_4)
  563. ctrl |= SDHCI_CTRL_4BITBUS;
  564. else
  565. ctrl &= ~SDHCI_CTRL_4BITBUS;
  566. writeb(ctrl, host->ioaddr + SDHCI_HOST_CONTROL);
  567. spin_unlock_irqrestore(&host->lock, flags);
  568. }
  569. static int sdhci_get_ro(struct mmc_host *mmc)
  570. {
  571. struct sdhci_host *host;
  572. unsigned long flags;
  573. int present;
  574. host = mmc_priv(mmc);
  575. spin_lock_irqsave(&host->lock, flags);
  576. present = readl(host->ioaddr + SDHCI_PRESENT_STATE);
  577. spin_unlock_irqrestore(&host->lock, flags);
  578. return !(present & SDHCI_WRITE_PROTECT);
  579. }
  580. static struct mmc_host_ops sdhci_ops = {
  581. .request = sdhci_request,
  582. .set_ios = sdhci_set_ios,
  583. .get_ro = sdhci_get_ro,
  584. };
  585. /*****************************************************************************\
  586. * *
  587. * Tasklets *
  588. * *
  589. \*****************************************************************************/
  590. static void sdhci_tasklet_card(unsigned long param)
  591. {
  592. struct sdhci_host *host;
  593. unsigned long flags;
  594. host = (struct sdhci_host*)param;
  595. spin_lock_irqsave(&host->lock, flags);
  596. if (!(readl(host->ioaddr + SDHCI_PRESENT_STATE) & SDHCI_CARD_PRESENT)) {
  597. if (host->mrq) {
  598. printk(KERN_ERR "%s: Card removed during transfer!\n",
  599. mmc_hostname(host->mmc));
  600. printk(KERN_ERR "%s: Resetting controller.\n",
  601. mmc_hostname(host->mmc));
  602. sdhci_reset(host, SDHCI_RESET_CMD);
  603. sdhci_reset(host, SDHCI_RESET_DATA);
  604. host->mrq->cmd->error = MMC_ERR_FAILED;
  605. tasklet_schedule(&host->finish_tasklet);
  606. }
  607. }
  608. spin_unlock_irqrestore(&host->lock, flags);
  609. mmc_detect_change(host->mmc, msecs_to_jiffies(500));
  610. }
  611. static void sdhci_tasklet_finish(unsigned long param)
  612. {
  613. struct sdhci_host *host;
  614. unsigned long flags;
  615. struct mmc_request *mrq;
  616. host = (struct sdhci_host*)param;
  617. spin_lock_irqsave(&host->lock, flags);
  618. del_timer(&host->timer);
  619. mrq = host->mrq;
  620. DBG("Ending request, cmd (%x)\n", mrq->cmd->opcode);
  621. /*
  622. * The controller needs a reset of internal state machines
  623. * upon error conditions.
  624. */
  625. if ((mrq->cmd->error != MMC_ERR_NONE) ||
  626. (mrq->data && ((mrq->data->error != MMC_ERR_NONE) ||
  627. (mrq->data->stop && (mrq->data->stop->error != MMC_ERR_NONE))))) {
  628. sdhci_reset(host, SDHCI_RESET_CMD);
  629. sdhci_reset(host, SDHCI_RESET_DATA);
  630. }
  631. host->mrq = NULL;
  632. host->cmd = NULL;
  633. host->data = NULL;
  634. sdhci_deactivate_led(host);
  635. spin_unlock_irqrestore(&host->lock, flags);
  636. mmc_request_done(host->mmc, mrq);
  637. }
  638. static void sdhci_timeout_timer(unsigned long data)
  639. {
  640. struct sdhci_host *host;
  641. unsigned long flags;
  642. host = (struct sdhci_host*)data;
  643. spin_lock_irqsave(&host->lock, flags);
  644. if (host->mrq) {
  645. printk(KERN_ERR "%s: Timeout waiting for hardware interrupt. "
  646. "Please report this to " BUGMAIL ".\n",
  647. mmc_hostname(host->mmc));
  648. sdhci_dumpregs(host);
  649. if (host->data) {
  650. host->data->error = MMC_ERR_TIMEOUT;
  651. sdhci_finish_data(host);
  652. } else {
  653. if (host->cmd)
  654. host->cmd->error = MMC_ERR_TIMEOUT;
  655. else
  656. host->mrq->cmd->error = MMC_ERR_TIMEOUT;
  657. tasklet_schedule(&host->finish_tasklet);
  658. }
  659. }
  660. spin_unlock_irqrestore(&host->lock, flags);
  661. }
  662. /*****************************************************************************\
  663. * *
  664. * Interrupt handling *
  665. * *
  666. \*****************************************************************************/
  667. static void sdhci_cmd_irq(struct sdhci_host *host, u32 intmask)
  668. {
  669. BUG_ON(intmask == 0);
  670. if (!host->cmd) {
  671. printk(KERN_ERR "%s: Got command interrupt even though no "
  672. "command operation was in progress.\n",
  673. mmc_hostname(host->mmc));
  674. printk(KERN_ERR "%s: Please report this to " BUGMAIL ".\n",
  675. mmc_hostname(host->mmc));
  676. sdhci_dumpregs(host);
  677. return;
  678. }
  679. if (intmask & SDHCI_INT_RESPONSE)
  680. sdhci_finish_command(host);
  681. else {
  682. if (intmask & SDHCI_INT_TIMEOUT)
  683. host->cmd->error = MMC_ERR_TIMEOUT;
  684. else if (intmask & SDHCI_INT_CRC)
  685. host->cmd->error = MMC_ERR_BADCRC;
  686. else if (intmask & (SDHCI_INT_END_BIT | SDHCI_INT_INDEX))
  687. host->cmd->error = MMC_ERR_FAILED;
  688. else
  689. host->cmd->error = MMC_ERR_INVALID;
  690. tasklet_schedule(&host->finish_tasklet);
  691. }
  692. }
  693. static void sdhci_data_irq(struct sdhci_host *host, u32 intmask)
  694. {
  695. BUG_ON(intmask == 0);
  696. if (!host->data) {
  697. /*
  698. * A data end interrupt is sent together with the response
  699. * for the stop command.
  700. */
  701. if (intmask & SDHCI_INT_DATA_END)
  702. return;
  703. printk(KERN_ERR "%s: Got data interrupt even though no "
  704. "data operation was in progress.\n",
  705. mmc_hostname(host->mmc));
  706. printk(KERN_ERR "%s: Please report this to " BUGMAIL ".\n",
  707. mmc_hostname(host->mmc));
  708. sdhci_dumpregs(host);
  709. return;
  710. }
  711. if (intmask & SDHCI_INT_DATA_TIMEOUT)
  712. host->data->error = MMC_ERR_TIMEOUT;
  713. else if (intmask & SDHCI_INT_DATA_CRC)
  714. host->data->error = MMC_ERR_BADCRC;
  715. else if (intmask & SDHCI_INT_DATA_END_BIT)
  716. host->data->error = MMC_ERR_FAILED;
  717. if (host->data->error != MMC_ERR_NONE)
  718. sdhci_finish_data(host);
  719. else {
  720. if (intmask & (SDHCI_INT_DATA_AVAIL | SDHCI_INT_SPACE_AVAIL))
  721. sdhci_transfer_pio(host);
  722. if (intmask & SDHCI_INT_DATA_END)
  723. sdhci_finish_data(host);
  724. }
  725. }
  726. static irqreturn_t sdhci_irq(int irq, void *dev_id, struct pt_regs *regs)
  727. {
  728. irqreturn_t result;
  729. struct sdhci_host* host = dev_id;
  730. u32 intmask;
  731. spin_lock(&host->lock);
  732. intmask = readl(host->ioaddr + SDHCI_INT_STATUS);
  733. if (!intmask) {
  734. result = IRQ_NONE;
  735. goto out;
  736. }
  737. DBG("*** %s got interrupt: 0x%08x\n", host->slot_descr, intmask);
  738. if (intmask & (SDHCI_INT_CARD_INSERT | SDHCI_INT_CARD_REMOVE)) {
  739. writel(intmask & (SDHCI_INT_CARD_INSERT | SDHCI_INT_CARD_REMOVE),
  740. host->ioaddr + SDHCI_INT_STATUS);
  741. tasklet_schedule(&host->card_tasklet);
  742. }
  743. intmask &= ~(SDHCI_INT_CARD_INSERT | SDHCI_INT_CARD_REMOVE);
  744. if (intmask & SDHCI_INT_CMD_MASK) {
  745. writel(intmask & SDHCI_INT_CMD_MASK,
  746. host->ioaddr + SDHCI_INT_STATUS);
  747. sdhci_cmd_irq(host, intmask & SDHCI_INT_CMD_MASK);
  748. }
  749. if (intmask & SDHCI_INT_DATA_MASK) {
  750. writel(intmask & SDHCI_INT_DATA_MASK,
  751. host->ioaddr + SDHCI_INT_STATUS);
  752. sdhci_data_irq(host, intmask & SDHCI_INT_DATA_MASK);
  753. }
  754. intmask &= ~(SDHCI_INT_CMD_MASK | SDHCI_INT_DATA_MASK);
  755. if (intmask & SDHCI_INT_BUS_POWER) {
  756. printk(KERN_ERR "%s: Card is consuming too much power!\n",
  757. mmc_hostname(host->mmc));
  758. writel(SDHCI_INT_BUS_POWER, host->ioaddr + SDHCI_INT_STATUS);
  759. }
  760. intmask &= SDHCI_INT_BUS_POWER;
  761. if (intmask) {
  762. printk(KERN_ERR "%s: Unexpected interrupt 0x%08x. Please "
  763. "report this to " BUGMAIL ".\n",
  764. mmc_hostname(host->mmc), intmask);
  765. sdhci_dumpregs(host);
  766. writel(intmask, host->ioaddr + SDHCI_INT_STATUS);
  767. }
  768. result = IRQ_HANDLED;
  769. out:
  770. spin_unlock(&host->lock);
  771. return result;
  772. }
  773. /*****************************************************************************\
  774. * *
  775. * Suspend/resume *
  776. * *
  777. \*****************************************************************************/
  778. #ifdef CONFIG_PM
  779. static int sdhci_suspend (struct pci_dev *pdev, pm_message_t state)
  780. {
  781. struct sdhci_chip *chip;
  782. int i, ret;
  783. chip = pci_get_drvdata(pdev);
  784. if (!chip)
  785. return 0;
  786. DBG("Suspending...\n");
  787. for (i = 0;i < chip->num_slots;i++) {
  788. if (!chip->hosts[i])
  789. continue;
  790. ret = mmc_suspend_host(chip->hosts[i]->mmc, state);
  791. if (ret) {
  792. for (i--;i >= 0;i--)
  793. mmc_resume_host(chip->hosts[i]->mmc);
  794. return ret;
  795. }
  796. }
  797. pci_save_state(pdev);
  798. pci_enable_wake(pdev, pci_choose_state(pdev, state), 0);
  799. pci_disable_device(pdev);
  800. pci_set_power_state(pdev, pci_choose_state(pdev, state));
  801. return 0;
  802. }
  803. static int sdhci_resume (struct pci_dev *pdev)
  804. {
  805. struct sdhci_chip *chip;
  806. int i, ret;
  807. chip = pci_get_drvdata(pdev);
  808. if (!chip)
  809. return 0;
  810. DBG("Resuming...\n");
  811. pci_set_power_state(pdev, PCI_D0);
  812. pci_restore_state(pdev);
  813. pci_enable_device(pdev);
  814. for (i = 0;i < chip->num_slots;i++) {
  815. if (!chip->hosts[i])
  816. continue;
  817. if (chip->hosts[i]->flags & SDHCI_USE_DMA)
  818. pci_set_master(pdev);
  819. sdhci_init(chip->hosts[i]);
  820. ret = mmc_resume_host(chip->hosts[i]->mmc);
  821. if (ret)
  822. return ret;
  823. }
  824. return 0;
  825. }
  826. #else /* CONFIG_PM */
  827. #define sdhci_suspend NULL
  828. #define sdhci_resume NULL
  829. #endif /* CONFIG_PM */
  830. /*****************************************************************************\
  831. * *
  832. * Device probing/removal *
  833. * *
  834. \*****************************************************************************/
  835. static int __devinit sdhci_probe_slot(struct pci_dev *pdev, int slot)
  836. {
  837. int ret;
  838. struct sdhci_chip *chip;
  839. struct mmc_host *mmc;
  840. struct sdhci_host *host;
  841. u8 first_bar;
  842. unsigned int caps;
  843. chip = pci_get_drvdata(pdev);
  844. BUG_ON(!chip);
  845. ret = pci_read_config_byte(pdev, PCI_SLOT_INFO, &first_bar);
  846. if (ret)
  847. return ret;
  848. first_bar &= PCI_SLOT_INFO_FIRST_BAR_MASK;
  849. if (first_bar > 5) {
  850. printk(KERN_ERR DRIVER_NAME ": Invalid first BAR. Aborting.\n");
  851. return -ENODEV;
  852. }
  853. if (!(pci_resource_flags(pdev, first_bar + slot) & IORESOURCE_MEM)) {
  854. printk(KERN_ERR DRIVER_NAME ": BAR is not iomem. Aborting.\n");
  855. return -ENODEV;
  856. }
  857. if (pci_resource_len(pdev, first_bar + slot) != 0x100) {
  858. printk(KERN_ERR DRIVER_NAME ": Invalid iomem size. Aborting.\n");
  859. return -ENODEV;
  860. }
  861. mmc = mmc_alloc_host(sizeof(struct sdhci_host), &pdev->dev);
  862. if (!mmc)
  863. return -ENOMEM;
  864. host = mmc_priv(mmc);
  865. host->mmc = mmc;
  866. host->bar = first_bar + slot;
  867. host->addr = pci_resource_start(pdev, host->bar);
  868. host->irq = pdev->irq;
  869. DBG("slot %d at 0x%08lx, irq %d\n", slot, host->addr, host->irq);
  870. snprintf(host->slot_descr, 20, "sdhci:slot%d", slot);
  871. ret = pci_request_region(pdev, host->bar, host->slot_descr);
  872. if (ret)
  873. goto free;
  874. host->ioaddr = ioremap_nocache(host->addr,
  875. pci_resource_len(pdev, host->bar));
  876. if (!host->ioaddr) {
  877. ret = -ENOMEM;
  878. goto release;
  879. }
  880. caps = readl(host->ioaddr + SDHCI_CAPABILITIES);
  881. if ((caps & SDHCI_CAN_DO_DMA) && ((pdev->class & 0x0000FF) == 0x01))
  882. host->flags |= SDHCI_USE_DMA;
  883. if (host->flags & SDHCI_USE_DMA) {
  884. if (pci_set_dma_mask(pdev, DMA_32BIT_MASK)) {
  885. printk(KERN_WARNING "%s: No suitable DMA available. "
  886. "Falling back to PIO.\n", host->slot_descr);
  887. host->flags &= ~SDHCI_USE_DMA;
  888. }
  889. }
  890. if (host->flags & SDHCI_USE_DMA)
  891. pci_set_master(pdev);
  892. else /* XXX: Hack to get MMC layer to avoid highmem */
  893. pdev->dma_mask = 0;
  894. host->max_clk =
  895. (caps & SDHCI_CLOCK_BASE_MASK) >> SDHCI_CLOCK_BASE_SHIFT;
  896. if (host->max_clk == 0) {
  897. printk(KERN_ERR "%s: Hardware doesn't specify base clock "
  898. "frequency.\n", host->slot_descr);
  899. ret = -ENODEV;
  900. goto unmap;
  901. }
  902. host->max_clk *= 1000000;
  903. host->timeout_clk =
  904. (caps & SDHCI_TIMEOUT_CLK_MASK) >> SDHCI_TIMEOUT_CLK_SHIFT;
  905. if (host->timeout_clk == 0) {
  906. printk(KERN_ERR "%s: Hardware doesn't specify timeout clock "
  907. "frequency.\n", host->slot_descr);
  908. ret = -ENODEV;
  909. goto unmap;
  910. }
  911. if (caps & SDHCI_TIMEOUT_CLK_UNIT)
  912. host->timeout_clk *= 1000;
  913. /*
  914. * Set host parameters.
  915. */
  916. mmc->ops = &sdhci_ops;
  917. mmc->f_min = host->max_clk / 256;
  918. mmc->f_max = host->max_clk;
  919. mmc->caps = MMC_CAP_4_BIT_DATA;
  920. mmc->ocr_avail = 0;
  921. if (caps & SDHCI_CAN_VDD_330)
  922. mmc->ocr_avail |= MMC_VDD_32_33|MMC_VDD_33_34;
  923. else if (caps & SDHCI_CAN_VDD_300)
  924. mmc->ocr_avail |= MMC_VDD_29_30|MMC_VDD_30_31;
  925. else if (caps & SDHCI_CAN_VDD_180)
  926. mmc->ocr_avail |= MMC_VDD_17_18|MMC_VDD_18_19;
  927. if (mmc->ocr_avail == 0) {
  928. printk(KERN_ERR "%s: Hardware doesn't report any "
  929. "support voltages.\n", host->slot_descr);
  930. ret = -ENODEV;
  931. goto unmap;
  932. }
  933. spin_lock_init(&host->lock);
  934. /*
  935. * Maximum number of segments. Hardware cannot do scatter lists.
  936. */
  937. if (host->flags & SDHCI_USE_DMA)
  938. mmc->max_hw_segs = 1;
  939. else
  940. mmc->max_hw_segs = 16;
  941. mmc->max_phys_segs = 16;
  942. /*
  943. * Maximum number of sectors in one transfer. Limited by DMA boundary
  944. * size (512KiB), which means (512 KiB/512=) 1024 entries.
  945. */
  946. mmc->max_sectors = 1024;
  947. /*
  948. * Maximum segment size. Could be one segment with the maximum number
  949. * of sectors.
  950. */
  951. mmc->max_seg_size = mmc->max_sectors * 512;
  952. /*
  953. * Init tasklets.
  954. */
  955. tasklet_init(&host->card_tasklet,
  956. sdhci_tasklet_card, (unsigned long)host);
  957. tasklet_init(&host->finish_tasklet,
  958. sdhci_tasklet_finish, (unsigned long)host);
  959. setup_timer(&host->timer, sdhci_timeout_timer, (long)host);
  960. ret = request_irq(host->irq, sdhci_irq, SA_SHIRQ,
  961. host->slot_descr, host);
  962. if (ret)
  963. goto untasklet;
  964. sdhci_init(host);
  965. #ifdef CONFIG_MMC_DEBUG
  966. sdhci_dumpregs(host);
  967. #endif
  968. host->chip = chip;
  969. chip->hosts[slot] = host;
  970. mmc_add_host(mmc);
  971. printk(KERN_INFO "%s: SDHCI at 0x%08lx irq %d %s\n", mmc_hostname(mmc),
  972. host->addr, host->irq,
  973. (host->flags & SDHCI_USE_DMA)?"DMA":"PIO");
  974. return 0;
  975. untasklet:
  976. tasklet_kill(&host->card_tasklet);
  977. tasklet_kill(&host->finish_tasklet);
  978. unmap:
  979. iounmap(host->ioaddr);
  980. release:
  981. pci_release_region(pdev, host->bar);
  982. free:
  983. mmc_free_host(mmc);
  984. return ret;
  985. }
  986. static void sdhci_remove_slot(struct pci_dev *pdev, int slot)
  987. {
  988. struct sdhci_chip *chip;
  989. struct mmc_host *mmc;
  990. struct sdhci_host *host;
  991. chip = pci_get_drvdata(pdev);
  992. host = chip->hosts[slot];
  993. mmc = host->mmc;
  994. chip->hosts[slot] = NULL;
  995. mmc_remove_host(mmc);
  996. sdhci_reset(host, SDHCI_RESET_ALL);
  997. free_irq(host->irq, host);
  998. del_timer_sync(&host->timer);
  999. tasklet_kill(&host->card_tasklet);
  1000. tasklet_kill(&host->finish_tasklet);
  1001. iounmap(host->ioaddr);
  1002. pci_release_region(pdev, host->bar);
  1003. mmc_free_host(mmc);
  1004. }
  1005. static int __devinit sdhci_probe(struct pci_dev *pdev,
  1006. const struct pci_device_id *ent)
  1007. {
  1008. int ret, i;
  1009. u8 slots, rev;
  1010. struct sdhci_chip *chip;
  1011. BUG_ON(pdev == NULL);
  1012. BUG_ON(ent == NULL);
  1013. pci_read_config_byte(pdev, PCI_CLASS_REVISION, &rev);
  1014. printk(KERN_INFO DRIVER_NAME
  1015. ": SDHCI controller found at %s [%04x:%04x] (rev %x)\n",
  1016. pci_name(pdev), (int)pdev->vendor, (int)pdev->device,
  1017. (int)rev);
  1018. ret = pci_read_config_byte(pdev, PCI_SLOT_INFO, &slots);
  1019. if (ret)
  1020. return ret;
  1021. slots = PCI_SLOT_INFO_SLOTS(slots) + 1;
  1022. DBG("found %d slot(s)\n", slots);
  1023. if (slots == 0)
  1024. return -ENODEV;
  1025. ret = pci_enable_device(pdev);
  1026. if (ret)
  1027. return ret;
  1028. chip = kzalloc(sizeof(struct sdhci_chip) +
  1029. sizeof(struct sdhci_host*) * slots, GFP_KERNEL);
  1030. if (!chip) {
  1031. ret = -ENOMEM;
  1032. goto err;
  1033. }
  1034. chip->pdev = pdev;
  1035. chip->num_slots = slots;
  1036. pci_set_drvdata(pdev, chip);
  1037. for (i = 0;i < slots;i++) {
  1038. ret = sdhci_probe_slot(pdev, i);
  1039. if (ret) {
  1040. for (i--;i >= 0;i--)
  1041. sdhci_remove_slot(pdev, i);
  1042. goto free;
  1043. }
  1044. }
  1045. return 0;
  1046. free:
  1047. pci_set_drvdata(pdev, NULL);
  1048. kfree(chip);
  1049. err:
  1050. pci_disable_device(pdev);
  1051. return ret;
  1052. }
  1053. static void __devexit sdhci_remove(struct pci_dev *pdev)
  1054. {
  1055. int i;
  1056. struct sdhci_chip *chip;
  1057. chip = pci_get_drvdata(pdev);
  1058. if (chip) {
  1059. for (i = 0;i < chip->num_slots;i++)
  1060. sdhci_remove_slot(pdev, i);
  1061. pci_set_drvdata(pdev, NULL);
  1062. kfree(chip);
  1063. }
  1064. pci_disable_device(pdev);
  1065. }
  1066. static struct pci_driver sdhci_driver = {
  1067. .name = DRIVER_NAME,
  1068. .id_table = pci_ids,
  1069. .probe = sdhci_probe,
  1070. .remove = __devexit_p(sdhci_remove),
  1071. .suspend = sdhci_suspend,
  1072. .resume = sdhci_resume,
  1073. };
  1074. /*****************************************************************************\
  1075. * *
  1076. * Driver init/exit *
  1077. * *
  1078. \*****************************************************************************/
  1079. static int __init sdhci_drv_init(void)
  1080. {
  1081. printk(KERN_INFO DRIVER_NAME
  1082. ": Secure Digital Host Controller Interface driver, "
  1083. DRIVER_VERSION "\n");
  1084. printk(KERN_INFO DRIVER_NAME ": Copyright(c) Pierre Ossman\n");
  1085. return pci_register_driver(&sdhci_driver);
  1086. }
  1087. static void __exit sdhci_drv_exit(void)
  1088. {
  1089. DBG("Exiting\n");
  1090. pci_unregister_driver(&sdhci_driver);
  1091. }
  1092. module_init(sdhci_drv_init);
  1093. module_exit(sdhci_drv_exit);
  1094. MODULE_AUTHOR("Pierre Ossman <drzeus@drzeus.cx>");
  1095. MODULE_DESCRIPTION("Secure Digital Host Controller Interface driver");
  1096. MODULE_VERSION(DRIVER_VERSION);
  1097. MODULE_LICENSE("GPL");