neponset.c 9.0 KB

123456789101112131415161718192021222324252627282930313233343536373839404142434445464748495051525354555657585960616263646566676869707172737475767778798081828384858687888990919293949596979899100101102103104105106107108109110111112113114115116117118119120121122123124125126127128129130131132133134135136137138139140141142143144145146147148149150151152153154155156157158159160161162163164165166167168169170171172173174175176177178179180181182183184185186187188189190191192193194195196197198199200201202203204205206207208209210211212213214215216217218219220221222223224225226227228229230231232233234235236237238239240241242243244245246247248249250251252253254255256257258259260261262263264265266267268269270271272273274275276277278279280281282283284285286287288289290291292293294295296297298299300301302303304305306307308309310311312313314315316317318319320321322323324325326327328329330331332333334335336337338339340341342343344345346347348349350351352353354355356357358359360361362363364365366367368369370371372373374375376377378379380381382383384385
  1. /*
  2. * linux/arch/arm/mach-sa1100/neponset.c
  3. */
  4. #include <linux/err.h>
  5. #include <linux/init.h>
  6. #include <linux/ioport.h>
  7. #include <linux/irq.h>
  8. #include <linux/kernel.h>
  9. #include <linux/module.h>
  10. #include <linux/platform_device.h>
  11. #include <linux/pm.h>
  12. #include <linux/serial_core.h>
  13. #include <linux/slab.h>
  14. #include <asm/mach-types.h>
  15. #include <asm/mach/map.h>
  16. #include <asm/mach/serial_sa1100.h>
  17. #include <asm/hardware/sa1111.h>
  18. #include <asm/sizes.h>
  19. #include <mach/hardware.h>
  20. #include <mach/assabet.h>
  21. #include <mach/neponset.h>
  22. #define NEP_IRQ_SMC91X 0
  23. #define NEP_IRQ_USAR 1
  24. #define NEP_IRQ_SA1111 2
  25. #define NEP_IRQ_NR 3
  26. extern void sa1110_mb_disable(void);
  27. struct neponset_drvdata {
  28. struct platform_device *sa1111;
  29. struct platform_device *smc91x;
  30. unsigned irq_base;
  31. #ifdef CONFIG_PM_SLEEP
  32. u32 ncr0;
  33. u32 mdm_ctl_0;
  34. #endif
  35. };
  36. void neponset_ncr_frob(unsigned int mask, unsigned int val)
  37. {
  38. unsigned long flags;
  39. local_irq_save(flags);
  40. NCR_0 = (NCR_0 & ~mask) | val;
  41. local_irq_restore(flags);
  42. }
  43. static void neponset_set_mctrl(struct uart_port *port, u_int mctrl)
  44. {
  45. u_int mdm_ctl0 = MDM_CTL_0;
  46. if (port->mapbase == _Ser1UTCR0) {
  47. if (mctrl & TIOCM_RTS)
  48. mdm_ctl0 &= ~MDM_CTL0_RTS2;
  49. else
  50. mdm_ctl0 |= MDM_CTL0_RTS2;
  51. if (mctrl & TIOCM_DTR)
  52. mdm_ctl0 &= ~MDM_CTL0_DTR2;
  53. else
  54. mdm_ctl0 |= MDM_CTL0_DTR2;
  55. } else if (port->mapbase == _Ser3UTCR0) {
  56. if (mctrl & TIOCM_RTS)
  57. mdm_ctl0 &= ~MDM_CTL0_RTS1;
  58. else
  59. mdm_ctl0 |= MDM_CTL0_RTS1;
  60. if (mctrl & TIOCM_DTR)
  61. mdm_ctl0 &= ~MDM_CTL0_DTR1;
  62. else
  63. mdm_ctl0 |= MDM_CTL0_DTR1;
  64. }
  65. MDM_CTL_0 = mdm_ctl0;
  66. }
  67. static u_int neponset_get_mctrl(struct uart_port *port)
  68. {
  69. u_int ret = TIOCM_CD | TIOCM_CTS | TIOCM_DSR;
  70. u_int mdm_ctl1 = MDM_CTL_1;
  71. if (port->mapbase == _Ser1UTCR0) {
  72. if (mdm_ctl1 & MDM_CTL1_DCD2)
  73. ret &= ~TIOCM_CD;
  74. if (mdm_ctl1 & MDM_CTL1_CTS2)
  75. ret &= ~TIOCM_CTS;
  76. if (mdm_ctl1 & MDM_CTL1_DSR2)
  77. ret &= ~TIOCM_DSR;
  78. } else if (port->mapbase == _Ser3UTCR0) {
  79. if (mdm_ctl1 & MDM_CTL1_DCD1)
  80. ret &= ~TIOCM_CD;
  81. if (mdm_ctl1 & MDM_CTL1_CTS1)
  82. ret &= ~TIOCM_CTS;
  83. if (mdm_ctl1 & MDM_CTL1_DSR1)
  84. ret &= ~TIOCM_DSR;
  85. }
  86. return ret;
  87. }
  88. static struct sa1100_port_fns neponset_port_fns __devinitdata = {
  89. .set_mctrl = neponset_set_mctrl,
  90. .get_mctrl = neponset_get_mctrl,
  91. };
  92. /*
  93. * Install handler for Neponset IRQ. Note that we have to loop here
  94. * since the ETHERNET and USAR IRQs are level based, and we need to
  95. * ensure that the IRQ signal is deasserted before returning. This
  96. * is rather unfortunate.
  97. */
  98. static void neponset_irq_handler(unsigned int irq, struct irq_desc *desc)
  99. {
  100. struct neponset_drvdata *d = irq_desc_get_handler_data(desc);
  101. unsigned int irr;
  102. while (1) {
  103. /*
  104. * Acknowledge the parent IRQ.
  105. */
  106. desc->irq_data.chip->irq_ack(&desc->irq_data);
  107. /*
  108. * Read the interrupt reason register. Let's have all
  109. * active IRQ bits high. Note: there is a typo in the
  110. * Neponset user's guide for the SA1111 IRR level.
  111. */
  112. irr = IRR ^ (IRR_ETHERNET | IRR_USAR);
  113. if ((irr & (IRR_ETHERNET | IRR_USAR | IRR_SA1111)) == 0)
  114. break;
  115. /*
  116. * Since there is no individual mask, we have to
  117. * mask the parent IRQ. This is safe, since we'll
  118. * recheck the register for any pending IRQs.
  119. */
  120. if (irr & (IRR_ETHERNET | IRR_USAR)) {
  121. desc->irq_data.chip->irq_mask(&desc->irq_data);
  122. /*
  123. * Ack the interrupt now to prevent re-entering
  124. * this neponset handler. Again, this is safe
  125. * since we'll check the IRR register prior to
  126. * leaving.
  127. */
  128. desc->irq_data.chip->irq_ack(&desc->irq_data);
  129. if (irr & IRR_ETHERNET)
  130. generic_handle_irq(d->irq_base + NEP_IRQ_SMC91X);
  131. if (irr & IRR_USAR)
  132. generic_handle_irq(d->irq_base + NEP_IRQ_USAR);
  133. desc->irq_data.chip->irq_unmask(&desc->irq_data);
  134. }
  135. if (irr & IRR_SA1111)
  136. generic_handle_irq(d->irq_base + NEP_IRQ_SA1111);
  137. }
  138. }
  139. /* Yes, we really do not have any kind of masking or unmasking */
  140. static void nochip_noop(struct irq_data *irq)
  141. {
  142. }
  143. static struct irq_chip nochip = {
  144. .name = "neponset",
  145. .irq_ack = nochip_noop,
  146. .irq_mask = nochip_noop,
  147. .irq_unmask = nochip_noop,
  148. };
  149. static struct sa1111_platform_data sa1111_info = {
  150. .irq_base = IRQ_BOARD_END,
  151. };
  152. static int __devinit neponset_probe(struct platform_device *dev)
  153. {
  154. struct neponset_drvdata *d;
  155. struct resource *sa1111_res, *smc91x_res;
  156. struct resource sa1111_resources[] = {
  157. DEFINE_RES_MEM(0x40000000, SZ_8K),
  158. { .flags = IORESOURCE_IRQ },
  159. };
  160. struct platform_device_info sa1111_devinfo = {
  161. .parent = &dev->dev,
  162. .name = "sa1111",
  163. .id = 0,
  164. .res = sa1111_resources,
  165. .num_res = ARRAY_SIZE(sa1111_resources),
  166. .data = &sa1111_info,
  167. .size_data = sizeof(sa1111_info),
  168. .dma_mask = 0xffffffffUL,
  169. };
  170. struct resource smc91x_resources[] = {
  171. DEFINE_RES_MEM_NAMED(SA1100_CS3_PHYS,
  172. 0x02000000, "smc91x-regs"),
  173. DEFINE_RES_MEM_NAMED(SA1100_CS3_PHYS + 0x02000000,
  174. 0x02000000, "smc91x-attrib"),
  175. { .flags = IORESOURCE_IRQ },
  176. };
  177. struct platform_device_info smc91x_devinfo = {
  178. .parent = &dev->dev,
  179. .name = "smc91x",
  180. .id = 0,
  181. .res = smc91x_resources,
  182. .num_res = ARRAY_SIZE(smc91x_resources),
  183. };
  184. int ret, irq;
  185. irq = ret = platform_get_irq(dev, 0);
  186. if (ret < 0)
  187. goto err_alloc;
  188. smc91x_res = platform_get_resource(dev, IORESOURCE_MEM, 1);
  189. sa1111_res = platform_get_resource(dev, IORESOURCE_MEM, 2);
  190. if (!smc91x_res || !sa1111_res) {
  191. ret = -ENXIO;
  192. goto err_alloc;
  193. }
  194. if (WHOAMI != 0x11) {
  195. dev_warn(&dev->dev, "Neponset board detected, but wrong ID: %02x\n",
  196. WHOAMI);
  197. ret = -ENODEV;
  198. goto err_alloc;
  199. }
  200. d = kzalloc(sizeof(*d), GFP_KERNEL);
  201. if (!d) {
  202. ret = -ENOMEM;
  203. goto err_alloc;
  204. }
  205. ret = irq_alloc_descs(-1, IRQ_BOARD_START, NEP_IRQ_NR, -1);
  206. if (ret <= 0) {
  207. dev_err(&dev->dev, "unable to allocate %u irqs: %d\n",
  208. NEP_IRQ_NR, ret);
  209. if (ret == 0)
  210. ret = -ENOMEM;
  211. goto err_irq_alloc;
  212. }
  213. d->irq_base = ret;
  214. irq_set_chip_and_handler(d->irq_base + NEP_IRQ_SMC91X, &nochip,
  215. handle_simple_irq);
  216. set_irq_flags(d->irq_base + NEP_IRQ_SMC91X, IRQF_VALID | IRQF_PROBE);
  217. irq_set_chip_and_handler(d->irq_base + NEP_IRQ_USAR, &nochip,
  218. handle_simple_irq);
  219. set_irq_flags(d->irq_base + NEP_IRQ_USAR, IRQF_VALID | IRQF_PROBE);
  220. irq_set_chip(d->irq_base + NEP_IRQ_SA1111, &nochip);
  221. irq_set_irq_type(irq, IRQ_TYPE_EDGE_RISING);
  222. irq_set_handler_data(irq, d);
  223. irq_set_chained_handler(irq, neponset_irq_handler);
  224. /*
  225. * We would set IRQ_GPIO25 to be a wake-up IRQ, but unfortunately
  226. * something on the Neponset activates this IRQ on sleep (eth?)
  227. */
  228. #if 0
  229. enable_irq_wake(irq);
  230. #endif
  231. dev_info(&dev->dev, "Neponset daughter board, providing IRQ%u-%u\n",
  232. d->irq_base, d->irq_base + NEP_IRQ_NR - 1);
  233. sa1100_register_uart_fns(&neponset_port_fns);
  234. /* Ensure that the memory bus request/grant signals are setup */
  235. sa1110_mb_disable();
  236. /* Disable GPIO 0/1 drivers so the buttons work on the Assabet */
  237. NCR_0 = NCR_GP01_OFF;
  238. sa1111_resources[0].parent = sa1111_res;
  239. sa1111_resources[1].start = d->irq_base + NEP_IRQ_SA1111;
  240. sa1111_resources[1].end = d->irq_base + NEP_IRQ_SA1111;
  241. d->sa1111 = platform_device_register_full(&sa1111_devinfo);
  242. smc91x_resources[0].parent = smc91x_res;
  243. smc91x_resources[1].parent = smc91x_res;
  244. smc91x_resources[2].start = d->irq_base + NEP_IRQ_SMC91X;
  245. smc91x_resources[2].end = d->irq_base + NEP_IRQ_SMC91X;
  246. d->smc91x = platform_device_register_full(&smc91x_devinfo);
  247. platform_set_drvdata(dev, d);
  248. return 0;
  249. err_irq_alloc:
  250. kfree(d);
  251. err_alloc:
  252. return ret;
  253. }
  254. static int __devexit neponset_remove(struct platform_device *dev)
  255. {
  256. struct neponset_drvdata *d = platform_get_drvdata(dev);
  257. int irq = platform_get_irq(dev, 0);
  258. if (!IS_ERR(d->sa1111))
  259. platform_device_unregister(d->sa1111);
  260. if (!IS_ERR(d->smc91x))
  261. platform_device_unregister(d->smc91x);
  262. irq_set_chained_handler(irq, NULL);
  263. irq_free_descs(d->irq_base, NEP_IRQ_NR);
  264. kfree(d);
  265. return 0;
  266. }
  267. #ifdef CONFIG_PM_SLEEP
  268. static int neponset_suspend(struct device *dev)
  269. {
  270. struct neponset_drvdata *d = dev_get_drvdata(dev);
  271. d->ncr0 = NCR_0;
  272. d->mdm_ctl_0 = MDM_CTL_0;
  273. return 0;
  274. }
  275. static int neponset_resume(struct device *dev)
  276. {
  277. struct neponset_drvdata *d = dev_get_drvdata(dev);
  278. NCR_0 = d->ncr0;
  279. MDM_CTL_0 = d->mdm_ctl_0;
  280. return 0;
  281. }
  282. static const struct dev_pm_ops neponset_pm_ops = {
  283. .suspend_noirq = neponset_suspend,
  284. .resume_noirq = neponset_resume,
  285. .freeze_noirq = neponset_suspend,
  286. .restore_noirq = neponset_resume,
  287. };
  288. #define PM_OPS &neponset_pm_ops
  289. #else
  290. #define PM_OPS NULL
  291. #endif
  292. static struct platform_driver neponset_device_driver = {
  293. .probe = neponset_probe,
  294. .remove = __devexit_p(neponset_remove),
  295. .driver = {
  296. .name = "neponset",
  297. .owner = THIS_MODULE,
  298. .pm = PM_OPS,
  299. },
  300. };
  301. static int __init neponset_init(void)
  302. {
  303. return platform_driver_register(&neponset_device_driver);
  304. }
  305. subsys_initcall(neponset_init);
  306. static struct map_desc neponset_io_desc[] __initdata = {
  307. { /* System Registers */
  308. .virtual = 0xf3000000,
  309. .pfn = __phys_to_pfn(0x10000000),
  310. .length = SZ_1M,
  311. .type = MT_DEVICE
  312. }, { /* SA-1111 */
  313. .virtual = 0xf4000000,
  314. .pfn = __phys_to_pfn(0x40000000),
  315. .length = SZ_1M,
  316. .type = MT_DEVICE
  317. }
  318. };
  319. void __init neponset_map_io(void)
  320. {
  321. iotable_init(neponset_io_desc, ARRAY_SIZE(neponset_io_desc));
  322. }