Kconfig 18 KB

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  1. comment "Processor Type"
  2. config CPU_32
  3. bool
  4. default y
  5. # Select CPU types depending on the architecture selected. This selects
  6. # which CPUs we support in the kernel image, and the compiler instruction
  7. # optimiser behaviour.
  8. # ARM610
  9. config CPU_ARM610
  10. bool "Support ARM610 processor"
  11. depends on ARCH_RPC
  12. select CPU_32v3
  13. select CPU_CACHE_V3
  14. select CPU_CACHE_VIVT
  15. select CPU_CP15_MMU
  16. select CPU_COPY_V3 if MMU
  17. select CPU_TLB_V3 if MMU
  18. select CPU_PABRT_NOIFAR
  19. help
  20. The ARM610 is the successor to the ARM3 processor
  21. and was produced by VLSI Technology Inc.
  22. Say Y if you want support for the ARM610 processor.
  23. Otherwise, say N.
  24. # ARM7TDMI
  25. config CPU_ARM7TDMI
  26. bool "Support ARM7TDMI processor"
  27. depends on !MMU
  28. select CPU_32v4T
  29. select CPU_ABRT_LV4T
  30. select CPU_CACHE_V4
  31. help
  32. A 32-bit RISC microprocessor based on the ARM7 processor core
  33. which has no memory control unit and cache.
  34. Say Y if you want support for the ARM7TDMI processor.
  35. Otherwise, say N.
  36. # ARM710
  37. config CPU_ARM710
  38. bool "Support ARM710 processor" if !ARCH_CLPS7500 && ARCH_RPC
  39. default y if ARCH_CLPS7500
  40. select CPU_32v3
  41. select CPU_CACHE_V3
  42. select CPU_CACHE_VIVT
  43. select CPU_CP15_MMU
  44. select CPU_COPY_V3 if MMU
  45. select CPU_TLB_V3 if MMU
  46. select CPU_PABRT_NOIFAR
  47. help
  48. A 32-bit RISC microprocessor based on the ARM7 processor core
  49. designed by Advanced RISC Machines Ltd. The ARM710 is the
  50. successor to the ARM610 processor. It was released in
  51. July 1994 by VLSI Technology Inc.
  52. Say Y if you want support for the ARM710 processor.
  53. Otherwise, say N.
  54. # ARM720T
  55. config CPU_ARM720T
  56. bool "Support ARM720T processor" if !ARCH_CLPS711X && !ARCH_L7200 && !ARCH_CDB89712 && ARCH_INTEGRATOR
  57. default y if ARCH_CLPS711X || ARCH_L7200 || ARCH_CDB89712 || ARCH_H720X
  58. select CPU_32v4T
  59. select CPU_ABRT_LV4T
  60. select CPU_PABRT_NOIFAR
  61. select CPU_CACHE_V4
  62. select CPU_CACHE_VIVT
  63. select CPU_CP15_MMU
  64. select CPU_COPY_V4WT if MMU
  65. select CPU_TLB_V4WT if MMU
  66. help
  67. A 32-bit RISC processor with 8kByte Cache, Write Buffer and
  68. MMU built around an ARM7TDMI core.
  69. Say Y if you want support for the ARM720T processor.
  70. Otherwise, say N.
  71. # ARM740T
  72. config CPU_ARM740T
  73. bool "Support ARM740T processor" if ARCH_INTEGRATOR
  74. depends on !MMU
  75. select CPU_32v4T
  76. select CPU_ABRT_LV4T
  77. select CPU_CACHE_V3 # although the core is v4t
  78. select CPU_CP15_MPU
  79. help
  80. A 32-bit RISC processor with 8KB cache or 4KB variants,
  81. write buffer and MPU(Protection Unit) built around
  82. an ARM7TDMI core.
  83. Say Y if you want support for the ARM740T processor.
  84. Otherwise, say N.
  85. # ARM9TDMI
  86. config CPU_ARM9TDMI
  87. bool "Support ARM9TDMI processor"
  88. depends on !MMU
  89. select CPU_32v4T
  90. select CPU_ABRT_NOMMU
  91. select CPU_CACHE_V4
  92. help
  93. A 32-bit RISC microprocessor based on the ARM9 processor core
  94. which has no memory control unit and cache.
  95. Say Y if you want support for the ARM9TDMI processor.
  96. Otherwise, say N.
  97. # ARM920T
  98. config CPU_ARM920T
  99. bool "Support ARM920T processor"
  100. depends on ARCH_EP93XX || ARCH_INTEGRATOR || CPU_S3C2410 || CPU_S3C2440 || CPU_S3C2442 || ARCH_IMX || ARCH_AAEC2000 || ARCH_AT91RM9200
  101. default y if CPU_S3C2410 || CPU_S3C2440 || CPU_S3C2442 || ARCH_AT91RM9200
  102. select CPU_32v4T
  103. select CPU_ABRT_EV4T
  104. select CPU_PABRT_NOIFAR
  105. select CPU_CACHE_V4WT
  106. select CPU_CACHE_VIVT
  107. select CPU_CP15_MMU
  108. select CPU_COPY_V4WB if MMU
  109. select CPU_TLB_V4WBI if MMU
  110. help
  111. The ARM920T is licensed to be produced by numerous vendors,
  112. and is used in the Maverick EP9312 and the Samsung S3C2410.
  113. More information on the Maverick EP9312 at
  114. <http://linuxdevices.com/products/PD2382866068.html>.
  115. Say Y if you want support for the ARM920T processor.
  116. Otherwise, say N.
  117. # ARM922T
  118. config CPU_ARM922T
  119. bool "Support ARM922T processor" if ARCH_INTEGRATOR
  120. depends on ARCH_LH7A40X || ARCH_INTEGRATOR || ARCH_KS8695
  121. default y if ARCH_LH7A40X || ARCH_KS8695
  122. select CPU_32v4T
  123. select CPU_ABRT_EV4T
  124. select CPU_PABRT_NOIFAR
  125. select CPU_CACHE_V4WT
  126. select CPU_CACHE_VIVT
  127. select CPU_CP15_MMU
  128. select CPU_COPY_V4WB if MMU
  129. select CPU_TLB_V4WBI if MMU
  130. help
  131. The ARM922T is a version of the ARM920T, but with smaller
  132. instruction and data caches. It is used in Altera's
  133. Excalibur XA device family and Micrel's KS8695 Centaur.
  134. Say Y if you want support for the ARM922T processor.
  135. Otherwise, say N.
  136. # ARM925T
  137. config CPU_ARM925T
  138. bool "Support ARM925T processor" if ARCH_OMAP1
  139. depends on ARCH_OMAP15XX
  140. default y if ARCH_OMAP15XX
  141. select CPU_32v4T
  142. select CPU_ABRT_EV4T
  143. select CPU_PABRT_NOIFAR
  144. select CPU_CACHE_V4WT
  145. select CPU_CACHE_VIVT
  146. select CPU_CP15_MMU
  147. select CPU_COPY_V4WB if MMU
  148. select CPU_TLB_V4WBI if MMU
  149. help
  150. The ARM925T is a mix between the ARM920T and ARM926T, but with
  151. different instruction and data caches. It is used in TI's OMAP
  152. device family.
  153. Say Y if you want support for the ARM925T processor.
  154. Otherwise, say N.
  155. # ARM926T
  156. config CPU_ARM926T
  157. bool "Support ARM926T processor"
  158. depends on ARCH_INTEGRATOR || ARCH_VERSATILE_PB || MACH_VERSATILE_AB || ARCH_OMAP730 || ARCH_OMAP16XX || MACH_REALVIEW_EB || ARCH_PNX4008 || ARCH_NETX || CPU_S3C2412 || ARCH_AT91SAM9260 || ARCH_AT91SAM9261 || ARCH_AT91SAM9263 || ARCH_AT91SAM9RL || ARCH_AT91CAP9 || ARCH_NS9XXX || ARCH_DAVINCI
  159. default y if ARCH_VERSATILE_PB || MACH_VERSATILE_AB || ARCH_OMAP730 || ARCH_OMAP16XX || ARCH_PNX4008 || ARCH_NETX || CPU_S3C2412 || ARCH_AT91SAM9260 || ARCH_AT91SAM9261 || ARCH_AT91SAM9263 || ARCH_AT91SAM9RL || ARCH_AT91CAP9 || ARCH_NS9XXX || ARCH_DAVINCI
  160. select CPU_32v5
  161. select CPU_ABRT_EV5TJ
  162. select CPU_PABRT_NOIFAR
  163. select CPU_CACHE_VIVT
  164. select CPU_CP15_MMU
  165. select CPU_COPY_V4WB if MMU
  166. select CPU_TLB_V4WBI if MMU
  167. help
  168. This is a variant of the ARM920. It has slightly different
  169. instruction sequences for cache and TLB operations. Curiously,
  170. there is no documentation on it at the ARM corporate website.
  171. Say Y if you want support for the ARM926T processor.
  172. Otherwise, say N.
  173. # ARM940T
  174. config CPU_ARM940T
  175. bool "Support ARM940T processor" if ARCH_INTEGRATOR
  176. depends on !MMU
  177. select CPU_32v4T
  178. select CPU_ABRT_NOMMU
  179. select CPU_CACHE_VIVT
  180. select CPU_CP15_MPU
  181. help
  182. ARM940T is a member of the ARM9TDMI family of general-
  183. purpose microprocessors with MPU and separate 4KB
  184. instruction and 4KB data cases, each with a 4-word line
  185. length.
  186. Say Y if you want support for the ARM940T processor.
  187. Otherwise, say N.
  188. # ARM946E-S
  189. config CPU_ARM946E
  190. bool "Support ARM946E-S processor" if ARCH_INTEGRATOR
  191. depends on !MMU
  192. select CPU_32v5
  193. select CPU_ABRT_NOMMU
  194. select CPU_CACHE_VIVT
  195. select CPU_CP15_MPU
  196. help
  197. ARM946E-S is a member of the ARM9E-S family of high-
  198. performance, 32-bit system-on-chip processor solutions.
  199. The TCM and ARMv5TE 32-bit instruction set is supported.
  200. Say Y if you want support for the ARM946E-S processor.
  201. Otherwise, say N.
  202. # ARM1020 - needs validating
  203. config CPU_ARM1020
  204. bool "Support ARM1020T (rev 0) processor"
  205. depends on ARCH_INTEGRATOR
  206. select CPU_32v5
  207. select CPU_ABRT_EV4T
  208. select CPU_PABRT_NOIFAR
  209. select CPU_CACHE_V4WT
  210. select CPU_CACHE_VIVT
  211. select CPU_CP15_MMU
  212. select CPU_COPY_V4WB if MMU
  213. select CPU_TLB_V4WBI if MMU
  214. help
  215. The ARM1020 is the 32K cached version of the ARM10 processor,
  216. with an addition of a floating-point unit.
  217. Say Y if you want support for the ARM1020 processor.
  218. Otherwise, say N.
  219. # ARM1020E - needs validating
  220. config CPU_ARM1020E
  221. bool "Support ARM1020E processor"
  222. depends on ARCH_INTEGRATOR
  223. select CPU_32v5
  224. select CPU_ABRT_EV4T
  225. select CPU_PABRT_NOIFAR
  226. select CPU_CACHE_V4WT
  227. select CPU_CACHE_VIVT
  228. select CPU_CP15_MMU
  229. select CPU_COPY_V4WB if MMU
  230. select CPU_TLB_V4WBI if MMU
  231. depends on n
  232. # ARM1022E
  233. config CPU_ARM1022
  234. bool "Support ARM1022E processor"
  235. depends on ARCH_INTEGRATOR
  236. select CPU_32v5
  237. select CPU_ABRT_EV4T
  238. select CPU_PABRT_NOIFAR
  239. select CPU_CACHE_VIVT
  240. select CPU_CP15_MMU
  241. select CPU_COPY_V4WB if MMU # can probably do better
  242. select CPU_TLB_V4WBI if MMU
  243. help
  244. The ARM1022E is an implementation of the ARMv5TE architecture
  245. based upon the ARM10 integer core with a 16KiB L1 Harvard cache,
  246. embedded trace macrocell, and a floating-point unit.
  247. Say Y if you want support for the ARM1022E processor.
  248. Otherwise, say N.
  249. # ARM1026EJ-S
  250. config CPU_ARM1026
  251. bool "Support ARM1026EJ-S processor"
  252. depends on ARCH_INTEGRATOR
  253. select CPU_32v5
  254. select CPU_ABRT_EV5T # But need Jazelle, but EV5TJ ignores bit 10
  255. select CPU_PABRT_NOIFAR
  256. select CPU_CACHE_VIVT
  257. select CPU_CP15_MMU
  258. select CPU_COPY_V4WB if MMU # can probably do better
  259. select CPU_TLB_V4WBI if MMU
  260. help
  261. The ARM1026EJ-S is an implementation of the ARMv5TEJ architecture
  262. based upon the ARM10 integer core.
  263. Say Y if you want support for the ARM1026EJ-S processor.
  264. Otherwise, say N.
  265. # SA110
  266. config CPU_SA110
  267. bool "Support StrongARM(R) SA-110 processor" if !ARCH_EBSA110 && !FOOTBRIDGE && !ARCH_TBOX && !ARCH_SHARK && !ARCH_NEXUSPCI && ARCH_RPC
  268. default y if ARCH_EBSA110 || FOOTBRIDGE || ARCH_TBOX || ARCH_SHARK || ARCH_NEXUSPCI
  269. select CPU_32v3 if ARCH_RPC
  270. select CPU_32v4 if !ARCH_RPC
  271. select CPU_ABRT_EV4
  272. select CPU_PABRT_NOIFAR
  273. select CPU_CACHE_V4WB
  274. select CPU_CACHE_VIVT
  275. select CPU_CP15_MMU
  276. select CPU_COPY_V4WB if MMU
  277. select CPU_TLB_V4WB if MMU
  278. help
  279. The Intel StrongARM(R) SA-110 is a 32-bit microprocessor and
  280. is available at five speeds ranging from 100 MHz to 233 MHz.
  281. More information is available at
  282. <http://developer.intel.com/design/strong/sa110.htm>.
  283. Say Y if you want support for the SA-110 processor.
  284. Otherwise, say N.
  285. # SA1100
  286. config CPU_SA1100
  287. bool
  288. depends on ARCH_SA1100
  289. default y
  290. select CPU_32v4
  291. select CPU_ABRT_EV4
  292. select CPU_PABRT_NOIFAR
  293. select CPU_CACHE_V4WB
  294. select CPU_CACHE_VIVT
  295. select CPU_CP15_MMU
  296. select CPU_TLB_V4WB if MMU
  297. # XScale
  298. config CPU_XSCALE
  299. bool
  300. depends on ARCH_IOP32X || ARCH_IOP33X || PXA25x || PXA27x || ARCH_IXP4XX || ARCH_IXP2000
  301. default y
  302. select CPU_32v5
  303. select CPU_ABRT_EV5T
  304. select CPU_PABRT_NOIFAR
  305. select CPU_CACHE_VIVT
  306. select CPU_CP15_MMU
  307. select CPU_TLB_V4WBI if MMU
  308. # XScale Core Version 3
  309. config CPU_XSC3
  310. bool
  311. depends on ARCH_IXP23XX || ARCH_IOP13XX || PXA3xx
  312. default y
  313. select CPU_32v5
  314. select CPU_ABRT_EV5T
  315. select CPU_CACHE_VIVT
  316. select CPU_CP15_MMU
  317. select CPU_TLB_V4WBI if MMU
  318. select IO_36
  319. # Feroceon
  320. config CPU_FEROCEON
  321. bool
  322. depends on ARCH_ORION
  323. default y
  324. select CPU_32v5
  325. select CPU_ABRT_EV5T
  326. select CPU_PABRT_NOIFAR
  327. select CPU_CACHE_VIVT
  328. select CPU_CP15_MMU
  329. select CPU_COPY_V4WB if MMU
  330. select CPU_TLB_V4WBI if MMU
  331. config CPU_FEROCEON_OLD_ID
  332. bool "Accept early Feroceon cores with an ARM926 ID"
  333. depends on CPU_FEROCEON && !CPU_ARM926T
  334. default y
  335. help
  336. This enables the usage of some old Feroceon cores
  337. for which the CPU ID is equal to the ARM926 ID.
  338. Relevant for Feroceon-1850 and early Feroceon-2850.
  339. # ARMv6
  340. config CPU_V6
  341. bool "Support ARM V6 processor"
  342. depends on ARCH_INTEGRATOR || MACH_REALVIEW_EB || ARCH_OMAP2 || ARCH_MX3 || ARCH_MSM7X00A || MACH_REALVIEW_PB11MP || MACH_REALVIEW_PB1176
  343. default y if ARCH_MX3
  344. default y if ARCH_MSM7X00A
  345. select CPU_32v6
  346. select CPU_ABRT_EV6
  347. select CPU_PABRT_NOIFAR
  348. select CPU_CACHE_V6
  349. select CPU_CACHE_VIPT
  350. select CPU_CP15_MMU
  351. select CPU_HAS_ASID if MMU
  352. select CPU_COPY_V6 if MMU
  353. select CPU_TLB_V6 if MMU
  354. # ARMv6k
  355. config CPU_32v6K
  356. bool "Support ARM V6K processor extensions" if !SMP
  357. depends on CPU_V6
  358. default y if SMP && !ARCH_MX3
  359. help
  360. Say Y here if your ARMv6 processor supports the 'K' extension.
  361. This enables the kernel to use some instructions not present
  362. on previous processors, and as such a kernel build with this
  363. enabled will not boot on processors with do not support these
  364. instructions.
  365. # ARMv7
  366. config CPU_V7
  367. bool "Support ARM V7 processor"
  368. depends on ARCH_INTEGRATOR || MACH_REALVIEW_EB
  369. select CPU_32v6K
  370. select CPU_32v7
  371. select CPU_ABRT_EV7
  372. select CPU_PABRT_IFAR
  373. select CPU_CACHE_V7
  374. select CPU_CACHE_VIPT
  375. select CPU_CP15_MMU
  376. select CPU_HAS_ASID if MMU
  377. select CPU_COPY_V6 if MMU
  378. select CPU_TLB_V7 if MMU
  379. # Figure out what processor architecture version we should be using.
  380. # This defines the compiler instruction set which depends on the machine type.
  381. config CPU_32v3
  382. bool
  383. select TLS_REG_EMUL if SMP || !MMU
  384. select NEEDS_SYSCALL_FOR_CMPXCHG if SMP
  385. config CPU_32v4
  386. bool
  387. select TLS_REG_EMUL if SMP || !MMU
  388. select NEEDS_SYSCALL_FOR_CMPXCHG if SMP
  389. config CPU_32v4T
  390. bool
  391. select TLS_REG_EMUL if SMP || !MMU
  392. select NEEDS_SYSCALL_FOR_CMPXCHG if SMP
  393. config CPU_32v5
  394. bool
  395. select TLS_REG_EMUL if SMP || !MMU
  396. select NEEDS_SYSCALL_FOR_CMPXCHG if SMP
  397. config CPU_32v6
  398. bool
  399. select TLS_REG_EMUL if !CPU_32v6K && !MMU
  400. config CPU_32v7
  401. bool
  402. # The abort model
  403. config CPU_ABRT_NOMMU
  404. bool
  405. config CPU_ABRT_EV4
  406. bool
  407. config CPU_ABRT_EV4T
  408. bool
  409. config CPU_ABRT_LV4T
  410. bool
  411. config CPU_ABRT_EV5T
  412. bool
  413. config CPU_ABRT_EV5TJ
  414. bool
  415. config CPU_ABRT_EV6
  416. bool
  417. config CPU_ABRT_EV7
  418. bool
  419. config CPU_PABRT_IFAR
  420. bool
  421. config CPU_PABRT_NOIFAR
  422. bool
  423. # The cache model
  424. config CPU_CACHE_V3
  425. bool
  426. config CPU_CACHE_V4
  427. bool
  428. config CPU_CACHE_V4WT
  429. bool
  430. config CPU_CACHE_V4WB
  431. bool
  432. config CPU_CACHE_V6
  433. bool
  434. config CPU_CACHE_V7
  435. bool
  436. config CPU_CACHE_VIVT
  437. bool
  438. config CPU_CACHE_VIPT
  439. bool
  440. if MMU
  441. # The copy-page model
  442. config CPU_COPY_V3
  443. bool
  444. config CPU_COPY_V4WT
  445. bool
  446. config CPU_COPY_V4WB
  447. bool
  448. config CPU_COPY_V6
  449. bool
  450. # This selects the TLB model
  451. config CPU_TLB_V3
  452. bool
  453. help
  454. ARM Architecture Version 3 TLB.
  455. config CPU_TLB_V4WT
  456. bool
  457. help
  458. ARM Architecture Version 4 TLB with writethrough cache.
  459. config CPU_TLB_V4WB
  460. bool
  461. help
  462. ARM Architecture Version 4 TLB with writeback cache.
  463. config CPU_TLB_V4WBI
  464. bool
  465. help
  466. ARM Architecture Version 4 TLB with writeback cache and invalidate
  467. instruction cache entry.
  468. config CPU_TLB_V6
  469. bool
  470. config CPU_TLB_V7
  471. bool
  472. endif
  473. config CPU_HAS_ASID
  474. bool
  475. help
  476. This indicates whether the CPU has the ASID register; used to
  477. tag TLB and possibly cache entries.
  478. config CPU_CP15
  479. bool
  480. help
  481. Processor has the CP15 register.
  482. config CPU_CP15_MMU
  483. bool
  484. select CPU_CP15
  485. help
  486. Processor has the CP15 register, which has MMU related registers.
  487. config CPU_CP15_MPU
  488. bool
  489. select CPU_CP15
  490. help
  491. Processor has the CP15 register, which has MPU related registers.
  492. #
  493. # CPU supports 36-bit I/O
  494. #
  495. config IO_36
  496. bool
  497. comment "Processor Features"
  498. config ARM_THUMB
  499. bool "Support Thumb user binaries"
  500. depends on CPU_ARM720T || CPU_ARM740T || CPU_ARM920T || CPU_ARM922T || CPU_ARM925T || CPU_ARM926T || CPU_ARM940T || CPU_ARM946E || CPU_ARM1020 || CPU_ARM1020E || CPU_ARM1022 || CPU_ARM1026 || CPU_XSCALE || CPU_XSC3 || CPU_V6 || CPU_V7 || CPU_FEROCEON
  501. default y
  502. help
  503. Say Y if you want to include kernel support for running user space
  504. Thumb binaries.
  505. The Thumb instruction set is a compressed form of the standard ARM
  506. instruction set resulting in smaller binaries at the expense of
  507. slightly less efficient code.
  508. If you don't know what this all is, saying Y is a safe choice.
  509. config ARM_THUMBEE
  510. bool "Enable ThumbEE CPU extension"
  511. depends on CPU_V7
  512. help
  513. Say Y here if you have a CPU with the ThumbEE extension and code to
  514. make use of it. Say N for code that can run on CPUs without ThumbEE.
  515. config CPU_BIG_ENDIAN
  516. bool "Build big-endian kernel"
  517. depends on ARCH_SUPPORTS_BIG_ENDIAN
  518. help
  519. Say Y if you plan on running a kernel in big-endian mode.
  520. Note that your board must be properly built and your board
  521. port must properly enable any big-endian related features
  522. of your chipset/board/processor.
  523. config CPU_HIGH_VECTOR
  524. depends on !MMU && CPU_CP15 && !CPU_ARM740T
  525. bool "Select the High exception vector"
  526. default n
  527. help
  528. Say Y here to select high exception vector(0xFFFF0000~).
  529. The exception vector can be vary depending on the platform
  530. design in nommu mode. If your platform needs to select
  531. high exception vector, say Y.
  532. Otherwise or if you are unsure, say N, and the low exception
  533. vector (0x00000000~) will be used.
  534. config CPU_ICACHE_DISABLE
  535. bool "Disable I-Cache (I-bit)"
  536. depends on CPU_CP15 && !(CPU_ARM610 || CPU_ARM710 || CPU_ARM720T || CPU_ARM740T || CPU_XSCALE || CPU_XSC3)
  537. help
  538. Say Y here to disable the processor instruction cache. Unless
  539. you have a reason not to or are unsure, say N.
  540. config CPU_DCACHE_DISABLE
  541. bool "Disable D-Cache (C-bit)"
  542. depends on CPU_CP15
  543. help
  544. Say Y here to disable the processor data cache. Unless
  545. you have a reason not to or are unsure, say N.
  546. config CPU_DCACHE_SIZE
  547. hex
  548. depends on CPU_ARM740T || CPU_ARM946E
  549. default 0x00001000 if CPU_ARM740T
  550. default 0x00002000 # default size for ARM946E-S
  551. help
  552. Some cores are synthesizable to have various sized cache. For
  553. ARM946E-S case, it can vary from 0KB to 1MB.
  554. To support such cache operations, it is efficient to know the size
  555. before compile time.
  556. If your SoC is configured to have a different size, define the value
  557. here with proper conditions.
  558. config CPU_DCACHE_WRITETHROUGH
  559. bool "Force write through D-cache"
  560. depends on (CPU_ARM740T || CPU_ARM920T || CPU_ARM922T || CPU_ARM925T || CPU_ARM926T || CPU_ARM940T || CPU_ARM946E || CPU_ARM1020 || CPU_FEROCEON) && !CPU_DCACHE_DISABLE
  561. default y if CPU_ARM925T
  562. help
  563. Say Y here to use the data cache in writethrough mode. Unless you
  564. specifically require this or are unsure, say N.
  565. config CPU_CACHE_ROUND_ROBIN
  566. bool "Round robin I and D cache replacement algorithm"
  567. depends on (CPU_ARM926T || CPU_ARM946E || CPU_ARM1020) && (!CPU_ICACHE_DISABLE || !CPU_DCACHE_DISABLE)
  568. help
  569. Say Y here to use the predictable round-robin cache replacement
  570. policy. Unless you specifically require this or are unsure, say N.
  571. config CPU_BPREDICT_DISABLE
  572. bool "Disable branch prediction"
  573. depends on CPU_ARM1020 || CPU_V6 || CPU_XSC3 || CPU_V7
  574. help
  575. Say Y here to disable branch prediction. If unsure, say N.
  576. config TLS_REG_EMUL
  577. bool
  578. help
  579. An SMP system using a pre-ARMv6 processor (there are apparently
  580. a few prototypes like that in existence) and therefore access to
  581. that required register must be emulated.
  582. config HAS_TLS_REG
  583. bool
  584. depends on !TLS_REG_EMUL
  585. default y if SMP || CPU_32v7
  586. help
  587. This selects support for the CP15 thread register.
  588. It is defined to be available on some ARMv6 processors (including
  589. all SMP capable ARMv6's) or later processors. User space may
  590. assume directly accessing that register and always obtain the
  591. expected value only on ARMv7 and above.
  592. config NEEDS_SYSCALL_FOR_CMPXCHG
  593. bool
  594. help
  595. SMP on a pre-ARMv6 processor? Well OK then.
  596. Forget about fast user space cmpxchg support.
  597. It is just not possible.
  598. config OUTER_CACHE
  599. bool
  600. default n
  601. config CACHE_L2X0
  602. bool "Enable the L2x0 outer cache controller"
  603. depends on REALVIEW_EB_ARM11MP || MACH_REALVIEW_PB11MP || MACH_REALVIEW_PB1176
  604. default y
  605. select OUTER_CACHE
  606. help
  607. This option enables the L2x0 PrimeCell.