setup.c 37 KB

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  1. /*
  2. * linux/arch/x86-64/kernel/setup.c
  3. *
  4. * Copyright (C) 1995 Linus Torvalds
  5. *
  6. * Nov 2001 Dave Jones <davej@suse.de>
  7. * Forked from i386 setup code.
  8. *
  9. * $Id$
  10. */
  11. /*
  12. * This file handles the architecture-dependent parts of initialization
  13. */
  14. #include <linux/errno.h>
  15. #include <linux/sched.h>
  16. #include <linux/kernel.h>
  17. #include <linux/mm.h>
  18. #include <linux/stddef.h>
  19. #include <linux/unistd.h>
  20. #include <linux/ptrace.h>
  21. #include <linux/slab.h>
  22. #include <linux/user.h>
  23. #include <linux/a.out.h>
  24. #include <linux/tty.h>
  25. #include <linux/ioport.h>
  26. #include <linux/delay.h>
  27. #include <linux/config.h>
  28. #include <linux/init.h>
  29. #include <linux/initrd.h>
  30. #include <linux/highmem.h>
  31. #include <linux/bootmem.h>
  32. #include <linux/module.h>
  33. #include <asm/processor.h>
  34. #include <linux/console.h>
  35. #include <linux/seq_file.h>
  36. #include <linux/crash_dump.h>
  37. #include <linux/root_dev.h>
  38. #include <linux/pci.h>
  39. #include <linux/acpi.h>
  40. #include <linux/kallsyms.h>
  41. #include <linux/edd.h>
  42. #include <linux/mmzone.h>
  43. #include <linux/kexec.h>
  44. #include <linux/cpufreq.h>
  45. #include <linux/dmi.h>
  46. #include <linux/dma-mapping.h>
  47. #include <linux/ctype.h>
  48. #include <asm/mtrr.h>
  49. #include <asm/uaccess.h>
  50. #include <asm/system.h>
  51. #include <asm/io.h>
  52. #include <asm/smp.h>
  53. #include <asm/msr.h>
  54. #include <asm/desc.h>
  55. #include <video/edid.h>
  56. #include <asm/e820.h>
  57. #include <asm/dma.h>
  58. #include <asm/mpspec.h>
  59. #include <asm/mmu_context.h>
  60. #include <asm/bootsetup.h>
  61. #include <asm/proto.h>
  62. #include <asm/setup.h>
  63. #include <asm/mach_apic.h>
  64. #include <asm/numa.h>
  65. #include <asm/swiotlb.h>
  66. #include <asm/sections.h>
  67. #include <asm/gart-mapping.h>
  68. #include <asm/dmi.h>
  69. /*
  70. * Machine setup..
  71. */
  72. struct cpuinfo_x86 boot_cpu_data __read_mostly;
  73. unsigned long mmu_cr4_features;
  74. int acpi_disabled;
  75. EXPORT_SYMBOL(acpi_disabled);
  76. #ifdef CONFIG_ACPI
  77. extern int __initdata acpi_ht;
  78. extern acpi_interrupt_flags acpi_sci_flags;
  79. int __initdata acpi_force = 0;
  80. #endif
  81. int acpi_numa __initdata;
  82. /* Boot loader ID as an integer, for the benefit of proc_dointvec */
  83. int bootloader_type;
  84. unsigned long saved_video_mode;
  85. /*
  86. * Early DMI memory
  87. */
  88. int dmi_alloc_index;
  89. char dmi_alloc_data[DMI_MAX_DATA];
  90. /*
  91. * Setup options
  92. */
  93. struct screen_info screen_info;
  94. struct sys_desc_table_struct {
  95. unsigned short length;
  96. unsigned char table[0];
  97. };
  98. struct edid_info edid_info;
  99. EXPORT_SYMBOL_GPL(edid_info);
  100. struct e820map e820;
  101. extern int root_mountflags;
  102. char command_line[COMMAND_LINE_SIZE];
  103. struct resource standard_io_resources[] = {
  104. { .name = "dma1", .start = 0x00, .end = 0x1f,
  105. .flags = IORESOURCE_BUSY | IORESOURCE_IO },
  106. { .name = "pic1", .start = 0x20, .end = 0x21,
  107. .flags = IORESOURCE_BUSY | IORESOURCE_IO },
  108. { .name = "timer0", .start = 0x40, .end = 0x43,
  109. .flags = IORESOURCE_BUSY | IORESOURCE_IO },
  110. { .name = "timer1", .start = 0x50, .end = 0x53,
  111. .flags = IORESOURCE_BUSY | IORESOURCE_IO },
  112. { .name = "keyboard", .start = 0x60, .end = 0x6f,
  113. .flags = IORESOURCE_BUSY | IORESOURCE_IO },
  114. { .name = "dma page reg", .start = 0x80, .end = 0x8f,
  115. .flags = IORESOURCE_BUSY | IORESOURCE_IO },
  116. { .name = "pic2", .start = 0xa0, .end = 0xa1,
  117. .flags = IORESOURCE_BUSY | IORESOURCE_IO },
  118. { .name = "dma2", .start = 0xc0, .end = 0xdf,
  119. .flags = IORESOURCE_BUSY | IORESOURCE_IO },
  120. { .name = "fpu", .start = 0xf0, .end = 0xff,
  121. .flags = IORESOURCE_BUSY | IORESOURCE_IO }
  122. };
  123. #define STANDARD_IO_RESOURCES \
  124. (sizeof standard_io_resources / sizeof standard_io_resources[0])
  125. #define IORESOURCE_RAM (IORESOURCE_BUSY | IORESOURCE_MEM)
  126. struct resource data_resource = {
  127. .name = "Kernel data",
  128. .start = 0,
  129. .end = 0,
  130. .flags = IORESOURCE_RAM,
  131. };
  132. struct resource code_resource = {
  133. .name = "Kernel code",
  134. .start = 0,
  135. .end = 0,
  136. .flags = IORESOURCE_RAM,
  137. };
  138. #define IORESOURCE_ROM (IORESOURCE_BUSY | IORESOURCE_READONLY | IORESOURCE_MEM)
  139. static struct resource system_rom_resource = {
  140. .name = "System ROM",
  141. .start = 0xf0000,
  142. .end = 0xfffff,
  143. .flags = IORESOURCE_ROM,
  144. };
  145. static struct resource extension_rom_resource = {
  146. .name = "Extension ROM",
  147. .start = 0xe0000,
  148. .end = 0xeffff,
  149. .flags = IORESOURCE_ROM,
  150. };
  151. static struct resource adapter_rom_resources[] = {
  152. { .name = "Adapter ROM", .start = 0xc8000, .end = 0,
  153. .flags = IORESOURCE_ROM },
  154. { .name = "Adapter ROM", .start = 0, .end = 0,
  155. .flags = IORESOURCE_ROM },
  156. { .name = "Adapter ROM", .start = 0, .end = 0,
  157. .flags = IORESOURCE_ROM },
  158. { .name = "Adapter ROM", .start = 0, .end = 0,
  159. .flags = IORESOURCE_ROM },
  160. { .name = "Adapter ROM", .start = 0, .end = 0,
  161. .flags = IORESOURCE_ROM },
  162. { .name = "Adapter ROM", .start = 0, .end = 0,
  163. .flags = IORESOURCE_ROM }
  164. };
  165. #define ADAPTER_ROM_RESOURCES \
  166. (sizeof adapter_rom_resources / sizeof adapter_rom_resources[0])
  167. static struct resource video_rom_resource = {
  168. .name = "Video ROM",
  169. .start = 0xc0000,
  170. .end = 0xc7fff,
  171. .flags = IORESOURCE_ROM,
  172. };
  173. static struct resource video_ram_resource = {
  174. .name = "Video RAM area",
  175. .start = 0xa0000,
  176. .end = 0xbffff,
  177. .flags = IORESOURCE_RAM,
  178. };
  179. #define romsignature(x) (*(unsigned short *)(x) == 0xaa55)
  180. static int __init romchecksum(unsigned char *rom, unsigned long length)
  181. {
  182. unsigned char *p, sum = 0;
  183. for (p = rom; p < rom + length; p++)
  184. sum += *p;
  185. return sum == 0;
  186. }
  187. static void __init probe_roms(void)
  188. {
  189. unsigned long start, length, upper;
  190. unsigned char *rom;
  191. int i;
  192. /* video rom */
  193. upper = adapter_rom_resources[0].start;
  194. for (start = video_rom_resource.start; start < upper; start += 2048) {
  195. rom = isa_bus_to_virt(start);
  196. if (!romsignature(rom))
  197. continue;
  198. video_rom_resource.start = start;
  199. /* 0 < length <= 0x7f * 512, historically */
  200. length = rom[2] * 512;
  201. /* if checksum okay, trust length byte */
  202. if (length && romchecksum(rom, length))
  203. video_rom_resource.end = start + length - 1;
  204. request_resource(&iomem_resource, &video_rom_resource);
  205. break;
  206. }
  207. start = (video_rom_resource.end + 1 + 2047) & ~2047UL;
  208. if (start < upper)
  209. start = upper;
  210. /* system rom */
  211. request_resource(&iomem_resource, &system_rom_resource);
  212. upper = system_rom_resource.start;
  213. /* check for extension rom (ignore length byte!) */
  214. rom = isa_bus_to_virt(extension_rom_resource.start);
  215. if (romsignature(rom)) {
  216. length = extension_rom_resource.end - extension_rom_resource.start + 1;
  217. if (romchecksum(rom, length)) {
  218. request_resource(&iomem_resource, &extension_rom_resource);
  219. upper = extension_rom_resource.start;
  220. }
  221. }
  222. /* check for adapter roms on 2k boundaries */
  223. for (i = 0; i < ADAPTER_ROM_RESOURCES && start < upper; start += 2048) {
  224. rom = isa_bus_to_virt(start);
  225. if (!romsignature(rom))
  226. continue;
  227. /* 0 < length <= 0x7f * 512, historically */
  228. length = rom[2] * 512;
  229. /* but accept any length that fits if checksum okay */
  230. if (!length || start + length > upper || !romchecksum(rom, length))
  231. continue;
  232. adapter_rom_resources[i].start = start;
  233. adapter_rom_resources[i].end = start + length - 1;
  234. request_resource(&iomem_resource, &adapter_rom_resources[i]);
  235. start = adapter_rom_resources[i++].end & ~2047UL;
  236. }
  237. }
  238. /* Check for full argument with no trailing characters */
  239. static int fullarg(char *p, char *arg)
  240. {
  241. int l = strlen(arg);
  242. return !memcmp(p, arg, l) && (p[l] == 0 || isspace(p[l]));
  243. }
  244. static __init void parse_cmdline_early (char ** cmdline_p)
  245. {
  246. char c = ' ', *to = command_line, *from = COMMAND_LINE;
  247. int len = 0;
  248. int userdef = 0;
  249. for (;;) {
  250. if (c != ' ')
  251. goto next_char;
  252. #ifdef CONFIG_SMP
  253. /*
  254. * If the BIOS enumerates physical processors before logical,
  255. * maxcpus=N at enumeration-time can be used to disable HT.
  256. */
  257. else if (!memcmp(from, "maxcpus=", 8)) {
  258. extern unsigned int maxcpus;
  259. maxcpus = simple_strtoul(from + 8, NULL, 0);
  260. }
  261. #endif
  262. #ifdef CONFIG_ACPI
  263. /* "acpi=off" disables both ACPI table parsing and interpreter init */
  264. if (fullarg(from,"acpi=off"))
  265. disable_acpi();
  266. if (fullarg(from, "acpi=force")) {
  267. /* add later when we do DMI horrors: */
  268. acpi_force = 1;
  269. acpi_disabled = 0;
  270. }
  271. /* acpi=ht just means: do ACPI MADT parsing
  272. at bootup, but don't enable the full ACPI interpreter */
  273. if (fullarg(from, "acpi=ht")) {
  274. if (!acpi_force)
  275. disable_acpi();
  276. acpi_ht = 1;
  277. }
  278. else if (fullarg(from, "pci=noacpi"))
  279. acpi_disable_pci();
  280. else if (fullarg(from, "acpi=noirq"))
  281. acpi_noirq_set();
  282. else if (fullarg(from, "acpi_sci=edge"))
  283. acpi_sci_flags.trigger = 1;
  284. else if (fullarg(from, "acpi_sci=level"))
  285. acpi_sci_flags.trigger = 3;
  286. else if (fullarg(from, "acpi_sci=high"))
  287. acpi_sci_flags.polarity = 1;
  288. else if (fullarg(from, "acpi_sci=low"))
  289. acpi_sci_flags.polarity = 3;
  290. /* acpi=strict disables out-of-spec workarounds */
  291. else if (fullarg(from, "acpi=strict")) {
  292. acpi_strict = 1;
  293. }
  294. #ifdef CONFIG_X86_IO_APIC
  295. else if (fullarg(from, "acpi_skip_timer_override"))
  296. acpi_skip_timer_override = 1;
  297. #endif
  298. #endif
  299. if (fullarg(from, "disable_timer_pin_1"))
  300. disable_timer_pin_1 = 1;
  301. if (fullarg(from, "enable_timer_pin_1"))
  302. disable_timer_pin_1 = -1;
  303. if (fullarg(from, "nolapic") || fullarg(from, "disableapic")) {
  304. clear_bit(X86_FEATURE_APIC, boot_cpu_data.x86_capability);
  305. disable_apic = 1;
  306. }
  307. if (fullarg(from, "noapic"))
  308. skip_ioapic_setup = 1;
  309. if (fullarg(from,"apic")) {
  310. skip_ioapic_setup = 0;
  311. ioapic_force = 1;
  312. }
  313. if (!memcmp(from, "mem=", 4))
  314. parse_memopt(from+4, &from);
  315. if (!memcmp(from, "memmap=", 7)) {
  316. /* exactmap option is for used defined memory */
  317. if (!memcmp(from+7, "exactmap", 8)) {
  318. #ifdef CONFIG_CRASH_DUMP
  319. /* If we are doing a crash dump, we
  320. * still need to know the real mem
  321. * size before original memory map is
  322. * reset.
  323. */
  324. saved_max_pfn = e820_end_of_ram();
  325. #endif
  326. from += 8+7;
  327. end_pfn_map = 0;
  328. e820.nr_map = 0;
  329. userdef = 1;
  330. }
  331. else {
  332. parse_memmapopt(from+7, &from);
  333. userdef = 1;
  334. }
  335. }
  336. #ifdef CONFIG_NUMA
  337. if (!memcmp(from, "numa=", 5))
  338. numa_setup(from+5);
  339. #endif
  340. if (!memcmp(from,"iommu=",6)) {
  341. iommu_setup(from+6);
  342. }
  343. if (fullarg(from,"oops=panic"))
  344. panic_on_oops = 1;
  345. if (!memcmp(from, "noexec=", 7))
  346. nonx_setup(from + 7);
  347. #ifdef CONFIG_KEXEC
  348. /* crashkernel=size@addr specifies the location to reserve for
  349. * a crash kernel. By reserving this memory we guarantee
  350. * that linux never set's it up as a DMA target.
  351. * Useful for holding code to do something appropriate
  352. * after a kernel panic.
  353. */
  354. else if (!memcmp(from, "crashkernel=", 12)) {
  355. unsigned long size, base;
  356. size = memparse(from+12, &from);
  357. if (*from == '@') {
  358. base = memparse(from+1, &from);
  359. /* FIXME: Do I want a sanity check
  360. * to validate the memory range?
  361. */
  362. crashk_res.start = base;
  363. crashk_res.end = base + size - 1;
  364. }
  365. }
  366. #endif
  367. #ifdef CONFIG_PROC_VMCORE
  368. /* elfcorehdr= specifies the location of elf core header
  369. * stored by the crashed kernel. This option will be passed
  370. * by kexec loader to the capture kernel.
  371. */
  372. else if(!memcmp(from, "elfcorehdr=", 11))
  373. elfcorehdr_addr = memparse(from+11, &from);
  374. #endif
  375. #ifdef CONFIG_HOTPLUG_CPU
  376. else if (!memcmp(from, "additional_cpus=", 16))
  377. setup_additional_cpus(from+16);
  378. #endif
  379. next_char:
  380. c = *(from++);
  381. if (!c)
  382. break;
  383. if (COMMAND_LINE_SIZE <= ++len)
  384. break;
  385. *(to++) = c;
  386. }
  387. if (userdef) {
  388. printk(KERN_INFO "user-defined physical RAM map:\n");
  389. e820_print_map("user");
  390. }
  391. *to = '\0';
  392. *cmdline_p = command_line;
  393. }
  394. #ifndef CONFIG_NUMA
  395. static void __init
  396. contig_initmem_init(unsigned long start_pfn, unsigned long end_pfn)
  397. {
  398. unsigned long bootmap_size, bootmap;
  399. bootmap_size = bootmem_bootmap_pages(end_pfn)<<PAGE_SHIFT;
  400. bootmap = find_e820_area(0, end_pfn<<PAGE_SHIFT, bootmap_size);
  401. if (bootmap == -1L)
  402. panic("Cannot find bootmem map of size %ld\n",bootmap_size);
  403. bootmap_size = init_bootmem(bootmap >> PAGE_SHIFT, end_pfn);
  404. e820_bootmem_free(NODE_DATA(0), 0, end_pfn << PAGE_SHIFT);
  405. reserve_bootmem(bootmap, bootmap_size);
  406. }
  407. #endif
  408. /* Use inline assembly to define this because the nops are defined
  409. as inline assembly strings in the include files and we cannot
  410. get them easily into strings. */
  411. asm("\t.data\nk8nops: "
  412. K8_NOP1 K8_NOP2 K8_NOP3 K8_NOP4 K8_NOP5 K8_NOP6
  413. K8_NOP7 K8_NOP8);
  414. extern unsigned char k8nops[];
  415. static unsigned char *k8_nops[ASM_NOP_MAX+1] = {
  416. NULL,
  417. k8nops,
  418. k8nops + 1,
  419. k8nops + 1 + 2,
  420. k8nops + 1 + 2 + 3,
  421. k8nops + 1 + 2 + 3 + 4,
  422. k8nops + 1 + 2 + 3 + 4 + 5,
  423. k8nops + 1 + 2 + 3 + 4 + 5 + 6,
  424. k8nops + 1 + 2 + 3 + 4 + 5 + 6 + 7,
  425. };
  426. extern char __vsyscall_0;
  427. /* Replace instructions with better alternatives for this CPU type.
  428. This runs before SMP is initialized to avoid SMP problems with
  429. self modifying code. This implies that assymetric systems where
  430. APs have less capabilities than the boot processor are not handled.
  431. In this case boot with "noreplacement". */
  432. void apply_alternatives(void *start, void *end)
  433. {
  434. struct alt_instr *a;
  435. int diff, i, k;
  436. for (a = start; (void *)a < end; a++) {
  437. u8 *instr;
  438. if (!boot_cpu_has(a->cpuid))
  439. continue;
  440. BUG_ON(a->replacementlen > a->instrlen);
  441. instr = a->instr;
  442. /* vsyscall code is not mapped yet. resolve it manually. */
  443. if (instr >= (u8 *)VSYSCALL_START && instr < (u8*)VSYSCALL_END)
  444. instr = __va(instr - (u8*)VSYSCALL_START + (u8*)__pa_symbol(&__vsyscall_0));
  445. __inline_memcpy(instr, a->replacement, a->replacementlen);
  446. diff = a->instrlen - a->replacementlen;
  447. /* Pad the rest with nops */
  448. for (i = a->replacementlen; diff > 0; diff -= k, i += k) {
  449. k = diff;
  450. if (k > ASM_NOP_MAX)
  451. k = ASM_NOP_MAX;
  452. __inline_memcpy(instr + i, k8_nops[k], k);
  453. }
  454. }
  455. }
  456. static int no_replacement __initdata = 0;
  457. void __init alternative_instructions(void)
  458. {
  459. extern struct alt_instr __alt_instructions[], __alt_instructions_end[];
  460. if (no_replacement)
  461. return;
  462. apply_alternatives(__alt_instructions, __alt_instructions_end);
  463. }
  464. static int __init noreplacement_setup(char *s)
  465. {
  466. no_replacement = 1;
  467. return 1;
  468. }
  469. __setup("noreplacement", noreplacement_setup);
  470. #if defined(CONFIG_EDD) || defined(CONFIG_EDD_MODULE)
  471. struct edd edd;
  472. #ifdef CONFIG_EDD_MODULE
  473. EXPORT_SYMBOL(edd);
  474. #endif
  475. /**
  476. * copy_edd() - Copy the BIOS EDD information
  477. * from boot_params into a safe place.
  478. *
  479. */
  480. static inline void copy_edd(void)
  481. {
  482. memcpy(edd.mbr_signature, EDD_MBR_SIGNATURE, sizeof(edd.mbr_signature));
  483. memcpy(edd.edd_info, EDD_BUF, sizeof(edd.edd_info));
  484. edd.mbr_signature_nr = EDD_MBR_SIG_NR;
  485. edd.edd_info_nr = EDD_NR;
  486. }
  487. #else
  488. static inline void copy_edd(void)
  489. {
  490. }
  491. #endif
  492. #define EBDA_ADDR_POINTER 0x40E
  493. unsigned __initdata ebda_addr;
  494. unsigned __initdata ebda_size;
  495. static void discover_ebda(void)
  496. {
  497. /*
  498. * there is a real-mode segmented pointer pointing to the
  499. * 4K EBDA area at 0x40E
  500. */
  501. ebda_addr = *(unsigned short *)EBDA_ADDR_POINTER;
  502. ebda_addr <<= 4;
  503. ebda_size = *(unsigned short *)(unsigned long)ebda_addr;
  504. /* Round EBDA up to pages */
  505. if (ebda_size == 0)
  506. ebda_size = 1;
  507. ebda_size <<= 10;
  508. ebda_size = round_up(ebda_size + (ebda_addr & ~PAGE_MASK), PAGE_SIZE);
  509. if (ebda_size > 64*1024)
  510. ebda_size = 64*1024;
  511. }
  512. void __init setup_arch(char **cmdline_p)
  513. {
  514. unsigned long kernel_end;
  515. ROOT_DEV = old_decode_dev(ORIG_ROOT_DEV);
  516. screen_info = SCREEN_INFO;
  517. edid_info = EDID_INFO;
  518. saved_video_mode = SAVED_VIDEO_MODE;
  519. bootloader_type = LOADER_TYPE;
  520. #ifdef CONFIG_BLK_DEV_RAM
  521. rd_image_start = RAMDISK_FLAGS & RAMDISK_IMAGE_START_MASK;
  522. rd_prompt = ((RAMDISK_FLAGS & RAMDISK_PROMPT_FLAG) != 0);
  523. rd_doload = ((RAMDISK_FLAGS & RAMDISK_LOAD_FLAG) != 0);
  524. #endif
  525. setup_memory_region();
  526. copy_edd();
  527. if (!MOUNT_ROOT_RDONLY)
  528. root_mountflags &= ~MS_RDONLY;
  529. init_mm.start_code = (unsigned long) &_text;
  530. init_mm.end_code = (unsigned long) &_etext;
  531. init_mm.end_data = (unsigned long) &_edata;
  532. init_mm.brk = (unsigned long) &_end;
  533. code_resource.start = virt_to_phys(&_text);
  534. code_resource.end = virt_to_phys(&_etext)-1;
  535. data_resource.start = virt_to_phys(&_etext);
  536. data_resource.end = virt_to_phys(&_edata)-1;
  537. parse_cmdline_early(cmdline_p);
  538. early_identify_cpu(&boot_cpu_data);
  539. /*
  540. * partially used pages are not usable - thus
  541. * we are rounding upwards:
  542. */
  543. end_pfn = e820_end_of_ram();
  544. num_physpages = end_pfn; /* for pfn_valid */
  545. check_efer();
  546. discover_ebda();
  547. init_memory_mapping(0, (end_pfn_map << PAGE_SHIFT));
  548. dmi_scan_machine();
  549. zap_low_mappings(0);
  550. #ifdef CONFIG_ACPI
  551. /*
  552. * Initialize the ACPI boot-time table parser (gets the RSDP and SDT).
  553. * Call this early for SRAT node setup.
  554. */
  555. acpi_boot_table_init();
  556. #endif
  557. #ifdef CONFIG_ACPI_NUMA
  558. /*
  559. * Parse SRAT to discover nodes.
  560. */
  561. acpi_numa_init();
  562. #endif
  563. #ifdef CONFIG_NUMA
  564. numa_initmem_init(0, end_pfn);
  565. #else
  566. contig_initmem_init(0, end_pfn);
  567. #endif
  568. /* Reserve direct mapping */
  569. reserve_bootmem_generic(table_start << PAGE_SHIFT,
  570. (table_end - table_start) << PAGE_SHIFT);
  571. /* reserve kernel */
  572. kernel_end = round_up(__pa_symbol(&_end),PAGE_SIZE);
  573. reserve_bootmem_generic(HIGH_MEMORY, kernel_end - HIGH_MEMORY);
  574. /*
  575. * reserve physical page 0 - it's a special BIOS page on many boxes,
  576. * enabling clean reboots, SMP operation, laptop functions.
  577. */
  578. reserve_bootmem_generic(0, PAGE_SIZE);
  579. /* reserve ebda region */
  580. if (ebda_addr)
  581. reserve_bootmem_generic(ebda_addr, ebda_size);
  582. #ifdef CONFIG_SMP
  583. /*
  584. * But first pinch a few for the stack/trampoline stuff
  585. * FIXME: Don't need the extra page at 4K, but need to fix
  586. * trampoline before removing it. (see the GDT stuff)
  587. */
  588. reserve_bootmem_generic(PAGE_SIZE, PAGE_SIZE);
  589. /* Reserve SMP trampoline */
  590. reserve_bootmem_generic(SMP_TRAMPOLINE_BASE, PAGE_SIZE);
  591. #endif
  592. #ifdef CONFIG_ACPI_SLEEP
  593. /*
  594. * Reserve low memory region for sleep support.
  595. */
  596. acpi_reserve_bootmem();
  597. #endif
  598. #ifdef CONFIG_X86_LOCAL_APIC
  599. /*
  600. * Find and reserve possible boot-time SMP configuration:
  601. */
  602. find_smp_config();
  603. #endif
  604. #ifdef CONFIG_BLK_DEV_INITRD
  605. if (LOADER_TYPE && INITRD_START) {
  606. if (INITRD_START + INITRD_SIZE <= (end_pfn << PAGE_SHIFT)) {
  607. reserve_bootmem_generic(INITRD_START, INITRD_SIZE);
  608. initrd_start =
  609. INITRD_START ? INITRD_START + PAGE_OFFSET : 0;
  610. initrd_end = initrd_start+INITRD_SIZE;
  611. }
  612. else {
  613. printk(KERN_ERR "initrd extends beyond end of memory "
  614. "(0x%08lx > 0x%08lx)\ndisabling initrd\n",
  615. (unsigned long)(INITRD_START + INITRD_SIZE),
  616. (unsigned long)(end_pfn << PAGE_SHIFT));
  617. initrd_start = 0;
  618. }
  619. }
  620. #endif
  621. #ifdef CONFIG_KEXEC
  622. if (crashk_res.start != crashk_res.end) {
  623. reserve_bootmem_generic(crashk_res.start,
  624. crashk_res.end - crashk_res.start + 1);
  625. }
  626. #endif
  627. paging_init();
  628. check_ioapic();
  629. /*
  630. * set this early, so we dont allocate cpu0
  631. * if MADT list doesnt list BSP first
  632. * mpparse.c/MP_processor_info() allocates logical cpu numbers.
  633. */
  634. cpu_set(0, cpu_present_map);
  635. #ifdef CONFIG_ACPI
  636. /*
  637. * Read APIC and some other early information from ACPI tables.
  638. */
  639. acpi_boot_init();
  640. #endif
  641. init_cpu_to_node();
  642. #ifdef CONFIG_X86_LOCAL_APIC
  643. /*
  644. * get boot-time SMP configuration:
  645. */
  646. if (smp_found_config)
  647. get_smp_config();
  648. init_apic_mappings();
  649. #endif
  650. /*
  651. * Request address space for all standard RAM and ROM resources
  652. * and also for regions reported as reserved by the e820.
  653. */
  654. probe_roms();
  655. e820_reserve_resources();
  656. request_resource(&iomem_resource, &video_ram_resource);
  657. {
  658. unsigned i;
  659. /* request I/O space for devices used on all i[345]86 PCs */
  660. for (i = 0; i < STANDARD_IO_RESOURCES; i++)
  661. request_resource(&ioport_resource, &standard_io_resources[i]);
  662. }
  663. e820_setup_gap();
  664. #ifdef CONFIG_GART_IOMMU
  665. iommu_hole_init();
  666. #endif
  667. #ifdef CONFIG_VT
  668. #if defined(CONFIG_VGA_CONSOLE)
  669. conswitchp = &vga_con;
  670. #elif defined(CONFIG_DUMMY_CONSOLE)
  671. conswitchp = &dummy_con;
  672. #endif
  673. #endif
  674. }
  675. static int __cpuinit get_model_name(struct cpuinfo_x86 *c)
  676. {
  677. unsigned int *v;
  678. if (c->extended_cpuid_level < 0x80000004)
  679. return 0;
  680. v = (unsigned int *) c->x86_model_id;
  681. cpuid(0x80000002, &v[0], &v[1], &v[2], &v[3]);
  682. cpuid(0x80000003, &v[4], &v[5], &v[6], &v[7]);
  683. cpuid(0x80000004, &v[8], &v[9], &v[10], &v[11]);
  684. c->x86_model_id[48] = 0;
  685. return 1;
  686. }
  687. static void __cpuinit display_cacheinfo(struct cpuinfo_x86 *c)
  688. {
  689. unsigned int n, dummy, eax, ebx, ecx, edx;
  690. n = c->extended_cpuid_level;
  691. if (n >= 0x80000005) {
  692. cpuid(0x80000005, &dummy, &ebx, &ecx, &edx);
  693. printk(KERN_INFO "CPU: L1 I Cache: %dK (%d bytes/line), D cache %dK (%d bytes/line)\n",
  694. edx>>24, edx&0xFF, ecx>>24, ecx&0xFF);
  695. c->x86_cache_size=(ecx>>24)+(edx>>24);
  696. /* On K8 L1 TLB is inclusive, so don't count it */
  697. c->x86_tlbsize = 0;
  698. }
  699. if (n >= 0x80000006) {
  700. cpuid(0x80000006, &dummy, &ebx, &ecx, &edx);
  701. ecx = cpuid_ecx(0x80000006);
  702. c->x86_cache_size = ecx >> 16;
  703. c->x86_tlbsize += ((ebx >> 16) & 0xfff) + (ebx & 0xfff);
  704. printk(KERN_INFO "CPU: L2 Cache: %dK (%d bytes/line)\n",
  705. c->x86_cache_size, ecx & 0xFF);
  706. }
  707. if (n >= 0x80000007)
  708. cpuid(0x80000007, &dummy, &dummy, &dummy, &c->x86_power);
  709. if (n >= 0x80000008) {
  710. cpuid(0x80000008, &eax, &dummy, &dummy, &dummy);
  711. c->x86_virt_bits = (eax >> 8) & 0xff;
  712. c->x86_phys_bits = eax & 0xff;
  713. }
  714. }
  715. #ifdef CONFIG_NUMA
  716. static int nearby_node(int apicid)
  717. {
  718. int i;
  719. for (i = apicid - 1; i >= 0; i--) {
  720. int node = apicid_to_node[i];
  721. if (node != NUMA_NO_NODE && node_online(node))
  722. return node;
  723. }
  724. for (i = apicid + 1; i < MAX_LOCAL_APIC; i++) {
  725. int node = apicid_to_node[i];
  726. if (node != NUMA_NO_NODE && node_online(node))
  727. return node;
  728. }
  729. return first_node(node_online_map); /* Shouldn't happen */
  730. }
  731. #endif
  732. /*
  733. * On a AMD dual core setup the lower bits of the APIC id distingush the cores.
  734. * Assumes number of cores is a power of two.
  735. */
  736. static void __init amd_detect_cmp(struct cpuinfo_x86 *c)
  737. {
  738. #ifdef CONFIG_SMP
  739. int cpu = smp_processor_id();
  740. unsigned bits;
  741. #ifdef CONFIG_NUMA
  742. int node = 0;
  743. unsigned apicid = hard_smp_processor_id();
  744. #endif
  745. bits = 0;
  746. while ((1 << bits) < c->x86_max_cores)
  747. bits++;
  748. /* Low order bits define the core id (index of core in socket) */
  749. cpu_core_id[cpu] = phys_proc_id[cpu] & ((1 << bits)-1);
  750. /* Convert the APIC ID into the socket ID */
  751. phys_proc_id[cpu] = phys_pkg_id(bits);
  752. #ifdef CONFIG_NUMA
  753. node = phys_proc_id[cpu];
  754. if (apicid_to_node[apicid] != NUMA_NO_NODE)
  755. node = apicid_to_node[apicid];
  756. if (!node_online(node)) {
  757. /* Two possibilities here:
  758. - The CPU is missing memory and no node was created.
  759. In that case try picking one from a nearby CPU
  760. - The APIC IDs differ from the HyperTransport node IDs
  761. which the K8 northbridge parsing fills in.
  762. Assume they are all increased by a constant offset,
  763. but in the same order as the HT nodeids.
  764. If that doesn't result in a usable node fall back to the
  765. path for the previous case. */
  766. int ht_nodeid = apicid - (phys_proc_id[0] << bits);
  767. if (ht_nodeid >= 0 &&
  768. apicid_to_node[ht_nodeid] != NUMA_NO_NODE)
  769. node = apicid_to_node[ht_nodeid];
  770. /* Pick a nearby node */
  771. if (!node_online(node))
  772. node = nearby_node(apicid);
  773. }
  774. numa_set_node(cpu, node);
  775. printk(KERN_INFO "CPU %d/%x(%d) -> Node %d -> Core %d\n",
  776. cpu, apicid, c->x86_max_cores, node, cpu_core_id[cpu]);
  777. #endif
  778. #endif
  779. }
  780. static int __init init_amd(struct cpuinfo_x86 *c)
  781. {
  782. int r;
  783. unsigned level;
  784. #ifdef CONFIG_SMP
  785. unsigned long value;
  786. /*
  787. * Disable TLB flush filter by setting HWCR.FFDIS on K8
  788. * bit 6 of msr C001_0015
  789. *
  790. * Errata 63 for SH-B3 steppings
  791. * Errata 122 for all steppings (F+ have it disabled by default)
  792. */
  793. if (c->x86 == 15) {
  794. rdmsrl(MSR_K8_HWCR, value);
  795. value |= 1 << 6;
  796. wrmsrl(MSR_K8_HWCR, value);
  797. }
  798. #endif
  799. /* Bit 31 in normal CPUID used for nonstandard 3DNow ID;
  800. 3DNow is IDd by bit 31 in extended CPUID (1*32+31) anyway */
  801. clear_bit(0*32+31, &c->x86_capability);
  802. /* On C+ stepping K8 rep microcode works well for copy/memset */
  803. level = cpuid_eax(1);
  804. if (c->x86 == 15 && ((level >= 0x0f48 && level < 0x0f50) || level >= 0x0f58))
  805. set_bit(X86_FEATURE_REP_GOOD, &c->x86_capability);
  806. /* Enable workaround for FXSAVE leak */
  807. if (c->x86 >= 6)
  808. set_bit(X86_FEATURE_FXSAVE_LEAK, &c->x86_capability);
  809. r = get_model_name(c);
  810. if (!r) {
  811. switch (c->x86) {
  812. case 15:
  813. /* Should distinguish Models here, but this is only
  814. a fallback anyways. */
  815. strcpy(c->x86_model_id, "Hammer");
  816. break;
  817. }
  818. }
  819. display_cacheinfo(c);
  820. /* c->x86_power is 8000_0007 edx. Bit 8 is constant TSC */
  821. if (c->x86_power & (1<<8))
  822. set_bit(X86_FEATURE_CONSTANT_TSC, &c->x86_capability);
  823. if (c->extended_cpuid_level >= 0x80000008) {
  824. c->x86_max_cores = (cpuid_ecx(0x80000008) & 0xff) + 1;
  825. amd_detect_cmp(c);
  826. }
  827. return r;
  828. }
  829. static void __cpuinit detect_ht(struct cpuinfo_x86 *c)
  830. {
  831. #ifdef CONFIG_SMP
  832. u32 eax, ebx, ecx, edx;
  833. int index_msb, core_bits;
  834. int cpu = smp_processor_id();
  835. cpuid(1, &eax, &ebx, &ecx, &edx);
  836. if (!cpu_has(c, X86_FEATURE_HT) || cpu_has(c, X86_FEATURE_CMP_LEGACY))
  837. return;
  838. smp_num_siblings = (ebx & 0xff0000) >> 16;
  839. if (smp_num_siblings == 1) {
  840. printk(KERN_INFO "CPU: Hyper-Threading is disabled\n");
  841. } else if (smp_num_siblings > 1 ) {
  842. if (smp_num_siblings > NR_CPUS) {
  843. printk(KERN_WARNING "CPU: Unsupported number of the siblings %d", smp_num_siblings);
  844. smp_num_siblings = 1;
  845. return;
  846. }
  847. index_msb = get_count_order(smp_num_siblings);
  848. phys_proc_id[cpu] = phys_pkg_id(index_msb);
  849. printk(KERN_INFO "CPU: Physical Processor ID: %d\n",
  850. phys_proc_id[cpu]);
  851. smp_num_siblings = smp_num_siblings / c->x86_max_cores;
  852. index_msb = get_count_order(smp_num_siblings) ;
  853. core_bits = get_count_order(c->x86_max_cores);
  854. cpu_core_id[cpu] = phys_pkg_id(index_msb) &
  855. ((1 << core_bits) - 1);
  856. if (c->x86_max_cores > 1)
  857. printk(KERN_INFO "CPU: Processor Core ID: %d\n",
  858. cpu_core_id[cpu]);
  859. }
  860. #endif
  861. }
  862. /*
  863. * find out the number of processor cores on the die
  864. */
  865. static int __cpuinit intel_num_cpu_cores(struct cpuinfo_x86 *c)
  866. {
  867. unsigned int eax;
  868. if (c->cpuid_level < 4)
  869. return 1;
  870. __asm__("cpuid"
  871. : "=a" (eax)
  872. : "0" (4), "c" (0)
  873. : "bx", "dx");
  874. if (eax & 0x1f)
  875. return ((eax >> 26) + 1);
  876. else
  877. return 1;
  878. }
  879. static void srat_detect_node(void)
  880. {
  881. #ifdef CONFIG_NUMA
  882. unsigned node;
  883. int cpu = smp_processor_id();
  884. /* Don't do the funky fallback heuristics the AMD version employs
  885. for now. */
  886. node = apicid_to_node[hard_smp_processor_id()];
  887. if (node == NUMA_NO_NODE)
  888. node = first_node(node_online_map);
  889. numa_set_node(cpu, node);
  890. if (acpi_numa > 0)
  891. printk(KERN_INFO "CPU %d -> Node %d\n", cpu, node);
  892. #endif
  893. }
  894. static void __cpuinit init_intel(struct cpuinfo_x86 *c)
  895. {
  896. /* Cache sizes */
  897. unsigned n;
  898. init_intel_cacheinfo(c);
  899. n = c->extended_cpuid_level;
  900. if (n >= 0x80000008) {
  901. unsigned eax = cpuid_eax(0x80000008);
  902. c->x86_virt_bits = (eax >> 8) & 0xff;
  903. c->x86_phys_bits = eax & 0xff;
  904. /* CPUID workaround for Intel 0F34 CPU */
  905. if (c->x86_vendor == X86_VENDOR_INTEL &&
  906. c->x86 == 0xF && c->x86_model == 0x3 &&
  907. c->x86_mask == 0x4)
  908. c->x86_phys_bits = 36;
  909. }
  910. if (c->x86 == 15)
  911. c->x86_cache_alignment = c->x86_clflush_size * 2;
  912. if ((c->x86 == 0xf && c->x86_model >= 0x03) ||
  913. (c->x86 == 0x6 && c->x86_model >= 0x0e))
  914. set_bit(X86_FEATURE_CONSTANT_TSC, &c->x86_capability);
  915. set_bit(X86_FEATURE_SYNC_RDTSC, &c->x86_capability);
  916. c->x86_max_cores = intel_num_cpu_cores(c);
  917. srat_detect_node();
  918. }
  919. static void __cpuinit get_cpu_vendor(struct cpuinfo_x86 *c)
  920. {
  921. char *v = c->x86_vendor_id;
  922. if (!strcmp(v, "AuthenticAMD"))
  923. c->x86_vendor = X86_VENDOR_AMD;
  924. else if (!strcmp(v, "GenuineIntel"))
  925. c->x86_vendor = X86_VENDOR_INTEL;
  926. else
  927. c->x86_vendor = X86_VENDOR_UNKNOWN;
  928. }
  929. struct cpu_model_info {
  930. int vendor;
  931. int family;
  932. char *model_names[16];
  933. };
  934. /* Do some early cpuid on the boot CPU to get some parameter that are
  935. needed before check_bugs. Everything advanced is in identify_cpu
  936. below. */
  937. void __cpuinit early_identify_cpu(struct cpuinfo_x86 *c)
  938. {
  939. u32 tfms;
  940. c->loops_per_jiffy = loops_per_jiffy;
  941. c->x86_cache_size = -1;
  942. c->x86_vendor = X86_VENDOR_UNKNOWN;
  943. c->x86_model = c->x86_mask = 0; /* So far unknown... */
  944. c->x86_vendor_id[0] = '\0'; /* Unset */
  945. c->x86_model_id[0] = '\0'; /* Unset */
  946. c->x86_clflush_size = 64;
  947. c->x86_cache_alignment = c->x86_clflush_size;
  948. c->x86_max_cores = 1;
  949. c->extended_cpuid_level = 0;
  950. memset(&c->x86_capability, 0, sizeof c->x86_capability);
  951. /* Get vendor name */
  952. cpuid(0x00000000, (unsigned int *)&c->cpuid_level,
  953. (unsigned int *)&c->x86_vendor_id[0],
  954. (unsigned int *)&c->x86_vendor_id[8],
  955. (unsigned int *)&c->x86_vendor_id[4]);
  956. get_cpu_vendor(c);
  957. /* Initialize the standard set of capabilities */
  958. /* Note that the vendor-specific code below might override */
  959. /* Intel-defined flags: level 0x00000001 */
  960. if (c->cpuid_level >= 0x00000001) {
  961. __u32 misc;
  962. cpuid(0x00000001, &tfms, &misc, &c->x86_capability[4],
  963. &c->x86_capability[0]);
  964. c->x86 = (tfms >> 8) & 0xf;
  965. c->x86_model = (tfms >> 4) & 0xf;
  966. c->x86_mask = tfms & 0xf;
  967. if (c->x86 == 0xf)
  968. c->x86 += (tfms >> 20) & 0xff;
  969. if (c->x86 >= 0x6)
  970. c->x86_model += ((tfms >> 16) & 0xF) << 4;
  971. if (c->x86_capability[0] & (1<<19))
  972. c->x86_clflush_size = ((misc >> 8) & 0xff) * 8;
  973. } else {
  974. /* Have CPUID level 0 only - unheard of */
  975. c->x86 = 4;
  976. }
  977. #ifdef CONFIG_SMP
  978. phys_proc_id[smp_processor_id()] = (cpuid_ebx(1) >> 24) & 0xff;
  979. #endif
  980. }
  981. /*
  982. * This does the hard work of actually picking apart the CPU stuff...
  983. */
  984. void __cpuinit identify_cpu(struct cpuinfo_x86 *c)
  985. {
  986. int i;
  987. u32 xlvl;
  988. early_identify_cpu(c);
  989. /* AMD-defined flags: level 0x80000001 */
  990. xlvl = cpuid_eax(0x80000000);
  991. c->extended_cpuid_level = xlvl;
  992. if ((xlvl & 0xffff0000) == 0x80000000) {
  993. if (xlvl >= 0x80000001) {
  994. c->x86_capability[1] = cpuid_edx(0x80000001);
  995. c->x86_capability[6] = cpuid_ecx(0x80000001);
  996. }
  997. if (xlvl >= 0x80000004)
  998. get_model_name(c); /* Default name */
  999. }
  1000. /* Transmeta-defined flags: level 0x80860001 */
  1001. xlvl = cpuid_eax(0x80860000);
  1002. if ((xlvl & 0xffff0000) == 0x80860000) {
  1003. /* Don't set x86_cpuid_level here for now to not confuse. */
  1004. if (xlvl >= 0x80860001)
  1005. c->x86_capability[2] = cpuid_edx(0x80860001);
  1006. }
  1007. c->apicid = phys_pkg_id(0);
  1008. /*
  1009. * Vendor-specific initialization. In this section we
  1010. * canonicalize the feature flags, meaning if there are
  1011. * features a certain CPU supports which CPUID doesn't
  1012. * tell us, CPUID claiming incorrect flags, or other bugs,
  1013. * we handle them here.
  1014. *
  1015. * At the end of this section, c->x86_capability better
  1016. * indicate the features this CPU genuinely supports!
  1017. */
  1018. switch (c->x86_vendor) {
  1019. case X86_VENDOR_AMD:
  1020. init_amd(c);
  1021. break;
  1022. case X86_VENDOR_INTEL:
  1023. init_intel(c);
  1024. break;
  1025. case X86_VENDOR_UNKNOWN:
  1026. default:
  1027. display_cacheinfo(c);
  1028. break;
  1029. }
  1030. select_idle_routine(c);
  1031. detect_ht(c);
  1032. /*
  1033. * On SMP, boot_cpu_data holds the common feature set between
  1034. * all CPUs; so make sure that we indicate which features are
  1035. * common between the CPUs. The first time this routine gets
  1036. * executed, c == &boot_cpu_data.
  1037. */
  1038. if (c != &boot_cpu_data) {
  1039. /* AND the already accumulated flags with these */
  1040. for (i = 0 ; i < NCAPINTS ; i++)
  1041. boot_cpu_data.x86_capability[i] &= c->x86_capability[i];
  1042. }
  1043. #ifdef CONFIG_X86_MCE
  1044. mcheck_init(c);
  1045. #endif
  1046. if (c == &boot_cpu_data)
  1047. mtrr_bp_init();
  1048. else
  1049. mtrr_ap_init();
  1050. #ifdef CONFIG_NUMA
  1051. numa_add_cpu(smp_processor_id());
  1052. #endif
  1053. }
  1054. void __cpuinit print_cpu_info(struct cpuinfo_x86 *c)
  1055. {
  1056. if (c->x86_model_id[0])
  1057. printk("%s", c->x86_model_id);
  1058. if (c->x86_mask || c->cpuid_level >= 0)
  1059. printk(" stepping %02x\n", c->x86_mask);
  1060. else
  1061. printk("\n");
  1062. }
  1063. /*
  1064. * Get CPU information for use by the procfs.
  1065. */
  1066. static int show_cpuinfo(struct seq_file *m, void *v)
  1067. {
  1068. struct cpuinfo_x86 *c = v;
  1069. /*
  1070. * These flag bits must match the definitions in <asm/cpufeature.h>.
  1071. * NULL means this bit is undefined or reserved; either way it doesn't
  1072. * have meaning as far as Linux is concerned. Note that it's important
  1073. * to realize there is a difference between this table and CPUID -- if
  1074. * applications want to get the raw CPUID data, they should access
  1075. * /dev/cpu/<cpu_nr>/cpuid instead.
  1076. */
  1077. static char *x86_cap_flags[] = {
  1078. /* Intel-defined */
  1079. "fpu", "vme", "de", "pse", "tsc", "msr", "pae", "mce",
  1080. "cx8", "apic", NULL, "sep", "mtrr", "pge", "mca", "cmov",
  1081. "pat", "pse36", "pn", "clflush", NULL, "dts", "acpi", "mmx",
  1082. "fxsr", "sse", "sse2", "ss", "ht", "tm", "ia64", NULL,
  1083. /* AMD-defined */
  1084. NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL,
  1085. NULL, NULL, NULL, "syscall", NULL, NULL, NULL, NULL,
  1086. NULL, NULL, NULL, NULL, "nx", NULL, "mmxext", NULL,
  1087. NULL, "fxsr_opt", "rdtscp", NULL, NULL, "lm", "3dnowext", "3dnow",
  1088. /* Transmeta-defined */
  1089. "recovery", "longrun", NULL, "lrti", NULL, NULL, NULL, NULL,
  1090. NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL,
  1091. NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL,
  1092. NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL,
  1093. /* Other (Linux-defined) */
  1094. "cxmmx", NULL, "cyrix_arr", "centaur_mcr", NULL,
  1095. "constant_tsc", NULL, NULL,
  1096. NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL,
  1097. NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL,
  1098. NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL,
  1099. /* Intel-defined (#2) */
  1100. "pni", NULL, NULL, "monitor", "ds_cpl", "vmx", "smx", "est",
  1101. "tm2", NULL, "cid", NULL, NULL, "cx16", "xtpr", NULL,
  1102. NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL,
  1103. NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL,
  1104. /* VIA/Cyrix/Centaur-defined */
  1105. NULL, NULL, "rng", "rng_en", NULL, NULL, "ace", "ace_en",
  1106. NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL,
  1107. NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL,
  1108. NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL,
  1109. /* AMD-defined (#2) */
  1110. "lahf_lm", "cmp_legacy", "svm", NULL, "cr8_legacy", NULL, NULL, NULL,
  1111. NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL,
  1112. NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL,
  1113. NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL,
  1114. };
  1115. static char *x86_power_flags[] = {
  1116. "ts", /* temperature sensor */
  1117. "fid", /* frequency id control */
  1118. "vid", /* voltage id control */
  1119. "ttp", /* thermal trip */
  1120. "tm",
  1121. "stc",
  1122. NULL,
  1123. /* nothing */ /* constant_tsc - moved to flags */
  1124. };
  1125. #ifdef CONFIG_SMP
  1126. if (!cpu_online(c-cpu_data))
  1127. return 0;
  1128. #endif
  1129. seq_printf(m,"processor\t: %u\n"
  1130. "vendor_id\t: %s\n"
  1131. "cpu family\t: %d\n"
  1132. "model\t\t: %d\n"
  1133. "model name\t: %s\n",
  1134. (unsigned)(c-cpu_data),
  1135. c->x86_vendor_id[0] ? c->x86_vendor_id : "unknown",
  1136. c->x86,
  1137. (int)c->x86_model,
  1138. c->x86_model_id[0] ? c->x86_model_id : "unknown");
  1139. if (c->x86_mask || c->cpuid_level >= 0)
  1140. seq_printf(m, "stepping\t: %d\n", c->x86_mask);
  1141. else
  1142. seq_printf(m, "stepping\t: unknown\n");
  1143. if (cpu_has(c,X86_FEATURE_TSC)) {
  1144. unsigned int freq = cpufreq_quick_get((unsigned)(c-cpu_data));
  1145. if (!freq)
  1146. freq = cpu_khz;
  1147. seq_printf(m, "cpu MHz\t\t: %u.%03u\n",
  1148. freq / 1000, (freq % 1000));
  1149. }
  1150. /* Cache size */
  1151. if (c->x86_cache_size >= 0)
  1152. seq_printf(m, "cache size\t: %d KB\n", c->x86_cache_size);
  1153. #ifdef CONFIG_SMP
  1154. if (smp_num_siblings * c->x86_max_cores > 1) {
  1155. int cpu = c - cpu_data;
  1156. seq_printf(m, "physical id\t: %d\n", phys_proc_id[cpu]);
  1157. seq_printf(m, "siblings\t: %d\n", cpus_weight(cpu_core_map[cpu]));
  1158. seq_printf(m, "core id\t\t: %d\n", cpu_core_id[cpu]);
  1159. seq_printf(m, "cpu cores\t: %d\n", c->booted_cores);
  1160. }
  1161. #endif
  1162. seq_printf(m,
  1163. "fpu\t\t: yes\n"
  1164. "fpu_exception\t: yes\n"
  1165. "cpuid level\t: %d\n"
  1166. "wp\t\t: yes\n"
  1167. "flags\t\t:",
  1168. c->cpuid_level);
  1169. {
  1170. int i;
  1171. for ( i = 0 ; i < 32*NCAPINTS ; i++ )
  1172. if (cpu_has(c, i) && x86_cap_flags[i] != NULL)
  1173. seq_printf(m, " %s", x86_cap_flags[i]);
  1174. }
  1175. seq_printf(m, "\nbogomips\t: %lu.%02lu\n",
  1176. c->loops_per_jiffy/(500000/HZ),
  1177. (c->loops_per_jiffy/(5000/HZ)) % 100);
  1178. if (c->x86_tlbsize > 0)
  1179. seq_printf(m, "TLB size\t: %d 4K pages\n", c->x86_tlbsize);
  1180. seq_printf(m, "clflush size\t: %d\n", c->x86_clflush_size);
  1181. seq_printf(m, "cache_alignment\t: %d\n", c->x86_cache_alignment);
  1182. seq_printf(m, "address sizes\t: %u bits physical, %u bits virtual\n",
  1183. c->x86_phys_bits, c->x86_virt_bits);
  1184. seq_printf(m, "power management:");
  1185. {
  1186. unsigned i;
  1187. for (i = 0; i < 32; i++)
  1188. if (c->x86_power & (1 << i)) {
  1189. if (i < ARRAY_SIZE(x86_power_flags) &&
  1190. x86_power_flags[i])
  1191. seq_printf(m, "%s%s",
  1192. x86_power_flags[i][0]?" ":"",
  1193. x86_power_flags[i]);
  1194. else
  1195. seq_printf(m, " [%d]", i);
  1196. }
  1197. }
  1198. seq_printf(m, "\n\n");
  1199. return 0;
  1200. }
  1201. static void *c_start(struct seq_file *m, loff_t *pos)
  1202. {
  1203. return *pos < NR_CPUS ? cpu_data + *pos : NULL;
  1204. }
  1205. static void *c_next(struct seq_file *m, void *v, loff_t *pos)
  1206. {
  1207. ++*pos;
  1208. return c_start(m, pos);
  1209. }
  1210. static void c_stop(struct seq_file *m, void *v)
  1211. {
  1212. }
  1213. struct seq_operations cpuinfo_op = {
  1214. .start =c_start,
  1215. .next = c_next,
  1216. .stop = c_stop,
  1217. .show = show_cpuinfo,
  1218. };
  1219. #ifdef CONFIG_INPUT_PCSPKR
  1220. #include <linux/platform_device.h>
  1221. static __init int add_pcspkr(void)
  1222. {
  1223. struct platform_device *pd;
  1224. int ret;
  1225. pd = platform_device_alloc("pcspkr", -1);
  1226. if (!pd)
  1227. return -ENOMEM;
  1228. ret = platform_device_add(pd);
  1229. if (ret)
  1230. platform_device_put(pd);
  1231. return ret;
  1232. }
  1233. device_initcall(add_pcspkr);
  1234. #endif