intel_crt.c 15 KB

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  1. /*
  2. * Copyright © 2006-2007 Intel Corporation
  3. *
  4. * Permission is hereby granted, free of charge, to any person obtaining a
  5. * copy of this software and associated documentation files (the "Software"),
  6. * to deal in the Software without restriction, including without limitation
  7. * the rights to use, copy, modify, merge, publish, distribute, sublicense,
  8. * and/or sell copies of the Software, and to permit persons to whom the
  9. * Software is furnished to do so, subject to the following conditions:
  10. *
  11. * The above copyright notice and this permission notice (including the next
  12. * paragraph) shall be included in all copies or substantial portions of the
  13. * Software.
  14. *
  15. * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16. * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17. * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
  18. * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19. * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20. * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
  21. * DEALINGS IN THE SOFTWARE.
  22. *
  23. * Authors:
  24. * Eric Anholt <eric@anholt.net>
  25. */
  26. #include <linux/i2c.h>
  27. #include <linux/slab.h>
  28. #include "drmP.h"
  29. #include "drm.h"
  30. #include "drm_crtc.h"
  31. #include "drm_crtc_helper.h"
  32. #include "intel_drv.h"
  33. #include "i915_drm.h"
  34. #include "i915_drv.h"
  35. static void intel_crt_dpms(struct drm_encoder *encoder, int mode)
  36. {
  37. struct drm_device *dev = encoder->dev;
  38. struct drm_i915_private *dev_priv = dev->dev_private;
  39. u32 temp, reg;
  40. if (HAS_PCH_SPLIT(dev))
  41. reg = PCH_ADPA;
  42. else
  43. reg = ADPA;
  44. temp = I915_READ(reg);
  45. temp &= ~(ADPA_HSYNC_CNTL_DISABLE | ADPA_VSYNC_CNTL_DISABLE);
  46. temp &= ~ADPA_DAC_ENABLE;
  47. switch(mode) {
  48. case DRM_MODE_DPMS_ON:
  49. temp |= ADPA_DAC_ENABLE;
  50. break;
  51. case DRM_MODE_DPMS_STANDBY:
  52. temp |= ADPA_DAC_ENABLE | ADPA_HSYNC_CNTL_DISABLE;
  53. break;
  54. case DRM_MODE_DPMS_SUSPEND:
  55. temp |= ADPA_DAC_ENABLE | ADPA_VSYNC_CNTL_DISABLE;
  56. break;
  57. case DRM_MODE_DPMS_OFF:
  58. temp |= ADPA_HSYNC_CNTL_DISABLE | ADPA_VSYNC_CNTL_DISABLE;
  59. break;
  60. }
  61. I915_WRITE(reg, temp);
  62. }
  63. static int intel_crt_mode_valid(struct drm_connector *connector,
  64. struct drm_display_mode *mode)
  65. {
  66. struct drm_device *dev = connector->dev;
  67. int max_clock = 0;
  68. if (mode->flags & DRM_MODE_FLAG_DBLSCAN)
  69. return MODE_NO_DBLESCAN;
  70. if (mode->clock < 25000)
  71. return MODE_CLOCK_LOW;
  72. if (IS_GEN2(dev))
  73. max_clock = 350000;
  74. else
  75. max_clock = 400000;
  76. if (mode->clock > max_clock)
  77. return MODE_CLOCK_HIGH;
  78. return MODE_OK;
  79. }
  80. static bool intel_crt_mode_fixup(struct drm_encoder *encoder,
  81. struct drm_display_mode *mode,
  82. struct drm_display_mode *adjusted_mode)
  83. {
  84. return true;
  85. }
  86. static void intel_crt_mode_set(struct drm_encoder *encoder,
  87. struct drm_display_mode *mode,
  88. struct drm_display_mode *adjusted_mode)
  89. {
  90. struct drm_device *dev = encoder->dev;
  91. struct drm_crtc *crtc = encoder->crtc;
  92. struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
  93. struct drm_i915_private *dev_priv = dev->dev_private;
  94. int dpll_md_reg;
  95. u32 adpa, dpll_md;
  96. u32 adpa_reg;
  97. if (intel_crtc->pipe == 0)
  98. dpll_md_reg = DPLL_A_MD;
  99. else
  100. dpll_md_reg = DPLL_B_MD;
  101. if (HAS_PCH_SPLIT(dev))
  102. adpa_reg = PCH_ADPA;
  103. else
  104. adpa_reg = ADPA;
  105. /*
  106. * Disable separate mode multiplier used when cloning SDVO to CRT
  107. * XXX this needs to be adjusted when we really are cloning
  108. */
  109. if (INTEL_INFO(dev)->gen >= 4 && !HAS_PCH_SPLIT(dev)) {
  110. dpll_md = I915_READ(dpll_md_reg);
  111. I915_WRITE(dpll_md_reg,
  112. dpll_md & ~DPLL_MD_UDI_MULTIPLIER_MASK);
  113. }
  114. adpa = 0;
  115. if (adjusted_mode->flags & DRM_MODE_FLAG_PHSYNC)
  116. adpa |= ADPA_HSYNC_ACTIVE_HIGH;
  117. if (adjusted_mode->flags & DRM_MODE_FLAG_PVSYNC)
  118. adpa |= ADPA_VSYNC_ACTIVE_HIGH;
  119. if (intel_crtc->pipe == 0) {
  120. if (HAS_PCH_CPT(dev))
  121. adpa |= PORT_TRANS_A_SEL_CPT;
  122. else
  123. adpa |= ADPA_PIPE_A_SELECT;
  124. if (!HAS_PCH_SPLIT(dev))
  125. I915_WRITE(BCLRPAT_A, 0);
  126. } else {
  127. if (HAS_PCH_CPT(dev))
  128. adpa |= PORT_TRANS_B_SEL_CPT;
  129. else
  130. adpa |= ADPA_PIPE_B_SELECT;
  131. if (!HAS_PCH_SPLIT(dev))
  132. I915_WRITE(BCLRPAT_B, 0);
  133. }
  134. I915_WRITE(adpa_reg, adpa);
  135. }
  136. static bool intel_ironlake_crt_detect_hotplug(struct drm_connector *connector)
  137. {
  138. struct drm_device *dev = connector->dev;
  139. struct drm_i915_private *dev_priv = dev->dev_private;
  140. u32 adpa, temp;
  141. bool ret;
  142. bool turn_off_dac = false;
  143. temp = adpa = I915_READ(PCH_ADPA);
  144. if (HAS_PCH_SPLIT(dev))
  145. turn_off_dac = true;
  146. adpa &= ~ADPA_CRT_HOTPLUG_MASK;
  147. if (turn_off_dac)
  148. adpa &= ~ADPA_DAC_ENABLE;
  149. /* disable HPD first */
  150. I915_WRITE(PCH_ADPA, adpa);
  151. (void)I915_READ(PCH_ADPA);
  152. adpa |= (ADPA_CRT_HOTPLUG_PERIOD_128 |
  153. ADPA_CRT_HOTPLUG_WARMUP_10MS |
  154. ADPA_CRT_HOTPLUG_SAMPLE_4S |
  155. ADPA_CRT_HOTPLUG_VOLTAGE_50 | /* default */
  156. ADPA_CRT_HOTPLUG_VOLREF_325MV |
  157. ADPA_CRT_HOTPLUG_ENABLE |
  158. ADPA_CRT_HOTPLUG_FORCE_TRIGGER);
  159. DRM_DEBUG_KMS("pch crt adpa 0x%x", adpa);
  160. I915_WRITE(PCH_ADPA, adpa);
  161. if (wait_for((I915_READ(PCH_ADPA) & ADPA_CRT_HOTPLUG_FORCE_TRIGGER) == 0,
  162. 1000))
  163. DRM_DEBUG_KMS("timed out waiting for FORCE_TRIGGER");
  164. if (turn_off_dac) {
  165. /* Make sure hotplug is enabled */
  166. I915_WRITE(PCH_ADPA, temp | ADPA_CRT_HOTPLUG_ENABLE);
  167. (void)I915_READ(PCH_ADPA);
  168. }
  169. /* Check the status to see if both blue and green are on now */
  170. adpa = I915_READ(PCH_ADPA);
  171. adpa &= ADPA_CRT_HOTPLUG_MONITOR_MASK;
  172. if ((adpa == ADPA_CRT_HOTPLUG_MONITOR_COLOR) ||
  173. (adpa == ADPA_CRT_HOTPLUG_MONITOR_MONO))
  174. ret = true;
  175. else
  176. ret = false;
  177. return ret;
  178. }
  179. /**
  180. * Uses CRT_HOTPLUG_EN and CRT_HOTPLUG_STAT to detect CRT presence.
  181. *
  182. * Not for i915G/i915GM
  183. *
  184. * \return true if CRT is connected.
  185. * \return false if CRT is disconnected.
  186. */
  187. static bool intel_crt_detect_hotplug(struct drm_connector *connector)
  188. {
  189. struct drm_device *dev = connector->dev;
  190. struct drm_i915_private *dev_priv = dev->dev_private;
  191. u32 hotplug_en, orig, stat;
  192. bool ret = false;
  193. int i, tries = 0;
  194. if (HAS_PCH_SPLIT(dev))
  195. return intel_ironlake_crt_detect_hotplug(connector);
  196. /*
  197. * On 4 series desktop, CRT detect sequence need to be done twice
  198. * to get a reliable result.
  199. */
  200. if (IS_G4X(dev) && !IS_GM45(dev))
  201. tries = 2;
  202. else
  203. tries = 1;
  204. hotplug_en = orig = I915_READ(PORT_HOTPLUG_EN);
  205. hotplug_en |= CRT_HOTPLUG_FORCE_DETECT;
  206. for (i = 0; i < tries ; i++) {
  207. /* turn on the FORCE_DETECT */
  208. I915_WRITE(PORT_HOTPLUG_EN, hotplug_en);
  209. /* wait for FORCE_DETECT to go off */
  210. if (wait_for((I915_READ(PORT_HOTPLUG_EN) &
  211. CRT_HOTPLUG_FORCE_DETECT) == 0,
  212. 1000))
  213. DRM_DEBUG_KMS("timed out waiting for FORCE_DETECT to go off");
  214. }
  215. stat = I915_READ(PORT_HOTPLUG_STAT);
  216. if ((stat & CRT_HOTPLUG_MONITOR_MASK) != CRT_HOTPLUG_MONITOR_NONE)
  217. ret = true;
  218. /* clear the interrupt we just generated, if any */
  219. I915_WRITE(PORT_HOTPLUG_STAT, CRT_HOTPLUG_INT_STATUS);
  220. /* and put the bits back */
  221. I915_WRITE(PORT_HOTPLUG_EN, orig);
  222. return ret;
  223. }
  224. static bool intel_crt_ddc_probe(struct drm_i915_private *dev_priv, int ddc_bus)
  225. {
  226. u8 buf;
  227. struct i2c_msg msgs[] = {
  228. {
  229. .addr = 0xA0,
  230. .flags = 0,
  231. .len = 1,
  232. .buf = &buf,
  233. },
  234. };
  235. /* DDC monitor detect: Does it ACK a write to 0xA0? */
  236. return i2c_transfer(&dev_priv->gmbus[ddc_bus].adapter, msgs, 1) == 1;
  237. }
  238. static bool intel_crt_detect_ddc(struct drm_encoder *encoder)
  239. {
  240. struct intel_encoder *intel_encoder = to_intel_encoder(encoder);
  241. struct drm_i915_private *dev_priv = encoder->dev->dev_private;
  242. /* CRT should always be at 0, but check anyway */
  243. if (intel_encoder->type != INTEL_OUTPUT_ANALOG)
  244. return false;
  245. if (intel_crt_ddc_probe(dev_priv, dev_priv->crt_ddc_pin)) {
  246. DRM_DEBUG_KMS("CRT detected via DDC:0xa0\n");
  247. return true;
  248. }
  249. if (intel_ddc_probe(intel_encoder, dev_priv->crt_ddc_pin)) {
  250. DRM_DEBUG_KMS("CRT detected via DDC:0x50 [EDID]\n");
  251. return true;
  252. }
  253. return false;
  254. }
  255. static enum drm_connector_status
  256. intel_crt_load_detect(struct drm_crtc *crtc, struct intel_encoder *intel_encoder)
  257. {
  258. struct drm_encoder *encoder = &intel_encoder->base;
  259. struct drm_device *dev = encoder->dev;
  260. struct drm_i915_private *dev_priv = dev->dev_private;
  261. struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
  262. uint32_t pipe = intel_crtc->pipe;
  263. uint32_t save_bclrpat;
  264. uint32_t save_vtotal;
  265. uint32_t vtotal, vactive;
  266. uint32_t vsample;
  267. uint32_t vblank, vblank_start, vblank_end;
  268. uint32_t dsl;
  269. uint32_t bclrpat_reg;
  270. uint32_t vtotal_reg;
  271. uint32_t vblank_reg;
  272. uint32_t vsync_reg;
  273. uint32_t pipeconf_reg;
  274. uint32_t pipe_dsl_reg;
  275. uint8_t st00;
  276. enum drm_connector_status status;
  277. DRM_DEBUG_KMS("starting load-detect on CRT\n");
  278. if (pipe == 0) {
  279. bclrpat_reg = BCLRPAT_A;
  280. vtotal_reg = VTOTAL_A;
  281. vblank_reg = VBLANK_A;
  282. vsync_reg = VSYNC_A;
  283. pipeconf_reg = PIPEACONF;
  284. pipe_dsl_reg = PIPEADSL;
  285. } else {
  286. bclrpat_reg = BCLRPAT_B;
  287. vtotal_reg = VTOTAL_B;
  288. vblank_reg = VBLANK_B;
  289. vsync_reg = VSYNC_B;
  290. pipeconf_reg = PIPEBCONF;
  291. pipe_dsl_reg = PIPEBDSL;
  292. }
  293. save_bclrpat = I915_READ(bclrpat_reg);
  294. save_vtotal = I915_READ(vtotal_reg);
  295. vblank = I915_READ(vblank_reg);
  296. vtotal = ((save_vtotal >> 16) & 0xfff) + 1;
  297. vactive = (save_vtotal & 0x7ff) + 1;
  298. vblank_start = (vblank & 0xfff) + 1;
  299. vblank_end = ((vblank >> 16) & 0xfff) + 1;
  300. /* Set the border color to purple. */
  301. I915_WRITE(bclrpat_reg, 0x500050);
  302. if (!IS_GEN2(dev)) {
  303. uint32_t pipeconf = I915_READ(pipeconf_reg);
  304. I915_WRITE(pipeconf_reg, pipeconf | PIPECONF_FORCE_BORDER);
  305. POSTING_READ(pipeconf_reg);
  306. /* Wait for next Vblank to substitue
  307. * border color for Color info */
  308. intel_wait_for_vblank(dev, pipe);
  309. st00 = I915_READ8(VGA_MSR_WRITE);
  310. status = ((st00 & (1 << 4)) != 0) ?
  311. connector_status_connected :
  312. connector_status_disconnected;
  313. I915_WRITE(pipeconf_reg, pipeconf);
  314. } else {
  315. bool restore_vblank = false;
  316. int count, detect;
  317. /*
  318. * If there isn't any border, add some.
  319. * Yes, this will flicker
  320. */
  321. if (vblank_start <= vactive && vblank_end >= vtotal) {
  322. uint32_t vsync = I915_READ(vsync_reg);
  323. uint32_t vsync_start = (vsync & 0xffff) + 1;
  324. vblank_start = vsync_start;
  325. I915_WRITE(vblank_reg,
  326. (vblank_start - 1) |
  327. ((vblank_end - 1) << 16));
  328. restore_vblank = true;
  329. }
  330. /* sample in the vertical border, selecting the larger one */
  331. if (vblank_start - vactive >= vtotal - vblank_end)
  332. vsample = (vblank_start + vactive) >> 1;
  333. else
  334. vsample = (vtotal + vblank_end) >> 1;
  335. /*
  336. * Wait for the border to be displayed
  337. */
  338. while (I915_READ(pipe_dsl_reg) >= vactive)
  339. ;
  340. while ((dsl = I915_READ(pipe_dsl_reg)) <= vsample)
  341. ;
  342. /*
  343. * Watch ST00 for an entire scanline
  344. */
  345. detect = 0;
  346. count = 0;
  347. do {
  348. count++;
  349. /* Read the ST00 VGA status register */
  350. st00 = I915_READ8(VGA_MSR_WRITE);
  351. if (st00 & (1 << 4))
  352. detect++;
  353. } while ((I915_READ(pipe_dsl_reg) == dsl));
  354. /* restore vblank if necessary */
  355. if (restore_vblank)
  356. I915_WRITE(vblank_reg, vblank);
  357. /*
  358. * If more than 3/4 of the scanline detected a monitor,
  359. * then it is assumed to be present. This works even on i830,
  360. * where there isn't any way to force the border color across
  361. * the screen
  362. */
  363. status = detect * 4 > count * 3 ?
  364. connector_status_connected :
  365. connector_status_disconnected;
  366. }
  367. /* Restore previous settings */
  368. I915_WRITE(bclrpat_reg, save_bclrpat);
  369. return status;
  370. }
  371. static enum drm_connector_status
  372. intel_crt_detect(struct drm_connector *connector, bool force)
  373. {
  374. struct drm_device *dev = connector->dev;
  375. struct intel_encoder *encoder = intel_attached_encoder(connector);
  376. struct drm_crtc *crtc;
  377. int dpms_mode;
  378. enum drm_connector_status status;
  379. if (I915_HAS_HOTPLUG(dev)) {
  380. if (intel_crt_detect_hotplug(connector)) {
  381. DRM_DEBUG_KMS("CRT detected via hotplug\n");
  382. return connector_status_connected;
  383. } else
  384. return connector_status_disconnected;
  385. }
  386. if (intel_crt_detect_ddc(&encoder->base))
  387. return connector_status_connected;
  388. if (!force)
  389. return connector->status;
  390. /* for pre-945g platforms use load detect */
  391. if (encoder->base.crtc && encoder->base.crtc->enabled) {
  392. status = intel_crt_load_detect(encoder->base.crtc, encoder);
  393. } else {
  394. crtc = intel_get_load_detect_pipe(encoder, connector,
  395. NULL, &dpms_mode);
  396. if (crtc) {
  397. if (intel_crt_detect_ddc(&encoder->base))
  398. status = connector_status_connected;
  399. else
  400. status = intel_crt_load_detect(crtc, encoder);
  401. intel_release_load_detect_pipe(encoder,
  402. connector, dpms_mode);
  403. } else
  404. status = connector_status_unknown;
  405. }
  406. return status;
  407. }
  408. static void intel_crt_destroy(struct drm_connector *connector)
  409. {
  410. drm_sysfs_connector_remove(connector);
  411. drm_connector_cleanup(connector);
  412. kfree(connector);
  413. }
  414. static int intel_crt_get_modes(struct drm_connector *connector)
  415. {
  416. struct drm_device *dev = connector->dev;
  417. struct drm_i915_private *dev_priv = dev->dev_private;
  418. int ret;
  419. ret = intel_ddc_get_modes(connector,
  420. &dev_priv->gmbus[dev_priv->crt_ddc_pin].adapter);
  421. if (ret || !IS_G4X(dev))
  422. return ret;
  423. /* Try to probe digital port for output in DVI-I -> VGA mode. */
  424. return intel_ddc_get_modes(connector,
  425. &dev_priv->gmbus[GMBUS_PORT_DPB].adapter);
  426. }
  427. static int intel_crt_set_property(struct drm_connector *connector,
  428. struct drm_property *property,
  429. uint64_t value)
  430. {
  431. return 0;
  432. }
  433. /*
  434. * Routines for controlling stuff on the analog port
  435. */
  436. static const struct drm_encoder_helper_funcs intel_crt_helper_funcs = {
  437. .dpms = intel_crt_dpms,
  438. .mode_fixup = intel_crt_mode_fixup,
  439. .prepare = intel_encoder_prepare,
  440. .commit = intel_encoder_commit,
  441. .mode_set = intel_crt_mode_set,
  442. };
  443. static const struct drm_connector_funcs intel_crt_connector_funcs = {
  444. .dpms = drm_helper_connector_dpms,
  445. .detect = intel_crt_detect,
  446. .fill_modes = drm_helper_probe_single_connector_modes,
  447. .destroy = intel_crt_destroy,
  448. .set_property = intel_crt_set_property,
  449. };
  450. static const struct drm_connector_helper_funcs intel_crt_connector_helper_funcs = {
  451. .mode_valid = intel_crt_mode_valid,
  452. .get_modes = intel_crt_get_modes,
  453. .best_encoder = intel_best_encoder,
  454. };
  455. static const struct drm_encoder_funcs intel_crt_enc_funcs = {
  456. .destroy = intel_encoder_destroy,
  457. };
  458. void intel_crt_init(struct drm_device *dev)
  459. {
  460. struct drm_connector *connector;
  461. struct intel_encoder *intel_encoder;
  462. struct intel_connector *intel_connector;
  463. struct drm_i915_private *dev_priv = dev->dev_private;
  464. intel_encoder = kzalloc(sizeof(struct intel_encoder), GFP_KERNEL);
  465. if (!intel_encoder)
  466. return;
  467. intel_connector = kzalloc(sizeof(struct intel_connector), GFP_KERNEL);
  468. if (!intel_connector) {
  469. kfree(intel_encoder);
  470. return;
  471. }
  472. connector = &intel_connector->base;
  473. drm_connector_init(dev, &intel_connector->base,
  474. &intel_crt_connector_funcs, DRM_MODE_CONNECTOR_VGA);
  475. drm_encoder_init(dev, &intel_encoder->base, &intel_crt_enc_funcs,
  476. DRM_MODE_ENCODER_DAC);
  477. intel_connector_attach_encoder(intel_connector, intel_encoder);
  478. intel_encoder->type = INTEL_OUTPUT_ANALOG;
  479. intel_encoder->clone_mask = (1 << INTEL_SDVO_NON_TV_CLONE_BIT) |
  480. (1 << INTEL_ANALOG_CLONE_BIT) |
  481. (1 << INTEL_SDVO_LVDS_CLONE_BIT);
  482. intel_encoder->crtc_mask = (1 << 0) | (1 << 1);
  483. connector->interlace_allowed = 1;
  484. connector->doublescan_allowed = 0;
  485. drm_encoder_helper_add(&intel_encoder->base, &intel_crt_helper_funcs);
  486. drm_connector_helper_add(connector, &intel_crt_connector_helper_funcs);
  487. drm_sysfs_connector_add(connector);
  488. if (I915_HAS_HOTPLUG(dev))
  489. connector->polled = DRM_CONNECTOR_POLL_HPD;
  490. else
  491. connector->polled = DRM_CONNECTOR_POLL_CONNECT;
  492. dev_priv->hotplug_supported_mask |= CRT_HOTPLUG_INT_STATUS;
  493. }