p54pci.c 16 KB

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  1. /*
  2. * Linux device driver for PCI based Prism54
  3. *
  4. * Copyright (c) 2006, Michael Wu <flamingice@sourmilk.net>
  5. * Copyright (c) 2008, Christian Lamparter <chunkeey@web.de>
  6. *
  7. * Based on the islsm (softmac prism54) driver, which is:
  8. * Copyright 2004-2006 Jean-Baptiste Note <jean-baptiste.note@m4x.org>, et al.
  9. *
  10. * This program is free software; you can redistribute it and/or modify
  11. * it under the terms of the GNU General Public License version 2 as
  12. * published by the Free Software Foundation.
  13. */
  14. #include <linux/init.h>
  15. #include <linux/pci.h>
  16. #include <linux/slab.h>
  17. #include <linux/firmware.h>
  18. #include <linux/etherdevice.h>
  19. #include <linux/delay.h>
  20. #include <linux/completion.h>
  21. #include <net/mac80211.h>
  22. #include "p54.h"
  23. #include "lmac.h"
  24. #include "p54pci.h"
  25. MODULE_AUTHOR("Michael Wu <flamingice@sourmilk.net>");
  26. MODULE_DESCRIPTION("Prism54 PCI wireless driver");
  27. MODULE_LICENSE("GPL");
  28. MODULE_ALIAS("prism54pci");
  29. MODULE_FIRMWARE("isl3886pci");
  30. static DEFINE_PCI_DEVICE_TABLE(p54p_table) = {
  31. /* Intersil PRISM Duette/Prism GT Wireless LAN adapter */
  32. { PCI_DEVICE(0x1260, 0x3890) },
  33. /* 3COM 3CRWE154G72 Wireless LAN adapter */
  34. { PCI_DEVICE(0x10b7, 0x6001) },
  35. /* Intersil PRISM Indigo Wireless LAN adapter */
  36. { PCI_DEVICE(0x1260, 0x3877) },
  37. /* Intersil PRISM Javelin/Xbow Wireless LAN adapter */
  38. { PCI_DEVICE(0x1260, 0x3886) },
  39. /* Intersil PRISM Xbow Wireless LAN adapter (Symbol AP-300) */
  40. { PCI_DEVICE(0x1260, 0xffff) },
  41. { },
  42. };
  43. MODULE_DEVICE_TABLE(pci, p54p_table);
  44. static int p54p_upload_firmware(struct ieee80211_hw *dev)
  45. {
  46. struct p54p_priv *priv = dev->priv;
  47. __le32 reg;
  48. int err;
  49. __le32 *data;
  50. u32 remains, left, device_addr;
  51. P54P_WRITE(int_enable, cpu_to_le32(0));
  52. P54P_READ(int_enable);
  53. udelay(10);
  54. reg = P54P_READ(ctrl_stat);
  55. reg &= cpu_to_le32(~ISL38XX_CTRL_STAT_RESET);
  56. reg &= cpu_to_le32(~ISL38XX_CTRL_STAT_RAMBOOT);
  57. P54P_WRITE(ctrl_stat, reg);
  58. P54P_READ(ctrl_stat);
  59. udelay(10);
  60. reg |= cpu_to_le32(ISL38XX_CTRL_STAT_RESET);
  61. P54P_WRITE(ctrl_stat, reg);
  62. wmb();
  63. udelay(10);
  64. reg &= cpu_to_le32(~ISL38XX_CTRL_STAT_RESET);
  65. P54P_WRITE(ctrl_stat, reg);
  66. wmb();
  67. /* wait for the firmware to reset properly */
  68. mdelay(10);
  69. err = p54_parse_firmware(dev, priv->firmware);
  70. if (err)
  71. return err;
  72. if (priv->common.fw_interface != FW_LM86) {
  73. dev_err(&priv->pdev->dev, "wrong firmware, "
  74. "please get a LM86(PCI) firmware a try again.\n");
  75. return -EINVAL;
  76. }
  77. data = (__le32 *) priv->firmware->data;
  78. remains = priv->firmware->size;
  79. device_addr = ISL38XX_DEV_FIRMWARE_ADDR;
  80. while (remains) {
  81. u32 i = 0;
  82. left = min((u32)0x1000, remains);
  83. P54P_WRITE(direct_mem_base, cpu_to_le32(device_addr));
  84. P54P_READ(int_enable);
  85. device_addr += 0x1000;
  86. while (i < left) {
  87. P54P_WRITE(direct_mem_win[i], *data++);
  88. i += sizeof(u32);
  89. }
  90. remains -= left;
  91. P54P_READ(int_enable);
  92. }
  93. reg = P54P_READ(ctrl_stat);
  94. reg &= cpu_to_le32(~ISL38XX_CTRL_STAT_CLKRUN);
  95. reg &= cpu_to_le32(~ISL38XX_CTRL_STAT_RESET);
  96. reg |= cpu_to_le32(ISL38XX_CTRL_STAT_RAMBOOT);
  97. P54P_WRITE(ctrl_stat, reg);
  98. P54P_READ(ctrl_stat);
  99. udelay(10);
  100. reg |= cpu_to_le32(ISL38XX_CTRL_STAT_RESET);
  101. P54P_WRITE(ctrl_stat, reg);
  102. wmb();
  103. udelay(10);
  104. reg &= cpu_to_le32(~ISL38XX_CTRL_STAT_RESET);
  105. P54P_WRITE(ctrl_stat, reg);
  106. wmb();
  107. udelay(10);
  108. /* wait for the firmware to boot properly */
  109. mdelay(100);
  110. return 0;
  111. }
  112. static void p54p_refill_rx_ring(struct ieee80211_hw *dev,
  113. int ring_index, struct p54p_desc *ring, u32 ring_limit,
  114. struct sk_buff **rx_buf, u32 index)
  115. {
  116. struct p54p_priv *priv = dev->priv;
  117. struct p54p_ring_control *ring_control = priv->ring_control;
  118. u32 limit, idx, i;
  119. idx = le32_to_cpu(ring_control->host_idx[ring_index]);
  120. limit = idx;
  121. limit -= index;
  122. limit = ring_limit - limit;
  123. i = idx % ring_limit;
  124. while (limit-- > 1) {
  125. struct p54p_desc *desc = &ring[i];
  126. if (!desc->host_addr) {
  127. struct sk_buff *skb;
  128. dma_addr_t mapping;
  129. skb = dev_alloc_skb(priv->common.rx_mtu + 32);
  130. if (!skb)
  131. break;
  132. mapping = pci_map_single(priv->pdev,
  133. skb_tail_pointer(skb),
  134. priv->common.rx_mtu + 32,
  135. PCI_DMA_FROMDEVICE);
  136. if (pci_dma_mapping_error(priv->pdev, mapping)) {
  137. dev_kfree_skb_any(skb);
  138. dev_err(&priv->pdev->dev,
  139. "RX DMA Mapping error\n");
  140. break;
  141. }
  142. desc->host_addr = cpu_to_le32(mapping);
  143. desc->device_addr = 0; // FIXME: necessary?
  144. desc->len = cpu_to_le16(priv->common.rx_mtu + 32);
  145. desc->flags = 0;
  146. rx_buf[i] = skb;
  147. }
  148. i++;
  149. idx++;
  150. i %= ring_limit;
  151. }
  152. wmb();
  153. ring_control->host_idx[ring_index] = cpu_to_le32(idx);
  154. }
  155. static void p54p_check_rx_ring(struct ieee80211_hw *dev, u32 *index,
  156. int ring_index, struct p54p_desc *ring, u32 ring_limit,
  157. struct sk_buff **rx_buf)
  158. {
  159. struct p54p_priv *priv = dev->priv;
  160. struct p54p_ring_control *ring_control = priv->ring_control;
  161. struct p54p_desc *desc;
  162. u32 idx, i;
  163. i = (*index) % ring_limit;
  164. (*index) = idx = le32_to_cpu(ring_control->device_idx[ring_index]);
  165. idx %= ring_limit;
  166. while (i != idx) {
  167. u16 len;
  168. struct sk_buff *skb;
  169. desc = &ring[i];
  170. len = le16_to_cpu(desc->len);
  171. skb = rx_buf[i];
  172. if (!skb) {
  173. i++;
  174. i %= ring_limit;
  175. continue;
  176. }
  177. if (unlikely(len > priv->common.rx_mtu)) {
  178. if (net_ratelimit())
  179. dev_err(&priv->pdev->dev, "rx'd frame size "
  180. "exceeds length threshold.\n");
  181. len = priv->common.rx_mtu;
  182. }
  183. skb_put(skb, len);
  184. if (p54_rx(dev, skb)) {
  185. pci_unmap_single(priv->pdev,
  186. le32_to_cpu(desc->host_addr),
  187. priv->common.rx_mtu + 32,
  188. PCI_DMA_FROMDEVICE);
  189. rx_buf[i] = NULL;
  190. desc->host_addr = 0;
  191. } else {
  192. skb_trim(skb, 0);
  193. desc->len = cpu_to_le16(priv->common.rx_mtu + 32);
  194. }
  195. i++;
  196. i %= ring_limit;
  197. }
  198. p54p_refill_rx_ring(dev, ring_index, ring, ring_limit, rx_buf, *index);
  199. }
  200. static void p54p_check_tx_ring(struct ieee80211_hw *dev, u32 *index,
  201. int ring_index, struct p54p_desc *ring, u32 ring_limit,
  202. struct sk_buff **tx_buf)
  203. {
  204. struct p54p_priv *priv = dev->priv;
  205. struct p54p_ring_control *ring_control = priv->ring_control;
  206. struct p54p_desc *desc;
  207. struct sk_buff *skb;
  208. u32 idx, i;
  209. i = (*index) % ring_limit;
  210. (*index) = idx = le32_to_cpu(ring_control->device_idx[ring_index]);
  211. idx %= ring_limit;
  212. while (i != idx) {
  213. desc = &ring[i];
  214. skb = tx_buf[i];
  215. tx_buf[i] = NULL;
  216. pci_unmap_single(priv->pdev, le32_to_cpu(desc->host_addr),
  217. le16_to_cpu(desc->len), PCI_DMA_TODEVICE);
  218. desc->host_addr = 0;
  219. desc->device_addr = 0;
  220. desc->len = 0;
  221. desc->flags = 0;
  222. if (skb && FREE_AFTER_TX(skb))
  223. p54_free_skb(dev, skb);
  224. i++;
  225. i %= ring_limit;
  226. }
  227. }
  228. static void p54p_tasklet(unsigned long dev_id)
  229. {
  230. struct ieee80211_hw *dev = (struct ieee80211_hw *)dev_id;
  231. struct p54p_priv *priv = dev->priv;
  232. struct p54p_ring_control *ring_control = priv->ring_control;
  233. p54p_check_tx_ring(dev, &priv->tx_idx_mgmt, 3, ring_control->tx_mgmt,
  234. ARRAY_SIZE(ring_control->tx_mgmt),
  235. priv->tx_buf_mgmt);
  236. p54p_check_tx_ring(dev, &priv->tx_idx_data, 1, ring_control->tx_data,
  237. ARRAY_SIZE(ring_control->tx_data),
  238. priv->tx_buf_data);
  239. p54p_check_rx_ring(dev, &priv->rx_idx_mgmt, 2, ring_control->rx_mgmt,
  240. ARRAY_SIZE(ring_control->rx_mgmt), priv->rx_buf_mgmt);
  241. p54p_check_rx_ring(dev, &priv->rx_idx_data, 0, ring_control->rx_data,
  242. ARRAY_SIZE(ring_control->rx_data), priv->rx_buf_data);
  243. wmb();
  244. P54P_WRITE(dev_int, cpu_to_le32(ISL38XX_DEV_INT_UPDATE));
  245. }
  246. static irqreturn_t p54p_interrupt(int irq, void *dev_id)
  247. {
  248. struct ieee80211_hw *dev = dev_id;
  249. struct p54p_priv *priv = dev->priv;
  250. __le32 reg;
  251. reg = P54P_READ(int_ident);
  252. if (unlikely(reg == cpu_to_le32(0xFFFFFFFF))) {
  253. goto out;
  254. }
  255. P54P_WRITE(int_ack, reg);
  256. reg &= P54P_READ(int_enable);
  257. if (reg & cpu_to_le32(ISL38XX_INT_IDENT_UPDATE))
  258. tasklet_schedule(&priv->tasklet);
  259. else if (reg & cpu_to_le32(ISL38XX_INT_IDENT_INIT))
  260. complete(&priv->boot_comp);
  261. out:
  262. return reg ? IRQ_HANDLED : IRQ_NONE;
  263. }
  264. static void p54p_tx(struct ieee80211_hw *dev, struct sk_buff *skb)
  265. {
  266. unsigned long flags;
  267. struct p54p_priv *priv = dev->priv;
  268. struct p54p_ring_control *ring_control = priv->ring_control;
  269. struct p54p_desc *desc;
  270. dma_addr_t mapping;
  271. u32 device_idx, idx, i;
  272. spin_lock_irqsave(&priv->lock, flags);
  273. device_idx = le32_to_cpu(ring_control->device_idx[1]);
  274. idx = le32_to_cpu(ring_control->host_idx[1]);
  275. i = idx % ARRAY_SIZE(ring_control->tx_data);
  276. mapping = pci_map_single(priv->pdev, skb->data, skb->len,
  277. PCI_DMA_TODEVICE);
  278. if (pci_dma_mapping_error(priv->pdev, mapping)) {
  279. spin_unlock_irqrestore(&priv->lock, flags);
  280. p54_free_skb(dev, skb);
  281. dev_err(&priv->pdev->dev, "TX DMA mapping error\n");
  282. return ;
  283. }
  284. priv->tx_buf_data[i] = skb;
  285. desc = &ring_control->tx_data[i];
  286. desc->host_addr = cpu_to_le32(mapping);
  287. desc->device_addr = ((struct p54_hdr *)skb->data)->req_id;
  288. desc->len = cpu_to_le16(skb->len);
  289. desc->flags = 0;
  290. wmb();
  291. ring_control->host_idx[1] = cpu_to_le32(idx + 1);
  292. spin_unlock_irqrestore(&priv->lock, flags);
  293. P54P_WRITE(dev_int, cpu_to_le32(ISL38XX_DEV_INT_UPDATE));
  294. P54P_READ(dev_int);
  295. }
  296. static void p54p_stop(struct ieee80211_hw *dev)
  297. {
  298. struct p54p_priv *priv = dev->priv;
  299. struct p54p_ring_control *ring_control = priv->ring_control;
  300. unsigned int i;
  301. struct p54p_desc *desc;
  302. P54P_WRITE(int_enable, cpu_to_le32(0));
  303. P54P_READ(int_enable);
  304. udelay(10);
  305. free_irq(priv->pdev->irq, dev);
  306. tasklet_kill(&priv->tasklet);
  307. P54P_WRITE(dev_int, cpu_to_le32(ISL38XX_DEV_INT_RESET));
  308. for (i = 0; i < ARRAY_SIZE(priv->rx_buf_data); i++) {
  309. desc = &ring_control->rx_data[i];
  310. if (desc->host_addr)
  311. pci_unmap_single(priv->pdev,
  312. le32_to_cpu(desc->host_addr),
  313. priv->common.rx_mtu + 32,
  314. PCI_DMA_FROMDEVICE);
  315. kfree_skb(priv->rx_buf_data[i]);
  316. priv->rx_buf_data[i] = NULL;
  317. }
  318. for (i = 0; i < ARRAY_SIZE(priv->rx_buf_mgmt); i++) {
  319. desc = &ring_control->rx_mgmt[i];
  320. if (desc->host_addr)
  321. pci_unmap_single(priv->pdev,
  322. le32_to_cpu(desc->host_addr),
  323. priv->common.rx_mtu + 32,
  324. PCI_DMA_FROMDEVICE);
  325. kfree_skb(priv->rx_buf_mgmt[i]);
  326. priv->rx_buf_mgmt[i] = NULL;
  327. }
  328. for (i = 0; i < ARRAY_SIZE(priv->tx_buf_data); i++) {
  329. desc = &ring_control->tx_data[i];
  330. if (desc->host_addr)
  331. pci_unmap_single(priv->pdev,
  332. le32_to_cpu(desc->host_addr),
  333. le16_to_cpu(desc->len),
  334. PCI_DMA_TODEVICE);
  335. p54_free_skb(dev, priv->tx_buf_data[i]);
  336. priv->tx_buf_data[i] = NULL;
  337. }
  338. for (i = 0; i < ARRAY_SIZE(priv->tx_buf_mgmt); i++) {
  339. desc = &ring_control->tx_mgmt[i];
  340. if (desc->host_addr)
  341. pci_unmap_single(priv->pdev,
  342. le32_to_cpu(desc->host_addr),
  343. le16_to_cpu(desc->len),
  344. PCI_DMA_TODEVICE);
  345. p54_free_skb(dev, priv->tx_buf_mgmt[i]);
  346. priv->tx_buf_mgmt[i] = NULL;
  347. }
  348. memset(ring_control, 0, sizeof(*ring_control));
  349. }
  350. static int p54p_open(struct ieee80211_hw *dev)
  351. {
  352. struct p54p_priv *priv = dev->priv;
  353. int err;
  354. init_completion(&priv->boot_comp);
  355. err = request_irq(priv->pdev->irq, p54p_interrupt,
  356. IRQF_SHARED, "p54pci", dev);
  357. if (err) {
  358. dev_err(&priv->pdev->dev, "failed to register IRQ handler\n");
  359. return err;
  360. }
  361. memset(priv->ring_control, 0, sizeof(*priv->ring_control));
  362. err = p54p_upload_firmware(dev);
  363. if (err) {
  364. free_irq(priv->pdev->irq, dev);
  365. return err;
  366. }
  367. priv->rx_idx_data = priv->tx_idx_data = 0;
  368. priv->rx_idx_mgmt = priv->tx_idx_mgmt = 0;
  369. p54p_refill_rx_ring(dev, 0, priv->ring_control->rx_data,
  370. ARRAY_SIZE(priv->ring_control->rx_data), priv->rx_buf_data, 0);
  371. p54p_refill_rx_ring(dev, 2, priv->ring_control->rx_mgmt,
  372. ARRAY_SIZE(priv->ring_control->rx_mgmt), priv->rx_buf_mgmt, 0);
  373. P54P_WRITE(ring_control_base, cpu_to_le32(priv->ring_control_dma));
  374. P54P_READ(ring_control_base);
  375. wmb();
  376. udelay(10);
  377. P54P_WRITE(int_enable, cpu_to_le32(ISL38XX_INT_IDENT_INIT));
  378. P54P_READ(int_enable);
  379. wmb();
  380. udelay(10);
  381. P54P_WRITE(dev_int, cpu_to_le32(ISL38XX_DEV_INT_RESET));
  382. P54P_READ(dev_int);
  383. if (!wait_for_completion_interruptible_timeout(&priv->boot_comp, HZ)) {
  384. wiphy_err(dev->wiphy, "Cannot boot firmware!\n");
  385. p54p_stop(dev);
  386. return -ETIMEDOUT;
  387. }
  388. P54P_WRITE(int_enable, cpu_to_le32(ISL38XX_INT_IDENT_UPDATE));
  389. P54P_READ(int_enable);
  390. wmb();
  391. udelay(10);
  392. P54P_WRITE(dev_int, cpu_to_le32(ISL38XX_DEV_INT_UPDATE));
  393. P54P_READ(dev_int);
  394. wmb();
  395. udelay(10);
  396. return 0;
  397. }
  398. static int __devinit p54p_probe(struct pci_dev *pdev,
  399. const struct pci_device_id *id)
  400. {
  401. struct p54p_priv *priv;
  402. struct ieee80211_hw *dev;
  403. unsigned long mem_addr, mem_len;
  404. int err;
  405. err = pci_enable_device(pdev);
  406. if (err) {
  407. dev_err(&pdev->dev, "Cannot enable new PCI device\n");
  408. return err;
  409. }
  410. mem_addr = pci_resource_start(pdev, 0);
  411. mem_len = pci_resource_len(pdev, 0);
  412. if (mem_len < sizeof(struct p54p_csr)) {
  413. dev_err(&pdev->dev, "Too short PCI resources\n");
  414. goto err_disable_dev;
  415. }
  416. err = pci_request_regions(pdev, "p54pci");
  417. if (err) {
  418. dev_err(&pdev->dev, "Cannot obtain PCI resources\n");
  419. goto err_disable_dev;
  420. }
  421. if (pci_set_dma_mask(pdev, DMA_BIT_MASK(32)) ||
  422. pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(32))) {
  423. dev_err(&pdev->dev, "No suitable DMA available\n");
  424. goto err_free_reg;
  425. }
  426. pci_set_master(pdev);
  427. pci_try_set_mwi(pdev);
  428. pci_write_config_byte(pdev, 0x40, 0);
  429. pci_write_config_byte(pdev, 0x41, 0);
  430. dev = p54_init_common(sizeof(*priv));
  431. if (!dev) {
  432. dev_err(&pdev->dev, "ieee80211 alloc failed\n");
  433. err = -ENOMEM;
  434. goto err_free_reg;
  435. }
  436. priv = dev->priv;
  437. priv->pdev = pdev;
  438. SET_IEEE80211_DEV(dev, &pdev->dev);
  439. pci_set_drvdata(pdev, dev);
  440. priv->map = ioremap(mem_addr, mem_len);
  441. if (!priv->map) {
  442. dev_err(&pdev->dev, "Cannot map device memory\n");
  443. err = -ENOMEM;
  444. goto err_free_dev;
  445. }
  446. priv->ring_control = pci_alloc_consistent(pdev, sizeof(*priv->ring_control),
  447. &priv->ring_control_dma);
  448. if (!priv->ring_control) {
  449. dev_err(&pdev->dev, "Cannot allocate rings\n");
  450. err = -ENOMEM;
  451. goto err_iounmap;
  452. }
  453. priv->common.open = p54p_open;
  454. priv->common.stop = p54p_stop;
  455. priv->common.tx = p54p_tx;
  456. spin_lock_init(&priv->lock);
  457. tasklet_init(&priv->tasklet, p54p_tasklet, (unsigned long)dev);
  458. err = request_firmware(&priv->firmware, "isl3886pci",
  459. &priv->pdev->dev);
  460. if (err) {
  461. dev_err(&pdev->dev, "Cannot find firmware (isl3886pci)\n");
  462. err = request_firmware(&priv->firmware, "isl3886",
  463. &priv->pdev->dev);
  464. if (err)
  465. goto err_free_common;
  466. }
  467. err = p54p_open(dev);
  468. if (err)
  469. goto err_free_common;
  470. err = p54_read_eeprom(dev);
  471. p54p_stop(dev);
  472. if (err)
  473. goto err_free_common;
  474. err = p54_register_common(dev, &pdev->dev);
  475. if (err)
  476. goto err_free_common;
  477. return 0;
  478. err_free_common:
  479. release_firmware(priv->firmware);
  480. pci_free_consistent(pdev, sizeof(*priv->ring_control),
  481. priv->ring_control, priv->ring_control_dma);
  482. err_iounmap:
  483. iounmap(priv->map);
  484. err_free_dev:
  485. pci_set_drvdata(pdev, NULL);
  486. p54_free_common(dev);
  487. err_free_reg:
  488. pci_release_regions(pdev);
  489. err_disable_dev:
  490. pci_disable_device(pdev);
  491. return err;
  492. }
  493. static void __devexit p54p_remove(struct pci_dev *pdev)
  494. {
  495. struct ieee80211_hw *dev = pci_get_drvdata(pdev);
  496. struct p54p_priv *priv;
  497. if (!dev)
  498. return;
  499. p54_unregister_common(dev);
  500. priv = dev->priv;
  501. release_firmware(priv->firmware);
  502. pci_free_consistent(pdev, sizeof(*priv->ring_control),
  503. priv->ring_control, priv->ring_control_dma);
  504. iounmap(priv->map);
  505. pci_release_regions(pdev);
  506. pci_disable_device(pdev);
  507. p54_free_common(dev);
  508. }
  509. #ifdef CONFIG_PM
  510. static int p54p_suspend(struct pci_dev *pdev, pm_message_t state)
  511. {
  512. struct ieee80211_hw *dev = pci_get_drvdata(pdev);
  513. struct p54p_priv *priv = dev->priv;
  514. if (priv->common.mode != NL80211_IFTYPE_UNSPECIFIED) {
  515. ieee80211_stop_queues(dev);
  516. p54p_stop(dev);
  517. }
  518. pci_save_state(pdev);
  519. pci_set_power_state(pdev, pci_choose_state(pdev, state));
  520. return 0;
  521. }
  522. static int p54p_resume(struct pci_dev *pdev)
  523. {
  524. struct ieee80211_hw *dev = pci_get_drvdata(pdev);
  525. struct p54p_priv *priv = dev->priv;
  526. pci_set_power_state(pdev, PCI_D0);
  527. pci_restore_state(pdev);
  528. if (priv->common.mode != NL80211_IFTYPE_UNSPECIFIED) {
  529. p54p_open(dev);
  530. ieee80211_wake_queues(dev);
  531. }
  532. return 0;
  533. }
  534. #endif /* CONFIG_PM */
  535. static struct pci_driver p54p_driver = {
  536. .name = "p54pci",
  537. .id_table = p54p_table,
  538. .probe = p54p_probe,
  539. .remove = __devexit_p(p54p_remove),
  540. #ifdef CONFIG_PM
  541. .suspend = p54p_suspend,
  542. .resume = p54p_resume,
  543. #endif /* CONFIG_PM */
  544. };
  545. static int __init p54p_init(void)
  546. {
  547. return pci_register_driver(&p54p_driver);
  548. }
  549. static void __exit p54p_exit(void)
  550. {
  551. pci_unregister_driver(&p54p_driver);
  552. }
  553. module_init(p54p_init);
  554. module_exit(p54p_exit);