attach.c 9.9 KB

123456789101112131415161718192021222324252627282930313233343536373839404142434445464748495051525354555657585960616263646566676869707172737475767778798081828384858687888990919293949596979899100101102103104105106107108109110111112113114115116117118119120121122123124125126127128129130131132133134135136137138139140141142143144145146147148149150151152153154155156157158159160161162163164165166167168169170171172173174175176177178179180181182183184185186187188189190191192193194195196197198199200201202203204205206207208209210211212213214215216217218219220221222223224225226227228229230231232233234235236237238239240241242243244245246247248249250251252253254255256257258259260261262263264265266267268269270271272273274275276277278279280281282283284285286287288289290291292293294295296297298299300301302303304305306307308309310311312313314315316317318319320321322323324325326327328329330331332333334335336337338339340341342343344345346347348349350351352353354355356357358359360361362363364365
  1. /*
  2. * Copyright (c) 2004-2008 Reyk Floeter <reyk@openbsd.org>
  3. * Copyright (c) 2006-2008 Nick Kossifidis <mickflemm@gmail.com>
  4. *
  5. * Permission to use, copy, modify, and distribute this software for any
  6. * purpose with or without fee is hereby granted, provided that the above
  7. * copyright notice and this permission notice appear in all copies.
  8. *
  9. * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
  10. * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
  11. * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
  12. * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
  13. * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
  14. * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
  15. * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
  16. *
  17. */
  18. /*************************************\
  19. * Attach/Detach Functions and helpers *
  20. \*************************************/
  21. #include <linux/pci.h>
  22. #include <linux/slab.h>
  23. #include "ath5k.h"
  24. #include "reg.h"
  25. #include "debug.h"
  26. #include "base.h"
  27. /**
  28. * ath5k_hw_post - Power On Self Test helper function
  29. *
  30. * @ah: The &struct ath5k_hw
  31. */
  32. static int ath5k_hw_post(struct ath5k_hw *ah)
  33. {
  34. static const u32 static_pattern[4] = {
  35. 0x55555555, 0xaaaaaaaa,
  36. 0x66666666, 0x99999999
  37. };
  38. static const u16 regs[2] = { AR5K_STA_ID0, AR5K_PHY(8) };
  39. int i, c;
  40. u16 cur_reg;
  41. u32 var_pattern;
  42. u32 init_val;
  43. u32 cur_val;
  44. for (c = 0; c < 2; c++) {
  45. cur_reg = regs[c];
  46. /* Save previous value */
  47. init_val = ath5k_hw_reg_read(ah, cur_reg);
  48. for (i = 0; i < 256; i++) {
  49. var_pattern = i << 16 | i;
  50. ath5k_hw_reg_write(ah, var_pattern, cur_reg);
  51. cur_val = ath5k_hw_reg_read(ah, cur_reg);
  52. if (cur_val != var_pattern) {
  53. ATH5K_ERR(ah->ah_sc, "POST Failed !!!\n");
  54. return -EAGAIN;
  55. }
  56. /* Found on ndiswrapper dumps */
  57. var_pattern = 0x0039080f;
  58. ath5k_hw_reg_write(ah, var_pattern, cur_reg);
  59. }
  60. for (i = 0; i < 4; i++) {
  61. var_pattern = static_pattern[i];
  62. ath5k_hw_reg_write(ah, var_pattern, cur_reg);
  63. cur_val = ath5k_hw_reg_read(ah, cur_reg);
  64. if (cur_val != var_pattern) {
  65. ATH5K_ERR(ah->ah_sc, "POST Failed !!!\n");
  66. return -EAGAIN;
  67. }
  68. /* Found on ndiswrapper dumps */
  69. var_pattern = 0x003b080f;
  70. ath5k_hw_reg_write(ah, var_pattern, cur_reg);
  71. }
  72. /* Restore previous value */
  73. ath5k_hw_reg_write(ah, init_val, cur_reg);
  74. }
  75. return 0;
  76. }
  77. /**
  78. * ath5k_hw_init - Check if hw is supported and init the needed structs
  79. *
  80. * @sc: The &struct ath5k_softc we got from the driver's init_softc function
  81. *
  82. * Check if the device is supported, perform a POST and initialize the needed
  83. * structs. Returns -ENOMEM if we don't have memory for the needed structs,
  84. * -ENODEV if the device is not supported or prints an error msg if something
  85. * else went wrong.
  86. */
  87. int ath5k_hw_init(struct ath5k_softc *sc)
  88. {
  89. struct ath5k_hw *ah = sc->ah;
  90. struct ath_common *common = ath5k_hw_common(ah);
  91. struct pci_dev *pdev = sc->pdev;
  92. struct ath5k_eeprom_info *ee;
  93. int ret;
  94. u32 srev;
  95. /*
  96. * HW information
  97. */
  98. ah->ah_radar.r_enabled = AR5K_TUNE_RADAR_ALERT;
  99. ah->ah_bwmode = AR5K_BWMODE_DEFAULT;
  100. ah->ah_txpower.txp_tpc = AR5K_TUNE_TPC_TXPOWER;
  101. ah->ah_imr = 0;
  102. ah->ah_limit_tx_retries = AR5K_INIT_TX_RETRY;
  103. ah->ah_software_retry = false;
  104. ah->ah_ant_mode = AR5K_ANTMODE_DEFAULT;
  105. ah->ah_noise_floor = -95; /* until first NF calibration is run */
  106. sc->ani_state.ani_mode = ATH5K_ANI_MODE_AUTO;
  107. ah->ah_current_channel = &sc->channels[0];
  108. /*
  109. * Find the mac version
  110. */
  111. ath5k_hw_read_srev(ah);
  112. srev = ah->ah_mac_srev;
  113. if (srev < AR5K_SREV_AR5311)
  114. ah->ah_version = AR5K_AR5210;
  115. else if (srev < AR5K_SREV_AR5212)
  116. ah->ah_version = AR5K_AR5211;
  117. else
  118. ah->ah_version = AR5K_AR5212;
  119. /* Get the MAC revision */
  120. ah->ah_mac_version = AR5K_REG_MS(srev, AR5K_SREV_VER);
  121. ah->ah_mac_revision = AR5K_REG_MS(srev, AR5K_SREV_REV);
  122. /* Fill the ath5k_hw struct with the needed functions */
  123. ret = ath5k_hw_init_desc_functions(ah);
  124. if (ret)
  125. goto err;
  126. /* Bring device out of sleep and reset its units */
  127. ret = ath5k_hw_nic_wakeup(ah, 0, true);
  128. if (ret)
  129. goto err;
  130. /* Get PHY and RADIO revisions */
  131. ah->ah_phy_revision = ath5k_hw_reg_read(ah, AR5K_PHY_CHIP_ID) &
  132. 0xffffffff;
  133. ah->ah_radio_5ghz_revision = ath5k_hw_radio_revision(ah,
  134. CHANNEL_5GHZ);
  135. ah->ah_phy = AR5K_PHY(0);
  136. /* Try to identify radio chip based on its srev */
  137. switch (ah->ah_radio_5ghz_revision & 0xf0) {
  138. case AR5K_SREV_RAD_5111:
  139. ah->ah_radio = AR5K_RF5111;
  140. ah->ah_single_chip = false;
  141. ah->ah_radio_2ghz_revision = ath5k_hw_radio_revision(ah,
  142. CHANNEL_2GHZ);
  143. break;
  144. case AR5K_SREV_RAD_5112:
  145. case AR5K_SREV_RAD_2112:
  146. ah->ah_radio = AR5K_RF5112;
  147. ah->ah_single_chip = false;
  148. ah->ah_radio_2ghz_revision = ath5k_hw_radio_revision(ah,
  149. CHANNEL_2GHZ);
  150. break;
  151. case AR5K_SREV_RAD_2413:
  152. ah->ah_radio = AR5K_RF2413;
  153. ah->ah_single_chip = true;
  154. break;
  155. case AR5K_SREV_RAD_5413:
  156. ah->ah_radio = AR5K_RF5413;
  157. ah->ah_single_chip = true;
  158. break;
  159. case AR5K_SREV_RAD_2316:
  160. ah->ah_radio = AR5K_RF2316;
  161. ah->ah_single_chip = true;
  162. break;
  163. case AR5K_SREV_RAD_2317:
  164. ah->ah_radio = AR5K_RF2317;
  165. ah->ah_single_chip = true;
  166. break;
  167. case AR5K_SREV_RAD_5424:
  168. if (ah->ah_mac_version == AR5K_SREV_AR2425 ||
  169. ah->ah_mac_version == AR5K_SREV_AR2417){
  170. ah->ah_radio = AR5K_RF2425;
  171. ah->ah_single_chip = true;
  172. } else {
  173. ah->ah_radio = AR5K_RF5413;
  174. ah->ah_single_chip = true;
  175. }
  176. break;
  177. default:
  178. /* Identify radio based on mac/phy srev */
  179. if (ah->ah_version == AR5K_AR5210) {
  180. ah->ah_radio = AR5K_RF5110;
  181. ah->ah_single_chip = false;
  182. } else if (ah->ah_version == AR5K_AR5211) {
  183. ah->ah_radio = AR5K_RF5111;
  184. ah->ah_single_chip = false;
  185. ah->ah_radio_2ghz_revision = ath5k_hw_radio_revision(ah,
  186. CHANNEL_2GHZ);
  187. } else if (ah->ah_mac_version == (AR5K_SREV_AR2425 >> 4) ||
  188. ah->ah_mac_version == (AR5K_SREV_AR2417 >> 4) ||
  189. ah->ah_phy_revision == AR5K_SREV_PHY_2425) {
  190. ah->ah_radio = AR5K_RF2425;
  191. ah->ah_single_chip = true;
  192. ah->ah_radio_5ghz_revision = AR5K_SREV_RAD_2425;
  193. } else if (srev == AR5K_SREV_AR5213A &&
  194. ah->ah_phy_revision == AR5K_SREV_PHY_5212B) {
  195. ah->ah_radio = AR5K_RF5112;
  196. ah->ah_single_chip = false;
  197. ah->ah_radio_5ghz_revision = AR5K_SREV_RAD_5112B;
  198. } else if (ah->ah_mac_version == (AR5K_SREV_AR2415 >> 4)) {
  199. ah->ah_radio = AR5K_RF2316;
  200. ah->ah_single_chip = true;
  201. ah->ah_radio_5ghz_revision = AR5K_SREV_RAD_2316;
  202. } else if (ah->ah_mac_version == (AR5K_SREV_AR5414 >> 4) ||
  203. ah->ah_phy_revision == AR5K_SREV_PHY_5413) {
  204. ah->ah_radio = AR5K_RF5413;
  205. ah->ah_single_chip = true;
  206. ah->ah_radio_5ghz_revision = AR5K_SREV_RAD_5413;
  207. } else if (ah->ah_mac_version == (AR5K_SREV_AR2414 >> 4) ||
  208. ah->ah_phy_revision == AR5K_SREV_PHY_2413) {
  209. ah->ah_radio = AR5K_RF2413;
  210. ah->ah_single_chip = true;
  211. ah->ah_radio_5ghz_revision = AR5K_SREV_RAD_2413;
  212. } else {
  213. ATH5K_ERR(sc, "Couldn't identify radio revision.\n");
  214. ret = -ENODEV;
  215. goto err;
  216. }
  217. }
  218. /* Return on unsuported chips (unsupported eeprom etc) */
  219. if ((srev >= AR5K_SREV_AR5416) &&
  220. (srev < AR5K_SREV_AR2425)) {
  221. ATH5K_ERR(sc, "Device not yet supported.\n");
  222. ret = -ENODEV;
  223. goto err;
  224. }
  225. /*
  226. * POST
  227. */
  228. ret = ath5k_hw_post(ah);
  229. if (ret)
  230. goto err;
  231. /* Enable pci core retry fix on Hainan (5213A) and later chips */
  232. if (srev >= AR5K_SREV_AR5213A)
  233. AR5K_REG_ENABLE_BITS(ah, AR5K_PCICFG, AR5K_PCICFG_RETRY_FIX);
  234. /*
  235. * Get card capabilities, calibration values etc
  236. * TODO: EEPROM work
  237. */
  238. ret = ath5k_eeprom_init(ah);
  239. if (ret) {
  240. ATH5K_ERR(sc, "unable to init EEPROM\n");
  241. goto err;
  242. }
  243. ee = &ah->ah_capabilities.cap_eeprom;
  244. /*
  245. * Write PCI-E power save settings
  246. */
  247. if ((ah->ah_version == AR5K_AR5212) && pdev && (pdev->is_pcie)) {
  248. ath5k_hw_reg_write(ah, 0x9248fc00, AR5K_PCIE_SERDES);
  249. ath5k_hw_reg_write(ah, 0x24924924, AR5K_PCIE_SERDES);
  250. /* Shut off RX when elecidle is asserted */
  251. ath5k_hw_reg_write(ah, 0x28000039, AR5K_PCIE_SERDES);
  252. ath5k_hw_reg_write(ah, 0x53160824, AR5K_PCIE_SERDES);
  253. /* If serdes programing is enabled, increase PCI-E
  254. * tx power for systems with long trace from host
  255. * to minicard connector. */
  256. if (ee->ee_serdes)
  257. ath5k_hw_reg_write(ah, 0xe5980579, AR5K_PCIE_SERDES);
  258. else
  259. ath5k_hw_reg_write(ah, 0xf6800579, AR5K_PCIE_SERDES);
  260. /* Shut off PLL and CLKREQ active in L1 */
  261. ath5k_hw_reg_write(ah, 0x001defff, AR5K_PCIE_SERDES);
  262. /* Preserve other settings */
  263. ath5k_hw_reg_write(ah, 0x1aaabe40, AR5K_PCIE_SERDES);
  264. ath5k_hw_reg_write(ah, 0xbe105554, AR5K_PCIE_SERDES);
  265. ath5k_hw_reg_write(ah, 0x000e3007, AR5K_PCIE_SERDES);
  266. /* Reset SERDES to load new settings */
  267. ath5k_hw_reg_write(ah, 0x00000000, AR5K_PCIE_SERDES_RESET);
  268. mdelay(1);
  269. }
  270. /* Get misc capabilities */
  271. ret = ath5k_hw_set_capabilities(ah);
  272. if (ret) {
  273. ATH5K_ERR(sc, "unable to get device capabilities\n");
  274. goto err;
  275. }
  276. /* Crypto settings */
  277. common->keymax = (sc->ah->ah_version == AR5K_AR5210 ?
  278. AR5K_KEYTABLE_SIZE_5210 : AR5K_KEYTABLE_SIZE_5211);
  279. if (srev >= AR5K_SREV_AR5212_V4 &&
  280. (ee->ee_version >= AR5K_EEPROM_VERSION_5_0 &&
  281. !AR5K_EEPROM_AES_DIS(ee->ee_misc5)))
  282. common->crypt_caps |= ATH_CRYPT_CAP_CIPHER_AESCCM;
  283. if (srev >= AR5K_SREV_AR2414) {
  284. common->crypt_caps |= ATH_CRYPT_CAP_MIC_COMBINED;
  285. AR5K_REG_ENABLE_BITS(ah, AR5K_MISC_MODE,
  286. AR5K_MISC_MODE_COMBINED_MIC);
  287. }
  288. /* MAC address is cleared until add_interface */
  289. ath5k_hw_set_lladdr(ah, (u8[ETH_ALEN]){});
  290. /* Set BSSID to bcast address: ff:ff:ff:ff:ff:ff for now */
  291. memcpy(common->curbssid, ath_bcast_mac, ETH_ALEN);
  292. ath5k_hw_set_bssid(ah);
  293. ath5k_hw_set_opmode(ah, sc->opmode);
  294. ath5k_hw_rfgain_opt_init(ah);
  295. ath5k_hw_init_nfcal_hist(ah);
  296. /* turn on HW LEDs */
  297. ath5k_hw_set_ledstate(ah, AR5K_LED_INIT);
  298. return 0;
  299. err:
  300. return ret;
  301. }
  302. /**
  303. * ath5k_hw_deinit - Free the ath5k_hw struct
  304. *
  305. * @ah: The &struct ath5k_hw
  306. */
  307. void ath5k_hw_deinit(struct ath5k_hw *ah)
  308. {
  309. __set_bit(ATH_STAT_INVALID, ah->ah_sc->status);
  310. if (ah->ah_rf_banks != NULL)
  311. kfree(ah->ah_rf_banks);
  312. ath5k_eeprom_detach(ah);
  313. /* assume interrupts are down */
  314. }