tx.c 32 KB

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  1. /****************************************************************************
  2. * Driver for Solarflare Solarstorm network controllers and boards
  3. * Copyright 2005-2006 Fen Systems Ltd.
  4. * Copyright 2005-2009 Solarflare Communications Inc.
  5. *
  6. * This program is free software; you can redistribute it and/or modify it
  7. * under the terms of the GNU General Public License version 2 as published
  8. * by the Free Software Foundation, incorporated herein by reference.
  9. */
  10. #include <linux/pci.h>
  11. #include <linux/tcp.h>
  12. #include <linux/ip.h>
  13. #include <linux/in.h>
  14. #include <linux/ipv6.h>
  15. #include <linux/slab.h>
  16. #include <net/ipv6.h>
  17. #include <linux/if_ether.h>
  18. #include <linux/highmem.h>
  19. #include "net_driver.h"
  20. #include "efx.h"
  21. #include "nic.h"
  22. #include "workarounds.h"
  23. /*
  24. * TX descriptor ring full threshold
  25. *
  26. * The tx_queue descriptor ring fill-level must fall below this value
  27. * before we restart the netif queue
  28. */
  29. #define EFX_TXQ_THRESHOLD(_efx) ((_efx)->txq_entries / 2u)
  30. /* We need to be able to nest calls to netif_tx_stop_queue(), partly
  31. * because of the 2 hardware queues associated with each core queue,
  32. * but also so that we can inhibit TX for reasons other than a full
  33. * hardware queue. */
  34. void efx_stop_queue(struct efx_channel *channel)
  35. {
  36. struct efx_nic *efx = channel->efx;
  37. struct efx_tx_queue *tx_queue = efx_channel_get_tx_queue(channel, 0);
  38. if (!tx_queue)
  39. return;
  40. spin_lock_bh(&channel->tx_stop_lock);
  41. netif_vdbg(efx, tx_queued, efx->net_dev, "stop TX queue\n");
  42. atomic_inc(&channel->tx_stop_count);
  43. netif_tx_stop_queue(
  44. netdev_get_tx_queue(efx->net_dev,
  45. tx_queue->queue / EFX_TXQ_TYPES));
  46. spin_unlock_bh(&channel->tx_stop_lock);
  47. }
  48. /* Decrement core TX queue stop count and wake it if the count is 0 */
  49. void efx_wake_queue(struct efx_channel *channel)
  50. {
  51. struct efx_nic *efx = channel->efx;
  52. struct efx_tx_queue *tx_queue = efx_channel_get_tx_queue(channel, 0);
  53. if (!tx_queue)
  54. return;
  55. local_bh_disable();
  56. if (atomic_dec_and_lock(&channel->tx_stop_count,
  57. &channel->tx_stop_lock)) {
  58. netif_vdbg(efx, tx_queued, efx->net_dev, "waking TX queue\n");
  59. netif_tx_wake_queue(
  60. netdev_get_tx_queue(efx->net_dev,
  61. tx_queue->queue / EFX_TXQ_TYPES));
  62. spin_unlock(&channel->tx_stop_lock);
  63. }
  64. local_bh_enable();
  65. }
  66. static void efx_dequeue_buffer(struct efx_tx_queue *tx_queue,
  67. struct efx_tx_buffer *buffer)
  68. {
  69. if (buffer->unmap_len) {
  70. struct pci_dev *pci_dev = tx_queue->efx->pci_dev;
  71. dma_addr_t unmap_addr = (buffer->dma_addr + buffer->len -
  72. buffer->unmap_len);
  73. if (buffer->unmap_single)
  74. pci_unmap_single(pci_dev, unmap_addr, buffer->unmap_len,
  75. PCI_DMA_TODEVICE);
  76. else
  77. pci_unmap_page(pci_dev, unmap_addr, buffer->unmap_len,
  78. PCI_DMA_TODEVICE);
  79. buffer->unmap_len = 0;
  80. buffer->unmap_single = false;
  81. }
  82. if (buffer->skb) {
  83. dev_kfree_skb_any((struct sk_buff *) buffer->skb);
  84. buffer->skb = NULL;
  85. netif_vdbg(tx_queue->efx, tx_done, tx_queue->efx->net_dev,
  86. "TX queue %d transmission id %x complete\n",
  87. tx_queue->queue, tx_queue->read_count);
  88. }
  89. }
  90. /**
  91. * struct efx_tso_header - a DMA mapped buffer for packet headers
  92. * @next: Linked list of free ones.
  93. * The list is protected by the TX queue lock.
  94. * @dma_unmap_len: Length to unmap for an oversize buffer, or 0.
  95. * @dma_addr: The DMA address of the header below.
  96. *
  97. * This controls the memory used for a TSO header. Use TSOH_DATA()
  98. * to find the packet header data. Use TSOH_SIZE() to calculate the
  99. * total size required for a given packet header length. TSO headers
  100. * in the free list are exactly %TSOH_STD_SIZE bytes in size.
  101. */
  102. struct efx_tso_header {
  103. union {
  104. struct efx_tso_header *next;
  105. size_t unmap_len;
  106. };
  107. dma_addr_t dma_addr;
  108. };
  109. static int efx_enqueue_skb_tso(struct efx_tx_queue *tx_queue,
  110. struct sk_buff *skb);
  111. static void efx_fini_tso(struct efx_tx_queue *tx_queue);
  112. static void efx_tsoh_heap_free(struct efx_tx_queue *tx_queue,
  113. struct efx_tso_header *tsoh);
  114. static void efx_tsoh_free(struct efx_tx_queue *tx_queue,
  115. struct efx_tx_buffer *buffer)
  116. {
  117. if (buffer->tsoh) {
  118. if (likely(!buffer->tsoh->unmap_len)) {
  119. buffer->tsoh->next = tx_queue->tso_headers_free;
  120. tx_queue->tso_headers_free = buffer->tsoh;
  121. } else {
  122. efx_tsoh_heap_free(tx_queue, buffer->tsoh);
  123. }
  124. buffer->tsoh = NULL;
  125. }
  126. }
  127. static inline unsigned
  128. efx_max_tx_len(struct efx_nic *efx, dma_addr_t dma_addr)
  129. {
  130. /* Depending on the NIC revision, we can use descriptor
  131. * lengths up to 8K or 8K-1. However, since PCI Express
  132. * devices must split read requests at 4K boundaries, there is
  133. * little benefit from using descriptors that cross those
  134. * boundaries and we keep things simple by not doing so.
  135. */
  136. unsigned len = (~dma_addr & 0xfff) + 1;
  137. /* Work around hardware bug for unaligned buffers. */
  138. if (EFX_WORKAROUND_5391(efx) && (dma_addr & 0xf))
  139. len = min_t(unsigned, len, 512 - (dma_addr & 0xf));
  140. return len;
  141. }
  142. /*
  143. * Add a socket buffer to a TX queue
  144. *
  145. * This maps all fragments of a socket buffer for DMA and adds them to
  146. * the TX queue. The queue's insert pointer will be incremented by
  147. * the number of fragments in the socket buffer.
  148. *
  149. * If any DMA mapping fails, any mapped fragments will be unmapped,
  150. * the queue's insert pointer will be restored to its original value.
  151. *
  152. * This function is split out from efx_hard_start_xmit to allow the
  153. * loopback test to direct packets via specific TX queues.
  154. *
  155. * Returns NETDEV_TX_OK or NETDEV_TX_BUSY
  156. * You must hold netif_tx_lock() to call this function.
  157. */
  158. netdev_tx_t efx_enqueue_skb(struct efx_tx_queue *tx_queue, struct sk_buff *skb)
  159. {
  160. struct efx_nic *efx = tx_queue->efx;
  161. struct pci_dev *pci_dev = efx->pci_dev;
  162. struct efx_tx_buffer *buffer;
  163. skb_frag_t *fragment;
  164. struct page *page;
  165. int page_offset;
  166. unsigned int len, unmap_len = 0, fill_level, insert_ptr;
  167. dma_addr_t dma_addr, unmap_addr = 0;
  168. unsigned int dma_len;
  169. bool unmap_single;
  170. int q_space, i = 0;
  171. netdev_tx_t rc = NETDEV_TX_OK;
  172. EFX_BUG_ON_PARANOID(tx_queue->write_count != tx_queue->insert_count);
  173. if (skb_shinfo(skb)->gso_size)
  174. return efx_enqueue_skb_tso(tx_queue, skb);
  175. /* Get size of the initial fragment */
  176. len = skb_headlen(skb);
  177. /* Pad if necessary */
  178. if (EFX_WORKAROUND_15592(efx) && skb->len <= 32) {
  179. EFX_BUG_ON_PARANOID(skb->data_len);
  180. len = 32 + 1;
  181. if (skb_pad(skb, len - skb->len))
  182. return NETDEV_TX_OK;
  183. }
  184. fill_level = tx_queue->insert_count - tx_queue->old_read_count;
  185. q_space = efx->txq_entries - 1 - fill_level;
  186. /* Map for DMA. Use pci_map_single rather than pci_map_page
  187. * since this is more efficient on machines with sparse
  188. * memory.
  189. */
  190. unmap_single = true;
  191. dma_addr = pci_map_single(pci_dev, skb->data, len, PCI_DMA_TODEVICE);
  192. /* Process all fragments */
  193. while (1) {
  194. if (unlikely(pci_dma_mapping_error(pci_dev, dma_addr)))
  195. goto pci_err;
  196. /* Store fields for marking in the per-fragment final
  197. * descriptor */
  198. unmap_len = len;
  199. unmap_addr = dma_addr;
  200. /* Add to TX queue, splitting across DMA boundaries */
  201. do {
  202. if (unlikely(q_space-- <= 0)) {
  203. /* It might be that completions have
  204. * happened since the xmit path last
  205. * checked. Update the xmit path's
  206. * copy of read_count.
  207. */
  208. ++tx_queue->stopped;
  209. /* This memory barrier protects the
  210. * change of stopped from the access
  211. * of read_count. */
  212. smp_mb();
  213. tx_queue->old_read_count =
  214. *(volatile unsigned *)
  215. &tx_queue->read_count;
  216. fill_level = (tx_queue->insert_count
  217. - tx_queue->old_read_count);
  218. q_space = efx->txq_entries - 1 - fill_level;
  219. if (unlikely(q_space-- <= 0))
  220. goto stop;
  221. smp_mb();
  222. --tx_queue->stopped;
  223. }
  224. insert_ptr = tx_queue->insert_count & tx_queue->ptr_mask;
  225. buffer = &tx_queue->buffer[insert_ptr];
  226. efx_tsoh_free(tx_queue, buffer);
  227. EFX_BUG_ON_PARANOID(buffer->tsoh);
  228. EFX_BUG_ON_PARANOID(buffer->skb);
  229. EFX_BUG_ON_PARANOID(buffer->len);
  230. EFX_BUG_ON_PARANOID(!buffer->continuation);
  231. EFX_BUG_ON_PARANOID(buffer->unmap_len);
  232. dma_len = efx_max_tx_len(efx, dma_addr);
  233. if (likely(dma_len >= len))
  234. dma_len = len;
  235. /* Fill out per descriptor fields */
  236. buffer->len = dma_len;
  237. buffer->dma_addr = dma_addr;
  238. len -= dma_len;
  239. dma_addr += dma_len;
  240. ++tx_queue->insert_count;
  241. } while (len);
  242. /* Transfer ownership of the unmapping to the final buffer */
  243. buffer->unmap_single = unmap_single;
  244. buffer->unmap_len = unmap_len;
  245. unmap_len = 0;
  246. /* Get address and size of next fragment */
  247. if (i >= skb_shinfo(skb)->nr_frags)
  248. break;
  249. fragment = &skb_shinfo(skb)->frags[i];
  250. len = fragment->size;
  251. page = fragment->page;
  252. page_offset = fragment->page_offset;
  253. i++;
  254. /* Map for DMA */
  255. unmap_single = false;
  256. dma_addr = pci_map_page(pci_dev, page, page_offset, len,
  257. PCI_DMA_TODEVICE);
  258. }
  259. /* Transfer ownership of the skb to the final buffer */
  260. buffer->skb = skb;
  261. buffer->continuation = false;
  262. /* Pass off to hardware */
  263. efx_nic_push_buffers(tx_queue);
  264. return NETDEV_TX_OK;
  265. pci_err:
  266. netif_err(efx, tx_err, efx->net_dev,
  267. " TX queue %d could not map skb with %d bytes %d "
  268. "fragments for DMA\n", tx_queue->queue, skb->len,
  269. skb_shinfo(skb)->nr_frags + 1);
  270. /* Mark the packet as transmitted, and free the SKB ourselves */
  271. dev_kfree_skb_any(skb);
  272. goto unwind;
  273. stop:
  274. rc = NETDEV_TX_BUSY;
  275. if (tx_queue->stopped == 1)
  276. efx_stop_queue(tx_queue->channel);
  277. unwind:
  278. /* Work backwards until we hit the original insert pointer value */
  279. while (tx_queue->insert_count != tx_queue->write_count) {
  280. --tx_queue->insert_count;
  281. insert_ptr = tx_queue->insert_count & tx_queue->ptr_mask;
  282. buffer = &tx_queue->buffer[insert_ptr];
  283. efx_dequeue_buffer(tx_queue, buffer);
  284. buffer->len = 0;
  285. }
  286. /* Free the fragment we were mid-way through pushing */
  287. if (unmap_len) {
  288. if (unmap_single)
  289. pci_unmap_single(pci_dev, unmap_addr, unmap_len,
  290. PCI_DMA_TODEVICE);
  291. else
  292. pci_unmap_page(pci_dev, unmap_addr, unmap_len,
  293. PCI_DMA_TODEVICE);
  294. }
  295. return rc;
  296. }
  297. /* Remove packets from the TX queue
  298. *
  299. * This removes packets from the TX queue, up to and including the
  300. * specified index.
  301. */
  302. static void efx_dequeue_buffers(struct efx_tx_queue *tx_queue,
  303. unsigned int index)
  304. {
  305. struct efx_nic *efx = tx_queue->efx;
  306. unsigned int stop_index, read_ptr;
  307. stop_index = (index + 1) & tx_queue->ptr_mask;
  308. read_ptr = tx_queue->read_count & tx_queue->ptr_mask;
  309. while (read_ptr != stop_index) {
  310. struct efx_tx_buffer *buffer = &tx_queue->buffer[read_ptr];
  311. if (unlikely(buffer->len == 0)) {
  312. netif_err(efx, tx_err, efx->net_dev,
  313. "TX queue %d spurious TX completion id %x\n",
  314. tx_queue->queue, read_ptr);
  315. efx_schedule_reset(efx, RESET_TYPE_TX_SKIP);
  316. return;
  317. }
  318. efx_dequeue_buffer(tx_queue, buffer);
  319. buffer->continuation = true;
  320. buffer->len = 0;
  321. ++tx_queue->read_count;
  322. read_ptr = tx_queue->read_count & tx_queue->ptr_mask;
  323. }
  324. }
  325. /* Initiate a packet transmission. We use one channel per CPU
  326. * (sharing when we have more CPUs than channels). On Falcon, the TX
  327. * completion events will be directed back to the CPU that transmitted
  328. * the packet, which should be cache-efficient.
  329. *
  330. * Context: non-blocking.
  331. * Note that returning anything other than NETDEV_TX_OK will cause the
  332. * OS to free the skb.
  333. */
  334. netdev_tx_t efx_hard_start_xmit(struct sk_buff *skb,
  335. struct net_device *net_dev)
  336. {
  337. struct efx_nic *efx = netdev_priv(net_dev);
  338. struct efx_tx_queue *tx_queue;
  339. if (unlikely(efx->port_inhibited))
  340. return NETDEV_TX_BUSY;
  341. tx_queue = efx_get_tx_queue(efx, skb_get_queue_mapping(skb),
  342. skb->ip_summed == CHECKSUM_PARTIAL ?
  343. EFX_TXQ_TYPE_OFFLOAD : 0);
  344. return efx_enqueue_skb(tx_queue, skb);
  345. }
  346. void efx_xmit_done(struct efx_tx_queue *tx_queue, unsigned int index)
  347. {
  348. unsigned fill_level;
  349. struct efx_nic *efx = tx_queue->efx;
  350. EFX_BUG_ON_PARANOID(index > tx_queue->ptr_mask);
  351. efx_dequeue_buffers(tx_queue, index);
  352. /* See if we need to restart the netif queue. This barrier
  353. * separates the update of read_count from the test of
  354. * stopped. */
  355. smp_mb();
  356. if (unlikely(tx_queue->stopped) && likely(efx->port_enabled)) {
  357. fill_level = tx_queue->insert_count - tx_queue->read_count;
  358. if (fill_level < EFX_TXQ_THRESHOLD(efx)) {
  359. EFX_BUG_ON_PARANOID(!efx_dev_registered(efx));
  360. /* Do this under netif_tx_lock(), to avoid racing
  361. * with efx_xmit(). */
  362. netif_tx_lock(efx->net_dev);
  363. if (tx_queue->stopped) {
  364. tx_queue->stopped = 0;
  365. efx_wake_queue(tx_queue->channel);
  366. }
  367. netif_tx_unlock(efx->net_dev);
  368. }
  369. }
  370. }
  371. int efx_probe_tx_queue(struct efx_tx_queue *tx_queue)
  372. {
  373. struct efx_nic *efx = tx_queue->efx;
  374. unsigned int entries;
  375. int i, rc;
  376. /* Create the smallest power-of-two aligned ring */
  377. entries = max(roundup_pow_of_two(efx->txq_entries), EFX_MIN_DMAQ_SIZE);
  378. EFX_BUG_ON_PARANOID(entries > EFX_MAX_DMAQ_SIZE);
  379. tx_queue->ptr_mask = entries - 1;
  380. netif_dbg(efx, probe, efx->net_dev,
  381. "creating TX queue %d size %#x mask %#x\n",
  382. tx_queue->queue, efx->txq_entries, tx_queue->ptr_mask);
  383. /* Allocate software ring */
  384. tx_queue->buffer = kzalloc(entries * sizeof(*tx_queue->buffer),
  385. GFP_KERNEL);
  386. if (!tx_queue->buffer)
  387. return -ENOMEM;
  388. for (i = 0; i <= tx_queue->ptr_mask; ++i)
  389. tx_queue->buffer[i].continuation = true;
  390. /* Allocate hardware ring */
  391. rc = efx_nic_probe_tx(tx_queue);
  392. if (rc)
  393. goto fail;
  394. return 0;
  395. fail:
  396. kfree(tx_queue->buffer);
  397. tx_queue->buffer = NULL;
  398. return rc;
  399. }
  400. void efx_init_tx_queue(struct efx_tx_queue *tx_queue)
  401. {
  402. netif_dbg(tx_queue->efx, drv, tx_queue->efx->net_dev,
  403. "initialising TX queue %d\n", tx_queue->queue);
  404. tx_queue->insert_count = 0;
  405. tx_queue->write_count = 0;
  406. tx_queue->read_count = 0;
  407. tx_queue->old_read_count = 0;
  408. BUG_ON(tx_queue->stopped);
  409. /* Set up TX descriptor ring */
  410. efx_nic_init_tx(tx_queue);
  411. }
  412. void efx_release_tx_buffers(struct efx_tx_queue *tx_queue)
  413. {
  414. struct efx_tx_buffer *buffer;
  415. if (!tx_queue->buffer)
  416. return;
  417. /* Free any buffers left in the ring */
  418. while (tx_queue->read_count != tx_queue->write_count) {
  419. buffer = &tx_queue->buffer[tx_queue->read_count & tx_queue->ptr_mask];
  420. efx_dequeue_buffer(tx_queue, buffer);
  421. buffer->continuation = true;
  422. buffer->len = 0;
  423. ++tx_queue->read_count;
  424. }
  425. }
  426. void efx_fini_tx_queue(struct efx_tx_queue *tx_queue)
  427. {
  428. netif_dbg(tx_queue->efx, drv, tx_queue->efx->net_dev,
  429. "shutting down TX queue %d\n", tx_queue->queue);
  430. /* Flush TX queue, remove descriptor ring */
  431. efx_nic_fini_tx(tx_queue);
  432. efx_release_tx_buffers(tx_queue);
  433. /* Free up TSO header cache */
  434. efx_fini_tso(tx_queue);
  435. /* Release queue's stop on port, if any */
  436. if (tx_queue->stopped) {
  437. tx_queue->stopped = 0;
  438. efx_wake_queue(tx_queue->channel);
  439. }
  440. }
  441. void efx_remove_tx_queue(struct efx_tx_queue *tx_queue)
  442. {
  443. netif_dbg(tx_queue->efx, drv, tx_queue->efx->net_dev,
  444. "destroying TX queue %d\n", tx_queue->queue);
  445. efx_nic_remove_tx(tx_queue);
  446. kfree(tx_queue->buffer);
  447. tx_queue->buffer = NULL;
  448. }
  449. /* Efx TCP segmentation acceleration.
  450. *
  451. * Why? Because by doing it here in the driver we can go significantly
  452. * faster than the GSO.
  453. *
  454. * Requires TX checksum offload support.
  455. */
  456. /* Number of bytes inserted at the start of a TSO header buffer,
  457. * similar to NET_IP_ALIGN.
  458. */
  459. #ifdef CONFIG_HAVE_EFFICIENT_UNALIGNED_ACCESS
  460. #define TSOH_OFFSET 0
  461. #else
  462. #define TSOH_OFFSET NET_IP_ALIGN
  463. #endif
  464. #define TSOH_BUFFER(tsoh) ((u8 *)(tsoh + 1) + TSOH_OFFSET)
  465. /* Total size of struct efx_tso_header, buffer and padding */
  466. #define TSOH_SIZE(hdr_len) \
  467. (sizeof(struct efx_tso_header) + TSOH_OFFSET + hdr_len)
  468. /* Size of blocks on free list. Larger blocks must be allocated from
  469. * the heap.
  470. */
  471. #define TSOH_STD_SIZE 128
  472. #define PTR_DIFF(p1, p2) ((u8 *)(p1) - (u8 *)(p2))
  473. #define ETH_HDR_LEN(skb) (skb_network_header(skb) - (skb)->data)
  474. #define SKB_TCP_OFF(skb) PTR_DIFF(tcp_hdr(skb), (skb)->data)
  475. #define SKB_IPV4_OFF(skb) PTR_DIFF(ip_hdr(skb), (skb)->data)
  476. #define SKB_IPV6_OFF(skb) PTR_DIFF(ipv6_hdr(skb), (skb)->data)
  477. /**
  478. * struct tso_state - TSO state for an SKB
  479. * @out_len: Remaining length in current segment
  480. * @seqnum: Current sequence number
  481. * @ipv4_id: Current IPv4 ID, host endian
  482. * @packet_space: Remaining space in current packet
  483. * @dma_addr: DMA address of current position
  484. * @in_len: Remaining length in current SKB fragment
  485. * @unmap_len: Length of SKB fragment
  486. * @unmap_addr: DMA address of SKB fragment
  487. * @unmap_single: DMA single vs page mapping flag
  488. * @protocol: Network protocol (after any VLAN header)
  489. * @header_len: Number of bytes of header
  490. * @full_packet_size: Number of bytes to put in each outgoing segment
  491. *
  492. * The state used during segmentation. It is put into this data structure
  493. * just to make it easy to pass into inline functions.
  494. */
  495. struct tso_state {
  496. /* Output position */
  497. unsigned out_len;
  498. unsigned seqnum;
  499. unsigned ipv4_id;
  500. unsigned packet_space;
  501. /* Input position */
  502. dma_addr_t dma_addr;
  503. unsigned in_len;
  504. unsigned unmap_len;
  505. dma_addr_t unmap_addr;
  506. bool unmap_single;
  507. __be16 protocol;
  508. unsigned header_len;
  509. int full_packet_size;
  510. };
  511. /*
  512. * Verify that our various assumptions about sk_buffs and the conditions
  513. * under which TSO will be attempted hold true. Return the protocol number.
  514. */
  515. static __be16 efx_tso_check_protocol(struct sk_buff *skb)
  516. {
  517. __be16 protocol = skb->protocol;
  518. EFX_BUG_ON_PARANOID(((struct ethhdr *)skb->data)->h_proto !=
  519. protocol);
  520. if (protocol == htons(ETH_P_8021Q)) {
  521. /* Find the encapsulated protocol; reset network header
  522. * and transport header based on that. */
  523. struct vlan_ethhdr *veh = (struct vlan_ethhdr *)skb->data;
  524. protocol = veh->h_vlan_encapsulated_proto;
  525. skb_set_network_header(skb, sizeof(*veh));
  526. if (protocol == htons(ETH_P_IP))
  527. skb_set_transport_header(skb, sizeof(*veh) +
  528. 4 * ip_hdr(skb)->ihl);
  529. else if (protocol == htons(ETH_P_IPV6))
  530. skb_set_transport_header(skb, sizeof(*veh) +
  531. sizeof(struct ipv6hdr));
  532. }
  533. if (protocol == htons(ETH_P_IP)) {
  534. EFX_BUG_ON_PARANOID(ip_hdr(skb)->protocol != IPPROTO_TCP);
  535. } else {
  536. EFX_BUG_ON_PARANOID(protocol != htons(ETH_P_IPV6));
  537. EFX_BUG_ON_PARANOID(ipv6_hdr(skb)->nexthdr != NEXTHDR_TCP);
  538. }
  539. EFX_BUG_ON_PARANOID((PTR_DIFF(tcp_hdr(skb), skb->data)
  540. + (tcp_hdr(skb)->doff << 2u)) >
  541. skb_headlen(skb));
  542. return protocol;
  543. }
  544. /*
  545. * Allocate a page worth of efx_tso_header structures, and string them
  546. * into the tx_queue->tso_headers_free linked list. Return 0 or -ENOMEM.
  547. */
  548. static int efx_tsoh_block_alloc(struct efx_tx_queue *tx_queue)
  549. {
  550. struct pci_dev *pci_dev = tx_queue->efx->pci_dev;
  551. struct efx_tso_header *tsoh;
  552. dma_addr_t dma_addr;
  553. u8 *base_kva, *kva;
  554. base_kva = pci_alloc_consistent(pci_dev, PAGE_SIZE, &dma_addr);
  555. if (base_kva == NULL) {
  556. netif_err(tx_queue->efx, tx_err, tx_queue->efx->net_dev,
  557. "Unable to allocate page for TSO headers\n");
  558. return -ENOMEM;
  559. }
  560. /* pci_alloc_consistent() allocates pages. */
  561. EFX_BUG_ON_PARANOID(dma_addr & (PAGE_SIZE - 1u));
  562. for (kva = base_kva; kva < base_kva + PAGE_SIZE; kva += TSOH_STD_SIZE) {
  563. tsoh = (struct efx_tso_header *)kva;
  564. tsoh->dma_addr = dma_addr + (TSOH_BUFFER(tsoh) - base_kva);
  565. tsoh->next = tx_queue->tso_headers_free;
  566. tx_queue->tso_headers_free = tsoh;
  567. }
  568. return 0;
  569. }
  570. /* Free up a TSO header, and all others in the same page. */
  571. static void efx_tsoh_block_free(struct efx_tx_queue *tx_queue,
  572. struct efx_tso_header *tsoh,
  573. struct pci_dev *pci_dev)
  574. {
  575. struct efx_tso_header **p;
  576. unsigned long base_kva;
  577. dma_addr_t base_dma;
  578. base_kva = (unsigned long)tsoh & PAGE_MASK;
  579. base_dma = tsoh->dma_addr & PAGE_MASK;
  580. p = &tx_queue->tso_headers_free;
  581. while (*p != NULL) {
  582. if (((unsigned long)*p & PAGE_MASK) == base_kva)
  583. *p = (*p)->next;
  584. else
  585. p = &(*p)->next;
  586. }
  587. pci_free_consistent(pci_dev, PAGE_SIZE, (void *)base_kva, base_dma);
  588. }
  589. static struct efx_tso_header *
  590. efx_tsoh_heap_alloc(struct efx_tx_queue *tx_queue, size_t header_len)
  591. {
  592. struct efx_tso_header *tsoh;
  593. tsoh = kmalloc(TSOH_SIZE(header_len), GFP_ATOMIC | GFP_DMA);
  594. if (unlikely(!tsoh))
  595. return NULL;
  596. tsoh->dma_addr = pci_map_single(tx_queue->efx->pci_dev,
  597. TSOH_BUFFER(tsoh), header_len,
  598. PCI_DMA_TODEVICE);
  599. if (unlikely(pci_dma_mapping_error(tx_queue->efx->pci_dev,
  600. tsoh->dma_addr))) {
  601. kfree(tsoh);
  602. return NULL;
  603. }
  604. tsoh->unmap_len = header_len;
  605. return tsoh;
  606. }
  607. static void
  608. efx_tsoh_heap_free(struct efx_tx_queue *tx_queue, struct efx_tso_header *tsoh)
  609. {
  610. pci_unmap_single(tx_queue->efx->pci_dev,
  611. tsoh->dma_addr, tsoh->unmap_len,
  612. PCI_DMA_TODEVICE);
  613. kfree(tsoh);
  614. }
  615. /**
  616. * efx_tx_queue_insert - push descriptors onto the TX queue
  617. * @tx_queue: Efx TX queue
  618. * @dma_addr: DMA address of fragment
  619. * @len: Length of fragment
  620. * @final_buffer: The final buffer inserted into the queue
  621. *
  622. * Push descriptors onto the TX queue. Return 0 on success or 1 if
  623. * @tx_queue full.
  624. */
  625. static int efx_tx_queue_insert(struct efx_tx_queue *tx_queue,
  626. dma_addr_t dma_addr, unsigned len,
  627. struct efx_tx_buffer **final_buffer)
  628. {
  629. struct efx_tx_buffer *buffer;
  630. struct efx_nic *efx = tx_queue->efx;
  631. unsigned dma_len, fill_level, insert_ptr;
  632. int q_space;
  633. EFX_BUG_ON_PARANOID(len <= 0);
  634. fill_level = tx_queue->insert_count - tx_queue->old_read_count;
  635. /* -1 as there is no way to represent all descriptors used */
  636. q_space = efx->txq_entries - 1 - fill_level;
  637. while (1) {
  638. if (unlikely(q_space-- <= 0)) {
  639. /* It might be that completions have happened
  640. * since the xmit path last checked. Update
  641. * the xmit path's copy of read_count.
  642. */
  643. ++tx_queue->stopped;
  644. /* This memory barrier protects the change of
  645. * stopped from the access of read_count. */
  646. smp_mb();
  647. tx_queue->old_read_count =
  648. *(volatile unsigned *)&tx_queue->read_count;
  649. fill_level = (tx_queue->insert_count
  650. - tx_queue->old_read_count);
  651. q_space = efx->txq_entries - 1 - fill_level;
  652. if (unlikely(q_space-- <= 0)) {
  653. *final_buffer = NULL;
  654. return 1;
  655. }
  656. smp_mb();
  657. --tx_queue->stopped;
  658. }
  659. insert_ptr = tx_queue->insert_count & tx_queue->ptr_mask;
  660. buffer = &tx_queue->buffer[insert_ptr];
  661. ++tx_queue->insert_count;
  662. EFX_BUG_ON_PARANOID(tx_queue->insert_count -
  663. tx_queue->read_count >=
  664. efx->txq_entries);
  665. efx_tsoh_free(tx_queue, buffer);
  666. EFX_BUG_ON_PARANOID(buffer->len);
  667. EFX_BUG_ON_PARANOID(buffer->unmap_len);
  668. EFX_BUG_ON_PARANOID(buffer->skb);
  669. EFX_BUG_ON_PARANOID(!buffer->continuation);
  670. EFX_BUG_ON_PARANOID(buffer->tsoh);
  671. buffer->dma_addr = dma_addr;
  672. dma_len = efx_max_tx_len(efx, dma_addr);
  673. /* If there is enough space to send then do so */
  674. if (dma_len >= len)
  675. break;
  676. buffer->len = dma_len; /* Don't set the other members */
  677. dma_addr += dma_len;
  678. len -= dma_len;
  679. }
  680. EFX_BUG_ON_PARANOID(!len);
  681. buffer->len = len;
  682. *final_buffer = buffer;
  683. return 0;
  684. }
  685. /*
  686. * Put a TSO header into the TX queue.
  687. *
  688. * This is special-cased because we know that it is small enough to fit in
  689. * a single fragment, and we know it doesn't cross a page boundary. It
  690. * also allows us to not worry about end-of-packet etc.
  691. */
  692. static void efx_tso_put_header(struct efx_tx_queue *tx_queue,
  693. struct efx_tso_header *tsoh, unsigned len)
  694. {
  695. struct efx_tx_buffer *buffer;
  696. buffer = &tx_queue->buffer[tx_queue->insert_count & tx_queue->ptr_mask];
  697. efx_tsoh_free(tx_queue, buffer);
  698. EFX_BUG_ON_PARANOID(buffer->len);
  699. EFX_BUG_ON_PARANOID(buffer->unmap_len);
  700. EFX_BUG_ON_PARANOID(buffer->skb);
  701. EFX_BUG_ON_PARANOID(!buffer->continuation);
  702. EFX_BUG_ON_PARANOID(buffer->tsoh);
  703. buffer->len = len;
  704. buffer->dma_addr = tsoh->dma_addr;
  705. buffer->tsoh = tsoh;
  706. ++tx_queue->insert_count;
  707. }
  708. /* Remove descriptors put into a tx_queue. */
  709. static void efx_enqueue_unwind(struct efx_tx_queue *tx_queue)
  710. {
  711. struct efx_tx_buffer *buffer;
  712. dma_addr_t unmap_addr;
  713. /* Work backwards until we hit the original insert pointer value */
  714. while (tx_queue->insert_count != tx_queue->write_count) {
  715. --tx_queue->insert_count;
  716. buffer = &tx_queue->buffer[tx_queue->insert_count &
  717. tx_queue->ptr_mask];
  718. efx_tsoh_free(tx_queue, buffer);
  719. EFX_BUG_ON_PARANOID(buffer->skb);
  720. if (buffer->unmap_len) {
  721. unmap_addr = (buffer->dma_addr + buffer->len -
  722. buffer->unmap_len);
  723. if (buffer->unmap_single)
  724. pci_unmap_single(tx_queue->efx->pci_dev,
  725. unmap_addr, buffer->unmap_len,
  726. PCI_DMA_TODEVICE);
  727. else
  728. pci_unmap_page(tx_queue->efx->pci_dev,
  729. unmap_addr, buffer->unmap_len,
  730. PCI_DMA_TODEVICE);
  731. buffer->unmap_len = 0;
  732. }
  733. buffer->len = 0;
  734. buffer->continuation = true;
  735. }
  736. }
  737. /* Parse the SKB header and initialise state. */
  738. static void tso_start(struct tso_state *st, const struct sk_buff *skb)
  739. {
  740. /* All ethernet/IP/TCP headers combined size is TCP header size
  741. * plus offset of TCP header relative to start of packet.
  742. */
  743. st->header_len = ((tcp_hdr(skb)->doff << 2u)
  744. + PTR_DIFF(tcp_hdr(skb), skb->data));
  745. st->full_packet_size = st->header_len + skb_shinfo(skb)->gso_size;
  746. if (st->protocol == htons(ETH_P_IP))
  747. st->ipv4_id = ntohs(ip_hdr(skb)->id);
  748. else
  749. st->ipv4_id = 0;
  750. st->seqnum = ntohl(tcp_hdr(skb)->seq);
  751. EFX_BUG_ON_PARANOID(tcp_hdr(skb)->urg);
  752. EFX_BUG_ON_PARANOID(tcp_hdr(skb)->syn);
  753. EFX_BUG_ON_PARANOID(tcp_hdr(skb)->rst);
  754. st->packet_space = st->full_packet_size;
  755. st->out_len = skb->len - st->header_len;
  756. st->unmap_len = 0;
  757. st->unmap_single = false;
  758. }
  759. static int tso_get_fragment(struct tso_state *st, struct efx_nic *efx,
  760. skb_frag_t *frag)
  761. {
  762. st->unmap_addr = pci_map_page(efx->pci_dev, frag->page,
  763. frag->page_offset, frag->size,
  764. PCI_DMA_TODEVICE);
  765. if (likely(!pci_dma_mapping_error(efx->pci_dev, st->unmap_addr))) {
  766. st->unmap_single = false;
  767. st->unmap_len = frag->size;
  768. st->in_len = frag->size;
  769. st->dma_addr = st->unmap_addr;
  770. return 0;
  771. }
  772. return -ENOMEM;
  773. }
  774. static int tso_get_head_fragment(struct tso_state *st, struct efx_nic *efx,
  775. const struct sk_buff *skb)
  776. {
  777. int hl = st->header_len;
  778. int len = skb_headlen(skb) - hl;
  779. st->unmap_addr = pci_map_single(efx->pci_dev, skb->data + hl,
  780. len, PCI_DMA_TODEVICE);
  781. if (likely(!pci_dma_mapping_error(efx->pci_dev, st->unmap_addr))) {
  782. st->unmap_single = true;
  783. st->unmap_len = len;
  784. st->in_len = len;
  785. st->dma_addr = st->unmap_addr;
  786. return 0;
  787. }
  788. return -ENOMEM;
  789. }
  790. /**
  791. * tso_fill_packet_with_fragment - form descriptors for the current fragment
  792. * @tx_queue: Efx TX queue
  793. * @skb: Socket buffer
  794. * @st: TSO state
  795. *
  796. * Form descriptors for the current fragment, until we reach the end
  797. * of fragment or end-of-packet. Return 0 on success, 1 if not enough
  798. * space in @tx_queue.
  799. */
  800. static int tso_fill_packet_with_fragment(struct efx_tx_queue *tx_queue,
  801. const struct sk_buff *skb,
  802. struct tso_state *st)
  803. {
  804. struct efx_tx_buffer *buffer;
  805. int n, end_of_packet, rc;
  806. if (st->in_len == 0)
  807. return 0;
  808. if (st->packet_space == 0)
  809. return 0;
  810. EFX_BUG_ON_PARANOID(st->in_len <= 0);
  811. EFX_BUG_ON_PARANOID(st->packet_space <= 0);
  812. n = min(st->in_len, st->packet_space);
  813. st->packet_space -= n;
  814. st->out_len -= n;
  815. st->in_len -= n;
  816. rc = efx_tx_queue_insert(tx_queue, st->dma_addr, n, &buffer);
  817. if (likely(rc == 0)) {
  818. if (st->out_len == 0)
  819. /* Transfer ownership of the skb */
  820. buffer->skb = skb;
  821. end_of_packet = st->out_len == 0 || st->packet_space == 0;
  822. buffer->continuation = !end_of_packet;
  823. if (st->in_len == 0) {
  824. /* Transfer ownership of the pci mapping */
  825. buffer->unmap_len = st->unmap_len;
  826. buffer->unmap_single = st->unmap_single;
  827. st->unmap_len = 0;
  828. }
  829. }
  830. st->dma_addr += n;
  831. return rc;
  832. }
  833. /**
  834. * tso_start_new_packet - generate a new header and prepare for the new packet
  835. * @tx_queue: Efx TX queue
  836. * @skb: Socket buffer
  837. * @st: TSO state
  838. *
  839. * Generate a new header and prepare for the new packet. Return 0 on
  840. * success, or -1 if failed to alloc header.
  841. */
  842. static int tso_start_new_packet(struct efx_tx_queue *tx_queue,
  843. const struct sk_buff *skb,
  844. struct tso_state *st)
  845. {
  846. struct efx_tso_header *tsoh;
  847. struct tcphdr *tsoh_th;
  848. unsigned ip_length;
  849. u8 *header;
  850. /* Allocate a DMA-mapped header buffer. */
  851. if (likely(TSOH_SIZE(st->header_len) <= TSOH_STD_SIZE)) {
  852. if (tx_queue->tso_headers_free == NULL) {
  853. if (efx_tsoh_block_alloc(tx_queue))
  854. return -1;
  855. }
  856. EFX_BUG_ON_PARANOID(!tx_queue->tso_headers_free);
  857. tsoh = tx_queue->tso_headers_free;
  858. tx_queue->tso_headers_free = tsoh->next;
  859. tsoh->unmap_len = 0;
  860. } else {
  861. tx_queue->tso_long_headers++;
  862. tsoh = efx_tsoh_heap_alloc(tx_queue, st->header_len);
  863. if (unlikely(!tsoh))
  864. return -1;
  865. }
  866. header = TSOH_BUFFER(tsoh);
  867. tsoh_th = (struct tcphdr *)(header + SKB_TCP_OFF(skb));
  868. /* Copy and update the headers. */
  869. memcpy(header, skb->data, st->header_len);
  870. tsoh_th->seq = htonl(st->seqnum);
  871. st->seqnum += skb_shinfo(skb)->gso_size;
  872. if (st->out_len > skb_shinfo(skb)->gso_size) {
  873. /* This packet will not finish the TSO burst. */
  874. ip_length = st->full_packet_size - ETH_HDR_LEN(skb);
  875. tsoh_th->fin = 0;
  876. tsoh_th->psh = 0;
  877. } else {
  878. /* This packet will be the last in the TSO burst. */
  879. ip_length = st->header_len - ETH_HDR_LEN(skb) + st->out_len;
  880. tsoh_th->fin = tcp_hdr(skb)->fin;
  881. tsoh_th->psh = tcp_hdr(skb)->psh;
  882. }
  883. if (st->protocol == htons(ETH_P_IP)) {
  884. struct iphdr *tsoh_iph =
  885. (struct iphdr *)(header + SKB_IPV4_OFF(skb));
  886. tsoh_iph->tot_len = htons(ip_length);
  887. /* Linux leaves suitable gaps in the IP ID space for us to fill. */
  888. tsoh_iph->id = htons(st->ipv4_id);
  889. st->ipv4_id++;
  890. } else {
  891. struct ipv6hdr *tsoh_iph =
  892. (struct ipv6hdr *)(header + SKB_IPV6_OFF(skb));
  893. tsoh_iph->payload_len = htons(ip_length - sizeof(*tsoh_iph));
  894. }
  895. st->packet_space = skb_shinfo(skb)->gso_size;
  896. ++tx_queue->tso_packets;
  897. /* Form a descriptor for this header. */
  898. efx_tso_put_header(tx_queue, tsoh, st->header_len);
  899. return 0;
  900. }
  901. /**
  902. * efx_enqueue_skb_tso - segment and transmit a TSO socket buffer
  903. * @tx_queue: Efx TX queue
  904. * @skb: Socket buffer
  905. *
  906. * Context: You must hold netif_tx_lock() to call this function.
  907. *
  908. * Add socket buffer @skb to @tx_queue, doing TSO or return != 0 if
  909. * @skb was not enqueued. In all cases @skb is consumed. Return
  910. * %NETDEV_TX_OK or %NETDEV_TX_BUSY.
  911. */
  912. static int efx_enqueue_skb_tso(struct efx_tx_queue *tx_queue,
  913. struct sk_buff *skb)
  914. {
  915. struct efx_nic *efx = tx_queue->efx;
  916. int frag_i, rc, rc2 = NETDEV_TX_OK;
  917. struct tso_state state;
  918. /* Find the packet protocol and sanity-check it */
  919. state.protocol = efx_tso_check_protocol(skb);
  920. EFX_BUG_ON_PARANOID(tx_queue->write_count != tx_queue->insert_count);
  921. tso_start(&state, skb);
  922. /* Assume that skb header area contains exactly the headers, and
  923. * all payload is in the frag list.
  924. */
  925. if (skb_headlen(skb) == state.header_len) {
  926. /* Grab the first payload fragment. */
  927. EFX_BUG_ON_PARANOID(skb_shinfo(skb)->nr_frags < 1);
  928. frag_i = 0;
  929. rc = tso_get_fragment(&state, efx,
  930. skb_shinfo(skb)->frags + frag_i);
  931. if (rc)
  932. goto mem_err;
  933. } else {
  934. rc = tso_get_head_fragment(&state, efx, skb);
  935. if (rc)
  936. goto mem_err;
  937. frag_i = -1;
  938. }
  939. if (tso_start_new_packet(tx_queue, skb, &state) < 0)
  940. goto mem_err;
  941. while (1) {
  942. rc = tso_fill_packet_with_fragment(tx_queue, skb, &state);
  943. if (unlikely(rc))
  944. goto stop;
  945. /* Move onto the next fragment? */
  946. if (state.in_len == 0) {
  947. if (++frag_i >= skb_shinfo(skb)->nr_frags)
  948. /* End of payload reached. */
  949. break;
  950. rc = tso_get_fragment(&state, efx,
  951. skb_shinfo(skb)->frags + frag_i);
  952. if (rc)
  953. goto mem_err;
  954. }
  955. /* Start at new packet? */
  956. if (state.packet_space == 0 &&
  957. tso_start_new_packet(tx_queue, skb, &state) < 0)
  958. goto mem_err;
  959. }
  960. /* Pass off to hardware */
  961. efx_nic_push_buffers(tx_queue);
  962. tx_queue->tso_bursts++;
  963. return NETDEV_TX_OK;
  964. mem_err:
  965. netif_err(efx, tx_err, efx->net_dev,
  966. "Out of memory for TSO headers, or PCI mapping error\n");
  967. dev_kfree_skb_any(skb);
  968. goto unwind;
  969. stop:
  970. rc2 = NETDEV_TX_BUSY;
  971. /* Stop the queue if it wasn't stopped before. */
  972. if (tx_queue->stopped == 1)
  973. efx_stop_queue(tx_queue->channel);
  974. unwind:
  975. /* Free the DMA mapping we were in the process of writing out */
  976. if (state.unmap_len) {
  977. if (state.unmap_single)
  978. pci_unmap_single(efx->pci_dev, state.unmap_addr,
  979. state.unmap_len, PCI_DMA_TODEVICE);
  980. else
  981. pci_unmap_page(efx->pci_dev, state.unmap_addr,
  982. state.unmap_len, PCI_DMA_TODEVICE);
  983. }
  984. efx_enqueue_unwind(tx_queue);
  985. return rc2;
  986. }
  987. /*
  988. * Free up all TSO datastructures associated with tx_queue. This
  989. * routine should be called only once the tx_queue is both empty and
  990. * will no longer be used.
  991. */
  992. static void efx_fini_tso(struct efx_tx_queue *tx_queue)
  993. {
  994. unsigned i;
  995. if (tx_queue->buffer) {
  996. for (i = 0; i <= tx_queue->ptr_mask; ++i)
  997. efx_tsoh_free(tx_queue, &tx_queue->buffer[i]);
  998. }
  999. while (tx_queue->tso_headers_free != NULL)
  1000. efx_tsoh_block_free(tx_queue, tx_queue->tso_headers_free,
  1001. tx_queue->efx->pci_dev);
  1002. }