cnic.c 126 KB

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  1. /* cnic.c: Broadcom CNIC core network driver.
  2. *
  3. * Copyright (c) 2006-2010 Broadcom Corporation
  4. *
  5. * This program is free software; you can redistribute it and/or modify
  6. * it under the terms of the GNU General Public License as published by
  7. * the Free Software Foundation.
  8. *
  9. * Original skeleton written by: John(Zongxi) Chen (zongxi@broadcom.com)
  10. * Modified and maintained by: Michael Chan <mchan@broadcom.com>
  11. */
  12. #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
  13. #include <linux/module.h>
  14. #include <linux/kernel.h>
  15. #include <linux/errno.h>
  16. #include <linux/list.h>
  17. #include <linux/slab.h>
  18. #include <linux/pci.h>
  19. #include <linux/init.h>
  20. #include <linux/netdevice.h>
  21. #include <linux/uio_driver.h>
  22. #include <linux/in.h>
  23. #include <linux/dma-mapping.h>
  24. #include <linux/delay.h>
  25. #include <linux/ethtool.h>
  26. #include <linux/if_vlan.h>
  27. #if defined(CONFIG_VLAN_8021Q) || defined(CONFIG_VLAN_8021Q_MODULE)
  28. #define BCM_VLAN 1
  29. #endif
  30. #include <net/ip.h>
  31. #include <net/tcp.h>
  32. #include <net/route.h>
  33. #include <net/ipv6.h>
  34. #include <net/ip6_route.h>
  35. #include <net/ip6_checksum.h>
  36. #include <scsi/iscsi_if.h>
  37. #include "cnic_if.h"
  38. #include "bnx2.h"
  39. #include "bnx2x/bnx2x_reg.h"
  40. #include "bnx2x/bnx2x_fw_defs.h"
  41. #include "bnx2x/bnx2x_hsi.h"
  42. #include "../scsi/bnx2i/57xx_iscsi_constants.h"
  43. #include "../scsi/bnx2i/57xx_iscsi_hsi.h"
  44. #include "cnic.h"
  45. #include "cnic_defs.h"
  46. #define DRV_MODULE_NAME "cnic"
  47. static char version[] __devinitdata =
  48. "Broadcom NetXtreme II CNIC Driver " DRV_MODULE_NAME " v" CNIC_MODULE_VERSION " (" CNIC_MODULE_RELDATE ")\n";
  49. MODULE_AUTHOR("Michael Chan <mchan@broadcom.com> and John(Zongxi) "
  50. "Chen (zongxi@broadcom.com");
  51. MODULE_DESCRIPTION("Broadcom NetXtreme II CNIC Driver");
  52. MODULE_LICENSE("GPL");
  53. MODULE_VERSION(CNIC_MODULE_VERSION);
  54. static LIST_HEAD(cnic_dev_list);
  55. static LIST_HEAD(cnic_udev_list);
  56. static DEFINE_RWLOCK(cnic_dev_lock);
  57. static DEFINE_MUTEX(cnic_lock);
  58. static struct cnic_ulp_ops *cnic_ulp_tbl[MAX_CNIC_ULP_TYPE];
  59. static int cnic_service_bnx2(void *, void *);
  60. static int cnic_service_bnx2x(void *, void *);
  61. static int cnic_ctl(void *, struct cnic_ctl_info *);
  62. static struct cnic_ops cnic_bnx2_ops = {
  63. .cnic_owner = THIS_MODULE,
  64. .cnic_handler = cnic_service_bnx2,
  65. .cnic_ctl = cnic_ctl,
  66. };
  67. static struct cnic_ops cnic_bnx2x_ops = {
  68. .cnic_owner = THIS_MODULE,
  69. .cnic_handler = cnic_service_bnx2x,
  70. .cnic_ctl = cnic_ctl,
  71. };
  72. static struct workqueue_struct *cnic_wq;
  73. static void cnic_shutdown_rings(struct cnic_dev *);
  74. static void cnic_init_rings(struct cnic_dev *);
  75. static int cnic_cm_set_pg(struct cnic_sock *);
  76. static int cnic_uio_open(struct uio_info *uinfo, struct inode *inode)
  77. {
  78. struct cnic_uio_dev *udev = uinfo->priv;
  79. struct cnic_dev *dev;
  80. if (!capable(CAP_NET_ADMIN))
  81. return -EPERM;
  82. if (udev->uio_dev != -1)
  83. return -EBUSY;
  84. rtnl_lock();
  85. dev = udev->dev;
  86. if (!dev || !test_bit(CNIC_F_CNIC_UP, &dev->flags)) {
  87. rtnl_unlock();
  88. return -ENODEV;
  89. }
  90. udev->uio_dev = iminor(inode);
  91. cnic_shutdown_rings(dev);
  92. cnic_init_rings(dev);
  93. rtnl_unlock();
  94. return 0;
  95. }
  96. static int cnic_uio_close(struct uio_info *uinfo, struct inode *inode)
  97. {
  98. struct cnic_uio_dev *udev = uinfo->priv;
  99. udev->uio_dev = -1;
  100. return 0;
  101. }
  102. static inline void cnic_hold(struct cnic_dev *dev)
  103. {
  104. atomic_inc(&dev->ref_count);
  105. }
  106. static inline void cnic_put(struct cnic_dev *dev)
  107. {
  108. atomic_dec(&dev->ref_count);
  109. }
  110. static inline void csk_hold(struct cnic_sock *csk)
  111. {
  112. atomic_inc(&csk->ref_count);
  113. }
  114. static inline void csk_put(struct cnic_sock *csk)
  115. {
  116. atomic_dec(&csk->ref_count);
  117. }
  118. static struct cnic_dev *cnic_from_netdev(struct net_device *netdev)
  119. {
  120. struct cnic_dev *cdev;
  121. read_lock(&cnic_dev_lock);
  122. list_for_each_entry(cdev, &cnic_dev_list, list) {
  123. if (netdev == cdev->netdev) {
  124. cnic_hold(cdev);
  125. read_unlock(&cnic_dev_lock);
  126. return cdev;
  127. }
  128. }
  129. read_unlock(&cnic_dev_lock);
  130. return NULL;
  131. }
  132. static inline void ulp_get(struct cnic_ulp_ops *ulp_ops)
  133. {
  134. atomic_inc(&ulp_ops->ref_count);
  135. }
  136. static inline void ulp_put(struct cnic_ulp_ops *ulp_ops)
  137. {
  138. atomic_dec(&ulp_ops->ref_count);
  139. }
  140. static void cnic_ctx_wr(struct cnic_dev *dev, u32 cid_addr, u32 off, u32 val)
  141. {
  142. struct cnic_local *cp = dev->cnic_priv;
  143. struct cnic_eth_dev *ethdev = cp->ethdev;
  144. struct drv_ctl_info info;
  145. struct drv_ctl_io *io = &info.data.io;
  146. info.cmd = DRV_CTL_CTX_WR_CMD;
  147. io->cid_addr = cid_addr;
  148. io->offset = off;
  149. io->data = val;
  150. ethdev->drv_ctl(dev->netdev, &info);
  151. }
  152. static void cnic_ctx_tbl_wr(struct cnic_dev *dev, u32 off, dma_addr_t addr)
  153. {
  154. struct cnic_local *cp = dev->cnic_priv;
  155. struct cnic_eth_dev *ethdev = cp->ethdev;
  156. struct drv_ctl_info info;
  157. struct drv_ctl_io *io = &info.data.io;
  158. info.cmd = DRV_CTL_CTXTBL_WR_CMD;
  159. io->offset = off;
  160. io->dma_addr = addr;
  161. ethdev->drv_ctl(dev->netdev, &info);
  162. }
  163. static void cnic_ring_ctl(struct cnic_dev *dev, u32 cid, u32 cl_id, int start)
  164. {
  165. struct cnic_local *cp = dev->cnic_priv;
  166. struct cnic_eth_dev *ethdev = cp->ethdev;
  167. struct drv_ctl_info info;
  168. struct drv_ctl_l2_ring *ring = &info.data.ring;
  169. if (start)
  170. info.cmd = DRV_CTL_START_L2_CMD;
  171. else
  172. info.cmd = DRV_CTL_STOP_L2_CMD;
  173. ring->cid = cid;
  174. ring->client_id = cl_id;
  175. ethdev->drv_ctl(dev->netdev, &info);
  176. }
  177. static void cnic_reg_wr_ind(struct cnic_dev *dev, u32 off, u32 val)
  178. {
  179. struct cnic_local *cp = dev->cnic_priv;
  180. struct cnic_eth_dev *ethdev = cp->ethdev;
  181. struct drv_ctl_info info;
  182. struct drv_ctl_io *io = &info.data.io;
  183. info.cmd = DRV_CTL_IO_WR_CMD;
  184. io->offset = off;
  185. io->data = val;
  186. ethdev->drv_ctl(dev->netdev, &info);
  187. }
  188. static u32 cnic_reg_rd_ind(struct cnic_dev *dev, u32 off)
  189. {
  190. struct cnic_local *cp = dev->cnic_priv;
  191. struct cnic_eth_dev *ethdev = cp->ethdev;
  192. struct drv_ctl_info info;
  193. struct drv_ctl_io *io = &info.data.io;
  194. info.cmd = DRV_CTL_IO_RD_CMD;
  195. io->offset = off;
  196. ethdev->drv_ctl(dev->netdev, &info);
  197. return io->data;
  198. }
  199. static int cnic_in_use(struct cnic_sock *csk)
  200. {
  201. return test_bit(SK_F_INUSE, &csk->flags);
  202. }
  203. static void cnic_spq_completion(struct cnic_dev *dev, int cmd, u32 count)
  204. {
  205. struct cnic_local *cp = dev->cnic_priv;
  206. struct cnic_eth_dev *ethdev = cp->ethdev;
  207. struct drv_ctl_info info;
  208. info.cmd = cmd;
  209. info.data.credit.credit_count = count;
  210. ethdev->drv_ctl(dev->netdev, &info);
  211. }
  212. static int cnic_get_l5_cid(struct cnic_local *cp, u32 cid, u32 *l5_cid)
  213. {
  214. u32 i;
  215. for (i = 0; i < cp->max_cid_space; i++) {
  216. if (cp->ctx_tbl[i].cid == cid) {
  217. *l5_cid = i;
  218. return 0;
  219. }
  220. }
  221. return -EINVAL;
  222. }
  223. static int cnic_send_nlmsg(struct cnic_local *cp, u32 type,
  224. struct cnic_sock *csk)
  225. {
  226. struct iscsi_path path_req;
  227. char *buf = NULL;
  228. u16 len = 0;
  229. u32 msg_type = ISCSI_KEVENT_IF_DOWN;
  230. struct cnic_ulp_ops *ulp_ops;
  231. struct cnic_uio_dev *udev = cp->udev;
  232. if (!udev || udev->uio_dev == -1)
  233. return -ENODEV;
  234. if (csk) {
  235. len = sizeof(path_req);
  236. buf = (char *) &path_req;
  237. memset(&path_req, 0, len);
  238. msg_type = ISCSI_KEVENT_PATH_REQ;
  239. path_req.handle = (u64) csk->l5_cid;
  240. if (test_bit(SK_F_IPV6, &csk->flags)) {
  241. memcpy(&path_req.dst.v6_addr, &csk->dst_ip[0],
  242. sizeof(struct in6_addr));
  243. path_req.ip_addr_len = 16;
  244. } else {
  245. memcpy(&path_req.dst.v4_addr, &csk->dst_ip[0],
  246. sizeof(struct in_addr));
  247. path_req.ip_addr_len = 4;
  248. }
  249. path_req.vlan_id = csk->vlan_id;
  250. path_req.pmtu = csk->mtu;
  251. }
  252. rcu_read_lock();
  253. ulp_ops = rcu_dereference(cnic_ulp_tbl[CNIC_ULP_ISCSI]);
  254. if (ulp_ops)
  255. ulp_ops->iscsi_nl_send_msg(cp->dev, msg_type, buf, len);
  256. rcu_read_unlock();
  257. return 0;
  258. }
  259. static int cnic_iscsi_nl_msg_recv(struct cnic_dev *dev, u32 msg_type,
  260. char *buf, u16 len)
  261. {
  262. int rc = -EINVAL;
  263. switch (msg_type) {
  264. case ISCSI_UEVENT_PATH_UPDATE: {
  265. struct cnic_local *cp;
  266. u32 l5_cid;
  267. struct cnic_sock *csk;
  268. struct iscsi_path *path_resp;
  269. if (len < sizeof(*path_resp))
  270. break;
  271. path_resp = (struct iscsi_path *) buf;
  272. cp = dev->cnic_priv;
  273. l5_cid = (u32) path_resp->handle;
  274. if (l5_cid >= MAX_CM_SK_TBL_SZ)
  275. break;
  276. rcu_read_lock();
  277. if (!rcu_dereference(cp->ulp_ops[CNIC_ULP_L4])) {
  278. rc = -ENODEV;
  279. rcu_read_unlock();
  280. break;
  281. }
  282. csk = &cp->csk_tbl[l5_cid];
  283. csk_hold(csk);
  284. if (cnic_in_use(csk)) {
  285. memcpy(csk->ha, path_resp->mac_addr, 6);
  286. if (test_bit(SK_F_IPV6, &csk->flags))
  287. memcpy(&csk->src_ip[0], &path_resp->src.v6_addr,
  288. sizeof(struct in6_addr));
  289. else
  290. memcpy(&csk->src_ip[0], &path_resp->src.v4_addr,
  291. sizeof(struct in_addr));
  292. if (is_valid_ether_addr(csk->ha))
  293. cnic_cm_set_pg(csk);
  294. }
  295. csk_put(csk);
  296. rcu_read_unlock();
  297. rc = 0;
  298. }
  299. }
  300. return rc;
  301. }
  302. static int cnic_offld_prep(struct cnic_sock *csk)
  303. {
  304. if (test_and_set_bit(SK_F_OFFLD_SCHED, &csk->flags))
  305. return 0;
  306. if (!test_bit(SK_F_CONNECT_START, &csk->flags)) {
  307. clear_bit(SK_F_OFFLD_SCHED, &csk->flags);
  308. return 0;
  309. }
  310. return 1;
  311. }
  312. static int cnic_close_prep(struct cnic_sock *csk)
  313. {
  314. clear_bit(SK_F_CONNECT_START, &csk->flags);
  315. smp_mb__after_clear_bit();
  316. if (test_and_clear_bit(SK_F_OFFLD_COMPLETE, &csk->flags)) {
  317. while (test_and_set_bit(SK_F_OFFLD_SCHED, &csk->flags))
  318. msleep(1);
  319. return 1;
  320. }
  321. return 0;
  322. }
  323. static int cnic_abort_prep(struct cnic_sock *csk)
  324. {
  325. clear_bit(SK_F_CONNECT_START, &csk->flags);
  326. smp_mb__after_clear_bit();
  327. while (test_and_set_bit(SK_F_OFFLD_SCHED, &csk->flags))
  328. msleep(1);
  329. if (test_and_clear_bit(SK_F_OFFLD_COMPLETE, &csk->flags)) {
  330. csk->state = L4_KCQE_OPCODE_VALUE_RESET_COMP;
  331. return 1;
  332. }
  333. return 0;
  334. }
  335. static void cnic_uio_stop(void)
  336. {
  337. struct cnic_dev *dev;
  338. read_lock(&cnic_dev_lock);
  339. list_for_each_entry(dev, &cnic_dev_list, list) {
  340. struct cnic_local *cp = dev->cnic_priv;
  341. cnic_send_nlmsg(cp, ISCSI_KEVENT_IF_DOWN, NULL);
  342. }
  343. read_unlock(&cnic_dev_lock);
  344. }
  345. int cnic_register_driver(int ulp_type, struct cnic_ulp_ops *ulp_ops)
  346. {
  347. struct cnic_dev *dev;
  348. if (ulp_type < 0 || ulp_type >= MAX_CNIC_ULP_TYPE) {
  349. pr_err("%s: Bad type %d\n", __func__, ulp_type);
  350. return -EINVAL;
  351. }
  352. mutex_lock(&cnic_lock);
  353. if (cnic_ulp_tbl[ulp_type]) {
  354. pr_err("%s: Type %d has already been registered\n",
  355. __func__, ulp_type);
  356. mutex_unlock(&cnic_lock);
  357. return -EBUSY;
  358. }
  359. read_lock(&cnic_dev_lock);
  360. list_for_each_entry(dev, &cnic_dev_list, list) {
  361. struct cnic_local *cp = dev->cnic_priv;
  362. clear_bit(ULP_F_INIT, &cp->ulp_flags[ulp_type]);
  363. }
  364. read_unlock(&cnic_dev_lock);
  365. atomic_set(&ulp_ops->ref_count, 0);
  366. rcu_assign_pointer(cnic_ulp_tbl[ulp_type], ulp_ops);
  367. mutex_unlock(&cnic_lock);
  368. /* Prevent race conditions with netdev_event */
  369. rtnl_lock();
  370. read_lock(&cnic_dev_lock);
  371. list_for_each_entry(dev, &cnic_dev_list, list) {
  372. struct cnic_local *cp = dev->cnic_priv;
  373. if (!test_and_set_bit(ULP_F_INIT, &cp->ulp_flags[ulp_type]))
  374. ulp_ops->cnic_init(dev);
  375. }
  376. read_unlock(&cnic_dev_lock);
  377. rtnl_unlock();
  378. return 0;
  379. }
  380. int cnic_unregister_driver(int ulp_type)
  381. {
  382. struct cnic_dev *dev;
  383. struct cnic_ulp_ops *ulp_ops;
  384. int i = 0;
  385. if (ulp_type < 0 || ulp_type >= MAX_CNIC_ULP_TYPE) {
  386. pr_err("%s: Bad type %d\n", __func__, ulp_type);
  387. return -EINVAL;
  388. }
  389. mutex_lock(&cnic_lock);
  390. ulp_ops = cnic_ulp_tbl[ulp_type];
  391. if (!ulp_ops) {
  392. pr_err("%s: Type %d has not been registered\n",
  393. __func__, ulp_type);
  394. goto out_unlock;
  395. }
  396. read_lock(&cnic_dev_lock);
  397. list_for_each_entry(dev, &cnic_dev_list, list) {
  398. struct cnic_local *cp = dev->cnic_priv;
  399. if (rcu_dereference(cp->ulp_ops[ulp_type])) {
  400. pr_err("%s: Type %d still has devices registered\n",
  401. __func__, ulp_type);
  402. read_unlock(&cnic_dev_lock);
  403. goto out_unlock;
  404. }
  405. }
  406. read_unlock(&cnic_dev_lock);
  407. if (ulp_type == CNIC_ULP_ISCSI)
  408. cnic_uio_stop();
  409. rcu_assign_pointer(cnic_ulp_tbl[ulp_type], NULL);
  410. mutex_unlock(&cnic_lock);
  411. synchronize_rcu();
  412. while ((atomic_read(&ulp_ops->ref_count) != 0) && (i < 20)) {
  413. msleep(100);
  414. i++;
  415. }
  416. if (atomic_read(&ulp_ops->ref_count) != 0)
  417. netdev_warn(dev->netdev, "Failed waiting for ref count to go to zero\n");
  418. return 0;
  419. out_unlock:
  420. mutex_unlock(&cnic_lock);
  421. return -EINVAL;
  422. }
  423. static int cnic_start_hw(struct cnic_dev *);
  424. static void cnic_stop_hw(struct cnic_dev *);
  425. static int cnic_register_device(struct cnic_dev *dev, int ulp_type,
  426. void *ulp_ctx)
  427. {
  428. struct cnic_local *cp = dev->cnic_priv;
  429. struct cnic_ulp_ops *ulp_ops;
  430. if (ulp_type < 0 || ulp_type >= MAX_CNIC_ULP_TYPE) {
  431. pr_err("%s: Bad type %d\n", __func__, ulp_type);
  432. return -EINVAL;
  433. }
  434. mutex_lock(&cnic_lock);
  435. if (cnic_ulp_tbl[ulp_type] == NULL) {
  436. pr_err("%s: Driver with type %d has not been registered\n",
  437. __func__, ulp_type);
  438. mutex_unlock(&cnic_lock);
  439. return -EAGAIN;
  440. }
  441. if (rcu_dereference(cp->ulp_ops[ulp_type])) {
  442. pr_err("%s: Type %d has already been registered to this device\n",
  443. __func__, ulp_type);
  444. mutex_unlock(&cnic_lock);
  445. return -EBUSY;
  446. }
  447. clear_bit(ULP_F_START, &cp->ulp_flags[ulp_type]);
  448. cp->ulp_handle[ulp_type] = ulp_ctx;
  449. ulp_ops = cnic_ulp_tbl[ulp_type];
  450. rcu_assign_pointer(cp->ulp_ops[ulp_type], ulp_ops);
  451. cnic_hold(dev);
  452. if (test_bit(CNIC_F_CNIC_UP, &dev->flags))
  453. if (!test_and_set_bit(ULP_F_START, &cp->ulp_flags[ulp_type]))
  454. ulp_ops->cnic_start(cp->ulp_handle[ulp_type]);
  455. mutex_unlock(&cnic_lock);
  456. return 0;
  457. }
  458. EXPORT_SYMBOL(cnic_register_driver);
  459. static int cnic_unregister_device(struct cnic_dev *dev, int ulp_type)
  460. {
  461. struct cnic_local *cp = dev->cnic_priv;
  462. int i = 0;
  463. if (ulp_type < 0 || ulp_type >= MAX_CNIC_ULP_TYPE) {
  464. pr_err("%s: Bad type %d\n", __func__, ulp_type);
  465. return -EINVAL;
  466. }
  467. mutex_lock(&cnic_lock);
  468. if (rcu_dereference(cp->ulp_ops[ulp_type])) {
  469. rcu_assign_pointer(cp->ulp_ops[ulp_type], NULL);
  470. cnic_put(dev);
  471. } else {
  472. pr_err("%s: device not registered to this ulp type %d\n",
  473. __func__, ulp_type);
  474. mutex_unlock(&cnic_lock);
  475. return -EINVAL;
  476. }
  477. mutex_unlock(&cnic_lock);
  478. synchronize_rcu();
  479. while (test_bit(ULP_F_CALL_PENDING, &cp->ulp_flags[ulp_type]) &&
  480. i < 20) {
  481. msleep(100);
  482. i++;
  483. }
  484. if (test_bit(ULP_F_CALL_PENDING, &cp->ulp_flags[ulp_type]))
  485. netdev_warn(dev->netdev, "Failed waiting for ULP up call to complete\n");
  486. return 0;
  487. }
  488. EXPORT_SYMBOL(cnic_unregister_driver);
  489. static int cnic_init_id_tbl(struct cnic_id_tbl *id_tbl, u32 size, u32 start_id)
  490. {
  491. id_tbl->start = start_id;
  492. id_tbl->max = size;
  493. id_tbl->next = 0;
  494. spin_lock_init(&id_tbl->lock);
  495. id_tbl->table = kzalloc(DIV_ROUND_UP(size, 32) * 4, GFP_KERNEL);
  496. if (!id_tbl->table)
  497. return -ENOMEM;
  498. return 0;
  499. }
  500. static void cnic_free_id_tbl(struct cnic_id_tbl *id_tbl)
  501. {
  502. kfree(id_tbl->table);
  503. id_tbl->table = NULL;
  504. }
  505. static int cnic_alloc_id(struct cnic_id_tbl *id_tbl, u32 id)
  506. {
  507. int ret = -1;
  508. id -= id_tbl->start;
  509. if (id >= id_tbl->max)
  510. return ret;
  511. spin_lock(&id_tbl->lock);
  512. if (!test_bit(id, id_tbl->table)) {
  513. set_bit(id, id_tbl->table);
  514. ret = 0;
  515. }
  516. spin_unlock(&id_tbl->lock);
  517. return ret;
  518. }
  519. /* Returns -1 if not successful */
  520. static u32 cnic_alloc_new_id(struct cnic_id_tbl *id_tbl)
  521. {
  522. u32 id;
  523. spin_lock(&id_tbl->lock);
  524. id = find_next_zero_bit(id_tbl->table, id_tbl->max, id_tbl->next);
  525. if (id >= id_tbl->max) {
  526. id = -1;
  527. if (id_tbl->next != 0) {
  528. id = find_first_zero_bit(id_tbl->table, id_tbl->next);
  529. if (id >= id_tbl->next)
  530. id = -1;
  531. }
  532. }
  533. if (id < id_tbl->max) {
  534. set_bit(id, id_tbl->table);
  535. id_tbl->next = (id + 1) & (id_tbl->max - 1);
  536. id += id_tbl->start;
  537. }
  538. spin_unlock(&id_tbl->lock);
  539. return id;
  540. }
  541. static void cnic_free_id(struct cnic_id_tbl *id_tbl, u32 id)
  542. {
  543. if (id == -1)
  544. return;
  545. id -= id_tbl->start;
  546. if (id >= id_tbl->max)
  547. return;
  548. clear_bit(id, id_tbl->table);
  549. }
  550. static void cnic_free_dma(struct cnic_dev *dev, struct cnic_dma *dma)
  551. {
  552. int i;
  553. if (!dma->pg_arr)
  554. return;
  555. for (i = 0; i < dma->num_pages; i++) {
  556. if (dma->pg_arr[i]) {
  557. dma_free_coherent(&dev->pcidev->dev, BCM_PAGE_SIZE,
  558. dma->pg_arr[i], dma->pg_map_arr[i]);
  559. dma->pg_arr[i] = NULL;
  560. }
  561. }
  562. if (dma->pgtbl) {
  563. dma_free_coherent(&dev->pcidev->dev, dma->pgtbl_size,
  564. dma->pgtbl, dma->pgtbl_map);
  565. dma->pgtbl = NULL;
  566. }
  567. kfree(dma->pg_arr);
  568. dma->pg_arr = NULL;
  569. dma->num_pages = 0;
  570. }
  571. static void cnic_setup_page_tbl(struct cnic_dev *dev, struct cnic_dma *dma)
  572. {
  573. int i;
  574. u32 *page_table = dma->pgtbl;
  575. for (i = 0; i < dma->num_pages; i++) {
  576. /* Each entry needs to be in big endian format. */
  577. *page_table = (u32) ((u64) dma->pg_map_arr[i] >> 32);
  578. page_table++;
  579. *page_table = (u32) dma->pg_map_arr[i];
  580. page_table++;
  581. }
  582. }
  583. static void cnic_setup_page_tbl_le(struct cnic_dev *dev, struct cnic_dma *dma)
  584. {
  585. int i;
  586. u32 *page_table = dma->pgtbl;
  587. for (i = 0; i < dma->num_pages; i++) {
  588. /* Each entry needs to be in little endian format. */
  589. *page_table = dma->pg_map_arr[i] & 0xffffffff;
  590. page_table++;
  591. *page_table = (u32) ((u64) dma->pg_map_arr[i] >> 32);
  592. page_table++;
  593. }
  594. }
  595. static int cnic_alloc_dma(struct cnic_dev *dev, struct cnic_dma *dma,
  596. int pages, int use_pg_tbl)
  597. {
  598. int i, size;
  599. struct cnic_local *cp = dev->cnic_priv;
  600. size = pages * (sizeof(void *) + sizeof(dma_addr_t));
  601. dma->pg_arr = kzalloc(size, GFP_ATOMIC);
  602. if (dma->pg_arr == NULL)
  603. return -ENOMEM;
  604. dma->pg_map_arr = (dma_addr_t *) (dma->pg_arr + pages);
  605. dma->num_pages = pages;
  606. for (i = 0; i < pages; i++) {
  607. dma->pg_arr[i] = dma_alloc_coherent(&dev->pcidev->dev,
  608. BCM_PAGE_SIZE,
  609. &dma->pg_map_arr[i],
  610. GFP_ATOMIC);
  611. if (dma->pg_arr[i] == NULL)
  612. goto error;
  613. }
  614. if (!use_pg_tbl)
  615. return 0;
  616. dma->pgtbl_size = ((pages * 8) + BCM_PAGE_SIZE - 1) &
  617. ~(BCM_PAGE_SIZE - 1);
  618. dma->pgtbl = dma_alloc_coherent(&dev->pcidev->dev, dma->pgtbl_size,
  619. &dma->pgtbl_map, GFP_ATOMIC);
  620. if (dma->pgtbl == NULL)
  621. goto error;
  622. cp->setup_pgtbl(dev, dma);
  623. return 0;
  624. error:
  625. cnic_free_dma(dev, dma);
  626. return -ENOMEM;
  627. }
  628. static void cnic_free_context(struct cnic_dev *dev)
  629. {
  630. struct cnic_local *cp = dev->cnic_priv;
  631. int i;
  632. for (i = 0; i < cp->ctx_blks; i++) {
  633. if (cp->ctx_arr[i].ctx) {
  634. dma_free_coherent(&dev->pcidev->dev, cp->ctx_blk_size,
  635. cp->ctx_arr[i].ctx,
  636. cp->ctx_arr[i].mapping);
  637. cp->ctx_arr[i].ctx = NULL;
  638. }
  639. }
  640. }
  641. static void __cnic_free_uio(struct cnic_uio_dev *udev)
  642. {
  643. uio_unregister_device(&udev->cnic_uinfo);
  644. if (udev->l2_buf) {
  645. dma_free_coherent(&udev->pdev->dev, udev->l2_buf_size,
  646. udev->l2_buf, udev->l2_buf_map);
  647. udev->l2_buf = NULL;
  648. }
  649. if (udev->l2_ring) {
  650. dma_free_coherent(&udev->pdev->dev, udev->l2_ring_size,
  651. udev->l2_ring, udev->l2_ring_map);
  652. udev->l2_ring = NULL;
  653. }
  654. pci_dev_put(udev->pdev);
  655. kfree(udev);
  656. }
  657. static void cnic_free_uio(struct cnic_uio_dev *udev)
  658. {
  659. if (!udev)
  660. return;
  661. write_lock(&cnic_dev_lock);
  662. list_del_init(&udev->list);
  663. write_unlock(&cnic_dev_lock);
  664. __cnic_free_uio(udev);
  665. }
  666. static void cnic_free_resc(struct cnic_dev *dev)
  667. {
  668. struct cnic_local *cp = dev->cnic_priv;
  669. struct cnic_uio_dev *udev = cp->udev;
  670. if (udev) {
  671. udev->dev = NULL;
  672. cp->udev = NULL;
  673. }
  674. cnic_free_context(dev);
  675. kfree(cp->ctx_arr);
  676. cp->ctx_arr = NULL;
  677. cp->ctx_blks = 0;
  678. cnic_free_dma(dev, &cp->gbl_buf_info);
  679. cnic_free_dma(dev, &cp->conn_buf_info);
  680. cnic_free_dma(dev, &cp->kwq_info);
  681. cnic_free_dma(dev, &cp->kwq_16_data_info);
  682. cnic_free_dma(dev, &cp->kcq1.dma);
  683. kfree(cp->iscsi_tbl);
  684. cp->iscsi_tbl = NULL;
  685. kfree(cp->ctx_tbl);
  686. cp->ctx_tbl = NULL;
  687. cnic_free_id_tbl(&cp->cid_tbl);
  688. }
  689. static int cnic_alloc_context(struct cnic_dev *dev)
  690. {
  691. struct cnic_local *cp = dev->cnic_priv;
  692. if (CHIP_NUM(cp) == CHIP_NUM_5709) {
  693. int i, k, arr_size;
  694. cp->ctx_blk_size = BCM_PAGE_SIZE;
  695. cp->cids_per_blk = BCM_PAGE_SIZE / 128;
  696. arr_size = BNX2_MAX_CID / cp->cids_per_blk *
  697. sizeof(struct cnic_ctx);
  698. cp->ctx_arr = kzalloc(arr_size, GFP_KERNEL);
  699. if (cp->ctx_arr == NULL)
  700. return -ENOMEM;
  701. k = 0;
  702. for (i = 0; i < 2; i++) {
  703. u32 j, reg, off, lo, hi;
  704. if (i == 0)
  705. off = BNX2_PG_CTX_MAP;
  706. else
  707. off = BNX2_ISCSI_CTX_MAP;
  708. reg = cnic_reg_rd_ind(dev, off);
  709. lo = reg >> 16;
  710. hi = reg & 0xffff;
  711. for (j = lo; j < hi; j += cp->cids_per_blk, k++)
  712. cp->ctx_arr[k].cid = j;
  713. }
  714. cp->ctx_blks = k;
  715. if (cp->ctx_blks >= (BNX2_MAX_CID / cp->cids_per_blk)) {
  716. cp->ctx_blks = 0;
  717. return -ENOMEM;
  718. }
  719. for (i = 0; i < cp->ctx_blks; i++) {
  720. cp->ctx_arr[i].ctx =
  721. dma_alloc_coherent(&dev->pcidev->dev,
  722. BCM_PAGE_SIZE,
  723. &cp->ctx_arr[i].mapping,
  724. GFP_KERNEL);
  725. if (cp->ctx_arr[i].ctx == NULL)
  726. return -ENOMEM;
  727. }
  728. }
  729. return 0;
  730. }
  731. static int cnic_alloc_kcq(struct cnic_dev *dev, struct kcq_info *info)
  732. {
  733. int err, i, is_bnx2 = 0;
  734. struct kcqe **kcq;
  735. if (test_bit(CNIC_F_BNX2_CLASS, &dev->flags))
  736. is_bnx2 = 1;
  737. err = cnic_alloc_dma(dev, &info->dma, KCQ_PAGE_CNT, is_bnx2);
  738. if (err)
  739. return err;
  740. kcq = (struct kcqe **) info->dma.pg_arr;
  741. info->kcq = kcq;
  742. if (is_bnx2)
  743. return 0;
  744. for (i = 0; i < KCQ_PAGE_CNT; i++) {
  745. struct bnx2x_bd_chain_next *next =
  746. (struct bnx2x_bd_chain_next *) &kcq[i][MAX_KCQE_CNT];
  747. int j = i + 1;
  748. if (j >= KCQ_PAGE_CNT)
  749. j = 0;
  750. next->addr_hi = (u64) info->dma.pg_map_arr[j] >> 32;
  751. next->addr_lo = info->dma.pg_map_arr[j] & 0xffffffff;
  752. }
  753. return 0;
  754. }
  755. static int cnic_alloc_uio_rings(struct cnic_dev *dev, int pages)
  756. {
  757. struct cnic_local *cp = dev->cnic_priv;
  758. struct cnic_uio_dev *udev;
  759. read_lock(&cnic_dev_lock);
  760. list_for_each_entry(udev, &cnic_udev_list, list) {
  761. if (udev->pdev == dev->pcidev) {
  762. udev->dev = dev;
  763. cp->udev = udev;
  764. read_unlock(&cnic_dev_lock);
  765. return 0;
  766. }
  767. }
  768. read_unlock(&cnic_dev_lock);
  769. udev = kzalloc(sizeof(struct cnic_uio_dev), GFP_ATOMIC);
  770. if (!udev)
  771. return -ENOMEM;
  772. udev->uio_dev = -1;
  773. udev->dev = dev;
  774. udev->pdev = dev->pcidev;
  775. udev->l2_ring_size = pages * BCM_PAGE_SIZE;
  776. udev->l2_ring = dma_alloc_coherent(&udev->pdev->dev, udev->l2_ring_size,
  777. &udev->l2_ring_map,
  778. GFP_KERNEL | __GFP_COMP);
  779. if (!udev->l2_ring)
  780. return -ENOMEM;
  781. udev->l2_buf_size = (cp->l2_rx_ring_size + 1) * cp->l2_single_buf_size;
  782. udev->l2_buf_size = PAGE_ALIGN(udev->l2_buf_size);
  783. udev->l2_buf = dma_alloc_coherent(&udev->pdev->dev, udev->l2_buf_size,
  784. &udev->l2_buf_map,
  785. GFP_KERNEL | __GFP_COMP);
  786. if (!udev->l2_buf)
  787. return -ENOMEM;
  788. write_lock(&cnic_dev_lock);
  789. list_add(&udev->list, &cnic_udev_list);
  790. write_unlock(&cnic_dev_lock);
  791. pci_dev_get(udev->pdev);
  792. cp->udev = udev;
  793. return 0;
  794. }
  795. static int cnic_init_uio(struct cnic_dev *dev)
  796. {
  797. struct cnic_local *cp = dev->cnic_priv;
  798. struct cnic_uio_dev *udev = cp->udev;
  799. struct uio_info *uinfo;
  800. int ret = 0;
  801. if (!udev)
  802. return -ENOMEM;
  803. uinfo = &udev->cnic_uinfo;
  804. uinfo->mem[0].addr = dev->netdev->base_addr;
  805. uinfo->mem[0].internal_addr = dev->regview;
  806. uinfo->mem[0].size = dev->netdev->mem_end - dev->netdev->mem_start;
  807. uinfo->mem[0].memtype = UIO_MEM_PHYS;
  808. if (test_bit(CNIC_F_BNX2_CLASS, &dev->flags)) {
  809. uinfo->mem[1].addr = (unsigned long) cp->status_blk.gen &
  810. PAGE_MASK;
  811. if (cp->ethdev->drv_state & CNIC_DRV_STATE_USING_MSIX)
  812. uinfo->mem[1].size = BNX2_SBLK_MSIX_ALIGN_SIZE * 9;
  813. else
  814. uinfo->mem[1].size = BNX2_SBLK_MSIX_ALIGN_SIZE;
  815. uinfo->name = "bnx2_cnic";
  816. } else if (test_bit(CNIC_F_BNX2X_CLASS, &dev->flags)) {
  817. uinfo->mem[1].addr = (unsigned long) cp->bnx2x_def_status_blk &
  818. PAGE_MASK;
  819. uinfo->mem[1].size = sizeof(*cp->bnx2x_def_status_blk);
  820. uinfo->name = "bnx2x_cnic";
  821. }
  822. uinfo->mem[1].memtype = UIO_MEM_LOGICAL;
  823. uinfo->mem[2].addr = (unsigned long) udev->l2_ring;
  824. uinfo->mem[2].size = udev->l2_ring_size;
  825. uinfo->mem[2].memtype = UIO_MEM_LOGICAL;
  826. uinfo->mem[3].addr = (unsigned long) udev->l2_buf;
  827. uinfo->mem[3].size = udev->l2_buf_size;
  828. uinfo->mem[3].memtype = UIO_MEM_LOGICAL;
  829. uinfo->version = CNIC_MODULE_VERSION;
  830. uinfo->irq = UIO_IRQ_CUSTOM;
  831. uinfo->open = cnic_uio_open;
  832. uinfo->release = cnic_uio_close;
  833. if (udev->uio_dev == -1) {
  834. if (!uinfo->priv) {
  835. uinfo->priv = udev;
  836. ret = uio_register_device(&udev->pdev->dev, uinfo);
  837. }
  838. } else {
  839. cnic_init_rings(dev);
  840. }
  841. return ret;
  842. }
  843. static int cnic_alloc_bnx2_resc(struct cnic_dev *dev)
  844. {
  845. struct cnic_local *cp = dev->cnic_priv;
  846. int ret;
  847. ret = cnic_alloc_dma(dev, &cp->kwq_info, KWQ_PAGE_CNT, 1);
  848. if (ret)
  849. goto error;
  850. cp->kwq = (struct kwqe **) cp->kwq_info.pg_arr;
  851. ret = cnic_alloc_kcq(dev, &cp->kcq1);
  852. if (ret)
  853. goto error;
  854. ret = cnic_alloc_context(dev);
  855. if (ret)
  856. goto error;
  857. ret = cnic_alloc_uio_rings(dev, 2);
  858. if (ret)
  859. goto error;
  860. ret = cnic_init_uio(dev);
  861. if (ret)
  862. goto error;
  863. return 0;
  864. error:
  865. cnic_free_resc(dev);
  866. return ret;
  867. }
  868. static int cnic_alloc_bnx2x_context(struct cnic_dev *dev)
  869. {
  870. struct cnic_local *cp = dev->cnic_priv;
  871. int ctx_blk_size = cp->ethdev->ctx_blk_size;
  872. int total_mem, blks, i;
  873. total_mem = BNX2X_CONTEXT_MEM_SIZE * cp->max_cid_space;
  874. blks = total_mem / ctx_blk_size;
  875. if (total_mem % ctx_blk_size)
  876. blks++;
  877. if (blks > cp->ethdev->ctx_tbl_len)
  878. return -ENOMEM;
  879. cp->ctx_arr = kcalloc(blks, sizeof(struct cnic_ctx), GFP_KERNEL);
  880. if (cp->ctx_arr == NULL)
  881. return -ENOMEM;
  882. cp->ctx_blks = blks;
  883. cp->ctx_blk_size = ctx_blk_size;
  884. if (!BNX2X_CHIP_IS_57710(cp->chip_id))
  885. cp->ctx_align = 0;
  886. else
  887. cp->ctx_align = ctx_blk_size;
  888. cp->cids_per_blk = ctx_blk_size / BNX2X_CONTEXT_MEM_SIZE;
  889. for (i = 0; i < blks; i++) {
  890. cp->ctx_arr[i].ctx =
  891. dma_alloc_coherent(&dev->pcidev->dev, cp->ctx_blk_size,
  892. &cp->ctx_arr[i].mapping,
  893. GFP_KERNEL);
  894. if (cp->ctx_arr[i].ctx == NULL)
  895. return -ENOMEM;
  896. if (cp->ctx_align && cp->ctx_blk_size == ctx_blk_size) {
  897. if (cp->ctx_arr[i].mapping & (cp->ctx_align - 1)) {
  898. cnic_free_context(dev);
  899. cp->ctx_blk_size += cp->ctx_align;
  900. i = -1;
  901. continue;
  902. }
  903. }
  904. }
  905. return 0;
  906. }
  907. static int cnic_alloc_bnx2x_resc(struct cnic_dev *dev)
  908. {
  909. struct cnic_local *cp = dev->cnic_priv;
  910. struct cnic_eth_dev *ethdev = cp->ethdev;
  911. u32 start_cid = ethdev->starting_cid;
  912. int i, j, n, ret, pages;
  913. struct cnic_dma *kwq_16_dma = &cp->kwq_16_data_info;
  914. cp->iro_arr = ethdev->iro_arr;
  915. cp->max_cid_space = MAX_ISCSI_TBL_SZ;
  916. cp->iscsi_start_cid = start_cid;
  917. if (start_cid < BNX2X_ISCSI_START_CID) {
  918. u32 delta = BNX2X_ISCSI_START_CID - start_cid;
  919. cp->iscsi_start_cid = BNX2X_ISCSI_START_CID;
  920. cp->max_cid_space += delta;
  921. }
  922. cp->iscsi_tbl = kzalloc(sizeof(struct cnic_iscsi) * MAX_ISCSI_TBL_SZ,
  923. GFP_KERNEL);
  924. if (!cp->iscsi_tbl)
  925. goto error;
  926. cp->ctx_tbl = kzalloc(sizeof(struct cnic_context) *
  927. cp->max_cid_space, GFP_KERNEL);
  928. if (!cp->ctx_tbl)
  929. goto error;
  930. for (i = 0; i < MAX_ISCSI_TBL_SZ; i++) {
  931. cp->ctx_tbl[i].proto.iscsi = &cp->iscsi_tbl[i];
  932. cp->ctx_tbl[i].ulp_proto_id = CNIC_ULP_ISCSI;
  933. }
  934. pages = PAGE_ALIGN(cp->max_cid_space * CNIC_KWQ16_DATA_SIZE) /
  935. PAGE_SIZE;
  936. ret = cnic_alloc_dma(dev, kwq_16_dma, pages, 0);
  937. if (ret)
  938. return -ENOMEM;
  939. n = PAGE_SIZE / CNIC_KWQ16_DATA_SIZE;
  940. for (i = 0, j = 0; i < cp->max_cid_space; i++) {
  941. long off = CNIC_KWQ16_DATA_SIZE * (i % n);
  942. cp->ctx_tbl[i].kwqe_data = kwq_16_dma->pg_arr[j] + off;
  943. cp->ctx_tbl[i].kwqe_data_mapping = kwq_16_dma->pg_map_arr[j] +
  944. off;
  945. if ((i % n) == (n - 1))
  946. j++;
  947. }
  948. ret = cnic_alloc_kcq(dev, &cp->kcq1);
  949. if (ret)
  950. goto error;
  951. pages = PAGE_ALIGN(BNX2X_ISCSI_NUM_CONNECTIONS *
  952. BNX2X_ISCSI_CONN_BUF_SIZE) / PAGE_SIZE;
  953. ret = cnic_alloc_dma(dev, &cp->conn_buf_info, pages, 1);
  954. if (ret)
  955. goto error;
  956. pages = PAGE_ALIGN(BNX2X_ISCSI_GLB_BUF_SIZE) / PAGE_SIZE;
  957. ret = cnic_alloc_dma(dev, &cp->gbl_buf_info, pages, 0);
  958. if (ret)
  959. goto error;
  960. ret = cnic_alloc_bnx2x_context(dev);
  961. if (ret)
  962. goto error;
  963. cp->bnx2x_def_status_blk = cp->ethdev->irq_arr[1].status_blk;
  964. cp->l2_rx_ring_size = 15;
  965. ret = cnic_alloc_uio_rings(dev, 4);
  966. if (ret)
  967. goto error;
  968. ret = cnic_init_uio(dev);
  969. if (ret)
  970. goto error;
  971. return 0;
  972. error:
  973. cnic_free_resc(dev);
  974. return -ENOMEM;
  975. }
  976. static inline u32 cnic_kwq_avail(struct cnic_local *cp)
  977. {
  978. return cp->max_kwq_idx -
  979. ((cp->kwq_prod_idx - cp->kwq_con_idx) & cp->max_kwq_idx);
  980. }
  981. static int cnic_submit_bnx2_kwqes(struct cnic_dev *dev, struct kwqe *wqes[],
  982. u32 num_wqes)
  983. {
  984. struct cnic_local *cp = dev->cnic_priv;
  985. struct kwqe *prod_qe;
  986. u16 prod, sw_prod, i;
  987. if (!test_bit(CNIC_F_CNIC_UP, &dev->flags))
  988. return -EAGAIN; /* bnx2 is down */
  989. spin_lock_bh(&cp->cnic_ulp_lock);
  990. if (num_wqes > cnic_kwq_avail(cp) &&
  991. !test_bit(CNIC_LCL_FL_KWQ_INIT, &cp->cnic_local_flags)) {
  992. spin_unlock_bh(&cp->cnic_ulp_lock);
  993. return -EAGAIN;
  994. }
  995. clear_bit(CNIC_LCL_FL_KWQ_INIT, &cp->cnic_local_flags);
  996. prod = cp->kwq_prod_idx;
  997. sw_prod = prod & MAX_KWQ_IDX;
  998. for (i = 0; i < num_wqes; i++) {
  999. prod_qe = &cp->kwq[KWQ_PG(sw_prod)][KWQ_IDX(sw_prod)];
  1000. memcpy(prod_qe, wqes[i], sizeof(struct kwqe));
  1001. prod++;
  1002. sw_prod = prod & MAX_KWQ_IDX;
  1003. }
  1004. cp->kwq_prod_idx = prod;
  1005. CNIC_WR16(dev, cp->kwq_io_addr, cp->kwq_prod_idx);
  1006. spin_unlock_bh(&cp->cnic_ulp_lock);
  1007. return 0;
  1008. }
  1009. static void *cnic_get_kwqe_16_data(struct cnic_local *cp, u32 l5_cid,
  1010. union l5cm_specific_data *l5_data)
  1011. {
  1012. struct cnic_context *ctx = &cp->ctx_tbl[l5_cid];
  1013. dma_addr_t map;
  1014. map = ctx->kwqe_data_mapping;
  1015. l5_data->phy_address.lo = (u64) map & 0xffffffff;
  1016. l5_data->phy_address.hi = (u64) map >> 32;
  1017. return ctx->kwqe_data;
  1018. }
  1019. static int cnic_submit_kwqe_16(struct cnic_dev *dev, u32 cmd, u32 cid,
  1020. u32 type, union l5cm_specific_data *l5_data)
  1021. {
  1022. struct cnic_local *cp = dev->cnic_priv;
  1023. struct l5cm_spe kwqe;
  1024. struct kwqe_16 *kwq[1];
  1025. int ret;
  1026. kwqe.hdr.conn_and_cmd_data =
  1027. cpu_to_le32(((cmd << SPE_HDR_CMD_ID_SHIFT) |
  1028. BNX2X_HW_CID(cp, cid)));
  1029. kwqe.hdr.type = cpu_to_le16(type);
  1030. kwqe.hdr.reserved1 = 0;
  1031. kwqe.data.phy_address.lo = cpu_to_le32(l5_data->phy_address.lo);
  1032. kwqe.data.phy_address.hi = cpu_to_le32(l5_data->phy_address.hi);
  1033. kwq[0] = (struct kwqe_16 *) &kwqe;
  1034. spin_lock_bh(&cp->cnic_ulp_lock);
  1035. ret = cp->ethdev->drv_submit_kwqes_16(dev->netdev, kwq, 1);
  1036. spin_unlock_bh(&cp->cnic_ulp_lock);
  1037. if (ret == 1)
  1038. return 0;
  1039. return -EBUSY;
  1040. }
  1041. static void cnic_reply_bnx2x_kcqes(struct cnic_dev *dev, int ulp_type,
  1042. struct kcqe *cqes[], u32 num_cqes)
  1043. {
  1044. struct cnic_local *cp = dev->cnic_priv;
  1045. struct cnic_ulp_ops *ulp_ops;
  1046. rcu_read_lock();
  1047. ulp_ops = rcu_dereference(cp->ulp_ops[ulp_type]);
  1048. if (likely(ulp_ops)) {
  1049. ulp_ops->indicate_kcqes(cp->ulp_handle[ulp_type],
  1050. cqes, num_cqes);
  1051. }
  1052. rcu_read_unlock();
  1053. }
  1054. static int cnic_bnx2x_iscsi_init1(struct cnic_dev *dev, struct kwqe *kwqe)
  1055. {
  1056. struct cnic_local *cp = dev->cnic_priv;
  1057. struct iscsi_kwqe_init1 *req1 = (struct iscsi_kwqe_init1 *) kwqe;
  1058. int hq_bds, pages;
  1059. u32 pfid = cp->pfid;
  1060. cp->num_iscsi_tasks = req1->num_tasks_per_conn;
  1061. cp->num_ccells = req1->num_ccells_per_conn;
  1062. cp->task_array_size = BNX2X_ISCSI_TASK_CONTEXT_SIZE *
  1063. cp->num_iscsi_tasks;
  1064. cp->r2tq_size = cp->num_iscsi_tasks * BNX2X_ISCSI_MAX_PENDING_R2TS *
  1065. BNX2X_ISCSI_R2TQE_SIZE;
  1066. cp->hq_size = cp->num_ccells * BNX2X_ISCSI_HQ_BD_SIZE;
  1067. pages = PAGE_ALIGN(cp->hq_size) / PAGE_SIZE;
  1068. hq_bds = pages * (PAGE_SIZE / BNX2X_ISCSI_HQ_BD_SIZE);
  1069. cp->num_cqs = req1->num_cqs;
  1070. if (!dev->max_iscsi_conn)
  1071. return 0;
  1072. /* init Tstorm RAM */
  1073. CNIC_WR16(dev, BAR_TSTRORM_INTMEM + TSTORM_ISCSI_RQ_SIZE_OFFSET(pfid),
  1074. req1->rq_num_wqes);
  1075. CNIC_WR16(dev, BAR_TSTRORM_INTMEM + TSTORM_ISCSI_PAGE_SIZE_OFFSET(pfid),
  1076. PAGE_SIZE);
  1077. CNIC_WR8(dev, BAR_TSTRORM_INTMEM +
  1078. TSTORM_ISCSI_PAGE_SIZE_LOG_OFFSET(pfid), PAGE_SHIFT);
  1079. CNIC_WR16(dev, BAR_TSTRORM_INTMEM +
  1080. TSTORM_ISCSI_NUM_OF_TASKS_OFFSET(pfid),
  1081. req1->num_tasks_per_conn);
  1082. /* init Ustorm RAM */
  1083. CNIC_WR16(dev, BAR_USTRORM_INTMEM +
  1084. USTORM_ISCSI_RQ_BUFFER_SIZE_OFFSET(pfid),
  1085. req1->rq_buffer_size);
  1086. CNIC_WR16(dev, BAR_USTRORM_INTMEM + USTORM_ISCSI_PAGE_SIZE_OFFSET(pfid),
  1087. PAGE_SIZE);
  1088. CNIC_WR8(dev, BAR_USTRORM_INTMEM +
  1089. USTORM_ISCSI_PAGE_SIZE_LOG_OFFSET(pfid), PAGE_SHIFT);
  1090. CNIC_WR16(dev, BAR_USTRORM_INTMEM +
  1091. USTORM_ISCSI_NUM_OF_TASKS_OFFSET(pfid),
  1092. req1->num_tasks_per_conn);
  1093. CNIC_WR16(dev, BAR_USTRORM_INTMEM + USTORM_ISCSI_RQ_SIZE_OFFSET(pfid),
  1094. req1->rq_num_wqes);
  1095. CNIC_WR16(dev, BAR_USTRORM_INTMEM + USTORM_ISCSI_CQ_SIZE_OFFSET(pfid),
  1096. req1->cq_num_wqes);
  1097. CNIC_WR16(dev, BAR_USTRORM_INTMEM + USTORM_ISCSI_R2TQ_SIZE_OFFSET(pfid),
  1098. cp->num_iscsi_tasks * BNX2X_ISCSI_MAX_PENDING_R2TS);
  1099. /* init Xstorm RAM */
  1100. CNIC_WR16(dev, BAR_XSTRORM_INTMEM + XSTORM_ISCSI_PAGE_SIZE_OFFSET(pfid),
  1101. PAGE_SIZE);
  1102. CNIC_WR8(dev, BAR_XSTRORM_INTMEM +
  1103. XSTORM_ISCSI_PAGE_SIZE_LOG_OFFSET(pfid), PAGE_SHIFT);
  1104. CNIC_WR16(dev, BAR_XSTRORM_INTMEM +
  1105. XSTORM_ISCSI_NUM_OF_TASKS_OFFSET(pfid),
  1106. req1->num_tasks_per_conn);
  1107. CNIC_WR16(dev, BAR_XSTRORM_INTMEM + XSTORM_ISCSI_HQ_SIZE_OFFSET(pfid),
  1108. hq_bds);
  1109. CNIC_WR16(dev, BAR_XSTRORM_INTMEM + XSTORM_ISCSI_SQ_SIZE_OFFSET(pfid),
  1110. req1->num_tasks_per_conn);
  1111. CNIC_WR16(dev, BAR_XSTRORM_INTMEM + XSTORM_ISCSI_R2TQ_SIZE_OFFSET(pfid),
  1112. cp->num_iscsi_tasks * BNX2X_ISCSI_MAX_PENDING_R2TS);
  1113. /* init Cstorm RAM */
  1114. CNIC_WR16(dev, BAR_CSTRORM_INTMEM + CSTORM_ISCSI_PAGE_SIZE_OFFSET(pfid),
  1115. PAGE_SIZE);
  1116. CNIC_WR8(dev, BAR_CSTRORM_INTMEM +
  1117. CSTORM_ISCSI_PAGE_SIZE_LOG_OFFSET(pfid), PAGE_SHIFT);
  1118. CNIC_WR16(dev, BAR_CSTRORM_INTMEM +
  1119. CSTORM_ISCSI_NUM_OF_TASKS_OFFSET(pfid),
  1120. req1->num_tasks_per_conn);
  1121. CNIC_WR16(dev, BAR_CSTRORM_INTMEM + CSTORM_ISCSI_CQ_SIZE_OFFSET(pfid),
  1122. req1->cq_num_wqes);
  1123. CNIC_WR16(dev, BAR_CSTRORM_INTMEM + CSTORM_ISCSI_HQ_SIZE_OFFSET(pfid),
  1124. hq_bds);
  1125. return 0;
  1126. }
  1127. static int cnic_bnx2x_iscsi_init2(struct cnic_dev *dev, struct kwqe *kwqe)
  1128. {
  1129. struct iscsi_kwqe_init2 *req2 = (struct iscsi_kwqe_init2 *) kwqe;
  1130. struct cnic_local *cp = dev->cnic_priv;
  1131. u32 pfid = cp->pfid;
  1132. struct iscsi_kcqe kcqe;
  1133. struct kcqe *cqes[1];
  1134. memset(&kcqe, 0, sizeof(kcqe));
  1135. if (!dev->max_iscsi_conn) {
  1136. kcqe.completion_status =
  1137. ISCSI_KCQE_COMPLETION_STATUS_ISCSI_NOT_SUPPORTED;
  1138. goto done;
  1139. }
  1140. CNIC_WR(dev, BAR_TSTRORM_INTMEM +
  1141. TSTORM_ISCSI_ERROR_BITMAP_OFFSET(pfid), req2->error_bit_map[0]);
  1142. CNIC_WR(dev, BAR_TSTRORM_INTMEM +
  1143. TSTORM_ISCSI_ERROR_BITMAP_OFFSET(pfid) + 4,
  1144. req2->error_bit_map[1]);
  1145. CNIC_WR16(dev, BAR_USTRORM_INTMEM +
  1146. USTORM_ISCSI_CQ_SQN_SIZE_OFFSET(pfid), req2->max_cq_sqn);
  1147. CNIC_WR(dev, BAR_USTRORM_INTMEM +
  1148. USTORM_ISCSI_ERROR_BITMAP_OFFSET(pfid), req2->error_bit_map[0]);
  1149. CNIC_WR(dev, BAR_USTRORM_INTMEM +
  1150. USTORM_ISCSI_ERROR_BITMAP_OFFSET(pfid) + 4,
  1151. req2->error_bit_map[1]);
  1152. CNIC_WR16(dev, BAR_CSTRORM_INTMEM +
  1153. CSTORM_ISCSI_CQ_SQN_SIZE_OFFSET(pfid), req2->max_cq_sqn);
  1154. kcqe.completion_status = ISCSI_KCQE_COMPLETION_STATUS_SUCCESS;
  1155. done:
  1156. kcqe.op_code = ISCSI_KCQE_OPCODE_INIT;
  1157. cqes[0] = (struct kcqe *) &kcqe;
  1158. cnic_reply_bnx2x_kcqes(dev, CNIC_ULP_ISCSI, cqes, 1);
  1159. return 0;
  1160. }
  1161. static void cnic_free_bnx2x_conn_resc(struct cnic_dev *dev, u32 l5_cid)
  1162. {
  1163. struct cnic_local *cp = dev->cnic_priv;
  1164. struct cnic_context *ctx = &cp->ctx_tbl[l5_cid];
  1165. if (ctx->ulp_proto_id == CNIC_ULP_ISCSI) {
  1166. struct cnic_iscsi *iscsi = ctx->proto.iscsi;
  1167. cnic_free_dma(dev, &iscsi->hq_info);
  1168. cnic_free_dma(dev, &iscsi->r2tq_info);
  1169. cnic_free_dma(dev, &iscsi->task_array_info);
  1170. }
  1171. cnic_free_id(&cp->cid_tbl, ctx->cid);
  1172. ctx->cid = 0;
  1173. }
  1174. static int cnic_alloc_bnx2x_conn_resc(struct cnic_dev *dev, u32 l5_cid)
  1175. {
  1176. u32 cid;
  1177. int ret, pages;
  1178. struct cnic_local *cp = dev->cnic_priv;
  1179. struct cnic_context *ctx = &cp->ctx_tbl[l5_cid];
  1180. struct cnic_iscsi *iscsi = ctx->proto.iscsi;
  1181. cid = cnic_alloc_new_id(&cp->cid_tbl);
  1182. if (cid == -1) {
  1183. ret = -ENOMEM;
  1184. goto error;
  1185. }
  1186. ctx->cid = cid;
  1187. pages = PAGE_ALIGN(cp->task_array_size) / PAGE_SIZE;
  1188. ret = cnic_alloc_dma(dev, &iscsi->task_array_info, pages, 1);
  1189. if (ret)
  1190. goto error;
  1191. pages = PAGE_ALIGN(cp->r2tq_size) / PAGE_SIZE;
  1192. ret = cnic_alloc_dma(dev, &iscsi->r2tq_info, pages, 1);
  1193. if (ret)
  1194. goto error;
  1195. pages = PAGE_ALIGN(cp->hq_size) / PAGE_SIZE;
  1196. ret = cnic_alloc_dma(dev, &iscsi->hq_info, pages, 1);
  1197. if (ret)
  1198. goto error;
  1199. return 0;
  1200. error:
  1201. cnic_free_bnx2x_conn_resc(dev, l5_cid);
  1202. return ret;
  1203. }
  1204. static void *cnic_get_bnx2x_ctx(struct cnic_dev *dev, u32 cid, int init,
  1205. struct regpair *ctx_addr)
  1206. {
  1207. struct cnic_local *cp = dev->cnic_priv;
  1208. struct cnic_eth_dev *ethdev = cp->ethdev;
  1209. int blk = (cid - ethdev->starting_cid) / cp->cids_per_blk;
  1210. int off = (cid - ethdev->starting_cid) % cp->cids_per_blk;
  1211. unsigned long align_off = 0;
  1212. dma_addr_t ctx_map;
  1213. void *ctx;
  1214. if (cp->ctx_align) {
  1215. unsigned long mask = cp->ctx_align - 1;
  1216. if (cp->ctx_arr[blk].mapping & mask)
  1217. align_off = cp->ctx_align -
  1218. (cp->ctx_arr[blk].mapping & mask);
  1219. }
  1220. ctx_map = cp->ctx_arr[blk].mapping + align_off +
  1221. (off * BNX2X_CONTEXT_MEM_SIZE);
  1222. ctx = cp->ctx_arr[blk].ctx + align_off +
  1223. (off * BNX2X_CONTEXT_MEM_SIZE);
  1224. if (init)
  1225. memset(ctx, 0, BNX2X_CONTEXT_MEM_SIZE);
  1226. ctx_addr->lo = ctx_map & 0xffffffff;
  1227. ctx_addr->hi = (u64) ctx_map >> 32;
  1228. return ctx;
  1229. }
  1230. static int cnic_setup_bnx2x_ctx(struct cnic_dev *dev, struct kwqe *wqes[],
  1231. u32 num)
  1232. {
  1233. struct cnic_local *cp = dev->cnic_priv;
  1234. struct iscsi_kwqe_conn_offload1 *req1 =
  1235. (struct iscsi_kwqe_conn_offload1 *) wqes[0];
  1236. struct iscsi_kwqe_conn_offload2 *req2 =
  1237. (struct iscsi_kwqe_conn_offload2 *) wqes[1];
  1238. struct iscsi_kwqe_conn_offload3 *req3;
  1239. struct cnic_context *ctx = &cp->ctx_tbl[req1->iscsi_conn_id];
  1240. struct cnic_iscsi *iscsi = ctx->proto.iscsi;
  1241. u32 cid = ctx->cid;
  1242. u32 hw_cid = BNX2X_HW_CID(cp, cid);
  1243. struct iscsi_context *ictx;
  1244. struct regpair context_addr;
  1245. int i, j, n = 2, n_max;
  1246. ctx->ctx_flags = 0;
  1247. if (!req2->num_additional_wqes)
  1248. return -EINVAL;
  1249. n_max = req2->num_additional_wqes + 2;
  1250. ictx = cnic_get_bnx2x_ctx(dev, cid, 1, &context_addr);
  1251. if (ictx == NULL)
  1252. return -ENOMEM;
  1253. req3 = (struct iscsi_kwqe_conn_offload3 *) wqes[n++];
  1254. ictx->xstorm_ag_context.hq_prod = 1;
  1255. ictx->xstorm_st_context.iscsi.first_burst_length =
  1256. ISCSI_DEF_FIRST_BURST_LEN;
  1257. ictx->xstorm_st_context.iscsi.max_send_pdu_length =
  1258. ISCSI_DEF_MAX_RECV_SEG_LEN;
  1259. ictx->xstorm_st_context.iscsi.sq_pbl_base.lo =
  1260. req1->sq_page_table_addr_lo;
  1261. ictx->xstorm_st_context.iscsi.sq_pbl_base.hi =
  1262. req1->sq_page_table_addr_hi;
  1263. ictx->xstorm_st_context.iscsi.sq_curr_pbe.lo = req2->sq_first_pte.hi;
  1264. ictx->xstorm_st_context.iscsi.sq_curr_pbe.hi = req2->sq_first_pte.lo;
  1265. ictx->xstorm_st_context.iscsi.hq_pbl_base.lo =
  1266. iscsi->hq_info.pgtbl_map & 0xffffffff;
  1267. ictx->xstorm_st_context.iscsi.hq_pbl_base.hi =
  1268. (u64) iscsi->hq_info.pgtbl_map >> 32;
  1269. ictx->xstorm_st_context.iscsi.hq_curr_pbe_base.lo =
  1270. iscsi->hq_info.pgtbl[0];
  1271. ictx->xstorm_st_context.iscsi.hq_curr_pbe_base.hi =
  1272. iscsi->hq_info.pgtbl[1];
  1273. ictx->xstorm_st_context.iscsi.r2tq_pbl_base.lo =
  1274. iscsi->r2tq_info.pgtbl_map & 0xffffffff;
  1275. ictx->xstorm_st_context.iscsi.r2tq_pbl_base.hi =
  1276. (u64) iscsi->r2tq_info.pgtbl_map >> 32;
  1277. ictx->xstorm_st_context.iscsi.r2tq_curr_pbe_base.lo =
  1278. iscsi->r2tq_info.pgtbl[0];
  1279. ictx->xstorm_st_context.iscsi.r2tq_curr_pbe_base.hi =
  1280. iscsi->r2tq_info.pgtbl[1];
  1281. ictx->xstorm_st_context.iscsi.task_pbl_base.lo =
  1282. iscsi->task_array_info.pgtbl_map & 0xffffffff;
  1283. ictx->xstorm_st_context.iscsi.task_pbl_base.hi =
  1284. (u64) iscsi->task_array_info.pgtbl_map >> 32;
  1285. ictx->xstorm_st_context.iscsi.task_pbl_cache_idx =
  1286. BNX2X_ISCSI_PBL_NOT_CACHED;
  1287. ictx->xstorm_st_context.iscsi.flags.flags |=
  1288. XSTORM_ISCSI_CONTEXT_FLAGS_B_IMMEDIATE_DATA;
  1289. ictx->xstorm_st_context.iscsi.flags.flags |=
  1290. XSTORM_ISCSI_CONTEXT_FLAGS_B_INITIAL_R2T;
  1291. ictx->tstorm_st_context.iscsi.hdr_bytes_2_fetch = ISCSI_HEADER_SIZE;
  1292. /* TSTORM requires the base address of RQ DB & not PTE */
  1293. ictx->tstorm_st_context.iscsi.rq_db_phy_addr.lo =
  1294. req2->rq_page_table_addr_lo & PAGE_MASK;
  1295. ictx->tstorm_st_context.iscsi.rq_db_phy_addr.hi =
  1296. req2->rq_page_table_addr_hi;
  1297. ictx->tstorm_st_context.iscsi.iscsi_conn_id = req1->iscsi_conn_id;
  1298. ictx->tstorm_st_context.tcp.cwnd = 0x5A8;
  1299. ictx->tstorm_st_context.tcp.flags2 |=
  1300. TSTORM_TCP_ST_CONTEXT_SECTION_DA_EN;
  1301. ictx->tstorm_st_context.tcp.ooo_support_mode =
  1302. TCP_TSTORM_OOO_DROP_AND_PROC_ACK;
  1303. ictx->timers_context.flags |= TIMERS_BLOCK_CONTEXT_CONN_VALID_FLG;
  1304. ictx->ustorm_st_context.ring.rq.pbl_base.lo =
  1305. req2->rq_page_table_addr_lo;
  1306. ictx->ustorm_st_context.ring.rq.pbl_base.hi =
  1307. req2->rq_page_table_addr_hi;
  1308. ictx->ustorm_st_context.ring.rq.curr_pbe.lo = req3->qp_first_pte[0].hi;
  1309. ictx->ustorm_st_context.ring.rq.curr_pbe.hi = req3->qp_first_pte[0].lo;
  1310. ictx->ustorm_st_context.ring.r2tq.pbl_base.lo =
  1311. iscsi->r2tq_info.pgtbl_map & 0xffffffff;
  1312. ictx->ustorm_st_context.ring.r2tq.pbl_base.hi =
  1313. (u64) iscsi->r2tq_info.pgtbl_map >> 32;
  1314. ictx->ustorm_st_context.ring.r2tq.curr_pbe.lo =
  1315. iscsi->r2tq_info.pgtbl[0];
  1316. ictx->ustorm_st_context.ring.r2tq.curr_pbe.hi =
  1317. iscsi->r2tq_info.pgtbl[1];
  1318. ictx->ustorm_st_context.ring.cq_pbl_base.lo =
  1319. req1->cq_page_table_addr_lo;
  1320. ictx->ustorm_st_context.ring.cq_pbl_base.hi =
  1321. req1->cq_page_table_addr_hi;
  1322. ictx->ustorm_st_context.ring.cq[0].cq_sn = ISCSI_INITIAL_SN;
  1323. ictx->ustorm_st_context.ring.cq[0].curr_pbe.lo = req2->cq_first_pte.hi;
  1324. ictx->ustorm_st_context.ring.cq[0].curr_pbe.hi = req2->cq_first_pte.lo;
  1325. ictx->ustorm_st_context.task_pbe_cache_index =
  1326. BNX2X_ISCSI_PBL_NOT_CACHED;
  1327. ictx->ustorm_st_context.task_pdu_cache_index =
  1328. BNX2X_ISCSI_PDU_HEADER_NOT_CACHED;
  1329. for (i = 1, j = 1; i < cp->num_cqs; i++, j++) {
  1330. if (j == 3) {
  1331. if (n >= n_max)
  1332. break;
  1333. req3 = (struct iscsi_kwqe_conn_offload3 *) wqes[n++];
  1334. j = 0;
  1335. }
  1336. ictx->ustorm_st_context.ring.cq[i].cq_sn = ISCSI_INITIAL_SN;
  1337. ictx->ustorm_st_context.ring.cq[i].curr_pbe.lo =
  1338. req3->qp_first_pte[j].hi;
  1339. ictx->ustorm_st_context.ring.cq[i].curr_pbe.hi =
  1340. req3->qp_first_pte[j].lo;
  1341. }
  1342. ictx->ustorm_st_context.task_pbl_base.lo =
  1343. iscsi->task_array_info.pgtbl_map & 0xffffffff;
  1344. ictx->ustorm_st_context.task_pbl_base.hi =
  1345. (u64) iscsi->task_array_info.pgtbl_map >> 32;
  1346. ictx->ustorm_st_context.tce_phy_addr.lo =
  1347. iscsi->task_array_info.pgtbl[0];
  1348. ictx->ustorm_st_context.tce_phy_addr.hi =
  1349. iscsi->task_array_info.pgtbl[1];
  1350. ictx->ustorm_st_context.iscsi_conn_id = req1->iscsi_conn_id;
  1351. ictx->ustorm_st_context.num_cqs = cp->num_cqs;
  1352. ictx->ustorm_st_context.negotiated_rx |= ISCSI_DEF_MAX_RECV_SEG_LEN;
  1353. ictx->ustorm_st_context.negotiated_rx_and_flags |=
  1354. ISCSI_DEF_MAX_BURST_LEN;
  1355. ictx->ustorm_st_context.negotiated_rx |=
  1356. ISCSI_DEFAULT_MAX_OUTSTANDING_R2T <<
  1357. USTORM_ISCSI_ST_CONTEXT_MAX_OUTSTANDING_R2TS_SHIFT;
  1358. ictx->cstorm_st_context.hq_pbl_base.lo =
  1359. iscsi->hq_info.pgtbl_map & 0xffffffff;
  1360. ictx->cstorm_st_context.hq_pbl_base.hi =
  1361. (u64) iscsi->hq_info.pgtbl_map >> 32;
  1362. ictx->cstorm_st_context.hq_curr_pbe.lo = iscsi->hq_info.pgtbl[0];
  1363. ictx->cstorm_st_context.hq_curr_pbe.hi = iscsi->hq_info.pgtbl[1];
  1364. ictx->cstorm_st_context.task_pbl_base.lo =
  1365. iscsi->task_array_info.pgtbl_map & 0xffffffff;
  1366. ictx->cstorm_st_context.task_pbl_base.hi =
  1367. (u64) iscsi->task_array_info.pgtbl_map >> 32;
  1368. /* CSTORM and USTORM initialization is different, CSTORM requires
  1369. * CQ DB base & not PTE addr */
  1370. ictx->cstorm_st_context.cq_db_base.lo =
  1371. req1->cq_page_table_addr_lo & PAGE_MASK;
  1372. ictx->cstorm_st_context.cq_db_base.hi = req1->cq_page_table_addr_hi;
  1373. ictx->cstorm_st_context.iscsi_conn_id = req1->iscsi_conn_id;
  1374. ictx->cstorm_st_context.cq_proc_en_bit_map = (1 << cp->num_cqs) - 1;
  1375. for (i = 0; i < cp->num_cqs; i++) {
  1376. ictx->cstorm_st_context.cq_c_prod_sqn_arr.sqn[i] =
  1377. ISCSI_INITIAL_SN;
  1378. ictx->cstorm_st_context.cq_c_sqn_2_notify_arr.sqn[i] =
  1379. ISCSI_INITIAL_SN;
  1380. }
  1381. ictx->xstorm_ag_context.cdu_reserved =
  1382. CDU_RSRVD_VALUE_TYPE_A(hw_cid, CDU_REGION_NUMBER_XCM_AG,
  1383. ISCSI_CONNECTION_TYPE);
  1384. ictx->ustorm_ag_context.cdu_usage =
  1385. CDU_RSRVD_VALUE_TYPE_A(hw_cid, CDU_REGION_NUMBER_UCM_AG,
  1386. ISCSI_CONNECTION_TYPE);
  1387. return 0;
  1388. }
  1389. static int cnic_bnx2x_iscsi_ofld1(struct cnic_dev *dev, struct kwqe *wqes[],
  1390. u32 num, int *work)
  1391. {
  1392. struct iscsi_kwqe_conn_offload1 *req1;
  1393. struct iscsi_kwqe_conn_offload2 *req2;
  1394. struct cnic_local *cp = dev->cnic_priv;
  1395. struct cnic_context *ctx;
  1396. struct iscsi_kcqe kcqe;
  1397. struct kcqe *cqes[1];
  1398. u32 l5_cid;
  1399. int ret = 0;
  1400. if (num < 2) {
  1401. *work = num;
  1402. return -EINVAL;
  1403. }
  1404. req1 = (struct iscsi_kwqe_conn_offload1 *) wqes[0];
  1405. req2 = (struct iscsi_kwqe_conn_offload2 *) wqes[1];
  1406. if ((num - 2) < req2->num_additional_wqes) {
  1407. *work = num;
  1408. return -EINVAL;
  1409. }
  1410. *work = 2 + req2->num_additional_wqes;;
  1411. l5_cid = req1->iscsi_conn_id;
  1412. if (l5_cid >= MAX_ISCSI_TBL_SZ)
  1413. return -EINVAL;
  1414. memset(&kcqe, 0, sizeof(kcqe));
  1415. kcqe.op_code = ISCSI_KCQE_OPCODE_OFFLOAD_CONN;
  1416. kcqe.iscsi_conn_id = l5_cid;
  1417. kcqe.completion_status = ISCSI_KCQE_COMPLETION_STATUS_CTX_ALLOC_FAILURE;
  1418. ctx = &cp->ctx_tbl[l5_cid];
  1419. if (test_bit(CTX_FL_OFFLD_START, &ctx->ctx_flags)) {
  1420. kcqe.completion_status =
  1421. ISCSI_KCQE_COMPLETION_STATUS_CID_BUSY;
  1422. goto done;
  1423. }
  1424. if (atomic_inc_return(&cp->iscsi_conn) > dev->max_iscsi_conn) {
  1425. atomic_dec(&cp->iscsi_conn);
  1426. goto done;
  1427. }
  1428. ret = cnic_alloc_bnx2x_conn_resc(dev, l5_cid);
  1429. if (ret) {
  1430. atomic_dec(&cp->iscsi_conn);
  1431. ret = 0;
  1432. goto done;
  1433. }
  1434. ret = cnic_setup_bnx2x_ctx(dev, wqes, num);
  1435. if (ret < 0) {
  1436. cnic_free_bnx2x_conn_resc(dev, l5_cid);
  1437. atomic_dec(&cp->iscsi_conn);
  1438. goto done;
  1439. }
  1440. kcqe.completion_status = ISCSI_KCQE_COMPLETION_STATUS_SUCCESS;
  1441. kcqe.iscsi_conn_context_id = BNX2X_HW_CID(cp, cp->ctx_tbl[l5_cid].cid);
  1442. done:
  1443. cqes[0] = (struct kcqe *) &kcqe;
  1444. cnic_reply_bnx2x_kcqes(dev, CNIC_ULP_ISCSI, cqes, 1);
  1445. return ret;
  1446. }
  1447. static int cnic_bnx2x_iscsi_update(struct cnic_dev *dev, struct kwqe *kwqe)
  1448. {
  1449. struct cnic_local *cp = dev->cnic_priv;
  1450. struct iscsi_kwqe_conn_update *req =
  1451. (struct iscsi_kwqe_conn_update *) kwqe;
  1452. void *data;
  1453. union l5cm_specific_data l5_data;
  1454. u32 l5_cid, cid = BNX2X_SW_CID(req->context_id);
  1455. int ret;
  1456. if (cnic_get_l5_cid(cp, cid, &l5_cid) != 0)
  1457. return -EINVAL;
  1458. data = cnic_get_kwqe_16_data(cp, l5_cid, &l5_data);
  1459. if (!data)
  1460. return -ENOMEM;
  1461. memcpy(data, kwqe, sizeof(struct kwqe));
  1462. ret = cnic_submit_kwqe_16(dev, ISCSI_RAMROD_CMD_ID_UPDATE_CONN,
  1463. req->context_id, ISCSI_CONNECTION_TYPE, &l5_data);
  1464. return ret;
  1465. }
  1466. static int cnic_bnx2x_destroy_ramrod(struct cnic_dev *dev, u32 l5_cid)
  1467. {
  1468. struct cnic_local *cp = dev->cnic_priv;
  1469. struct cnic_context *ctx = &cp->ctx_tbl[l5_cid];
  1470. union l5cm_specific_data l5_data;
  1471. int ret;
  1472. u32 hw_cid, type;
  1473. init_waitqueue_head(&ctx->waitq);
  1474. ctx->wait_cond = 0;
  1475. memset(&l5_data, 0, sizeof(l5_data));
  1476. hw_cid = BNX2X_HW_CID(cp, ctx->cid);
  1477. type = (NONE_CONNECTION_TYPE << SPE_HDR_CONN_TYPE_SHIFT)
  1478. & SPE_HDR_CONN_TYPE;
  1479. type |= ((cp->pfid << SPE_HDR_FUNCTION_ID_SHIFT) &
  1480. SPE_HDR_FUNCTION_ID);
  1481. ret = cnic_submit_kwqe_16(dev, RAMROD_CMD_ID_COMMON_CFC_DEL,
  1482. hw_cid, type, &l5_data);
  1483. if (ret == 0)
  1484. wait_event(ctx->waitq, ctx->wait_cond);
  1485. return ret;
  1486. }
  1487. static int cnic_bnx2x_iscsi_destroy(struct cnic_dev *dev, struct kwqe *kwqe)
  1488. {
  1489. struct cnic_local *cp = dev->cnic_priv;
  1490. struct iscsi_kwqe_conn_destroy *req =
  1491. (struct iscsi_kwqe_conn_destroy *) kwqe;
  1492. u32 l5_cid = req->reserved0;
  1493. struct cnic_context *ctx = &cp->ctx_tbl[l5_cid];
  1494. int ret = 0;
  1495. struct iscsi_kcqe kcqe;
  1496. struct kcqe *cqes[1];
  1497. if (!test_bit(CTX_FL_OFFLD_START, &ctx->ctx_flags))
  1498. goto skip_cfc_delete;
  1499. if (!time_after(jiffies, ctx->timestamp + (2 * HZ))) {
  1500. unsigned long delta = ctx->timestamp + (2 * HZ) - jiffies;
  1501. if (delta > (2 * HZ))
  1502. delta = 0;
  1503. set_bit(CTX_FL_DELETE_WAIT, &ctx->ctx_flags);
  1504. queue_delayed_work(cnic_wq, &cp->delete_task, delta);
  1505. goto destroy_reply;
  1506. }
  1507. ret = cnic_bnx2x_destroy_ramrod(dev, l5_cid);
  1508. skip_cfc_delete:
  1509. cnic_free_bnx2x_conn_resc(dev, l5_cid);
  1510. atomic_dec(&cp->iscsi_conn);
  1511. clear_bit(CTX_FL_OFFLD_START, &ctx->ctx_flags);
  1512. destroy_reply:
  1513. memset(&kcqe, 0, sizeof(kcqe));
  1514. kcqe.op_code = ISCSI_KCQE_OPCODE_DESTROY_CONN;
  1515. kcqe.iscsi_conn_id = l5_cid;
  1516. kcqe.completion_status = ISCSI_KCQE_COMPLETION_STATUS_SUCCESS;
  1517. kcqe.iscsi_conn_context_id = req->context_id;
  1518. cqes[0] = (struct kcqe *) &kcqe;
  1519. cnic_reply_bnx2x_kcqes(dev, CNIC_ULP_ISCSI, cqes, 1);
  1520. return ret;
  1521. }
  1522. static void cnic_init_storm_conn_bufs(struct cnic_dev *dev,
  1523. struct l4_kwq_connect_req1 *kwqe1,
  1524. struct l4_kwq_connect_req3 *kwqe3,
  1525. struct l5cm_active_conn_buffer *conn_buf)
  1526. {
  1527. struct l5cm_conn_addr_params *conn_addr = &conn_buf->conn_addr_buf;
  1528. struct l5cm_xstorm_conn_buffer *xstorm_buf =
  1529. &conn_buf->xstorm_conn_buffer;
  1530. struct l5cm_tstorm_conn_buffer *tstorm_buf =
  1531. &conn_buf->tstorm_conn_buffer;
  1532. struct regpair context_addr;
  1533. u32 cid = BNX2X_SW_CID(kwqe1->cid);
  1534. struct in6_addr src_ip, dst_ip;
  1535. int i;
  1536. u32 *addrp;
  1537. addrp = (u32 *) &conn_addr->local_ip_addr;
  1538. for (i = 0; i < 4; i++, addrp++)
  1539. src_ip.in6_u.u6_addr32[i] = cpu_to_be32(*addrp);
  1540. addrp = (u32 *) &conn_addr->remote_ip_addr;
  1541. for (i = 0; i < 4; i++, addrp++)
  1542. dst_ip.in6_u.u6_addr32[i] = cpu_to_be32(*addrp);
  1543. cnic_get_bnx2x_ctx(dev, cid, 0, &context_addr);
  1544. xstorm_buf->context_addr.hi = context_addr.hi;
  1545. xstorm_buf->context_addr.lo = context_addr.lo;
  1546. xstorm_buf->mss = 0xffff;
  1547. xstorm_buf->rcv_buf = kwqe3->rcv_buf;
  1548. if (kwqe1->tcp_flags & L4_KWQ_CONNECT_REQ1_NAGLE_ENABLE)
  1549. xstorm_buf->params |= L5CM_XSTORM_CONN_BUFFER_NAGLE_ENABLE;
  1550. xstorm_buf->pseudo_header_checksum =
  1551. swab16(~csum_ipv6_magic(&src_ip, &dst_ip, 0, IPPROTO_TCP, 0));
  1552. if (!(kwqe1->tcp_flags & L4_KWQ_CONNECT_REQ1_NO_DELAY_ACK))
  1553. tstorm_buf->params |=
  1554. L5CM_TSTORM_CONN_BUFFER_DELAYED_ACK_ENABLE;
  1555. if (kwqe3->ka_timeout) {
  1556. tstorm_buf->ka_enable = 1;
  1557. tstorm_buf->ka_timeout = kwqe3->ka_timeout;
  1558. tstorm_buf->ka_interval = kwqe3->ka_interval;
  1559. tstorm_buf->ka_max_probe_count = kwqe3->ka_max_probe_count;
  1560. }
  1561. tstorm_buf->rcv_buf = kwqe3->rcv_buf;
  1562. tstorm_buf->snd_buf = kwqe3->snd_buf;
  1563. tstorm_buf->max_rt_time = 0xffffffff;
  1564. }
  1565. static void cnic_init_bnx2x_mac(struct cnic_dev *dev)
  1566. {
  1567. struct cnic_local *cp = dev->cnic_priv;
  1568. u32 pfid = cp->pfid;
  1569. u8 *mac = dev->mac_addr;
  1570. CNIC_WR8(dev, BAR_XSTRORM_INTMEM +
  1571. XSTORM_ISCSI_LOCAL_MAC_ADDR0_OFFSET(pfid), mac[0]);
  1572. CNIC_WR8(dev, BAR_XSTRORM_INTMEM +
  1573. XSTORM_ISCSI_LOCAL_MAC_ADDR1_OFFSET(pfid), mac[1]);
  1574. CNIC_WR8(dev, BAR_XSTRORM_INTMEM +
  1575. XSTORM_ISCSI_LOCAL_MAC_ADDR2_OFFSET(pfid), mac[2]);
  1576. CNIC_WR8(dev, BAR_XSTRORM_INTMEM +
  1577. XSTORM_ISCSI_LOCAL_MAC_ADDR3_OFFSET(pfid), mac[3]);
  1578. CNIC_WR8(dev, BAR_XSTRORM_INTMEM +
  1579. XSTORM_ISCSI_LOCAL_MAC_ADDR4_OFFSET(pfid), mac[4]);
  1580. CNIC_WR8(dev, BAR_XSTRORM_INTMEM +
  1581. XSTORM_ISCSI_LOCAL_MAC_ADDR5_OFFSET(pfid), mac[5]);
  1582. CNIC_WR8(dev, BAR_TSTRORM_INTMEM +
  1583. TSTORM_ISCSI_TCP_VARS_LSB_LOCAL_MAC_ADDR_OFFSET(pfid), mac[5]);
  1584. CNIC_WR8(dev, BAR_TSTRORM_INTMEM +
  1585. TSTORM_ISCSI_TCP_VARS_LSB_LOCAL_MAC_ADDR_OFFSET(pfid) + 1,
  1586. mac[4]);
  1587. CNIC_WR8(dev, BAR_TSTRORM_INTMEM +
  1588. TSTORM_ISCSI_TCP_VARS_MSB_LOCAL_MAC_ADDR_OFFSET(pfid), mac[3]);
  1589. CNIC_WR8(dev, BAR_TSTRORM_INTMEM +
  1590. TSTORM_ISCSI_TCP_VARS_MSB_LOCAL_MAC_ADDR_OFFSET(pfid) + 1,
  1591. mac[2]);
  1592. CNIC_WR8(dev, BAR_TSTRORM_INTMEM +
  1593. TSTORM_ISCSI_TCP_VARS_MSB_LOCAL_MAC_ADDR_OFFSET(pfid) + 2,
  1594. mac[1]);
  1595. CNIC_WR8(dev, BAR_TSTRORM_INTMEM +
  1596. TSTORM_ISCSI_TCP_VARS_MSB_LOCAL_MAC_ADDR_OFFSET(pfid) + 3,
  1597. mac[0]);
  1598. }
  1599. static void cnic_bnx2x_set_tcp_timestamp(struct cnic_dev *dev, int tcp_ts)
  1600. {
  1601. struct cnic_local *cp = dev->cnic_priv;
  1602. u8 xstorm_flags = XSTORM_L5CM_TCP_FLAGS_WND_SCL_EN;
  1603. u16 tstorm_flags = 0;
  1604. if (tcp_ts) {
  1605. xstorm_flags |= XSTORM_L5CM_TCP_FLAGS_TS_ENABLED;
  1606. tstorm_flags |= TSTORM_L5CM_TCP_FLAGS_TS_ENABLED;
  1607. }
  1608. CNIC_WR8(dev, BAR_XSTRORM_INTMEM +
  1609. XSTORM_ISCSI_TCP_VARS_FLAGS_OFFSET(cp->pfid), xstorm_flags);
  1610. CNIC_WR16(dev, BAR_TSTRORM_INTMEM +
  1611. TSTORM_ISCSI_TCP_VARS_FLAGS_OFFSET(cp->pfid), tstorm_flags);
  1612. }
  1613. static int cnic_bnx2x_connect(struct cnic_dev *dev, struct kwqe *wqes[],
  1614. u32 num, int *work)
  1615. {
  1616. struct cnic_local *cp = dev->cnic_priv;
  1617. struct l4_kwq_connect_req1 *kwqe1 =
  1618. (struct l4_kwq_connect_req1 *) wqes[0];
  1619. struct l4_kwq_connect_req3 *kwqe3;
  1620. struct l5cm_active_conn_buffer *conn_buf;
  1621. struct l5cm_conn_addr_params *conn_addr;
  1622. union l5cm_specific_data l5_data;
  1623. u32 l5_cid = kwqe1->pg_cid;
  1624. struct cnic_sock *csk = &cp->csk_tbl[l5_cid];
  1625. struct cnic_context *ctx = &cp->ctx_tbl[l5_cid];
  1626. int ret;
  1627. if (num < 2) {
  1628. *work = num;
  1629. return -EINVAL;
  1630. }
  1631. if (kwqe1->conn_flags & L4_KWQ_CONNECT_REQ1_IP_V6)
  1632. *work = 3;
  1633. else
  1634. *work = 2;
  1635. if (num < *work) {
  1636. *work = num;
  1637. return -EINVAL;
  1638. }
  1639. if (sizeof(*conn_buf) > CNIC_KWQ16_DATA_SIZE) {
  1640. netdev_err(dev->netdev, "conn_buf size too big\n");
  1641. return -ENOMEM;
  1642. }
  1643. conn_buf = cnic_get_kwqe_16_data(cp, l5_cid, &l5_data);
  1644. if (!conn_buf)
  1645. return -ENOMEM;
  1646. memset(conn_buf, 0, sizeof(*conn_buf));
  1647. conn_addr = &conn_buf->conn_addr_buf;
  1648. conn_addr->remote_addr_0 = csk->ha[0];
  1649. conn_addr->remote_addr_1 = csk->ha[1];
  1650. conn_addr->remote_addr_2 = csk->ha[2];
  1651. conn_addr->remote_addr_3 = csk->ha[3];
  1652. conn_addr->remote_addr_4 = csk->ha[4];
  1653. conn_addr->remote_addr_5 = csk->ha[5];
  1654. if (kwqe1->conn_flags & L4_KWQ_CONNECT_REQ1_IP_V6) {
  1655. struct l4_kwq_connect_req2 *kwqe2 =
  1656. (struct l4_kwq_connect_req2 *) wqes[1];
  1657. conn_addr->local_ip_addr.ip_addr_hi_hi = kwqe2->src_ip_v6_4;
  1658. conn_addr->local_ip_addr.ip_addr_hi_lo = kwqe2->src_ip_v6_3;
  1659. conn_addr->local_ip_addr.ip_addr_lo_hi = kwqe2->src_ip_v6_2;
  1660. conn_addr->remote_ip_addr.ip_addr_hi_hi = kwqe2->dst_ip_v6_4;
  1661. conn_addr->remote_ip_addr.ip_addr_hi_lo = kwqe2->dst_ip_v6_3;
  1662. conn_addr->remote_ip_addr.ip_addr_lo_hi = kwqe2->dst_ip_v6_2;
  1663. conn_addr->params |= L5CM_CONN_ADDR_PARAMS_IP_VERSION;
  1664. }
  1665. kwqe3 = (struct l4_kwq_connect_req3 *) wqes[*work - 1];
  1666. conn_addr->local_ip_addr.ip_addr_lo_lo = kwqe1->src_ip;
  1667. conn_addr->remote_ip_addr.ip_addr_lo_lo = kwqe1->dst_ip;
  1668. conn_addr->local_tcp_port = kwqe1->src_port;
  1669. conn_addr->remote_tcp_port = kwqe1->dst_port;
  1670. conn_addr->pmtu = kwqe3->pmtu;
  1671. cnic_init_storm_conn_bufs(dev, kwqe1, kwqe3, conn_buf);
  1672. CNIC_WR16(dev, BAR_XSTRORM_INTMEM +
  1673. XSTORM_ISCSI_LOCAL_VLAN_OFFSET(cp->pfid), csk->vlan_id);
  1674. cnic_bnx2x_set_tcp_timestamp(dev,
  1675. kwqe1->tcp_flags & L4_KWQ_CONNECT_REQ1_TIME_STAMP);
  1676. ret = cnic_submit_kwqe_16(dev, L5CM_RAMROD_CMD_ID_TCP_CONNECT,
  1677. kwqe1->cid, ISCSI_CONNECTION_TYPE, &l5_data);
  1678. if (!ret)
  1679. set_bit(CTX_FL_OFFLD_START, &ctx->ctx_flags);
  1680. return ret;
  1681. }
  1682. static int cnic_bnx2x_close(struct cnic_dev *dev, struct kwqe *kwqe)
  1683. {
  1684. struct l4_kwq_close_req *req = (struct l4_kwq_close_req *) kwqe;
  1685. union l5cm_specific_data l5_data;
  1686. int ret;
  1687. memset(&l5_data, 0, sizeof(l5_data));
  1688. ret = cnic_submit_kwqe_16(dev, L5CM_RAMROD_CMD_ID_CLOSE,
  1689. req->cid, ISCSI_CONNECTION_TYPE, &l5_data);
  1690. return ret;
  1691. }
  1692. static int cnic_bnx2x_reset(struct cnic_dev *dev, struct kwqe *kwqe)
  1693. {
  1694. struct l4_kwq_reset_req *req = (struct l4_kwq_reset_req *) kwqe;
  1695. union l5cm_specific_data l5_data;
  1696. int ret;
  1697. memset(&l5_data, 0, sizeof(l5_data));
  1698. ret = cnic_submit_kwqe_16(dev, L5CM_RAMROD_CMD_ID_ABORT,
  1699. req->cid, ISCSI_CONNECTION_TYPE, &l5_data);
  1700. return ret;
  1701. }
  1702. static int cnic_bnx2x_offload_pg(struct cnic_dev *dev, struct kwqe *kwqe)
  1703. {
  1704. struct l4_kwq_offload_pg *req = (struct l4_kwq_offload_pg *) kwqe;
  1705. struct l4_kcq kcqe;
  1706. struct kcqe *cqes[1];
  1707. memset(&kcqe, 0, sizeof(kcqe));
  1708. kcqe.pg_host_opaque = req->host_opaque;
  1709. kcqe.pg_cid = req->host_opaque;
  1710. kcqe.op_code = L4_KCQE_OPCODE_VALUE_OFFLOAD_PG;
  1711. cqes[0] = (struct kcqe *) &kcqe;
  1712. cnic_reply_bnx2x_kcqes(dev, CNIC_ULP_L4, cqes, 1);
  1713. return 0;
  1714. }
  1715. static int cnic_bnx2x_update_pg(struct cnic_dev *dev, struct kwqe *kwqe)
  1716. {
  1717. struct l4_kwq_update_pg *req = (struct l4_kwq_update_pg *) kwqe;
  1718. struct l4_kcq kcqe;
  1719. struct kcqe *cqes[1];
  1720. memset(&kcqe, 0, sizeof(kcqe));
  1721. kcqe.pg_host_opaque = req->pg_host_opaque;
  1722. kcqe.pg_cid = req->pg_cid;
  1723. kcqe.op_code = L4_KCQE_OPCODE_VALUE_UPDATE_PG;
  1724. cqes[0] = (struct kcqe *) &kcqe;
  1725. cnic_reply_bnx2x_kcqes(dev, CNIC_ULP_L4, cqes, 1);
  1726. return 0;
  1727. }
  1728. static int cnic_submit_bnx2x_kwqes(struct cnic_dev *dev, struct kwqe *wqes[],
  1729. u32 num_wqes)
  1730. {
  1731. int i, work, ret;
  1732. u32 opcode;
  1733. struct kwqe *kwqe;
  1734. if (!test_bit(CNIC_F_CNIC_UP, &dev->flags))
  1735. return -EAGAIN; /* bnx2 is down */
  1736. for (i = 0; i < num_wqes; ) {
  1737. kwqe = wqes[i];
  1738. opcode = KWQE_OPCODE(kwqe->kwqe_op_flag);
  1739. work = 1;
  1740. switch (opcode) {
  1741. case ISCSI_KWQE_OPCODE_INIT1:
  1742. ret = cnic_bnx2x_iscsi_init1(dev, kwqe);
  1743. break;
  1744. case ISCSI_KWQE_OPCODE_INIT2:
  1745. ret = cnic_bnx2x_iscsi_init2(dev, kwqe);
  1746. break;
  1747. case ISCSI_KWQE_OPCODE_OFFLOAD_CONN1:
  1748. ret = cnic_bnx2x_iscsi_ofld1(dev, &wqes[i],
  1749. num_wqes - i, &work);
  1750. break;
  1751. case ISCSI_KWQE_OPCODE_UPDATE_CONN:
  1752. ret = cnic_bnx2x_iscsi_update(dev, kwqe);
  1753. break;
  1754. case ISCSI_KWQE_OPCODE_DESTROY_CONN:
  1755. ret = cnic_bnx2x_iscsi_destroy(dev, kwqe);
  1756. break;
  1757. case L4_KWQE_OPCODE_VALUE_CONNECT1:
  1758. ret = cnic_bnx2x_connect(dev, &wqes[i], num_wqes - i,
  1759. &work);
  1760. break;
  1761. case L4_KWQE_OPCODE_VALUE_CLOSE:
  1762. ret = cnic_bnx2x_close(dev, kwqe);
  1763. break;
  1764. case L4_KWQE_OPCODE_VALUE_RESET:
  1765. ret = cnic_bnx2x_reset(dev, kwqe);
  1766. break;
  1767. case L4_KWQE_OPCODE_VALUE_OFFLOAD_PG:
  1768. ret = cnic_bnx2x_offload_pg(dev, kwqe);
  1769. break;
  1770. case L4_KWQE_OPCODE_VALUE_UPDATE_PG:
  1771. ret = cnic_bnx2x_update_pg(dev, kwqe);
  1772. break;
  1773. case L4_KWQE_OPCODE_VALUE_UPLOAD_PG:
  1774. ret = 0;
  1775. break;
  1776. default:
  1777. ret = 0;
  1778. netdev_err(dev->netdev, "Unknown type of KWQE(0x%x)\n",
  1779. opcode);
  1780. break;
  1781. }
  1782. if (ret < 0)
  1783. netdev_err(dev->netdev, "KWQE(0x%x) failed\n",
  1784. opcode);
  1785. i += work;
  1786. }
  1787. return 0;
  1788. }
  1789. static void service_kcqes(struct cnic_dev *dev, int num_cqes)
  1790. {
  1791. struct cnic_local *cp = dev->cnic_priv;
  1792. int i, j, comp = 0;
  1793. i = 0;
  1794. j = 1;
  1795. while (num_cqes) {
  1796. struct cnic_ulp_ops *ulp_ops;
  1797. int ulp_type;
  1798. u32 kcqe_op_flag = cp->completed_kcq[i]->kcqe_op_flag;
  1799. u32 kcqe_layer = kcqe_op_flag & KCQE_FLAGS_LAYER_MASK;
  1800. if (unlikely(kcqe_op_flag & KCQE_RAMROD_COMPLETION))
  1801. comp++;
  1802. while (j < num_cqes) {
  1803. u32 next_op = cp->completed_kcq[i + j]->kcqe_op_flag;
  1804. if ((next_op & KCQE_FLAGS_LAYER_MASK) != kcqe_layer)
  1805. break;
  1806. if (unlikely(next_op & KCQE_RAMROD_COMPLETION))
  1807. comp++;
  1808. j++;
  1809. }
  1810. if (kcqe_layer == KCQE_FLAGS_LAYER_MASK_L5_RDMA)
  1811. ulp_type = CNIC_ULP_RDMA;
  1812. else if (kcqe_layer == KCQE_FLAGS_LAYER_MASK_L5_ISCSI)
  1813. ulp_type = CNIC_ULP_ISCSI;
  1814. else if (kcqe_layer == KCQE_FLAGS_LAYER_MASK_L4)
  1815. ulp_type = CNIC_ULP_L4;
  1816. else if (kcqe_layer == KCQE_FLAGS_LAYER_MASK_L2)
  1817. goto end;
  1818. else {
  1819. netdev_err(dev->netdev, "Unknown type of KCQE(0x%x)\n",
  1820. kcqe_op_flag);
  1821. goto end;
  1822. }
  1823. rcu_read_lock();
  1824. ulp_ops = rcu_dereference(cp->ulp_ops[ulp_type]);
  1825. if (likely(ulp_ops)) {
  1826. ulp_ops->indicate_kcqes(cp->ulp_handle[ulp_type],
  1827. cp->completed_kcq + i, j);
  1828. }
  1829. rcu_read_unlock();
  1830. end:
  1831. num_cqes -= j;
  1832. i += j;
  1833. j = 1;
  1834. }
  1835. if (unlikely(comp))
  1836. cnic_spq_completion(dev, DRV_CTL_RET_L5_SPQ_CREDIT_CMD, comp);
  1837. }
  1838. static u16 cnic_bnx2_next_idx(u16 idx)
  1839. {
  1840. return idx + 1;
  1841. }
  1842. static u16 cnic_bnx2_hw_idx(u16 idx)
  1843. {
  1844. return idx;
  1845. }
  1846. static u16 cnic_bnx2x_next_idx(u16 idx)
  1847. {
  1848. idx++;
  1849. if ((idx & MAX_KCQE_CNT) == MAX_KCQE_CNT)
  1850. idx++;
  1851. return idx;
  1852. }
  1853. static u16 cnic_bnx2x_hw_idx(u16 idx)
  1854. {
  1855. if ((idx & MAX_KCQE_CNT) == MAX_KCQE_CNT)
  1856. idx++;
  1857. return idx;
  1858. }
  1859. static int cnic_get_kcqes(struct cnic_dev *dev, struct kcq_info *info)
  1860. {
  1861. struct cnic_local *cp = dev->cnic_priv;
  1862. u16 i, ri, hw_prod, last;
  1863. struct kcqe *kcqe;
  1864. int kcqe_cnt = 0, last_cnt = 0;
  1865. i = ri = last = info->sw_prod_idx;
  1866. ri &= MAX_KCQ_IDX;
  1867. hw_prod = *info->hw_prod_idx_ptr;
  1868. hw_prod = cp->hw_idx(hw_prod);
  1869. while ((i != hw_prod) && (kcqe_cnt < MAX_COMPLETED_KCQE)) {
  1870. kcqe = &info->kcq[KCQ_PG(ri)][KCQ_IDX(ri)];
  1871. cp->completed_kcq[kcqe_cnt++] = kcqe;
  1872. i = cp->next_idx(i);
  1873. ri = i & MAX_KCQ_IDX;
  1874. if (likely(!(kcqe->kcqe_op_flag & KCQE_FLAGS_NEXT))) {
  1875. last_cnt = kcqe_cnt;
  1876. last = i;
  1877. }
  1878. }
  1879. info->sw_prod_idx = last;
  1880. return last_cnt;
  1881. }
  1882. static int cnic_l2_completion(struct cnic_local *cp)
  1883. {
  1884. u16 hw_cons, sw_cons;
  1885. struct cnic_uio_dev *udev = cp->udev;
  1886. union eth_rx_cqe *cqe, *cqe_ring = (union eth_rx_cqe *)
  1887. (udev->l2_ring + (2 * BCM_PAGE_SIZE));
  1888. u32 cmd;
  1889. int comp = 0;
  1890. if (!test_bit(CNIC_F_BNX2X_CLASS, &cp->dev->flags))
  1891. return 0;
  1892. hw_cons = *cp->rx_cons_ptr;
  1893. if ((hw_cons & BNX2X_MAX_RCQ_DESC_CNT) == BNX2X_MAX_RCQ_DESC_CNT)
  1894. hw_cons++;
  1895. sw_cons = cp->rx_cons;
  1896. while (sw_cons != hw_cons) {
  1897. u8 cqe_fp_flags;
  1898. cqe = &cqe_ring[sw_cons & BNX2X_MAX_RCQ_DESC_CNT];
  1899. cqe_fp_flags = cqe->fast_path_cqe.type_error_flags;
  1900. if (cqe_fp_flags & ETH_FAST_PATH_RX_CQE_TYPE) {
  1901. cmd = le32_to_cpu(cqe->ramrod_cqe.conn_and_cmd_data);
  1902. cmd >>= COMMON_RAMROD_ETH_RX_CQE_CMD_ID_SHIFT;
  1903. if (cmd == RAMROD_CMD_ID_ETH_CLIENT_SETUP ||
  1904. cmd == RAMROD_CMD_ID_ETH_HALT)
  1905. comp++;
  1906. }
  1907. sw_cons = BNX2X_NEXT_RCQE(sw_cons);
  1908. }
  1909. return comp;
  1910. }
  1911. static void cnic_chk_pkt_rings(struct cnic_local *cp)
  1912. {
  1913. u16 rx_cons, tx_cons;
  1914. int comp = 0;
  1915. if (!test_bit(CNIC_LCL_FL_RINGS_INITED, &cp->cnic_local_flags))
  1916. return;
  1917. rx_cons = *cp->rx_cons_ptr;
  1918. tx_cons = *cp->tx_cons_ptr;
  1919. if (cp->tx_cons != tx_cons || cp->rx_cons != rx_cons) {
  1920. if (test_bit(CNIC_LCL_FL_L2_WAIT, &cp->cnic_local_flags))
  1921. comp = cnic_l2_completion(cp);
  1922. cp->tx_cons = tx_cons;
  1923. cp->rx_cons = rx_cons;
  1924. if (cp->udev)
  1925. uio_event_notify(&cp->udev->cnic_uinfo);
  1926. }
  1927. if (comp)
  1928. clear_bit(CNIC_LCL_FL_L2_WAIT, &cp->cnic_local_flags);
  1929. }
  1930. static u32 cnic_service_bnx2_queues(struct cnic_dev *dev)
  1931. {
  1932. struct cnic_local *cp = dev->cnic_priv;
  1933. u32 status_idx = (u16) *cp->kcq1.status_idx_ptr;
  1934. int kcqe_cnt;
  1935. cp->kwq_con_idx = *cp->kwq_con_idx_ptr;
  1936. while ((kcqe_cnt = cnic_get_kcqes(dev, &cp->kcq1))) {
  1937. service_kcqes(dev, kcqe_cnt);
  1938. /* Tell compiler that status_blk fields can change. */
  1939. barrier();
  1940. if (status_idx != *cp->kcq1.status_idx_ptr) {
  1941. status_idx = (u16) *cp->kcq1.status_idx_ptr;
  1942. cp->kwq_con_idx = *cp->kwq_con_idx_ptr;
  1943. } else
  1944. break;
  1945. }
  1946. CNIC_WR16(dev, cp->kcq1.io_addr, cp->kcq1.sw_prod_idx);
  1947. cnic_chk_pkt_rings(cp);
  1948. return status_idx;
  1949. }
  1950. static int cnic_service_bnx2(void *data, void *status_blk)
  1951. {
  1952. struct cnic_dev *dev = data;
  1953. struct cnic_local *cp = dev->cnic_priv;
  1954. u32 status_idx = *cp->kcq1.status_idx_ptr;
  1955. if (unlikely(!test_bit(CNIC_F_CNIC_UP, &dev->flags)))
  1956. return status_idx;
  1957. return cnic_service_bnx2_queues(dev);
  1958. }
  1959. static void cnic_service_bnx2_msix(unsigned long data)
  1960. {
  1961. struct cnic_dev *dev = (struct cnic_dev *) data;
  1962. struct cnic_local *cp = dev->cnic_priv;
  1963. cp->last_status_idx = cnic_service_bnx2_queues(dev);
  1964. CNIC_WR(dev, BNX2_PCICFG_INT_ACK_CMD, cp->int_num |
  1965. BNX2_PCICFG_INT_ACK_CMD_INDEX_VALID | cp->last_status_idx);
  1966. }
  1967. static void cnic_doirq(struct cnic_dev *dev)
  1968. {
  1969. struct cnic_local *cp = dev->cnic_priv;
  1970. u16 prod = cp->kcq1.sw_prod_idx & MAX_KCQ_IDX;
  1971. if (likely(test_bit(CNIC_F_CNIC_UP, &dev->flags))) {
  1972. prefetch(cp->status_blk.gen);
  1973. prefetch(&cp->kcq1.kcq[KCQ_PG(prod)][KCQ_IDX(prod)]);
  1974. tasklet_schedule(&cp->cnic_irq_task);
  1975. }
  1976. }
  1977. static irqreturn_t cnic_irq(int irq, void *dev_instance)
  1978. {
  1979. struct cnic_dev *dev = dev_instance;
  1980. struct cnic_local *cp = dev->cnic_priv;
  1981. if (cp->ack_int)
  1982. cp->ack_int(dev);
  1983. cnic_doirq(dev);
  1984. return IRQ_HANDLED;
  1985. }
  1986. static inline void cnic_ack_bnx2x_int(struct cnic_dev *dev, u8 id, u8 storm,
  1987. u16 index, u8 op, u8 update)
  1988. {
  1989. struct cnic_local *cp = dev->cnic_priv;
  1990. u32 hc_addr = (HC_REG_COMMAND_REG + CNIC_PORT(cp) * 32 +
  1991. COMMAND_REG_INT_ACK);
  1992. struct igu_ack_register igu_ack;
  1993. igu_ack.status_block_index = index;
  1994. igu_ack.sb_id_and_flags =
  1995. ((id << IGU_ACK_REGISTER_STATUS_BLOCK_ID_SHIFT) |
  1996. (storm << IGU_ACK_REGISTER_STORM_ID_SHIFT) |
  1997. (update << IGU_ACK_REGISTER_UPDATE_INDEX_SHIFT) |
  1998. (op << IGU_ACK_REGISTER_INTERRUPT_MODE_SHIFT));
  1999. CNIC_WR(dev, hc_addr, (*(u32 *)&igu_ack));
  2000. }
  2001. static void cnic_ack_igu_sb(struct cnic_dev *dev, u8 igu_sb_id, u8 segment,
  2002. u16 index, u8 op, u8 update)
  2003. {
  2004. struct igu_regular cmd_data;
  2005. u32 igu_addr = BAR_IGU_INTMEM + (IGU_CMD_INT_ACK_BASE + igu_sb_id) * 8;
  2006. cmd_data.sb_id_and_flags =
  2007. (index << IGU_REGULAR_SB_INDEX_SHIFT) |
  2008. (segment << IGU_REGULAR_SEGMENT_ACCESS_SHIFT) |
  2009. (update << IGU_REGULAR_BUPDATE_SHIFT) |
  2010. (op << IGU_REGULAR_ENABLE_INT_SHIFT);
  2011. CNIC_WR(dev, igu_addr, cmd_data.sb_id_and_flags);
  2012. }
  2013. static void cnic_ack_bnx2x_msix(struct cnic_dev *dev)
  2014. {
  2015. struct cnic_local *cp = dev->cnic_priv;
  2016. cnic_ack_bnx2x_int(dev, cp->bnx2x_igu_sb_id, CSTORM_ID, 0,
  2017. IGU_INT_DISABLE, 0);
  2018. }
  2019. static void cnic_ack_bnx2x_e2_msix(struct cnic_dev *dev)
  2020. {
  2021. struct cnic_local *cp = dev->cnic_priv;
  2022. cnic_ack_igu_sb(dev, cp->bnx2x_igu_sb_id, IGU_SEG_ACCESS_DEF, 0,
  2023. IGU_INT_DISABLE, 0);
  2024. }
  2025. static u32 cnic_service_bnx2x_kcq(struct cnic_dev *dev, struct kcq_info *info)
  2026. {
  2027. u32 last_status = *info->status_idx_ptr;
  2028. int kcqe_cnt;
  2029. while ((kcqe_cnt = cnic_get_kcqes(dev, info))) {
  2030. service_kcqes(dev, kcqe_cnt);
  2031. /* Tell compiler that sblk fields can change. */
  2032. barrier();
  2033. if (last_status == *info->status_idx_ptr)
  2034. break;
  2035. last_status = *info->status_idx_ptr;
  2036. }
  2037. return last_status;
  2038. }
  2039. static void cnic_service_bnx2x_bh(unsigned long data)
  2040. {
  2041. struct cnic_dev *dev = (struct cnic_dev *) data;
  2042. struct cnic_local *cp = dev->cnic_priv;
  2043. u32 status_idx;
  2044. if (unlikely(!test_bit(CNIC_F_CNIC_UP, &dev->flags)))
  2045. return;
  2046. status_idx = cnic_service_bnx2x_kcq(dev, &cp->kcq1);
  2047. CNIC_WR16(dev, cp->kcq1.io_addr, cp->kcq1.sw_prod_idx + MAX_KCQ_IDX);
  2048. if (BNX2X_CHIP_IS_E2(cp->chip_id))
  2049. cnic_ack_igu_sb(dev, cp->bnx2x_igu_sb_id, IGU_SEG_ACCESS_DEF,
  2050. status_idx, IGU_INT_ENABLE, 1);
  2051. else
  2052. cnic_ack_bnx2x_int(dev, cp->bnx2x_igu_sb_id, USTORM_ID,
  2053. status_idx, IGU_INT_ENABLE, 1);
  2054. }
  2055. static int cnic_service_bnx2x(void *data, void *status_blk)
  2056. {
  2057. struct cnic_dev *dev = data;
  2058. struct cnic_local *cp = dev->cnic_priv;
  2059. if (!(cp->ethdev->drv_state & CNIC_DRV_STATE_USING_MSIX))
  2060. cnic_doirq(dev);
  2061. cnic_chk_pkt_rings(cp);
  2062. return 0;
  2063. }
  2064. static void cnic_ulp_stop(struct cnic_dev *dev)
  2065. {
  2066. struct cnic_local *cp = dev->cnic_priv;
  2067. int if_type;
  2068. cnic_send_nlmsg(cp, ISCSI_KEVENT_IF_DOWN, NULL);
  2069. for (if_type = 0; if_type < MAX_CNIC_ULP_TYPE; if_type++) {
  2070. struct cnic_ulp_ops *ulp_ops;
  2071. mutex_lock(&cnic_lock);
  2072. ulp_ops = cp->ulp_ops[if_type];
  2073. if (!ulp_ops) {
  2074. mutex_unlock(&cnic_lock);
  2075. continue;
  2076. }
  2077. set_bit(ULP_F_CALL_PENDING, &cp->ulp_flags[if_type]);
  2078. mutex_unlock(&cnic_lock);
  2079. if (test_and_clear_bit(ULP_F_START, &cp->ulp_flags[if_type]))
  2080. ulp_ops->cnic_stop(cp->ulp_handle[if_type]);
  2081. clear_bit(ULP_F_CALL_PENDING, &cp->ulp_flags[if_type]);
  2082. }
  2083. }
  2084. static void cnic_ulp_start(struct cnic_dev *dev)
  2085. {
  2086. struct cnic_local *cp = dev->cnic_priv;
  2087. int if_type;
  2088. for (if_type = 0; if_type < MAX_CNIC_ULP_TYPE; if_type++) {
  2089. struct cnic_ulp_ops *ulp_ops;
  2090. mutex_lock(&cnic_lock);
  2091. ulp_ops = cp->ulp_ops[if_type];
  2092. if (!ulp_ops || !ulp_ops->cnic_start) {
  2093. mutex_unlock(&cnic_lock);
  2094. continue;
  2095. }
  2096. set_bit(ULP_F_CALL_PENDING, &cp->ulp_flags[if_type]);
  2097. mutex_unlock(&cnic_lock);
  2098. if (!test_and_set_bit(ULP_F_START, &cp->ulp_flags[if_type]))
  2099. ulp_ops->cnic_start(cp->ulp_handle[if_type]);
  2100. clear_bit(ULP_F_CALL_PENDING, &cp->ulp_flags[if_type]);
  2101. }
  2102. }
  2103. static int cnic_ctl(void *data, struct cnic_ctl_info *info)
  2104. {
  2105. struct cnic_dev *dev = data;
  2106. switch (info->cmd) {
  2107. case CNIC_CTL_STOP_CMD:
  2108. cnic_hold(dev);
  2109. cnic_ulp_stop(dev);
  2110. cnic_stop_hw(dev);
  2111. cnic_put(dev);
  2112. break;
  2113. case CNIC_CTL_START_CMD:
  2114. cnic_hold(dev);
  2115. if (!cnic_start_hw(dev))
  2116. cnic_ulp_start(dev);
  2117. cnic_put(dev);
  2118. break;
  2119. case CNIC_CTL_COMPLETION_CMD: {
  2120. u32 cid = BNX2X_SW_CID(info->data.comp.cid);
  2121. u32 l5_cid;
  2122. struct cnic_local *cp = dev->cnic_priv;
  2123. if (cnic_get_l5_cid(cp, cid, &l5_cid) == 0) {
  2124. struct cnic_context *ctx = &cp->ctx_tbl[l5_cid];
  2125. ctx->wait_cond = 1;
  2126. wake_up(&ctx->waitq);
  2127. }
  2128. break;
  2129. }
  2130. default:
  2131. return -EINVAL;
  2132. }
  2133. return 0;
  2134. }
  2135. static void cnic_ulp_init(struct cnic_dev *dev)
  2136. {
  2137. int i;
  2138. struct cnic_local *cp = dev->cnic_priv;
  2139. for (i = 0; i < MAX_CNIC_ULP_TYPE_EXT; i++) {
  2140. struct cnic_ulp_ops *ulp_ops;
  2141. mutex_lock(&cnic_lock);
  2142. ulp_ops = cnic_ulp_tbl[i];
  2143. if (!ulp_ops || !ulp_ops->cnic_init) {
  2144. mutex_unlock(&cnic_lock);
  2145. continue;
  2146. }
  2147. ulp_get(ulp_ops);
  2148. mutex_unlock(&cnic_lock);
  2149. if (!test_and_set_bit(ULP_F_INIT, &cp->ulp_flags[i]))
  2150. ulp_ops->cnic_init(dev);
  2151. ulp_put(ulp_ops);
  2152. }
  2153. }
  2154. static void cnic_ulp_exit(struct cnic_dev *dev)
  2155. {
  2156. int i;
  2157. struct cnic_local *cp = dev->cnic_priv;
  2158. for (i = 0; i < MAX_CNIC_ULP_TYPE_EXT; i++) {
  2159. struct cnic_ulp_ops *ulp_ops;
  2160. mutex_lock(&cnic_lock);
  2161. ulp_ops = cnic_ulp_tbl[i];
  2162. if (!ulp_ops || !ulp_ops->cnic_exit) {
  2163. mutex_unlock(&cnic_lock);
  2164. continue;
  2165. }
  2166. ulp_get(ulp_ops);
  2167. mutex_unlock(&cnic_lock);
  2168. if (test_and_clear_bit(ULP_F_INIT, &cp->ulp_flags[i]))
  2169. ulp_ops->cnic_exit(dev);
  2170. ulp_put(ulp_ops);
  2171. }
  2172. }
  2173. static int cnic_cm_offload_pg(struct cnic_sock *csk)
  2174. {
  2175. struct cnic_dev *dev = csk->dev;
  2176. struct l4_kwq_offload_pg *l4kwqe;
  2177. struct kwqe *wqes[1];
  2178. l4kwqe = (struct l4_kwq_offload_pg *) &csk->kwqe1;
  2179. memset(l4kwqe, 0, sizeof(*l4kwqe));
  2180. wqes[0] = (struct kwqe *) l4kwqe;
  2181. l4kwqe->op_code = L4_KWQE_OPCODE_VALUE_OFFLOAD_PG;
  2182. l4kwqe->flags =
  2183. L4_LAYER_CODE << L4_KWQ_OFFLOAD_PG_LAYER_CODE_SHIFT;
  2184. l4kwqe->l2hdr_nbytes = ETH_HLEN;
  2185. l4kwqe->da0 = csk->ha[0];
  2186. l4kwqe->da1 = csk->ha[1];
  2187. l4kwqe->da2 = csk->ha[2];
  2188. l4kwqe->da3 = csk->ha[3];
  2189. l4kwqe->da4 = csk->ha[4];
  2190. l4kwqe->da5 = csk->ha[5];
  2191. l4kwqe->sa0 = dev->mac_addr[0];
  2192. l4kwqe->sa1 = dev->mac_addr[1];
  2193. l4kwqe->sa2 = dev->mac_addr[2];
  2194. l4kwqe->sa3 = dev->mac_addr[3];
  2195. l4kwqe->sa4 = dev->mac_addr[4];
  2196. l4kwqe->sa5 = dev->mac_addr[5];
  2197. l4kwqe->etype = ETH_P_IP;
  2198. l4kwqe->ipid_start = DEF_IPID_START;
  2199. l4kwqe->host_opaque = csk->l5_cid;
  2200. if (csk->vlan_id) {
  2201. l4kwqe->pg_flags |= L4_KWQ_OFFLOAD_PG_VLAN_TAGGING;
  2202. l4kwqe->vlan_tag = csk->vlan_id;
  2203. l4kwqe->l2hdr_nbytes += 4;
  2204. }
  2205. return dev->submit_kwqes(dev, wqes, 1);
  2206. }
  2207. static int cnic_cm_update_pg(struct cnic_sock *csk)
  2208. {
  2209. struct cnic_dev *dev = csk->dev;
  2210. struct l4_kwq_update_pg *l4kwqe;
  2211. struct kwqe *wqes[1];
  2212. l4kwqe = (struct l4_kwq_update_pg *) &csk->kwqe1;
  2213. memset(l4kwqe, 0, sizeof(*l4kwqe));
  2214. wqes[0] = (struct kwqe *) l4kwqe;
  2215. l4kwqe->opcode = L4_KWQE_OPCODE_VALUE_UPDATE_PG;
  2216. l4kwqe->flags =
  2217. L4_LAYER_CODE << L4_KWQ_UPDATE_PG_LAYER_CODE_SHIFT;
  2218. l4kwqe->pg_cid = csk->pg_cid;
  2219. l4kwqe->da0 = csk->ha[0];
  2220. l4kwqe->da1 = csk->ha[1];
  2221. l4kwqe->da2 = csk->ha[2];
  2222. l4kwqe->da3 = csk->ha[3];
  2223. l4kwqe->da4 = csk->ha[4];
  2224. l4kwqe->da5 = csk->ha[5];
  2225. l4kwqe->pg_host_opaque = csk->l5_cid;
  2226. l4kwqe->pg_valids = L4_KWQ_UPDATE_PG_VALIDS_DA;
  2227. return dev->submit_kwqes(dev, wqes, 1);
  2228. }
  2229. static int cnic_cm_upload_pg(struct cnic_sock *csk)
  2230. {
  2231. struct cnic_dev *dev = csk->dev;
  2232. struct l4_kwq_upload *l4kwqe;
  2233. struct kwqe *wqes[1];
  2234. l4kwqe = (struct l4_kwq_upload *) &csk->kwqe1;
  2235. memset(l4kwqe, 0, sizeof(*l4kwqe));
  2236. wqes[0] = (struct kwqe *) l4kwqe;
  2237. l4kwqe->opcode = L4_KWQE_OPCODE_VALUE_UPLOAD_PG;
  2238. l4kwqe->flags =
  2239. L4_LAYER_CODE << L4_KWQ_UPLOAD_LAYER_CODE_SHIFT;
  2240. l4kwqe->cid = csk->pg_cid;
  2241. return dev->submit_kwqes(dev, wqes, 1);
  2242. }
  2243. static int cnic_cm_conn_req(struct cnic_sock *csk)
  2244. {
  2245. struct cnic_dev *dev = csk->dev;
  2246. struct l4_kwq_connect_req1 *l4kwqe1;
  2247. struct l4_kwq_connect_req2 *l4kwqe2;
  2248. struct l4_kwq_connect_req3 *l4kwqe3;
  2249. struct kwqe *wqes[3];
  2250. u8 tcp_flags = 0;
  2251. int num_wqes = 2;
  2252. l4kwqe1 = (struct l4_kwq_connect_req1 *) &csk->kwqe1;
  2253. l4kwqe2 = (struct l4_kwq_connect_req2 *) &csk->kwqe2;
  2254. l4kwqe3 = (struct l4_kwq_connect_req3 *) &csk->kwqe3;
  2255. memset(l4kwqe1, 0, sizeof(*l4kwqe1));
  2256. memset(l4kwqe2, 0, sizeof(*l4kwqe2));
  2257. memset(l4kwqe3, 0, sizeof(*l4kwqe3));
  2258. l4kwqe3->op_code = L4_KWQE_OPCODE_VALUE_CONNECT3;
  2259. l4kwqe3->flags =
  2260. L4_LAYER_CODE << L4_KWQ_CONNECT_REQ3_LAYER_CODE_SHIFT;
  2261. l4kwqe3->ka_timeout = csk->ka_timeout;
  2262. l4kwqe3->ka_interval = csk->ka_interval;
  2263. l4kwqe3->ka_max_probe_count = csk->ka_max_probe_count;
  2264. l4kwqe3->tos = csk->tos;
  2265. l4kwqe3->ttl = csk->ttl;
  2266. l4kwqe3->snd_seq_scale = csk->snd_seq_scale;
  2267. l4kwqe3->pmtu = csk->mtu;
  2268. l4kwqe3->rcv_buf = csk->rcv_buf;
  2269. l4kwqe3->snd_buf = csk->snd_buf;
  2270. l4kwqe3->seed = csk->seed;
  2271. wqes[0] = (struct kwqe *) l4kwqe1;
  2272. if (test_bit(SK_F_IPV6, &csk->flags)) {
  2273. wqes[1] = (struct kwqe *) l4kwqe2;
  2274. wqes[2] = (struct kwqe *) l4kwqe3;
  2275. num_wqes = 3;
  2276. l4kwqe1->conn_flags = L4_KWQ_CONNECT_REQ1_IP_V6;
  2277. l4kwqe2->op_code = L4_KWQE_OPCODE_VALUE_CONNECT2;
  2278. l4kwqe2->flags =
  2279. L4_KWQ_CONNECT_REQ2_LINKED_WITH_NEXT |
  2280. L4_LAYER_CODE << L4_KWQ_CONNECT_REQ2_LAYER_CODE_SHIFT;
  2281. l4kwqe2->src_ip_v6_2 = be32_to_cpu(csk->src_ip[1]);
  2282. l4kwqe2->src_ip_v6_3 = be32_to_cpu(csk->src_ip[2]);
  2283. l4kwqe2->src_ip_v6_4 = be32_to_cpu(csk->src_ip[3]);
  2284. l4kwqe2->dst_ip_v6_2 = be32_to_cpu(csk->dst_ip[1]);
  2285. l4kwqe2->dst_ip_v6_3 = be32_to_cpu(csk->dst_ip[2]);
  2286. l4kwqe2->dst_ip_v6_4 = be32_to_cpu(csk->dst_ip[3]);
  2287. l4kwqe3->mss = l4kwqe3->pmtu - sizeof(struct ipv6hdr) -
  2288. sizeof(struct tcphdr);
  2289. } else {
  2290. wqes[1] = (struct kwqe *) l4kwqe3;
  2291. l4kwqe3->mss = l4kwqe3->pmtu - sizeof(struct iphdr) -
  2292. sizeof(struct tcphdr);
  2293. }
  2294. l4kwqe1->op_code = L4_KWQE_OPCODE_VALUE_CONNECT1;
  2295. l4kwqe1->flags =
  2296. (L4_LAYER_CODE << L4_KWQ_CONNECT_REQ1_LAYER_CODE_SHIFT) |
  2297. L4_KWQ_CONNECT_REQ3_LINKED_WITH_NEXT;
  2298. l4kwqe1->cid = csk->cid;
  2299. l4kwqe1->pg_cid = csk->pg_cid;
  2300. l4kwqe1->src_ip = be32_to_cpu(csk->src_ip[0]);
  2301. l4kwqe1->dst_ip = be32_to_cpu(csk->dst_ip[0]);
  2302. l4kwqe1->src_port = be16_to_cpu(csk->src_port);
  2303. l4kwqe1->dst_port = be16_to_cpu(csk->dst_port);
  2304. if (csk->tcp_flags & SK_TCP_NO_DELAY_ACK)
  2305. tcp_flags |= L4_KWQ_CONNECT_REQ1_NO_DELAY_ACK;
  2306. if (csk->tcp_flags & SK_TCP_KEEP_ALIVE)
  2307. tcp_flags |= L4_KWQ_CONNECT_REQ1_KEEP_ALIVE;
  2308. if (csk->tcp_flags & SK_TCP_NAGLE)
  2309. tcp_flags |= L4_KWQ_CONNECT_REQ1_NAGLE_ENABLE;
  2310. if (csk->tcp_flags & SK_TCP_TIMESTAMP)
  2311. tcp_flags |= L4_KWQ_CONNECT_REQ1_TIME_STAMP;
  2312. if (csk->tcp_flags & SK_TCP_SACK)
  2313. tcp_flags |= L4_KWQ_CONNECT_REQ1_SACK;
  2314. if (csk->tcp_flags & SK_TCP_SEG_SCALING)
  2315. tcp_flags |= L4_KWQ_CONNECT_REQ1_SEG_SCALING;
  2316. l4kwqe1->tcp_flags = tcp_flags;
  2317. return dev->submit_kwqes(dev, wqes, num_wqes);
  2318. }
  2319. static int cnic_cm_close_req(struct cnic_sock *csk)
  2320. {
  2321. struct cnic_dev *dev = csk->dev;
  2322. struct l4_kwq_close_req *l4kwqe;
  2323. struct kwqe *wqes[1];
  2324. l4kwqe = (struct l4_kwq_close_req *) &csk->kwqe2;
  2325. memset(l4kwqe, 0, sizeof(*l4kwqe));
  2326. wqes[0] = (struct kwqe *) l4kwqe;
  2327. l4kwqe->op_code = L4_KWQE_OPCODE_VALUE_CLOSE;
  2328. l4kwqe->flags = L4_LAYER_CODE << L4_KWQ_CLOSE_REQ_LAYER_CODE_SHIFT;
  2329. l4kwqe->cid = csk->cid;
  2330. return dev->submit_kwqes(dev, wqes, 1);
  2331. }
  2332. static int cnic_cm_abort_req(struct cnic_sock *csk)
  2333. {
  2334. struct cnic_dev *dev = csk->dev;
  2335. struct l4_kwq_reset_req *l4kwqe;
  2336. struct kwqe *wqes[1];
  2337. l4kwqe = (struct l4_kwq_reset_req *) &csk->kwqe2;
  2338. memset(l4kwqe, 0, sizeof(*l4kwqe));
  2339. wqes[0] = (struct kwqe *) l4kwqe;
  2340. l4kwqe->op_code = L4_KWQE_OPCODE_VALUE_RESET;
  2341. l4kwqe->flags = L4_LAYER_CODE << L4_KWQ_RESET_REQ_LAYER_CODE_SHIFT;
  2342. l4kwqe->cid = csk->cid;
  2343. return dev->submit_kwqes(dev, wqes, 1);
  2344. }
  2345. static int cnic_cm_create(struct cnic_dev *dev, int ulp_type, u32 cid,
  2346. u32 l5_cid, struct cnic_sock **csk, void *context)
  2347. {
  2348. struct cnic_local *cp = dev->cnic_priv;
  2349. struct cnic_sock *csk1;
  2350. if (l5_cid >= MAX_CM_SK_TBL_SZ)
  2351. return -EINVAL;
  2352. if (cp->ctx_tbl) {
  2353. struct cnic_context *ctx = &cp->ctx_tbl[l5_cid];
  2354. if (test_bit(CTX_FL_OFFLD_START, &ctx->ctx_flags))
  2355. return -EAGAIN;
  2356. }
  2357. csk1 = &cp->csk_tbl[l5_cid];
  2358. if (atomic_read(&csk1->ref_count))
  2359. return -EAGAIN;
  2360. if (test_and_set_bit(SK_F_INUSE, &csk1->flags))
  2361. return -EBUSY;
  2362. csk1->dev = dev;
  2363. csk1->cid = cid;
  2364. csk1->l5_cid = l5_cid;
  2365. csk1->ulp_type = ulp_type;
  2366. csk1->context = context;
  2367. csk1->ka_timeout = DEF_KA_TIMEOUT;
  2368. csk1->ka_interval = DEF_KA_INTERVAL;
  2369. csk1->ka_max_probe_count = DEF_KA_MAX_PROBE_COUNT;
  2370. csk1->tos = DEF_TOS;
  2371. csk1->ttl = DEF_TTL;
  2372. csk1->snd_seq_scale = DEF_SND_SEQ_SCALE;
  2373. csk1->rcv_buf = DEF_RCV_BUF;
  2374. csk1->snd_buf = DEF_SND_BUF;
  2375. csk1->seed = DEF_SEED;
  2376. *csk = csk1;
  2377. return 0;
  2378. }
  2379. static void cnic_cm_cleanup(struct cnic_sock *csk)
  2380. {
  2381. if (csk->src_port) {
  2382. struct cnic_dev *dev = csk->dev;
  2383. struct cnic_local *cp = dev->cnic_priv;
  2384. cnic_free_id(&cp->csk_port_tbl, csk->src_port);
  2385. csk->src_port = 0;
  2386. }
  2387. }
  2388. static void cnic_close_conn(struct cnic_sock *csk)
  2389. {
  2390. if (test_bit(SK_F_PG_OFFLD_COMPLETE, &csk->flags)) {
  2391. cnic_cm_upload_pg(csk);
  2392. clear_bit(SK_F_PG_OFFLD_COMPLETE, &csk->flags);
  2393. }
  2394. cnic_cm_cleanup(csk);
  2395. }
  2396. static int cnic_cm_destroy(struct cnic_sock *csk)
  2397. {
  2398. if (!cnic_in_use(csk))
  2399. return -EINVAL;
  2400. csk_hold(csk);
  2401. clear_bit(SK_F_INUSE, &csk->flags);
  2402. smp_mb__after_clear_bit();
  2403. while (atomic_read(&csk->ref_count) != 1)
  2404. msleep(1);
  2405. cnic_cm_cleanup(csk);
  2406. csk->flags = 0;
  2407. csk_put(csk);
  2408. return 0;
  2409. }
  2410. static inline u16 cnic_get_vlan(struct net_device *dev,
  2411. struct net_device **vlan_dev)
  2412. {
  2413. if (dev->priv_flags & IFF_802_1Q_VLAN) {
  2414. *vlan_dev = vlan_dev_real_dev(dev);
  2415. return vlan_dev_vlan_id(dev);
  2416. }
  2417. *vlan_dev = dev;
  2418. return 0;
  2419. }
  2420. static int cnic_get_v4_route(struct sockaddr_in *dst_addr,
  2421. struct dst_entry **dst)
  2422. {
  2423. #if defined(CONFIG_INET)
  2424. struct flowi fl;
  2425. int err;
  2426. struct rtable *rt;
  2427. memset(&fl, 0, sizeof(fl));
  2428. fl.nl_u.ip4_u.daddr = dst_addr->sin_addr.s_addr;
  2429. err = ip_route_output_key(&init_net, &rt, &fl);
  2430. if (!err)
  2431. *dst = &rt->dst;
  2432. return err;
  2433. #else
  2434. return -ENETUNREACH;
  2435. #endif
  2436. }
  2437. static int cnic_get_v6_route(struct sockaddr_in6 *dst_addr,
  2438. struct dst_entry **dst)
  2439. {
  2440. #if defined(CONFIG_IPV6) || (defined(CONFIG_IPV6_MODULE) && defined(MODULE))
  2441. struct flowi fl;
  2442. memset(&fl, 0, sizeof(fl));
  2443. ipv6_addr_copy(&fl.fl6_dst, &dst_addr->sin6_addr);
  2444. if (ipv6_addr_type(&fl.fl6_dst) & IPV6_ADDR_LINKLOCAL)
  2445. fl.oif = dst_addr->sin6_scope_id;
  2446. *dst = ip6_route_output(&init_net, NULL, &fl);
  2447. if (*dst)
  2448. return 0;
  2449. #endif
  2450. return -ENETUNREACH;
  2451. }
  2452. static struct cnic_dev *cnic_cm_select_dev(struct sockaddr_in *dst_addr,
  2453. int ulp_type)
  2454. {
  2455. struct cnic_dev *dev = NULL;
  2456. struct dst_entry *dst;
  2457. struct net_device *netdev = NULL;
  2458. int err = -ENETUNREACH;
  2459. if (dst_addr->sin_family == AF_INET)
  2460. err = cnic_get_v4_route(dst_addr, &dst);
  2461. else if (dst_addr->sin_family == AF_INET6) {
  2462. struct sockaddr_in6 *dst_addr6 =
  2463. (struct sockaddr_in6 *) dst_addr;
  2464. err = cnic_get_v6_route(dst_addr6, &dst);
  2465. } else
  2466. return NULL;
  2467. if (err)
  2468. return NULL;
  2469. if (!dst->dev)
  2470. goto done;
  2471. cnic_get_vlan(dst->dev, &netdev);
  2472. dev = cnic_from_netdev(netdev);
  2473. done:
  2474. dst_release(dst);
  2475. if (dev)
  2476. cnic_put(dev);
  2477. return dev;
  2478. }
  2479. static int cnic_resolve_addr(struct cnic_sock *csk, struct cnic_sockaddr *saddr)
  2480. {
  2481. struct cnic_dev *dev = csk->dev;
  2482. struct cnic_local *cp = dev->cnic_priv;
  2483. return cnic_send_nlmsg(cp, ISCSI_KEVENT_PATH_REQ, csk);
  2484. }
  2485. static int cnic_get_route(struct cnic_sock *csk, struct cnic_sockaddr *saddr)
  2486. {
  2487. struct cnic_dev *dev = csk->dev;
  2488. struct cnic_local *cp = dev->cnic_priv;
  2489. int is_v6, rc = 0;
  2490. struct dst_entry *dst = NULL;
  2491. struct net_device *realdev;
  2492. u32 local_port;
  2493. if (saddr->local.v6.sin6_family == AF_INET6 &&
  2494. saddr->remote.v6.sin6_family == AF_INET6)
  2495. is_v6 = 1;
  2496. else if (saddr->local.v4.sin_family == AF_INET &&
  2497. saddr->remote.v4.sin_family == AF_INET)
  2498. is_v6 = 0;
  2499. else
  2500. return -EINVAL;
  2501. clear_bit(SK_F_IPV6, &csk->flags);
  2502. if (is_v6) {
  2503. set_bit(SK_F_IPV6, &csk->flags);
  2504. cnic_get_v6_route(&saddr->remote.v6, &dst);
  2505. memcpy(&csk->dst_ip[0], &saddr->remote.v6.sin6_addr,
  2506. sizeof(struct in6_addr));
  2507. csk->dst_port = saddr->remote.v6.sin6_port;
  2508. local_port = saddr->local.v6.sin6_port;
  2509. } else {
  2510. cnic_get_v4_route(&saddr->remote.v4, &dst);
  2511. csk->dst_ip[0] = saddr->remote.v4.sin_addr.s_addr;
  2512. csk->dst_port = saddr->remote.v4.sin_port;
  2513. local_port = saddr->local.v4.sin_port;
  2514. }
  2515. csk->vlan_id = 0;
  2516. csk->mtu = dev->netdev->mtu;
  2517. if (dst && dst->dev) {
  2518. u16 vlan = cnic_get_vlan(dst->dev, &realdev);
  2519. if (realdev == dev->netdev) {
  2520. csk->vlan_id = vlan;
  2521. csk->mtu = dst_mtu(dst);
  2522. }
  2523. }
  2524. if (local_port >= CNIC_LOCAL_PORT_MIN &&
  2525. local_port < CNIC_LOCAL_PORT_MAX) {
  2526. if (cnic_alloc_id(&cp->csk_port_tbl, local_port))
  2527. local_port = 0;
  2528. } else
  2529. local_port = 0;
  2530. if (!local_port) {
  2531. local_port = cnic_alloc_new_id(&cp->csk_port_tbl);
  2532. if (local_port == -1) {
  2533. rc = -ENOMEM;
  2534. goto err_out;
  2535. }
  2536. }
  2537. csk->src_port = local_port;
  2538. err_out:
  2539. dst_release(dst);
  2540. return rc;
  2541. }
  2542. static void cnic_init_csk_state(struct cnic_sock *csk)
  2543. {
  2544. csk->state = 0;
  2545. clear_bit(SK_F_OFFLD_SCHED, &csk->flags);
  2546. clear_bit(SK_F_CLOSING, &csk->flags);
  2547. }
  2548. static int cnic_cm_connect(struct cnic_sock *csk, struct cnic_sockaddr *saddr)
  2549. {
  2550. int err = 0;
  2551. if (!cnic_in_use(csk))
  2552. return -EINVAL;
  2553. if (test_and_set_bit(SK_F_CONNECT_START, &csk->flags))
  2554. return -EINVAL;
  2555. cnic_init_csk_state(csk);
  2556. err = cnic_get_route(csk, saddr);
  2557. if (err)
  2558. goto err_out;
  2559. err = cnic_resolve_addr(csk, saddr);
  2560. if (!err)
  2561. return 0;
  2562. err_out:
  2563. clear_bit(SK_F_CONNECT_START, &csk->flags);
  2564. return err;
  2565. }
  2566. static int cnic_cm_abort(struct cnic_sock *csk)
  2567. {
  2568. struct cnic_local *cp = csk->dev->cnic_priv;
  2569. u32 opcode = L4_KCQE_OPCODE_VALUE_RESET_COMP;
  2570. if (!cnic_in_use(csk))
  2571. return -EINVAL;
  2572. if (cnic_abort_prep(csk))
  2573. return cnic_cm_abort_req(csk);
  2574. /* Getting here means that we haven't started connect, or
  2575. * connect was not successful.
  2576. */
  2577. cp->close_conn(csk, opcode);
  2578. if (csk->state != opcode)
  2579. return -EALREADY;
  2580. return 0;
  2581. }
  2582. static int cnic_cm_close(struct cnic_sock *csk)
  2583. {
  2584. if (!cnic_in_use(csk))
  2585. return -EINVAL;
  2586. if (cnic_close_prep(csk)) {
  2587. csk->state = L4_KCQE_OPCODE_VALUE_CLOSE_COMP;
  2588. return cnic_cm_close_req(csk);
  2589. } else {
  2590. return -EALREADY;
  2591. }
  2592. return 0;
  2593. }
  2594. static void cnic_cm_upcall(struct cnic_local *cp, struct cnic_sock *csk,
  2595. u8 opcode)
  2596. {
  2597. struct cnic_ulp_ops *ulp_ops;
  2598. int ulp_type = csk->ulp_type;
  2599. rcu_read_lock();
  2600. ulp_ops = rcu_dereference(cp->ulp_ops[ulp_type]);
  2601. if (ulp_ops) {
  2602. if (opcode == L4_KCQE_OPCODE_VALUE_CONNECT_COMPLETE)
  2603. ulp_ops->cm_connect_complete(csk);
  2604. else if (opcode == L4_KCQE_OPCODE_VALUE_CLOSE_COMP)
  2605. ulp_ops->cm_close_complete(csk);
  2606. else if (opcode == L4_KCQE_OPCODE_VALUE_RESET_RECEIVED)
  2607. ulp_ops->cm_remote_abort(csk);
  2608. else if (opcode == L4_KCQE_OPCODE_VALUE_RESET_COMP)
  2609. ulp_ops->cm_abort_complete(csk);
  2610. else if (opcode == L4_KCQE_OPCODE_VALUE_CLOSE_RECEIVED)
  2611. ulp_ops->cm_remote_close(csk);
  2612. }
  2613. rcu_read_unlock();
  2614. }
  2615. static int cnic_cm_set_pg(struct cnic_sock *csk)
  2616. {
  2617. if (cnic_offld_prep(csk)) {
  2618. if (test_bit(SK_F_PG_OFFLD_COMPLETE, &csk->flags))
  2619. cnic_cm_update_pg(csk);
  2620. else
  2621. cnic_cm_offload_pg(csk);
  2622. }
  2623. return 0;
  2624. }
  2625. static void cnic_cm_process_offld_pg(struct cnic_dev *dev, struct l4_kcq *kcqe)
  2626. {
  2627. struct cnic_local *cp = dev->cnic_priv;
  2628. u32 l5_cid = kcqe->pg_host_opaque;
  2629. u8 opcode = kcqe->op_code;
  2630. struct cnic_sock *csk = &cp->csk_tbl[l5_cid];
  2631. csk_hold(csk);
  2632. if (!cnic_in_use(csk))
  2633. goto done;
  2634. if (opcode == L4_KCQE_OPCODE_VALUE_UPDATE_PG) {
  2635. clear_bit(SK_F_OFFLD_SCHED, &csk->flags);
  2636. goto done;
  2637. }
  2638. /* Possible PG kcqe status: SUCCESS, OFFLOADED_PG, or CTX_ALLOC_FAIL */
  2639. if (kcqe->status == L4_KCQE_COMPLETION_STATUS_CTX_ALLOC_FAIL) {
  2640. clear_bit(SK_F_OFFLD_SCHED, &csk->flags);
  2641. cnic_cm_upcall(cp, csk,
  2642. L4_KCQE_OPCODE_VALUE_CONNECT_COMPLETE);
  2643. goto done;
  2644. }
  2645. csk->pg_cid = kcqe->pg_cid;
  2646. set_bit(SK_F_PG_OFFLD_COMPLETE, &csk->flags);
  2647. cnic_cm_conn_req(csk);
  2648. done:
  2649. csk_put(csk);
  2650. }
  2651. static void cnic_cm_process_kcqe(struct cnic_dev *dev, struct kcqe *kcqe)
  2652. {
  2653. struct cnic_local *cp = dev->cnic_priv;
  2654. struct l4_kcq *l4kcqe = (struct l4_kcq *) kcqe;
  2655. u8 opcode = l4kcqe->op_code;
  2656. u32 l5_cid;
  2657. struct cnic_sock *csk;
  2658. if (opcode == L4_KCQE_OPCODE_VALUE_OFFLOAD_PG ||
  2659. opcode == L4_KCQE_OPCODE_VALUE_UPDATE_PG) {
  2660. cnic_cm_process_offld_pg(dev, l4kcqe);
  2661. return;
  2662. }
  2663. l5_cid = l4kcqe->conn_id;
  2664. if (opcode & 0x80)
  2665. l5_cid = l4kcqe->cid;
  2666. if (l5_cid >= MAX_CM_SK_TBL_SZ)
  2667. return;
  2668. csk = &cp->csk_tbl[l5_cid];
  2669. csk_hold(csk);
  2670. if (!cnic_in_use(csk)) {
  2671. csk_put(csk);
  2672. return;
  2673. }
  2674. switch (opcode) {
  2675. case L5CM_RAMROD_CMD_ID_TCP_CONNECT:
  2676. if (l4kcqe->status != 0) {
  2677. clear_bit(SK_F_OFFLD_SCHED, &csk->flags);
  2678. cnic_cm_upcall(cp, csk,
  2679. L4_KCQE_OPCODE_VALUE_CONNECT_COMPLETE);
  2680. }
  2681. break;
  2682. case L4_KCQE_OPCODE_VALUE_CONNECT_COMPLETE:
  2683. if (l4kcqe->status == 0)
  2684. set_bit(SK_F_OFFLD_COMPLETE, &csk->flags);
  2685. smp_mb__before_clear_bit();
  2686. clear_bit(SK_F_OFFLD_SCHED, &csk->flags);
  2687. cnic_cm_upcall(cp, csk, opcode);
  2688. break;
  2689. case L4_KCQE_OPCODE_VALUE_RESET_RECEIVED:
  2690. case L4_KCQE_OPCODE_VALUE_CLOSE_COMP:
  2691. case L4_KCQE_OPCODE_VALUE_RESET_COMP:
  2692. case L5CM_RAMROD_CMD_ID_SEARCHER_DELETE:
  2693. case L5CM_RAMROD_CMD_ID_TERMINATE_OFFLOAD:
  2694. cp->close_conn(csk, opcode);
  2695. break;
  2696. case L4_KCQE_OPCODE_VALUE_CLOSE_RECEIVED:
  2697. cnic_cm_upcall(cp, csk, opcode);
  2698. break;
  2699. }
  2700. csk_put(csk);
  2701. }
  2702. static void cnic_cm_indicate_kcqe(void *data, struct kcqe *kcqe[], u32 num)
  2703. {
  2704. struct cnic_dev *dev = data;
  2705. int i;
  2706. for (i = 0; i < num; i++)
  2707. cnic_cm_process_kcqe(dev, kcqe[i]);
  2708. }
  2709. static struct cnic_ulp_ops cm_ulp_ops = {
  2710. .indicate_kcqes = cnic_cm_indicate_kcqe,
  2711. };
  2712. static void cnic_cm_free_mem(struct cnic_dev *dev)
  2713. {
  2714. struct cnic_local *cp = dev->cnic_priv;
  2715. kfree(cp->csk_tbl);
  2716. cp->csk_tbl = NULL;
  2717. cnic_free_id_tbl(&cp->csk_port_tbl);
  2718. }
  2719. static int cnic_cm_alloc_mem(struct cnic_dev *dev)
  2720. {
  2721. struct cnic_local *cp = dev->cnic_priv;
  2722. cp->csk_tbl = kzalloc(sizeof(struct cnic_sock) * MAX_CM_SK_TBL_SZ,
  2723. GFP_KERNEL);
  2724. if (!cp->csk_tbl)
  2725. return -ENOMEM;
  2726. if (cnic_init_id_tbl(&cp->csk_port_tbl, CNIC_LOCAL_PORT_RANGE,
  2727. CNIC_LOCAL_PORT_MIN)) {
  2728. cnic_cm_free_mem(dev);
  2729. return -ENOMEM;
  2730. }
  2731. return 0;
  2732. }
  2733. static int cnic_ready_to_close(struct cnic_sock *csk, u32 opcode)
  2734. {
  2735. if (test_and_clear_bit(SK_F_OFFLD_COMPLETE, &csk->flags)) {
  2736. /* Unsolicited RESET_COMP or RESET_RECEIVED */
  2737. opcode = L4_KCQE_OPCODE_VALUE_RESET_RECEIVED;
  2738. csk->state = opcode;
  2739. }
  2740. /* 1. If event opcode matches the expected event in csk->state
  2741. * 2. If the expected event is CLOSE_COMP, we accept any event
  2742. * 3. If the expected event is 0, meaning the connection was never
  2743. * never established, we accept the opcode from cm_abort.
  2744. */
  2745. if (opcode == csk->state || csk->state == 0 ||
  2746. csk->state == L4_KCQE_OPCODE_VALUE_CLOSE_COMP) {
  2747. if (!test_and_set_bit(SK_F_CLOSING, &csk->flags)) {
  2748. if (csk->state == 0)
  2749. csk->state = opcode;
  2750. return 1;
  2751. }
  2752. }
  2753. return 0;
  2754. }
  2755. static void cnic_close_bnx2_conn(struct cnic_sock *csk, u32 opcode)
  2756. {
  2757. struct cnic_dev *dev = csk->dev;
  2758. struct cnic_local *cp = dev->cnic_priv;
  2759. if (opcode == L4_KCQE_OPCODE_VALUE_RESET_RECEIVED) {
  2760. cnic_cm_upcall(cp, csk, opcode);
  2761. return;
  2762. }
  2763. clear_bit(SK_F_CONNECT_START, &csk->flags);
  2764. cnic_close_conn(csk);
  2765. csk->state = opcode;
  2766. cnic_cm_upcall(cp, csk, opcode);
  2767. }
  2768. static void cnic_cm_stop_bnx2_hw(struct cnic_dev *dev)
  2769. {
  2770. }
  2771. static int cnic_cm_init_bnx2_hw(struct cnic_dev *dev)
  2772. {
  2773. u32 seed;
  2774. get_random_bytes(&seed, 4);
  2775. cnic_ctx_wr(dev, 45, 0, seed);
  2776. return 0;
  2777. }
  2778. static void cnic_close_bnx2x_conn(struct cnic_sock *csk, u32 opcode)
  2779. {
  2780. struct cnic_dev *dev = csk->dev;
  2781. struct cnic_local *cp = dev->cnic_priv;
  2782. struct cnic_context *ctx = &cp->ctx_tbl[csk->l5_cid];
  2783. union l5cm_specific_data l5_data;
  2784. u32 cmd = 0;
  2785. int close_complete = 0;
  2786. switch (opcode) {
  2787. case L4_KCQE_OPCODE_VALUE_RESET_RECEIVED:
  2788. case L4_KCQE_OPCODE_VALUE_CLOSE_COMP:
  2789. case L4_KCQE_OPCODE_VALUE_RESET_COMP:
  2790. if (cnic_ready_to_close(csk, opcode)) {
  2791. if (test_bit(SK_F_PG_OFFLD_COMPLETE, &csk->flags))
  2792. cmd = L5CM_RAMROD_CMD_ID_SEARCHER_DELETE;
  2793. else
  2794. close_complete = 1;
  2795. }
  2796. break;
  2797. case L5CM_RAMROD_CMD_ID_SEARCHER_DELETE:
  2798. cmd = L5CM_RAMROD_CMD_ID_TERMINATE_OFFLOAD;
  2799. break;
  2800. case L5CM_RAMROD_CMD_ID_TERMINATE_OFFLOAD:
  2801. close_complete = 1;
  2802. break;
  2803. }
  2804. if (cmd) {
  2805. memset(&l5_data, 0, sizeof(l5_data));
  2806. cnic_submit_kwqe_16(dev, cmd, csk->cid, ISCSI_CONNECTION_TYPE,
  2807. &l5_data);
  2808. } else if (close_complete) {
  2809. ctx->timestamp = jiffies;
  2810. cnic_close_conn(csk);
  2811. cnic_cm_upcall(cp, csk, csk->state);
  2812. }
  2813. }
  2814. static void cnic_cm_stop_bnx2x_hw(struct cnic_dev *dev)
  2815. {
  2816. struct cnic_local *cp = dev->cnic_priv;
  2817. int i;
  2818. if (!cp->ctx_tbl)
  2819. return;
  2820. if (!netif_running(dev->netdev))
  2821. return;
  2822. for (i = 0; i < cp->max_cid_space; i++) {
  2823. struct cnic_context *ctx = &cp->ctx_tbl[i];
  2824. while (test_bit(CTX_FL_DELETE_WAIT, &ctx->ctx_flags))
  2825. msleep(10);
  2826. if (test_bit(CTX_FL_OFFLD_START, &ctx->ctx_flags))
  2827. netdev_warn(dev->netdev, "CID %x not deleted\n",
  2828. ctx->cid);
  2829. }
  2830. cancel_delayed_work(&cp->delete_task);
  2831. flush_workqueue(cnic_wq);
  2832. if (atomic_read(&cp->iscsi_conn) != 0)
  2833. netdev_warn(dev->netdev, "%d iSCSI connections not destroyed\n",
  2834. atomic_read(&cp->iscsi_conn));
  2835. }
  2836. static int cnic_cm_init_bnx2x_hw(struct cnic_dev *dev)
  2837. {
  2838. struct cnic_local *cp = dev->cnic_priv;
  2839. u32 pfid = cp->pfid;
  2840. u32 port = CNIC_PORT(cp);
  2841. cnic_init_bnx2x_mac(dev);
  2842. cnic_bnx2x_set_tcp_timestamp(dev, 1);
  2843. CNIC_WR16(dev, BAR_XSTRORM_INTMEM +
  2844. XSTORM_ISCSI_LOCAL_VLAN_OFFSET(pfid), 0);
  2845. CNIC_WR(dev, BAR_XSTRORM_INTMEM +
  2846. XSTORM_TCP_GLOBAL_DEL_ACK_COUNTER_ENABLED_OFFSET(port), 1);
  2847. CNIC_WR(dev, BAR_XSTRORM_INTMEM +
  2848. XSTORM_TCP_GLOBAL_DEL_ACK_COUNTER_MAX_COUNT_OFFSET(port),
  2849. DEF_MAX_DA_COUNT);
  2850. CNIC_WR8(dev, BAR_XSTRORM_INTMEM +
  2851. XSTORM_ISCSI_TCP_VARS_TTL_OFFSET(pfid), DEF_TTL);
  2852. CNIC_WR8(dev, BAR_XSTRORM_INTMEM +
  2853. XSTORM_ISCSI_TCP_VARS_TOS_OFFSET(pfid), DEF_TOS);
  2854. CNIC_WR8(dev, BAR_XSTRORM_INTMEM +
  2855. XSTORM_ISCSI_TCP_VARS_ADV_WND_SCL_OFFSET(pfid), 2);
  2856. CNIC_WR(dev, BAR_XSTRORM_INTMEM +
  2857. XSTORM_TCP_TX_SWS_TIMER_VAL_OFFSET(pfid), DEF_SWS_TIMER);
  2858. CNIC_WR(dev, BAR_TSTRORM_INTMEM + TSTORM_TCP_MAX_CWND_OFFSET(pfid),
  2859. DEF_MAX_CWND);
  2860. return 0;
  2861. }
  2862. static void cnic_delete_task(struct work_struct *work)
  2863. {
  2864. struct cnic_local *cp;
  2865. struct cnic_dev *dev;
  2866. u32 i;
  2867. int need_resched = 0;
  2868. cp = container_of(work, struct cnic_local, delete_task.work);
  2869. dev = cp->dev;
  2870. for (i = 0; i < cp->max_cid_space; i++) {
  2871. struct cnic_context *ctx = &cp->ctx_tbl[i];
  2872. if (!test_bit(CTX_FL_OFFLD_START, &ctx->ctx_flags) ||
  2873. !test_bit(CTX_FL_DELETE_WAIT, &ctx->ctx_flags))
  2874. continue;
  2875. if (!time_after(jiffies, ctx->timestamp + (2 * HZ))) {
  2876. need_resched = 1;
  2877. continue;
  2878. }
  2879. if (!test_and_clear_bit(CTX_FL_DELETE_WAIT, &ctx->ctx_flags))
  2880. continue;
  2881. cnic_bnx2x_destroy_ramrod(dev, i);
  2882. cnic_free_bnx2x_conn_resc(dev, i);
  2883. if (ctx->ulp_proto_id == CNIC_ULP_ISCSI)
  2884. atomic_dec(&cp->iscsi_conn);
  2885. clear_bit(CTX_FL_OFFLD_START, &ctx->ctx_flags);
  2886. }
  2887. if (need_resched)
  2888. queue_delayed_work(cnic_wq, &cp->delete_task,
  2889. msecs_to_jiffies(10));
  2890. }
  2891. static int cnic_cm_open(struct cnic_dev *dev)
  2892. {
  2893. struct cnic_local *cp = dev->cnic_priv;
  2894. int err;
  2895. err = cnic_cm_alloc_mem(dev);
  2896. if (err)
  2897. return err;
  2898. err = cp->start_cm(dev);
  2899. if (err)
  2900. goto err_out;
  2901. INIT_DELAYED_WORK(&cp->delete_task, cnic_delete_task);
  2902. dev->cm_create = cnic_cm_create;
  2903. dev->cm_destroy = cnic_cm_destroy;
  2904. dev->cm_connect = cnic_cm_connect;
  2905. dev->cm_abort = cnic_cm_abort;
  2906. dev->cm_close = cnic_cm_close;
  2907. dev->cm_select_dev = cnic_cm_select_dev;
  2908. cp->ulp_handle[CNIC_ULP_L4] = dev;
  2909. rcu_assign_pointer(cp->ulp_ops[CNIC_ULP_L4], &cm_ulp_ops);
  2910. return 0;
  2911. err_out:
  2912. cnic_cm_free_mem(dev);
  2913. return err;
  2914. }
  2915. static int cnic_cm_shutdown(struct cnic_dev *dev)
  2916. {
  2917. struct cnic_local *cp = dev->cnic_priv;
  2918. int i;
  2919. cp->stop_cm(dev);
  2920. if (!cp->csk_tbl)
  2921. return 0;
  2922. for (i = 0; i < MAX_CM_SK_TBL_SZ; i++) {
  2923. struct cnic_sock *csk = &cp->csk_tbl[i];
  2924. clear_bit(SK_F_INUSE, &csk->flags);
  2925. cnic_cm_cleanup(csk);
  2926. }
  2927. cnic_cm_free_mem(dev);
  2928. return 0;
  2929. }
  2930. static void cnic_init_context(struct cnic_dev *dev, u32 cid)
  2931. {
  2932. u32 cid_addr;
  2933. int i;
  2934. cid_addr = GET_CID_ADDR(cid);
  2935. for (i = 0; i < CTX_SIZE; i += 4)
  2936. cnic_ctx_wr(dev, cid_addr, i, 0);
  2937. }
  2938. static int cnic_setup_5709_context(struct cnic_dev *dev, int valid)
  2939. {
  2940. struct cnic_local *cp = dev->cnic_priv;
  2941. int ret = 0, i;
  2942. u32 valid_bit = valid ? BNX2_CTX_HOST_PAGE_TBL_DATA0_VALID : 0;
  2943. if (CHIP_NUM(cp) != CHIP_NUM_5709)
  2944. return 0;
  2945. for (i = 0; i < cp->ctx_blks; i++) {
  2946. int j;
  2947. u32 idx = cp->ctx_arr[i].cid / cp->cids_per_blk;
  2948. u32 val;
  2949. memset(cp->ctx_arr[i].ctx, 0, BCM_PAGE_SIZE);
  2950. CNIC_WR(dev, BNX2_CTX_HOST_PAGE_TBL_DATA0,
  2951. (cp->ctx_arr[i].mapping & 0xffffffff) | valid_bit);
  2952. CNIC_WR(dev, BNX2_CTX_HOST_PAGE_TBL_DATA1,
  2953. (u64) cp->ctx_arr[i].mapping >> 32);
  2954. CNIC_WR(dev, BNX2_CTX_HOST_PAGE_TBL_CTRL, idx |
  2955. BNX2_CTX_HOST_PAGE_TBL_CTRL_WRITE_REQ);
  2956. for (j = 0; j < 10; j++) {
  2957. val = CNIC_RD(dev, BNX2_CTX_HOST_PAGE_TBL_CTRL);
  2958. if (!(val & BNX2_CTX_HOST_PAGE_TBL_CTRL_WRITE_REQ))
  2959. break;
  2960. udelay(5);
  2961. }
  2962. if (val & BNX2_CTX_HOST_PAGE_TBL_CTRL_WRITE_REQ) {
  2963. ret = -EBUSY;
  2964. break;
  2965. }
  2966. }
  2967. return ret;
  2968. }
  2969. static void cnic_free_irq(struct cnic_dev *dev)
  2970. {
  2971. struct cnic_local *cp = dev->cnic_priv;
  2972. struct cnic_eth_dev *ethdev = cp->ethdev;
  2973. if (ethdev->drv_state & CNIC_DRV_STATE_USING_MSIX) {
  2974. cp->disable_int_sync(dev);
  2975. tasklet_kill(&cp->cnic_irq_task);
  2976. free_irq(ethdev->irq_arr[0].vector, dev);
  2977. }
  2978. }
  2979. static int cnic_request_irq(struct cnic_dev *dev)
  2980. {
  2981. struct cnic_local *cp = dev->cnic_priv;
  2982. struct cnic_eth_dev *ethdev = cp->ethdev;
  2983. int err;
  2984. err = request_irq(ethdev->irq_arr[0].vector, cnic_irq, 0, "cnic", dev);
  2985. if (err)
  2986. tasklet_disable(&cp->cnic_irq_task);
  2987. return err;
  2988. }
  2989. static int cnic_init_bnx2_irq(struct cnic_dev *dev)
  2990. {
  2991. struct cnic_local *cp = dev->cnic_priv;
  2992. struct cnic_eth_dev *ethdev = cp->ethdev;
  2993. if (ethdev->drv_state & CNIC_DRV_STATE_USING_MSIX) {
  2994. int err, i = 0;
  2995. int sblk_num = cp->status_blk_num;
  2996. u32 base = ((sblk_num - 1) * BNX2_HC_SB_CONFIG_SIZE) +
  2997. BNX2_HC_SB_CONFIG_1;
  2998. CNIC_WR(dev, base, BNX2_HC_SB_CONFIG_1_ONE_SHOT);
  2999. CNIC_WR(dev, base + BNX2_HC_COMP_PROD_TRIP_OFF, (2 << 16) | 8);
  3000. CNIC_WR(dev, base + BNX2_HC_COM_TICKS_OFF, (64 << 16) | 220);
  3001. CNIC_WR(dev, base + BNX2_HC_CMD_TICKS_OFF, (64 << 16) | 220);
  3002. cp->last_status_idx = cp->status_blk.bnx2->status_idx;
  3003. tasklet_init(&cp->cnic_irq_task, cnic_service_bnx2_msix,
  3004. (unsigned long) dev);
  3005. err = cnic_request_irq(dev);
  3006. if (err)
  3007. return err;
  3008. while (cp->status_blk.bnx2->status_completion_producer_index &&
  3009. i < 10) {
  3010. CNIC_WR(dev, BNX2_HC_COALESCE_NOW,
  3011. 1 << (11 + sblk_num));
  3012. udelay(10);
  3013. i++;
  3014. barrier();
  3015. }
  3016. if (cp->status_blk.bnx2->status_completion_producer_index) {
  3017. cnic_free_irq(dev);
  3018. goto failed;
  3019. }
  3020. } else {
  3021. struct status_block *sblk = cp->status_blk.gen;
  3022. u32 hc_cmd = CNIC_RD(dev, BNX2_HC_COMMAND);
  3023. int i = 0;
  3024. while (sblk->status_completion_producer_index && i < 10) {
  3025. CNIC_WR(dev, BNX2_HC_COMMAND,
  3026. hc_cmd | BNX2_HC_COMMAND_COAL_NOW_WO_INT);
  3027. udelay(10);
  3028. i++;
  3029. barrier();
  3030. }
  3031. if (sblk->status_completion_producer_index)
  3032. goto failed;
  3033. }
  3034. return 0;
  3035. failed:
  3036. netdev_err(dev->netdev, "KCQ index not resetting to 0\n");
  3037. return -EBUSY;
  3038. }
  3039. static void cnic_enable_bnx2_int(struct cnic_dev *dev)
  3040. {
  3041. struct cnic_local *cp = dev->cnic_priv;
  3042. struct cnic_eth_dev *ethdev = cp->ethdev;
  3043. if (!(ethdev->drv_state & CNIC_DRV_STATE_USING_MSIX))
  3044. return;
  3045. CNIC_WR(dev, BNX2_PCICFG_INT_ACK_CMD, cp->int_num |
  3046. BNX2_PCICFG_INT_ACK_CMD_INDEX_VALID | cp->last_status_idx);
  3047. }
  3048. static void cnic_disable_bnx2_int_sync(struct cnic_dev *dev)
  3049. {
  3050. struct cnic_local *cp = dev->cnic_priv;
  3051. struct cnic_eth_dev *ethdev = cp->ethdev;
  3052. if (!(ethdev->drv_state & CNIC_DRV_STATE_USING_MSIX))
  3053. return;
  3054. CNIC_WR(dev, BNX2_PCICFG_INT_ACK_CMD, cp->int_num |
  3055. BNX2_PCICFG_INT_ACK_CMD_MASK_INT);
  3056. CNIC_RD(dev, BNX2_PCICFG_INT_ACK_CMD);
  3057. synchronize_irq(ethdev->irq_arr[0].vector);
  3058. }
  3059. static void cnic_init_bnx2_tx_ring(struct cnic_dev *dev)
  3060. {
  3061. struct cnic_local *cp = dev->cnic_priv;
  3062. struct cnic_eth_dev *ethdev = cp->ethdev;
  3063. struct cnic_uio_dev *udev = cp->udev;
  3064. u32 cid_addr, tx_cid, sb_id;
  3065. u32 val, offset0, offset1, offset2, offset3;
  3066. int i;
  3067. struct tx_bd *txbd;
  3068. dma_addr_t buf_map, ring_map = udev->l2_ring_map;
  3069. struct status_block *s_blk = cp->status_blk.gen;
  3070. sb_id = cp->status_blk_num;
  3071. tx_cid = 20;
  3072. cp->tx_cons_ptr = &s_blk->status_tx_quick_consumer_index2;
  3073. if (ethdev->drv_state & CNIC_DRV_STATE_USING_MSIX) {
  3074. struct status_block_msix *sblk = cp->status_blk.bnx2;
  3075. tx_cid = TX_TSS_CID + sb_id - 1;
  3076. CNIC_WR(dev, BNX2_TSCH_TSS_CFG, (sb_id << 24) |
  3077. (TX_TSS_CID << 7));
  3078. cp->tx_cons_ptr = &sblk->status_tx_quick_consumer_index;
  3079. }
  3080. cp->tx_cons = *cp->tx_cons_ptr;
  3081. cid_addr = GET_CID_ADDR(tx_cid);
  3082. if (CHIP_NUM(cp) == CHIP_NUM_5709) {
  3083. u32 cid_addr2 = GET_CID_ADDR(tx_cid + 4) + 0x40;
  3084. for (i = 0; i < PHY_CTX_SIZE; i += 4)
  3085. cnic_ctx_wr(dev, cid_addr2, i, 0);
  3086. offset0 = BNX2_L2CTX_TYPE_XI;
  3087. offset1 = BNX2_L2CTX_CMD_TYPE_XI;
  3088. offset2 = BNX2_L2CTX_TBDR_BHADDR_HI_XI;
  3089. offset3 = BNX2_L2CTX_TBDR_BHADDR_LO_XI;
  3090. } else {
  3091. cnic_init_context(dev, tx_cid);
  3092. cnic_init_context(dev, tx_cid + 1);
  3093. offset0 = BNX2_L2CTX_TYPE;
  3094. offset1 = BNX2_L2CTX_CMD_TYPE;
  3095. offset2 = BNX2_L2CTX_TBDR_BHADDR_HI;
  3096. offset3 = BNX2_L2CTX_TBDR_BHADDR_LO;
  3097. }
  3098. val = BNX2_L2CTX_TYPE_TYPE_L2 | BNX2_L2CTX_TYPE_SIZE_L2;
  3099. cnic_ctx_wr(dev, cid_addr, offset0, val);
  3100. val = BNX2_L2CTX_CMD_TYPE_TYPE_L2 | (8 << 16);
  3101. cnic_ctx_wr(dev, cid_addr, offset1, val);
  3102. txbd = (struct tx_bd *) udev->l2_ring;
  3103. buf_map = udev->l2_buf_map;
  3104. for (i = 0; i < MAX_TX_DESC_CNT; i++, txbd++) {
  3105. txbd->tx_bd_haddr_hi = (u64) buf_map >> 32;
  3106. txbd->tx_bd_haddr_lo = (u64) buf_map & 0xffffffff;
  3107. }
  3108. val = (u64) ring_map >> 32;
  3109. cnic_ctx_wr(dev, cid_addr, offset2, val);
  3110. txbd->tx_bd_haddr_hi = val;
  3111. val = (u64) ring_map & 0xffffffff;
  3112. cnic_ctx_wr(dev, cid_addr, offset3, val);
  3113. txbd->tx_bd_haddr_lo = val;
  3114. }
  3115. static void cnic_init_bnx2_rx_ring(struct cnic_dev *dev)
  3116. {
  3117. struct cnic_local *cp = dev->cnic_priv;
  3118. struct cnic_eth_dev *ethdev = cp->ethdev;
  3119. struct cnic_uio_dev *udev = cp->udev;
  3120. u32 cid_addr, sb_id, val, coal_reg, coal_val;
  3121. int i;
  3122. struct rx_bd *rxbd;
  3123. struct status_block *s_blk = cp->status_blk.gen;
  3124. dma_addr_t ring_map = udev->l2_ring_map;
  3125. sb_id = cp->status_blk_num;
  3126. cnic_init_context(dev, 2);
  3127. cp->rx_cons_ptr = &s_blk->status_rx_quick_consumer_index2;
  3128. coal_reg = BNX2_HC_COMMAND;
  3129. coal_val = CNIC_RD(dev, coal_reg);
  3130. if (ethdev->drv_state & CNIC_DRV_STATE_USING_MSIX) {
  3131. struct status_block_msix *sblk = cp->status_blk.bnx2;
  3132. cp->rx_cons_ptr = &sblk->status_rx_quick_consumer_index;
  3133. coal_reg = BNX2_HC_COALESCE_NOW;
  3134. coal_val = 1 << (11 + sb_id);
  3135. }
  3136. i = 0;
  3137. while (!(*cp->rx_cons_ptr != 0) && i < 10) {
  3138. CNIC_WR(dev, coal_reg, coal_val);
  3139. udelay(10);
  3140. i++;
  3141. barrier();
  3142. }
  3143. cp->rx_cons = *cp->rx_cons_ptr;
  3144. cid_addr = GET_CID_ADDR(2);
  3145. val = BNX2_L2CTX_CTX_TYPE_CTX_BD_CHN_TYPE_VALUE |
  3146. BNX2_L2CTX_CTX_TYPE_SIZE_L2 | (0x02 << 8);
  3147. cnic_ctx_wr(dev, cid_addr, BNX2_L2CTX_CTX_TYPE, val);
  3148. if (sb_id == 0)
  3149. val = 2 << BNX2_L2CTX_L2_STATUSB_NUM_SHIFT;
  3150. else
  3151. val = BNX2_L2CTX_L2_STATUSB_NUM(sb_id);
  3152. cnic_ctx_wr(dev, cid_addr, BNX2_L2CTX_HOST_BDIDX, val);
  3153. rxbd = (struct rx_bd *) (udev->l2_ring + BCM_PAGE_SIZE);
  3154. for (i = 0; i < MAX_RX_DESC_CNT; i++, rxbd++) {
  3155. dma_addr_t buf_map;
  3156. int n = (i % cp->l2_rx_ring_size) + 1;
  3157. buf_map = udev->l2_buf_map + (n * cp->l2_single_buf_size);
  3158. rxbd->rx_bd_len = cp->l2_single_buf_size;
  3159. rxbd->rx_bd_flags = RX_BD_FLAGS_START | RX_BD_FLAGS_END;
  3160. rxbd->rx_bd_haddr_hi = (u64) buf_map >> 32;
  3161. rxbd->rx_bd_haddr_lo = (u64) buf_map & 0xffffffff;
  3162. }
  3163. val = (u64) (ring_map + BCM_PAGE_SIZE) >> 32;
  3164. cnic_ctx_wr(dev, cid_addr, BNX2_L2CTX_NX_BDHADDR_HI, val);
  3165. rxbd->rx_bd_haddr_hi = val;
  3166. val = (u64) (ring_map + BCM_PAGE_SIZE) & 0xffffffff;
  3167. cnic_ctx_wr(dev, cid_addr, BNX2_L2CTX_NX_BDHADDR_LO, val);
  3168. rxbd->rx_bd_haddr_lo = val;
  3169. val = cnic_reg_rd_ind(dev, BNX2_RXP_SCRATCH_RXP_FLOOD);
  3170. cnic_reg_wr_ind(dev, BNX2_RXP_SCRATCH_RXP_FLOOD, val | (1 << 2));
  3171. }
  3172. static void cnic_shutdown_bnx2_rx_ring(struct cnic_dev *dev)
  3173. {
  3174. struct kwqe *wqes[1], l2kwqe;
  3175. memset(&l2kwqe, 0, sizeof(l2kwqe));
  3176. wqes[0] = &l2kwqe;
  3177. l2kwqe.kwqe_op_flag = (L2_LAYER_CODE << KWQE_FLAGS_LAYER_SHIFT) |
  3178. (L2_KWQE_OPCODE_VALUE_FLUSH <<
  3179. KWQE_OPCODE_SHIFT) | 2;
  3180. dev->submit_kwqes(dev, wqes, 1);
  3181. }
  3182. static void cnic_set_bnx2_mac(struct cnic_dev *dev)
  3183. {
  3184. struct cnic_local *cp = dev->cnic_priv;
  3185. u32 val;
  3186. val = cp->func << 2;
  3187. cp->shmem_base = cnic_reg_rd_ind(dev, BNX2_SHM_HDR_ADDR_0 + val);
  3188. val = cnic_reg_rd_ind(dev, cp->shmem_base +
  3189. BNX2_PORT_HW_CFG_ISCSI_MAC_UPPER);
  3190. dev->mac_addr[0] = (u8) (val >> 8);
  3191. dev->mac_addr[1] = (u8) val;
  3192. CNIC_WR(dev, BNX2_EMAC_MAC_MATCH4, val);
  3193. val = cnic_reg_rd_ind(dev, cp->shmem_base +
  3194. BNX2_PORT_HW_CFG_ISCSI_MAC_LOWER);
  3195. dev->mac_addr[2] = (u8) (val >> 24);
  3196. dev->mac_addr[3] = (u8) (val >> 16);
  3197. dev->mac_addr[4] = (u8) (val >> 8);
  3198. dev->mac_addr[5] = (u8) val;
  3199. CNIC_WR(dev, BNX2_EMAC_MAC_MATCH5, val);
  3200. val = 4 | BNX2_RPM_SORT_USER2_BC_EN;
  3201. if (CHIP_NUM(cp) != CHIP_NUM_5709)
  3202. val |= BNX2_RPM_SORT_USER2_PROM_VLAN;
  3203. CNIC_WR(dev, BNX2_RPM_SORT_USER2, 0x0);
  3204. CNIC_WR(dev, BNX2_RPM_SORT_USER2, val);
  3205. CNIC_WR(dev, BNX2_RPM_SORT_USER2, val | BNX2_RPM_SORT_USER2_ENA);
  3206. }
  3207. static int cnic_start_bnx2_hw(struct cnic_dev *dev)
  3208. {
  3209. struct cnic_local *cp = dev->cnic_priv;
  3210. struct cnic_eth_dev *ethdev = cp->ethdev;
  3211. struct status_block *sblk = cp->status_blk.gen;
  3212. u32 val, kcq_cid_addr, kwq_cid_addr;
  3213. int err;
  3214. cnic_set_bnx2_mac(dev);
  3215. val = CNIC_RD(dev, BNX2_MQ_CONFIG);
  3216. val &= ~BNX2_MQ_CONFIG_KNL_BYP_BLK_SIZE;
  3217. if (BCM_PAGE_BITS > 12)
  3218. val |= (12 - 8) << 4;
  3219. else
  3220. val |= (BCM_PAGE_BITS - 8) << 4;
  3221. CNIC_WR(dev, BNX2_MQ_CONFIG, val);
  3222. CNIC_WR(dev, BNX2_HC_COMP_PROD_TRIP, (2 << 16) | 8);
  3223. CNIC_WR(dev, BNX2_HC_COM_TICKS, (64 << 16) | 220);
  3224. CNIC_WR(dev, BNX2_HC_CMD_TICKS, (64 << 16) | 220);
  3225. err = cnic_setup_5709_context(dev, 1);
  3226. if (err)
  3227. return err;
  3228. cnic_init_context(dev, KWQ_CID);
  3229. cnic_init_context(dev, KCQ_CID);
  3230. kwq_cid_addr = GET_CID_ADDR(KWQ_CID);
  3231. cp->kwq_io_addr = MB_GET_CID_ADDR(KWQ_CID) + L5_KRNLQ_HOST_QIDX;
  3232. cp->max_kwq_idx = MAX_KWQ_IDX;
  3233. cp->kwq_prod_idx = 0;
  3234. cp->kwq_con_idx = 0;
  3235. set_bit(CNIC_LCL_FL_KWQ_INIT, &cp->cnic_local_flags);
  3236. if (CHIP_NUM(cp) == CHIP_NUM_5706 || CHIP_NUM(cp) == CHIP_NUM_5708)
  3237. cp->kwq_con_idx_ptr = &sblk->status_rx_quick_consumer_index15;
  3238. else
  3239. cp->kwq_con_idx_ptr = &sblk->status_cmd_consumer_index;
  3240. /* Initialize the kernel work queue context. */
  3241. val = KRNLQ_TYPE_TYPE_KRNLQ | KRNLQ_SIZE_TYPE_SIZE |
  3242. (BCM_PAGE_BITS - 8) | KRNLQ_FLAGS_QE_SELF_SEQ;
  3243. cnic_ctx_wr(dev, kwq_cid_addr, L5_KRNLQ_TYPE, val);
  3244. val = (BCM_PAGE_SIZE / sizeof(struct kwqe) - 1) << 16;
  3245. cnic_ctx_wr(dev, kwq_cid_addr, L5_KRNLQ_QE_SELF_SEQ_MAX, val);
  3246. val = ((BCM_PAGE_SIZE / sizeof(struct kwqe)) << 16) | KWQ_PAGE_CNT;
  3247. cnic_ctx_wr(dev, kwq_cid_addr, L5_KRNLQ_PGTBL_NPAGES, val);
  3248. val = (u32) ((u64) cp->kwq_info.pgtbl_map >> 32);
  3249. cnic_ctx_wr(dev, kwq_cid_addr, L5_KRNLQ_PGTBL_HADDR_HI, val);
  3250. val = (u32) cp->kwq_info.pgtbl_map;
  3251. cnic_ctx_wr(dev, kwq_cid_addr, L5_KRNLQ_PGTBL_HADDR_LO, val);
  3252. kcq_cid_addr = GET_CID_ADDR(KCQ_CID);
  3253. cp->kcq1.io_addr = MB_GET_CID_ADDR(KCQ_CID) + L5_KRNLQ_HOST_QIDX;
  3254. cp->kcq1.sw_prod_idx = 0;
  3255. cp->kcq1.hw_prod_idx_ptr =
  3256. (u16 *) &sblk->status_completion_producer_index;
  3257. cp->kcq1.status_idx_ptr = (u16 *) &sblk->status_idx;
  3258. /* Initialize the kernel complete queue context. */
  3259. val = KRNLQ_TYPE_TYPE_KRNLQ | KRNLQ_SIZE_TYPE_SIZE |
  3260. (BCM_PAGE_BITS - 8) | KRNLQ_FLAGS_QE_SELF_SEQ;
  3261. cnic_ctx_wr(dev, kcq_cid_addr, L5_KRNLQ_TYPE, val);
  3262. val = (BCM_PAGE_SIZE / sizeof(struct kcqe) - 1) << 16;
  3263. cnic_ctx_wr(dev, kcq_cid_addr, L5_KRNLQ_QE_SELF_SEQ_MAX, val);
  3264. val = ((BCM_PAGE_SIZE / sizeof(struct kcqe)) << 16) | KCQ_PAGE_CNT;
  3265. cnic_ctx_wr(dev, kcq_cid_addr, L5_KRNLQ_PGTBL_NPAGES, val);
  3266. val = (u32) ((u64) cp->kcq1.dma.pgtbl_map >> 32);
  3267. cnic_ctx_wr(dev, kcq_cid_addr, L5_KRNLQ_PGTBL_HADDR_HI, val);
  3268. val = (u32) cp->kcq1.dma.pgtbl_map;
  3269. cnic_ctx_wr(dev, kcq_cid_addr, L5_KRNLQ_PGTBL_HADDR_LO, val);
  3270. cp->int_num = 0;
  3271. if (ethdev->drv_state & CNIC_DRV_STATE_USING_MSIX) {
  3272. struct status_block_msix *msblk = cp->status_blk.bnx2;
  3273. u32 sb_id = cp->status_blk_num;
  3274. u32 sb = BNX2_L2CTX_L5_STATUSB_NUM(sb_id);
  3275. cp->kcq1.hw_prod_idx_ptr =
  3276. (u16 *) &msblk->status_completion_producer_index;
  3277. cp->kcq1.status_idx_ptr = (u16 *) &msblk->status_idx;
  3278. cp->kwq_con_idx_ptr = (u16 *) &msblk->status_cmd_consumer_index;
  3279. cp->int_num = sb_id << BNX2_PCICFG_INT_ACK_CMD_INT_NUM_SHIFT;
  3280. cnic_ctx_wr(dev, kwq_cid_addr, L5_KRNLQ_HOST_QIDX, sb);
  3281. cnic_ctx_wr(dev, kcq_cid_addr, L5_KRNLQ_HOST_QIDX, sb);
  3282. }
  3283. /* Enable Commnad Scheduler notification when we write to the
  3284. * host producer index of the kernel contexts. */
  3285. CNIC_WR(dev, BNX2_MQ_KNL_CMD_MASK1, 2);
  3286. /* Enable Command Scheduler notification when we write to either
  3287. * the Send Queue or Receive Queue producer indexes of the kernel
  3288. * bypass contexts. */
  3289. CNIC_WR(dev, BNX2_MQ_KNL_BYP_CMD_MASK1, 7);
  3290. CNIC_WR(dev, BNX2_MQ_KNL_BYP_WRITE_MASK1, 7);
  3291. /* Notify COM when the driver post an application buffer. */
  3292. CNIC_WR(dev, BNX2_MQ_KNL_RX_V2P_MASK2, 0x2000);
  3293. /* Set the CP and COM doorbells. These two processors polls the
  3294. * doorbell for a non zero value before running. This must be done
  3295. * after setting up the kernel queue contexts. */
  3296. cnic_reg_wr_ind(dev, BNX2_CP_SCRATCH + 0x20, 1);
  3297. cnic_reg_wr_ind(dev, BNX2_COM_SCRATCH + 0x20, 1);
  3298. cnic_init_bnx2_tx_ring(dev);
  3299. cnic_init_bnx2_rx_ring(dev);
  3300. err = cnic_init_bnx2_irq(dev);
  3301. if (err) {
  3302. netdev_err(dev->netdev, "cnic_init_irq failed\n");
  3303. cnic_reg_wr_ind(dev, BNX2_CP_SCRATCH + 0x20, 0);
  3304. cnic_reg_wr_ind(dev, BNX2_COM_SCRATCH + 0x20, 0);
  3305. return err;
  3306. }
  3307. return 0;
  3308. }
  3309. static void cnic_setup_bnx2x_context(struct cnic_dev *dev)
  3310. {
  3311. struct cnic_local *cp = dev->cnic_priv;
  3312. struct cnic_eth_dev *ethdev = cp->ethdev;
  3313. u32 start_offset = ethdev->ctx_tbl_offset;
  3314. int i;
  3315. for (i = 0; i < cp->ctx_blks; i++) {
  3316. struct cnic_ctx *ctx = &cp->ctx_arr[i];
  3317. dma_addr_t map = ctx->mapping;
  3318. if (cp->ctx_align) {
  3319. unsigned long mask = cp->ctx_align - 1;
  3320. map = (map + mask) & ~mask;
  3321. }
  3322. cnic_ctx_tbl_wr(dev, start_offset + i, map);
  3323. }
  3324. }
  3325. static int cnic_init_bnx2x_irq(struct cnic_dev *dev)
  3326. {
  3327. struct cnic_local *cp = dev->cnic_priv;
  3328. struct cnic_eth_dev *ethdev = cp->ethdev;
  3329. int err = 0;
  3330. tasklet_init(&cp->cnic_irq_task, cnic_service_bnx2x_bh,
  3331. (unsigned long) dev);
  3332. if (ethdev->drv_state & CNIC_DRV_STATE_USING_MSIX)
  3333. err = cnic_request_irq(dev);
  3334. return err;
  3335. }
  3336. static inline void cnic_storm_memset_hc_disable(struct cnic_dev *dev,
  3337. u16 sb_id, u8 sb_index,
  3338. u8 disable)
  3339. {
  3340. u32 addr = BAR_CSTRORM_INTMEM +
  3341. CSTORM_STATUS_BLOCK_DATA_OFFSET(sb_id) +
  3342. offsetof(struct hc_status_block_data_e1x, index_data) +
  3343. sizeof(struct hc_index_data)*sb_index +
  3344. offsetof(struct hc_index_data, flags);
  3345. u16 flags = CNIC_RD16(dev, addr);
  3346. /* clear and set */
  3347. flags &= ~HC_INDEX_DATA_HC_ENABLED;
  3348. flags |= (((~disable) << HC_INDEX_DATA_HC_ENABLED_SHIFT) &
  3349. HC_INDEX_DATA_HC_ENABLED);
  3350. CNIC_WR16(dev, addr, flags);
  3351. }
  3352. static void cnic_enable_bnx2x_int(struct cnic_dev *dev)
  3353. {
  3354. struct cnic_local *cp = dev->cnic_priv;
  3355. u8 sb_id = cp->status_blk_num;
  3356. CNIC_WR8(dev, BAR_CSTRORM_INTMEM +
  3357. CSTORM_STATUS_BLOCK_DATA_OFFSET(sb_id) +
  3358. offsetof(struct hc_status_block_data_e1x, index_data) +
  3359. sizeof(struct hc_index_data)*HC_INDEX_ISCSI_EQ_CONS +
  3360. offsetof(struct hc_index_data, timeout), 64 / 12);
  3361. cnic_storm_memset_hc_disable(dev, sb_id, HC_INDEX_ISCSI_EQ_CONS, 0);
  3362. }
  3363. static void cnic_disable_bnx2x_int_sync(struct cnic_dev *dev)
  3364. {
  3365. }
  3366. static void cnic_init_bnx2x_tx_ring(struct cnic_dev *dev,
  3367. struct client_init_ramrod_data *data)
  3368. {
  3369. struct cnic_local *cp = dev->cnic_priv;
  3370. struct cnic_uio_dev *udev = cp->udev;
  3371. union eth_tx_bd_types *txbd = (union eth_tx_bd_types *) udev->l2_ring;
  3372. dma_addr_t buf_map, ring_map = udev->l2_ring_map;
  3373. struct host_sp_status_block *sb = cp->bnx2x_def_status_blk;
  3374. int port = CNIC_PORT(cp);
  3375. int i;
  3376. int cli = BNX2X_ISCSI_CL_ID(CNIC_E1HVN(cp));
  3377. u32 val;
  3378. memset(txbd, 0, BCM_PAGE_SIZE);
  3379. buf_map = udev->l2_buf_map;
  3380. for (i = 0; i < MAX_TX_DESC_CNT; i += 3, txbd += 3) {
  3381. struct eth_tx_start_bd *start_bd = &txbd->start_bd;
  3382. struct eth_tx_bd *reg_bd = &((txbd + 2)->reg_bd);
  3383. start_bd->addr_hi = cpu_to_le32((u64) buf_map >> 32);
  3384. start_bd->addr_lo = cpu_to_le32(buf_map & 0xffffffff);
  3385. reg_bd->addr_hi = start_bd->addr_hi;
  3386. reg_bd->addr_lo = start_bd->addr_lo + 0x10;
  3387. start_bd->nbytes = cpu_to_le16(0x10);
  3388. start_bd->nbd = cpu_to_le16(3);
  3389. start_bd->bd_flags.as_bitfield = ETH_TX_BD_FLAGS_START_BD;
  3390. start_bd->general_data = (UNICAST_ADDRESS <<
  3391. ETH_TX_START_BD_ETH_ADDR_TYPE_SHIFT);
  3392. start_bd->general_data |= (1 << ETH_TX_START_BD_HDR_NBDS_SHIFT);
  3393. }
  3394. val = (u64) ring_map >> 32;
  3395. txbd->next_bd.addr_hi = cpu_to_le32(val);
  3396. data->tx.tx_bd_page_base.hi = cpu_to_le32(val);
  3397. val = (u64) ring_map & 0xffffffff;
  3398. txbd->next_bd.addr_lo = cpu_to_le32(val);
  3399. data->tx.tx_bd_page_base.lo = cpu_to_le32(val);
  3400. /* Other ramrod params */
  3401. data->tx.tx_sb_index_number = HC_SP_INDEX_ETH_ISCSI_CQ_CONS;
  3402. data->tx.tx_status_block_id = BNX2X_DEF_SB_ID;
  3403. /* reset xstorm per client statistics */
  3404. if (cli < MAX_STAT_COUNTER_ID) {
  3405. val = BAR_XSTRORM_INTMEM +
  3406. XSTORM_PER_COUNTER_ID_STATS_OFFSET(port, cli);
  3407. for (i = 0; i < sizeof(struct xstorm_per_client_stats) / 4; i++)
  3408. CNIC_WR(dev, val + i * 4, 0);
  3409. }
  3410. cp->tx_cons_ptr =
  3411. &sb->sp_sb.index_values[HC_SP_INDEX_ETH_ISCSI_CQ_CONS];
  3412. }
  3413. static void cnic_init_bnx2x_rx_ring(struct cnic_dev *dev,
  3414. struct client_init_ramrod_data *data)
  3415. {
  3416. struct cnic_local *cp = dev->cnic_priv;
  3417. struct cnic_uio_dev *udev = cp->udev;
  3418. struct eth_rx_bd *rxbd = (struct eth_rx_bd *) (udev->l2_ring +
  3419. BCM_PAGE_SIZE);
  3420. struct eth_rx_cqe_next_page *rxcqe = (struct eth_rx_cqe_next_page *)
  3421. (udev->l2_ring + (2 * BCM_PAGE_SIZE));
  3422. struct host_sp_status_block *sb = cp->bnx2x_def_status_blk;
  3423. int i;
  3424. int port = CNIC_PORT(cp);
  3425. int cli = BNX2X_ISCSI_CL_ID(CNIC_E1HVN(cp));
  3426. int cl_qzone_id = BNX2X_CL_QZONE_ID(cp, cli);
  3427. u32 val;
  3428. dma_addr_t ring_map = udev->l2_ring_map;
  3429. /* General data */
  3430. data->general.client_id = cli;
  3431. data->general.statistics_en_flg = 1;
  3432. data->general.statistics_counter_id = cli;
  3433. data->general.activate_flg = 1;
  3434. data->general.sp_client_id = cli;
  3435. for (i = 0; i < BNX2X_MAX_RX_DESC_CNT; i++, rxbd++) {
  3436. dma_addr_t buf_map;
  3437. int n = (i % cp->l2_rx_ring_size) + 1;
  3438. buf_map = udev->l2_buf_map + (n * cp->l2_single_buf_size);
  3439. rxbd->addr_hi = cpu_to_le32((u64) buf_map >> 32);
  3440. rxbd->addr_lo = cpu_to_le32(buf_map & 0xffffffff);
  3441. }
  3442. val = (u64) (ring_map + BCM_PAGE_SIZE) >> 32;
  3443. rxbd->addr_hi = cpu_to_le32(val);
  3444. data->rx.bd_page_base.hi = cpu_to_le32(val);
  3445. val = (u64) (ring_map + BCM_PAGE_SIZE) & 0xffffffff;
  3446. rxbd->addr_lo = cpu_to_le32(val);
  3447. data->rx.bd_page_base.lo = cpu_to_le32(val);
  3448. rxcqe += BNX2X_MAX_RCQ_DESC_CNT;
  3449. val = (u64) (ring_map + (2 * BCM_PAGE_SIZE)) >> 32;
  3450. rxcqe->addr_hi = cpu_to_le32(val);
  3451. data->rx.cqe_page_base.hi = cpu_to_le32(val);
  3452. val = (u64) (ring_map + (2 * BCM_PAGE_SIZE)) & 0xffffffff;
  3453. rxcqe->addr_lo = cpu_to_le32(val);
  3454. data->rx.cqe_page_base.lo = cpu_to_le32(val);
  3455. /* Other ramrod params */
  3456. data->rx.client_qzone_id = cl_qzone_id;
  3457. data->rx.rx_sb_index_number = HC_SP_INDEX_ETH_ISCSI_RX_CQ_CONS;
  3458. data->rx.status_block_id = BNX2X_DEF_SB_ID;
  3459. data->rx.cache_line_alignment_log_size = L1_CACHE_SHIFT;
  3460. data->rx.bd_buff_size = cpu_to_le16(cp->l2_single_buf_size);
  3461. data->rx.mtu = cpu_to_le16(cp->l2_single_buf_size - 14);
  3462. data->rx.outer_vlan_removal_enable_flg = 1;
  3463. /* reset tstorm and ustorm per client statistics */
  3464. if (cli < MAX_STAT_COUNTER_ID) {
  3465. val = BAR_TSTRORM_INTMEM +
  3466. TSTORM_PER_COUNTER_ID_STATS_OFFSET(port, cli);
  3467. for (i = 0; i < sizeof(struct tstorm_per_client_stats) / 4; i++)
  3468. CNIC_WR(dev, val + i * 4, 0);
  3469. val = BAR_USTRORM_INTMEM +
  3470. USTORM_PER_COUNTER_ID_STATS_OFFSET(port, cli);
  3471. for (i = 0; i < sizeof(struct ustorm_per_client_stats) / 4; i++)
  3472. CNIC_WR(dev, val + i * 4, 0);
  3473. }
  3474. cp->rx_cons_ptr =
  3475. &sb->sp_sb.index_values[HC_SP_INDEX_ETH_ISCSI_RX_CQ_CONS];
  3476. }
  3477. static void cnic_get_bnx2x_iscsi_info(struct cnic_dev *dev)
  3478. {
  3479. struct cnic_local *cp = dev->cnic_priv;
  3480. u32 base, base2, addr, val;
  3481. int port = CNIC_PORT(cp);
  3482. dev->max_iscsi_conn = 0;
  3483. base = CNIC_RD(dev, MISC_REG_SHARED_MEM_ADDR);
  3484. if (base == 0)
  3485. return;
  3486. base2 = CNIC_RD(dev, (CNIC_PATH(cp) ? MISC_REG_GENERIC_CR_1 :
  3487. MISC_REG_GENERIC_CR_0));
  3488. addr = BNX2X_SHMEM_ADDR(base,
  3489. dev_info.port_hw_config[port].iscsi_mac_upper);
  3490. val = CNIC_RD(dev, addr);
  3491. dev->mac_addr[0] = (u8) (val >> 8);
  3492. dev->mac_addr[1] = (u8) val;
  3493. addr = BNX2X_SHMEM_ADDR(base,
  3494. dev_info.port_hw_config[port].iscsi_mac_lower);
  3495. val = CNIC_RD(dev, addr);
  3496. dev->mac_addr[2] = (u8) (val >> 24);
  3497. dev->mac_addr[3] = (u8) (val >> 16);
  3498. dev->mac_addr[4] = (u8) (val >> 8);
  3499. dev->mac_addr[5] = (u8) val;
  3500. addr = BNX2X_SHMEM_ADDR(base, validity_map[port]);
  3501. val = CNIC_RD(dev, addr);
  3502. if (!(val & SHR_MEM_VALIDITY_LIC_NO_KEY_IN_EFFECT)) {
  3503. u16 val16;
  3504. addr = BNX2X_SHMEM_ADDR(base,
  3505. drv_lic_key[port].max_iscsi_init_conn);
  3506. val16 = CNIC_RD16(dev, addr);
  3507. if (val16)
  3508. val16 ^= 0x1e1e;
  3509. dev->max_iscsi_conn = val16;
  3510. }
  3511. if (BNX2X_CHIP_IS_E1H(cp->chip_id) || BNX2X_CHIP_IS_E2(cp->chip_id)) {
  3512. int func = CNIC_FUNC(cp);
  3513. u32 mf_cfg_addr;
  3514. if (BNX2X_SHMEM2_HAS(base2, mf_cfg_addr))
  3515. mf_cfg_addr = CNIC_RD(dev, BNX2X_SHMEM2_ADDR(base2,
  3516. mf_cfg_addr));
  3517. else
  3518. mf_cfg_addr = base + BNX2X_SHMEM_MF_BLK_OFFSET;
  3519. addr = mf_cfg_addr +
  3520. offsetof(struct mf_cfg, func_mf_config[func].e1hov_tag);
  3521. val = CNIC_RD(dev, addr);
  3522. val &= FUNC_MF_CFG_E1HOV_TAG_MASK;
  3523. if (val != FUNC_MF_CFG_E1HOV_TAG_DEFAULT) {
  3524. addr = mf_cfg_addr +
  3525. offsetof(struct mf_cfg,
  3526. func_mf_config[func].config);
  3527. val = CNIC_RD(dev, addr);
  3528. val &= FUNC_MF_CFG_PROTOCOL_MASK;
  3529. if (val != FUNC_MF_CFG_PROTOCOL_ISCSI)
  3530. dev->max_iscsi_conn = 0;
  3531. }
  3532. }
  3533. }
  3534. static int cnic_start_bnx2x_hw(struct cnic_dev *dev)
  3535. {
  3536. struct cnic_local *cp = dev->cnic_priv;
  3537. struct cnic_eth_dev *ethdev = cp->ethdev;
  3538. int func = CNIC_FUNC(cp), ret, i;
  3539. u32 pfid;
  3540. if (BNX2X_CHIP_IS_E2(cp->chip_id)) {
  3541. u32 val = CNIC_RD(dev, MISC_REG_PORT4MODE_EN_OVWR);
  3542. if (!(val & 1))
  3543. val = CNIC_RD(dev, MISC_REG_PORT4MODE_EN);
  3544. else
  3545. val = (val >> 1) & 1;
  3546. if (val)
  3547. cp->pfid = func >> 1;
  3548. else
  3549. cp->pfid = func & 0x6;
  3550. } else {
  3551. cp->pfid = func;
  3552. }
  3553. pfid = cp->pfid;
  3554. ret = cnic_init_id_tbl(&cp->cid_tbl, MAX_ISCSI_TBL_SZ,
  3555. cp->iscsi_start_cid);
  3556. if (ret)
  3557. return -ENOMEM;
  3558. cp->bnx2x_igu_sb_id = ethdev->irq_arr[0].status_blk_num2;
  3559. cp->kcq1.io_addr = BAR_CSTRORM_INTMEM +
  3560. CSTORM_ISCSI_EQ_PROD_OFFSET(pfid, 0);
  3561. cp->kcq1.sw_prod_idx = 0;
  3562. if (BNX2X_CHIP_IS_E2(cp->chip_id)) {
  3563. struct host_hc_status_block_e2 *sb = cp->status_blk.gen;
  3564. cp->kcq1.hw_prod_idx_ptr =
  3565. &sb->sb.index_values[HC_INDEX_ISCSI_EQ_CONS];
  3566. cp->kcq1.status_idx_ptr =
  3567. &sb->sb.running_index[SM_RX_ID];
  3568. } else {
  3569. struct host_hc_status_block_e1x *sb = cp->status_blk.gen;
  3570. cp->kcq1.hw_prod_idx_ptr =
  3571. &sb->sb.index_values[HC_INDEX_ISCSI_EQ_CONS];
  3572. cp->kcq1.status_idx_ptr =
  3573. &sb->sb.running_index[SM_RX_ID];
  3574. }
  3575. cnic_get_bnx2x_iscsi_info(dev);
  3576. /* Only 1 EQ */
  3577. CNIC_WR16(dev, cp->kcq1.io_addr, MAX_KCQ_IDX);
  3578. CNIC_WR(dev, BAR_CSTRORM_INTMEM +
  3579. CSTORM_ISCSI_EQ_CONS_OFFSET(pfid, 0), 0);
  3580. CNIC_WR(dev, BAR_CSTRORM_INTMEM +
  3581. CSTORM_ISCSI_EQ_NEXT_PAGE_ADDR_OFFSET(pfid, 0),
  3582. cp->kcq1.dma.pg_map_arr[1] & 0xffffffff);
  3583. CNIC_WR(dev, BAR_CSTRORM_INTMEM +
  3584. CSTORM_ISCSI_EQ_NEXT_PAGE_ADDR_OFFSET(pfid, 0) + 4,
  3585. (u64) cp->kcq1.dma.pg_map_arr[1] >> 32);
  3586. CNIC_WR(dev, BAR_CSTRORM_INTMEM +
  3587. CSTORM_ISCSI_EQ_NEXT_EQE_ADDR_OFFSET(pfid, 0),
  3588. cp->kcq1.dma.pg_map_arr[0] & 0xffffffff);
  3589. CNIC_WR(dev, BAR_CSTRORM_INTMEM +
  3590. CSTORM_ISCSI_EQ_NEXT_EQE_ADDR_OFFSET(pfid, 0) + 4,
  3591. (u64) cp->kcq1.dma.pg_map_arr[0] >> 32);
  3592. CNIC_WR8(dev, BAR_CSTRORM_INTMEM +
  3593. CSTORM_ISCSI_EQ_NEXT_PAGE_ADDR_VALID_OFFSET(pfid, 0), 1);
  3594. CNIC_WR16(dev, BAR_CSTRORM_INTMEM +
  3595. CSTORM_ISCSI_EQ_SB_NUM_OFFSET(pfid, 0), cp->status_blk_num);
  3596. CNIC_WR8(dev, BAR_CSTRORM_INTMEM +
  3597. CSTORM_ISCSI_EQ_SB_INDEX_OFFSET(pfid, 0),
  3598. HC_INDEX_ISCSI_EQ_CONS);
  3599. for (i = 0; i < cp->conn_buf_info.num_pages; i++) {
  3600. CNIC_WR(dev, BAR_TSTRORM_INTMEM +
  3601. TSTORM_ISCSI_CONN_BUF_PBL_OFFSET(pfid, i),
  3602. cp->conn_buf_info.pgtbl[2 * i]);
  3603. CNIC_WR(dev, BAR_TSTRORM_INTMEM +
  3604. TSTORM_ISCSI_CONN_BUF_PBL_OFFSET(pfid, i) + 4,
  3605. cp->conn_buf_info.pgtbl[(2 * i) + 1]);
  3606. }
  3607. CNIC_WR(dev, BAR_USTRORM_INTMEM +
  3608. USTORM_ISCSI_GLOBAL_BUF_PHYS_ADDR_OFFSET(pfid),
  3609. cp->gbl_buf_info.pg_map_arr[0] & 0xffffffff);
  3610. CNIC_WR(dev, BAR_USTRORM_INTMEM +
  3611. USTORM_ISCSI_GLOBAL_BUF_PHYS_ADDR_OFFSET(pfid) + 4,
  3612. (u64) cp->gbl_buf_info.pg_map_arr[0] >> 32);
  3613. CNIC_WR(dev, BAR_TSTRORM_INTMEM +
  3614. TSTORM_ISCSI_TCP_LOCAL_ADV_WND_OFFSET(pfid), DEF_RCV_BUF);
  3615. cnic_setup_bnx2x_context(dev);
  3616. ret = cnic_init_bnx2x_irq(dev);
  3617. if (ret)
  3618. return ret;
  3619. return 0;
  3620. }
  3621. static void cnic_init_rings(struct cnic_dev *dev)
  3622. {
  3623. struct cnic_local *cp = dev->cnic_priv;
  3624. struct cnic_uio_dev *udev = cp->udev;
  3625. if (test_bit(CNIC_LCL_FL_RINGS_INITED, &cp->cnic_local_flags))
  3626. return;
  3627. if (test_bit(CNIC_F_BNX2_CLASS, &dev->flags)) {
  3628. cnic_init_bnx2_tx_ring(dev);
  3629. cnic_init_bnx2_rx_ring(dev);
  3630. set_bit(CNIC_LCL_FL_RINGS_INITED, &cp->cnic_local_flags);
  3631. } else if (test_bit(CNIC_F_BNX2X_CLASS, &dev->flags)) {
  3632. u32 cli = BNX2X_ISCSI_CL_ID(CNIC_E1HVN(cp));
  3633. u32 cl_qzone_id, type;
  3634. struct client_init_ramrod_data *data;
  3635. union l5cm_specific_data l5_data;
  3636. struct ustorm_eth_rx_producers rx_prods = {0};
  3637. u32 off, i;
  3638. rx_prods.bd_prod = 0;
  3639. rx_prods.cqe_prod = BNX2X_MAX_RCQ_DESC_CNT;
  3640. barrier();
  3641. cl_qzone_id = BNX2X_CL_QZONE_ID(cp, cli);
  3642. off = BAR_USTRORM_INTMEM +
  3643. (BNX2X_CHIP_IS_E2(cp->chip_id) ?
  3644. USTORM_RX_PRODS_E2_OFFSET(cl_qzone_id) :
  3645. USTORM_RX_PRODS_E1X_OFFSET(CNIC_PORT(cp), cli));
  3646. for (i = 0; i < sizeof(struct ustorm_eth_rx_producers) / 4; i++)
  3647. CNIC_WR(dev, off + i * 4, ((u32 *) &rx_prods)[i]);
  3648. set_bit(CNIC_LCL_FL_L2_WAIT, &cp->cnic_local_flags);
  3649. data = udev->l2_buf;
  3650. memset(data, 0, sizeof(*data));
  3651. cnic_init_bnx2x_tx_ring(dev, data);
  3652. cnic_init_bnx2x_rx_ring(dev, data);
  3653. l5_data.phy_address.lo = udev->l2_buf_map & 0xffffffff;
  3654. l5_data.phy_address.hi = (u64) udev->l2_buf_map >> 32;
  3655. type = (ETH_CONNECTION_TYPE << SPE_HDR_CONN_TYPE_SHIFT)
  3656. & SPE_HDR_CONN_TYPE;
  3657. type |= ((cp->pfid << SPE_HDR_FUNCTION_ID_SHIFT) &
  3658. SPE_HDR_FUNCTION_ID);
  3659. set_bit(CNIC_LCL_FL_RINGS_INITED, &cp->cnic_local_flags);
  3660. cnic_submit_kwqe_16(dev, RAMROD_CMD_ID_ETH_CLIENT_SETUP,
  3661. BNX2X_ISCSI_L2_CID, type, &l5_data);
  3662. i = 0;
  3663. while (test_bit(CNIC_LCL_FL_L2_WAIT, &cp->cnic_local_flags) &&
  3664. ++i < 10)
  3665. msleep(1);
  3666. if (test_bit(CNIC_LCL_FL_L2_WAIT, &cp->cnic_local_flags))
  3667. netdev_err(dev->netdev,
  3668. "iSCSI CLIENT_SETUP did not complete\n");
  3669. cnic_spq_completion(dev, DRV_CTL_RET_L2_SPQ_CREDIT_CMD, 1);
  3670. cnic_ring_ctl(dev, BNX2X_ISCSI_L2_CID, cli, 1);
  3671. }
  3672. }
  3673. static void cnic_shutdown_rings(struct cnic_dev *dev)
  3674. {
  3675. struct cnic_local *cp = dev->cnic_priv;
  3676. if (!test_bit(CNIC_LCL_FL_RINGS_INITED, &cp->cnic_local_flags))
  3677. return;
  3678. if (test_bit(CNIC_F_BNX2_CLASS, &dev->flags)) {
  3679. cnic_shutdown_bnx2_rx_ring(dev);
  3680. } else if (test_bit(CNIC_F_BNX2X_CLASS, &dev->flags)) {
  3681. struct cnic_local *cp = dev->cnic_priv;
  3682. u32 cli = BNX2X_ISCSI_CL_ID(CNIC_E1HVN(cp));
  3683. union l5cm_specific_data l5_data;
  3684. int i;
  3685. u32 type;
  3686. cnic_ring_ctl(dev, BNX2X_ISCSI_L2_CID, cli, 0);
  3687. set_bit(CNIC_LCL_FL_L2_WAIT, &cp->cnic_local_flags);
  3688. l5_data.phy_address.lo = cli;
  3689. l5_data.phy_address.hi = 0;
  3690. cnic_submit_kwqe_16(dev, RAMROD_CMD_ID_ETH_HALT,
  3691. BNX2X_ISCSI_L2_CID, ETH_CONNECTION_TYPE, &l5_data);
  3692. i = 0;
  3693. while (test_bit(CNIC_LCL_FL_L2_WAIT, &cp->cnic_local_flags) &&
  3694. ++i < 10)
  3695. msleep(1);
  3696. if (test_bit(CNIC_LCL_FL_L2_WAIT, &cp->cnic_local_flags))
  3697. netdev_err(dev->netdev,
  3698. "iSCSI CLIENT_HALT did not complete\n");
  3699. cnic_spq_completion(dev, DRV_CTL_RET_L2_SPQ_CREDIT_CMD, 1);
  3700. memset(&l5_data, 0, sizeof(l5_data));
  3701. type = (NONE_CONNECTION_TYPE << SPE_HDR_CONN_TYPE_SHIFT)
  3702. & SPE_HDR_CONN_TYPE;
  3703. type |= ((cp->pfid << SPE_HDR_FUNCTION_ID_SHIFT) &
  3704. SPE_HDR_FUNCTION_ID);
  3705. cnic_submit_kwqe_16(dev, RAMROD_CMD_ID_COMMON_CFC_DEL,
  3706. BNX2X_ISCSI_L2_CID, type, &l5_data);
  3707. msleep(10);
  3708. }
  3709. clear_bit(CNIC_LCL_FL_RINGS_INITED, &cp->cnic_local_flags);
  3710. }
  3711. static int cnic_register_netdev(struct cnic_dev *dev)
  3712. {
  3713. struct cnic_local *cp = dev->cnic_priv;
  3714. struct cnic_eth_dev *ethdev = cp->ethdev;
  3715. int err;
  3716. if (!ethdev)
  3717. return -ENODEV;
  3718. if (ethdev->drv_state & CNIC_DRV_STATE_REGD)
  3719. return 0;
  3720. err = ethdev->drv_register_cnic(dev->netdev, cp->cnic_ops, dev);
  3721. if (err)
  3722. netdev_err(dev->netdev, "register_cnic failed\n");
  3723. return err;
  3724. }
  3725. static void cnic_unregister_netdev(struct cnic_dev *dev)
  3726. {
  3727. struct cnic_local *cp = dev->cnic_priv;
  3728. struct cnic_eth_dev *ethdev = cp->ethdev;
  3729. if (!ethdev)
  3730. return;
  3731. ethdev->drv_unregister_cnic(dev->netdev);
  3732. }
  3733. static int cnic_start_hw(struct cnic_dev *dev)
  3734. {
  3735. struct cnic_local *cp = dev->cnic_priv;
  3736. struct cnic_eth_dev *ethdev = cp->ethdev;
  3737. int err;
  3738. if (test_bit(CNIC_F_CNIC_UP, &dev->flags))
  3739. return -EALREADY;
  3740. dev->regview = ethdev->io_base;
  3741. pci_dev_get(dev->pcidev);
  3742. cp->func = PCI_FUNC(dev->pcidev->devfn);
  3743. cp->status_blk.gen = ethdev->irq_arr[0].status_blk;
  3744. cp->status_blk_num = ethdev->irq_arr[0].status_blk_num;
  3745. err = cp->alloc_resc(dev);
  3746. if (err) {
  3747. netdev_err(dev->netdev, "allocate resource failure\n");
  3748. goto err1;
  3749. }
  3750. err = cp->start_hw(dev);
  3751. if (err)
  3752. goto err1;
  3753. err = cnic_cm_open(dev);
  3754. if (err)
  3755. goto err1;
  3756. set_bit(CNIC_F_CNIC_UP, &dev->flags);
  3757. cp->enable_int(dev);
  3758. return 0;
  3759. err1:
  3760. cp->free_resc(dev);
  3761. pci_dev_put(dev->pcidev);
  3762. return err;
  3763. }
  3764. static void cnic_stop_bnx2_hw(struct cnic_dev *dev)
  3765. {
  3766. cnic_disable_bnx2_int_sync(dev);
  3767. cnic_reg_wr_ind(dev, BNX2_CP_SCRATCH + 0x20, 0);
  3768. cnic_reg_wr_ind(dev, BNX2_COM_SCRATCH + 0x20, 0);
  3769. cnic_init_context(dev, KWQ_CID);
  3770. cnic_init_context(dev, KCQ_CID);
  3771. cnic_setup_5709_context(dev, 0);
  3772. cnic_free_irq(dev);
  3773. cnic_free_resc(dev);
  3774. }
  3775. static void cnic_stop_bnx2x_hw(struct cnic_dev *dev)
  3776. {
  3777. struct cnic_local *cp = dev->cnic_priv;
  3778. cnic_free_irq(dev);
  3779. *cp->kcq1.hw_prod_idx_ptr = 0;
  3780. CNIC_WR(dev, BAR_CSTRORM_INTMEM +
  3781. CSTORM_ISCSI_EQ_CONS_OFFSET(cp->pfid, 0), 0);
  3782. CNIC_WR16(dev, cp->kcq1.io_addr, 0);
  3783. cnic_free_resc(dev);
  3784. }
  3785. static void cnic_stop_hw(struct cnic_dev *dev)
  3786. {
  3787. if (test_bit(CNIC_F_CNIC_UP, &dev->flags)) {
  3788. struct cnic_local *cp = dev->cnic_priv;
  3789. int i = 0;
  3790. /* Need to wait for the ring shutdown event to complete
  3791. * before clearing the CNIC_UP flag.
  3792. */
  3793. while (cp->udev->uio_dev != -1 && i < 15) {
  3794. msleep(100);
  3795. i++;
  3796. }
  3797. cnic_shutdown_rings(dev);
  3798. clear_bit(CNIC_F_CNIC_UP, &dev->flags);
  3799. rcu_assign_pointer(cp->ulp_ops[CNIC_ULP_L4], NULL);
  3800. synchronize_rcu();
  3801. cnic_cm_shutdown(dev);
  3802. cp->stop_hw(dev);
  3803. pci_dev_put(dev->pcidev);
  3804. }
  3805. }
  3806. static void cnic_free_dev(struct cnic_dev *dev)
  3807. {
  3808. int i = 0;
  3809. while ((atomic_read(&dev->ref_count) != 0) && i < 10) {
  3810. msleep(100);
  3811. i++;
  3812. }
  3813. if (atomic_read(&dev->ref_count) != 0)
  3814. netdev_err(dev->netdev, "Failed waiting for ref count to go to zero\n");
  3815. netdev_info(dev->netdev, "Removed CNIC device\n");
  3816. dev_put(dev->netdev);
  3817. kfree(dev);
  3818. }
  3819. static struct cnic_dev *cnic_alloc_dev(struct net_device *dev,
  3820. struct pci_dev *pdev)
  3821. {
  3822. struct cnic_dev *cdev;
  3823. struct cnic_local *cp;
  3824. int alloc_size;
  3825. alloc_size = sizeof(struct cnic_dev) + sizeof(struct cnic_local);
  3826. cdev = kzalloc(alloc_size , GFP_KERNEL);
  3827. if (cdev == NULL) {
  3828. netdev_err(dev, "allocate dev struct failure\n");
  3829. return NULL;
  3830. }
  3831. cdev->netdev = dev;
  3832. cdev->cnic_priv = (char *)cdev + sizeof(struct cnic_dev);
  3833. cdev->register_device = cnic_register_device;
  3834. cdev->unregister_device = cnic_unregister_device;
  3835. cdev->iscsi_nl_msg_recv = cnic_iscsi_nl_msg_recv;
  3836. cp = cdev->cnic_priv;
  3837. cp->dev = cdev;
  3838. cp->l2_single_buf_size = 0x400;
  3839. cp->l2_rx_ring_size = 3;
  3840. spin_lock_init(&cp->cnic_ulp_lock);
  3841. netdev_info(dev, "Added CNIC device\n");
  3842. return cdev;
  3843. }
  3844. static struct cnic_dev *init_bnx2_cnic(struct net_device *dev)
  3845. {
  3846. struct pci_dev *pdev;
  3847. struct cnic_dev *cdev;
  3848. struct cnic_local *cp;
  3849. struct cnic_eth_dev *ethdev = NULL;
  3850. struct cnic_eth_dev *(*probe)(struct net_device *) = NULL;
  3851. probe = symbol_get(bnx2_cnic_probe);
  3852. if (probe) {
  3853. ethdev = (*probe)(dev);
  3854. symbol_put(bnx2_cnic_probe);
  3855. }
  3856. if (!ethdev)
  3857. return NULL;
  3858. pdev = ethdev->pdev;
  3859. if (!pdev)
  3860. return NULL;
  3861. dev_hold(dev);
  3862. pci_dev_get(pdev);
  3863. if (pdev->device == PCI_DEVICE_ID_NX2_5709 ||
  3864. pdev->device == PCI_DEVICE_ID_NX2_5709S) {
  3865. u8 rev;
  3866. pci_read_config_byte(pdev, PCI_REVISION_ID, &rev);
  3867. if (rev < 0x10) {
  3868. pci_dev_put(pdev);
  3869. goto cnic_err;
  3870. }
  3871. }
  3872. pci_dev_put(pdev);
  3873. cdev = cnic_alloc_dev(dev, pdev);
  3874. if (cdev == NULL)
  3875. goto cnic_err;
  3876. set_bit(CNIC_F_BNX2_CLASS, &cdev->flags);
  3877. cdev->submit_kwqes = cnic_submit_bnx2_kwqes;
  3878. cp = cdev->cnic_priv;
  3879. cp->ethdev = ethdev;
  3880. cdev->pcidev = pdev;
  3881. cp->chip_id = ethdev->chip_id;
  3882. cp->cnic_ops = &cnic_bnx2_ops;
  3883. cp->start_hw = cnic_start_bnx2_hw;
  3884. cp->stop_hw = cnic_stop_bnx2_hw;
  3885. cp->setup_pgtbl = cnic_setup_page_tbl;
  3886. cp->alloc_resc = cnic_alloc_bnx2_resc;
  3887. cp->free_resc = cnic_free_resc;
  3888. cp->start_cm = cnic_cm_init_bnx2_hw;
  3889. cp->stop_cm = cnic_cm_stop_bnx2_hw;
  3890. cp->enable_int = cnic_enable_bnx2_int;
  3891. cp->disable_int_sync = cnic_disable_bnx2_int_sync;
  3892. cp->close_conn = cnic_close_bnx2_conn;
  3893. cp->next_idx = cnic_bnx2_next_idx;
  3894. cp->hw_idx = cnic_bnx2_hw_idx;
  3895. return cdev;
  3896. cnic_err:
  3897. dev_put(dev);
  3898. return NULL;
  3899. }
  3900. static struct cnic_dev *init_bnx2x_cnic(struct net_device *dev)
  3901. {
  3902. struct pci_dev *pdev;
  3903. struct cnic_dev *cdev;
  3904. struct cnic_local *cp;
  3905. struct cnic_eth_dev *ethdev = NULL;
  3906. struct cnic_eth_dev *(*probe)(struct net_device *) = NULL;
  3907. probe = symbol_get(bnx2x_cnic_probe);
  3908. if (probe) {
  3909. ethdev = (*probe)(dev);
  3910. symbol_put(bnx2x_cnic_probe);
  3911. }
  3912. if (!ethdev)
  3913. return NULL;
  3914. pdev = ethdev->pdev;
  3915. if (!pdev)
  3916. return NULL;
  3917. dev_hold(dev);
  3918. cdev = cnic_alloc_dev(dev, pdev);
  3919. if (cdev == NULL) {
  3920. dev_put(dev);
  3921. return NULL;
  3922. }
  3923. set_bit(CNIC_F_BNX2X_CLASS, &cdev->flags);
  3924. cdev->submit_kwqes = cnic_submit_bnx2x_kwqes;
  3925. cp = cdev->cnic_priv;
  3926. cp->ethdev = ethdev;
  3927. cdev->pcidev = pdev;
  3928. cp->chip_id = ethdev->chip_id;
  3929. cp->cnic_ops = &cnic_bnx2x_ops;
  3930. cp->start_hw = cnic_start_bnx2x_hw;
  3931. cp->stop_hw = cnic_stop_bnx2x_hw;
  3932. cp->setup_pgtbl = cnic_setup_page_tbl_le;
  3933. cp->alloc_resc = cnic_alloc_bnx2x_resc;
  3934. cp->free_resc = cnic_free_resc;
  3935. cp->start_cm = cnic_cm_init_bnx2x_hw;
  3936. cp->stop_cm = cnic_cm_stop_bnx2x_hw;
  3937. cp->enable_int = cnic_enable_bnx2x_int;
  3938. cp->disable_int_sync = cnic_disable_bnx2x_int_sync;
  3939. if (BNX2X_CHIP_IS_E2(cp->chip_id))
  3940. cp->ack_int = cnic_ack_bnx2x_e2_msix;
  3941. else
  3942. cp->ack_int = cnic_ack_bnx2x_msix;
  3943. cp->close_conn = cnic_close_bnx2x_conn;
  3944. cp->next_idx = cnic_bnx2x_next_idx;
  3945. cp->hw_idx = cnic_bnx2x_hw_idx;
  3946. return cdev;
  3947. }
  3948. static struct cnic_dev *is_cnic_dev(struct net_device *dev)
  3949. {
  3950. struct ethtool_drvinfo drvinfo;
  3951. struct cnic_dev *cdev = NULL;
  3952. if (dev->ethtool_ops && dev->ethtool_ops->get_drvinfo) {
  3953. memset(&drvinfo, 0, sizeof(drvinfo));
  3954. dev->ethtool_ops->get_drvinfo(dev, &drvinfo);
  3955. if (!strcmp(drvinfo.driver, "bnx2"))
  3956. cdev = init_bnx2_cnic(dev);
  3957. if (!strcmp(drvinfo.driver, "bnx2x"))
  3958. cdev = init_bnx2x_cnic(dev);
  3959. if (cdev) {
  3960. write_lock(&cnic_dev_lock);
  3961. list_add(&cdev->list, &cnic_dev_list);
  3962. write_unlock(&cnic_dev_lock);
  3963. }
  3964. }
  3965. return cdev;
  3966. }
  3967. /**
  3968. * netdev event handler
  3969. */
  3970. static int cnic_netdev_event(struct notifier_block *this, unsigned long event,
  3971. void *ptr)
  3972. {
  3973. struct net_device *netdev = ptr;
  3974. struct cnic_dev *dev;
  3975. int if_type;
  3976. int new_dev = 0;
  3977. dev = cnic_from_netdev(netdev);
  3978. if (!dev && (event == NETDEV_REGISTER || event == NETDEV_UP)) {
  3979. /* Check for the hot-plug device */
  3980. dev = is_cnic_dev(netdev);
  3981. if (dev) {
  3982. new_dev = 1;
  3983. cnic_hold(dev);
  3984. }
  3985. }
  3986. if (dev) {
  3987. struct cnic_local *cp = dev->cnic_priv;
  3988. if (new_dev)
  3989. cnic_ulp_init(dev);
  3990. else if (event == NETDEV_UNREGISTER)
  3991. cnic_ulp_exit(dev);
  3992. if (event == NETDEV_UP) {
  3993. if (cnic_register_netdev(dev) != 0) {
  3994. cnic_put(dev);
  3995. goto done;
  3996. }
  3997. if (!cnic_start_hw(dev))
  3998. cnic_ulp_start(dev);
  3999. }
  4000. rcu_read_lock();
  4001. for (if_type = 0; if_type < MAX_CNIC_ULP_TYPE; if_type++) {
  4002. struct cnic_ulp_ops *ulp_ops;
  4003. void *ctx;
  4004. ulp_ops = rcu_dereference(cp->ulp_ops[if_type]);
  4005. if (!ulp_ops || !ulp_ops->indicate_netevent)
  4006. continue;
  4007. ctx = cp->ulp_handle[if_type];
  4008. ulp_ops->indicate_netevent(ctx, event);
  4009. }
  4010. rcu_read_unlock();
  4011. if (event == NETDEV_GOING_DOWN) {
  4012. cnic_ulp_stop(dev);
  4013. cnic_stop_hw(dev);
  4014. cnic_unregister_netdev(dev);
  4015. } else if (event == NETDEV_UNREGISTER) {
  4016. write_lock(&cnic_dev_lock);
  4017. list_del_init(&dev->list);
  4018. write_unlock(&cnic_dev_lock);
  4019. cnic_put(dev);
  4020. cnic_free_dev(dev);
  4021. goto done;
  4022. }
  4023. cnic_put(dev);
  4024. }
  4025. done:
  4026. return NOTIFY_DONE;
  4027. }
  4028. static struct notifier_block cnic_netdev_notifier = {
  4029. .notifier_call = cnic_netdev_event
  4030. };
  4031. static void cnic_release(void)
  4032. {
  4033. struct cnic_dev *dev;
  4034. struct cnic_uio_dev *udev;
  4035. while (!list_empty(&cnic_dev_list)) {
  4036. dev = list_entry(cnic_dev_list.next, struct cnic_dev, list);
  4037. if (test_bit(CNIC_F_CNIC_UP, &dev->flags)) {
  4038. cnic_ulp_stop(dev);
  4039. cnic_stop_hw(dev);
  4040. }
  4041. cnic_ulp_exit(dev);
  4042. cnic_unregister_netdev(dev);
  4043. list_del_init(&dev->list);
  4044. cnic_free_dev(dev);
  4045. }
  4046. while (!list_empty(&cnic_udev_list)) {
  4047. udev = list_entry(cnic_udev_list.next, struct cnic_uio_dev,
  4048. list);
  4049. cnic_free_uio(udev);
  4050. }
  4051. }
  4052. static int __init cnic_init(void)
  4053. {
  4054. int rc = 0;
  4055. pr_info("%s", version);
  4056. rc = register_netdevice_notifier(&cnic_netdev_notifier);
  4057. if (rc) {
  4058. cnic_release();
  4059. return rc;
  4060. }
  4061. cnic_wq = create_singlethread_workqueue("cnic_wq");
  4062. if (!cnic_wq) {
  4063. cnic_release();
  4064. unregister_netdevice_notifier(&cnic_netdev_notifier);
  4065. return -ENOMEM;
  4066. }
  4067. return 0;
  4068. }
  4069. static void __exit cnic_exit(void)
  4070. {
  4071. unregister_netdevice_notifier(&cnic_netdev_notifier);
  4072. cnic_release();
  4073. destroy_workqueue(cnic_wq);
  4074. }
  4075. module_init(cnic_init);
  4076. module_exit(cnic_exit);