au1000_eth.c 33 KB

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  1. /*
  2. *
  3. * Alchemy Au1x00 ethernet driver
  4. *
  5. * Copyright 2001-2003, 2006 MontaVista Software Inc.
  6. * Copyright 2002 TimeSys Corp.
  7. * Added ethtool/mii-tool support,
  8. * Copyright 2004 Matt Porter <mporter@kernel.crashing.org>
  9. * Update: 2004 Bjoern Riemer, riemer@fokus.fraunhofer.de
  10. * or riemer@riemer-nt.de: fixed the link beat detection with
  11. * ioctls (SIOCGMIIPHY)
  12. * Copyright 2006 Herbert Valerio Riedel <hvr@gnu.org>
  13. * converted to use linux-2.6.x's PHY framework
  14. *
  15. * Author: MontaVista Software, Inc.
  16. * ppopov@mvista.com or source@mvista.com
  17. *
  18. * ########################################################################
  19. *
  20. * This program is free software; you can distribute it and/or modify it
  21. * under the terms of the GNU General Public License (Version 2) as
  22. * published by the Free Software Foundation.
  23. *
  24. * This program is distributed in the hope it will be useful, but WITHOUT
  25. * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  26. * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
  27. * for more details.
  28. *
  29. * You should have received a copy of the GNU General Public License along
  30. * with this program; if not, write to the Free Software Foundation, Inc.,
  31. * 59 Temple Place - Suite 330, Boston MA 02111-1307, USA.
  32. *
  33. * ########################################################################
  34. *
  35. *
  36. */
  37. #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
  38. #include <linux/capability.h>
  39. #include <linux/dma-mapping.h>
  40. #include <linux/module.h>
  41. #include <linux/kernel.h>
  42. #include <linux/string.h>
  43. #include <linux/timer.h>
  44. #include <linux/errno.h>
  45. #include <linux/in.h>
  46. #include <linux/ioport.h>
  47. #include <linux/bitops.h>
  48. #include <linux/slab.h>
  49. #include <linux/interrupt.h>
  50. #include <linux/init.h>
  51. #include <linux/netdevice.h>
  52. #include <linux/etherdevice.h>
  53. #include <linux/ethtool.h>
  54. #include <linux/mii.h>
  55. #include <linux/skbuff.h>
  56. #include <linux/delay.h>
  57. #include <linux/crc32.h>
  58. #include <linux/phy.h>
  59. #include <linux/platform_device.h>
  60. #include <linux/cpu.h>
  61. #include <linux/io.h>
  62. #include <asm/mipsregs.h>
  63. #include <asm/irq.h>
  64. #include <asm/processor.h>
  65. #include <au1000.h>
  66. #include <au1xxx_eth.h>
  67. #include <prom.h>
  68. #include "au1000_eth.h"
  69. #ifdef AU1000_ETH_DEBUG
  70. static int au1000_debug = 5;
  71. #else
  72. static int au1000_debug = 3;
  73. #endif
  74. #define AU1000_DEF_MSG_ENABLE (NETIF_MSG_DRV | \
  75. NETIF_MSG_PROBE | \
  76. NETIF_MSG_LINK)
  77. #define DRV_NAME "au1000_eth"
  78. #define DRV_VERSION "1.7"
  79. #define DRV_AUTHOR "Pete Popov <ppopov@embeddedalley.com>"
  80. #define DRV_DESC "Au1xxx on-chip Ethernet driver"
  81. MODULE_AUTHOR(DRV_AUTHOR);
  82. MODULE_DESCRIPTION(DRV_DESC);
  83. MODULE_LICENSE("GPL");
  84. MODULE_VERSION(DRV_VERSION);
  85. /*
  86. * Theory of operation
  87. *
  88. * The Au1000 MACs use a simple rx and tx descriptor ring scheme.
  89. * There are four receive and four transmit descriptors. These
  90. * descriptors are not in memory; rather, they are just a set of
  91. * hardware registers.
  92. *
  93. * Since the Au1000 has a coherent data cache, the receive and
  94. * transmit buffers are allocated from the KSEG0 segment. The
  95. * hardware registers, however, are still mapped at KSEG1 to
  96. * make sure there's no out-of-order writes, and that all writes
  97. * complete immediately.
  98. */
  99. struct au1000_private *au_macs[NUM_ETH_INTERFACES];
  100. /*
  101. * board-specific configurations
  102. *
  103. * PHY detection algorithm
  104. *
  105. * If phy_static_config is undefined, the PHY setup is
  106. * autodetected:
  107. *
  108. * mii_probe() first searches the current MAC's MII bus for a PHY,
  109. * selecting the first (or last, if phy_search_highest_addr is
  110. * defined) PHY address not already claimed by another netdev.
  111. *
  112. * If nothing was found that way when searching for the 2nd ethernet
  113. * controller's PHY and phy1_search_mac0 is defined, then
  114. * the first MII bus is searched as well for an unclaimed PHY; this is
  115. * needed in case of a dual-PHY accessible only through the MAC0's MII
  116. * bus.
  117. *
  118. * Finally, if no PHY is found, then the corresponding ethernet
  119. * controller is not registered to the network subsystem.
  120. */
  121. /* autodetection defaults: phy1_search_mac0 */
  122. /* static PHY setup
  123. *
  124. * most boards PHY setup should be detectable properly with the
  125. * autodetection algorithm in mii_probe(), but in some cases (e.g. if
  126. * you have a switch attached, or want to use the PHY's interrupt
  127. * notification capabilities) you can provide a static PHY
  128. * configuration here
  129. *
  130. * IRQs may only be set, if a PHY address was configured
  131. * If a PHY address is given, also a bus id is required to be set
  132. *
  133. * ps: make sure the used irqs are configured properly in the board
  134. * specific irq-map
  135. */
  136. static void au1000_enable_mac(struct net_device *dev, int force_reset)
  137. {
  138. unsigned long flags;
  139. struct au1000_private *aup = netdev_priv(dev);
  140. spin_lock_irqsave(&aup->lock, flags);
  141. if (force_reset || (!aup->mac_enabled)) {
  142. writel(MAC_EN_CLOCK_ENABLE, &aup->enable);
  143. au_sync_delay(2);
  144. writel((MAC_EN_RESET0 | MAC_EN_RESET1 | MAC_EN_RESET2
  145. | MAC_EN_CLOCK_ENABLE), &aup->enable);
  146. au_sync_delay(2);
  147. aup->mac_enabled = 1;
  148. }
  149. spin_unlock_irqrestore(&aup->lock, flags);
  150. }
  151. /*
  152. * MII operations
  153. */
  154. static int au1000_mdio_read(struct net_device *dev, int phy_addr, int reg)
  155. {
  156. struct au1000_private *aup = netdev_priv(dev);
  157. u32 *const mii_control_reg = &aup->mac->mii_control;
  158. u32 *const mii_data_reg = &aup->mac->mii_data;
  159. u32 timedout = 20;
  160. u32 mii_control;
  161. while (readl(mii_control_reg) & MAC_MII_BUSY) {
  162. mdelay(1);
  163. if (--timedout == 0) {
  164. netdev_err(dev, "read_MII busy timeout!!\n");
  165. return -1;
  166. }
  167. }
  168. mii_control = MAC_SET_MII_SELECT_REG(reg) |
  169. MAC_SET_MII_SELECT_PHY(phy_addr) | MAC_MII_READ;
  170. writel(mii_control, mii_control_reg);
  171. timedout = 20;
  172. while (readl(mii_control_reg) & MAC_MII_BUSY) {
  173. mdelay(1);
  174. if (--timedout == 0) {
  175. netdev_err(dev, "mdio_read busy timeout!!\n");
  176. return -1;
  177. }
  178. }
  179. return readl(mii_data_reg);
  180. }
  181. static void au1000_mdio_write(struct net_device *dev, int phy_addr,
  182. int reg, u16 value)
  183. {
  184. struct au1000_private *aup = netdev_priv(dev);
  185. u32 *const mii_control_reg = &aup->mac->mii_control;
  186. u32 *const mii_data_reg = &aup->mac->mii_data;
  187. u32 timedout = 20;
  188. u32 mii_control;
  189. while (readl(mii_control_reg) & MAC_MII_BUSY) {
  190. mdelay(1);
  191. if (--timedout == 0) {
  192. netdev_err(dev, "mdio_write busy timeout!!\n");
  193. return;
  194. }
  195. }
  196. mii_control = MAC_SET_MII_SELECT_REG(reg) |
  197. MAC_SET_MII_SELECT_PHY(phy_addr) | MAC_MII_WRITE;
  198. writel(value, mii_data_reg);
  199. writel(mii_control, mii_control_reg);
  200. }
  201. static int au1000_mdiobus_read(struct mii_bus *bus, int phy_addr, int regnum)
  202. {
  203. /* WARNING: bus->phy_map[phy_addr].attached_dev == dev does
  204. * _NOT_ hold (e.g. when PHY is accessed through other MAC's MII bus)
  205. */
  206. struct net_device *const dev = bus->priv;
  207. /* make sure the MAC associated with this
  208. * mii_bus is enabled
  209. */
  210. au1000_enable_mac(dev, 0);
  211. return au1000_mdio_read(dev, phy_addr, regnum);
  212. }
  213. static int au1000_mdiobus_write(struct mii_bus *bus, int phy_addr, int regnum,
  214. u16 value)
  215. {
  216. struct net_device *const dev = bus->priv;
  217. /* make sure the MAC associated with this
  218. * mii_bus is enabled
  219. */
  220. au1000_enable_mac(dev, 0);
  221. au1000_mdio_write(dev, phy_addr, regnum, value);
  222. return 0;
  223. }
  224. static int au1000_mdiobus_reset(struct mii_bus *bus)
  225. {
  226. struct net_device *const dev = bus->priv;
  227. /* make sure the MAC associated with this
  228. * mii_bus is enabled
  229. */
  230. au1000_enable_mac(dev, 0);
  231. return 0;
  232. }
  233. static void au1000_hard_stop(struct net_device *dev)
  234. {
  235. struct au1000_private *aup = netdev_priv(dev);
  236. u32 reg;
  237. netif_dbg(aup, drv, dev, "hard stop\n");
  238. reg = readl(&aup->mac->control);
  239. reg &= ~(MAC_RX_ENABLE | MAC_TX_ENABLE);
  240. writel(reg, &aup->mac->control);
  241. au_sync_delay(10);
  242. }
  243. static void au1000_enable_rx_tx(struct net_device *dev)
  244. {
  245. struct au1000_private *aup = netdev_priv(dev);
  246. u32 reg;
  247. netif_dbg(aup, hw, dev, "enable_rx_tx\n");
  248. reg = readl(&aup->mac->control);
  249. reg |= (MAC_RX_ENABLE | MAC_TX_ENABLE);
  250. writel(reg, &aup->mac->control);
  251. au_sync_delay(10);
  252. }
  253. static void
  254. au1000_adjust_link(struct net_device *dev)
  255. {
  256. struct au1000_private *aup = netdev_priv(dev);
  257. struct phy_device *phydev = aup->phy_dev;
  258. unsigned long flags;
  259. u32 reg;
  260. int status_change = 0;
  261. BUG_ON(!aup->phy_dev);
  262. spin_lock_irqsave(&aup->lock, flags);
  263. if (phydev->link && (aup->old_speed != phydev->speed)) {
  264. /* speed changed */
  265. switch (phydev->speed) {
  266. case SPEED_10:
  267. case SPEED_100:
  268. break;
  269. default:
  270. netdev_warn(dev, "Speed (%d) is not 10/100 ???\n",
  271. phydev->speed);
  272. break;
  273. }
  274. aup->old_speed = phydev->speed;
  275. status_change = 1;
  276. }
  277. if (phydev->link && (aup->old_duplex != phydev->duplex)) {
  278. /* duplex mode changed */
  279. /* switching duplex mode requires to disable rx and tx! */
  280. au1000_hard_stop(dev);
  281. reg = readl(&aup->mac->control);
  282. if (DUPLEX_FULL == phydev->duplex) {
  283. reg |= MAC_FULL_DUPLEX;
  284. reg &= ~MAC_DISABLE_RX_OWN;
  285. } else {
  286. reg &= ~MAC_FULL_DUPLEX;
  287. reg |= MAC_DISABLE_RX_OWN;
  288. }
  289. writel(reg, &aup->mac->control);
  290. au_sync_delay(1);
  291. au1000_enable_rx_tx(dev);
  292. aup->old_duplex = phydev->duplex;
  293. status_change = 1;
  294. }
  295. if (phydev->link != aup->old_link) {
  296. /* link state changed */
  297. if (!phydev->link) {
  298. /* link went down */
  299. aup->old_speed = 0;
  300. aup->old_duplex = -1;
  301. }
  302. aup->old_link = phydev->link;
  303. status_change = 1;
  304. }
  305. spin_unlock_irqrestore(&aup->lock, flags);
  306. if (status_change) {
  307. if (phydev->link)
  308. netdev_info(dev, "link up (%d/%s)\n",
  309. phydev->speed,
  310. DUPLEX_FULL == phydev->duplex ? "Full" : "Half");
  311. else
  312. netdev_info(dev, "link down\n");
  313. }
  314. }
  315. static int au1000_mii_probe(struct net_device *dev)
  316. {
  317. struct au1000_private *const aup = netdev_priv(dev);
  318. struct phy_device *phydev = NULL;
  319. int phy_addr;
  320. if (aup->phy_static_config) {
  321. BUG_ON(aup->mac_id < 0 || aup->mac_id > 1);
  322. if (aup->phy_addr)
  323. phydev = aup->mii_bus->phy_map[aup->phy_addr];
  324. else
  325. netdev_info(dev, "using PHY-less setup\n");
  326. return 0;
  327. }
  328. /* find the first (lowest address) PHY
  329. * on the current MAC's MII bus
  330. */
  331. for (phy_addr = 0; phy_addr < PHY_MAX_ADDR; phy_addr++)
  332. if (aup->mii_bus->phy_map[phy_addr]) {
  333. phydev = aup->mii_bus->phy_map[phy_addr];
  334. if (!aup->phy_search_highest_addr)
  335. /* break out with first one found */
  336. break;
  337. }
  338. if (aup->phy1_search_mac0) {
  339. /* try harder to find a PHY */
  340. if (!phydev && (aup->mac_id == 1)) {
  341. /* no PHY found, maybe we have a dual PHY? */
  342. dev_info(&dev->dev, ": no PHY found on MAC1, "
  343. "let's see if it's attached to MAC0...\n");
  344. /* find the first (lowest address) non-attached
  345. * PHY on the MAC0 MII bus
  346. */
  347. for (phy_addr = 0; phy_addr < PHY_MAX_ADDR; phy_addr++) {
  348. struct phy_device *const tmp_phydev =
  349. aup->mii_bus->phy_map[phy_addr];
  350. if (aup->mac_id == 1)
  351. break;
  352. /* no PHY here... */
  353. if (!tmp_phydev)
  354. continue;
  355. /* already claimed by MAC0 */
  356. if (tmp_phydev->attached_dev)
  357. continue;
  358. phydev = tmp_phydev;
  359. break; /* found it */
  360. }
  361. }
  362. }
  363. if (!phydev) {
  364. netdev_err(dev, "no PHY found\n");
  365. return -1;
  366. }
  367. /* now we are supposed to have a proper phydev, to attach to... */
  368. BUG_ON(phydev->attached_dev);
  369. phydev = phy_connect(dev, dev_name(&phydev->dev), &au1000_adjust_link,
  370. 0, PHY_INTERFACE_MODE_MII);
  371. if (IS_ERR(phydev)) {
  372. netdev_err(dev, "Could not attach to PHY\n");
  373. return PTR_ERR(phydev);
  374. }
  375. /* mask with MAC supported features */
  376. phydev->supported &= (SUPPORTED_10baseT_Half
  377. | SUPPORTED_10baseT_Full
  378. | SUPPORTED_100baseT_Half
  379. | SUPPORTED_100baseT_Full
  380. | SUPPORTED_Autoneg
  381. /* | SUPPORTED_Pause | SUPPORTED_Asym_Pause */
  382. | SUPPORTED_MII
  383. | SUPPORTED_TP);
  384. phydev->advertising = phydev->supported;
  385. aup->old_link = 0;
  386. aup->old_speed = 0;
  387. aup->old_duplex = -1;
  388. aup->phy_dev = phydev;
  389. netdev_info(dev, "attached PHY driver [%s] "
  390. "(mii_bus:phy_addr=%s, irq=%d)\n",
  391. phydev->drv->name, dev_name(&phydev->dev), phydev->irq);
  392. return 0;
  393. }
  394. /*
  395. * Buffer allocation/deallocation routines. The buffer descriptor returned
  396. * has the virtual and dma address of a buffer suitable for
  397. * both, receive and transmit operations.
  398. */
  399. static struct db_dest *au1000_GetFreeDB(struct au1000_private *aup)
  400. {
  401. struct db_dest *pDB;
  402. pDB = aup->pDBfree;
  403. if (pDB)
  404. aup->pDBfree = pDB->pnext;
  405. return pDB;
  406. }
  407. void au1000_ReleaseDB(struct au1000_private *aup, struct db_dest *pDB)
  408. {
  409. struct db_dest *pDBfree = aup->pDBfree;
  410. if (pDBfree)
  411. pDBfree->pnext = pDB;
  412. aup->pDBfree = pDB;
  413. }
  414. static void au1000_reset_mac_unlocked(struct net_device *dev)
  415. {
  416. struct au1000_private *const aup = netdev_priv(dev);
  417. int i;
  418. au1000_hard_stop(dev);
  419. writel(MAC_EN_CLOCK_ENABLE, &aup->enable);
  420. au_sync_delay(2);
  421. writel(0, &aup->enable);
  422. au_sync_delay(2);
  423. aup->tx_full = 0;
  424. for (i = 0; i < NUM_RX_DMA; i++) {
  425. /* reset control bits */
  426. aup->rx_dma_ring[i]->buff_stat &= ~0xf;
  427. }
  428. for (i = 0; i < NUM_TX_DMA; i++) {
  429. /* reset control bits */
  430. aup->tx_dma_ring[i]->buff_stat &= ~0xf;
  431. }
  432. aup->mac_enabled = 0;
  433. }
  434. static void au1000_reset_mac(struct net_device *dev)
  435. {
  436. struct au1000_private *const aup = netdev_priv(dev);
  437. unsigned long flags;
  438. netif_dbg(aup, hw, dev, "reset mac, aup %x\n",
  439. (unsigned)aup);
  440. spin_lock_irqsave(&aup->lock, flags);
  441. au1000_reset_mac_unlocked(dev);
  442. spin_unlock_irqrestore(&aup->lock, flags);
  443. }
  444. /*
  445. * Setup the receive and transmit "rings". These pointers are the addresses
  446. * of the rx and tx MAC DMA registers so they are fixed by the hardware --
  447. * these are not descriptors sitting in memory.
  448. */
  449. static void
  450. au1000_setup_hw_rings(struct au1000_private *aup, u32 rx_base, u32 tx_base)
  451. {
  452. int i;
  453. for (i = 0; i < NUM_RX_DMA; i++) {
  454. aup->rx_dma_ring[i] =
  455. (struct rx_dma *)
  456. (rx_base + sizeof(struct rx_dma)*i);
  457. }
  458. for (i = 0; i < NUM_TX_DMA; i++) {
  459. aup->tx_dma_ring[i] =
  460. (struct tx_dma *)
  461. (tx_base + sizeof(struct tx_dma)*i);
  462. }
  463. }
  464. /*
  465. * ethtool operations
  466. */
  467. static int au1000_get_settings(struct net_device *dev, struct ethtool_cmd *cmd)
  468. {
  469. struct au1000_private *aup = netdev_priv(dev);
  470. if (aup->phy_dev)
  471. return phy_ethtool_gset(aup->phy_dev, cmd);
  472. return -EINVAL;
  473. }
  474. static int au1000_set_settings(struct net_device *dev, struct ethtool_cmd *cmd)
  475. {
  476. struct au1000_private *aup = netdev_priv(dev);
  477. if (!capable(CAP_NET_ADMIN))
  478. return -EPERM;
  479. if (aup->phy_dev)
  480. return phy_ethtool_sset(aup->phy_dev, cmd);
  481. return -EINVAL;
  482. }
  483. static void
  484. au1000_get_drvinfo(struct net_device *dev, struct ethtool_drvinfo *info)
  485. {
  486. struct au1000_private *aup = netdev_priv(dev);
  487. strcpy(info->driver, DRV_NAME);
  488. strcpy(info->version, DRV_VERSION);
  489. info->fw_version[0] = '\0';
  490. sprintf(info->bus_info, "%s %d", DRV_NAME, aup->mac_id);
  491. info->regdump_len = 0;
  492. }
  493. static void au1000_set_msglevel(struct net_device *dev, u32 value)
  494. {
  495. struct au1000_private *aup = netdev_priv(dev);
  496. aup->msg_enable = value;
  497. }
  498. static u32 au1000_get_msglevel(struct net_device *dev)
  499. {
  500. struct au1000_private *aup = netdev_priv(dev);
  501. return aup->msg_enable;
  502. }
  503. static const struct ethtool_ops au1000_ethtool_ops = {
  504. .get_settings = au1000_get_settings,
  505. .set_settings = au1000_set_settings,
  506. .get_drvinfo = au1000_get_drvinfo,
  507. .get_link = ethtool_op_get_link,
  508. .get_msglevel = au1000_get_msglevel,
  509. .set_msglevel = au1000_set_msglevel,
  510. };
  511. /*
  512. * Initialize the interface.
  513. *
  514. * When the device powers up, the clocks are disabled and the
  515. * mac is in reset state. When the interface is closed, we
  516. * do the same -- reset the device and disable the clocks to
  517. * conserve power. Thus, whenever au1000_init() is called,
  518. * the device should already be in reset state.
  519. */
  520. static int au1000_init(struct net_device *dev)
  521. {
  522. struct au1000_private *aup = netdev_priv(dev);
  523. unsigned long flags;
  524. int i;
  525. u32 control;
  526. netif_dbg(aup, hw, dev, "au1000_init\n");
  527. /* bring the device out of reset */
  528. au1000_enable_mac(dev, 1);
  529. spin_lock_irqsave(&aup->lock, flags);
  530. writel(0, &aup->mac->control);
  531. aup->tx_head = (aup->tx_dma_ring[0]->buff_stat & 0xC) >> 2;
  532. aup->tx_tail = aup->tx_head;
  533. aup->rx_head = (aup->rx_dma_ring[0]->buff_stat & 0xC) >> 2;
  534. writel(dev->dev_addr[5]<<8 | dev->dev_addr[4],
  535. &aup->mac->mac_addr_high);
  536. writel(dev->dev_addr[3]<<24 | dev->dev_addr[2]<<16 |
  537. dev->dev_addr[1]<<8 | dev->dev_addr[0],
  538. &aup->mac->mac_addr_low);
  539. for (i = 0; i < NUM_RX_DMA; i++)
  540. aup->rx_dma_ring[i]->buff_stat |= RX_DMA_ENABLE;
  541. au_sync();
  542. control = MAC_RX_ENABLE | MAC_TX_ENABLE;
  543. #ifndef CONFIG_CPU_LITTLE_ENDIAN
  544. control |= MAC_BIG_ENDIAN;
  545. #endif
  546. if (aup->phy_dev) {
  547. if (aup->phy_dev->link && (DUPLEX_FULL == aup->phy_dev->duplex))
  548. control |= MAC_FULL_DUPLEX;
  549. else
  550. control |= MAC_DISABLE_RX_OWN;
  551. } else { /* PHY-less op, assume full-duplex */
  552. control |= MAC_FULL_DUPLEX;
  553. }
  554. writel(control, &aup->mac->control);
  555. writel(0x8100, &aup->mac->vlan1_tag); /* activate vlan support */
  556. au_sync();
  557. spin_unlock_irqrestore(&aup->lock, flags);
  558. return 0;
  559. }
  560. static inline void au1000_update_rx_stats(struct net_device *dev, u32 status)
  561. {
  562. struct net_device_stats *ps = &dev->stats;
  563. ps->rx_packets++;
  564. if (status & RX_MCAST_FRAME)
  565. ps->multicast++;
  566. if (status & RX_ERROR) {
  567. ps->rx_errors++;
  568. if (status & RX_MISSED_FRAME)
  569. ps->rx_missed_errors++;
  570. if (status & (RX_OVERLEN | RX_RUNT | RX_LEN_ERROR))
  571. ps->rx_length_errors++;
  572. if (status & RX_CRC_ERROR)
  573. ps->rx_crc_errors++;
  574. if (status & RX_COLL)
  575. ps->collisions++;
  576. } else
  577. ps->rx_bytes += status & RX_FRAME_LEN_MASK;
  578. }
  579. /*
  580. * Au1000 receive routine.
  581. */
  582. static int au1000_rx(struct net_device *dev)
  583. {
  584. struct au1000_private *aup = netdev_priv(dev);
  585. struct sk_buff *skb;
  586. struct rx_dma *prxd;
  587. u32 buff_stat, status;
  588. struct db_dest *pDB;
  589. u32 frmlen;
  590. netif_dbg(aup, rx_status, dev, "au1000_rx head %d\n", aup->rx_head);
  591. prxd = aup->rx_dma_ring[aup->rx_head];
  592. buff_stat = prxd->buff_stat;
  593. while (buff_stat & RX_T_DONE) {
  594. status = prxd->status;
  595. pDB = aup->rx_db_inuse[aup->rx_head];
  596. au1000_update_rx_stats(dev, status);
  597. if (!(status & RX_ERROR)) {
  598. /* good frame */
  599. frmlen = (status & RX_FRAME_LEN_MASK);
  600. frmlen -= 4; /* Remove FCS */
  601. skb = dev_alloc_skb(frmlen + 2);
  602. if (skb == NULL) {
  603. netdev_err(dev, "Memory squeeze, dropping packet.\n");
  604. dev->stats.rx_dropped++;
  605. continue;
  606. }
  607. skb_reserve(skb, 2); /* 16 byte IP header align */
  608. skb_copy_to_linear_data(skb,
  609. (unsigned char *)pDB->vaddr, frmlen);
  610. skb_put(skb, frmlen);
  611. skb->protocol = eth_type_trans(skb, dev);
  612. netif_rx(skb); /* pass the packet to upper layers */
  613. } else {
  614. if (au1000_debug > 4) {
  615. pr_err("rx_error(s):");
  616. if (status & RX_MISSED_FRAME)
  617. pr_cont(" miss");
  618. if (status & RX_WDOG_TIMER)
  619. pr_cont(" wdog");
  620. if (status & RX_RUNT)
  621. pr_cont(" runt");
  622. if (status & RX_OVERLEN)
  623. pr_cont(" overlen");
  624. if (status & RX_COLL)
  625. pr_cont(" coll");
  626. if (status & RX_MII_ERROR)
  627. pr_cont(" mii error");
  628. if (status & RX_CRC_ERROR)
  629. pr_cont(" crc error");
  630. if (status & RX_LEN_ERROR)
  631. pr_cont(" len error");
  632. if (status & RX_U_CNTRL_FRAME)
  633. pr_cont(" u control frame");
  634. pr_cont("\n");
  635. }
  636. }
  637. prxd->buff_stat = (u32)(pDB->dma_addr | RX_DMA_ENABLE);
  638. aup->rx_head = (aup->rx_head + 1) & (NUM_RX_DMA - 1);
  639. au_sync();
  640. /* next descriptor */
  641. prxd = aup->rx_dma_ring[aup->rx_head];
  642. buff_stat = prxd->buff_stat;
  643. }
  644. return 0;
  645. }
  646. static void au1000_update_tx_stats(struct net_device *dev, u32 status)
  647. {
  648. struct au1000_private *aup = netdev_priv(dev);
  649. struct net_device_stats *ps = &dev->stats;
  650. if (status & TX_FRAME_ABORTED) {
  651. if (!aup->phy_dev || (DUPLEX_FULL == aup->phy_dev->duplex)) {
  652. if (status & (TX_JAB_TIMEOUT | TX_UNDERRUN)) {
  653. /* any other tx errors are only valid
  654. * in half duplex mode
  655. */
  656. ps->tx_errors++;
  657. ps->tx_aborted_errors++;
  658. }
  659. } else {
  660. ps->tx_errors++;
  661. ps->tx_aborted_errors++;
  662. if (status & (TX_NO_CARRIER | TX_LOSS_CARRIER))
  663. ps->tx_carrier_errors++;
  664. }
  665. }
  666. }
  667. /*
  668. * Called from the interrupt service routine to acknowledge
  669. * the TX DONE bits. This is a must if the irq is setup as
  670. * edge triggered.
  671. */
  672. static void au1000_tx_ack(struct net_device *dev)
  673. {
  674. struct au1000_private *aup = netdev_priv(dev);
  675. struct tx_dma *ptxd;
  676. ptxd = aup->tx_dma_ring[aup->tx_tail];
  677. while (ptxd->buff_stat & TX_T_DONE) {
  678. au1000_update_tx_stats(dev, ptxd->status);
  679. ptxd->buff_stat &= ~TX_T_DONE;
  680. ptxd->len = 0;
  681. au_sync();
  682. aup->tx_tail = (aup->tx_tail + 1) & (NUM_TX_DMA - 1);
  683. ptxd = aup->tx_dma_ring[aup->tx_tail];
  684. if (aup->tx_full) {
  685. aup->tx_full = 0;
  686. netif_wake_queue(dev);
  687. }
  688. }
  689. }
  690. /*
  691. * Au1000 interrupt service routine.
  692. */
  693. static irqreturn_t au1000_interrupt(int irq, void *dev_id)
  694. {
  695. struct net_device *dev = dev_id;
  696. /* Handle RX interrupts first to minimize chance of overrun */
  697. au1000_rx(dev);
  698. au1000_tx_ack(dev);
  699. return IRQ_RETVAL(1);
  700. }
  701. static int au1000_open(struct net_device *dev)
  702. {
  703. int retval;
  704. struct au1000_private *aup = netdev_priv(dev);
  705. netif_dbg(aup, drv, dev, "open: dev=%p\n", dev);
  706. retval = request_irq(dev->irq, au1000_interrupt, 0,
  707. dev->name, dev);
  708. if (retval) {
  709. netdev_err(dev, "unable to get IRQ %d\n", dev->irq);
  710. return retval;
  711. }
  712. retval = au1000_init(dev);
  713. if (retval) {
  714. netdev_err(dev, "error in au1000_init\n");
  715. free_irq(dev->irq, dev);
  716. return retval;
  717. }
  718. if (aup->phy_dev) {
  719. /* cause the PHY state machine to schedule a link state check */
  720. aup->phy_dev->state = PHY_CHANGELINK;
  721. phy_start(aup->phy_dev);
  722. }
  723. netif_start_queue(dev);
  724. netif_dbg(aup, drv, dev, "open: Initialization done.\n");
  725. return 0;
  726. }
  727. static int au1000_close(struct net_device *dev)
  728. {
  729. unsigned long flags;
  730. struct au1000_private *const aup = netdev_priv(dev);
  731. netif_dbg(aup, drv, dev, "close: dev=%p\n", dev);
  732. if (aup->phy_dev)
  733. phy_stop(aup->phy_dev);
  734. spin_lock_irqsave(&aup->lock, flags);
  735. au1000_reset_mac_unlocked(dev);
  736. /* stop the device */
  737. netif_stop_queue(dev);
  738. /* disable the interrupt */
  739. free_irq(dev->irq, dev);
  740. spin_unlock_irqrestore(&aup->lock, flags);
  741. return 0;
  742. }
  743. /*
  744. * Au1000 transmit routine.
  745. */
  746. static netdev_tx_t au1000_tx(struct sk_buff *skb, struct net_device *dev)
  747. {
  748. struct au1000_private *aup = netdev_priv(dev);
  749. struct net_device_stats *ps = &dev->stats;
  750. struct tx_dma *ptxd;
  751. u32 buff_stat;
  752. struct db_dest *pDB;
  753. int i;
  754. netif_dbg(aup, tx_queued, dev, "tx: aup %x len=%d, data=%p, head %d\n",
  755. (unsigned)aup, skb->len,
  756. skb->data, aup->tx_head);
  757. ptxd = aup->tx_dma_ring[aup->tx_head];
  758. buff_stat = ptxd->buff_stat;
  759. if (buff_stat & TX_DMA_ENABLE) {
  760. /* We've wrapped around and the transmitter is still busy */
  761. netif_stop_queue(dev);
  762. aup->tx_full = 1;
  763. return NETDEV_TX_BUSY;
  764. } else if (buff_stat & TX_T_DONE) {
  765. au1000_update_tx_stats(dev, ptxd->status);
  766. ptxd->len = 0;
  767. }
  768. if (aup->tx_full) {
  769. aup->tx_full = 0;
  770. netif_wake_queue(dev);
  771. }
  772. pDB = aup->tx_db_inuse[aup->tx_head];
  773. skb_copy_from_linear_data(skb, (void *)pDB->vaddr, skb->len);
  774. if (skb->len < ETH_ZLEN) {
  775. for (i = skb->len; i < ETH_ZLEN; i++)
  776. ((char *)pDB->vaddr)[i] = 0;
  777. ptxd->len = ETH_ZLEN;
  778. } else
  779. ptxd->len = skb->len;
  780. ps->tx_packets++;
  781. ps->tx_bytes += ptxd->len;
  782. ptxd->buff_stat = pDB->dma_addr | TX_DMA_ENABLE;
  783. au_sync();
  784. dev_kfree_skb(skb);
  785. aup->tx_head = (aup->tx_head + 1) & (NUM_TX_DMA - 1);
  786. return NETDEV_TX_OK;
  787. }
  788. /*
  789. * The Tx ring has been full longer than the watchdog timeout
  790. * value. The transmitter must be hung?
  791. */
  792. static void au1000_tx_timeout(struct net_device *dev)
  793. {
  794. netdev_err(dev, "au1000_tx_timeout: dev=%p\n", dev);
  795. au1000_reset_mac(dev);
  796. au1000_init(dev);
  797. dev->trans_start = jiffies; /* prevent tx timeout */
  798. netif_wake_queue(dev);
  799. }
  800. static void au1000_multicast_list(struct net_device *dev)
  801. {
  802. struct au1000_private *aup = netdev_priv(dev);
  803. u32 reg;
  804. netif_dbg(aup, drv, dev, "%s: flags=%x\n", __func__, dev->flags);
  805. reg = readl(&aup->mac->control);
  806. if (dev->flags & IFF_PROMISC) { /* Set promiscuous. */
  807. reg |= MAC_PROMISCUOUS;
  808. } else if ((dev->flags & IFF_ALLMULTI) ||
  809. netdev_mc_count(dev) > MULTICAST_FILTER_LIMIT) {
  810. reg |= MAC_PASS_ALL_MULTI;
  811. reg &= ~MAC_PROMISCUOUS;
  812. netdev_info(dev, "Pass all multicast\n");
  813. } else {
  814. struct netdev_hw_addr *ha;
  815. u32 mc_filter[2]; /* Multicast hash filter */
  816. mc_filter[1] = mc_filter[0] = 0;
  817. netdev_for_each_mc_addr(ha, dev)
  818. set_bit(ether_crc(ETH_ALEN, ha->addr)>>26,
  819. (long *)mc_filter);
  820. writel(mc_filter[1], &aup->mac->multi_hash_high);
  821. writel(mc_filter[0], &aup->mac->multi_hash_low);
  822. reg &= ~MAC_PROMISCUOUS;
  823. reg |= MAC_HASH_MODE;
  824. }
  825. writel(reg, &aup->mac->control);
  826. }
  827. static int au1000_ioctl(struct net_device *dev, struct ifreq *rq, int cmd)
  828. {
  829. struct au1000_private *aup = netdev_priv(dev);
  830. if (!netif_running(dev))
  831. return -EINVAL;
  832. if (!aup->phy_dev)
  833. return -EINVAL; /* PHY not controllable */
  834. return phy_mii_ioctl(aup->phy_dev, rq, cmd);
  835. }
  836. static const struct net_device_ops au1000_netdev_ops = {
  837. .ndo_open = au1000_open,
  838. .ndo_stop = au1000_close,
  839. .ndo_start_xmit = au1000_tx,
  840. .ndo_set_multicast_list = au1000_multicast_list,
  841. .ndo_do_ioctl = au1000_ioctl,
  842. .ndo_tx_timeout = au1000_tx_timeout,
  843. .ndo_set_mac_address = eth_mac_addr,
  844. .ndo_validate_addr = eth_validate_addr,
  845. .ndo_change_mtu = eth_change_mtu,
  846. };
  847. static int __devinit au1000_probe(struct platform_device *pdev)
  848. {
  849. static unsigned version_printed;
  850. struct au1000_private *aup = NULL;
  851. struct au1000_eth_platform_data *pd;
  852. struct net_device *dev = NULL;
  853. struct db_dest *pDB, *pDBfree;
  854. int irq, i, err = 0;
  855. struct resource *base, *macen;
  856. base = platform_get_resource(pdev, IORESOURCE_MEM, 0);
  857. if (!base) {
  858. dev_err(&pdev->dev, "failed to retrieve base register\n");
  859. err = -ENODEV;
  860. goto out;
  861. }
  862. macen = platform_get_resource(pdev, IORESOURCE_MEM, 1);
  863. if (!macen) {
  864. dev_err(&pdev->dev, "failed to retrieve MAC Enable register\n");
  865. err = -ENODEV;
  866. goto out;
  867. }
  868. irq = platform_get_irq(pdev, 0);
  869. if (irq < 0) {
  870. dev_err(&pdev->dev, "failed to retrieve IRQ\n");
  871. err = -ENODEV;
  872. goto out;
  873. }
  874. if (!request_mem_region(base->start, resource_size(base),
  875. pdev->name)) {
  876. dev_err(&pdev->dev, "failed to request memory region for base registers\n");
  877. err = -ENXIO;
  878. goto out;
  879. }
  880. if (!request_mem_region(macen->start, resource_size(macen),
  881. pdev->name)) {
  882. dev_err(&pdev->dev, "failed to request memory region for MAC enable register\n");
  883. err = -ENXIO;
  884. goto err_request;
  885. }
  886. dev = alloc_etherdev(sizeof(struct au1000_private));
  887. if (!dev) {
  888. dev_err(&pdev->dev, "alloc_etherdev failed\n");
  889. err = -ENOMEM;
  890. goto err_alloc;
  891. }
  892. SET_NETDEV_DEV(dev, &pdev->dev);
  893. platform_set_drvdata(pdev, dev);
  894. aup = netdev_priv(dev);
  895. spin_lock_init(&aup->lock);
  896. aup->msg_enable = (au1000_debug < 4 ?
  897. AU1000_DEF_MSG_ENABLE : au1000_debug);
  898. /* Allocate the data buffers
  899. * Snooping works fine with eth on all au1xxx
  900. */
  901. aup->vaddr = (u32)dma_alloc_noncoherent(NULL, MAX_BUF_SIZE *
  902. (NUM_TX_BUFFS + NUM_RX_BUFFS),
  903. &aup->dma_addr, 0);
  904. if (!aup->vaddr) {
  905. dev_err(&pdev->dev, "failed to allocate data buffers\n");
  906. err = -ENOMEM;
  907. goto err_vaddr;
  908. }
  909. /* aup->mac is the base address of the MAC's registers */
  910. aup->mac = (struct mac_reg *)
  911. ioremap_nocache(base->start, resource_size(base));
  912. if (!aup->mac) {
  913. dev_err(&pdev->dev, "failed to ioremap MAC registers\n");
  914. err = -ENXIO;
  915. goto err_remap1;
  916. }
  917. /* Setup some variables for quick register address access */
  918. aup->enable = (u32 *)ioremap_nocache(macen->start,
  919. resource_size(macen));
  920. if (!aup->enable) {
  921. dev_err(&pdev->dev, "failed to ioremap MAC enable register\n");
  922. err = -ENXIO;
  923. goto err_remap2;
  924. }
  925. aup->mac_id = pdev->id;
  926. if (pdev->id == 0)
  927. au1000_setup_hw_rings(aup, MAC0_RX_DMA_ADDR, MAC0_TX_DMA_ADDR);
  928. else if (pdev->id == 1)
  929. au1000_setup_hw_rings(aup, MAC1_RX_DMA_ADDR, MAC1_TX_DMA_ADDR);
  930. /* set a random MAC now in case platform_data doesn't provide one */
  931. random_ether_addr(dev->dev_addr);
  932. writel(0, &aup->enable);
  933. aup->mac_enabled = 0;
  934. pd = pdev->dev.platform_data;
  935. if (!pd) {
  936. dev_info(&pdev->dev, "no platform_data passed,"
  937. " PHY search on MAC0\n");
  938. aup->phy1_search_mac0 = 1;
  939. } else {
  940. if (is_valid_ether_addr(pd->mac))
  941. memcpy(dev->dev_addr, pd->mac, 6);
  942. aup->phy_static_config = pd->phy_static_config;
  943. aup->phy_search_highest_addr = pd->phy_search_highest_addr;
  944. aup->phy1_search_mac0 = pd->phy1_search_mac0;
  945. aup->phy_addr = pd->phy_addr;
  946. aup->phy_busid = pd->phy_busid;
  947. aup->phy_irq = pd->phy_irq;
  948. }
  949. if (aup->phy_busid && aup->phy_busid > 0) {
  950. dev_err(&pdev->dev, "MAC0-associated PHY attached 2nd MACs MII bus not supported yet\n");
  951. err = -ENODEV;
  952. goto err_mdiobus_alloc;
  953. }
  954. aup->mii_bus = mdiobus_alloc();
  955. if (aup->mii_bus == NULL) {
  956. dev_err(&pdev->dev, "failed to allocate mdiobus structure\n");
  957. err = -ENOMEM;
  958. goto err_mdiobus_alloc;
  959. }
  960. aup->mii_bus->priv = dev;
  961. aup->mii_bus->read = au1000_mdiobus_read;
  962. aup->mii_bus->write = au1000_mdiobus_write;
  963. aup->mii_bus->reset = au1000_mdiobus_reset;
  964. aup->mii_bus->name = "au1000_eth_mii";
  965. snprintf(aup->mii_bus->id, MII_BUS_ID_SIZE, "%x", aup->mac_id);
  966. aup->mii_bus->irq = kmalloc(sizeof(int)*PHY_MAX_ADDR, GFP_KERNEL);
  967. if (aup->mii_bus->irq == NULL)
  968. goto err_out;
  969. for (i = 0; i < PHY_MAX_ADDR; ++i)
  970. aup->mii_bus->irq[i] = PHY_POLL;
  971. /* if known, set corresponding PHY IRQs */
  972. if (aup->phy_static_config)
  973. if (aup->phy_irq && aup->phy_busid == aup->mac_id)
  974. aup->mii_bus->irq[aup->phy_addr] = aup->phy_irq;
  975. err = mdiobus_register(aup->mii_bus);
  976. if (err) {
  977. dev_err(&pdev->dev, "failed to register MDIO bus\n");
  978. goto err_mdiobus_reg;
  979. }
  980. if (au1000_mii_probe(dev) != 0)
  981. goto err_out;
  982. pDBfree = NULL;
  983. /* setup the data buffer descriptors and attach a buffer to each one */
  984. pDB = aup->db;
  985. for (i = 0; i < (NUM_TX_BUFFS+NUM_RX_BUFFS); i++) {
  986. pDB->pnext = pDBfree;
  987. pDBfree = pDB;
  988. pDB->vaddr = (u32 *)((unsigned)aup->vaddr + MAX_BUF_SIZE*i);
  989. pDB->dma_addr = (dma_addr_t)virt_to_bus(pDB->vaddr);
  990. pDB++;
  991. }
  992. aup->pDBfree = pDBfree;
  993. for (i = 0; i < NUM_RX_DMA; i++) {
  994. pDB = au1000_GetFreeDB(aup);
  995. if (!pDB)
  996. goto err_out;
  997. aup->rx_dma_ring[i]->buff_stat = (unsigned)pDB->dma_addr;
  998. aup->rx_db_inuse[i] = pDB;
  999. }
  1000. for (i = 0; i < NUM_TX_DMA; i++) {
  1001. pDB = au1000_GetFreeDB(aup);
  1002. if (!pDB)
  1003. goto err_out;
  1004. aup->tx_dma_ring[i]->buff_stat = (unsigned)pDB->dma_addr;
  1005. aup->tx_dma_ring[i]->len = 0;
  1006. aup->tx_db_inuse[i] = pDB;
  1007. }
  1008. dev->base_addr = base->start;
  1009. dev->irq = irq;
  1010. dev->netdev_ops = &au1000_netdev_ops;
  1011. SET_ETHTOOL_OPS(dev, &au1000_ethtool_ops);
  1012. dev->watchdog_timeo = ETH_TX_TIMEOUT;
  1013. /*
  1014. * The boot code uses the ethernet controller, so reset it to start
  1015. * fresh. au1000_init() expects that the device is in reset state.
  1016. */
  1017. au1000_reset_mac(dev);
  1018. err = register_netdev(dev);
  1019. if (err) {
  1020. netdev_err(dev, "Cannot register net device, aborting.\n");
  1021. goto err_out;
  1022. }
  1023. netdev_info(dev, "Au1xx0 Ethernet found at 0x%lx, irq %d\n",
  1024. (unsigned long)base->start, irq);
  1025. if (version_printed++ == 0)
  1026. pr_info("%s version %s %s\n",
  1027. DRV_NAME, DRV_VERSION, DRV_AUTHOR);
  1028. return 0;
  1029. err_out:
  1030. if (aup->mii_bus != NULL)
  1031. mdiobus_unregister(aup->mii_bus);
  1032. /* here we should have a valid dev plus aup-> register addresses
  1033. * so we can reset the mac properly.
  1034. */
  1035. au1000_reset_mac(dev);
  1036. for (i = 0; i < NUM_RX_DMA; i++) {
  1037. if (aup->rx_db_inuse[i])
  1038. au1000_ReleaseDB(aup, aup->rx_db_inuse[i]);
  1039. }
  1040. for (i = 0; i < NUM_TX_DMA; i++) {
  1041. if (aup->tx_db_inuse[i])
  1042. au1000_ReleaseDB(aup, aup->tx_db_inuse[i]);
  1043. }
  1044. err_mdiobus_reg:
  1045. mdiobus_free(aup->mii_bus);
  1046. err_mdiobus_alloc:
  1047. iounmap(aup->enable);
  1048. err_remap2:
  1049. iounmap(aup->mac);
  1050. err_remap1:
  1051. dma_free_noncoherent(NULL, MAX_BUF_SIZE * (NUM_TX_BUFFS + NUM_RX_BUFFS),
  1052. (void *)aup->vaddr, aup->dma_addr);
  1053. err_vaddr:
  1054. free_netdev(dev);
  1055. err_alloc:
  1056. release_mem_region(macen->start, resource_size(macen));
  1057. err_request:
  1058. release_mem_region(base->start, resource_size(base));
  1059. out:
  1060. return err;
  1061. }
  1062. static int __devexit au1000_remove(struct platform_device *pdev)
  1063. {
  1064. struct net_device *dev = platform_get_drvdata(pdev);
  1065. struct au1000_private *aup = netdev_priv(dev);
  1066. int i;
  1067. struct resource *base, *macen;
  1068. platform_set_drvdata(pdev, NULL);
  1069. unregister_netdev(dev);
  1070. mdiobus_unregister(aup->mii_bus);
  1071. mdiobus_free(aup->mii_bus);
  1072. for (i = 0; i < NUM_RX_DMA; i++)
  1073. if (aup->rx_db_inuse[i])
  1074. au1000_ReleaseDB(aup, aup->rx_db_inuse[i]);
  1075. for (i = 0; i < NUM_TX_DMA; i++)
  1076. if (aup->tx_db_inuse[i])
  1077. au1000_ReleaseDB(aup, aup->tx_db_inuse[i]);
  1078. dma_free_noncoherent(NULL, MAX_BUF_SIZE *
  1079. (NUM_TX_BUFFS + NUM_RX_BUFFS),
  1080. (void *)aup->vaddr, aup->dma_addr);
  1081. iounmap(aup->mac);
  1082. iounmap(aup->enable);
  1083. base = platform_get_resource(pdev, IORESOURCE_MEM, 0);
  1084. release_mem_region(base->start, resource_size(base));
  1085. macen = platform_get_resource(pdev, IORESOURCE_MEM, 1);
  1086. release_mem_region(macen->start, resource_size(macen));
  1087. free_netdev(dev);
  1088. return 0;
  1089. }
  1090. static struct platform_driver au1000_eth_driver = {
  1091. .probe = au1000_probe,
  1092. .remove = __devexit_p(au1000_remove),
  1093. .driver = {
  1094. .name = "au1000-eth",
  1095. .owner = THIS_MODULE,
  1096. },
  1097. };
  1098. MODULE_ALIAS("platform:au1000-eth");
  1099. static int __init au1000_init_module(void)
  1100. {
  1101. return platform_driver_register(&au1000_eth_driver);
  1102. }
  1103. static void __exit au1000_exit_module(void)
  1104. {
  1105. platform_driver_unregister(&au1000_eth_driver);
  1106. }
  1107. module_init(au1000_init_module);
  1108. module_exit(au1000_exit_module);