dhd_sdio.c 108 KB

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  1. /*
  2. * Copyright (c) 2010 Broadcom Corporation
  3. *
  4. * Permission to use, copy, modify, and/or distribute this software for any
  5. * purpose with or without fee is hereby granted, provided that the above
  6. * copyright notice and this permission notice appear in all copies.
  7. *
  8. * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
  9. * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
  10. * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY
  11. * SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
  12. * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN ACTION
  13. * OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF OR IN
  14. * CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
  15. */
  16. #include <linux/types.h>
  17. #include <linux/kernel.h>
  18. #include <linux/kthread.h>
  19. #include <linux/printk.h>
  20. #include <linux/pci_ids.h>
  21. #include <linux/netdevice.h>
  22. #include <linux/interrupt.h>
  23. #include <linux/sched.h>
  24. #include <linux/mmc/sdio.h>
  25. #include <linux/mmc/sdio_func.h>
  26. #include <linux/mmc/card.h>
  27. #include <linux/semaphore.h>
  28. #include <linux/firmware.h>
  29. #include <linux/module.h>
  30. #include <linux/bcma/bcma.h>
  31. #include <asm/unaligned.h>
  32. #include <defs.h>
  33. #include <brcmu_wifi.h>
  34. #include <brcmu_utils.h>
  35. #include <brcm_hw_ids.h>
  36. #include <soc.h>
  37. #include "sdio_host.h"
  38. #include "sdio_chip.h"
  39. #define DCMD_RESP_TIMEOUT 2000 /* In milli second */
  40. #ifdef BCMDBG
  41. #define BRCMF_TRAP_INFO_SIZE 80
  42. #define CBUF_LEN (128)
  43. struct rte_log_le {
  44. __le32 buf; /* Can't be pointer on (64-bit) hosts */
  45. __le32 buf_size;
  46. __le32 idx;
  47. char *_buf_compat; /* Redundant pointer for backward compat. */
  48. };
  49. struct rte_console {
  50. /* Virtual UART
  51. * When there is no UART (e.g. Quickturn),
  52. * the host should write a complete
  53. * input line directly into cbuf and then write
  54. * the length into vcons_in.
  55. * This may also be used when there is a real UART
  56. * (at risk of conflicting with
  57. * the real UART). vcons_out is currently unused.
  58. */
  59. uint vcons_in;
  60. uint vcons_out;
  61. /* Output (logging) buffer
  62. * Console output is written to a ring buffer log_buf at index log_idx.
  63. * The host may read the output when it sees log_idx advance.
  64. * Output will be lost if the output wraps around faster than the host
  65. * polls.
  66. */
  67. struct rte_log_le log_le;
  68. /* Console input line buffer
  69. * Characters are read one at a time into cbuf
  70. * until <CR> is received, then
  71. * the buffer is processed as a command line.
  72. * Also used for virtual UART.
  73. */
  74. uint cbuf_idx;
  75. char cbuf[CBUF_LEN];
  76. };
  77. #endif /* BCMDBG */
  78. #include <chipcommon.h>
  79. #include "dhd.h"
  80. #include "dhd_bus.h"
  81. #include "dhd_proto.h"
  82. #include "dhd_dbg.h"
  83. #define TXQLEN 2048 /* bulk tx queue length */
  84. #define TXHI (TXQLEN - 256) /* turn on flow control above TXHI */
  85. #define TXLOW (TXHI - 256) /* turn off flow control below TXLOW */
  86. #define PRIOMASK 7
  87. #define TXRETRIES 2 /* # of retries for tx frames */
  88. #define BRCMF_RXBOUND 50 /* Default for max rx frames in
  89. one scheduling */
  90. #define BRCMF_TXBOUND 20 /* Default for max tx frames in
  91. one scheduling */
  92. #define BRCMF_TXMINMAX 1 /* Max tx frames if rx still pending */
  93. #define MEMBLOCK 2048 /* Block size used for downloading
  94. of dongle image */
  95. #define MAX_DATA_BUF (32 * 1024) /* Must be large enough to hold
  96. biggest possible glom */
  97. #define BRCMF_FIRSTREAD (1 << 6)
  98. /* SBSDIO_DEVICE_CTL */
  99. /* 1: device will assert busy signal when receiving CMD53 */
  100. #define SBSDIO_DEVCTL_SETBUSY 0x01
  101. /* 1: assertion of sdio interrupt is synchronous to the sdio clock */
  102. #define SBSDIO_DEVCTL_SPI_INTR_SYNC 0x02
  103. /* 1: mask all interrupts to host except the chipActive (rev 8) */
  104. #define SBSDIO_DEVCTL_CA_INT_ONLY 0x04
  105. /* 1: isolate internal sdio signals, put external pads in tri-state; requires
  106. * sdio bus power cycle to clear (rev 9) */
  107. #define SBSDIO_DEVCTL_PADS_ISO 0x08
  108. /* Force SD->SB reset mapping (rev 11) */
  109. #define SBSDIO_DEVCTL_SB_RST_CTL 0x30
  110. /* Determined by CoreControl bit */
  111. #define SBSDIO_DEVCTL_RST_CORECTL 0x00
  112. /* Force backplane reset */
  113. #define SBSDIO_DEVCTL_RST_BPRESET 0x10
  114. /* Force no backplane reset */
  115. #define SBSDIO_DEVCTL_RST_NOBPRESET 0x20
  116. /* direct(mapped) cis space */
  117. /* MAPPED common CIS address */
  118. #define SBSDIO_CIS_BASE_COMMON 0x1000
  119. /* maximum bytes in one CIS */
  120. #define SBSDIO_CIS_SIZE_LIMIT 0x200
  121. /* cis offset addr is < 17 bits */
  122. #define SBSDIO_CIS_OFT_ADDR_MASK 0x1FFFF
  123. /* manfid tuple length, include tuple, link bytes */
  124. #define SBSDIO_CIS_MANFID_TUPLE_LEN 6
  125. /* intstatus */
  126. #define I_SMB_SW0 (1 << 0) /* To SB Mail S/W interrupt 0 */
  127. #define I_SMB_SW1 (1 << 1) /* To SB Mail S/W interrupt 1 */
  128. #define I_SMB_SW2 (1 << 2) /* To SB Mail S/W interrupt 2 */
  129. #define I_SMB_SW3 (1 << 3) /* To SB Mail S/W interrupt 3 */
  130. #define I_SMB_SW_MASK 0x0000000f /* To SB Mail S/W interrupts mask */
  131. #define I_SMB_SW_SHIFT 0 /* To SB Mail S/W interrupts shift */
  132. #define I_HMB_SW0 (1 << 4) /* To Host Mail S/W interrupt 0 */
  133. #define I_HMB_SW1 (1 << 5) /* To Host Mail S/W interrupt 1 */
  134. #define I_HMB_SW2 (1 << 6) /* To Host Mail S/W interrupt 2 */
  135. #define I_HMB_SW3 (1 << 7) /* To Host Mail S/W interrupt 3 */
  136. #define I_HMB_SW_MASK 0x000000f0 /* To Host Mail S/W interrupts mask */
  137. #define I_HMB_SW_SHIFT 4 /* To Host Mail S/W interrupts shift */
  138. #define I_WR_OOSYNC (1 << 8) /* Write Frame Out Of Sync */
  139. #define I_RD_OOSYNC (1 << 9) /* Read Frame Out Of Sync */
  140. #define I_PC (1 << 10) /* descriptor error */
  141. #define I_PD (1 << 11) /* data error */
  142. #define I_DE (1 << 12) /* Descriptor protocol Error */
  143. #define I_RU (1 << 13) /* Receive descriptor Underflow */
  144. #define I_RO (1 << 14) /* Receive fifo Overflow */
  145. #define I_XU (1 << 15) /* Transmit fifo Underflow */
  146. #define I_RI (1 << 16) /* Receive Interrupt */
  147. #define I_BUSPWR (1 << 17) /* SDIO Bus Power Change (rev 9) */
  148. #define I_XMTDATA_AVAIL (1 << 23) /* bits in fifo */
  149. #define I_XI (1 << 24) /* Transmit Interrupt */
  150. #define I_RF_TERM (1 << 25) /* Read Frame Terminate */
  151. #define I_WF_TERM (1 << 26) /* Write Frame Terminate */
  152. #define I_PCMCIA_XU (1 << 27) /* PCMCIA Transmit FIFO Underflow */
  153. #define I_SBINT (1 << 28) /* sbintstatus Interrupt */
  154. #define I_CHIPACTIVE (1 << 29) /* chip from doze to active state */
  155. #define I_SRESET (1 << 30) /* CCCR RES interrupt */
  156. #define I_IOE2 (1U << 31) /* CCCR IOE2 Bit Changed */
  157. #define I_ERRORS (I_PC | I_PD | I_DE | I_RU | I_RO | I_XU)
  158. #define I_DMA (I_RI | I_XI | I_ERRORS)
  159. /* corecontrol */
  160. #define CC_CISRDY (1 << 0) /* CIS Ready */
  161. #define CC_BPRESEN (1 << 1) /* CCCR RES signal */
  162. #define CC_F2RDY (1 << 2) /* set CCCR IOR2 bit */
  163. #define CC_CLRPADSISO (1 << 3) /* clear SDIO pads isolation */
  164. #define CC_XMTDATAAVAIL_MODE (1 << 4)
  165. #define CC_XMTDATAAVAIL_CTRL (1 << 5)
  166. /* SDA_FRAMECTRL */
  167. #define SFC_RF_TERM (1 << 0) /* Read Frame Terminate */
  168. #define SFC_WF_TERM (1 << 1) /* Write Frame Terminate */
  169. #define SFC_CRC4WOOS (1 << 2) /* CRC error for write out of sync */
  170. #define SFC_ABORTALL (1 << 3) /* Abort all in-progress frames */
  171. /* HW frame tag */
  172. #define SDPCM_FRAMETAG_LEN 4 /* 2 bytes len, 2 bytes check val */
  173. /* Total length of frame header for dongle protocol */
  174. #define SDPCM_HDRLEN (SDPCM_FRAMETAG_LEN + SDPCM_SWHEADER_LEN)
  175. #define SDPCM_RESERVE (SDPCM_HDRLEN + BRCMF_SDALIGN)
  176. /*
  177. * Software allocation of To SB Mailbox resources
  178. */
  179. /* tosbmailbox bits corresponding to intstatus bits */
  180. #define SMB_NAK (1 << 0) /* Frame NAK */
  181. #define SMB_INT_ACK (1 << 1) /* Host Interrupt ACK */
  182. #define SMB_USE_OOB (1 << 2) /* Use OOB Wakeup */
  183. #define SMB_DEV_INT (1 << 3) /* Miscellaneous Interrupt */
  184. /* tosbmailboxdata */
  185. #define SMB_DATA_VERSION_SHIFT 16 /* host protocol version */
  186. /*
  187. * Software allocation of To Host Mailbox resources
  188. */
  189. /* intstatus bits */
  190. #define I_HMB_FC_STATE I_HMB_SW0 /* Flow Control State */
  191. #define I_HMB_FC_CHANGE I_HMB_SW1 /* Flow Control State Changed */
  192. #define I_HMB_FRAME_IND I_HMB_SW2 /* Frame Indication */
  193. #define I_HMB_HOST_INT I_HMB_SW3 /* Miscellaneous Interrupt */
  194. /* tohostmailboxdata */
  195. #define HMB_DATA_NAKHANDLED 1 /* retransmit NAK'd frame */
  196. #define HMB_DATA_DEVREADY 2 /* talk to host after enable */
  197. #define HMB_DATA_FC 4 /* per prio flowcontrol update flag */
  198. #define HMB_DATA_FWREADY 8 /* fw ready for protocol activity */
  199. #define HMB_DATA_FCDATA_MASK 0xff000000
  200. #define HMB_DATA_FCDATA_SHIFT 24
  201. #define HMB_DATA_VERSION_MASK 0x00ff0000
  202. #define HMB_DATA_VERSION_SHIFT 16
  203. /*
  204. * Software-defined protocol header
  205. */
  206. /* Current protocol version */
  207. #define SDPCM_PROT_VERSION 4
  208. /* SW frame header */
  209. #define SDPCM_PACKET_SEQUENCE(p) (((u8 *)p)[0] & 0xff)
  210. #define SDPCM_CHANNEL_MASK 0x00000f00
  211. #define SDPCM_CHANNEL_SHIFT 8
  212. #define SDPCM_PACKET_CHANNEL(p) (((u8 *)p)[1] & 0x0f)
  213. #define SDPCM_NEXTLEN_OFFSET 2
  214. /* Data Offset from SOF (HW Tag, SW Tag, Pad) */
  215. #define SDPCM_DOFFSET_OFFSET 3 /* Data Offset */
  216. #define SDPCM_DOFFSET_VALUE(p) (((u8 *)p)[SDPCM_DOFFSET_OFFSET] & 0xff)
  217. #define SDPCM_DOFFSET_MASK 0xff000000
  218. #define SDPCM_DOFFSET_SHIFT 24
  219. #define SDPCM_FCMASK_OFFSET 4 /* Flow control */
  220. #define SDPCM_FCMASK_VALUE(p) (((u8 *)p)[SDPCM_FCMASK_OFFSET] & 0xff)
  221. #define SDPCM_WINDOW_OFFSET 5 /* Credit based fc */
  222. #define SDPCM_WINDOW_VALUE(p) (((u8 *)p)[SDPCM_WINDOW_OFFSET] & 0xff)
  223. #define SDPCM_SWHEADER_LEN 8 /* SW header is 64 bits */
  224. /* logical channel numbers */
  225. #define SDPCM_CONTROL_CHANNEL 0 /* Control channel Id */
  226. #define SDPCM_EVENT_CHANNEL 1 /* Asyc Event Indication Channel Id */
  227. #define SDPCM_DATA_CHANNEL 2 /* Data Xmit/Recv Channel Id */
  228. #define SDPCM_GLOM_CHANNEL 3 /* For coalesced packets */
  229. #define SDPCM_TEST_CHANNEL 15 /* Reserved for test/debug packets */
  230. #define SDPCM_SEQUENCE_WRAP 256 /* wrap-around val for 8bit frame seq */
  231. #define SDPCM_GLOMDESC(p) (((u8 *)p)[1] & 0x80)
  232. /*
  233. * Shared structure between dongle and the host.
  234. * The structure contains pointers to trap or assert information.
  235. */
  236. #define SDPCM_SHARED_VERSION 0x0002
  237. #define SDPCM_SHARED_VERSION_MASK 0x00FF
  238. #define SDPCM_SHARED_ASSERT_BUILT 0x0100
  239. #define SDPCM_SHARED_ASSERT 0x0200
  240. #define SDPCM_SHARED_TRAP 0x0400
  241. /* Space for header read, limit for data packets */
  242. #define MAX_HDR_READ (1 << 6)
  243. #define MAX_RX_DATASZ 2048
  244. /* Maximum milliseconds to wait for F2 to come up */
  245. #define BRCMF_WAIT_F2RDY 3000
  246. /* Bump up limit on waiting for HT to account for first startup;
  247. * if the image is doing a CRC calculation before programming the PMU
  248. * for HT availability, it could take a couple hundred ms more, so
  249. * max out at a 1 second (1000000us).
  250. */
  251. #undef PMU_MAX_TRANSITION_DLY
  252. #define PMU_MAX_TRANSITION_DLY 1000000
  253. /* Value for ChipClockCSR during initial setup */
  254. #define BRCMF_INIT_CLKCTL1 (SBSDIO_FORCE_HW_CLKREQ_OFF | \
  255. SBSDIO_ALP_AVAIL_REQ)
  256. /* Flags for SDH calls */
  257. #define F2SYNC (SDIO_REQ_4BYTE | SDIO_REQ_FIXED)
  258. #define BRCMFMAC_FW_NAME "brcm/brcmfmac.bin"
  259. #define BRCMFMAC_NV_NAME "brcm/brcmfmac.txt"
  260. MODULE_FIRMWARE(BRCMFMAC_FW_NAME);
  261. MODULE_FIRMWARE(BRCMFMAC_NV_NAME);
  262. /*
  263. * Conversion of 802.1D priority to precedence level
  264. */
  265. static uint prio2prec(u32 prio)
  266. {
  267. return (prio == PRIO_8021D_NONE || prio == PRIO_8021D_BE) ?
  268. (prio^2) : prio;
  269. }
  270. /* core registers */
  271. struct sdpcmd_regs {
  272. u32 corecontrol; /* 0x00, rev8 */
  273. u32 corestatus; /* rev8 */
  274. u32 PAD[1];
  275. u32 biststatus; /* rev8 */
  276. /* PCMCIA access */
  277. u16 pcmciamesportaladdr; /* 0x010, rev8 */
  278. u16 PAD[1];
  279. u16 pcmciamesportalmask; /* rev8 */
  280. u16 PAD[1];
  281. u16 pcmciawrframebc; /* rev8 */
  282. u16 PAD[1];
  283. u16 pcmciaunderflowtimer; /* rev8 */
  284. u16 PAD[1];
  285. /* interrupt */
  286. u32 intstatus; /* 0x020, rev8 */
  287. u32 hostintmask; /* rev8 */
  288. u32 intmask; /* rev8 */
  289. u32 sbintstatus; /* rev8 */
  290. u32 sbintmask; /* rev8 */
  291. u32 funcintmask; /* rev4 */
  292. u32 PAD[2];
  293. u32 tosbmailbox; /* 0x040, rev8 */
  294. u32 tohostmailbox; /* rev8 */
  295. u32 tosbmailboxdata; /* rev8 */
  296. u32 tohostmailboxdata; /* rev8 */
  297. /* synchronized access to registers in SDIO clock domain */
  298. u32 sdioaccess; /* 0x050, rev8 */
  299. u32 PAD[3];
  300. /* PCMCIA frame control */
  301. u8 pcmciaframectrl; /* 0x060, rev8 */
  302. u8 PAD[3];
  303. u8 pcmciawatermark; /* rev8 */
  304. u8 PAD[155];
  305. /* interrupt batching control */
  306. u32 intrcvlazy; /* 0x100, rev8 */
  307. u32 PAD[3];
  308. /* counters */
  309. u32 cmd52rd; /* 0x110, rev8 */
  310. u32 cmd52wr; /* rev8 */
  311. u32 cmd53rd; /* rev8 */
  312. u32 cmd53wr; /* rev8 */
  313. u32 abort; /* rev8 */
  314. u32 datacrcerror; /* rev8 */
  315. u32 rdoutofsync; /* rev8 */
  316. u32 wroutofsync; /* rev8 */
  317. u32 writebusy; /* rev8 */
  318. u32 readwait; /* rev8 */
  319. u32 readterm; /* rev8 */
  320. u32 writeterm; /* rev8 */
  321. u32 PAD[40];
  322. u32 clockctlstatus; /* rev8 */
  323. u32 PAD[7];
  324. u32 PAD[128]; /* DMA engines */
  325. /* SDIO/PCMCIA CIS region */
  326. char cis[512]; /* 0x400-0x5ff, rev6 */
  327. /* PCMCIA function control registers */
  328. char pcmciafcr[256]; /* 0x600-6ff, rev6 */
  329. u16 PAD[55];
  330. /* PCMCIA backplane access */
  331. u16 backplanecsr; /* 0x76E, rev6 */
  332. u16 backplaneaddr0; /* rev6 */
  333. u16 backplaneaddr1; /* rev6 */
  334. u16 backplaneaddr2; /* rev6 */
  335. u16 backplaneaddr3; /* rev6 */
  336. u16 backplanedata0; /* rev6 */
  337. u16 backplanedata1; /* rev6 */
  338. u16 backplanedata2; /* rev6 */
  339. u16 backplanedata3; /* rev6 */
  340. u16 PAD[31];
  341. /* sprom "size" & "blank" info */
  342. u16 spromstatus; /* 0x7BE, rev2 */
  343. u32 PAD[464];
  344. u16 PAD[0x80];
  345. };
  346. #ifdef BCMDBG
  347. /* Device console log buffer state */
  348. struct brcmf_console {
  349. uint count; /* Poll interval msec counter */
  350. uint log_addr; /* Log struct address (fixed) */
  351. struct rte_log_le log_le; /* Log struct (host copy) */
  352. uint bufsize; /* Size of log buffer */
  353. u8 *buf; /* Log buffer (host copy) */
  354. uint last; /* Last buffer read index */
  355. };
  356. #endif /* BCMDBG */
  357. struct sdpcm_shared {
  358. u32 flags;
  359. u32 trap_addr;
  360. u32 assert_exp_addr;
  361. u32 assert_file_addr;
  362. u32 assert_line;
  363. u32 console_addr; /* Address of struct rte_console */
  364. u32 msgtrace_addr;
  365. u8 tag[32];
  366. };
  367. struct sdpcm_shared_le {
  368. __le32 flags;
  369. __le32 trap_addr;
  370. __le32 assert_exp_addr;
  371. __le32 assert_file_addr;
  372. __le32 assert_line;
  373. __le32 console_addr; /* Address of struct rte_console */
  374. __le32 msgtrace_addr;
  375. u8 tag[32];
  376. };
  377. /* misc chip info needed by some of the routines */
  378. /* Private data for SDIO bus interaction */
  379. struct brcmf_sdio {
  380. struct brcmf_sdio_dev *sdiodev; /* sdio device handler */
  381. struct chip_info *ci; /* Chip info struct */
  382. char *vars; /* Variables (from CIS and/or other) */
  383. uint varsz; /* Size of variables buffer */
  384. u32 ramsize; /* Size of RAM in SOCRAM (bytes) */
  385. u32 hostintmask; /* Copy of Host Interrupt Mask */
  386. u32 intstatus; /* Intstatus bits (events) pending */
  387. bool dpc_sched; /* Indicates DPC schedule (intrpt rcvd) */
  388. bool fcstate; /* State of dongle flow-control */
  389. uint blocksize; /* Block size of SDIO transfers */
  390. uint roundup; /* Max roundup limit */
  391. struct pktq txq; /* Queue length used for flow-control */
  392. u8 flowcontrol; /* per prio flow control bitmask */
  393. u8 tx_seq; /* Transmit sequence number (next) */
  394. u8 tx_max; /* Maximum transmit sequence allowed */
  395. u8 hdrbuf[MAX_HDR_READ + BRCMF_SDALIGN];
  396. u8 *rxhdr; /* Header of current rx frame (in hdrbuf) */
  397. u16 nextlen; /* Next Read Len from last header */
  398. u8 rx_seq; /* Receive sequence number (expected) */
  399. bool rxskip; /* Skip receive (awaiting NAK ACK) */
  400. uint rxbound; /* Rx frames to read before resched */
  401. uint txbound; /* Tx frames to send before resched */
  402. uint txminmax;
  403. struct sk_buff *glomd; /* Packet containing glomming descriptor */
  404. struct sk_buff_head glom; /* Packet list for glommed superframe */
  405. uint glomerr; /* Glom packet read errors */
  406. u8 *rxbuf; /* Buffer for receiving control packets */
  407. uint rxblen; /* Allocated length of rxbuf */
  408. u8 *rxctl; /* Aligned pointer into rxbuf */
  409. u8 *databuf; /* Buffer for receiving big glom packet */
  410. u8 *dataptr; /* Aligned pointer into databuf */
  411. uint rxlen; /* Length of valid data in buffer */
  412. u8 sdpcm_ver; /* Bus protocol reported by dongle */
  413. bool intr; /* Use interrupts */
  414. bool poll; /* Use polling */
  415. bool ipend; /* Device interrupt is pending */
  416. uint intrcount; /* Count of device interrupt callbacks */
  417. uint lastintrs; /* Count as of last watchdog timer */
  418. uint spurious; /* Count of spurious interrupts */
  419. uint pollrate; /* Ticks between device polls */
  420. uint polltick; /* Tick counter */
  421. uint pollcnt; /* Count of active polls */
  422. #ifdef BCMDBG
  423. uint console_interval;
  424. struct brcmf_console console; /* Console output polling support */
  425. uint console_addr; /* Console address from shared struct */
  426. #endif /* BCMDBG */
  427. uint regfails; /* Count of R_REG failures */
  428. uint clkstate; /* State of sd and backplane clock(s) */
  429. bool activity; /* Activity flag for clock down */
  430. s32 idletime; /* Control for activity timeout */
  431. s32 idlecount; /* Activity timeout counter */
  432. s32 idleclock; /* How to set bus driver when idle */
  433. s32 sd_rxchain;
  434. bool use_rxchain; /* If brcmf should use PKT chains */
  435. bool sleeping; /* Is SDIO bus sleeping? */
  436. bool rxflow_mode; /* Rx flow control mode */
  437. bool rxflow; /* Is rx flow control on */
  438. bool alp_only; /* Don't use HT clock (ALP only) */
  439. /* Field to decide if rx of control frames happen in rxbuf or lb-pool */
  440. bool usebufpool;
  441. /* Some additional counters */
  442. uint tx_sderrs; /* Count of tx attempts with sd errors */
  443. uint fcqueued; /* Tx packets that got queued */
  444. uint rxrtx; /* Count of rtx requests (NAK to dongle) */
  445. uint rx_toolong; /* Receive frames too long to receive */
  446. uint rxc_errors; /* SDIO errors when reading control frames */
  447. uint rx_hdrfail; /* SDIO errors on header reads */
  448. uint rx_badhdr; /* Bad received headers (roosync?) */
  449. uint rx_badseq; /* Mismatched rx sequence number */
  450. uint fc_rcvd; /* Number of flow-control events received */
  451. uint fc_xoff; /* Number which turned on flow-control */
  452. uint fc_xon; /* Number which turned off flow-control */
  453. uint rxglomfail; /* Failed deglom attempts */
  454. uint rxglomframes; /* Number of glom frames (superframes) */
  455. uint rxglompkts; /* Number of packets from glom frames */
  456. uint f2rxhdrs; /* Number of header reads */
  457. uint f2rxdata; /* Number of frame data reads */
  458. uint f2txdata; /* Number of f2 frame writes */
  459. uint f1regdata; /* Number of f1 register accesses */
  460. uint tickcnt; /* Number of watchdog been schedule */
  461. unsigned long tx_ctlerrs; /* Err of sending ctrl frames */
  462. unsigned long tx_ctlpkts; /* Ctrl frames sent to dongle */
  463. unsigned long rx_ctlerrs; /* Err of processing rx ctrl frames */
  464. unsigned long rx_ctlpkts; /* Ctrl frames processed from dongle */
  465. unsigned long rx_readahead_cnt; /* Number of packets where header
  466. * read-ahead was used. */
  467. u8 *ctrl_frame_buf;
  468. u32 ctrl_frame_len;
  469. bool ctrl_frame_stat;
  470. spinlock_t txqlock;
  471. wait_queue_head_t ctrl_wait;
  472. wait_queue_head_t dcmd_resp_wait;
  473. struct timer_list timer;
  474. struct completion watchdog_wait;
  475. struct task_struct *watchdog_tsk;
  476. bool wd_timer_valid;
  477. uint save_ms;
  478. struct task_struct *dpc_tsk;
  479. struct completion dpc_wait;
  480. struct semaphore sdsem;
  481. const struct firmware *firmware;
  482. u32 fw_ptr;
  483. bool txoff; /* Transmit flow-controlled */
  484. };
  485. /* clkstate */
  486. #define CLK_NONE 0
  487. #define CLK_SDONLY 1
  488. #define CLK_PENDING 2 /* Not used yet */
  489. #define CLK_AVAIL 3
  490. #ifdef BCMDBG
  491. static int qcount[NUMPRIO];
  492. static int tx_packets[NUMPRIO];
  493. #endif /* BCMDBG */
  494. #define SDIO_DRIVE_STRENGTH 6 /* in milliamps */
  495. #define RETRYCHAN(chan) ((chan) == SDPCM_EVENT_CHANNEL)
  496. /* Retry count for register access failures */
  497. static const uint retry_limit = 2;
  498. /* Limit on rounding up frames */
  499. static const uint max_roundup = 512;
  500. #define ALIGNMENT 4
  501. static void pkt_align(struct sk_buff *p, int len, int align)
  502. {
  503. uint datalign;
  504. datalign = (unsigned long)(p->data);
  505. datalign = roundup(datalign, (align)) - datalign;
  506. if (datalign)
  507. skb_pull(p, datalign);
  508. __skb_trim(p, len);
  509. }
  510. /* To check if there's window offered */
  511. static bool data_ok(struct brcmf_sdio *bus)
  512. {
  513. return (u8)(bus->tx_max - bus->tx_seq) != 0 &&
  514. ((u8)(bus->tx_max - bus->tx_seq) & 0x80) == 0;
  515. }
  516. /*
  517. * Reads a register in the SDIO hardware block. This block occupies a series of
  518. * adresses on the 32 bit backplane bus.
  519. */
  520. static void
  521. r_sdreg32(struct brcmf_sdio *bus, u32 *regvar, u32 reg_offset, u32 *retryvar)
  522. {
  523. u8 idx = brcmf_sdio_chip_getinfidx(bus->ci, BCMA_CORE_SDIO_DEV);
  524. *retryvar = 0;
  525. do {
  526. *regvar = brcmf_sdcard_reg_read(bus->sdiodev,
  527. bus->ci->c_inf[idx].base + reg_offset,
  528. sizeof(u32));
  529. } while (brcmf_sdcard_regfail(bus->sdiodev) &&
  530. (++(*retryvar) <= retry_limit));
  531. if (*retryvar) {
  532. bus->regfails += (*retryvar-1);
  533. if (*retryvar > retry_limit) {
  534. brcmf_dbg(ERROR, "FAILED READ %Xh\n", reg_offset);
  535. *regvar = 0;
  536. }
  537. }
  538. }
  539. static void
  540. w_sdreg32(struct brcmf_sdio *bus, u32 regval, u32 reg_offset, u32 *retryvar)
  541. {
  542. u8 idx = brcmf_sdio_chip_getinfidx(bus->ci, BCMA_CORE_SDIO_DEV);
  543. *retryvar = 0;
  544. do {
  545. brcmf_sdcard_reg_write(bus->sdiodev,
  546. bus->ci->c_inf[idx].base + reg_offset,
  547. sizeof(u32), regval);
  548. } while (brcmf_sdcard_regfail(bus->sdiodev) &&
  549. (++(*retryvar) <= retry_limit));
  550. if (*retryvar) {
  551. bus->regfails += (*retryvar-1);
  552. if (*retryvar > retry_limit)
  553. brcmf_dbg(ERROR, "FAILED REGISTER WRITE %Xh\n",
  554. reg_offset);
  555. }
  556. }
  557. #define PKT_AVAILABLE() (intstatus & I_HMB_FRAME_IND)
  558. #define HOSTINTMASK (I_HMB_SW_MASK | I_CHIPACTIVE)
  559. /* Packet free applicable unconditionally for sdio and sdspi.
  560. * Conditional if bufpool was present for gspi bus.
  561. */
  562. static void brcmf_sdbrcm_pktfree2(struct brcmf_sdio *bus, struct sk_buff *pkt)
  563. {
  564. if (bus->usebufpool)
  565. brcmu_pkt_buf_free_skb(pkt);
  566. }
  567. /* Turn backplane clock on or off */
  568. static int brcmf_sdbrcm_htclk(struct brcmf_sdio *bus, bool on, bool pendok)
  569. {
  570. int err;
  571. u8 clkctl, clkreq, devctl;
  572. unsigned long timeout;
  573. brcmf_dbg(TRACE, "Enter\n");
  574. clkctl = 0;
  575. if (on) {
  576. /* Request HT Avail */
  577. clkreq =
  578. bus->alp_only ? SBSDIO_ALP_AVAIL_REQ : SBSDIO_HT_AVAIL_REQ;
  579. brcmf_sdcard_cfg_write(bus->sdiodev, SDIO_FUNC_1,
  580. SBSDIO_FUNC1_CHIPCLKCSR, clkreq, &err);
  581. if (err) {
  582. brcmf_dbg(ERROR, "HT Avail request error: %d\n", err);
  583. return -EBADE;
  584. }
  585. /* Check current status */
  586. clkctl = brcmf_sdcard_cfg_read(bus->sdiodev, SDIO_FUNC_1,
  587. SBSDIO_FUNC1_CHIPCLKCSR, &err);
  588. if (err) {
  589. brcmf_dbg(ERROR, "HT Avail read error: %d\n", err);
  590. return -EBADE;
  591. }
  592. /* Go to pending and await interrupt if appropriate */
  593. if (!SBSDIO_CLKAV(clkctl, bus->alp_only) && pendok) {
  594. /* Allow only clock-available interrupt */
  595. devctl = brcmf_sdcard_cfg_read(bus->sdiodev,
  596. SDIO_FUNC_1,
  597. SBSDIO_DEVICE_CTL, &err);
  598. if (err) {
  599. brcmf_dbg(ERROR, "Devctl error setting CA: %d\n",
  600. err);
  601. return -EBADE;
  602. }
  603. devctl |= SBSDIO_DEVCTL_CA_INT_ONLY;
  604. brcmf_sdcard_cfg_write(bus->sdiodev, SDIO_FUNC_1,
  605. SBSDIO_DEVICE_CTL, devctl, &err);
  606. brcmf_dbg(INFO, "CLKCTL: set PENDING\n");
  607. bus->clkstate = CLK_PENDING;
  608. return 0;
  609. } else if (bus->clkstate == CLK_PENDING) {
  610. /* Cancel CA-only interrupt filter */
  611. devctl =
  612. brcmf_sdcard_cfg_read(bus->sdiodev, SDIO_FUNC_1,
  613. SBSDIO_DEVICE_CTL, &err);
  614. devctl &= ~SBSDIO_DEVCTL_CA_INT_ONLY;
  615. brcmf_sdcard_cfg_write(bus->sdiodev, SDIO_FUNC_1,
  616. SBSDIO_DEVICE_CTL, devctl, &err);
  617. }
  618. /* Otherwise, wait here (polling) for HT Avail */
  619. timeout = jiffies +
  620. msecs_to_jiffies(PMU_MAX_TRANSITION_DLY/1000);
  621. while (!SBSDIO_CLKAV(clkctl, bus->alp_only)) {
  622. clkctl = brcmf_sdcard_cfg_read(bus->sdiodev,
  623. SDIO_FUNC_1,
  624. SBSDIO_FUNC1_CHIPCLKCSR,
  625. &err);
  626. if (time_after(jiffies, timeout))
  627. break;
  628. else
  629. usleep_range(5000, 10000);
  630. }
  631. if (err) {
  632. brcmf_dbg(ERROR, "HT Avail request error: %d\n", err);
  633. return -EBADE;
  634. }
  635. if (!SBSDIO_CLKAV(clkctl, bus->alp_only)) {
  636. brcmf_dbg(ERROR, "HT Avail timeout (%d): clkctl 0x%02x\n",
  637. PMU_MAX_TRANSITION_DLY, clkctl);
  638. return -EBADE;
  639. }
  640. /* Mark clock available */
  641. bus->clkstate = CLK_AVAIL;
  642. brcmf_dbg(INFO, "CLKCTL: turned ON\n");
  643. #if defined(BCMDBG)
  644. if (bus->alp_only != true) {
  645. if (SBSDIO_ALPONLY(clkctl))
  646. brcmf_dbg(ERROR, "HT Clock should be on\n");
  647. }
  648. #endif /* defined (BCMDBG) */
  649. bus->activity = true;
  650. } else {
  651. clkreq = 0;
  652. if (bus->clkstate == CLK_PENDING) {
  653. /* Cancel CA-only interrupt filter */
  654. devctl = brcmf_sdcard_cfg_read(bus->sdiodev,
  655. SDIO_FUNC_1,
  656. SBSDIO_DEVICE_CTL, &err);
  657. devctl &= ~SBSDIO_DEVCTL_CA_INT_ONLY;
  658. brcmf_sdcard_cfg_write(bus->sdiodev, SDIO_FUNC_1,
  659. SBSDIO_DEVICE_CTL, devctl, &err);
  660. }
  661. bus->clkstate = CLK_SDONLY;
  662. brcmf_sdcard_cfg_write(bus->sdiodev, SDIO_FUNC_1,
  663. SBSDIO_FUNC1_CHIPCLKCSR, clkreq, &err);
  664. brcmf_dbg(INFO, "CLKCTL: turned OFF\n");
  665. if (err) {
  666. brcmf_dbg(ERROR, "Failed access turning clock off: %d\n",
  667. err);
  668. return -EBADE;
  669. }
  670. }
  671. return 0;
  672. }
  673. /* Change idle/active SD state */
  674. static int brcmf_sdbrcm_sdclk(struct brcmf_sdio *bus, bool on)
  675. {
  676. brcmf_dbg(TRACE, "Enter\n");
  677. if (on)
  678. bus->clkstate = CLK_SDONLY;
  679. else
  680. bus->clkstate = CLK_NONE;
  681. return 0;
  682. }
  683. /* Transition SD and backplane clock readiness */
  684. static int brcmf_sdbrcm_clkctl(struct brcmf_sdio *bus, uint target, bool pendok)
  685. {
  686. #ifdef BCMDBG
  687. uint oldstate = bus->clkstate;
  688. #endif /* BCMDBG */
  689. brcmf_dbg(TRACE, "Enter\n");
  690. /* Early exit if we're already there */
  691. if (bus->clkstate == target) {
  692. if (target == CLK_AVAIL) {
  693. brcmf_sdbrcm_wd_timer(bus, BRCMF_WD_POLL_MS);
  694. bus->activity = true;
  695. }
  696. return 0;
  697. }
  698. switch (target) {
  699. case CLK_AVAIL:
  700. /* Make sure SD clock is available */
  701. if (bus->clkstate == CLK_NONE)
  702. brcmf_sdbrcm_sdclk(bus, true);
  703. /* Now request HT Avail on the backplane */
  704. brcmf_sdbrcm_htclk(bus, true, pendok);
  705. brcmf_sdbrcm_wd_timer(bus, BRCMF_WD_POLL_MS);
  706. bus->activity = true;
  707. break;
  708. case CLK_SDONLY:
  709. /* Remove HT request, or bring up SD clock */
  710. if (bus->clkstate == CLK_NONE)
  711. brcmf_sdbrcm_sdclk(bus, true);
  712. else if (bus->clkstate == CLK_AVAIL)
  713. brcmf_sdbrcm_htclk(bus, false, false);
  714. else
  715. brcmf_dbg(ERROR, "request for %d -> %d\n",
  716. bus->clkstate, target);
  717. brcmf_sdbrcm_wd_timer(bus, BRCMF_WD_POLL_MS);
  718. break;
  719. case CLK_NONE:
  720. /* Make sure to remove HT request */
  721. if (bus->clkstate == CLK_AVAIL)
  722. brcmf_sdbrcm_htclk(bus, false, false);
  723. /* Now remove the SD clock */
  724. brcmf_sdbrcm_sdclk(bus, false);
  725. brcmf_sdbrcm_wd_timer(bus, 0);
  726. break;
  727. }
  728. #ifdef BCMDBG
  729. brcmf_dbg(INFO, "%d -> %d\n", oldstate, bus->clkstate);
  730. #endif /* BCMDBG */
  731. return 0;
  732. }
  733. static int brcmf_sdbrcm_bussleep(struct brcmf_sdio *bus, bool sleep)
  734. {
  735. uint retries = 0;
  736. brcmf_dbg(INFO, "request %s (currently %s)\n",
  737. sleep ? "SLEEP" : "WAKE",
  738. bus->sleeping ? "SLEEP" : "WAKE");
  739. /* Done if we're already in the requested state */
  740. if (sleep == bus->sleeping)
  741. return 0;
  742. /* Going to sleep: set the alarm and turn off the lights... */
  743. if (sleep) {
  744. /* Don't sleep if something is pending */
  745. if (bus->dpc_sched || bus->rxskip || pktq_len(&bus->txq))
  746. return -EBUSY;
  747. /* Make sure the controller has the bus up */
  748. brcmf_sdbrcm_clkctl(bus, CLK_AVAIL, false);
  749. /* Tell device to start using OOB wakeup */
  750. w_sdreg32(bus, SMB_USE_OOB,
  751. offsetof(struct sdpcmd_regs, tosbmailbox), &retries);
  752. if (retries > retry_limit)
  753. brcmf_dbg(ERROR, "CANNOT SIGNAL CHIP, WILL NOT WAKE UP!!\n");
  754. /* Turn off our contribution to the HT clock request */
  755. brcmf_sdbrcm_clkctl(bus, CLK_SDONLY, false);
  756. brcmf_sdcard_cfg_write(bus->sdiodev, SDIO_FUNC_1,
  757. SBSDIO_FUNC1_CHIPCLKCSR,
  758. SBSDIO_FORCE_HW_CLKREQ_OFF, NULL);
  759. /* Isolate the bus */
  760. brcmf_sdcard_cfg_write(bus->sdiodev, SDIO_FUNC_1,
  761. SBSDIO_DEVICE_CTL,
  762. SBSDIO_DEVCTL_PADS_ISO, NULL);
  763. /* Change state */
  764. bus->sleeping = true;
  765. } else {
  766. /* Waking up: bus power up is ok, set local state */
  767. brcmf_sdcard_cfg_write(bus->sdiodev, SDIO_FUNC_1,
  768. SBSDIO_FUNC1_CHIPCLKCSR, 0, NULL);
  769. /* Make sure the controller has the bus up */
  770. brcmf_sdbrcm_clkctl(bus, CLK_AVAIL, false);
  771. /* Send misc interrupt to indicate OOB not needed */
  772. w_sdreg32(bus, 0, offsetof(struct sdpcmd_regs, tosbmailboxdata),
  773. &retries);
  774. if (retries <= retry_limit)
  775. w_sdreg32(bus, SMB_DEV_INT,
  776. offsetof(struct sdpcmd_regs, tosbmailbox),
  777. &retries);
  778. if (retries > retry_limit)
  779. brcmf_dbg(ERROR, "CANNOT SIGNAL CHIP TO CLEAR OOB!!\n");
  780. /* Make sure we have SD bus access */
  781. brcmf_sdbrcm_clkctl(bus, CLK_SDONLY, false);
  782. /* Change state */
  783. bus->sleeping = false;
  784. }
  785. return 0;
  786. }
  787. static void bus_wake(struct brcmf_sdio *bus)
  788. {
  789. if (bus->sleeping)
  790. brcmf_sdbrcm_bussleep(bus, false);
  791. }
  792. static u32 brcmf_sdbrcm_hostmail(struct brcmf_sdio *bus)
  793. {
  794. u32 intstatus = 0;
  795. u32 hmb_data;
  796. u8 fcbits;
  797. uint retries = 0;
  798. brcmf_dbg(TRACE, "Enter\n");
  799. /* Read mailbox data and ack that we did so */
  800. r_sdreg32(bus, &hmb_data,
  801. offsetof(struct sdpcmd_regs, tohostmailboxdata), &retries);
  802. if (retries <= retry_limit)
  803. w_sdreg32(bus, SMB_INT_ACK,
  804. offsetof(struct sdpcmd_regs, tosbmailbox), &retries);
  805. bus->f1regdata += 2;
  806. /* Dongle recomposed rx frames, accept them again */
  807. if (hmb_data & HMB_DATA_NAKHANDLED) {
  808. brcmf_dbg(INFO, "Dongle reports NAK handled, expect rtx of %d\n",
  809. bus->rx_seq);
  810. if (!bus->rxskip)
  811. brcmf_dbg(ERROR, "unexpected NAKHANDLED!\n");
  812. bus->rxskip = false;
  813. intstatus |= I_HMB_FRAME_IND;
  814. }
  815. /*
  816. * DEVREADY does not occur with gSPI.
  817. */
  818. if (hmb_data & (HMB_DATA_DEVREADY | HMB_DATA_FWREADY)) {
  819. bus->sdpcm_ver =
  820. (hmb_data & HMB_DATA_VERSION_MASK) >>
  821. HMB_DATA_VERSION_SHIFT;
  822. if (bus->sdpcm_ver != SDPCM_PROT_VERSION)
  823. brcmf_dbg(ERROR, "Version mismatch, dongle reports %d, "
  824. "expecting %d\n",
  825. bus->sdpcm_ver, SDPCM_PROT_VERSION);
  826. else
  827. brcmf_dbg(INFO, "Dongle ready, protocol version %d\n",
  828. bus->sdpcm_ver);
  829. }
  830. /*
  831. * Flow Control has been moved into the RX headers and this out of band
  832. * method isn't used any more.
  833. * remaining backward compatible with older dongles.
  834. */
  835. if (hmb_data & HMB_DATA_FC) {
  836. fcbits = (hmb_data & HMB_DATA_FCDATA_MASK) >>
  837. HMB_DATA_FCDATA_SHIFT;
  838. if (fcbits & ~bus->flowcontrol)
  839. bus->fc_xoff++;
  840. if (bus->flowcontrol & ~fcbits)
  841. bus->fc_xon++;
  842. bus->fc_rcvd++;
  843. bus->flowcontrol = fcbits;
  844. }
  845. /* Shouldn't be any others */
  846. if (hmb_data & ~(HMB_DATA_DEVREADY |
  847. HMB_DATA_NAKHANDLED |
  848. HMB_DATA_FC |
  849. HMB_DATA_FWREADY |
  850. HMB_DATA_FCDATA_MASK | HMB_DATA_VERSION_MASK))
  851. brcmf_dbg(ERROR, "Unknown mailbox data content: 0x%02x\n",
  852. hmb_data);
  853. return intstatus;
  854. }
  855. static void brcmf_sdbrcm_rxfail(struct brcmf_sdio *bus, bool abort, bool rtx)
  856. {
  857. uint retries = 0;
  858. u16 lastrbc;
  859. u8 hi, lo;
  860. int err;
  861. brcmf_dbg(ERROR, "%sterminate frame%s\n",
  862. abort ? "abort command, " : "",
  863. rtx ? ", send NAK" : "");
  864. if (abort)
  865. brcmf_sdcard_abort(bus->sdiodev, SDIO_FUNC_2);
  866. brcmf_sdcard_cfg_write(bus->sdiodev, SDIO_FUNC_1,
  867. SBSDIO_FUNC1_FRAMECTRL,
  868. SFC_RF_TERM, &err);
  869. bus->f1regdata++;
  870. /* Wait until the packet has been flushed (device/FIFO stable) */
  871. for (lastrbc = retries = 0xffff; retries > 0; retries--) {
  872. hi = brcmf_sdcard_cfg_read(bus->sdiodev, SDIO_FUNC_1,
  873. SBSDIO_FUNC1_RFRAMEBCHI, NULL);
  874. lo = brcmf_sdcard_cfg_read(bus->sdiodev, SDIO_FUNC_1,
  875. SBSDIO_FUNC1_RFRAMEBCLO, NULL);
  876. bus->f1regdata += 2;
  877. if ((hi == 0) && (lo == 0))
  878. break;
  879. if ((hi > (lastrbc >> 8)) && (lo > (lastrbc & 0x00ff))) {
  880. brcmf_dbg(ERROR, "count growing: last 0x%04x now 0x%04x\n",
  881. lastrbc, (hi << 8) + lo);
  882. }
  883. lastrbc = (hi << 8) + lo;
  884. }
  885. if (!retries)
  886. brcmf_dbg(ERROR, "count never zeroed: last 0x%04x\n", lastrbc);
  887. else
  888. brcmf_dbg(INFO, "flush took %d iterations\n", 0xffff - retries);
  889. if (rtx) {
  890. bus->rxrtx++;
  891. w_sdreg32(bus, SMB_NAK,
  892. offsetof(struct sdpcmd_regs, tosbmailbox), &retries);
  893. bus->f1regdata++;
  894. if (retries <= retry_limit)
  895. bus->rxskip = true;
  896. }
  897. /* Clear partial in any case */
  898. bus->nextlen = 0;
  899. /* If we can't reach the device, signal failure */
  900. if (err || brcmf_sdcard_regfail(bus->sdiodev))
  901. bus->sdiodev->bus_if->state = BRCMF_BUS_DOWN;
  902. }
  903. /* copy a buffer into a pkt buffer chain */
  904. static uint brcmf_sdbrcm_glom_from_buf(struct brcmf_sdio *bus, uint len)
  905. {
  906. uint n, ret = 0;
  907. struct sk_buff *p;
  908. u8 *buf;
  909. buf = bus->dataptr;
  910. /* copy the data */
  911. skb_queue_walk(&bus->glom, p) {
  912. n = min_t(uint, p->len, len);
  913. memcpy(p->data, buf, n);
  914. buf += n;
  915. len -= n;
  916. ret += n;
  917. if (!len)
  918. break;
  919. }
  920. return ret;
  921. }
  922. /* return total length of buffer chain */
  923. static uint brcmf_sdbrcm_glom_len(struct brcmf_sdio *bus)
  924. {
  925. struct sk_buff *p;
  926. uint total;
  927. total = 0;
  928. skb_queue_walk(&bus->glom, p)
  929. total += p->len;
  930. return total;
  931. }
  932. static void brcmf_sdbrcm_free_glom(struct brcmf_sdio *bus)
  933. {
  934. struct sk_buff *cur, *next;
  935. skb_queue_walk_safe(&bus->glom, cur, next) {
  936. skb_unlink(cur, &bus->glom);
  937. brcmu_pkt_buf_free_skb(cur);
  938. }
  939. }
  940. static u8 brcmf_sdbrcm_rxglom(struct brcmf_sdio *bus, u8 rxseq)
  941. {
  942. u16 dlen, totlen;
  943. u8 *dptr, num = 0;
  944. u16 sublen, check;
  945. struct sk_buff *pfirst, *pnext;
  946. int errcode;
  947. u8 chan, seq, doff, sfdoff;
  948. u8 txmax;
  949. int ifidx = 0;
  950. bool usechain = bus->use_rxchain;
  951. /* If packets, issue read(s) and send up packet chain */
  952. /* Return sequence numbers consumed? */
  953. brcmf_dbg(TRACE, "start: glomd %p glom %p\n",
  954. bus->glomd, skb_peek(&bus->glom));
  955. /* If there's a descriptor, generate the packet chain */
  956. if (bus->glomd) {
  957. pfirst = pnext = NULL;
  958. dlen = (u16) (bus->glomd->len);
  959. dptr = bus->glomd->data;
  960. if (!dlen || (dlen & 1)) {
  961. brcmf_dbg(ERROR, "bad glomd len(%d), ignore descriptor\n",
  962. dlen);
  963. dlen = 0;
  964. }
  965. for (totlen = num = 0; dlen; num++) {
  966. /* Get (and move past) next length */
  967. sublen = get_unaligned_le16(dptr);
  968. dlen -= sizeof(u16);
  969. dptr += sizeof(u16);
  970. if ((sublen < SDPCM_HDRLEN) ||
  971. ((num == 0) && (sublen < (2 * SDPCM_HDRLEN)))) {
  972. brcmf_dbg(ERROR, "descriptor len %d bad: %d\n",
  973. num, sublen);
  974. pnext = NULL;
  975. break;
  976. }
  977. if (sublen % BRCMF_SDALIGN) {
  978. brcmf_dbg(ERROR, "sublen %d not multiple of %d\n",
  979. sublen, BRCMF_SDALIGN);
  980. usechain = false;
  981. }
  982. totlen += sublen;
  983. /* For last frame, adjust read len so total
  984. is a block multiple */
  985. if (!dlen) {
  986. sublen +=
  987. (roundup(totlen, bus->blocksize) - totlen);
  988. totlen = roundup(totlen, bus->blocksize);
  989. }
  990. /* Allocate/chain packet for next subframe */
  991. pnext = brcmu_pkt_buf_get_skb(sublen + BRCMF_SDALIGN);
  992. if (pnext == NULL) {
  993. brcmf_dbg(ERROR, "bcm_pkt_buf_get_skb failed, num %d len %d\n",
  994. num, sublen);
  995. break;
  996. }
  997. skb_queue_tail(&bus->glom, pnext);
  998. /* Adhere to start alignment requirements */
  999. pkt_align(pnext, sublen, BRCMF_SDALIGN);
  1000. }
  1001. /* If all allocations succeeded, save packet chain
  1002. in bus structure */
  1003. if (pnext) {
  1004. brcmf_dbg(GLOM, "allocated %d-byte packet chain for %d subframes\n",
  1005. totlen, num);
  1006. if (BRCMF_GLOM_ON() && bus->nextlen &&
  1007. totlen != bus->nextlen) {
  1008. brcmf_dbg(GLOM, "glomdesc mismatch: nextlen %d glomdesc %d rxseq %d\n",
  1009. bus->nextlen, totlen, rxseq);
  1010. }
  1011. pfirst = pnext = NULL;
  1012. } else {
  1013. brcmf_sdbrcm_free_glom(bus);
  1014. num = 0;
  1015. }
  1016. /* Done with descriptor packet */
  1017. brcmu_pkt_buf_free_skb(bus->glomd);
  1018. bus->glomd = NULL;
  1019. bus->nextlen = 0;
  1020. }
  1021. /* Ok -- either we just generated a packet chain,
  1022. or had one from before */
  1023. if (!skb_queue_empty(&bus->glom)) {
  1024. if (BRCMF_GLOM_ON()) {
  1025. brcmf_dbg(GLOM, "try superframe read, packet chain:\n");
  1026. skb_queue_walk(&bus->glom, pnext) {
  1027. brcmf_dbg(GLOM, " %p: %p len 0x%04x (%d)\n",
  1028. pnext, (u8 *) (pnext->data),
  1029. pnext->len, pnext->len);
  1030. }
  1031. }
  1032. pfirst = skb_peek(&bus->glom);
  1033. dlen = (u16) brcmf_sdbrcm_glom_len(bus);
  1034. /* Do an SDIO read for the superframe. Configurable iovar to
  1035. * read directly into the chained packet, or allocate a large
  1036. * packet and and copy into the chain.
  1037. */
  1038. if (usechain) {
  1039. errcode = brcmf_sdcard_recv_chain(bus->sdiodev,
  1040. bus->sdiodev->sbwad,
  1041. SDIO_FUNC_2, F2SYNC, &bus->glom);
  1042. } else if (bus->dataptr) {
  1043. errcode = brcmf_sdcard_recv_buf(bus->sdiodev,
  1044. bus->sdiodev->sbwad,
  1045. SDIO_FUNC_2, F2SYNC,
  1046. bus->dataptr, dlen);
  1047. sublen = (u16) brcmf_sdbrcm_glom_from_buf(bus, dlen);
  1048. if (sublen != dlen) {
  1049. brcmf_dbg(ERROR, "FAILED TO COPY, dlen %d sublen %d\n",
  1050. dlen, sublen);
  1051. errcode = -1;
  1052. }
  1053. pnext = NULL;
  1054. } else {
  1055. brcmf_dbg(ERROR, "COULDN'T ALLOC %d-BYTE GLOM, FORCE FAILURE\n",
  1056. dlen);
  1057. errcode = -1;
  1058. }
  1059. bus->f2rxdata++;
  1060. /* On failure, kill the superframe, allow a couple retries */
  1061. if (errcode < 0) {
  1062. brcmf_dbg(ERROR, "glom read of %d bytes failed: %d\n",
  1063. dlen, errcode);
  1064. bus->sdiodev->bus_if->dstats.rx_errors++;
  1065. if (bus->glomerr++ < 3) {
  1066. brcmf_sdbrcm_rxfail(bus, true, true);
  1067. } else {
  1068. bus->glomerr = 0;
  1069. brcmf_sdbrcm_rxfail(bus, true, false);
  1070. bus->rxglomfail++;
  1071. brcmf_sdbrcm_free_glom(bus);
  1072. }
  1073. return 0;
  1074. }
  1075. #ifdef BCMDBG
  1076. if (BRCMF_GLOM_ON()) {
  1077. printk(KERN_DEBUG "SUPERFRAME:\n");
  1078. print_hex_dump_bytes("", DUMP_PREFIX_OFFSET,
  1079. pfirst->data, min_t(int, pfirst->len, 48));
  1080. }
  1081. #endif
  1082. /* Validate the superframe header */
  1083. dptr = (u8 *) (pfirst->data);
  1084. sublen = get_unaligned_le16(dptr);
  1085. check = get_unaligned_le16(dptr + sizeof(u16));
  1086. chan = SDPCM_PACKET_CHANNEL(&dptr[SDPCM_FRAMETAG_LEN]);
  1087. seq = SDPCM_PACKET_SEQUENCE(&dptr[SDPCM_FRAMETAG_LEN]);
  1088. bus->nextlen = dptr[SDPCM_FRAMETAG_LEN + SDPCM_NEXTLEN_OFFSET];
  1089. if ((bus->nextlen << 4) > MAX_RX_DATASZ) {
  1090. brcmf_dbg(INFO, "nextlen too large (%d) seq %d\n",
  1091. bus->nextlen, seq);
  1092. bus->nextlen = 0;
  1093. }
  1094. doff = SDPCM_DOFFSET_VALUE(&dptr[SDPCM_FRAMETAG_LEN]);
  1095. txmax = SDPCM_WINDOW_VALUE(&dptr[SDPCM_FRAMETAG_LEN]);
  1096. errcode = 0;
  1097. if ((u16)~(sublen ^ check)) {
  1098. brcmf_dbg(ERROR, "(superframe): HW hdr error: len/check 0x%04x/0x%04x\n",
  1099. sublen, check);
  1100. errcode = -1;
  1101. } else if (roundup(sublen, bus->blocksize) != dlen) {
  1102. brcmf_dbg(ERROR, "(superframe): len 0x%04x, rounded 0x%04x, expect 0x%04x\n",
  1103. sublen, roundup(sublen, bus->blocksize),
  1104. dlen);
  1105. errcode = -1;
  1106. } else if (SDPCM_PACKET_CHANNEL(&dptr[SDPCM_FRAMETAG_LEN]) !=
  1107. SDPCM_GLOM_CHANNEL) {
  1108. brcmf_dbg(ERROR, "(superframe): bad channel %d\n",
  1109. SDPCM_PACKET_CHANNEL(
  1110. &dptr[SDPCM_FRAMETAG_LEN]));
  1111. errcode = -1;
  1112. } else if (SDPCM_GLOMDESC(&dptr[SDPCM_FRAMETAG_LEN])) {
  1113. brcmf_dbg(ERROR, "(superframe): got 2nd descriptor?\n");
  1114. errcode = -1;
  1115. } else if ((doff < SDPCM_HDRLEN) ||
  1116. (doff > (pfirst->len - SDPCM_HDRLEN))) {
  1117. brcmf_dbg(ERROR, "(superframe): Bad data offset %d: HW %d pkt %d min %d\n",
  1118. doff, sublen, pfirst->len, SDPCM_HDRLEN);
  1119. errcode = -1;
  1120. }
  1121. /* Check sequence number of superframe SW header */
  1122. if (rxseq != seq) {
  1123. brcmf_dbg(INFO, "(superframe) rx_seq %d, expected %d\n",
  1124. seq, rxseq);
  1125. bus->rx_badseq++;
  1126. rxseq = seq;
  1127. }
  1128. /* Check window for sanity */
  1129. if ((u8) (txmax - bus->tx_seq) > 0x40) {
  1130. brcmf_dbg(ERROR, "unlikely tx max %d with tx_seq %d\n",
  1131. txmax, bus->tx_seq);
  1132. txmax = bus->tx_seq + 2;
  1133. }
  1134. bus->tx_max = txmax;
  1135. /* Remove superframe header, remember offset */
  1136. skb_pull(pfirst, doff);
  1137. sfdoff = doff;
  1138. num = 0;
  1139. /* Validate all the subframe headers */
  1140. skb_queue_walk(&bus->glom, pnext) {
  1141. /* leave when invalid subframe is found */
  1142. if (errcode)
  1143. break;
  1144. dptr = (u8 *) (pnext->data);
  1145. dlen = (u16) (pnext->len);
  1146. sublen = get_unaligned_le16(dptr);
  1147. check = get_unaligned_le16(dptr + sizeof(u16));
  1148. chan = SDPCM_PACKET_CHANNEL(&dptr[SDPCM_FRAMETAG_LEN]);
  1149. doff = SDPCM_DOFFSET_VALUE(&dptr[SDPCM_FRAMETAG_LEN]);
  1150. #ifdef BCMDBG
  1151. if (BRCMF_GLOM_ON()) {
  1152. printk(KERN_DEBUG "subframe:\n");
  1153. print_hex_dump_bytes("", DUMP_PREFIX_OFFSET,
  1154. dptr, 32);
  1155. }
  1156. #endif
  1157. if ((u16)~(sublen ^ check)) {
  1158. brcmf_dbg(ERROR, "(subframe %d): HW hdr error: len/check 0x%04x/0x%04x\n",
  1159. num, sublen, check);
  1160. errcode = -1;
  1161. } else if ((sublen > dlen) || (sublen < SDPCM_HDRLEN)) {
  1162. brcmf_dbg(ERROR, "(subframe %d): length mismatch: len 0x%04x, expect 0x%04x\n",
  1163. num, sublen, dlen);
  1164. errcode = -1;
  1165. } else if ((chan != SDPCM_DATA_CHANNEL) &&
  1166. (chan != SDPCM_EVENT_CHANNEL)) {
  1167. brcmf_dbg(ERROR, "(subframe %d): bad channel %d\n",
  1168. num, chan);
  1169. errcode = -1;
  1170. } else if ((doff < SDPCM_HDRLEN) || (doff > sublen)) {
  1171. brcmf_dbg(ERROR, "(subframe %d): Bad data offset %d: HW %d min %d\n",
  1172. num, doff, sublen, SDPCM_HDRLEN);
  1173. errcode = -1;
  1174. }
  1175. /* increase the subframe count */
  1176. num++;
  1177. }
  1178. if (errcode) {
  1179. /* Terminate frame on error, request
  1180. a couple retries */
  1181. if (bus->glomerr++ < 3) {
  1182. /* Restore superframe header space */
  1183. skb_push(pfirst, sfdoff);
  1184. brcmf_sdbrcm_rxfail(bus, true, true);
  1185. } else {
  1186. bus->glomerr = 0;
  1187. brcmf_sdbrcm_rxfail(bus, true, false);
  1188. bus->rxglomfail++;
  1189. brcmf_sdbrcm_free_glom(bus);
  1190. }
  1191. bus->nextlen = 0;
  1192. return 0;
  1193. }
  1194. /* Basic SD framing looks ok - process each packet (header) */
  1195. skb_queue_walk_safe(&bus->glom, pfirst, pnext) {
  1196. dptr = (u8 *) (pfirst->data);
  1197. sublen = get_unaligned_le16(dptr);
  1198. chan = SDPCM_PACKET_CHANNEL(&dptr[SDPCM_FRAMETAG_LEN]);
  1199. seq = SDPCM_PACKET_SEQUENCE(&dptr[SDPCM_FRAMETAG_LEN]);
  1200. doff = SDPCM_DOFFSET_VALUE(&dptr[SDPCM_FRAMETAG_LEN]);
  1201. brcmf_dbg(GLOM, "Get subframe %d, %p(%p/%d), sublen %d chan %d seq %d\n",
  1202. num, pfirst, pfirst->data,
  1203. pfirst->len, sublen, chan, seq);
  1204. /* precondition: chan == SDPCM_DATA_CHANNEL ||
  1205. chan == SDPCM_EVENT_CHANNEL */
  1206. if (rxseq != seq) {
  1207. brcmf_dbg(GLOM, "rx_seq %d, expected %d\n",
  1208. seq, rxseq);
  1209. bus->rx_badseq++;
  1210. rxseq = seq;
  1211. }
  1212. rxseq++;
  1213. #ifdef BCMDBG
  1214. if (BRCMF_BYTES_ON() && BRCMF_DATA_ON()) {
  1215. printk(KERN_DEBUG "Rx Subframe Data:\n");
  1216. print_hex_dump_bytes("", DUMP_PREFIX_OFFSET,
  1217. dptr, dlen);
  1218. }
  1219. #endif
  1220. __skb_trim(pfirst, sublen);
  1221. skb_pull(pfirst, doff);
  1222. if (pfirst->len == 0) {
  1223. skb_unlink(pfirst, &bus->glom);
  1224. brcmu_pkt_buf_free_skb(pfirst);
  1225. continue;
  1226. } else if (brcmf_proto_hdrpull(bus->sdiodev->dev,
  1227. &ifidx, pfirst) != 0) {
  1228. brcmf_dbg(ERROR, "rx protocol error\n");
  1229. bus->sdiodev->bus_if->dstats.rx_errors++;
  1230. skb_unlink(pfirst, &bus->glom);
  1231. brcmu_pkt_buf_free_skb(pfirst);
  1232. continue;
  1233. }
  1234. #ifdef BCMDBG
  1235. if (BRCMF_GLOM_ON()) {
  1236. brcmf_dbg(GLOM, "subframe %d to stack, %p (%p/%d) nxt/lnk %p/%p\n",
  1237. bus->glom.qlen, pfirst, pfirst->data,
  1238. pfirst->len, pfirst->next,
  1239. pfirst->prev);
  1240. print_hex_dump_bytes("", DUMP_PREFIX_OFFSET,
  1241. pfirst->data,
  1242. min_t(int, pfirst->len, 32));
  1243. }
  1244. #endif /* BCMDBG */
  1245. }
  1246. /* sent any remaining packets up */
  1247. if (bus->glom.qlen) {
  1248. up(&bus->sdsem);
  1249. brcmf_rx_frame(bus->sdiodev->dev, ifidx, &bus->glom);
  1250. down(&bus->sdsem);
  1251. }
  1252. bus->rxglomframes++;
  1253. bus->rxglompkts += bus->glom.qlen;
  1254. }
  1255. return num;
  1256. }
  1257. static int brcmf_sdbrcm_dcmd_resp_wait(struct brcmf_sdio *bus, uint *condition,
  1258. bool *pending)
  1259. {
  1260. DECLARE_WAITQUEUE(wait, current);
  1261. int timeout = msecs_to_jiffies(DCMD_RESP_TIMEOUT);
  1262. /* Wait until control frame is available */
  1263. add_wait_queue(&bus->dcmd_resp_wait, &wait);
  1264. set_current_state(TASK_INTERRUPTIBLE);
  1265. while (!(*condition) && (!signal_pending(current) && timeout))
  1266. timeout = schedule_timeout(timeout);
  1267. if (signal_pending(current))
  1268. *pending = true;
  1269. set_current_state(TASK_RUNNING);
  1270. remove_wait_queue(&bus->dcmd_resp_wait, &wait);
  1271. return timeout;
  1272. }
  1273. static int brcmf_sdbrcm_dcmd_resp_wake(struct brcmf_sdio *bus)
  1274. {
  1275. if (waitqueue_active(&bus->dcmd_resp_wait))
  1276. wake_up_interruptible(&bus->dcmd_resp_wait);
  1277. return 0;
  1278. }
  1279. static void
  1280. brcmf_sdbrcm_read_control(struct brcmf_sdio *bus, u8 *hdr, uint len, uint doff)
  1281. {
  1282. uint rdlen, pad;
  1283. int sdret;
  1284. brcmf_dbg(TRACE, "Enter\n");
  1285. /* Set rxctl for frame (w/optional alignment) */
  1286. bus->rxctl = bus->rxbuf;
  1287. bus->rxctl += BRCMF_FIRSTREAD;
  1288. pad = ((unsigned long)bus->rxctl % BRCMF_SDALIGN);
  1289. if (pad)
  1290. bus->rxctl += (BRCMF_SDALIGN - pad);
  1291. bus->rxctl -= BRCMF_FIRSTREAD;
  1292. /* Copy the already-read portion over */
  1293. memcpy(bus->rxctl, hdr, BRCMF_FIRSTREAD);
  1294. if (len <= BRCMF_FIRSTREAD)
  1295. goto gotpkt;
  1296. /* Raise rdlen to next SDIO block to avoid tail command */
  1297. rdlen = len - BRCMF_FIRSTREAD;
  1298. if (bus->roundup && bus->blocksize && (rdlen > bus->blocksize)) {
  1299. pad = bus->blocksize - (rdlen % bus->blocksize);
  1300. if ((pad <= bus->roundup) && (pad < bus->blocksize) &&
  1301. ((len + pad) < bus->sdiodev->bus_if->maxctl))
  1302. rdlen += pad;
  1303. } else if (rdlen % BRCMF_SDALIGN) {
  1304. rdlen += BRCMF_SDALIGN - (rdlen % BRCMF_SDALIGN);
  1305. }
  1306. /* Satisfy length-alignment requirements */
  1307. if (rdlen & (ALIGNMENT - 1))
  1308. rdlen = roundup(rdlen, ALIGNMENT);
  1309. /* Drop if the read is too big or it exceeds our maximum */
  1310. if ((rdlen + BRCMF_FIRSTREAD) > bus->sdiodev->bus_if->maxctl) {
  1311. brcmf_dbg(ERROR, "%d-byte control read exceeds %d-byte buffer\n",
  1312. rdlen, bus->sdiodev->bus_if->maxctl);
  1313. bus->sdiodev->bus_if->dstats.rx_errors++;
  1314. brcmf_sdbrcm_rxfail(bus, false, false);
  1315. goto done;
  1316. }
  1317. if ((len - doff) > bus->sdiodev->bus_if->maxctl) {
  1318. brcmf_dbg(ERROR, "%d-byte ctl frame (%d-byte ctl data) exceeds %d-byte limit\n",
  1319. len, len - doff, bus->sdiodev->bus_if->maxctl);
  1320. bus->sdiodev->bus_if->dstats.rx_errors++;
  1321. bus->rx_toolong++;
  1322. brcmf_sdbrcm_rxfail(bus, false, false);
  1323. goto done;
  1324. }
  1325. /* Read remainder of frame body into the rxctl buffer */
  1326. sdret = brcmf_sdcard_recv_buf(bus->sdiodev,
  1327. bus->sdiodev->sbwad,
  1328. SDIO_FUNC_2,
  1329. F2SYNC, (bus->rxctl + BRCMF_FIRSTREAD), rdlen);
  1330. bus->f2rxdata++;
  1331. /* Control frame failures need retransmission */
  1332. if (sdret < 0) {
  1333. brcmf_dbg(ERROR, "read %d control bytes failed: %d\n",
  1334. rdlen, sdret);
  1335. bus->rxc_errors++;
  1336. brcmf_sdbrcm_rxfail(bus, true, true);
  1337. goto done;
  1338. }
  1339. gotpkt:
  1340. #ifdef BCMDBG
  1341. if (BRCMF_BYTES_ON() && BRCMF_CTL_ON()) {
  1342. printk(KERN_DEBUG "RxCtrl:\n");
  1343. print_hex_dump_bytes("", DUMP_PREFIX_OFFSET, bus->rxctl, len);
  1344. }
  1345. #endif
  1346. /* Point to valid data and indicate its length */
  1347. bus->rxctl += doff;
  1348. bus->rxlen = len - doff;
  1349. done:
  1350. /* Awake any waiters */
  1351. brcmf_sdbrcm_dcmd_resp_wake(bus);
  1352. }
  1353. /* Pad read to blocksize for efficiency */
  1354. static void brcmf_pad(struct brcmf_sdio *bus, u16 *pad, u16 *rdlen)
  1355. {
  1356. if (bus->roundup && bus->blocksize && *rdlen > bus->blocksize) {
  1357. *pad = bus->blocksize - (*rdlen % bus->blocksize);
  1358. if (*pad <= bus->roundup && *pad < bus->blocksize &&
  1359. *rdlen + *pad + BRCMF_FIRSTREAD < MAX_RX_DATASZ)
  1360. *rdlen += *pad;
  1361. } else if (*rdlen % BRCMF_SDALIGN) {
  1362. *rdlen += BRCMF_SDALIGN - (*rdlen % BRCMF_SDALIGN);
  1363. }
  1364. }
  1365. static void
  1366. brcmf_alloc_pkt_and_read(struct brcmf_sdio *bus, u16 rdlen,
  1367. struct sk_buff **pkt, u8 **rxbuf)
  1368. {
  1369. int sdret; /* Return code from calls */
  1370. *pkt = brcmu_pkt_buf_get_skb(rdlen + BRCMF_SDALIGN);
  1371. if (*pkt == NULL)
  1372. return;
  1373. pkt_align(*pkt, rdlen, BRCMF_SDALIGN);
  1374. *rxbuf = (u8 *) ((*pkt)->data);
  1375. /* Read the entire frame */
  1376. sdret = brcmf_sdcard_recv_pkt(bus->sdiodev, bus->sdiodev->sbwad,
  1377. SDIO_FUNC_2, F2SYNC, *pkt);
  1378. bus->f2rxdata++;
  1379. if (sdret < 0) {
  1380. brcmf_dbg(ERROR, "(nextlen): read %d bytes failed: %d\n",
  1381. rdlen, sdret);
  1382. brcmu_pkt_buf_free_skb(*pkt);
  1383. bus->sdiodev->bus_if->dstats.rx_errors++;
  1384. /* Force retry w/normal header read.
  1385. * Don't attempt NAK for
  1386. * gSPI
  1387. */
  1388. brcmf_sdbrcm_rxfail(bus, true, true);
  1389. *pkt = NULL;
  1390. }
  1391. }
  1392. /* Checks the header */
  1393. static int
  1394. brcmf_check_rxbuf(struct brcmf_sdio *bus, struct sk_buff *pkt, u8 *rxbuf,
  1395. u8 rxseq, u16 nextlen, u16 *len)
  1396. {
  1397. u16 check;
  1398. bool len_consistent; /* Result of comparing readahead len and
  1399. len from hw-hdr */
  1400. memcpy(bus->rxhdr, rxbuf, SDPCM_HDRLEN);
  1401. /* Extract hardware header fields */
  1402. *len = get_unaligned_le16(bus->rxhdr);
  1403. check = get_unaligned_le16(bus->rxhdr + sizeof(u16));
  1404. /* All zeros means readahead info was bad */
  1405. if (!(*len | check)) {
  1406. brcmf_dbg(INFO, "(nextlen): read zeros in HW header???\n");
  1407. goto fail;
  1408. }
  1409. /* Validate check bytes */
  1410. if ((u16)~(*len ^ check)) {
  1411. brcmf_dbg(ERROR, "(nextlen): HW hdr error: nextlen/len/check 0x%04x/0x%04x/0x%04x\n",
  1412. nextlen, *len, check);
  1413. bus->rx_badhdr++;
  1414. brcmf_sdbrcm_rxfail(bus, false, false);
  1415. goto fail;
  1416. }
  1417. /* Validate frame length */
  1418. if (*len < SDPCM_HDRLEN) {
  1419. brcmf_dbg(ERROR, "(nextlen): HW hdr length invalid: %d\n",
  1420. *len);
  1421. goto fail;
  1422. }
  1423. /* Check for consistency with readahead info */
  1424. len_consistent = (nextlen != (roundup(*len, 16) >> 4));
  1425. if (len_consistent) {
  1426. /* Mismatch, force retry w/normal
  1427. header (may be >4K) */
  1428. brcmf_dbg(ERROR, "(nextlen): mismatch, nextlen %d len %d rnd %d; expected rxseq %d\n",
  1429. nextlen, *len, roundup(*len, 16),
  1430. rxseq);
  1431. brcmf_sdbrcm_rxfail(bus, true, true);
  1432. goto fail;
  1433. }
  1434. return 0;
  1435. fail:
  1436. brcmf_sdbrcm_pktfree2(bus, pkt);
  1437. return -EINVAL;
  1438. }
  1439. /* Return true if there may be more frames to read */
  1440. static uint
  1441. brcmf_sdbrcm_readframes(struct brcmf_sdio *bus, uint maxframes, bool *finished)
  1442. {
  1443. u16 len, check; /* Extracted hardware header fields */
  1444. u8 chan, seq, doff; /* Extracted software header fields */
  1445. u8 fcbits; /* Extracted fcbits from software header */
  1446. struct sk_buff *pkt; /* Packet for event or data frames */
  1447. u16 pad; /* Number of pad bytes to read */
  1448. u16 rdlen; /* Total number of bytes to read */
  1449. u8 rxseq; /* Next sequence number to expect */
  1450. uint rxleft = 0; /* Remaining number of frames allowed */
  1451. int sdret; /* Return code from calls */
  1452. u8 txmax; /* Maximum tx sequence offered */
  1453. u8 *rxbuf;
  1454. int ifidx = 0;
  1455. uint rxcount = 0; /* Total frames read */
  1456. brcmf_dbg(TRACE, "Enter\n");
  1457. /* Not finished unless we encounter no more frames indication */
  1458. *finished = false;
  1459. for (rxseq = bus->rx_seq, rxleft = maxframes;
  1460. !bus->rxskip && rxleft &&
  1461. bus->sdiodev->bus_if->state != BRCMF_BUS_DOWN;
  1462. rxseq++, rxleft--) {
  1463. /* Handle glomming separately */
  1464. if (bus->glomd || !skb_queue_empty(&bus->glom)) {
  1465. u8 cnt;
  1466. brcmf_dbg(GLOM, "calling rxglom: glomd %p, glom %p\n",
  1467. bus->glomd, skb_peek(&bus->glom));
  1468. cnt = brcmf_sdbrcm_rxglom(bus, rxseq);
  1469. brcmf_dbg(GLOM, "rxglom returned %d\n", cnt);
  1470. rxseq += cnt - 1;
  1471. rxleft = (rxleft > cnt) ? (rxleft - cnt) : 1;
  1472. continue;
  1473. }
  1474. /* Try doing single read if we can */
  1475. if (bus->nextlen) {
  1476. u16 nextlen = bus->nextlen;
  1477. bus->nextlen = 0;
  1478. rdlen = len = nextlen << 4;
  1479. brcmf_pad(bus, &pad, &rdlen);
  1480. /*
  1481. * After the frame is received we have to
  1482. * distinguish whether it is data
  1483. * or non-data frame.
  1484. */
  1485. brcmf_alloc_pkt_and_read(bus, rdlen, &pkt, &rxbuf);
  1486. if (pkt == NULL) {
  1487. /* Give up on data, request rtx of events */
  1488. brcmf_dbg(ERROR, "(nextlen): brcmf_alloc_pkt_and_read failed: len %d rdlen %d expected rxseq %d\n",
  1489. len, rdlen, rxseq);
  1490. continue;
  1491. }
  1492. if (brcmf_check_rxbuf(bus, pkt, rxbuf, rxseq, nextlen,
  1493. &len) < 0)
  1494. continue;
  1495. /* Extract software header fields */
  1496. chan = SDPCM_PACKET_CHANNEL(
  1497. &bus->rxhdr[SDPCM_FRAMETAG_LEN]);
  1498. seq = SDPCM_PACKET_SEQUENCE(
  1499. &bus->rxhdr[SDPCM_FRAMETAG_LEN]);
  1500. doff = SDPCM_DOFFSET_VALUE(
  1501. &bus->rxhdr[SDPCM_FRAMETAG_LEN]);
  1502. txmax = SDPCM_WINDOW_VALUE(
  1503. &bus->rxhdr[SDPCM_FRAMETAG_LEN]);
  1504. bus->nextlen =
  1505. bus->rxhdr[SDPCM_FRAMETAG_LEN +
  1506. SDPCM_NEXTLEN_OFFSET];
  1507. if ((bus->nextlen << 4) > MAX_RX_DATASZ) {
  1508. brcmf_dbg(INFO, "(nextlen): got frame w/nextlen too large (%d), seq %d\n",
  1509. bus->nextlen, seq);
  1510. bus->nextlen = 0;
  1511. }
  1512. bus->rx_readahead_cnt++;
  1513. /* Handle Flow Control */
  1514. fcbits = SDPCM_FCMASK_VALUE(
  1515. &bus->rxhdr[SDPCM_FRAMETAG_LEN]);
  1516. if (bus->flowcontrol != fcbits) {
  1517. if (~bus->flowcontrol & fcbits)
  1518. bus->fc_xoff++;
  1519. if (bus->flowcontrol & ~fcbits)
  1520. bus->fc_xon++;
  1521. bus->fc_rcvd++;
  1522. bus->flowcontrol = fcbits;
  1523. }
  1524. /* Check and update sequence number */
  1525. if (rxseq != seq) {
  1526. brcmf_dbg(INFO, "(nextlen): rx_seq %d, expected %d\n",
  1527. seq, rxseq);
  1528. bus->rx_badseq++;
  1529. rxseq = seq;
  1530. }
  1531. /* Check window for sanity */
  1532. if ((u8) (txmax - bus->tx_seq) > 0x40) {
  1533. brcmf_dbg(ERROR, "got unlikely tx max %d with tx_seq %d\n",
  1534. txmax, bus->tx_seq);
  1535. txmax = bus->tx_seq + 2;
  1536. }
  1537. bus->tx_max = txmax;
  1538. #ifdef BCMDBG
  1539. if (BRCMF_BYTES_ON() && BRCMF_DATA_ON()) {
  1540. printk(KERN_DEBUG "Rx Data:\n");
  1541. print_hex_dump_bytes("", DUMP_PREFIX_OFFSET,
  1542. rxbuf, len);
  1543. } else if (BRCMF_HDRS_ON()) {
  1544. printk(KERN_DEBUG "RxHdr:\n");
  1545. print_hex_dump_bytes("", DUMP_PREFIX_OFFSET,
  1546. bus->rxhdr, SDPCM_HDRLEN);
  1547. }
  1548. #endif
  1549. if (chan == SDPCM_CONTROL_CHANNEL) {
  1550. brcmf_dbg(ERROR, "(nextlen): readahead on control packet %d?\n",
  1551. seq);
  1552. /* Force retry w/normal header read */
  1553. bus->nextlen = 0;
  1554. brcmf_sdbrcm_rxfail(bus, false, true);
  1555. brcmf_sdbrcm_pktfree2(bus, pkt);
  1556. continue;
  1557. }
  1558. /* Validate data offset */
  1559. if ((doff < SDPCM_HDRLEN) || (doff > len)) {
  1560. brcmf_dbg(ERROR, "(nextlen): bad data offset %d: HW len %d min %d\n",
  1561. doff, len, SDPCM_HDRLEN);
  1562. brcmf_sdbrcm_rxfail(bus, false, false);
  1563. brcmf_sdbrcm_pktfree2(bus, pkt);
  1564. continue;
  1565. }
  1566. /* All done with this one -- now deliver the packet */
  1567. goto deliver;
  1568. }
  1569. /* Read frame header (hardware and software) */
  1570. sdret = brcmf_sdcard_recv_buf(bus->sdiodev, bus->sdiodev->sbwad,
  1571. SDIO_FUNC_2, F2SYNC, bus->rxhdr,
  1572. BRCMF_FIRSTREAD);
  1573. bus->f2rxhdrs++;
  1574. if (sdret < 0) {
  1575. brcmf_dbg(ERROR, "RXHEADER FAILED: %d\n", sdret);
  1576. bus->rx_hdrfail++;
  1577. brcmf_sdbrcm_rxfail(bus, true, true);
  1578. continue;
  1579. }
  1580. #ifdef BCMDBG
  1581. if (BRCMF_BYTES_ON() || BRCMF_HDRS_ON()) {
  1582. printk(KERN_DEBUG "RxHdr:\n");
  1583. print_hex_dump_bytes("", DUMP_PREFIX_OFFSET,
  1584. bus->rxhdr, SDPCM_HDRLEN);
  1585. }
  1586. #endif
  1587. /* Extract hardware header fields */
  1588. len = get_unaligned_le16(bus->rxhdr);
  1589. check = get_unaligned_le16(bus->rxhdr + sizeof(u16));
  1590. /* All zeros means no more frames */
  1591. if (!(len | check)) {
  1592. *finished = true;
  1593. break;
  1594. }
  1595. /* Validate check bytes */
  1596. if ((u16) ~(len ^ check)) {
  1597. brcmf_dbg(ERROR, "HW hdr err: len/check 0x%04x/0x%04x\n",
  1598. len, check);
  1599. bus->rx_badhdr++;
  1600. brcmf_sdbrcm_rxfail(bus, false, false);
  1601. continue;
  1602. }
  1603. /* Validate frame length */
  1604. if (len < SDPCM_HDRLEN) {
  1605. brcmf_dbg(ERROR, "HW hdr length invalid: %d\n", len);
  1606. continue;
  1607. }
  1608. /* Extract software header fields */
  1609. chan = SDPCM_PACKET_CHANNEL(&bus->rxhdr[SDPCM_FRAMETAG_LEN]);
  1610. seq = SDPCM_PACKET_SEQUENCE(&bus->rxhdr[SDPCM_FRAMETAG_LEN]);
  1611. doff = SDPCM_DOFFSET_VALUE(&bus->rxhdr[SDPCM_FRAMETAG_LEN]);
  1612. txmax = SDPCM_WINDOW_VALUE(&bus->rxhdr[SDPCM_FRAMETAG_LEN]);
  1613. /* Validate data offset */
  1614. if ((doff < SDPCM_HDRLEN) || (doff > len)) {
  1615. brcmf_dbg(ERROR, "Bad data offset %d: HW len %d, min %d seq %d\n",
  1616. doff, len, SDPCM_HDRLEN, seq);
  1617. bus->rx_badhdr++;
  1618. brcmf_sdbrcm_rxfail(bus, false, false);
  1619. continue;
  1620. }
  1621. /* Save the readahead length if there is one */
  1622. bus->nextlen =
  1623. bus->rxhdr[SDPCM_FRAMETAG_LEN + SDPCM_NEXTLEN_OFFSET];
  1624. if ((bus->nextlen << 4) > MAX_RX_DATASZ) {
  1625. brcmf_dbg(INFO, "(nextlen): got frame w/nextlen too large (%d), seq %d\n",
  1626. bus->nextlen, seq);
  1627. bus->nextlen = 0;
  1628. }
  1629. /* Handle Flow Control */
  1630. fcbits = SDPCM_FCMASK_VALUE(&bus->rxhdr[SDPCM_FRAMETAG_LEN]);
  1631. if (bus->flowcontrol != fcbits) {
  1632. if (~bus->flowcontrol & fcbits)
  1633. bus->fc_xoff++;
  1634. if (bus->flowcontrol & ~fcbits)
  1635. bus->fc_xon++;
  1636. bus->fc_rcvd++;
  1637. bus->flowcontrol = fcbits;
  1638. }
  1639. /* Check and update sequence number */
  1640. if (rxseq != seq) {
  1641. brcmf_dbg(INFO, "rx_seq %d, expected %d\n", seq, rxseq);
  1642. bus->rx_badseq++;
  1643. rxseq = seq;
  1644. }
  1645. /* Check window for sanity */
  1646. if ((u8) (txmax - bus->tx_seq) > 0x40) {
  1647. brcmf_dbg(ERROR, "unlikely tx max %d with tx_seq %d\n",
  1648. txmax, bus->tx_seq);
  1649. txmax = bus->tx_seq + 2;
  1650. }
  1651. bus->tx_max = txmax;
  1652. /* Call a separate function for control frames */
  1653. if (chan == SDPCM_CONTROL_CHANNEL) {
  1654. brcmf_sdbrcm_read_control(bus, bus->rxhdr, len, doff);
  1655. continue;
  1656. }
  1657. /* precondition: chan is either SDPCM_DATA_CHANNEL,
  1658. SDPCM_EVENT_CHANNEL, SDPCM_TEST_CHANNEL or
  1659. SDPCM_GLOM_CHANNEL */
  1660. /* Length to read */
  1661. rdlen = (len > BRCMF_FIRSTREAD) ? (len - BRCMF_FIRSTREAD) : 0;
  1662. /* May pad read to blocksize for efficiency */
  1663. if (bus->roundup && bus->blocksize &&
  1664. (rdlen > bus->blocksize)) {
  1665. pad = bus->blocksize - (rdlen % bus->blocksize);
  1666. if ((pad <= bus->roundup) && (pad < bus->blocksize) &&
  1667. ((rdlen + pad + BRCMF_FIRSTREAD) < MAX_RX_DATASZ))
  1668. rdlen += pad;
  1669. } else if (rdlen % BRCMF_SDALIGN) {
  1670. rdlen += BRCMF_SDALIGN - (rdlen % BRCMF_SDALIGN);
  1671. }
  1672. /* Satisfy length-alignment requirements */
  1673. if (rdlen & (ALIGNMENT - 1))
  1674. rdlen = roundup(rdlen, ALIGNMENT);
  1675. if ((rdlen + BRCMF_FIRSTREAD) > MAX_RX_DATASZ) {
  1676. /* Too long -- skip this frame */
  1677. brcmf_dbg(ERROR, "too long: len %d rdlen %d\n",
  1678. len, rdlen);
  1679. bus->sdiodev->bus_if->dstats.rx_errors++;
  1680. bus->rx_toolong++;
  1681. brcmf_sdbrcm_rxfail(bus, false, false);
  1682. continue;
  1683. }
  1684. pkt = brcmu_pkt_buf_get_skb(rdlen +
  1685. BRCMF_FIRSTREAD + BRCMF_SDALIGN);
  1686. if (!pkt) {
  1687. /* Give up on data, request rtx of events */
  1688. brcmf_dbg(ERROR, "brcmu_pkt_buf_get_skb failed: rdlen %d chan %d\n",
  1689. rdlen, chan);
  1690. bus->sdiodev->bus_if->dstats.rx_dropped++;
  1691. brcmf_sdbrcm_rxfail(bus, false, RETRYCHAN(chan));
  1692. continue;
  1693. }
  1694. /* Leave room for what we already read, and align remainder */
  1695. skb_pull(pkt, BRCMF_FIRSTREAD);
  1696. pkt_align(pkt, rdlen, BRCMF_SDALIGN);
  1697. /* Read the remaining frame data */
  1698. sdret = brcmf_sdcard_recv_pkt(bus->sdiodev, bus->sdiodev->sbwad,
  1699. SDIO_FUNC_2, F2SYNC, pkt);
  1700. bus->f2rxdata++;
  1701. if (sdret < 0) {
  1702. brcmf_dbg(ERROR, "read %d %s bytes failed: %d\n", rdlen,
  1703. ((chan == SDPCM_EVENT_CHANNEL) ? "event"
  1704. : ((chan == SDPCM_DATA_CHANNEL) ? "data"
  1705. : "test")), sdret);
  1706. brcmu_pkt_buf_free_skb(pkt);
  1707. bus->sdiodev->bus_if->dstats.rx_errors++;
  1708. brcmf_sdbrcm_rxfail(bus, true, RETRYCHAN(chan));
  1709. continue;
  1710. }
  1711. /* Copy the already-read portion */
  1712. skb_push(pkt, BRCMF_FIRSTREAD);
  1713. memcpy(pkt->data, bus->rxhdr, BRCMF_FIRSTREAD);
  1714. #ifdef BCMDBG
  1715. if (BRCMF_BYTES_ON() && BRCMF_DATA_ON()) {
  1716. printk(KERN_DEBUG "Rx Data:\n");
  1717. print_hex_dump_bytes("", DUMP_PREFIX_OFFSET,
  1718. pkt->data, len);
  1719. }
  1720. #endif
  1721. deliver:
  1722. /* Save superframe descriptor and allocate packet frame */
  1723. if (chan == SDPCM_GLOM_CHANNEL) {
  1724. if (SDPCM_GLOMDESC(&bus->rxhdr[SDPCM_FRAMETAG_LEN])) {
  1725. brcmf_dbg(GLOM, "glom descriptor, %d bytes:\n",
  1726. len);
  1727. #ifdef BCMDBG
  1728. if (BRCMF_GLOM_ON()) {
  1729. printk(KERN_DEBUG "Glom Data:\n");
  1730. print_hex_dump_bytes("",
  1731. DUMP_PREFIX_OFFSET,
  1732. pkt->data, len);
  1733. }
  1734. #endif
  1735. __skb_trim(pkt, len);
  1736. skb_pull(pkt, SDPCM_HDRLEN);
  1737. bus->glomd = pkt;
  1738. } else {
  1739. brcmf_dbg(ERROR, "%s: glom superframe w/o "
  1740. "descriptor!\n", __func__);
  1741. brcmf_sdbrcm_rxfail(bus, false, false);
  1742. }
  1743. continue;
  1744. }
  1745. /* Fill in packet len and prio, deliver upward */
  1746. __skb_trim(pkt, len);
  1747. skb_pull(pkt, doff);
  1748. if (pkt->len == 0) {
  1749. brcmu_pkt_buf_free_skb(pkt);
  1750. continue;
  1751. } else if (brcmf_proto_hdrpull(bus->sdiodev->dev, &ifidx,
  1752. pkt) != 0) {
  1753. brcmf_dbg(ERROR, "rx protocol error\n");
  1754. brcmu_pkt_buf_free_skb(pkt);
  1755. bus->sdiodev->bus_if->dstats.rx_errors++;
  1756. continue;
  1757. }
  1758. /* Unlock during rx call */
  1759. up(&bus->sdsem);
  1760. brcmf_rx_packet(bus->sdiodev->dev, ifidx, pkt);
  1761. down(&bus->sdsem);
  1762. }
  1763. rxcount = maxframes - rxleft;
  1764. #ifdef BCMDBG
  1765. /* Message if we hit the limit */
  1766. if (!rxleft)
  1767. brcmf_dbg(DATA, "hit rx limit of %d frames\n",
  1768. maxframes);
  1769. else
  1770. #endif /* BCMDBG */
  1771. brcmf_dbg(DATA, "processed %d frames\n", rxcount);
  1772. /* Back off rxseq if awaiting rtx, update rx_seq */
  1773. if (bus->rxskip)
  1774. rxseq--;
  1775. bus->rx_seq = rxseq;
  1776. return rxcount;
  1777. }
  1778. static void
  1779. brcmf_sdbrcm_wait_for_event(struct brcmf_sdio *bus, bool *lockvar)
  1780. {
  1781. up(&bus->sdsem);
  1782. wait_event_interruptible_timeout(bus->ctrl_wait,
  1783. (*lockvar == false), HZ * 2);
  1784. down(&bus->sdsem);
  1785. return;
  1786. }
  1787. static void
  1788. brcmf_sdbrcm_wait_event_wakeup(struct brcmf_sdio *bus)
  1789. {
  1790. if (waitqueue_active(&bus->ctrl_wait))
  1791. wake_up_interruptible(&bus->ctrl_wait);
  1792. return;
  1793. }
  1794. /* Writes a HW/SW header into the packet and sends it. */
  1795. /* Assumes: (a) header space already there, (b) caller holds lock */
  1796. static int brcmf_sdbrcm_txpkt(struct brcmf_sdio *bus, struct sk_buff *pkt,
  1797. uint chan, bool free_pkt)
  1798. {
  1799. int ret;
  1800. u8 *frame;
  1801. u16 len, pad = 0;
  1802. u32 swheader;
  1803. struct sk_buff *new;
  1804. int i;
  1805. brcmf_dbg(TRACE, "Enter\n");
  1806. frame = (u8 *) (pkt->data);
  1807. /* Add alignment padding, allocate new packet if needed */
  1808. pad = ((unsigned long)frame % BRCMF_SDALIGN);
  1809. if (pad) {
  1810. if (skb_headroom(pkt) < pad) {
  1811. brcmf_dbg(INFO, "insufficient headroom %d for %d pad\n",
  1812. skb_headroom(pkt), pad);
  1813. bus->sdiodev->bus_if->tx_realloc++;
  1814. new = brcmu_pkt_buf_get_skb(pkt->len + BRCMF_SDALIGN);
  1815. if (!new) {
  1816. brcmf_dbg(ERROR, "couldn't allocate new %d-byte packet\n",
  1817. pkt->len + BRCMF_SDALIGN);
  1818. ret = -ENOMEM;
  1819. goto done;
  1820. }
  1821. pkt_align(new, pkt->len, BRCMF_SDALIGN);
  1822. memcpy(new->data, pkt->data, pkt->len);
  1823. if (free_pkt)
  1824. brcmu_pkt_buf_free_skb(pkt);
  1825. /* free the pkt if canned one is not used */
  1826. free_pkt = true;
  1827. pkt = new;
  1828. frame = (u8 *) (pkt->data);
  1829. /* precondition: (frame % BRCMF_SDALIGN) == 0) */
  1830. pad = 0;
  1831. } else {
  1832. skb_push(pkt, pad);
  1833. frame = (u8 *) (pkt->data);
  1834. /* precondition: pad + SDPCM_HDRLEN <= pkt->len */
  1835. memset(frame, 0, pad + SDPCM_HDRLEN);
  1836. }
  1837. }
  1838. /* precondition: pad < BRCMF_SDALIGN */
  1839. /* Hardware tag: 2 byte len followed by 2 byte ~len check (all LE) */
  1840. len = (u16) (pkt->len);
  1841. *(__le16 *) frame = cpu_to_le16(len);
  1842. *(((__le16 *) frame) + 1) = cpu_to_le16(~len);
  1843. /* Software tag: channel, sequence number, data offset */
  1844. swheader =
  1845. ((chan << SDPCM_CHANNEL_SHIFT) & SDPCM_CHANNEL_MASK) | bus->tx_seq |
  1846. (((pad +
  1847. SDPCM_HDRLEN) << SDPCM_DOFFSET_SHIFT) & SDPCM_DOFFSET_MASK);
  1848. put_unaligned_le32(swheader, frame + SDPCM_FRAMETAG_LEN);
  1849. put_unaligned_le32(0, frame + SDPCM_FRAMETAG_LEN + sizeof(swheader));
  1850. #ifdef BCMDBG
  1851. tx_packets[pkt->priority]++;
  1852. if (BRCMF_BYTES_ON() &&
  1853. (((BRCMF_CTL_ON() && (chan == SDPCM_CONTROL_CHANNEL)) ||
  1854. (BRCMF_DATA_ON() && (chan != SDPCM_CONTROL_CHANNEL))))) {
  1855. printk(KERN_DEBUG "Tx Frame:\n");
  1856. print_hex_dump_bytes("", DUMP_PREFIX_OFFSET, frame, len);
  1857. } else if (BRCMF_HDRS_ON()) {
  1858. printk(KERN_DEBUG "TxHdr:\n");
  1859. print_hex_dump_bytes("", DUMP_PREFIX_OFFSET,
  1860. frame, min_t(u16, len, 16));
  1861. }
  1862. #endif
  1863. /* Raise len to next SDIO block to eliminate tail command */
  1864. if (bus->roundup && bus->blocksize && (len > bus->blocksize)) {
  1865. u16 pad = bus->blocksize - (len % bus->blocksize);
  1866. if ((pad <= bus->roundup) && (pad < bus->blocksize))
  1867. len += pad;
  1868. } else if (len % BRCMF_SDALIGN) {
  1869. len += BRCMF_SDALIGN - (len % BRCMF_SDALIGN);
  1870. }
  1871. /* Some controllers have trouble with odd bytes -- round to even */
  1872. if (len & (ALIGNMENT - 1))
  1873. len = roundup(len, ALIGNMENT);
  1874. ret = brcmf_sdcard_send_pkt(bus->sdiodev, bus->sdiodev->sbwad,
  1875. SDIO_FUNC_2, F2SYNC, pkt);
  1876. bus->f2txdata++;
  1877. if (ret < 0) {
  1878. /* On failure, abort the command and terminate the frame */
  1879. brcmf_dbg(INFO, "sdio error %d, abort command and terminate frame\n",
  1880. ret);
  1881. bus->tx_sderrs++;
  1882. brcmf_sdcard_abort(bus->sdiodev, SDIO_FUNC_2);
  1883. brcmf_sdcard_cfg_write(bus->sdiodev, SDIO_FUNC_1,
  1884. SBSDIO_FUNC1_FRAMECTRL, SFC_WF_TERM,
  1885. NULL);
  1886. bus->f1regdata++;
  1887. for (i = 0; i < 3; i++) {
  1888. u8 hi, lo;
  1889. hi = brcmf_sdcard_cfg_read(bus->sdiodev,
  1890. SDIO_FUNC_1,
  1891. SBSDIO_FUNC1_WFRAMEBCHI,
  1892. NULL);
  1893. lo = brcmf_sdcard_cfg_read(bus->sdiodev,
  1894. SDIO_FUNC_1,
  1895. SBSDIO_FUNC1_WFRAMEBCLO,
  1896. NULL);
  1897. bus->f1regdata += 2;
  1898. if ((hi == 0) && (lo == 0))
  1899. break;
  1900. }
  1901. }
  1902. if (ret == 0)
  1903. bus->tx_seq = (bus->tx_seq + 1) % SDPCM_SEQUENCE_WRAP;
  1904. done:
  1905. /* restore pkt buffer pointer before calling tx complete routine */
  1906. skb_pull(pkt, SDPCM_HDRLEN + pad);
  1907. up(&bus->sdsem);
  1908. brcmf_txcomplete(bus->sdiodev->dev, pkt, ret != 0);
  1909. down(&bus->sdsem);
  1910. if (free_pkt)
  1911. brcmu_pkt_buf_free_skb(pkt);
  1912. return ret;
  1913. }
  1914. static uint brcmf_sdbrcm_sendfromq(struct brcmf_sdio *bus, uint maxframes)
  1915. {
  1916. struct sk_buff *pkt;
  1917. u32 intstatus = 0;
  1918. uint retries = 0;
  1919. int ret = 0, prec_out;
  1920. uint cnt = 0;
  1921. uint datalen;
  1922. u8 tx_prec_map;
  1923. brcmf_dbg(TRACE, "Enter\n");
  1924. tx_prec_map = ~bus->flowcontrol;
  1925. /* Send frames until the limit or some other event */
  1926. for (cnt = 0; (cnt < maxframes) && data_ok(bus); cnt++) {
  1927. spin_lock_bh(&bus->txqlock);
  1928. pkt = brcmu_pktq_mdeq(&bus->txq, tx_prec_map, &prec_out);
  1929. if (pkt == NULL) {
  1930. spin_unlock_bh(&bus->txqlock);
  1931. break;
  1932. }
  1933. spin_unlock_bh(&bus->txqlock);
  1934. datalen = pkt->len - SDPCM_HDRLEN;
  1935. ret = brcmf_sdbrcm_txpkt(bus, pkt, SDPCM_DATA_CHANNEL, true);
  1936. if (ret)
  1937. bus->sdiodev->bus_if->dstats.tx_errors++;
  1938. else
  1939. bus->sdiodev->bus_if->dstats.tx_bytes += datalen;
  1940. /* In poll mode, need to check for other events */
  1941. if (!bus->intr && cnt) {
  1942. /* Check device status, signal pending interrupt */
  1943. r_sdreg32(bus, &intstatus,
  1944. offsetof(struct sdpcmd_regs, intstatus),
  1945. &retries);
  1946. bus->f2txdata++;
  1947. if (brcmf_sdcard_regfail(bus->sdiodev))
  1948. break;
  1949. if (intstatus & bus->hostintmask)
  1950. bus->ipend = true;
  1951. }
  1952. }
  1953. /* Deflow-control stack if needed */
  1954. if (bus->sdiodev->bus_if->drvr_up &&
  1955. (bus->sdiodev->bus_if->state == BRCMF_BUS_DATA) &&
  1956. bus->txoff && (pktq_len(&bus->txq) < TXLOW)) {
  1957. bus->txoff = OFF;
  1958. brcmf_txflowcontrol(bus->sdiodev->dev, 0, OFF);
  1959. }
  1960. return cnt;
  1961. }
  1962. static void brcmf_sdbrcm_bus_stop(struct device *dev)
  1963. {
  1964. u32 local_hostintmask;
  1965. u8 saveclk;
  1966. uint retries;
  1967. int err;
  1968. struct brcmf_bus *bus_if = dev_get_drvdata(dev);
  1969. struct brcmf_sdio_dev *sdiodev = bus_if->bus_priv;
  1970. struct brcmf_sdio *bus = sdiodev->bus;
  1971. brcmf_dbg(TRACE, "Enter\n");
  1972. if (bus->watchdog_tsk) {
  1973. send_sig(SIGTERM, bus->watchdog_tsk, 1);
  1974. kthread_stop(bus->watchdog_tsk);
  1975. bus->watchdog_tsk = NULL;
  1976. }
  1977. if (bus->dpc_tsk && bus->dpc_tsk != current) {
  1978. send_sig(SIGTERM, bus->dpc_tsk, 1);
  1979. kthread_stop(bus->dpc_tsk);
  1980. bus->dpc_tsk = NULL;
  1981. }
  1982. down(&bus->sdsem);
  1983. bus_wake(bus);
  1984. /* Enable clock for device interrupts */
  1985. brcmf_sdbrcm_clkctl(bus, CLK_AVAIL, false);
  1986. /* Disable and clear interrupts at the chip level also */
  1987. w_sdreg32(bus, 0, offsetof(struct sdpcmd_regs, hostintmask), &retries);
  1988. local_hostintmask = bus->hostintmask;
  1989. bus->hostintmask = 0;
  1990. /* Change our idea of bus state */
  1991. bus->sdiodev->bus_if->state = BRCMF_BUS_DOWN;
  1992. /* Force clocks on backplane to be sure F2 interrupt propagates */
  1993. saveclk = brcmf_sdcard_cfg_read(bus->sdiodev, SDIO_FUNC_1,
  1994. SBSDIO_FUNC1_CHIPCLKCSR, &err);
  1995. if (!err) {
  1996. brcmf_sdcard_cfg_write(bus->sdiodev, SDIO_FUNC_1,
  1997. SBSDIO_FUNC1_CHIPCLKCSR,
  1998. (saveclk | SBSDIO_FORCE_HT), &err);
  1999. }
  2000. if (err)
  2001. brcmf_dbg(ERROR, "Failed to force clock for F2: err %d\n", err);
  2002. /* Turn off the bus (F2), free any pending packets */
  2003. brcmf_dbg(INTR, "disable SDIO interrupts\n");
  2004. brcmf_sdcard_cfg_write(bus->sdiodev, SDIO_FUNC_0, SDIO_CCCR_IOEx,
  2005. SDIO_FUNC_ENABLE_1, NULL);
  2006. /* Clear any pending interrupts now that F2 is disabled */
  2007. w_sdreg32(bus, local_hostintmask,
  2008. offsetof(struct sdpcmd_regs, intstatus), &retries);
  2009. /* Turn off the backplane clock (only) */
  2010. brcmf_sdbrcm_clkctl(bus, CLK_SDONLY, false);
  2011. /* Clear the data packet queues */
  2012. brcmu_pktq_flush(&bus->txq, true, NULL, NULL);
  2013. /* Clear any held glomming stuff */
  2014. if (bus->glomd)
  2015. brcmu_pkt_buf_free_skb(bus->glomd);
  2016. brcmf_sdbrcm_free_glom(bus);
  2017. /* Clear rx control and wake any waiters */
  2018. bus->rxlen = 0;
  2019. brcmf_sdbrcm_dcmd_resp_wake(bus);
  2020. /* Reset some F2 state stuff */
  2021. bus->rxskip = false;
  2022. bus->tx_seq = bus->rx_seq = 0;
  2023. up(&bus->sdsem);
  2024. }
  2025. static bool brcmf_sdbrcm_dpc(struct brcmf_sdio *bus)
  2026. {
  2027. u32 intstatus, newstatus = 0;
  2028. uint retries = 0;
  2029. uint rxlimit = bus->rxbound; /* Rx frames to read before resched */
  2030. uint txlimit = bus->txbound; /* Tx frames to send before resched */
  2031. uint framecnt = 0; /* Temporary counter of tx/rx frames */
  2032. bool rxdone = true; /* Flag for no more read data */
  2033. bool resched = false; /* Flag indicating resched wanted */
  2034. brcmf_dbg(TRACE, "Enter\n");
  2035. /* Start with leftover status bits */
  2036. intstatus = bus->intstatus;
  2037. down(&bus->sdsem);
  2038. /* If waiting for HTAVAIL, check status */
  2039. if (bus->clkstate == CLK_PENDING) {
  2040. int err;
  2041. u8 clkctl, devctl = 0;
  2042. #ifdef BCMDBG
  2043. /* Check for inconsistent device control */
  2044. devctl = brcmf_sdcard_cfg_read(bus->sdiodev, SDIO_FUNC_1,
  2045. SBSDIO_DEVICE_CTL, &err);
  2046. if (err) {
  2047. brcmf_dbg(ERROR, "error reading DEVCTL: %d\n", err);
  2048. bus->sdiodev->bus_if->state = BRCMF_BUS_DOWN;
  2049. }
  2050. #endif /* BCMDBG */
  2051. /* Read CSR, if clock on switch to AVAIL, else ignore */
  2052. clkctl = brcmf_sdcard_cfg_read(bus->sdiodev, SDIO_FUNC_1,
  2053. SBSDIO_FUNC1_CHIPCLKCSR, &err);
  2054. if (err) {
  2055. brcmf_dbg(ERROR, "error reading CSR: %d\n",
  2056. err);
  2057. bus->sdiodev->bus_if->state = BRCMF_BUS_DOWN;
  2058. }
  2059. brcmf_dbg(INFO, "DPC: PENDING, devctl 0x%02x clkctl 0x%02x\n",
  2060. devctl, clkctl);
  2061. if (SBSDIO_HTAV(clkctl)) {
  2062. devctl = brcmf_sdcard_cfg_read(bus->sdiodev,
  2063. SDIO_FUNC_1,
  2064. SBSDIO_DEVICE_CTL, &err);
  2065. if (err) {
  2066. brcmf_dbg(ERROR, "error reading DEVCTL: %d\n",
  2067. err);
  2068. bus->sdiodev->bus_if->state = BRCMF_BUS_DOWN;
  2069. }
  2070. devctl &= ~SBSDIO_DEVCTL_CA_INT_ONLY;
  2071. brcmf_sdcard_cfg_write(bus->sdiodev, SDIO_FUNC_1,
  2072. SBSDIO_DEVICE_CTL, devctl, &err);
  2073. if (err) {
  2074. brcmf_dbg(ERROR, "error writing DEVCTL: %d\n",
  2075. err);
  2076. bus->sdiodev->bus_if->state = BRCMF_BUS_DOWN;
  2077. }
  2078. bus->clkstate = CLK_AVAIL;
  2079. } else {
  2080. goto clkwait;
  2081. }
  2082. }
  2083. bus_wake(bus);
  2084. /* Make sure backplane clock is on */
  2085. brcmf_sdbrcm_clkctl(bus, CLK_AVAIL, true);
  2086. if (bus->clkstate == CLK_PENDING)
  2087. goto clkwait;
  2088. /* Pending interrupt indicates new device status */
  2089. if (bus->ipend) {
  2090. bus->ipend = false;
  2091. r_sdreg32(bus, &newstatus,
  2092. offsetof(struct sdpcmd_regs, intstatus), &retries);
  2093. bus->f1regdata++;
  2094. if (brcmf_sdcard_regfail(bus->sdiodev))
  2095. newstatus = 0;
  2096. newstatus &= bus->hostintmask;
  2097. bus->fcstate = !!(newstatus & I_HMB_FC_STATE);
  2098. if (newstatus) {
  2099. w_sdreg32(bus, newstatus,
  2100. offsetof(struct sdpcmd_regs, intstatus),
  2101. &retries);
  2102. bus->f1regdata++;
  2103. }
  2104. }
  2105. /* Merge new bits with previous */
  2106. intstatus |= newstatus;
  2107. bus->intstatus = 0;
  2108. /* Handle flow-control change: read new state in case our ack
  2109. * crossed another change interrupt. If change still set, assume
  2110. * FC ON for safety, let next loop through do the debounce.
  2111. */
  2112. if (intstatus & I_HMB_FC_CHANGE) {
  2113. intstatus &= ~I_HMB_FC_CHANGE;
  2114. w_sdreg32(bus, I_HMB_FC_CHANGE,
  2115. offsetof(struct sdpcmd_regs, intstatus), &retries);
  2116. r_sdreg32(bus, &newstatus,
  2117. offsetof(struct sdpcmd_regs, intstatus), &retries);
  2118. bus->f1regdata += 2;
  2119. bus->fcstate =
  2120. !!(newstatus & (I_HMB_FC_STATE | I_HMB_FC_CHANGE));
  2121. intstatus |= (newstatus & bus->hostintmask);
  2122. }
  2123. /* Handle host mailbox indication */
  2124. if (intstatus & I_HMB_HOST_INT) {
  2125. intstatus &= ~I_HMB_HOST_INT;
  2126. intstatus |= brcmf_sdbrcm_hostmail(bus);
  2127. }
  2128. /* Generally don't ask for these, can get CRC errors... */
  2129. if (intstatus & I_WR_OOSYNC) {
  2130. brcmf_dbg(ERROR, "Dongle reports WR_OOSYNC\n");
  2131. intstatus &= ~I_WR_OOSYNC;
  2132. }
  2133. if (intstatus & I_RD_OOSYNC) {
  2134. brcmf_dbg(ERROR, "Dongle reports RD_OOSYNC\n");
  2135. intstatus &= ~I_RD_OOSYNC;
  2136. }
  2137. if (intstatus & I_SBINT) {
  2138. brcmf_dbg(ERROR, "Dongle reports SBINT\n");
  2139. intstatus &= ~I_SBINT;
  2140. }
  2141. /* Would be active due to wake-wlan in gSPI */
  2142. if (intstatus & I_CHIPACTIVE) {
  2143. brcmf_dbg(INFO, "Dongle reports CHIPACTIVE\n");
  2144. intstatus &= ~I_CHIPACTIVE;
  2145. }
  2146. /* Ignore frame indications if rxskip is set */
  2147. if (bus->rxskip)
  2148. intstatus &= ~I_HMB_FRAME_IND;
  2149. /* On frame indication, read available frames */
  2150. if (PKT_AVAILABLE()) {
  2151. framecnt = brcmf_sdbrcm_readframes(bus, rxlimit, &rxdone);
  2152. if (rxdone || bus->rxskip)
  2153. intstatus &= ~I_HMB_FRAME_IND;
  2154. rxlimit -= min(framecnt, rxlimit);
  2155. }
  2156. /* Keep still-pending events for next scheduling */
  2157. bus->intstatus = intstatus;
  2158. clkwait:
  2159. if (data_ok(bus) && bus->ctrl_frame_stat &&
  2160. (bus->clkstate == CLK_AVAIL)) {
  2161. int ret, i;
  2162. ret = brcmf_sdcard_send_buf(bus->sdiodev, bus->sdiodev->sbwad,
  2163. SDIO_FUNC_2, F2SYNC, (u8 *) bus->ctrl_frame_buf,
  2164. (u32) bus->ctrl_frame_len);
  2165. if (ret < 0) {
  2166. /* On failure, abort the command and
  2167. terminate the frame */
  2168. brcmf_dbg(INFO, "sdio error %d, abort command and terminate frame\n",
  2169. ret);
  2170. bus->tx_sderrs++;
  2171. brcmf_sdcard_abort(bus->sdiodev, SDIO_FUNC_2);
  2172. brcmf_sdcard_cfg_write(bus->sdiodev, SDIO_FUNC_1,
  2173. SBSDIO_FUNC1_FRAMECTRL, SFC_WF_TERM,
  2174. NULL);
  2175. bus->f1regdata++;
  2176. for (i = 0; i < 3; i++) {
  2177. u8 hi, lo;
  2178. hi = brcmf_sdcard_cfg_read(bus->sdiodev,
  2179. SDIO_FUNC_1,
  2180. SBSDIO_FUNC1_WFRAMEBCHI,
  2181. NULL);
  2182. lo = brcmf_sdcard_cfg_read(bus->sdiodev,
  2183. SDIO_FUNC_1,
  2184. SBSDIO_FUNC1_WFRAMEBCLO,
  2185. NULL);
  2186. bus->f1regdata += 2;
  2187. if ((hi == 0) && (lo == 0))
  2188. break;
  2189. }
  2190. }
  2191. if (ret == 0)
  2192. bus->tx_seq = (bus->tx_seq + 1) % SDPCM_SEQUENCE_WRAP;
  2193. brcmf_dbg(INFO, "Return_dpc value is : %d\n", ret);
  2194. bus->ctrl_frame_stat = false;
  2195. brcmf_sdbrcm_wait_event_wakeup(bus);
  2196. }
  2197. /* Send queued frames (limit 1 if rx may still be pending) */
  2198. else if ((bus->clkstate == CLK_AVAIL) && !bus->fcstate &&
  2199. brcmu_pktq_mlen(&bus->txq, ~bus->flowcontrol) && txlimit
  2200. && data_ok(bus)) {
  2201. framecnt = rxdone ? txlimit : min(txlimit, bus->txminmax);
  2202. framecnt = brcmf_sdbrcm_sendfromq(bus, framecnt);
  2203. txlimit -= framecnt;
  2204. }
  2205. /* Resched if events or tx frames are pending,
  2206. else await next interrupt */
  2207. /* On failed register access, all bets are off:
  2208. no resched or interrupts */
  2209. if ((bus->sdiodev->bus_if->state == BRCMF_BUS_DOWN) ||
  2210. brcmf_sdcard_regfail(bus->sdiodev)) {
  2211. brcmf_dbg(ERROR, "failed backplane access over SDIO, halting operation %d\n",
  2212. brcmf_sdcard_regfail(bus->sdiodev));
  2213. bus->sdiodev->bus_if->state = BRCMF_BUS_DOWN;
  2214. bus->intstatus = 0;
  2215. } else if (bus->clkstate == CLK_PENDING) {
  2216. brcmf_dbg(INFO, "rescheduled due to CLK_PENDING awaiting I_CHIPACTIVE interrupt\n");
  2217. resched = true;
  2218. } else if (bus->intstatus || bus->ipend ||
  2219. (!bus->fcstate && brcmu_pktq_mlen(&bus->txq, ~bus->flowcontrol)
  2220. && data_ok(bus)) || PKT_AVAILABLE()) {
  2221. resched = true;
  2222. }
  2223. bus->dpc_sched = resched;
  2224. /* If we're done for now, turn off clock request. */
  2225. if ((bus->clkstate != CLK_PENDING)
  2226. && bus->idletime == BRCMF_IDLE_IMMEDIATE) {
  2227. bus->activity = false;
  2228. brcmf_sdbrcm_clkctl(bus, CLK_NONE, false);
  2229. }
  2230. up(&bus->sdsem);
  2231. return resched;
  2232. }
  2233. static int brcmf_sdbrcm_dpc_thread(void *data)
  2234. {
  2235. struct brcmf_sdio *bus = (struct brcmf_sdio *) data;
  2236. allow_signal(SIGTERM);
  2237. /* Run until signal received */
  2238. while (1) {
  2239. if (kthread_should_stop())
  2240. break;
  2241. if (!wait_for_completion_interruptible(&bus->dpc_wait)) {
  2242. /* Call bus dpc unless it indicated down
  2243. (then clean stop) */
  2244. if (bus->sdiodev->bus_if->state != BRCMF_BUS_DOWN) {
  2245. if (brcmf_sdbrcm_dpc(bus))
  2246. complete(&bus->dpc_wait);
  2247. } else {
  2248. /* after stopping the bus, exit thread */
  2249. brcmf_sdbrcm_bus_stop(bus->sdiodev->dev);
  2250. bus->dpc_tsk = NULL;
  2251. break;
  2252. }
  2253. } else
  2254. break;
  2255. }
  2256. return 0;
  2257. }
  2258. static int brcmf_sdbrcm_bus_txdata(struct device *dev, struct sk_buff *pkt)
  2259. {
  2260. int ret = -EBADE;
  2261. uint datalen, prec;
  2262. struct brcmf_bus *bus_if = dev_get_drvdata(dev);
  2263. struct brcmf_sdio_dev *sdiodev = bus_if->bus_priv;
  2264. struct brcmf_sdio *bus = sdiodev->bus;
  2265. brcmf_dbg(TRACE, "Enter\n");
  2266. datalen = pkt->len;
  2267. /* Add space for the header */
  2268. skb_push(pkt, SDPCM_HDRLEN);
  2269. /* precondition: IS_ALIGNED((unsigned long)(pkt->data), 2) */
  2270. prec = prio2prec((pkt->priority & PRIOMASK));
  2271. /* Check for existing queue, current flow-control,
  2272. pending event, or pending clock */
  2273. brcmf_dbg(TRACE, "deferring pktq len %d\n", pktq_len(&bus->txq));
  2274. bus->fcqueued++;
  2275. /* Priority based enq */
  2276. spin_lock_bh(&bus->txqlock);
  2277. if (brcmf_c_prec_enq(bus->sdiodev->dev, &bus->txq, pkt, prec) ==
  2278. false) {
  2279. skb_pull(pkt, SDPCM_HDRLEN);
  2280. brcmf_txcomplete(bus->sdiodev->dev, pkt, false);
  2281. brcmu_pkt_buf_free_skb(pkt);
  2282. brcmf_dbg(ERROR, "out of bus->txq !!!\n");
  2283. ret = -ENOSR;
  2284. } else {
  2285. ret = 0;
  2286. }
  2287. spin_unlock_bh(&bus->txqlock);
  2288. if (pktq_len(&bus->txq) >= TXHI) {
  2289. bus->txoff = ON;
  2290. brcmf_txflowcontrol(bus->sdiodev->dev, 0, ON);
  2291. }
  2292. #ifdef BCMDBG
  2293. if (pktq_plen(&bus->txq, prec) > qcount[prec])
  2294. qcount[prec] = pktq_plen(&bus->txq, prec);
  2295. #endif
  2296. /* Schedule DPC if needed to send queued packet(s) */
  2297. if (!bus->dpc_sched) {
  2298. bus->dpc_sched = true;
  2299. if (bus->dpc_tsk)
  2300. complete(&bus->dpc_wait);
  2301. }
  2302. return ret;
  2303. }
  2304. static int
  2305. brcmf_sdbrcm_membytes(struct brcmf_sdio *bus, bool write, u32 address, u8 *data,
  2306. uint size)
  2307. {
  2308. int bcmerror = 0;
  2309. u32 sdaddr;
  2310. uint dsize;
  2311. /* Determine initial transfer parameters */
  2312. sdaddr = address & SBSDIO_SB_OFT_ADDR_MASK;
  2313. if ((sdaddr + size) & SBSDIO_SBWINDOW_MASK)
  2314. dsize = (SBSDIO_SB_OFT_ADDR_LIMIT - sdaddr);
  2315. else
  2316. dsize = size;
  2317. /* Set the backplane window to include the start address */
  2318. bcmerror = brcmf_sdcard_set_sbaddr_window(bus->sdiodev, address);
  2319. if (bcmerror) {
  2320. brcmf_dbg(ERROR, "window change failed\n");
  2321. goto xfer_done;
  2322. }
  2323. /* Do the transfer(s) */
  2324. while (size) {
  2325. brcmf_dbg(INFO, "%s %d bytes at offset 0x%08x in window 0x%08x\n",
  2326. write ? "write" : "read", dsize,
  2327. sdaddr, address & SBSDIO_SBWINDOW_MASK);
  2328. bcmerror = brcmf_sdcard_rwdata(bus->sdiodev, write,
  2329. sdaddr, data, dsize);
  2330. if (bcmerror) {
  2331. brcmf_dbg(ERROR, "membytes transfer failed\n");
  2332. break;
  2333. }
  2334. /* Adjust for next transfer (if any) */
  2335. size -= dsize;
  2336. if (size) {
  2337. data += dsize;
  2338. address += dsize;
  2339. bcmerror = brcmf_sdcard_set_sbaddr_window(bus->sdiodev,
  2340. address);
  2341. if (bcmerror) {
  2342. brcmf_dbg(ERROR, "window change failed\n");
  2343. break;
  2344. }
  2345. sdaddr = 0;
  2346. dsize = min_t(uint, SBSDIO_SB_OFT_ADDR_LIMIT, size);
  2347. }
  2348. }
  2349. xfer_done:
  2350. /* Return the window to backplane enumeration space for core access */
  2351. if (brcmf_sdcard_set_sbaddr_window(bus->sdiodev, bus->sdiodev->sbwad))
  2352. brcmf_dbg(ERROR, "FAILED to set window back to 0x%x\n",
  2353. bus->sdiodev->sbwad);
  2354. return bcmerror;
  2355. }
  2356. #ifdef BCMDBG
  2357. #define CONSOLE_LINE_MAX 192
  2358. static int brcmf_sdbrcm_readconsole(struct brcmf_sdio *bus)
  2359. {
  2360. struct brcmf_console *c = &bus->console;
  2361. u8 line[CONSOLE_LINE_MAX], ch;
  2362. u32 n, idx, addr;
  2363. int rv;
  2364. /* Don't do anything until FWREADY updates console address */
  2365. if (bus->console_addr == 0)
  2366. return 0;
  2367. /* Read console log struct */
  2368. addr = bus->console_addr + offsetof(struct rte_console, log_le);
  2369. rv = brcmf_sdbrcm_membytes(bus, false, addr, (u8 *)&c->log_le,
  2370. sizeof(c->log_le));
  2371. if (rv < 0)
  2372. return rv;
  2373. /* Allocate console buffer (one time only) */
  2374. if (c->buf == NULL) {
  2375. c->bufsize = le32_to_cpu(c->log_le.buf_size);
  2376. c->buf = kmalloc(c->bufsize, GFP_ATOMIC);
  2377. if (c->buf == NULL)
  2378. return -ENOMEM;
  2379. }
  2380. idx = le32_to_cpu(c->log_le.idx);
  2381. /* Protect against corrupt value */
  2382. if (idx > c->bufsize)
  2383. return -EBADE;
  2384. /* Skip reading the console buffer if the index pointer
  2385. has not moved */
  2386. if (idx == c->last)
  2387. return 0;
  2388. /* Read the console buffer */
  2389. addr = le32_to_cpu(c->log_le.buf);
  2390. rv = brcmf_sdbrcm_membytes(bus, false, addr, c->buf, c->bufsize);
  2391. if (rv < 0)
  2392. return rv;
  2393. while (c->last != idx) {
  2394. for (n = 0; n < CONSOLE_LINE_MAX - 2; n++) {
  2395. if (c->last == idx) {
  2396. /* This would output a partial line.
  2397. * Instead, back up
  2398. * the buffer pointer and output this
  2399. * line next time around.
  2400. */
  2401. if (c->last >= n)
  2402. c->last -= n;
  2403. else
  2404. c->last = c->bufsize - n;
  2405. goto break2;
  2406. }
  2407. ch = c->buf[c->last];
  2408. c->last = (c->last + 1) % c->bufsize;
  2409. if (ch == '\n')
  2410. break;
  2411. line[n] = ch;
  2412. }
  2413. if (n > 0) {
  2414. if (line[n - 1] == '\r')
  2415. n--;
  2416. line[n] = 0;
  2417. printk(KERN_DEBUG "CONSOLE: %s\n", line);
  2418. }
  2419. }
  2420. break2:
  2421. return 0;
  2422. }
  2423. #endif /* BCMDBG */
  2424. static int brcmf_tx_frame(struct brcmf_sdio *bus, u8 *frame, u16 len)
  2425. {
  2426. int i;
  2427. int ret;
  2428. bus->ctrl_frame_stat = false;
  2429. ret = brcmf_sdcard_send_buf(bus->sdiodev, bus->sdiodev->sbwad,
  2430. SDIO_FUNC_2, F2SYNC, frame, len);
  2431. if (ret < 0) {
  2432. /* On failure, abort the command and terminate the frame */
  2433. brcmf_dbg(INFO, "sdio error %d, abort command and terminate frame\n",
  2434. ret);
  2435. bus->tx_sderrs++;
  2436. brcmf_sdcard_abort(bus->sdiodev, SDIO_FUNC_2);
  2437. brcmf_sdcard_cfg_write(bus->sdiodev, SDIO_FUNC_1,
  2438. SBSDIO_FUNC1_FRAMECTRL,
  2439. SFC_WF_TERM, NULL);
  2440. bus->f1regdata++;
  2441. for (i = 0; i < 3; i++) {
  2442. u8 hi, lo;
  2443. hi = brcmf_sdcard_cfg_read(bus->sdiodev, SDIO_FUNC_1,
  2444. SBSDIO_FUNC1_WFRAMEBCHI,
  2445. NULL);
  2446. lo = brcmf_sdcard_cfg_read(bus->sdiodev, SDIO_FUNC_1,
  2447. SBSDIO_FUNC1_WFRAMEBCLO,
  2448. NULL);
  2449. bus->f1regdata += 2;
  2450. if (hi == 0 && lo == 0)
  2451. break;
  2452. }
  2453. return ret;
  2454. }
  2455. bus->tx_seq = (bus->tx_seq + 1) % SDPCM_SEQUENCE_WRAP;
  2456. return ret;
  2457. }
  2458. int
  2459. brcmf_sdbrcm_bus_txctl(struct device *dev, unsigned char *msg, uint msglen)
  2460. {
  2461. u8 *frame;
  2462. u16 len;
  2463. u32 swheader;
  2464. uint retries = 0;
  2465. u8 doff = 0;
  2466. int ret = -1;
  2467. struct brcmf_bus *bus_if = dev_get_drvdata(dev);
  2468. struct brcmf_sdio_dev *sdiodev = bus_if->bus_priv;
  2469. struct brcmf_sdio *bus = sdiodev->bus;
  2470. brcmf_dbg(TRACE, "Enter\n");
  2471. /* Back the pointer to make a room for bus header */
  2472. frame = msg - SDPCM_HDRLEN;
  2473. len = (msglen += SDPCM_HDRLEN);
  2474. /* Add alignment padding (optional for ctl frames) */
  2475. doff = ((unsigned long)frame % BRCMF_SDALIGN);
  2476. if (doff) {
  2477. frame -= doff;
  2478. len += doff;
  2479. msglen += doff;
  2480. memset(frame, 0, doff + SDPCM_HDRLEN);
  2481. }
  2482. /* precondition: doff < BRCMF_SDALIGN */
  2483. doff += SDPCM_HDRLEN;
  2484. /* Round send length to next SDIO block */
  2485. if (bus->roundup && bus->blocksize && (len > bus->blocksize)) {
  2486. u16 pad = bus->blocksize - (len % bus->blocksize);
  2487. if ((pad <= bus->roundup) && (pad < bus->blocksize))
  2488. len += pad;
  2489. } else if (len % BRCMF_SDALIGN) {
  2490. len += BRCMF_SDALIGN - (len % BRCMF_SDALIGN);
  2491. }
  2492. /* Satisfy length-alignment requirements */
  2493. if (len & (ALIGNMENT - 1))
  2494. len = roundup(len, ALIGNMENT);
  2495. /* precondition: IS_ALIGNED((unsigned long)frame, 2) */
  2496. /* Need to lock here to protect txseq and SDIO tx calls */
  2497. down(&bus->sdsem);
  2498. bus_wake(bus);
  2499. /* Make sure backplane clock is on */
  2500. brcmf_sdbrcm_clkctl(bus, CLK_AVAIL, false);
  2501. /* Hardware tag: 2 byte len followed by 2 byte ~len check (all LE) */
  2502. *(__le16 *) frame = cpu_to_le16((u16) msglen);
  2503. *(((__le16 *) frame) + 1) = cpu_to_le16(~msglen);
  2504. /* Software tag: channel, sequence number, data offset */
  2505. swheader =
  2506. ((SDPCM_CONTROL_CHANNEL << SDPCM_CHANNEL_SHIFT) &
  2507. SDPCM_CHANNEL_MASK)
  2508. | bus->tx_seq | ((doff << SDPCM_DOFFSET_SHIFT) &
  2509. SDPCM_DOFFSET_MASK);
  2510. put_unaligned_le32(swheader, frame + SDPCM_FRAMETAG_LEN);
  2511. put_unaligned_le32(0, frame + SDPCM_FRAMETAG_LEN + sizeof(swheader));
  2512. if (!data_ok(bus)) {
  2513. brcmf_dbg(INFO, "No bus credit bus->tx_max %d, bus->tx_seq %d\n",
  2514. bus->tx_max, bus->tx_seq);
  2515. bus->ctrl_frame_stat = true;
  2516. /* Send from dpc */
  2517. bus->ctrl_frame_buf = frame;
  2518. bus->ctrl_frame_len = len;
  2519. brcmf_sdbrcm_wait_for_event(bus, &bus->ctrl_frame_stat);
  2520. if (bus->ctrl_frame_stat == false) {
  2521. brcmf_dbg(INFO, "ctrl_frame_stat == false\n");
  2522. ret = 0;
  2523. } else {
  2524. brcmf_dbg(INFO, "ctrl_frame_stat == true\n");
  2525. ret = -1;
  2526. }
  2527. }
  2528. if (ret == -1) {
  2529. #ifdef BCMDBG
  2530. if (BRCMF_BYTES_ON() && BRCMF_CTL_ON()) {
  2531. printk(KERN_DEBUG "Tx Frame:\n");
  2532. print_hex_dump_bytes("", DUMP_PREFIX_OFFSET,
  2533. frame, len);
  2534. } else if (BRCMF_HDRS_ON()) {
  2535. printk(KERN_DEBUG "TxHdr:\n");
  2536. print_hex_dump_bytes("", DUMP_PREFIX_OFFSET,
  2537. frame, min_t(u16, len, 16));
  2538. }
  2539. #endif
  2540. do {
  2541. ret = brcmf_tx_frame(bus, frame, len);
  2542. } while (ret < 0 && retries++ < TXRETRIES);
  2543. }
  2544. if ((bus->idletime == BRCMF_IDLE_IMMEDIATE) && !bus->dpc_sched) {
  2545. bus->activity = false;
  2546. brcmf_sdbrcm_clkctl(bus, CLK_NONE, true);
  2547. }
  2548. up(&bus->sdsem);
  2549. if (ret)
  2550. bus->tx_ctlerrs++;
  2551. else
  2552. bus->tx_ctlpkts++;
  2553. return ret ? -EIO : 0;
  2554. }
  2555. int
  2556. brcmf_sdbrcm_bus_rxctl(struct device *dev, unsigned char *msg, uint msglen)
  2557. {
  2558. int timeleft;
  2559. uint rxlen = 0;
  2560. bool pending;
  2561. struct brcmf_bus *bus_if = dev_get_drvdata(dev);
  2562. struct brcmf_sdio_dev *sdiodev = bus_if->bus_priv;
  2563. struct brcmf_sdio *bus = sdiodev->bus;
  2564. brcmf_dbg(TRACE, "Enter\n");
  2565. /* Wait until control frame is available */
  2566. timeleft = brcmf_sdbrcm_dcmd_resp_wait(bus, &bus->rxlen, &pending);
  2567. down(&bus->sdsem);
  2568. rxlen = bus->rxlen;
  2569. memcpy(msg, bus->rxctl, min(msglen, rxlen));
  2570. bus->rxlen = 0;
  2571. up(&bus->sdsem);
  2572. if (rxlen) {
  2573. brcmf_dbg(CTL, "resumed on rxctl frame, got %d expected %d\n",
  2574. rxlen, msglen);
  2575. } else if (timeleft == 0) {
  2576. brcmf_dbg(ERROR, "resumed on timeout\n");
  2577. } else if (pending == true) {
  2578. brcmf_dbg(CTL, "cancelled\n");
  2579. return -ERESTARTSYS;
  2580. } else {
  2581. brcmf_dbg(CTL, "resumed for unknown reason?\n");
  2582. }
  2583. if (rxlen)
  2584. bus->rx_ctlpkts++;
  2585. else
  2586. bus->rx_ctlerrs++;
  2587. return rxlen ? (int)rxlen : -ETIMEDOUT;
  2588. }
  2589. static int brcmf_sdbrcm_downloadvars(struct brcmf_sdio *bus, void *arg, int len)
  2590. {
  2591. int bcmerror = 0;
  2592. brcmf_dbg(TRACE, "Enter\n");
  2593. /* Basic sanity checks */
  2594. if (bus->sdiodev->bus_if->drvr_up) {
  2595. bcmerror = -EISCONN;
  2596. goto err;
  2597. }
  2598. if (!len) {
  2599. bcmerror = -EOVERFLOW;
  2600. goto err;
  2601. }
  2602. /* Free the old ones and replace with passed variables */
  2603. kfree(bus->vars);
  2604. bus->vars = kmalloc(len, GFP_ATOMIC);
  2605. bus->varsz = bus->vars ? len : 0;
  2606. if (bus->vars == NULL) {
  2607. bcmerror = -ENOMEM;
  2608. goto err;
  2609. }
  2610. /* Copy the passed variables, which should include the
  2611. terminating double-null */
  2612. memcpy(bus->vars, arg, bus->varsz);
  2613. err:
  2614. return bcmerror;
  2615. }
  2616. static int brcmf_sdbrcm_write_vars(struct brcmf_sdio *bus)
  2617. {
  2618. int bcmerror = 0;
  2619. u32 varsize;
  2620. u32 varaddr;
  2621. u8 *vbuffer;
  2622. u32 varsizew;
  2623. __le32 varsizew_le;
  2624. #ifdef BCMDBG
  2625. char *nvram_ularray;
  2626. #endif /* BCMDBG */
  2627. /* Even if there are no vars are to be written, we still
  2628. need to set the ramsize. */
  2629. varsize = bus->varsz ? roundup(bus->varsz, 4) : 0;
  2630. varaddr = (bus->ramsize - 4) - varsize;
  2631. if (bus->vars) {
  2632. vbuffer = kzalloc(varsize, GFP_ATOMIC);
  2633. if (!vbuffer)
  2634. return -ENOMEM;
  2635. memcpy(vbuffer, bus->vars, bus->varsz);
  2636. /* Write the vars list */
  2637. bcmerror =
  2638. brcmf_sdbrcm_membytes(bus, true, varaddr, vbuffer, varsize);
  2639. #ifdef BCMDBG
  2640. /* Verify NVRAM bytes */
  2641. brcmf_dbg(INFO, "Compare NVRAM dl & ul; varsize=%d\n", varsize);
  2642. nvram_ularray = kmalloc(varsize, GFP_ATOMIC);
  2643. if (!nvram_ularray)
  2644. return -ENOMEM;
  2645. /* Upload image to verify downloaded contents. */
  2646. memset(nvram_ularray, 0xaa, varsize);
  2647. /* Read the vars list to temp buffer for comparison */
  2648. bcmerror =
  2649. brcmf_sdbrcm_membytes(bus, false, varaddr, nvram_ularray,
  2650. varsize);
  2651. if (bcmerror) {
  2652. brcmf_dbg(ERROR, "error %d on reading %d nvram bytes at 0x%08x\n",
  2653. bcmerror, varsize, varaddr);
  2654. }
  2655. /* Compare the org NVRAM with the one read from RAM */
  2656. if (memcmp(vbuffer, nvram_ularray, varsize))
  2657. brcmf_dbg(ERROR, "Downloaded NVRAM image is corrupted\n");
  2658. else
  2659. brcmf_dbg(ERROR, "Download/Upload/Compare of NVRAM ok\n");
  2660. kfree(nvram_ularray);
  2661. #endif /* BCMDBG */
  2662. kfree(vbuffer);
  2663. }
  2664. /* adjust to the user specified RAM */
  2665. brcmf_dbg(INFO, "Physical memory size: %d\n", bus->ramsize);
  2666. brcmf_dbg(INFO, "Vars are at %d, orig varsize is %d\n",
  2667. varaddr, varsize);
  2668. varsize = ((bus->ramsize - 4) - varaddr);
  2669. /*
  2670. * Determine the length token:
  2671. * Varsize, converted to words, in lower 16-bits, checksum
  2672. * in upper 16-bits.
  2673. */
  2674. if (bcmerror) {
  2675. varsizew = 0;
  2676. varsizew_le = cpu_to_le32(0);
  2677. } else {
  2678. varsizew = varsize / 4;
  2679. varsizew = (~varsizew << 16) | (varsizew & 0x0000FFFF);
  2680. varsizew_le = cpu_to_le32(varsizew);
  2681. }
  2682. brcmf_dbg(INFO, "New varsize is %d, length token=0x%08x\n",
  2683. varsize, varsizew);
  2684. /* Write the length token to the last word */
  2685. bcmerror = brcmf_sdbrcm_membytes(bus, true, (bus->ramsize - 4),
  2686. (u8 *)&varsizew_le, 4);
  2687. return bcmerror;
  2688. }
  2689. static int brcmf_sdbrcm_download_state(struct brcmf_sdio *bus, bool enter)
  2690. {
  2691. uint retries;
  2692. int bcmerror = 0;
  2693. struct chip_info *ci = bus->ci;
  2694. /* To enter download state, disable ARM and reset SOCRAM.
  2695. * To exit download state, simply reset ARM (default is RAM boot).
  2696. */
  2697. if (enter) {
  2698. bus->alp_only = true;
  2699. ci->coredisable(bus->sdiodev, ci, BCMA_CORE_ARM_CM3);
  2700. ci->resetcore(bus->sdiodev, ci, BCMA_CORE_INTERNAL_MEM);
  2701. /* Clear the top bit of memory */
  2702. if (bus->ramsize) {
  2703. u32 zeros = 0;
  2704. brcmf_sdbrcm_membytes(bus, true, bus->ramsize - 4,
  2705. (u8 *)&zeros, 4);
  2706. }
  2707. } else {
  2708. if (!ci->iscoreup(bus->sdiodev, ci, BCMA_CORE_INTERNAL_MEM)) {
  2709. brcmf_dbg(ERROR, "SOCRAM core is down after reset?\n");
  2710. bcmerror = -EBADE;
  2711. goto fail;
  2712. }
  2713. bcmerror = brcmf_sdbrcm_write_vars(bus);
  2714. if (bcmerror) {
  2715. brcmf_dbg(ERROR, "no vars written to RAM\n");
  2716. bcmerror = 0;
  2717. }
  2718. w_sdreg32(bus, 0xFFFFFFFF,
  2719. offsetof(struct sdpcmd_regs, intstatus), &retries);
  2720. ci->resetcore(bus->sdiodev, ci, BCMA_CORE_ARM_CM3);
  2721. /* Allow HT Clock now that the ARM is running. */
  2722. bus->alp_only = false;
  2723. bus->sdiodev->bus_if->state = BRCMF_BUS_LOAD;
  2724. }
  2725. fail:
  2726. return bcmerror;
  2727. }
  2728. static int brcmf_sdbrcm_get_image(char *buf, int len, struct brcmf_sdio *bus)
  2729. {
  2730. if (bus->firmware->size < bus->fw_ptr + len)
  2731. len = bus->firmware->size - bus->fw_ptr;
  2732. memcpy(buf, &bus->firmware->data[bus->fw_ptr], len);
  2733. bus->fw_ptr += len;
  2734. return len;
  2735. }
  2736. static int brcmf_sdbrcm_download_code_file(struct brcmf_sdio *bus)
  2737. {
  2738. int offset = 0;
  2739. uint len;
  2740. u8 *memblock = NULL, *memptr;
  2741. int ret;
  2742. brcmf_dbg(INFO, "Enter\n");
  2743. ret = request_firmware(&bus->firmware, BRCMFMAC_FW_NAME,
  2744. &bus->sdiodev->func[2]->dev);
  2745. if (ret) {
  2746. brcmf_dbg(ERROR, "Fail to request firmware %d\n", ret);
  2747. return ret;
  2748. }
  2749. bus->fw_ptr = 0;
  2750. memptr = memblock = kmalloc(MEMBLOCK + BRCMF_SDALIGN, GFP_ATOMIC);
  2751. if (memblock == NULL) {
  2752. ret = -ENOMEM;
  2753. goto err;
  2754. }
  2755. if ((u32)(unsigned long)memblock % BRCMF_SDALIGN)
  2756. memptr += (BRCMF_SDALIGN -
  2757. ((u32)(unsigned long)memblock % BRCMF_SDALIGN));
  2758. /* Download image */
  2759. while ((len =
  2760. brcmf_sdbrcm_get_image((char *)memptr, MEMBLOCK, bus))) {
  2761. ret = brcmf_sdbrcm_membytes(bus, true, offset, memptr, len);
  2762. if (ret) {
  2763. brcmf_dbg(ERROR, "error %d on writing %d membytes at 0x%08x\n",
  2764. ret, MEMBLOCK, offset);
  2765. goto err;
  2766. }
  2767. offset += MEMBLOCK;
  2768. }
  2769. err:
  2770. kfree(memblock);
  2771. release_firmware(bus->firmware);
  2772. bus->fw_ptr = 0;
  2773. return ret;
  2774. }
  2775. /*
  2776. * ProcessVars:Takes a buffer of "<var>=<value>\n" lines read from a file
  2777. * and ending in a NUL.
  2778. * Removes carriage returns, empty lines, comment lines, and converts
  2779. * newlines to NULs.
  2780. * Shortens buffer as needed and pads with NULs. End of buffer is marked
  2781. * by two NULs.
  2782. */
  2783. static uint brcmf_process_nvram_vars(char *varbuf, uint len)
  2784. {
  2785. char *dp;
  2786. bool findNewline;
  2787. int column;
  2788. uint buf_len, n;
  2789. dp = varbuf;
  2790. findNewline = false;
  2791. column = 0;
  2792. for (n = 0; n < len; n++) {
  2793. if (varbuf[n] == 0)
  2794. break;
  2795. if (varbuf[n] == '\r')
  2796. continue;
  2797. if (findNewline && varbuf[n] != '\n')
  2798. continue;
  2799. findNewline = false;
  2800. if (varbuf[n] == '#') {
  2801. findNewline = true;
  2802. continue;
  2803. }
  2804. if (varbuf[n] == '\n') {
  2805. if (column == 0)
  2806. continue;
  2807. *dp++ = 0;
  2808. column = 0;
  2809. continue;
  2810. }
  2811. *dp++ = varbuf[n];
  2812. column++;
  2813. }
  2814. buf_len = dp - varbuf;
  2815. while (dp < varbuf + n)
  2816. *dp++ = 0;
  2817. return buf_len;
  2818. }
  2819. static int brcmf_sdbrcm_download_nvram(struct brcmf_sdio *bus)
  2820. {
  2821. uint len;
  2822. char *memblock = NULL;
  2823. char *bufp;
  2824. int ret;
  2825. ret = request_firmware(&bus->firmware, BRCMFMAC_NV_NAME,
  2826. &bus->sdiodev->func[2]->dev);
  2827. if (ret) {
  2828. brcmf_dbg(ERROR, "Fail to request nvram %d\n", ret);
  2829. return ret;
  2830. }
  2831. bus->fw_ptr = 0;
  2832. memblock = kmalloc(MEMBLOCK, GFP_ATOMIC);
  2833. if (memblock == NULL) {
  2834. ret = -ENOMEM;
  2835. goto err;
  2836. }
  2837. len = brcmf_sdbrcm_get_image(memblock, MEMBLOCK, bus);
  2838. if (len > 0 && len < MEMBLOCK) {
  2839. bufp = (char *)memblock;
  2840. bufp[len] = 0;
  2841. len = brcmf_process_nvram_vars(bufp, len);
  2842. bufp += len;
  2843. *bufp++ = 0;
  2844. if (len)
  2845. ret = brcmf_sdbrcm_downloadvars(bus, memblock, len + 1);
  2846. if (ret)
  2847. brcmf_dbg(ERROR, "error downloading vars: %d\n", ret);
  2848. } else {
  2849. brcmf_dbg(ERROR, "error reading nvram file: %d\n", len);
  2850. ret = -EIO;
  2851. }
  2852. err:
  2853. kfree(memblock);
  2854. release_firmware(bus->firmware);
  2855. bus->fw_ptr = 0;
  2856. return ret;
  2857. }
  2858. static int _brcmf_sdbrcm_download_firmware(struct brcmf_sdio *bus)
  2859. {
  2860. int bcmerror = -1;
  2861. /* Keep arm in reset */
  2862. if (brcmf_sdbrcm_download_state(bus, true)) {
  2863. brcmf_dbg(ERROR, "error placing ARM core in reset\n");
  2864. goto err;
  2865. }
  2866. /* External image takes precedence if specified */
  2867. if (brcmf_sdbrcm_download_code_file(bus)) {
  2868. brcmf_dbg(ERROR, "dongle image file download failed\n");
  2869. goto err;
  2870. }
  2871. /* External nvram takes precedence if specified */
  2872. if (brcmf_sdbrcm_download_nvram(bus))
  2873. brcmf_dbg(ERROR, "dongle nvram file download failed\n");
  2874. /* Take arm out of reset */
  2875. if (brcmf_sdbrcm_download_state(bus, false)) {
  2876. brcmf_dbg(ERROR, "error getting out of ARM core reset\n");
  2877. goto err;
  2878. }
  2879. bcmerror = 0;
  2880. err:
  2881. return bcmerror;
  2882. }
  2883. static bool
  2884. brcmf_sdbrcm_download_firmware(struct brcmf_sdio *bus)
  2885. {
  2886. bool ret;
  2887. /* Download the firmware */
  2888. brcmf_sdbrcm_clkctl(bus, CLK_AVAIL, false);
  2889. ret = _brcmf_sdbrcm_download_firmware(bus) == 0;
  2890. brcmf_sdbrcm_clkctl(bus, CLK_SDONLY, false);
  2891. return ret;
  2892. }
  2893. static int brcmf_sdbrcm_bus_init(struct device *dev)
  2894. {
  2895. struct brcmf_bus *bus_if = dev_get_drvdata(dev);
  2896. struct brcmf_sdio_dev *sdiodev = bus_if->bus_priv;
  2897. struct brcmf_sdio *bus = sdiodev->bus;
  2898. unsigned long timeout;
  2899. uint retries = 0;
  2900. u8 ready, enable;
  2901. int err, ret = 0;
  2902. u8 saveclk;
  2903. brcmf_dbg(TRACE, "Enter\n");
  2904. /* try to download image and nvram to the dongle */
  2905. if (bus_if->state == BRCMF_BUS_DOWN) {
  2906. if (!(brcmf_sdbrcm_download_firmware(bus)))
  2907. return -1;
  2908. }
  2909. if (!bus->sdiodev->bus_if->drvr)
  2910. return 0;
  2911. /* Start the watchdog timer */
  2912. bus->tickcnt = 0;
  2913. brcmf_sdbrcm_wd_timer(bus, BRCMF_WD_POLL_MS);
  2914. down(&bus->sdsem);
  2915. /* Make sure backplane clock is on, needed to generate F2 interrupt */
  2916. brcmf_sdbrcm_clkctl(bus, CLK_AVAIL, false);
  2917. if (bus->clkstate != CLK_AVAIL)
  2918. goto exit;
  2919. /* Force clocks on backplane to be sure F2 interrupt propagates */
  2920. saveclk =
  2921. brcmf_sdcard_cfg_read(bus->sdiodev, SDIO_FUNC_1,
  2922. SBSDIO_FUNC1_CHIPCLKCSR, &err);
  2923. if (!err) {
  2924. brcmf_sdcard_cfg_write(bus->sdiodev, SDIO_FUNC_1,
  2925. SBSDIO_FUNC1_CHIPCLKCSR,
  2926. (saveclk | SBSDIO_FORCE_HT), &err);
  2927. }
  2928. if (err) {
  2929. brcmf_dbg(ERROR, "Failed to force clock for F2: err %d\n", err);
  2930. goto exit;
  2931. }
  2932. /* Enable function 2 (frame transfers) */
  2933. w_sdreg32(bus, SDPCM_PROT_VERSION << SMB_DATA_VERSION_SHIFT,
  2934. offsetof(struct sdpcmd_regs, tosbmailboxdata), &retries);
  2935. enable = (SDIO_FUNC_ENABLE_1 | SDIO_FUNC_ENABLE_2);
  2936. brcmf_sdcard_cfg_write(bus->sdiodev, SDIO_FUNC_0, SDIO_CCCR_IOEx,
  2937. enable, NULL);
  2938. timeout = jiffies + msecs_to_jiffies(BRCMF_WAIT_F2RDY);
  2939. ready = 0;
  2940. while (enable != ready) {
  2941. ready = brcmf_sdcard_cfg_read(bus->sdiodev, SDIO_FUNC_0,
  2942. SDIO_CCCR_IORx, NULL);
  2943. if (time_after(jiffies, timeout))
  2944. break;
  2945. else if (time_after(jiffies, timeout - BRCMF_WAIT_F2RDY + 50))
  2946. /* prevent busy waiting if it takes too long */
  2947. msleep_interruptible(20);
  2948. }
  2949. brcmf_dbg(INFO, "enable 0x%02x, ready 0x%02x\n", enable, ready);
  2950. /* If F2 successfully enabled, set core and enable interrupts */
  2951. if (ready == enable) {
  2952. /* Set up the interrupt mask and enable interrupts */
  2953. bus->hostintmask = HOSTINTMASK;
  2954. w_sdreg32(bus, bus->hostintmask,
  2955. offsetof(struct sdpcmd_regs, hostintmask), &retries);
  2956. brcmf_sdcard_cfg_write(bus->sdiodev, SDIO_FUNC_1,
  2957. SBSDIO_WATERMARK, 8, &err);
  2958. /* Set bus state according to enable result */
  2959. bus_if->state = BRCMF_BUS_DATA;
  2960. }
  2961. else {
  2962. /* Disable F2 again */
  2963. enable = SDIO_FUNC_ENABLE_1;
  2964. brcmf_sdcard_cfg_write(bus->sdiodev, SDIO_FUNC_0,
  2965. SDIO_CCCR_IOEx, enable, NULL);
  2966. }
  2967. /* Restore previous clock setting */
  2968. brcmf_sdcard_cfg_write(bus->sdiodev, SDIO_FUNC_1,
  2969. SBSDIO_FUNC1_CHIPCLKCSR, saveclk, &err);
  2970. /* If we didn't come up, turn off backplane clock */
  2971. if (bus_if->state != BRCMF_BUS_DATA)
  2972. brcmf_sdbrcm_clkctl(bus, CLK_NONE, false);
  2973. exit:
  2974. up(&bus->sdsem);
  2975. return ret;
  2976. }
  2977. void brcmf_sdbrcm_isr(void *arg)
  2978. {
  2979. struct brcmf_sdio *bus = (struct brcmf_sdio *) arg;
  2980. brcmf_dbg(TRACE, "Enter\n");
  2981. if (!bus) {
  2982. brcmf_dbg(ERROR, "bus is null pointer, exiting\n");
  2983. return;
  2984. }
  2985. if (bus->sdiodev->bus_if->state == BRCMF_BUS_DOWN) {
  2986. brcmf_dbg(ERROR, "bus is down. we have nothing to do\n");
  2987. return;
  2988. }
  2989. /* Count the interrupt call */
  2990. bus->intrcount++;
  2991. bus->ipend = true;
  2992. /* Shouldn't get this interrupt if we're sleeping? */
  2993. if (bus->sleeping) {
  2994. brcmf_dbg(ERROR, "INTERRUPT WHILE SLEEPING??\n");
  2995. return;
  2996. }
  2997. /* Disable additional interrupts (is this needed now)? */
  2998. if (!bus->intr)
  2999. brcmf_dbg(ERROR, "isr w/o interrupt configured!\n");
  3000. bus->dpc_sched = true;
  3001. if (bus->dpc_tsk)
  3002. complete(&bus->dpc_wait);
  3003. }
  3004. static bool brcmf_sdbrcm_bus_watchdog(struct brcmf_sdio *bus)
  3005. {
  3006. #ifdef BCMDBG
  3007. struct brcmf_bus *bus_if = dev_get_drvdata(bus->sdiodev->dev);
  3008. #endif /* BCMDBG */
  3009. brcmf_dbg(TIMER, "Enter\n");
  3010. /* Ignore the timer if simulating bus down */
  3011. if (bus->sleeping)
  3012. return false;
  3013. down(&bus->sdsem);
  3014. /* Poll period: check device if appropriate. */
  3015. if (bus->poll && (++bus->polltick >= bus->pollrate)) {
  3016. u32 intstatus = 0;
  3017. /* Reset poll tick */
  3018. bus->polltick = 0;
  3019. /* Check device if no interrupts */
  3020. if (!bus->intr || (bus->intrcount == bus->lastintrs)) {
  3021. if (!bus->dpc_sched) {
  3022. u8 devpend;
  3023. devpend = brcmf_sdcard_cfg_read(bus->sdiodev,
  3024. SDIO_FUNC_0, SDIO_CCCR_INTx,
  3025. NULL);
  3026. intstatus =
  3027. devpend & (INTR_STATUS_FUNC1 |
  3028. INTR_STATUS_FUNC2);
  3029. }
  3030. /* If there is something, make like the ISR and
  3031. schedule the DPC */
  3032. if (intstatus) {
  3033. bus->pollcnt++;
  3034. bus->ipend = true;
  3035. bus->dpc_sched = true;
  3036. if (bus->dpc_tsk)
  3037. complete(&bus->dpc_wait);
  3038. }
  3039. }
  3040. /* Update interrupt tracking */
  3041. bus->lastintrs = bus->intrcount;
  3042. }
  3043. #ifdef BCMDBG
  3044. /* Poll for console output periodically */
  3045. if (bus_if->state == BRCMF_BUS_DATA &&
  3046. bus->console_interval != 0) {
  3047. bus->console.count += BRCMF_WD_POLL_MS;
  3048. if (bus->console.count >= bus->console_interval) {
  3049. bus->console.count -= bus->console_interval;
  3050. /* Make sure backplane clock is on */
  3051. brcmf_sdbrcm_clkctl(bus, CLK_AVAIL, false);
  3052. if (brcmf_sdbrcm_readconsole(bus) < 0)
  3053. /* stop on error */
  3054. bus->console_interval = 0;
  3055. }
  3056. }
  3057. #endif /* BCMDBG */
  3058. /* On idle timeout clear activity flag and/or turn off clock */
  3059. if ((bus->idletime > 0) && (bus->clkstate == CLK_AVAIL)) {
  3060. if (++bus->idlecount >= bus->idletime) {
  3061. bus->idlecount = 0;
  3062. if (bus->activity) {
  3063. bus->activity = false;
  3064. brcmf_sdbrcm_wd_timer(bus, BRCMF_WD_POLL_MS);
  3065. } else {
  3066. brcmf_sdbrcm_clkctl(bus, CLK_NONE, false);
  3067. }
  3068. }
  3069. }
  3070. up(&bus->sdsem);
  3071. return bus->ipend;
  3072. }
  3073. static bool brcmf_sdbrcm_chipmatch(u16 chipid)
  3074. {
  3075. if (chipid == BCM4329_CHIP_ID)
  3076. return true;
  3077. if (chipid == BCM4330_CHIP_ID)
  3078. return true;
  3079. return false;
  3080. }
  3081. static void brcmf_sdbrcm_release_malloc(struct brcmf_sdio *bus)
  3082. {
  3083. brcmf_dbg(TRACE, "Enter\n");
  3084. kfree(bus->rxbuf);
  3085. bus->rxctl = bus->rxbuf = NULL;
  3086. bus->rxlen = 0;
  3087. kfree(bus->databuf);
  3088. bus->databuf = NULL;
  3089. }
  3090. static bool brcmf_sdbrcm_probe_malloc(struct brcmf_sdio *bus)
  3091. {
  3092. brcmf_dbg(TRACE, "Enter\n");
  3093. if (bus->sdiodev->bus_if->maxctl) {
  3094. bus->rxblen =
  3095. roundup((bus->sdiodev->bus_if->maxctl + SDPCM_HDRLEN),
  3096. ALIGNMENT) + BRCMF_SDALIGN;
  3097. bus->rxbuf = kmalloc(bus->rxblen, GFP_ATOMIC);
  3098. if (!(bus->rxbuf))
  3099. goto fail;
  3100. }
  3101. /* Allocate buffer to receive glomed packet */
  3102. bus->databuf = kmalloc(MAX_DATA_BUF, GFP_ATOMIC);
  3103. if (!(bus->databuf)) {
  3104. /* release rxbuf which was already located as above */
  3105. if (!bus->rxblen)
  3106. kfree(bus->rxbuf);
  3107. goto fail;
  3108. }
  3109. /* Align the buffer */
  3110. if ((unsigned long)bus->databuf % BRCMF_SDALIGN)
  3111. bus->dataptr = bus->databuf + (BRCMF_SDALIGN -
  3112. ((unsigned long)bus->databuf % BRCMF_SDALIGN));
  3113. else
  3114. bus->dataptr = bus->databuf;
  3115. return true;
  3116. fail:
  3117. return false;
  3118. }
  3119. static bool
  3120. brcmf_sdbrcm_probe_attach(struct brcmf_sdio *bus, u32 regsva)
  3121. {
  3122. u8 clkctl = 0;
  3123. int err = 0;
  3124. int reg_addr;
  3125. u32 reg_val;
  3126. u8 idx;
  3127. bus->alp_only = true;
  3128. /* Return the window to backplane enumeration space for core access */
  3129. if (brcmf_sdcard_set_sbaddr_window(bus->sdiodev, SI_ENUM_BASE))
  3130. brcmf_dbg(ERROR, "FAILED to return to SI_ENUM_BASE\n");
  3131. #ifdef BCMDBG
  3132. printk(KERN_DEBUG "F1 signature read @0x18000000=0x%4x\n",
  3133. brcmf_sdcard_reg_read(bus->sdiodev, SI_ENUM_BASE, 4));
  3134. #endif /* BCMDBG */
  3135. /*
  3136. * Force PLL off until brcmf_sdio_chip_attach()
  3137. * programs PLL control regs
  3138. */
  3139. brcmf_sdcard_cfg_write(bus->sdiodev, SDIO_FUNC_1,
  3140. SBSDIO_FUNC1_CHIPCLKCSR,
  3141. BRCMF_INIT_CLKCTL1, &err);
  3142. if (!err)
  3143. clkctl =
  3144. brcmf_sdcard_cfg_read(bus->sdiodev, SDIO_FUNC_1,
  3145. SBSDIO_FUNC1_CHIPCLKCSR, &err);
  3146. if (err || ((clkctl & ~SBSDIO_AVBITS) != BRCMF_INIT_CLKCTL1)) {
  3147. brcmf_dbg(ERROR, "ChipClkCSR access: err %d wrote 0x%02x read 0x%02x\n",
  3148. err, BRCMF_INIT_CLKCTL1, clkctl);
  3149. goto fail;
  3150. }
  3151. if (brcmf_sdio_chip_attach(bus->sdiodev, &bus->ci, regsva)) {
  3152. brcmf_dbg(ERROR, "brcmf_sdio_chip_attach failed!\n");
  3153. goto fail;
  3154. }
  3155. if (!brcmf_sdbrcm_chipmatch((u16) bus->ci->chip)) {
  3156. brcmf_dbg(ERROR, "unsupported chip: 0x%04x\n", bus->ci->chip);
  3157. goto fail;
  3158. }
  3159. brcmf_sdio_chip_drivestrengthinit(bus->sdiodev, bus->ci,
  3160. SDIO_DRIVE_STRENGTH);
  3161. /* Get info on the SOCRAM cores... */
  3162. bus->ramsize = bus->ci->ramsize;
  3163. if (!(bus->ramsize)) {
  3164. brcmf_dbg(ERROR, "failed to find SOCRAM memory!\n");
  3165. goto fail;
  3166. }
  3167. /* Set core control so an SDIO reset does a backplane reset */
  3168. idx = brcmf_sdio_chip_getinfidx(bus->ci, BCMA_CORE_SDIO_DEV);
  3169. reg_addr = bus->ci->c_inf[idx].base +
  3170. offsetof(struct sdpcmd_regs, corecontrol);
  3171. reg_val = brcmf_sdcard_reg_read(bus->sdiodev, reg_addr, sizeof(u32));
  3172. brcmf_sdcard_reg_write(bus->sdiodev, reg_addr, sizeof(u32),
  3173. reg_val | CC_BPRESEN);
  3174. brcmu_pktq_init(&bus->txq, (PRIOMASK + 1), TXQLEN);
  3175. /* Locate an appropriately-aligned portion of hdrbuf */
  3176. bus->rxhdr = (u8 *) roundup((unsigned long)&bus->hdrbuf[0],
  3177. BRCMF_SDALIGN);
  3178. /* Set the poll and/or interrupt flags */
  3179. bus->intr = true;
  3180. bus->poll = false;
  3181. if (bus->poll)
  3182. bus->pollrate = 1;
  3183. return true;
  3184. fail:
  3185. return false;
  3186. }
  3187. static bool brcmf_sdbrcm_probe_init(struct brcmf_sdio *bus)
  3188. {
  3189. brcmf_dbg(TRACE, "Enter\n");
  3190. /* Disable F2 to clear any intermediate frame state on the dongle */
  3191. brcmf_sdcard_cfg_write(bus->sdiodev, SDIO_FUNC_0, SDIO_CCCR_IOEx,
  3192. SDIO_FUNC_ENABLE_1, NULL);
  3193. bus->sdiodev->bus_if->state = BRCMF_BUS_DOWN;
  3194. bus->sleeping = false;
  3195. bus->rxflow = false;
  3196. /* Done with backplane-dependent accesses, can drop clock... */
  3197. brcmf_sdcard_cfg_write(bus->sdiodev, SDIO_FUNC_1,
  3198. SBSDIO_FUNC1_CHIPCLKCSR, 0, NULL);
  3199. /* ...and initialize clock/power states */
  3200. bus->clkstate = CLK_SDONLY;
  3201. bus->idletime = BRCMF_IDLE_INTERVAL;
  3202. bus->idleclock = BRCMF_IDLE_ACTIVE;
  3203. /* Query the F2 block size, set roundup accordingly */
  3204. bus->blocksize = bus->sdiodev->func[2]->cur_blksize;
  3205. bus->roundup = min(max_roundup, bus->blocksize);
  3206. /* bus module does not support packet chaining */
  3207. bus->use_rxchain = false;
  3208. bus->sd_rxchain = false;
  3209. return true;
  3210. }
  3211. static int
  3212. brcmf_sdbrcm_watchdog_thread(void *data)
  3213. {
  3214. struct brcmf_sdio *bus = (struct brcmf_sdio *)data;
  3215. allow_signal(SIGTERM);
  3216. /* Run until signal received */
  3217. while (1) {
  3218. if (kthread_should_stop())
  3219. break;
  3220. if (!wait_for_completion_interruptible(&bus->watchdog_wait)) {
  3221. brcmf_sdbrcm_bus_watchdog(bus);
  3222. /* Count the tick for reference */
  3223. bus->tickcnt++;
  3224. } else
  3225. break;
  3226. }
  3227. return 0;
  3228. }
  3229. static void
  3230. brcmf_sdbrcm_watchdog(unsigned long data)
  3231. {
  3232. struct brcmf_sdio *bus = (struct brcmf_sdio *)data;
  3233. if (bus->watchdog_tsk) {
  3234. complete(&bus->watchdog_wait);
  3235. /* Reschedule the watchdog */
  3236. if (bus->wd_timer_valid)
  3237. mod_timer(&bus->timer,
  3238. jiffies + BRCMF_WD_POLL_MS * HZ / 1000);
  3239. }
  3240. }
  3241. static void brcmf_sdbrcm_release_dongle(struct brcmf_sdio *bus)
  3242. {
  3243. brcmf_dbg(TRACE, "Enter\n");
  3244. if (bus->ci) {
  3245. brcmf_sdbrcm_clkctl(bus, CLK_AVAIL, false);
  3246. brcmf_sdbrcm_clkctl(bus, CLK_NONE, false);
  3247. brcmf_sdio_chip_detach(&bus->ci);
  3248. if (bus->vars && bus->varsz)
  3249. kfree(bus->vars);
  3250. bus->vars = NULL;
  3251. }
  3252. brcmf_dbg(TRACE, "Disconnected\n");
  3253. }
  3254. /* Detach and free everything */
  3255. static void brcmf_sdbrcm_release(struct brcmf_sdio *bus)
  3256. {
  3257. brcmf_dbg(TRACE, "Enter\n");
  3258. if (bus) {
  3259. /* De-register interrupt handler */
  3260. brcmf_sdcard_intr_dereg(bus->sdiodev);
  3261. if (bus->sdiodev->bus_if->drvr) {
  3262. brcmf_detach(bus->sdiodev->dev);
  3263. brcmf_sdbrcm_release_dongle(bus);
  3264. }
  3265. brcmf_sdbrcm_release_malloc(bus);
  3266. kfree(bus);
  3267. }
  3268. brcmf_dbg(TRACE, "Disconnected\n");
  3269. }
  3270. void *brcmf_sdbrcm_probe(u32 regsva, struct brcmf_sdio_dev *sdiodev)
  3271. {
  3272. int ret;
  3273. struct brcmf_sdio *bus;
  3274. brcmf_dbg(TRACE, "Enter\n");
  3275. /* We make an assumption about address window mappings:
  3276. * regsva == SI_ENUM_BASE*/
  3277. /* Allocate private bus interface state */
  3278. bus = kzalloc(sizeof(struct brcmf_sdio), GFP_ATOMIC);
  3279. if (!bus)
  3280. goto fail;
  3281. bus->sdiodev = sdiodev;
  3282. sdiodev->bus = bus;
  3283. skb_queue_head_init(&bus->glom);
  3284. bus->txbound = BRCMF_TXBOUND;
  3285. bus->rxbound = BRCMF_RXBOUND;
  3286. bus->txminmax = BRCMF_TXMINMAX;
  3287. bus->tx_seq = SDPCM_SEQUENCE_WRAP - 1;
  3288. bus->usebufpool = false; /* Use bufpool if allocated,
  3289. else use locally malloced rxbuf */
  3290. /* attempt to attach to the dongle */
  3291. if (!(brcmf_sdbrcm_probe_attach(bus, regsva))) {
  3292. brcmf_dbg(ERROR, "brcmf_sdbrcm_probe_attach failed\n");
  3293. goto fail;
  3294. }
  3295. spin_lock_init(&bus->txqlock);
  3296. init_waitqueue_head(&bus->ctrl_wait);
  3297. init_waitqueue_head(&bus->dcmd_resp_wait);
  3298. /* Set up the watchdog timer */
  3299. init_timer(&bus->timer);
  3300. bus->timer.data = (unsigned long)bus;
  3301. bus->timer.function = brcmf_sdbrcm_watchdog;
  3302. /* Initialize thread based operation and lock */
  3303. sema_init(&bus->sdsem, 1);
  3304. /* Initialize watchdog thread */
  3305. init_completion(&bus->watchdog_wait);
  3306. bus->watchdog_tsk = kthread_run(brcmf_sdbrcm_watchdog_thread,
  3307. bus, "brcmf_watchdog");
  3308. if (IS_ERR(bus->watchdog_tsk)) {
  3309. printk(KERN_WARNING
  3310. "brcmf_watchdog thread failed to start\n");
  3311. bus->watchdog_tsk = NULL;
  3312. }
  3313. /* Initialize DPC thread */
  3314. init_completion(&bus->dpc_wait);
  3315. bus->dpc_tsk = kthread_run(brcmf_sdbrcm_dpc_thread,
  3316. bus, "brcmf_dpc");
  3317. if (IS_ERR(bus->dpc_tsk)) {
  3318. printk(KERN_WARNING
  3319. "brcmf_dpc thread failed to start\n");
  3320. bus->dpc_tsk = NULL;
  3321. }
  3322. /* Assign bus interface call back */
  3323. bus->sdiodev->bus_if->brcmf_bus_stop = brcmf_sdbrcm_bus_stop;
  3324. bus->sdiodev->bus_if->brcmf_bus_init = brcmf_sdbrcm_bus_init;
  3325. bus->sdiodev->bus_if->brcmf_bus_txdata = brcmf_sdbrcm_bus_txdata;
  3326. /* Attach to the brcmf/OS/network interface */
  3327. ret = brcmf_attach(SDPCM_RESERVE, bus->sdiodev->dev);
  3328. if (ret != 0) {
  3329. brcmf_dbg(ERROR, "brcmf_attach failed\n");
  3330. goto fail;
  3331. }
  3332. /* Allocate buffers */
  3333. if (!(brcmf_sdbrcm_probe_malloc(bus))) {
  3334. brcmf_dbg(ERROR, "brcmf_sdbrcm_probe_malloc failed\n");
  3335. goto fail;
  3336. }
  3337. if (!(brcmf_sdbrcm_probe_init(bus))) {
  3338. brcmf_dbg(ERROR, "brcmf_sdbrcm_probe_init failed\n");
  3339. goto fail;
  3340. }
  3341. /* Register interrupt callback, but mask it (not operational yet). */
  3342. brcmf_dbg(INTR, "disable SDIO interrupts (not interested yet)\n");
  3343. ret = brcmf_sdcard_intr_reg(bus->sdiodev);
  3344. if (ret != 0) {
  3345. brcmf_dbg(ERROR, "FAILED: sdcard_intr_reg returned %d\n", ret);
  3346. goto fail;
  3347. }
  3348. brcmf_dbg(INTR, "registered SDIO interrupt function ok\n");
  3349. brcmf_dbg(INFO, "completed!!\n");
  3350. /* if firmware path present try to download and bring up bus */
  3351. ret = brcmf_bus_start(bus->sdiodev->dev);
  3352. if (ret != 0) {
  3353. if (ret == -ENOLINK) {
  3354. brcmf_dbg(ERROR, "dongle is not responding\n");
  3355. goto fail;
  3356. }
  3357. }
  3358. /* add interface and open for business */
  3359. if (brcmf_add_if(bus->sdiodev->dev, 0, "wlan%d", NULL)) {
  3360. brcmf_dbg(ERROR, "Add primary net device interface failed!!\n");
  3361. goto fail;
  3362. }
  3363. return bus;
  3364. fail:
  3365. brcmf_sdbrcm_release(bus);
  3366. return NULL;
  3367. }
  3368. void brcmf_sdbrcm_disconnect(void *ptr)
  3369. {
  3370. struct brcmf_sdio *bus = (struct brcmf_sdio *)ptr;
  3371. brcmf_dbg(TRACE, "Enter\n");
  3372. if (bus)
  3373. brcmf_sdbrcm_release(bus);
  3374. brcmf_dbg(TRACE, "Disconnected\n");
  3375. }
  3376. void
  3377. brcmf_sdbrcm_wd_timer(struct brcmf_sdio *bus, uint wdtick)
  3378. {
  3379. /* Totally stop the timer */
  3380. if (!wdtick && bus->wd_timer_valid == true) {
  3381. del_timer_sync(&bus->timer);
  3382. bus->wd_timer_valid = false;
  3383. bus->save_ms = wdtick;
  3384. return;
  3385. }
  3386. /* don't start the wd until fw is loaded */
  3387. if (bus->sdiodev->bus_if->state == BRCMF_BUS_DOWN)
  3388. return;
  3389. if (wdtick) {
  3390. if (bus->save_ms != BRCMF_WD_POLL_MS) {
  3391. if (bus->wd_timer_valid == true)
  3392. /* Stop timer and restart at new value */
  3393. del_timer_sync(&bus->timer);
  3394. /* Create timer again when watchdog period is
  3395. dynamically changed or in the first instance
  3396. */
  3397. bus->timer.expires =
  3398. jiffies + BRCMF_WD_POLL_MS * HZ / 1000;
  3399. add_timer(&bus->timer);
  3400. } else {
  3401. /* Re arm the timer, at last watchdog period */
  3402. mod_timer(&bus->timer,
  3403. jiffies + BRCMF_WD_POLL_MS * HZ / 1000);
  3404. }
  3405. bus->wd_timer_valid = true;
  3406. bus->save_ms = wdtick;
  3407. }
  3408. }