pm-sh7372.c 5.5 KB

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  1. /*
  2. * sh7372 Power management support
  3. *
  4. * Copyright (C) 2011 Magnus Damm
  5. *
  6. * This file is subject to the terms and conditions of the GNU General Public
  7. * License. See the file "COPYING" in the main directory of this archive
  8. * for more details.
  9. */
  10. #include <linux/pm.h>
  11. #include <linux/suspend.h>
  12. #include <linux/cpuidle.h>
  13. #include <linux/module.h>
  14. #include <linux/list.h>
  15. #include <linux/err.h>
  16. #include <linux/slab.h>
  17. #include <linux/pm_runtime.h>
  18. #include <linux/platform_device.h>
  19. #include <linux/delay.h>
  20. #include <asm/system.h>
  21. #include <asm/io.h>
  22. #include <asm/tlbflush.h>
  23. #include <mach/common.h>
  24. #include <mach/sh7372.h>
  25. #define SMFRAM 0xe6a70000
  26. #define SYSTBCR 0xe6150024
  27. #define SBAR 0xe6180020
  28. #define APARMBAREA 0xe6f10020
  29. #define SPDCR 0xe6180008
  30. #define SWUCR 0xe6180014
  31. #define PSTR 0xe6180080
  32. #define PSTR_RETRIES 100
  33. #define PSTR_DELAY_US 10
  34. #ifdef CONFIG_PM
  35. static int pd_power_down(struct generic_pm_domain *genpd)
  36. {
  37. struct sh7372_pm_domain *sh7372_pd = to_sh7372_pd(genpd);
  38. unsigned int mask = 1 << sh7372_pd->bit_shift;
  39. if (__raw_readl(PSTR) & mask) {
  40. unsigned int retry_count;
  41. __raw_writel(mask, SPDCR);
  42. for (retry_count = PSTR_RETRIES; retry_count; retry_count--) {
  43. if (!(__raw_readl(SPDCR) & mask))
  44. break;
  45. cpu_relax();
  46. }
  47. }
  48. pr_debug("sh7372 power domain down 0x%08x -> PSTR = 0x%08x\n",
  49. mask, __raw_readl(PSTR));
  50. return 0;
  51. }
  52. static int pd_power_up(struct generic_pm_domain *genpd)
  53. {
  54. struct sh7372_pm_domain *sh7372_pd = to_sh7372_pd(genpd);
  55. unsigned int mask = 1 << sh7372_pd->bit_shift;
  56. unsigned int retry_count;
  57. int ret = 0;
  58. if (__raw_readl(PSTR) & mask)
  59. goto out;
  60. __raw_writel(mask, SWUCR);
  61. for (retry_count = 2 * PSTR_RETRIES; retry_count; retry_count--) {
  62. if (!(__raw_readl(SWUCR) & mask))
  63. goto out;
  64. if (retry_count > PSTR_RETRIES)
  65. udelay(PSTR_DELAY_US);
  66. else
  67. cpu_relax();
  68. }
  69. if (__raw_readl(SWUCR) & mask)
  70. ret = -EIO;
  71. out:
  72. pr_debug("sh7372 power domain up 0x%08x -> PSTR = 0x%08x\n",
  73. mask, __raw_readl(PSTR));
  74. return ret;
  75. }
  76. static bool pd_active_wakeup(struct device *dev)
  77. {
  78. return true;
  79. }
  80. static void sh7372_late_pm_domain_off(void)
  81. {
  82. /* request power down of unused pm domains */
  83. queue_work(pm_wq, &sh7372_a4lc.genpd.power_off_work);
  84. queue_work(pm_wq, &sh7372_a4mp.genpd.power_off_work);
  85. queue_work(pm_wq, &sh7372_d4.genpd.power_off_work);
  86. queue_work(pm_wq, &sh7372_a3rv.genpd.power_off_work);
  87. queue_work(pm_wq, &sh7372_a3ri.genpd.power_off_work);
  88. queue_work(pm_wq, &sh7372_a3sg.genpd.power_off_work);
  89. }
  90. void sh7372_init_pm_domain(struct sh7372_pm_domain *sh7372_pd)
  91. {
  92. struct generic_pm_domain *genpd = &sh7372_pd->genpd;
  93. pm_genpd_init(genpd, NULL, false);
  94. genpd->stop_device = pm_clk_suspend;
  95. genpd->start_device = pm_clk_resume;
  96. genpd->active_wakeup = pd_active_wakeup;
  97. genpd->power_off = pd_power_down;
  98. genpd->power_on = pd_power_up;
  99. pd_power_up(&sh7372_pd->genpd);
  100. shmobile_runtime_pm_late_init = sh7372_late_pm_domain_off;
  101. }
  102. void sh7372_add_device_to_domain(struct sh7372_pm_domain *sh7372_pd,
  103. struct platform_device *pdev)
  104. {
  105. struct device *dev = &pdev->dev;
  106. if (!dev->power.subsys_data) {
  107. pm_clk_init(dev);
  108. pm_clk_add(dev, NULL);
  109. }
  110. pm_genpd_add_device(&sh7372_pd->genpd, dev);
  111. }
  112. struct sh7372_pm_domain sh7372_a4lc = {
  113. .bit_shift = 1,
  114. };
  115. struct sh7372_pm_domain sh7372_a4mp = {
  116. .bit_shift = 2,
  117. };
  118. struct sh7372_pm_domain sh7372_d4 = {
  119. .bit_shift = 3,
  120. };
  121. struct sh7372_pm_domain sh7372_a3rv = {
  122. .bit_shift = 6,
  123. };
  124. struct sh7372_pm_domain sh7372_a3ri = {
  125. .bit_shift = 8,
  126. };
  127. struct sh7372_pm_domain sh7372_a3sg = {
  128. .bit_shift = 13,
  129. };
  130. #endif /* CONFIG_PM */
  131. static void sh7372_enter_core_standby(void)
  132. {
  133. void __iomem *smfram = (void __iomem *)SMFRAM;
  134. __raw_writel(0, APARMBAREA); /* translate 4k */
  135. __raw_writel(__pa(sh7372_cpu_resume), SBAR); /* set reset vector */
  136. __raw_writel(0x10, SYSTBCR); /* enable core standby */
  137. __raw_writel(0, smfram + 0x3c); /* clear page table address */
  138. sh7372_cpu_suspend();
  139. cpu_init();
  140. /* if page table address is non-NULL then we have been powered down */
  141. if (__raw_readl(smfram + 0x3c)) {
  142. __raw_writel(__raw_readl(smfram + 0x40),
  143. __va(__raw_readl(smfram + 0x3c)));
  144. flush_tlb_all();
  145. set_cr(__raw_readl(smfram + 0x38));
  146. }
  147. __raw_writel(0, SYSTBCR); /* disable core standby */
  148. __raw_writel(0, SBAR); /* disable reset vector translation */
  149. }
  150. #ifdef CONFIG_CPU_IDLE
  151. static void sh7372_cpuidle_setup(struct cpuidle_device *dev)
  152. {
  153. struct cpuidle_state *state;
  154. int i = dev->state_count;
  155. state = &dev->states[i];
  156. snprintf(state->name, CPUIDLE_NAME_LEN, "C2");
  157. strncpy(state->desc, "Core Standby Mode", CPUIDLE_DESC_LEN);
  158. state->exit_latency = 10;
  159. state->target_residency = 20 + 10;
  160. state->power_usage = 1; /* perhaps not */
  161. state->flags = 0;
  162. state->flags |= CPUIDLE_FLAG_TIME_VALID;
  163. shmobile_cpuidle_modes[i] = sh7372_enter_core_standby;
  164. dev->state_count = i + 1;
  165. }
  166. static void sh7372_cpuidle_init(void)
  167. {
  168. shmobile_cpuidle_setup = sh7372_cpuidle_setup;
  169. }
  170. #else
  171. static void sh7372_cpuidle_init(void) {}
  172. #endif
  173. #ifdef CONFIG_SUSPEND
  174. static int sh7372_enter_suspend(suspend_state_t suspend_state)
  175. {
  176. sh7372_enter_core_standby();
  177. return 0;
  178. }
  179. static void sh7372_suspend_init(void)
  180. {
  181. shmobile_suspend_ops.enter = sh7372_enter_suspend;
  182. }
  183. #else
  184. static void sh7372_suspend_init(void) {}
  185. #endif
  186. #define DBGREG1 0xe6100020
  187. #define DBGREG9 0xe6100040
  188. void __init sh7372_pm_init(void)
  189. {
  190. /* enable DBG hardware block to kick SYSC */
  191. __raw_writel(0x0000a500, DBGREG9);
  192. __raw_writel(0x0000a501, DBGREG9);
  193. __raw_writel(0x00000000, DBGREG1);
  194. sh7372_suspend_init();
  195. sh7372_cpuidle_init();
  196. }