exynos_tmu.c 14 KB

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  1. /*
  2. * exynos_tmu.c - Samsung EXYNOS TMU (Thermal Management Unit)
  3. *
  4. * Copyright (C) 2011 Samsung Electronics
  5. * Donggeun Kim <dg77.kim@samsung.com>
  6. * Amit Daniel Kachhap <amit.kachhap@linaro.org>
  7. *
  8. * This program is free software; you can redistribute it and/or modify
  9. * it under the terms of the GNU General Public License as published by
  10. * the Free Software Foundation; either version 2 of the License, or
  11. * (at your option) any later version.
  12. *
  13. * This program is distributed in the hope that it will be useful,
  14. * but WITHOUT ANY WARRANTY; without even the implied warranty of
  15. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  16. * GNU General Public License for more details.
  17. *
  18. * You should have received a copy of the GNU General Public License
  19. * along with this program; if not, write to the Free Software
  20. * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
  21. *
  22. */
  23. #include <linux/clk.h>
  24. #include <linux/io.h>
  25. #include <linux/interrupt.h>
  26. #include <linux/module.h>
  27. #include <linux/of.h>
  28. #include <linux/platform_device.h>
  29. #include "exynos_thermal_common.h"
  30. #include "exynos_tmu.h"
  31. #include "exynos_tmu_data.h"
  32. struct exynos_tmu_data {
  33. struct exynos_tmu_platform_data *pdata;
  34. struct resource *mem;
  35. void __iomem *base;
  36. int irq;
  37. enum soc_type soc;
  38. struct work_struct irq_work;
  39. struct mutex lock;
  40. struct clk *clk;
  41. u8 temp_error1, temp_error2;
  42. };
  43. /*
  44. * TMU treats temperature as a mapped temperature code.
  45. * The temperature is converted differently depending on the calibration type.
  46. */
  47. static int temp_to_code(struct exynos_tmu_data *data, u8 temp)
  48. {
  49. struct exynos_tmu_platform_data *pdata = data->pdata;
  50. int temp_code;
  51. if (data->soc == SOC_ARCH_EXYNOS4210)
  52. /* temp should range between 25 and 125 */
  53. if (temp < 25 || temp > 125) {
  54. temp_code = -EINVAL;
  55. goto out;
  56. }
  57. switch (pdata->cal_type) {
  58. case TYPE_TWO_POINT_TRIMMING:
  59. temp_code = (temp - pdata->first_point_trim) *
  60. (data->temp_error2 - data->temp_error1) /
  61. (pdata->second_point_trim - pdata->first_point_trim) +
  62. data->temp_error1;
  63. break;
  64. case TYPE_ONE_POINT_TRIMMING:
  65. temp_code = temp + data->temp_error1 - pdata->first_point_trim;
  66. break;
  67. default:
  68. temp_code = temp + pdata->default_temp_offset;
  69. break;
  70. }
  71. out:
  72. return temp_code;
  73. }
  74. /*
  75. * Calculate a temperature value from a temperature code.
  76. * The unit of the temperature is degree Celsius.
  77. */
  78. static int code_to_temp(struct exynos_tmu_data *data, u8 temp_code)
  79. {
  80. struct exynos_tmu_platform_data *pdata = data->pdata;
  81. int temp;
  82. if (data->soc == SOC_ARCH_EXYNOS4210)
  83. /* temp_code should range between 75 and 175 */
  84. if (temp_code < 75 || temp_code > 175) {
  85. temp = -ENODATA;
  86. goto out;
  87. }
  88. switch (pdata->cal_type) {
  89. case TYPE_TWO_POINT_TRIMMING:
  90. temp = (temp_code - data->temp_error1) *
  91. (pdata->second_point_trim - pdata->first_point_trim) /
  92. (data->temp_error2 - data->temp_error1) +
  93. pdata->first_point_trim;
  94. break;
  95. case TYPE_ONE_POINT_TRIMMING:
  96. temp = temp_code - data->temp_error1 + pdata->first_point_trim;
  97. break;
  98. default:
  99. temp = temp_code - pdata->default_temp_offset;
  100. break;
  101. }
  102. out:
  103. return temp;
  104. }
  105. static int exynos_tmu_initialize(struct platform_device *pdev)
  106. {
  107. struct exynos_tmu_data *data = platform_get_drvdata(pdev);
  108. struct exynos_tmu_platform_data *pdata = data->pdata;
  109. const struct exynos_tmu_registers *reg = pdata->registers;
  110. unsigned int status, trim_info;
  111. unsigned int rising_threshold = 0, falling_threshold = 0;
  112. int ret = 0, threshold_code, i, trigger_levs = 0;
  113. mutex_lock(&data->lock);
  114. clk_enable(data->clk);
  115. status = readb(data->base + reg->tmu_status);
  116. if (!status) {
  117. ret = -EBUSY;
  118. goto out;
  119. }
  120. if (data->soc == SOC_ARCH_EXYNOS)
  121. __raw_writel(1, data->base + reg->triminfo_ctrl);
  122. /* Save trimming info in order to perform calibration */
  123. trim_info = readl(data->base + reg->triminfo_data);
  124. data->temp_error1 = trim_info & EXYNOS_TMU_TEMP_MASK;
  125. data->temp_error2 = ((trim_info >> reg->triminfo_85_shift) &
  126. EXYNOS_TMU_TEMP_MASK);
  127. if ((pdata->min_efuse_value > data->temp_error1) ||
  128. (data->temp_error1 > pdata->max_efuse_value) ||
  129. (data->temp_error2 != 0))
  130. data->temp_error1 = pdata->efuse_value;
  131. /* Count trigger levels to be enabled */
  132. for (i = 0; i < MAX_THRESHOLD_LEVS; i++)
  133. if (pdata->trigger_levels[i])
  134. trigger_levs++;
  135. if (data->soc == SOC_ARCH_EXYNOS4210) {
  136. /* Write temperature code for threshold */
  137. threshold_code = temp_to_code(data, pdata->threshold);
  138. if (threshold_code < 0) {
  139. ret = threshold_code;
  140. goto out;
  141. }
  142. writeb(threshold_code,
  143. data->base + reg->threshold_temp);
  144. for (i = 0; i < trigger_levs; i++)
  145. writeb(pdata->trigger_levels[i], data->base +
  146. reg->threshold_th0 + i * sizeof(reg->threshold_th0));
  147. writel(reg->inten_rise_mask, data->base + reg->tmu_intclear);
  148. } else if (data->soc == SOC_ARCH_EXYNOS) {
  149. /* Write temperature code for rising and falling threshold */
  150. for (i = 0; i < trigger_levs; i++) {
  151. threshold_code = temp_to_code(data,
  152. pdata->trigger_levels[i]);
  153. if (threshold_code < 0) {
  154. ret = threshold_code;
  155. goto out;
  156. }
  157. rising_threshold |= threshold_code << 8 * i;
  158. if (pdata->threshold_falling) {
  159. threshold_code = temp_to_code(data,
  160. pdata->trigger_levels[i] -
  161. pdata->threshold_falling);
  162. if (threshold_code > 0)
  163. falling_threshold |=
  164. threshold_code << 8 * i;
  165. }
  166. }
  167. writel(rising_threshold,
  168. data->base + reg->threshold_th0);
  169. writel(falling_threshold,
  170. data->base + reg->threshold_th1);
  171. writel((reg->inten_rise_mask << reg->inten_rise_shift) |
  172. (reg->inten_fall_mask << reg->inten_fall_shift),
  173. data->base + reg->tmu_intclear);
  174. }
  175. out:
  176. clk_disable(data->clk);
  177. mutex_unlock(&data->lock);
  178. return ret;
  179. }
  180. static void exynos_tmu_control(struct platform_device *pdev, bool on)
  181. {
  182. struct exynos_tmu_data *data = platform_get_drvdata(pdev);
  183. struct exynos_tmu_platform_data *pdata = data->pdata;
  184. const struct exynos_tmu_registers *reg = pdata->registers;
  185. unsigned int con, interrupt_en;
  186. mutex_lock(&data->lock);
  187. clk_enable(data->clk);
  188. con = readl(data->base + reg->tmu_ctrl);
  189. if (pdata->reference_voltage) {
  190. con &= ~(reg->buf_vref_sel_mask << reg->buf_vref_sel_shift);
  191. con |= pdata->reference_voltage << reg->buf_vref_sel_shift;
  192. }
  193. if (pdata->gain) {
  194. con &= ~(reg->buf_slope_sel_mask << reg->buf_slope_sel_shift);
  195. con |= (pdata->gain << reg->buf_slope_sel_shift);
  196. }
  197. if (pdata->noise_cancel_mode) {
  198. con &= ~(reg->therm_trip_mode_mask <<
  199. reg->therm_trip_mode_shift);
  200. con |= (pdata->noise_cancel_mode << reg->therm_trip_mode_shift);
  201. }
  202. if (on) {
  203. con |= (1 << reg->core_en_shift);
  204. interrupt_en =
  205. pdata->trigger_enable[3] << reg->inten_rise3_shift |
  206. pdata->trigger_enable[2] << reg->inten_rise2_shift |
  207. pdata->trigger_enable[1] << reg->inten_rise1_shift |
  208. pdata->trigger_enable[0] << reg->inten_rise0_shift;
  209. if (pdata->threshold_falling)
  210. interrupt_en |=
  211. interrupt_en << reg->inten_fall0_shift;
  212. } else {
  213. con &= ~(1 << reg->core_en_shift);
  214. interrupt_en = 0; /* Disable all interrupts */
  215. }
  216. writel(interrupt_en, data->base + reg->tmu_inten);
  217. writel(con, data->base + reg->tmu_ctrl);
  218. clk_disable(data->clk);
  219. mutex_unlock(&data->lock);
  220. }
  221. static int exynos_tmu_read(struct exynos_tmu_data *data)
  222. {
  223. struct exynos_tmu_platform_data *pdata = data->pdata;
  224. const struct exynos_tmu_registers *reg = pdata->registers;
  225. u8 temp_code;
  226. int temp;
  227. mutex_lock(&data->lock);
  228. clk_enable(data->clk);
  229. temp_code = readb(data->base + reg->tmu_cur_temp);
  230. temp = code_to_temp(data, temp_code);
  231. clk_disable(data->clk);
  232. mutex_unlock(&data->lock);
  233. return temp;
  234. }
  235. #ifdef CONFIG_THERMAL_EMULATION
  236. static int exynos_tmu_set_emulation(void *drv_data, unsigned long temp)
  237. {
  238. struct exynos_tmu_data *data = drv_data;
  239. struct exynos_tmu_platform_data *pdata = data->pdata;
  240. const struct exynos_tmu_registers *reg = pdata->registers;
  241. unsigned int val;
  242. int ret = -EINVAL;
  243. if (data->soc == SOC_ARCH_EXYNOS4210)
  244. goto out;
  245. if (temp && temp < MCELSIUS)
  246. goto out;
  247. mutex_lock(&data->lock);
  248. clk_enable(data->clk);
  249. val = readl(data->base + reg->emul_con);
  250. if (temp) {
  251. temp /= MCELSIUS;
  252. val = (EXYNOS_EMUL_TIME << reg->emul_time_shift) |
  253. (temp_to_code(data, temp)
  254. << reg->emul_temp_shift) | EXYNOS_EMUL_ENABLE;
  255. } else {
  256. val &= ~EXYNOS_EMUL_ENABLE;
  257. }
  258. writel(val, data->base + reg->emul_con);
  259. clk_disable(data->clk);
  260. mutex_unlock(&data->lock);
  261. return 0;
  262. out:
  263. return ret;
  264. }
  265. #else
  266. static int exynos_tmu_set_emulation(void *drv_data, unsigned long temp)
  267. { return -EINVAL; }
  268. #endif/*CONFIG_THERMAL_EMULATION*/
  269. static void exynos_tmu_work(struct work_struct *work)
  270. {
  271. struct exynos_tmu_data *data = container_of(work,
  272. struct exynos_tmu_data, irq_work);
  273. struct exynos_tmu_platform_data *pdata = data->pdata;
  274. const struct exynos_tmu_registers *reg = pdata->registers;
  275. exynos_report_trigger();
  276. mutex_lock(&data->lock);
  277. clk_enable(data->clk);
  278. if (data->soc == SOC_ARCH_EXYNOS)
  279. writel((reg->inten_rise_mask << reg->inten_rise_shift) |
  280. (reg->inten_fall_mask << reg->inten_fall_shift),
  281. data->base + reg->tmu_intclear);
  282. else
  283. writel(reg->inten_rise_mask, data->base + reg->tmu_intclear);
  284. clk_disable(data->clk);
  285. mutex_unlock(&data->lock);
  286. enable_irq(data->irq);
  287. }
  288. static irqreturn_t exynos_tmu_irq(int irq, void *id)
  289. {
  290. struct exynos_tmu_data *data = id;
  291. disable_irq_nosync(irq);
  292. schedule_work(&data->irq_work);
  293. return IRQ_HANDLED;
  294. }
  295. static struct thermal_sensor_conf exynos_sensor_conf = {
  296. .name = "exynos-therm",
  297. .read_temperature = (int (*)(void *))exynos_tmu_read,
  298. .write_emul_temp = exynos_tmu_set_emulation,
  299. };
  300. #ifdef CONFIG_OF
  301. static const struct of_device_id exynos_tmu_match[] = {
  302. {
  303. .compatible = "samsung,exynos4210-tmu",
  304. .data = (void *)EXYNOS4210_TMU_DRV_DATA,
  305. },
  306. {
  307. .compatible = "samsung,exynos4412-tmu",
  308. .data = (void *)EXYNOS5250_TMU_DRV_DATA,
  309. },
  310. {
  311. .compatible = "samsung,exynos5250-tmu",
  312. .data = (void *)EXYNOS5250_TMU_DRV_DATA,
  313. },
  314. {},
  315. };
  316. MODULE_DEVICE_TABLE(of, exynos_tmu_match);
  317. #endif
  318. static struct platform_device_id exynos_tmu_driver_ids[] = {
  319. {
  320. .name = "exynos4210-tmu",
  321. .driver_data = (kernel_ulong_t)EXYNOS4210_TMU_DRV_DATA,
  322. },
  323. {
  324. .name = "exynos5250-tmu",
  325. .driver_data = (kernel_ulong_t)EXYNOS5250_TMU_DRV_DATA,
  326. },
  327. { },
  328. };
  329. MODULE_DEVICE_TABLE(platform, exynos_tmu_driver_ids);
  330. static inline struct exynos_tmu_platform_data *exynos_get_driver_data(
  331. struct platform_device *pdev)
  332. {
  333. #ifdef CONFIG_OF
  334. if (pdev->dev.of_node) {
  335. const struct of_device_id *match;
  336. match = of_match_node(exynos_tmu_match, pdev->dev.of_node);
  337. if (!match)
  338. return NULL;
  339. return (struct exynos_tmu_platform_data *) match->data;
  340. }
  341. #endif
  342. return (struct exynos_tmu_platform_data *)
  343. platform_get_device_id(pdev)->driver_data;
  344. }
  345. static int exynos_tmu_probe(struct platform_device *pdev)
  346. {
  347. struct exynos_tmu_data *data;
  348. struct exynos_tmu_platform_data *pdata = pdev->dev.platform_data;
  349. int ret, i;
  350. if (!pdata)
  351. pdata = exynos_get_driver_data(pdev);
  352. if (!pdata) {
  353. dev_err(&pdev->dev, "No platform init data supplied.\n");
  354. return -ENODEV;
  355. }
  356. data = devm_kzalloc(&pdev->dev, sizeof(struct exynos_tmu_data),
  357. GFP_KERNEL);
  358. if (!data) {
  359. dev_err(&pdev->dev, "Failed to allocate driver structure\n");
  360. return -ENOMEM;
  361. }
  362. data->irq = platform_get_irq(pdev, 0);
  363. if (data->irq < 0) {
  364. dev_err(&pdev->dev, "Failed to get platform irq\n");
  365. return data->irq;
  366. }
  367. INIT_WORK(&data->irq_work, exynos_tmu_work);
  368. data->mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
  369. data->base = devm_ioremap_resource(&pdev->dev, data->mem);
  370. if (IS_ERR(data->base))
  371. return PTR_ERR(data->base);
  372. ret = devm_request_irq(&pdev->dev, data->irq, exynos_tmu_irq,
  373. IRQF_TRIGGER_RISING, "exynos-tmu", data);
  374. if (ret) {
  375. dev_err(&pdev->dev, "Failed to request irq: %d\n", data->irq);
  376. return ret;
  377. }
  378. data->clk = devm_clk_get(&pdev->dev, "tmu_apbif");
  379. if (IS_ERR(data->clk)) {
  380. dev_err(&pdev->dev, "Failed to get clock\n");
  381. return PTR_ERR(data->clk);
  382. }
  383. ret = clk_prepare(data->clk);
  384. if (ret)
  385. return ret;
  386. if (pdata->type == SOC_ARCH_EXYNOS ||
  387. pdata->type == SOC_ARCH_EXYNOS4210)
  388. data->soc = pdata->type;
  389. else {
  390. ret = -EINVAL;
  391. dev_err(&pdev->dev, "Platform not supported\n");
  392. goto err_clk;
  393. }
  394. data->pdata = pdata;
  395. platform_set_drvdata(pdev, data);
  396. mutex_init(&data->lock);
  397. ret = exynos_tmu_initialize(pdev);
  398. if (ret) {
  399. dev_err(&pdev->dev, "Failed to initialize TMU\n");
  400. goto err_clk;
  401. }
  402. exynos_tmu_control(pdev, true);
  403. /* Register the sensor with thermal management interface */
  404. (&exynos_sensor_conf)->private_data = data;
  405. exynos_sensor_conf.trip_data.trip_count = pdata->trigger_enable[0] +
  406. pdata->trigger_enable[1] + pdata->trigger_enable[2]+
  407. pdata->trigger_enable[3];
  408. for (i = 0; i < exynos_sensor_conf.trip_data.trip_count; i++)
  409. exynos_sensor_conf.trip_data.trip_val[i] =
  410. pdata->threshold + pdata->trigger_levels[i];
  411. exynos_sensor_conf.trip_data.trigger_falling = pdata->threshold_falling;
  412. exynos_sensor_conf.cooling_data.freq_clip_count =
  413. pdata->freq_tab_count;
  414. for (i = 0; i < pdata->freq_tab_count; i++) {
  415. exynos_sensor_conf.cooling_data.freq_data[i].freq_clip_max =
  416. pdata->freq_tab[i].freq_clip_max;
  417. exynos_sensor_conf.cooling_data.freq_data[i].temp_level =
  418. pdata->freq_tab[i].temp_level;
  419. }
  420. ret = exynos_register_thermal(&exynos_sensor_conf);
  421. if (ret) {
  422. dev_err(&pdev->dev, "Failed to register thermal interface\n");
  423. goto err_clk;
  424. }
  425. return 0;
  426. err_clk:
  427. clk_unprepare(data->clk);
  428. return ret;
  429. }
  430. static int exynos_tmu_remove(struct platform_device *pdev)
  431. {
  432. struct exynos_tmu_data *data = platform_get_drvdata(pdev);
  433. exynos_tmu_control(pdev, false);
  434. exynos_unregister_thermal();
  435. clk_unprepare(data->clk);
  436. return 0;
  437. }
  438. #ifdef CONFIG_PM_SLEEP
  439. static int exynos_tmu_suspend(struct device *dev)
  440. {
  441. exynos_tmu_control(to_platform_device(dev), false);
  442. return 0;
  443. }
  444. static int exynos_tmu_resume(struct device *dev)
  445. {
  446. struct platform_device *pdev = to_platform_device(dev);
  447. exynos_tmu_initialize(pdev);
  448. exynos_tmu_control(pdev, true);
  449. return 0;
  450. }
  451. static SIMPLE_DEV_PM_OPS(exynos_tmu_pm,
  452. exynos_tmu_suspend, exynos_tmu_resume);
  453. #define EXYNOS_TMU_PM (&exynos_tmu_pm)
  454. #else
  455. #define EXYNOS_TMU_PM NULL
  456. #endif
  457. static struct platform_driver exynos_tmu_driver = {
  458. .driver = {
  459. .name = "exynos-tmu",
  460. .owner = THIS_MODULE,
  461. .pm = EXYNOS_TMU_PM,
  462. .of_match_table = of_match_ptr(exynos_tmu_match),
  463. },
  464. .probe = exynos_tmu_probe,
  465. .remove = exynos_tmu_remove,
  466. .id_table = exynos_tmu_driver_ids,
  467. };
  468. module_platform_driver(exynos_tmu_driver);
  469. MODULE_DESCRIPTION("EXYNOS TMU Driver");
  470. MODULE_AUTHOR("Donggeun Kim <dg77.kim@samsung.com>");
  471. MODULE_LICENSE("GPL");
  472. MODULE_ALIAS("platform:exynos-tmu");