spi_s3c24xx.c 9.9 KB

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  1. /* linux/drivers/spi/spi_s3c24xx.c
  2. *
  3. * Copyright (c) 2006 Ben Dooks
  4. * Copyright (c) 2006 Simtec Electronics
  5. * Ben Dooks <ben@simtec.co.uk>
  6. *
  7. * This program is free software; you can redistribute it and/or modify
  8. * it under the terms of the GNU General Public License version 2 as
  9. * published by the Free Software Foundation.
  10. *
  11. */
  12. #include <linux/init.h>
  13. #include <linux/spinlock.h>
  14. #include <linux/workqueue.h>
  15. #include <linux/interrupt.h>
  16. #include <linux/delay.h>
  17. #include <linux/errno.h>
  18. #include <linux/err.h>
  19. #include <linux/clk.h>
  20. #include <linux/platform_device.h>
  21. #include <linux/gpio.h>
  22. #include <linux/spi/spi.h>
  23. #include <linux/spi/spi_bitbang.h>
  24. #include <asm/io.h>
  25. #include <asm/dma.h>
  26. #include <mach/hardware.h>
  27. #include <plat/regs-spi.h>
  28. #include <mach/spi.h>
  29. struct s3c24xx_spi {
  30. /* bitbang has to be first */
  31. struct spi_bitbang bitbang;
  32. struct completion done;
  33. void __iomem *regs;
  34. int irq;
  35. int len;
  36. int count;
  37. void (*set_cs)(struct s3c2410_spi_info *spi,
  38. int cs, int pol);
  39. /* data buffers */
  40. const unsigned char *tx;
  41. unsigned char *rx;
  42. struct clk *clk;
  43. struct resource *ioarea;
  44. struct spi_master *master;
  45. struct spi_device *curdev;
  46. struct device *dev;
  47. struct s3c2410_spi_info *pdata;
  48. };
  49. #define SPCON_DEFAULT (S3C2410_SPCON_MSTR | S3C2410_SPCON_SMOD_INT)
  50. #define SPPIN_DEFAULT (S3C2410_SPPIN_KEEP)
  51. static inline struct s3c24xx_spi *to_hw(struct spi_device *sdev)
  52. {
  53. return spi_master_get_devdata(sdev->master);
  54. }
  55. static void s3c24xx_spi_gpiocs(struct s3c2410_spi_info *spi, int cs, int pol)
  56. {
  57. gpio_set_value(spi->pin_cs, pol);
  58. }
  59. static void s3c24xx_spi_chipsel(struct spi_device *spi, int value)
  60. {
  61. struct s3c24xx_spi *hw = to_hw(spi);
  62. unsigned int cspol = spi->mode & SPI_CS_HIGH ? 1 : 0;
  63. unsigned int spcon;
  64. switch (value) {
  65. case BITBANG_CS_INACTIVE:
  66. hw->set_cs(hw->pdata, spi->chip_select, cspol^1);
  67. break;
  68. case BITBANG_CS_ACTIVE:
  69. spcon = readb(hw->regs + S3C2410_SPCON);
  70. if (spi->mode & SPI_CPHA)
  71. spcon |= S3C2410_SPCON_CPHA_FMTB;
  72. else
  73. spcon &= ~S3C2410_SPCON_CPHA_FMTB;
  74. if (spi->mode & SPI_CPOL)
  75. spcon |= S3C2410_SPCON_CPOL_HIGH;
  76. else
  77. spcon &= ~S3C2410_SPCON_CPOL_HIGH;
  78. spcon |= S3C2410_SPCON_ENSCK;
  79. /* write new configration */
  80. writeb(spcon, hw->regs + S3C2410_SPCON);
  81. hw->set_cs(hw->pdata, spi->chip_select, cspol);
  82. break;
  83. }
  84. }
  85. static int s3c24xx_spi_setupxfer(struct spi_device *spi,
  86. struct spi_transfer *t)
  87. {
  88. struct s3c24xx_spi *hw = to_hw(spi);
  89. unsigned int bpw;
  90. unsigned int hz;
  91. unsigned int div;
  92. unsigned long clk;
  93. bpw = t ? t->bits_per_word : spi->bits_per_word;
  94. hz = t ? t->speed_hz : spi->max_speed_hz;
  95. if (bpw != 8) {
  96. dev_err(&spi->dev, "invalid bits-per-word (%d)\n", bpw);
  97. return -EINVAL;
  98. }
  99. clk = clk_get_rate(hw->clk);
  100. div = DIV_ROUND_UP(clk, hz * 2) - 1;
  101. if (div > 255)
  102. div = 255;
  103. dev_dbg(&spi->dev, "setting pre-scaler to %d (wanted %d, got %ld)\n",
  104. div, hz, clk / (2 * (div + 1)));
  105. writeb(div, hw->regs + S3C2410_SPPRE);
  106. spin_lock(&hw->bitbang.lock);
  107. if (!hw->bitbang.busy) {
  108. hw->bitbang.chipselect(spi, BITBANG_CS_INACTIVE);
  109. /* need to ndelay for 0.5 clocktick ? */
  110. }
  111. spin_unlock(&hw->bitbang.lock);
  112. return 0;
  113. }
  114. static int s3c24xx_spi_setup(struct spi_device *spi)
  115. {
  116. int ret;
  117. ret = s3c24xx_spi_setupxfer(spi, NULL);
  118. if (ret < 0) {
  119. dev_err(&spi->dev, "setupxfer returned %d\n", ret);
  120. return ret;
  121. }
  122. return 0;
  123. }
  124. static inline unsigned int hw_txbyte(struct s3c24xx_spi *hw, int count)
  125. {
  126. return hw->tx ? hw->tx[count] : 0;
  127. }
  128. static int s3c24xx_spi_txrx(struct spi_device *spi, struct spi_transfer *t)
  129. {
  130. struct s3c24xx_spi *hw = to_hw(spi);
  131. dev_dbg(&spi->dev, "txrx: tx %p, rx %p, len %d\n",
  132. t->tx_buf, t->rx_buf, t->len);
  133. hw->tx = t->tx_buf;
  134. hw->rx = t->rx_buf;
  135. hw->len = t->len;
  136. hw->count = 0;
  137. init_completion(&hw->done);
  138. /* send the first byte */
  139. writeb(hw_txbyte(hw, 0), hw->regs + S3C2410_SPTDAT);
  140. wait_for_completion(&hw->done);
  141. return hw->count;
  142. }
  143. static irqreturn_t s3c24xx_spi_irq(int irq, void *dev)
  144. {
  145. struct s3c24xx_spi *hw = dev;
  146. unsigned int spsta = readb(hw->regs + S3C2410_SPSTA);
  147. unsigned int count = hw->count;
  148. if (spsta & S3C2410_SPSTA_DCOL) {
  149. dev_dbg(hw->dev, "data-collision\n");
  150. complete(&hw->done);
  151. goto irq_done;
  152. }
  153. if (!(spsta & S3C2410_SPSTA_READY)) {
  154. dev_dbg(hw->dev, "spi not ready for tx?\n");
  155. complete(&hw->done);
  156. goto irq_done;
  157. }
  158. hw->count++;
  159. if (hw->rx)
  160. hw->rx[count] = readb(hw->regs + S3C2410_SPRDAT);
  161. count++;
  162. if (count < hw->len)
  163. writeb(hw_txbyte(hw, count), hw->regs + S3C2410_SPTDAT);
  164. else
  165. complete(&hw->done);
  166. irq_done:
  167. return IRQ_HANDLED;
  168. }
  169. static void s3c24xx_spi_initialsetup(struct s3c24xx_spi *hw)
  170. {
  171. /* for the moment, permanently enable the clock */
  172. clk_enable(hw->clk);
  173. /* program defaults into the registers */
  174. writeb(0xff, hw->regs + S3C2410_SPPRE);
  175. writeb(SPPIN_DEFAULT, hw->regs + S3C2410_SPPIN);
  176. writeb(SPCON_DEFAULT, hw->regs + S3C2410_SPCON);
  177. if (hw->pdata) {
  178. if (hw->set_cs == s3c24xx_spi_gpiocs)
  179. gpio_direction_output(hw->pdata->pin_cs, 1);
  180. if (hw->pdata->gpio_setup)
  181. hw->pdata->gpio_setup(hw->pdata, 1);
  182. }
  183. }
  184. static int __init s3c24xx_spi_probe(struct platform_device *pdev)
  185. {
  186. struct s3c2410_spi_info *pdata;
  187. struct s3c24xx_spi *hw;
  188. struct spi_master *master;
  189. struct resource *res;
  190. int err = 0;
  191. master = spi_alloc_master(&pdev->dev, sizeof(struct s3c24xx_spi));
  192. if (master == NULL) {
  193. dev_err(&pdev->dev, "No memory for spi_master\n");
  194. err = -ENOMEM;
  195. goto err_nomem;
  196. }
  197. hw = spi_master_get_devdata(master);
  198. memset(hw, 0, sizeof(struct s3c24xx_spi));
  199. hw->master = spi_master_get(master);
  200. hw->pdata = pdata = pdev->dev.platform_data;
  201. hw->dev = &pdev->dev;
  202. if (pdata == NULL) {
  203. dev_err(&pdev->dev, "No platform data supplied\n");
  204. err = -ENOENT;
  205. goto err_no_pdata;
  206. }
  207. platform_set_drvdata(pdev, hw);
  208. init_completion(&hw->done);
  209. /* setup the master state. */
  210. /* the spi->mode bits understood by this driver: */
  211. master->mode_bits = SPI_CPOL | SPI_CPHA | SPI_CS_HIGH;
  212. master->num_chipselect = hw->pdata->num_cs;
  213. master->bus_num = pdata->bus_num;
  214. /* setup the state for the bitbang driver */
  215. hw->bitbang.master = hw->master;
  216. hw->bitbang.setup_transfer = s3c24xx_spi_setupxfer;
  217. hw->bitbang.chipselect = s3c24xx_spi_chipsel;
  218. hw->bitbang.txrx_bufs = s3c24xx_spi_txrx;
  219. hw->bitbang.master->setup = s3c24xx_spi_setup;
  220. dev_dbg(hw->dev, "bitbang at %p\n", &hw->bitbang);
  221. /* find and map our resources */
  222. res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
  223. if (res == NULL) {
  224. dev_err(&pdev->dev, "Cannot get IORESOURCE_MEM\n");
  225. err = -ENOENT;
  226. goto err_no_iores;
  227. }
  228. hw->ioarea = request_mem_region(res->start, (res->end - res->start)+1,
  229. pdev->name);
  230. if (hw->ioarea == NULL) {
  231. dev_err(&pdev->dev, "Cannot reserve region\n");
  232. err = -ENXIO;
  233. goto err_no_iores;
  234. }
  235. hw->regs = ioremap(res->start, (res->end - res->start)+1);
  236. if (hw->regs == NULL) {
  237. dev_err(&pdev->dev, "Cannot map IO\n");
  238. err = -ENXIO;
  239. goto err_no_iomap;
  240. }
  241. hw->irq = platform_get_irq(pdev, 0);
  242. if (hw->irq < 0) {
  243. dev_err(&pdev->dev, "No IRQ specified\n");
  244. err = -ENOENT;
  245. goto err_no_irq;
  246. }
  247. err = request_irq(hw->irq, s3c24xx_spi_irq, 0, pdev->name, hw);
  248. if (err) {
  249. dev_err(&pdev->dev, "Cannot claim IRQ\n");
  250. goto err_no_irq;
  251. }
  252. hw->clk = clk_get(&pdev->dev, "spi");
  253. if (IS_ERR(hw->clk)) {
  254. dev_err(&pdev->dev, "No clock for device\n");
  255. err = PTR_ERR(hw->clk);
  256. goto err_no_clk;
  257. }
  258. /* setup any gpio we can */
  259. if (!pdata->set_cs) {
  260. if (pdata->pin_cs < 0) {
  261. dev_err(&pdev->dev, "No chipselect pin\n");
  262. goto err_register;
  263. }
  264. err = gpio_request(pdata->pin_cs, dev_name(&pdev->dev));
  265. if (err) {
  266. dev_err(&pdev->dev, "Failed to get gpio for cs\n");
  267. goto err_register;
  268. }
  269. hw->set_cs = s3c24xx_spi_gpiocs;
  270. gpio_direction_output(pdata->pin_cs, 1);
  271. } else
  272. hw->set_cs = pdata->set_cs;
  273. s3c24xx_spi_initialsetup(hw);
  274. /* register our spi controller */
  275. err = spi_bitbang_start(&hw->bitbang);
  276. if (err) {
  277. dev_err(&pdev->dev, "Failed to register SPI master\n");
  278. goto err_register;
  279. }
  280. return 0;
  281. err_register:
  282. if (hw->set_cs == s3c24xx_spi_gpiocs)
  283. gpio_free(pdata->pin_cs);
  284. clk_disable(hw->clk);
  285. clk_put(hw->clk);
  286. err_no_clk:
  287. free_irq(hw->irq, hw);
  288. err_no_irq:
  289. iounmap(hw->regs);
  290. err_no_iomap:
  291. release_resource(hw->ioarea);
  292. kfree(hw->ioarea);
  293. err_no_iores:
  294. err_no_pdata:
  295. spi_master_put(hw->master);;
  296. err_nomem:
  297. return err;
  298. }
  299. static int __exit s3c24xx_spi_remove(struct platform_device *dev)
  300. {
  301. struct s3c24xx_spi *hw = platform_get_drvdata(dev);
  302. platform_set_drvdata(dev, NULL);
  303. spi_unregister_master(hw->master);
  304. clk_disable(hw->clk);
  305. clk_put(hw->clk);
  306. free_irq(hw->irq, hw);
  307. iounmap(hw->regs);
  308. if (hw->set_cs == s3c24xx_spi_gpiocs)
  309. gpio_free(hw->pdata->pin_cs);
  310. release_resource(hw->ioarea);
  311. kfree(hw->ioarea);
  312. spi_master_put(hw->master);
  313. return 0;
  314. }
  315. #ifdef CONFIG_PM
  316. static int s3c24xx_spi_suspend(struct platform_device *pdev, pm_message_t msg)
  317. {
  318. struct s3c24xx_spi *hw = platform_get_drvdata(pdev);
  319. if (hw->pdata && hw->pdata->gpio_setup)
  320. hw->pdata->gpio_setup(hw->pdata, 0);
  321. clk_disable(hw->clk);
  322. return 0;
  323. }
  324. static int s3c24xx_spi_resume(struct platform_device *pdev)
  325. {
  326. struct s3c24xx_spi *hw = platform_get_drvdata(pdev);
  327. s3c24xx_spi_initialsetup(hw);
  328. return 0;
  329. }
  330. #else
  331. #define s3c24xx_spi_suspend NULL
  332. #define s3c24xx_spi_resume NULL
  333. #endif
  334. MODULE_ALIAS("platform:s3c2410-spi");
  335. static struct platform_driver s3c24xx_spi_driver = {
  336. .remove = __exit_p(s3c24xx_spi_remove),
  337. .suspend = s3c24xx_spi_suspend,
  338. .resume = s3c24xx_spi_resume,
  339. .driver = {
  340. .name = "s3c2410-spi",
  341. .owner = THIS_MODULE,
  342. },
  343. };
  344. static int __init s3c24xx_spi_init(void)
  345. {
  346. return platform_driver_probe(&s3c24xx_spi_driver, s3c24xx_spi_probe);
  347. }
  348. static void __exit s3c24xx_spi_exit(void)
  349. {
  350. platform_driver_unregister(&s3c24xx_spi_driver);
  351. }
  352. module_init(s3c24xx_spi_init);
  353. module_exit(s3c24xx_spi_exit);
  354. MODULE_DESCRIPTION("S3C24XX SPI Driver");
  355. MODULE_AUTHOR("Ben Dooks, <ben@simtec.co.uk>");
  356. MODULE_LICENSE("GPL");