omap-mcpdm.c 14 KB

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  1. /*
  2. * omap-mcpdm.c -- OMAP ALSA SoC DAI driver using McPDM port
  3. *
  4. * Copyright (C) 2009 - 2011 Texas Instruments
  5. *
  6. * Author: Misael Lopez Cruz <misael.lopez@ti.com>
  7. * Contact: Jorge Eduardo Candelaria <x0107209@ti.com>
  8. * Margarita Olaya <magi.olaya@ti.com>
  9. * Peter Ujfalusi <peter.ujfalusi@ti.com>
  10. *
  11. * This program is free software; you can redistribute it and/or
  12. * modify it under the terms of the GNU General Public License
  13. * version 2 as published by the Free Software Foundation.
  14. *
  15. * This program is distributed in the hope that it will be useful, but
  16. * WITHOUT ANY WARRANTY; without even the implied warranty of
  17. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
  18. * General Public License for more details.
  19. *
  20. * You should have received a copy of the GNU General Public License
  21. * along with this program; if not, write to the Free Software
  22. * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA
  23. * 02110-1301 USA
  24. *
  25. */
  26. #include <linux/init.h>
  27. #include <linux/module.h>
  28. #include <linux/platform_device.h>
  29. #include <linux/interrupt.h>
  30. #include <linux/err.h>
  31. #include <linux/io.h>
  32. #include <linux/irq.h>
  33. #include <linux/slab.h>
  34. #include <linux/pm_runtime.h>
  35. #include <sound/core.h>
  36. #include <sound/pcm.h>
  37. #include <sound/pcm_params.h>
  38. #include <sound/soc.h>
  39. #include <plat/dma.h>
  40. #include <plat/omap_hwmod.h>
  41. #include "omap-mcpdm.h"
  42. #include "omap-pcm.h"
  43. struct omap_mcpdm {
  44. struct device *dev;
  45. unsigned long phys_base;
  46. void __iomem *io_base;
  47. int irq;
  48. struct mutex mutex;
  49. /* channel data */
  50. u32 dn_channels;
  51. u32 up_channels;
  52. /* McPDM FIFO thresholds */
  53. u32 dn_threshold;
  54. u32 up_threshold;
  55. /* McPDM dn offsets for rx1, and 2 channels */
  56. u32 dn_rx_offset;
  57. };
  58. /*
  59. * Stream DMA parameters
  60. */
  61. static struct omap_pcm_dma_data omap_mcpdm_dai_dma_params[] = {
  62. {
  63. .name = "Audio playback",
  64. .dma_req = OMAP44XX_DMA_MCPDM_DL,
  65. .data_type = OMAP_DMA_DATA_TYPE_S32,
  66. .sync_mode = OMAP_DMA_SYNC_PACKET,
  67. .port_addr = OMAP44XX_MCPDM_L3_BASE + MCPDM_REG_DN_DATA,
  68. },
  69. {
  70. .name = "Audio capture",
  71. .dma_req = OMAP44XX_DMA_MCPDM_UP,
  72. .data_type = OMAP_DMA_DATA_TYPE_S32,
  73. .sync_mode = OMAP_DMA_SYNC_PACKET,
  74. .port_addr = OMAP44XX_MCPDM_L3_BASE + MCPDM_REG_UP_DATA,
  75. },
  76. };
  77. static inline void omap_mcpdm_write(struct omap_mcpdm *mcpdm, u16 reg, u32 val)
  78. {
  79. __raw_writel(val, mcpdm->io_base + reg);
  80. }
  81. static inline int omap_mcpdm_read(struct omap_mcpdm *mcpdm, u16 reg)
  82. {
  83. return __raw_readl(mcpdm->io_base + reg);
  84. }
  85. #ifdef DEBUG
  86. static void omap_mcpdm_reg_dump(struct omap_mcpdm *mcpdm)
  87. {
  88. dev_dbg(mcpdm->dev, "***********************\n");
  89. dev_dbg(mcpdm->dev, "IRQSTATUS_RAW: 0x%04x\n",
  90. omap_mcpdm_read(mcpdm, MCPDM_REG_IRQSTATUS_RAW));
  91. dev_dbg(mcpdm->dev, "IRQSTATUS: 0x%04x\n",
  92. omap_mcpdm_read(mcpdm, MCPDM_REG_IRQSTATUS));
  93. dev_dbg(mcpdm->dev, "IRQENABLE_SET: 0x%04x\n",
  94. omap_mcpdm_read(mcpdm, MCPDM_REG_IRQENABLE_SET));
  95. dev_dbg(mcpdm->dev, "IRQENABLE_CLR: 0x%04x\n",
  96. omap_mcpdm_read(mcpdm, MCPDM_REG_IRQENABLE_CLR));
  97. dev_dbg(mcpdm->dev, "IRQWAKE_EN: 0x%04x\n",
  98. omap_mcpdm_read(mcpdm, MCPDM_REG_IRQWAKE_EN));
  99. dev_dbg(mcpdm->dev, "DMAENABLE_SET: 0x%04x\n",
  100. omap_mcpdm_read(mcpdm, MCPDM_REG_DMAENABLE_SET));
  101. dev_dbg(mcpdm->dev, "DMAENABLE_CLR: 0x%04x\n",
  102. omap_mcpdm_read(mcpdm, MCPDM_REG_DMAENABLE_CLR));
  103. dev_dbg(mcpdm->dev, "DMAWAKEEN: 0x%04x\n",
  104. omap_mcpdm_read(mcpdm, MCPDM_REG_DMAWAKEEN));
  105. dev_dbg(mcpdm->dev, "CTRL: 0x%04x\n",
  106. omap_mcpdm_read(mcpdm, MCPDM_REG_CTRL));
  107. dev_dbg(mcpdm->dev, "DN_DATA: 0x%04x\n",
  108. omap_mcpdm_read(mcpdm, MCPDM_REG_DN_DATA));
  109. dev_dbg(mcpdm->dev, "UP_DATA: 0x%04x\n",
  110. omap_mcpdm_read(mcpdm, MCPDM_REG_UP_DATA));
  111. dev_dbg(mcpdm->dev, "FIFO_CTRL_DN: 0x%04x\n",
  112. omap_mcpdm_read(mcpdm, MCPDM_REG_FIFO_CTRL_DN));
  113. dev_dbg(mcpdm->dev, "FIFO_CTRL_UP: 0x%04x\n",
  114. omap_mcpdm_read(mcpdm, MCPDM_REG_FIFO_CTRL_UP));
  115. dev_dbg(mcpdm->dev, "***********************\n");
  116. }
  117. #else
  118. static void omap_mcpdm_reg_dump(struct omap_mcpdm *mcpdm) {}
  119. #endif
  120. /*
  121. * Enables the transfer through the PDM interface to/from the Phoenix
  122. * codec by enabling the corresponding UP or DN channels.
  123. */
  124. static void omap_mcpdm_start(struct omap_mcpdm *mcpdm)
  125. {
  126. u32 ctrl = omap_mcpdm_read(mcpdm, MCPDM_REG_CTRL);
  127. ctrl |= (MCPDM_SW_DN_RST | MCPDM_SW_UP_RST);
  128. omap_mcpdm_write(mcpdm, MCPDM_REG_CTRL, ctrl);
  129. ctrl |= mcpdm->dn_channels | mcpdm->up_channels;
  130. omap_mcpdm_write(mcpdm, MCPDM_REG_CTRL, ctrl);
  131. ctrl &= ~(MCPDM_SW_DN_RST | MCPDM_SW_UP_RST);
  132. omap_mcpdm_write(mcpdm, MCPDM_REG_CTRL, ctrl);
  133. }
  134. /*
  135. * Disables the transfer through the PDM interface to/from the Phoenix
  136. * codec by disabling the corresponding UP or DN channels.
  137. */
  138. static void omap_mcpdm_stop(struct omap_mcpdm *mcpdm)
  139. {
  140. u32 ctrl = omap_mcpdm_read(mcpdm, MCPDM_REG_CTRL);
  141. ctrl |= (MCPDM_SW_DN_RST | MCPDM_SW_UP_RST);
  142. omap_mcpdm_write(mcpdm, MCPDM_REG_CTRL, ctrl);
  143. ctrl &= ~(mcpdm->dn_channels | mcpdm->up_channels);
  144. omap_mcpdm_write(mcpdm, MCPDM_REG_CTRL, ctrl);
  145. ctrl &= ~(MCPDM_SW_DN_RST | MCPDM_SW_UP_RST);
  146. omap_mcpdm_write(mcpdm, MCPDM_REG_CTRL, ctrl);
  147. }
  148. /*
  149. * Is the physical McPDM interface active.
  150. */
  151. static inline int omap_mcpdm_active(struct omap_mcpdm *mcpdm)
  152. {
  153. return omap_mcpdm_read(mcpdm, MCPDM_REG_CTRL) &
  154. (MCPDM_PDM_DN_MASK | MCPDM_PDM_UP_MASK);
  155. }
  156. /*
  157. * Configures McPDM uplink, and downlink for audio.
  158. * This function should be called before omap_mcpdm_start.
  159. */
  160. static void omap_mcpdm_open_streams(struct omap_mcpdm *mcpdm)
  161. {
  162. omap_mcpdm_write(mcpdm, MCPDM_REG_IRQENABLE_SET,
  163. MCPDM_DN_IRQ_EMPTY | MCPDM_DN_IRQ_FULL |
  164. MCPDM_UP_IRQ_EMPTY | MCPDM_UP_IRQ_FULL);
  165. /* Enable DN RX1/2 offset cancellation feature, if configured */
  166. if (mcpdm->dn_rx_offset) {
  167. u32 dn_offset = mcpdm->dn_rx_offset;
  168. omap_mcpdm_write(mcpdm, MCPDM_REG_DN_OFFSET, dn_offset);
  169. dn_offset |= (MCPDM_DN_OFST_RX1_EN | MCPDM_DN_OFST_RX2_EN);
  170. omap_mcpdm_write(mcpdm, MCPDM_REG_DN_OFFSET, dn_offset);
  171. }
  172. omap_mcpdm_write(mcpdm, MCPDM_REG_FIFO_CTRL_DN, mcpdm->dn_threshold);
  173. omap_mcpdm_write(mcpdm, MCPDM_REG_FIFO_CTRL_UP, mcpdm->up_threshold);
  174. omap_mcpdm_write(mcpdm, MCPDM_REG_DMAENABLE_SET,
  175. MCPDM_DMA_DN_ENABLE | MCPDM_DMA_UP_ENABLE);
  176. }
  177. /*
  178. * Cleans McPDM uplink, and downlink configuration.
  179. * This function should be called when the stream is closed.
  180. */
  181. static void omap_mcpdm_close_streams(struct omap_mcpdm *mcpdm)
  182. {
  183. /* Disable irq request generation for downlink */
  184. omap_mcpdm_write(mcpdm, MCPDM_REG_IRQENABLE_CLR,
  185. MCPDM_DN_IRQ_EMPTY | MCPDM_DN_IRQ_FULL);
  186. /* Disable DMA request generation for downlink */
  187. omap_mcpdm_write(mcpdm, MCPDM_REG_DMAENABLE_CLR, MCPDM_DMA_DN_ENABLE);
  188. /* Disable irq request generation for uplink */
  189. omap_mcpdm_write(mcpdm, MCPDM_REG_IRQENABLE_CLR,
  190. MCPDM_UP_IRQ_EMPTY | MCPDM_UP_IRQ_FULL);
  191. /* Disable DMA request generation for uplink */
  192. omap_mcpdm_write(mcpdm, MCPDM_REG_DMAENABLE_CLR, MCPDM_DMA_UP_ENABLE);
  193. /* Disable RX1/2 offset cancellation */
  194. if (mcpdm->dn_rx_offset)
  195. omap_mcpdm_write(mcpdm, MCPDM_REG_DN_OFFSET, 0);
  196. }
  197. static irqreturn_t omap_mcpdm_irq_handler(int irq, void *dev_id)
  198. {
  199. struct omap_mcpdm *mcpdm = dev_id;
  200. int irq_status;
  201. irq_status = omap_mcpdm_read(mcpdm, MCPDM_REG_IRQSTATUS);
  202. /* Acknowledge irq event */
  203. omap_mcpdm_write(mcpdm, MCPDM_REG_IRQSTATUS, irq_status);
  204. if (irq_status & MCPDM_DN_IRQ_FULL)
  205. dev_dbg(mcpdm->dev, "DN (playback) FIFO Full\n");
  206. if (irq_status & MCPDM_DN_IRQ_EMPTY)
  207. dev_dbg(mcpdm->dev, "DN (playback) FIFO Empty\n");
  208. if (irq_status & MCPDM_DN_IRQ)
  209. dev_dbg(mcpdm->dev, "DN (playback) write request\n");
  210. if (irq_status & MCPDM_UP_IRQ_FULL)
  211. dev_dbg(mcpdm->dev, "UP (capture) FIFO Full\n");
  212. if (irq_status & MCPDM_UP_IRQ_EMPTY)
  213. dev_dbg(mcpdm->dev, "UP (capture) FIFO Empty\n");
  214. if (irq_status & MCPDM_UP_IRQ)
  215. dev_dbg(mcpdm->dev, "UP (capture) write request\n");
  216. return IRQ_HANDLED;
  217. }
  218. static int omap_mcpdm_dai_startup(struct snd_pcm_substream *substream,
  219. struct snd_soc_dai *dai)
  220. {
  221. struct omap_mcpdm *mcpdm = snd_soc_dai_get_drvdata(dai);
  222. mutex_lock(&mcpdm->mutex);
  223. if (!dai->active) {
  224. pm_runtime_get_sync(mcpdm->dev);
  225. /* Enable watch dog for ES above ES 1.0 to avoid saturation */
  226. if (omap_rev() != OMAP4430_REV_ES1_0) {
  227. u32 ctrl = omap_mcpdm_read(mcpdm, MCPDM_REG_CTRL);
  228. omap_mcpdm_write(mcpdm, MCPDM_REG_CTRL,
  229. ctrl | MCPDM_WD_EN);
  230. }
  231. omap_mcpdm_open_streams(mcpdm);
  232. }
  233. mutex_unlock(&mcpdm->mutex);
  234. return 0;
  235. }
  236. static void omap_mcpdm_dai_shutdown(struct snd_pcm_substream *substream,
  237. struct snd_soc_dai *dai)
  238. {
  239. struct omap_mcpdm *mcpdm = snd_soc_dai_get_drvdata(dai);
  240. mutex_lock(&mcpdm->mutex);
  241. if (!dai->active) {
  242. if (omap_mcpdm_active(mcpdm)) {
  243. omap_mcpdm_stop(mcpdm);
  244. omap_mcpdm_close_streams(mcpdm);
  245. }
  246. if (!omap_mcpdm_active(mcpdm))
  247. pm_runtime_put_sync(mcpdm->dev);
  248. }
  249. mutex_unlock(&mcpdm->mutex);
  250. }
  251. static int omap_mcpdm_dai_hw_params(struct snd_pcm_substream *substream,
  252. struct snd_pcm_hw_params *params,
  253. struct snd_soc_dai *dai)
  254. {
  255. struct omap_mcpdm *mcpdm = snd_soc_dai_get_drvdata(dai);
  256. int stream = substream->stream;
  257. struct omap_pcm_dma_data *dma_data;
  258. int channels;
  259. int link_mask = 0;
  260. channels = params_channels(params);
  261. switch (channels) {
  262. case 5:
  263. if (stream == SNDRV_PCM_STREAM_CAPTURE)
  264. /* up to 3 channels for capture */
  265. return -EINVAL;
  266. link_mask |= 1 << 4;
  267. case 4:
  268. if (stream == SNDRV_PCM_STREAM_CAPTURE)
  269. /* up to 3 channels for capture */
  270. return -EINVAL;
  271. link_mask |= 1 << 3;
  272. case 3:
  273. link_mask |= 1 << 2;
  274. case 2:
  275. link_mask |= 1 << 1;
  276. case 1:
  277. link_mask |= 1 << 0;
  278. break;
  279. default:
  280. /* unsupported number of channels */
  281. return -EINVAL;
  282. }
  283. dma_data = &omap_mcpdm_dai_dma_params[stream];
  284. /* Configure McPDM channels, and DMA packet size */
  285. if (stream == SNDRV_PCM_STREAM_PLAYBACK) {
  286. mcpdm->dn_channels = link_mask << 3;
  287. dma_data->packet_size =
  288. (MCPDM_DN_THRES_MAX - mcpdm->dn_threshold) * channels;
  289. } else {
  290. mcpdm->up_channels = link_mask << 0;
  291. dma_data->packet_size = mcpdm->up_threshold * channels;
  292. }
  293. snd_soc_dai_set_dma_data(dai, substream, dma_data);
  294. return 0;
  295. }
  296. static int omap_mcpdm_prepare(struct snd_pcm_substream *substream,
  297. struct snd_soc_dai *dai)
  298. {
  299. struct omap_mcpdm *mcpdm = snd_soc_dai_get_drvdata(dai);
  300. if (!omap_mcpdm_active(mcpdm)) {
  301. omap_mcpdm_start(mcpdm);
  302. omap_mcpdm_reg_dump(mcpdm);
  303. }
  304. return 0;
  305. }
  306. static struct snd_soc_dai_ops omap_mcpdm_dai_ops = {
  307. .startup = omap_mcpdm_dai_startup,
  308. .shutdown = omap_mcpdm_dai_shutdown,
  309. .hw_params = omap_mcpdm_dai_hw_params,
  310. .prepare = omap_mcpdm_prepare,
  311. };
  312. static int omap_mcpdm_probe(struct snd_soc_dai *dai)
  313. {
  314. struct omap_mcpdm *mcpdm = snd_soc_dai_get_drvdata(dai);
  315. int ret;
  316. pm_runtime_enable(mcpdm->dev);
  317. /* Disable lines while request is ongoing */
  318. pm_runtime_get_sync(mcpdm->dev);
  319. omap_mcpdm_write(mcpdm, MCPDM_REG_CTRL, 0x00);
  320. ret = request_irq(mcpdm->irq, omap_mcpdm_irq_handler,
  321. 0, "McPDM", (void *)mcpdm);
  322. pm_runtime_put_sync(mcpdm->dev);
  323. if (ret) {
  324. dev_err(mcpdm->dev, "Request for IRQ failed\n");
  325. pm_runtime_disable(mcpdm->dev);
  326. }
  327. /* Configure McPDM threshold values */
  328. mcpdm->dn_threshold = 2;
  329. mcpdm->up_threshold = MCPDM_UP_THRES_MAX - 3;
  330. return ret;
  331. }
  332. static int omap_mcpdm_remove(struct snd_soc_dai *dai)
  333. {
  334. struct omap_mcpdm *mcpdm = snd_soc_dai_get_drvdata(dai);
  335. free_irq(mcpdm->irq, (void *)mcpdm);
  336. pm_runtime_disable(mcpdm->dev);
  337. return 0;
  338. }
  339. #define OMAP_MCPDM_RATES (SNDRV_PCM_RATE_88200 | SNDRV_PCM_RATE_96000)
  340. #define OMAP_MCPDM_FORMATS SNDRV_PCM_FMTBIT_S32_LE
  341. static struct snd_soc_dai_driver omap_mcpdm_dai = {
  342. .probe = omap_mcpdm_probe,
  343. .remove = omap_mcpdm_remove,
  344. .probe_order = SND_SOC_COMP_ORDER_LATE,
  345. .remove_order = SND_SOC_COMP_ORDER_EARLY,
  346. .playback = {
  347. .channels_min = 1,
  348. .channels_max = 5,
  349. .rates = OMAP_MCPDM_RATES,
  350. .formats = OMAP_MCPDM_FORMATS,
  351. },
  352. .capture = {
  353. .channels_min = 1,
  354. .channels_max = 3,
  355. .rates = OMAP_MCPDM_RATES,
  356. .formats = OMAP_MCPDM_FORMATS,
  357. },
  358. .ops = &omap_mcpdm_dai_ops,
  359. };
  360. void omap_mcpdm_configure_dn_offsets(struct snd_soc_pcm_runtime *rtd,
  361. u8 rx1, u8 rx2)
  362. {
  363. struct omap_mcpdm *mcpdm = snd_soc_dai_get_drvdata(rtd->cpu_dai);
  364. mcpdm->dn_rx_offset = MCPDM_DNOFST_RX1(rx1) | MCPDM_DNOFST_RX2(rx2);
  365. }
  366. EXPORT_SYMBOL_GPL(omap_mcpdm_configure_dn_offsets);
  367. static __devinit int asoc_mcpdm_probe(struct platform_device *pdev)
  368. {
  369. struct omap_mcpdm *mcpdm;
  370. struct resource *res;
  371. int ret = 0;
  372. mcpdm = kzalloc(sizeof(struct omap_mcpdm), GFP_KERNEL);
  373. if (!mcpdm)
  374. return -ENOMEM;
  375. platform_set_drvdata(pdev, mcpdm);
  376. mutex_init(&mcpdm->mutex);
  377. res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
  378. if (res == NULL) {
  379. dev_err(&pdev->dev, "no resource\n");
  380. goto err_res;
  381. }
  382. if (!request_mem_region(res->start, resource_size(res), "McPDM")) {
  383. ret = -EBUSY;
  384. goto err_res;
  385. }
  386. mcpdm->io_base = ioremap(res->start, resource_size(res));
  387. if (!mcpdm->io_base) {
  388. ret = -ENOMEM;
  389. goto err_iomap;
  390. }
  391. mcpdm->irq = platform_get_irq(pdev, 0);
  392. if (mcpdm->irq < 0) {
  393. ret = mcpdm->irq;
  394. goto err_irq;
  395. }
  396. mcpdm->dev = &pdev->dev;
  397. ret = snd_soc_register_dai(&pdev->dev, &omap_mcpdm_dai);
  398. if (!ret)
  399. return 0;
  400. err_irq:
  401. iounmap(mcpdm->io_base);
  402. err_iomap:
  403. release_mem_region(res->start, resource_size(res));
  404. err_res:
  405. kfree(mcpdm);
  406. return ret;
  407. }
  408. static int __devexit asoc_mcpdm_remove(struct platform_device *pdev)
  409. {
  410. struct omap_mcpdm *mcpdm = platform_get_drvdata(pdev);
  411. struct resource *res;
  412. snd_soc_unregister_dai(&pdev->dev);
  413. res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
  414. iounmap(mcpdm->io_base);
  415. release_mem_region(res->start, resource_size(res));
  416. kfree(mcpdm);
  417. return 0;
  418. }
  419. static struct platform_driver asoc_mcpdm_driver = {
  420. .driver = {
  421. .name = "omap-mcpdm",
  422. .owner = THIS_MODULE,
  423. },
  424. .probe = asoc_mcpdm_probe,
  425. .remove = __devexit_p(asoc_mcpdm_remove),
  426. };
  427. static int __init snd_omap_mcpdm_init(void)
  428. {
  429. return platform_driver_register(&asoc_mcpdm_driver);
  430. }
  431. module_init(snd_omap_mcpdm_init);
  432. static void __exit snd_omap_mcpdm_exit(void)
  433. {
  434. platform_driver_unregister(&asoc_mcpdm_driver);
  435. }
  436. module_exit(snd_omap_mcpdm_exit);
  437. MODULE_AUTHOR("Misael Lopez Cruz <misael.lopez@ti.com>");
  438. MODULE_DESCRIPTION("OMAP PDM SoC Interface");
  439. MODULE_LICENSE("GPL");