wm8958-dsp2.c 27 KB

1234567891011121314151617181920212223242526272829303132333435363738394041424344454647484950515253545556575859606162636465666768697071727374757677787980818283848586878889909192939495969798991001011021031041051061071081091101111121131141151161171181191201211221231241251261271281291301311321331341351361371381391401411421431441451461471481491501511521531541551561571581591601611621631641651661671681691701711721731741751761771781791801811821831841851861871881891901911921931941951961971981992002012022032042052062072082092102112122132142152162172182192202212222232242252262272282292302312322332342352362372382392402412422432442452462472482492502512522532542552562572582592602612622632642652662672682692702712722732742752762772782792802812822832842852862872882892902912922932942952962972982993003013023033043053063073083093103113123133143153163173183193203213223233243253263273283293303313323333343353363373383393403413423433443453463473483493503513523533543553563573583593603613623633643653663673683693703713723733743753763773783793803813823833843853863873883893903913923933943953963973983994004014024034044054064074084094104114124134144154164174184194204214224234244254264274284294304314324334344354364374384394404414424434444454464474484494504514524534544554564574584594604614624634644654664674684694704714724734744754764774784794804814824834844854864874884894904914924934944954964974984995005015025035045055065075085095105115125135145155165175185195205215225235245255265275285295305315325335345355365375385395405415425435445455465475485495505515525535545555565575585595605615625635645655665675685695705715725735745755765775785795805815825835845855865875885895905915925935945955965975985996006016026036046056066076086096106116126136146156166176186196206216226236246256266276286296306316326336346356366376386396406416426436446456466476486496506516526536546556566576586596606616626636646656666676686696706716726736746756766776786796806816826836846856866876886896906916926936946956966976986997007017027037047057067077087097107117127137147157167177187197207217227237247257267277287297307317327337347357367377387397407417427437447457467477487497507517527537547557567577587597607617627637647657667677687697707717727737747757767777787797807817827837847857867877887897907917927937947957967977987998008018028038048058068078088098108118128138148158168178188198208218228238248258268278288298308318328338348358368378388398408418428438448458468478488498508518528538548558568578588598608618628638648658668678688698708718728738748758768778788798808818828838848858868878888898908918928938948958968978988999009019029039049059069079089099109119129139149159169179189199209219229239249259269279289299309319329339349359369379389399409419429439449459469479489499509519529539549559569579589599609619629639649659669679689699709719729739749759769779789799809819829839849859869879889899909919929939949959969979989991000100110021003100410051006100710081009101010111012101310141015101610171018101910201021102210231024102510261027102810291030103110321033103410351036103710381039104010411042104310441045104610471048104910501051
  1. /*
  2. * wm8958-dsp2.c -- WM8958 DSP2 support
  3. *
  4. * Copyright 2011 Wolfson Microelectronics plc
  5. *
  6. * Author: Mark Brown <broonie@opensource.wolfsonmicro.com>
  7. *
  8. * This program is free software; you can redistribute it and/or modify
  9. * it under the terms of the GNU General Public License version 2 as
  10. * published by the Free Software Foundation.
  11. */
  12. #include <linux/module.h>
  13. #include <linux/moduleparam.h>
  14. #include <linux/init.h>
  15. #include <linux/delay.h>
  16. #include <linux/pm.h>
  17. #include <linux/i2c.h>
  18. #include <linux/platform_device.h>
  19. #include <linux/slab.h>
  20. #include <sound/soc.h>
  21. #include <sound/initval.h>
  22. #include <sound/tlv.h>
  23. #include <trace/events/asoc.h>
  24. #include <linux/mfd/wm8994/core.h>
  25. #include <linux/mfd/wm8994/registers.h>
  26. #include <linux/mfd/wm8994/pdata.h>
  27. #include <linux/mfd/wm8994/gpio.h>
  28. #include "wm8994.h"
  29. #define WM_FW_BLOCK_INFO 0xff
  30. #define WM_FW_BLOCK_PM 0x00
  31. #define WM_FW_BLOCK_X 0x01
  32. #define WM_FW_BLOCK_Y 0x02
  33. #define WM_FW_BLOCK_Z 0x03
  34. #define WM_FW_BLOCK_I 0x06
  35. #define WM_FW_BLOCK_A 0x08
  36. #define WM_FW_BLOCK_C 0x0c
  37. static int wm8958_dsp2_fw(struct snd_soc_codec *codec, const char *name,
  38. const struct firmware *fw, bool check)
  39. {
  40. struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
  41. u64 data64;
  42. u32 data32;
  43. const u8 *data;
  44. char *str;
  45. size_t block_len, len;
  46. int ret = 0;
  47. /* Suppress unneeded downloads */
  48. if (wm8994->cur_fw == fw)
  49. return 0;
  50. if (fw->size < 32) {
  51. dev_err(codec->dev, "%s: firmware too short\n", name);
  52. goto err;
  53. }
  54. if (memcmp(fw->data, "WMFW", 4) != 0) {
  55. dev_err(codec->dev, "%s: firmware has bad file magic %08x\n",
  56. name, data32);
  57. goto err;
  58. }
  59. memcpy(&data32, fw->data + 4, sizeof(data32));
  60. len = be32_to_cpu(data32);
  61. memcpy(&data32, fw->data + 8, sizeof(data32));
  62. data32 = be32_to_cpu(data32);
  63. if ((data32 >> 24) & 0xff) {
  64. dev_err(codec->dev, "%s: unsupported firmware version %d\n",
  65. name, (data32 >> 24) & 0xff);
  66. goto err;
  67. }
  68. if ((data32 & 0xffff) != 8958) {
  69. dev_err(codec->dev, "%s: unsupported target device %d\n",
  70. name, data32 & 0xffff);
  71. goto err;
  72. }
  73. if (((data32 >> 16) & 0xff) != 0xc) {
  74. dev_err(codec->dev, "%s: unsupported target core %d\n",
  75. name, (data32 >> 16) & 0xff);
  76. goto err;
  77. }
  78. if (check) {
  79. memcpy(&data64, fw->data + 24, sizeof(u64));
  80. dev_info(codec->dev, "%s timestamp %llx\n",
  81. name, be64_to_cpu(data64));
  82. } else {
  83. snd_soc_write(codec, 0x102, 0x2);
  84. snd_soc_write(codec, 0x900, 0x2);
  85. }
  86. data = fw->data + len;
  87. len = fw->size - len;
  88. while (len) {
  89. if (len < 12) {
  90. dev_err(codec->dev, "%s short data block of %zd\n",
  91. name, len);
  92. goto err;
  93. }
  94. memcpy(&data32, data + 4, sizeof(data32));
  95. block_len = be32_to_cpu(data32);
  96. if (block_len + 8 > len) {
  97. dev_err(codec->dev, "%zd byte block longer than file\n",
  98. block_len);
  99. goto err;
  100. }
  101. if (block_len == 0) {
  102. dev_err(codec->dev, "Zero length block\n");
  103. goto err;
  104. }
  105. memcpy(&data32, data, sizeof(data32));
  106. data32 = be32_to_cpu(data32);
  107. switch ((data32 >> 24) & 0xff) {
  108. case WM_FW_BLOCK_INFO:
  109. /* Informational text */
  110. if (!check)
  111. break;
  112. str = kzalloc(block_len + 1, GFP_KERNEL);
  113. if (str) {
  114. memcpy(str, data + 8, block_len);
  115. dev_info(codec->dev, "%s: %s\n", name, str);
  116. kfree(str);
  117. } else {
  118. dev_err(codec->dev, "Out of memory\n");
  119. }
  120. break;
  121. case WM_FW_BLOCK_PM:
  122. case WM_FW_BLOCK_X:
  123. case WM_FW_BLOCK_Y:
  124. case WM_FW_BLOCK_Z:
  125. case WM_FW_BLOCK_I:
  126. case WM_FW_BLOCK_A:
  127. case WM_FW_BLOCK_C:
  128. dev_dbg(codec->dev, "%s: %zd bytes of %x@%x\n", name,
  129. block_len, (data32 >> 24) & 0xff,
  130. data32 & 0xffffff);
  131. if (check)
  132. break;
  133. data32 &= 0xffffff;
  134. wm8994_bulk_write(codec->control_data,
  135. data32 & 0xffffff,
  136. block_len / 2,
  137. (void *)(data + 8));
  138. break;
  139. default:
  140. dev_warn(codec->dev, "%s: unknown block type %d\n",
  141. name, (data32 >> 24) & 0xff);
  142. break;
  143. }
  144. /* Round up to the next 32 bit word */
  145. block_len += block_len % 4;
  146. data += block_len + 8;
  147. len -= block_len + 8;
  148. }
  149. if (!check) {
  150. dev_dbg(codec->dev, "%s: download done\n", name);
  151. wm8994->cur_fw = fw;
  152. } else {
  153. dev_info(codec->dev, "%s: got firmware\n", name);
  154. }
  155. goto ok;
  156. err:
  157. ret = -EINVAL;
  158. ok:
  159. if (!check) {
  160. snd_soc_write(codec, 0x900, 0x0);
  161. snd_soc_write(codec, 0x102, 0x0);
  162. }
  163. return ret;
  164. }
  165. static void wm8958_dsp_start_mbc(struct snd_soc_codec *codec, int path)
  166. {
  167. struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
  168. struct wm8994_pdata *pdata = wm8994->pdata;
  169. int i;
  170. /* If the DSP is already running then noop */
  171. if (snd_soc_read(codec, WM8958_DSP2_PROGRAM) & WM8958_DSP2_ENA)
  172. return;
  173. /* If we have MBC firmware download it */
  174. if (wm8994->mbc)
  175. wm8958_dsp2_fw(codec, "MBC", wm8994->mbc, false);
  176. snd_soc_update_bits(codec, WM8958_DSP2_PROGRAM,
  177. WM8958_DSP2_ENA, WM8958_DSP2_ENA);
  178. /* If we've got user supplied MBC settings use them */
  179. if (pdata && pdata->num_mbc_cfgs) {
  180. struct wm8958_mbc_cfg *cfg
  181. = &pdata->mbc_cfgs[wm8994->mbc_cfg];
  182. for (i = 0; i < ARRAY_SIZE(cfg->coeff_regs); i++)
  183. snd_soc_write(codec, i + WM8958_MBC_BAND_1_K_1,
  184. cfg->coeff_regs[i]);
  185. for (i = 0; i < ARRAY_SIZE(cfg->cutoff_regs); i++)
  186. snd_soc_write(codec,
  187. i + WM8958_MBC_BAND_2_LOWER_CUTOFF_C1_1,
  188. cfg->cutoff_regs[i]);
  189. }
  190. /* Run the DSP */
  191. snd_soc_write(codec, WM8958_DSP2_EXECCONTROL,
  192. WM8958_DSP2_RUNR);
  193. /* And we're off! */
  194. snd_soc_update_bits(codec, WM8958_DSP2_CONFIG,
  195. WM8958_MBC_ENA |
  196. WM8958_MBC_SEL_MASK,
  197. path << WM8958_MBC_SEL_SHIFT |
  198. WM8958_MBC_ENA);
  199. }
  200. static void wm8958_dsp_start_vss(struct snd_soc_codec *codec, int path)
  201. {
  202. struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
  203. struct wm8994_pdata *pdata = wm8994->pdata;
  204. int i, ena;
  205. if (wm8994->mbc_vss)
  206. wm8958_dsp2_fw(codec, "MBC+VSS", wm8994->mbc_vss, false);
  207. snd_soc_update_bits(codec, WM8958_DSP2_PROGRAM,
  208. WM8958_DSP2_ENA, WM8958_DSP2_ENA);
  209. /* If we've got user supplied settings use them */
  210. if (pdata && pdata->num_mbc_cfgs) {
  211. struct wm8958_mbc_cfg *cfg
  212. = &pdata->mbc_cfgs[wm8994->mbc_cfg];
  213. for (i = 0; i < ARRAY_SIZE(cfg->combined_regs); i++)
  214. snd_soc_write(codec, i + 0x2800,
  215. cfg->combined_regs[i]);
  216. }
  217. if (pdata && pdata->num_vss_cfgs) {
  218. struct wm8958_vss_cfg *cfg
  219. = &pdata->vss_cfgs[wm8994->vss_cfg];
  220. for (i = 0; i < ARRAY_SIZE(cfg->regs); i++)
  221. snd_soc_write(codec, i + 0x2600, cfg->regs[i]);
  222. }
  223. if (pdata && pdata->num_vss_hpf_cfgs) {
  224. struct wm8958_vss_hpf_cfg *cfg
  225. = &pdata->vss_hpf_cfgs[wm8994->vss_hpf_cfg];
  226. for (i = 0; i < ARRAY_SIZE(cfg->regs); i++)
  227. snd_soc_write(codec, i + 0x2400, cfg->regs[i]);
  228. }
  229. /* Run the DSP */
  230. snd_soc_write(codec, WM8958_DSP2_EXECCONTROL,
  231. WM8958_DSP2_RUNR);
  232. /* Enable the algorithms we've selected */
  233. ena = 0;
  234. if (wm8994->mbc_ena[path])
  235. ena |= 0x8;
  236. if (wm8994->hpf2_ena[path])
  237. ena |= 0x4;
  238. if (wm8994->hpf1_ena[path])
  239. ena |= 0x2;
  240. if (wm8994->vss_ena[path])
  241. ena |= 0x1;
  242. snd_soc_write(codec, 0x2201, ena);
  243. /* Switch the DSP into the data path */
  244. snd_soc_update_bits(codec, WM8958_DSP2_CONFIG,
  245. WM8958_MBC_SEL_MASK | WM8958_MBC_ENA,
  246. path << WM8958_MBC_SEL_SHIFT | WM8958_MBC_ENA);
  247. }
  248. static void wm8958_dsp_start_enh_eq(struct snd_soc_codec *codec, int path)
  249. {
  250. struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
  251. struct wm8994_pdata *pdata = wm8994->pdata;
  252. int i;
  253. wm8958_dsp2_fw(codec, "ENH_EQ", wm8994->enh_eq, false);
  254. snd_soc_update_bits(codec, WM8958_DSP2_PROGRAM,
  255. WM8958_DSP2_ENA, WM8958_DSP2_ENA);
  256. /* If we've got user supplied settings use them */
  257. if (pdata && pdata->num_enh_eq_cfgs) {
  258. struct wm8958_enh_eq_cfg *cfg
  259. = &pdata->enh_eq_cfgs[wm8994->enh_eq_cfg];
  260. for (i = 0; i < ARRAY_SIZE(cfg->regs); i++)
  261. snd_soc_write(codec, i + 0x2200,
  262. cfg->regs[i]);
  263. }
  264. /* Run the DSP */
  265. snd_soc_write(codec, WM8958_DSP2_EXECCONTROL,
  266. WM8958_DSP2_RUNR);
  267. /* Switch the DSP into the data path */
  268. snd_soc_update_bits(codec, WM8958_DSP2_CONFIG,
  269. WM8958_MBC_SEL_MASK | WM8958_MBC_ENA,
  270. path << WM8958_MBC_SEL_SHIFT | WM8958_MBC_ENA);
  271. }
  272. static void wm8958_dsp_apply(struct snd_soc_codec *codec, int path, int start)
  273. {
  274. struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
  275. int pwr_reg = snd_soc_read(codec, WM8994_POWER_MANAGEMENT_5);
  276. int ena, reg, aif;
  277. switch (path) {
  278. case 0:
  279. pwr_reg &= (WM8994_AIF1DAC1L_ENA | WM8994_AIF1DAC1R_ENA);
  280. aif = 0;
  281. break;
  282. case 1:
  283. pwr_reg &= (WM8994_AIF1DAC2L_ENA | WM8994_AIF1DAC2R_ENA);
  284. aif = 0;
  285. break;
  286. case 2:
  287. pwr_reg &= (WM8994_AIF2DACL_ENA | WM8994_AIF2DACR_ENA);
  288. aif = 1;
  289. break;
  290. default:
  291. BUG();
  292. return;
  293. }
  294. /* Do we have both an active AIF and an active algorithm? */
  295. ena = wm8994->mbc_ena[path] || wm8994->vss_ena[path] ||
  296. wm8994->hpf1_ena[path] || wm8994->hpf2_ena[path] ||
  297. wm8994->enh_eq_ena[path];
  298. if (!pwr_reg)
  299. ena = 0;
  300. reg = snd_soc_read(codec, WM8958_DSP2_PROGRAM);
  301. dev_dbg(codec->dev, "DSP path %d %d startup: %d, power: %x, DSP: %x\n",
  302. path, wm8994->dsp_active, start, pwr_reg, reg);
  303. if (start && ena) {
  304. /* If the DSP is already running then noop */
  305. if (reg & WM8958_DSP2_ENA)
  306. return;
  307. /* If either AIFnCLK is not yet enabled postpone */
  308. if (!(snd_soc_read(codec, WM8994_AIF1_CLOCKING_1)
  309. & WM8994_AIF1CLK_ENA_MASK) &&
  310. !(snd_soc_read(codec, WM8994_AIF2_CLOCKING_1)
  311. & WM8994_AIF2CLK_ENA_MASK))
  312. return;
  313. /* Switch the clock over to the appropriate AIF */
  314. snd_soc_update_bits(codec, WM8994_CLOCKING_1,
  315. WM8958_DSP2CLK_SRC | WM8958_DSP2CLK_ENA,
  316. aif << WM8958_DSP2CLK_SRC_SHIFT |
  317. WM8958_DSP2CLK_ENA);
  318. if (wm8994->enh_eq_ena[path])
  319. wm8958_dsp_start_enh_eq(codec, path);
  320. else if (wm8994->vss_ena[path] || wm8994->hpf1_ena[path] ||
  321. wm8994->hpf2_ena[path])
  322. wm8958_dsp_start_vss(codec, path);
  323. else if (wm8994->mbc_ena[path])
  324. wm8958_dsp_start_mbc(codec, path);
  325. wm8994->dsp_active = path;
  326. dev_dbg(codec->dev, "DSP running in path %d\n", path);
  327. }
  328. if (!start && wm8994->dsp_active == path) {
  329. /* If the DSP is already stopped then noop */
  330. if (!(reg & WM8958_DSP2_ENA))
  331. return;
  332. snd_soc_update_bits(codec, WM8958_DSP2_CONFIG,
  333. WM8958_MBC_ENA, 0);
  334. snd_soc_write(codec, WM8958_DSP2_EXECCONTROL,
  335. WM8958_DSP2_STOP);
  336. snd_soc_update_bits(codec, WM8958_DSP2_PROGRAM,
  337. WM8958_DSP2_ENA, 0);
  338. snd_soc_update_bits(codec, WM8994_CLOCKING_1,
  339. WM8958_DSP2CLK_ENA, 0);
  340. wm8994->dsp_active = -1;
  341. dev_dbg(codec->dev, "DSP stopped\n");
  342. }
  343. }
  344. int wm8958_aif_ev(struct snd_soc_dapm_widget *w,
  345. struct snd_kcontrol *kcontrol, int event)
  346. {
  347. struct snd_soc_codec *codec = w->codec;
  348. int i;
  349. switch (event) {
  350. case SND_SOC_DAPM_POST_PMU:
  351. case SND_SOC_DAPM_PRE_PMU:
  352. for (i = 0; i < 3; i++)
  353. wm8958_dsp_apply(codec, i, 1);
  354. break;
  355. case SND_SOC_DAPM_POST_PMD:
  356. case SND_SOC_DAPM_PRE_PMD:
  357. for (i = 0; i < 3; i++)
  358. wm8958_dsp_apply(codec, i, 0);
  359. break;
  360. }
  361. return 0;
  362. }
  363. /* Check if DSP2 is in use on another AIF */
  364. static int wm8958_dsp2_busy(struct wm8994_priv *wm8994, int aif)
  365. {
  366. int i;
  367. for (i = 0; i < ARRAY_SIZE(wm8994->mbc_ena); i++) {
  368. if (i == aif)
  369. continue;
  370. if (wm8994->mbc_ena[i] || wm8994->vss_ena[i] ||
  371. wm8994->hpf1_ena[i] || wm8994->hpf2_ena[i])
  372. return 1;
  373. }
  374. return 0;
  375. }
  376. static int wm8958_put_mbc_enum(struct snd_kcontrol *kcontrol,
  377. struct snd_ctl_elem_value *ucontrol)
  378. {
  379. struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
  380. struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
  381. struct wm8994_pdata *pdata = wm8994->pdata;
  382. int value = ucontrol->value.integer.value[0];
  383. int reg;
  384. /* Don't allow on the fly reconfiguration */
  385. reg = snd_soc_read(codec, WM8994_CLOCKING_1);
  386. if (reg < 0 || reg & WM8958_DSP2CLK_ENA)
  387. return -EBUSY;
  388. if (value >= pdata->num_mbc_cfgs)
  389. return -EINVAL;
  390. wm8994->mbc_cfg = value;
  391. return 0;
  392. }
  393. static int wm8958_get_mbc_enum(struct snd_kcontrol *kcontrol,
  394. struct snd_ctl_elem_value *ucontrol)
  395. {
  396. struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
  397. struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
  398. ucontrol->value.enumerated.item[0] = wm8994->mbc_cfg;
  399. return 0;
  400. }
  401. static int wm8958_mbc_info(struct snd_kcontrol *kcontrol,
  402. struct snd_ctl_elem_info *uinfo)
  403. {
  404. uinfo->type = SNDRV_CTL_ELEM_TYPE_BOOLEAN;
  405. uinfo->count = 1;
  406. uinfo->value.integer.min = 0;
  407. uinfo->value.integer.max = 1;
  408. return 0;
  409. }
  410. static int wm8958_mbc_get(struct snd_kcontrol *kcontrol,
  411. struct snd_ctl_elem_value *ucontrol)
  412. {
  413. int mbc = kcontrol->private_value;
  414. struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
  415. struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
  416. ucontrol->value.integer.value[0] = wm8994->mbc_ena[mbc];
  417. return 0;
  418. }
  419. static int wm8958_mbc_put(struct snd_kcontrol *kcontrol,
  420. struct snd_ctl_elem_value *ucontrol)
  421. {
  422. int mbc = kcontrol->private_value;
  423. struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
  424. struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
  425. if (wm8994->mbc_ena[mbc] == ucontrol->value.integer.value[0])
  426. return 0;
  427. if (ucontrol->value.integer.value[0] > 1)
  428. return -EINVAL;
  429. if (wm8958_dsp2_busy(wm8994, mbc)) {
  430. dev_dbg(codec->dev, "DSP2 active on %d already\n", mbc);
  431. return -EBUSY;
  432. }
  433. if (wm8994->enh_eq_ena[mbc])
  434. return -EBUSY;
  435. wm8994->mbc_ena[mbc] = ucontrol->value.integer.value[0];
  436. wm8958_dsp_apply(codec, mbc, wm8994->mbc_ena[mbc]);
  437. return 0;
  438. }
  439. #define WM8958_MBC_SWITCH(xname, xval) {\
  440. .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = (xname), \
  441. .access = SNDRV_CTL_ELEM_ACCESS_READWRITE,\
  442. .info = wm8958_mbc_info, \
  443. .get = wm8958_mbc_get, .put = wm8958_mbc_put, \
  444. .private_value = xval }
  445. static int wm8958_put_vss_enum(struct snd_kcontrol *kcontrol,
  446. struct snd_ctl_elem_value *ucontrol)
  447. {
  448. struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
  449. struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
  450. struct wm8994_pdata *pdata = wm8994->pdata;
  451. int value = ucontrol->value.integer.value[0];
  452. int reg;
  453. /* Don't allow on the fly reconfiguration */
  454. reg = snd_soc_read(codec, WM8994_CLOCKING_1);
  455. if (reg < 0 || reg & WM8958_DSP2CLK_ENA)
  456. return -EBUSY;
  457. if (value >= pdata->num_vss_cfgs)
  458. return -EINVAL;
  459. wm8994->vss_cfg = value;
  460. return 0;
  461. }
  462. static int wm8958_get_vss_enum(struct snd_kcontrol *kcontrol,
  463. struct snd_ctl_elem_value *ucontrol)
  464. {
  465. struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
  466. struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
  467. ucontrol->value.enumerated.item[0] = wm8994->vss_cfg;
  468. return 0;
  469. }
  470. static int wm8958_put_vss_hpf_enum(struct snd_kcontrol *kcontrol,
  471. struct snd_ctl_elem_value *ucontrol)
  472. {
  473. struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
  474. struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
  475. struct wm8994_pdata *pdata = wm8994->pdata;
  476. int value = ucontrol->value.integer.value[0];
  477. int reg;
  478. /* Don't allow on the fly reconfiguration */
  479. reg = snd_soc_read(codec, WM8994_CLOCKING_1);
  480. if (reg < 0 || reg & WM8958_DSP2CLK_ENA)
  481. return -EBUSY;
  482. if (value >= pdata->num_vss_hpf_cfgs)
  483. return -EINVAL;
  484. wm8994->vss_hpf_cfg = value;
  485. return 0;
  486. }
  487. static int wm8958_get_vss_hpf_enum(struct snd_kcontrol *kcontrol,
  488. struct snd_ctl_elem_value *ucontrol)
  489. {
  490. struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
  491. struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
  492. ucontrol->value.enumerated.item[0] = wm8994->vss_hpf_cfg;
  493. return 0;
  494. }
  495. static int wm8958_vss_info(struct snd_kcontrol *kcontrol,
  496. struct snd_ctl_elem_info *uinfo)
  497. {
  498. uinfo->type = SNDRV_CTL_ELEM_TYPE_BOOLEAN;
  499. uinfo->count = 1;
  500. uinfo->value.integer.min = 0;
  501. uinfo->value.integer.max = 1;
  502. return 0;
  503. }
  504. static int wm8958_vss_get(struct snd_kcontrol *kcontrol,
  505. struct snd_ctl_elem_value *ucontrol)
  506. {
  507. int vss = kcontrol->private_value;
  508. struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
  509. struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
  510. ucontrol->value.integer.value[0] = wm8994->vss_ena[vss];
  511. return 0;
  512. }
  513. static int wm8958_vss_put(struct snd_kcontrol *kcontrol,
  514. struct snd_ctl_elem_value *ucontrol)
  515. {
  516. int vss = kcontrol->private_value;
  517. struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
  518. struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
  519. if (wm8994->vss_ena[vss] == ucontrol->value.integer.value[0])
  520. return 0;
  521. if (ucontrol->value.integer.value[0] > 1)
  522. return -EINVAL;
  523. if (!wm8994->mbc_vss)
  524. return -ENODEV;
  525. if (wm8958_dsp2_busy(wm8994, vss)) {
  526. dev_dbg(codec->dev, "DSP2 active on %d already\n", vss);
  527. return -EBUSY;
  528. }
  529. if (wm8994->enh_eq_ena[vss])
  530. return -EBUSY;
  531. wm8994->vss_ena[vss] = ucontrol->value.integer.value[0];
  532. wm8958_dsp_apply(codec, vss, wm8994->vss_ena[vss]);
  533. return 0;
  534. }
  535. #define WM8958_VSS_SWITCH(xname, xval) {\
  536. .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = (xname), \
  537. .access = SNDRV_CTL_ELEM_ACCESS_READWRITE,\
  538. .info = wm8958_vss_info, \
  539. .get = wm8958_vss_get, .put = wm8958_vss_put, \
  540. .private_value = xval }
  541. static int wm8958_hpf_info(struct snd_kcontrol *kcontrol,
  542. struct snd_ctl_elem_info *uinfo)
  543. {
  544. uinfo->type = SNDRV_CTL_ELEM_TYPE_BOOLEAN;
  545. uinfo->count = 1;
  546. uinfo->value.integer.min = 0;
  547. uinfo->value.integer.max = 1;
  548. return 0;
  549. }
  550. static int wm8958_hpf_get(struct snd_kcontrol *kcontrol,
  551. struct snd_ctl_elem_value *ucontrol)
  552. {
  553. int hpf = kcontrol->private_value;
  554. struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
  555. struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
  556. if (hpf < 3)
  557. ucontrol->value.integer.value[0] = wm8994->hpf1_ena[hpf % 3];
  558. else
  559. ucontrol->value.integer.value[0] = wm8994->hpf2_ena[hpf % 3];
  560. return 0;
  561. }
  562. static int wm8958_hpf_put(struct snd_kcontrol *kcontrol,
  563. struct snd_ctl_elem_value *ucontrol)
  564. {
  565. int hpf = kcontrol->private_value;
  566. struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
  567. struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
  568. if (hpf < 3) {
  569. if (wm8994->hpf1_ena[hpf % 3] ==
  570. ucontrol->value.integer.value[0])
  571. return 0;
  572. } else {
  573. if (wm8994->hpf2_ena[hpf % 3] ==
  574. ucontrol->value.integer.value[0])
  575. return 0;
  576. }
  577. if (ucontrol->value.integer.value[0] > 1)
  578. return -EINVAL;
  579. if (!wm8994->mbc_vss)
  580. return -ENODEV;
  581. if (wm8958_dsp2_busy(wm8994, hpf % 3)) {
  582. dev_dbg(codec->dev, "DSP2 active on %d already\n", hpf);
  583. return -EBUSY;
  584. }
  585. if (wm8994->enh_eq_ena[hpf % 3])
  586. return -EBUSY;
  587. if (hpf < 3)
  588. wm8994->hpf1_ena[hpf % 3] = ucontrol->value.integer.value[0];
  589. else
  590. wm8994->hpf2_ena[hpf % 3] = ucontrol->value.integer.value[0];
  591. wm8958_dsp_apply(codec, hpf % 3, ucontrol->value.integer.value[0]);
  592. return 0;
  593. }
  594. #define WM8958_HPF_SWITCH(xname, xval) {\
  595. .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = (xname), \
  596. .access = SNDRV_CTL_ELEM_ACCESS_READWRITE,\
  597. .info = wm8958_hpf_info, \
  598. .get = wm8958_hpf_get, .put = wm8958_hpf_put, \
  599. .private_value = xval }
  600. static int wm8958_put_enh_eq_enum(struct snd_kcontrol *kcontrol,
  601. struct snd_ctl_elem_value *ucontrol)
  602. {
  603. struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
  604. struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
  605. struct wm8994_pdata *pdata = wm8994->pdata;
  606. int value = ucontrol->value.integer.value[0];
  607. int reg;
  608. /* Don't allow on the fly reconfiguration */
  609. reg = snd_soc_read(codec, WM8994_CLOCKING_1);
  610. if (reg < 0 || reg & WM8958_DSP2CLK_ENA)
  611. return -EBUSY;
  612. if (value >= pdata->num_enh_eq_cfgs)
  613. return -EINVAL;
  614. wm8994->enh_eq_cfg = value;
  615. return 0;
  616. }
  617. static int wm8958_get_enh_eq_enum(struct snd_kcontrol *kcontrol,
  618. struct snd_ctl_elem_value *ucontrol)
  619. {
  620. struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
  621. struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
  622. ucontrol->value.enumerated.item[0] = wm8994->enh_eq_cfg;
  623. return 0;
  624. }
  625. static int wm8958_enh_eq_info(struct snd_kcontrol *kcontrol,
  626. struct snd_ctl_elem_info *uinfo)
  627. {
  628. uinfo->type = SNDRV_CTL_ELEM_TYPE_BOOLEAN;
  629. uinfo->count = 1;
  630. uinfo->value.integer.min = 0;
  631. uinfo->value.integer.max = 1;
  632. return 0;
  633. }
  634. static int wm8958_enh_eq_get(struct snd_kcontrol *kcontrol,
  635. struct snd_ctl_elem_value *ucontrol)
  636. {
  637. int eq = kcontrol->private_value;
  638. struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
  639. struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
  640. ucontrol->value.integer.value[0] = wm8994->enh_eq_ena[eq];
  641. return 0;
  642. }
  643. static int wm8958_enh_eq_put(struct snd_kcontrol *kcontrol,
  644. struct snd_ctl_elem_value *ucontrol)
  645. {
  646. int eq = kcontrol->private_value;
  647. struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
  648. struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
  649. if (wm8994->enh_eq_ena[eq] == ucontrol->value.integer.value[0])
  650. return 0;
  651. if (ucontrol->value.integer.value[0] > 1)
  652. return -EINVAL;
  653. if (!wm8994->enh_eq)
  654. return -ENODEV;
  655. if (wm8958_dsp2_busy(wm8994, eq)) {
  656. dev_dbg(codec->dev, "DSP2 active on %d already\n", eq);
  657. return -EBUSY;
  658. }
  659. if (wm8994->mbc_ena[eq] || wm8994->vss_ena[eq] ||
  660. wm8994->hpf1_ena[eq] || wm8994->hpf2_ena[eq])
  661. return -EBUSY;
  662. wm8994->enh_eq_ena[eq] = ucontrol->value.integer.value[0];
  663. wm8958_dsp_apply(codec, eq, ucontrol->value.integer.value[0]);
  664. return 0;
  665. }
  666. #define WM8958_ENH_EQ_SWITCH(xname, xval) {\
  667. .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = (xname), \
  668. .access = SNDRV_CTL_ELEM_ACCESS_READWRITE,\
  669. .info = wm8958_enh_eq_info, \
  670. .get = wm8958_enh_eq_get, .put = wm8958_enh_eq_put, \
  671. .private_value = xval }
  672. static const struct snd_kcontrol_new wm8958_mbc_snd_controls[] = {
  673. WM8958_MBC_SWITCH("AIF1DAC1 MBC Switch", 0),
  674. WM8958_MBC_SWITCH("AIF1DAC2 MBC Switch", 1),
  675. WM8958_MBC_SWITCH("AIF2DAC MBC Switch", 2),
  676. };
  677. static const struct snd_kcontrol_new wm8958_vss_snd_controls[] = {
  678. WM8958_VSS_SWITCH("AIF1DAC1 VSS Switch", 0),
  679. WM8958_VSS_SWITCH("AIF1DAC2 VSS Switch", 1),
  680. WM8958_VSS_SWITCH("AIF2DAC VSS Switch", 2),
  681. WM8958_HPF_SWITCH("AIF1DAC1 HPF1 Switch", 0),
  682. WM8958_HPF_SWITCH("AIF1DAC2 HPF1 Switch", 1),
  683. WM8958_HPF_SWITCH("AIF2DAC HPF1 Switch", 2),
  684. WM8958_HPF_SWITCH("AIF1DAC1 HPF2 Switch", 3),
  685. WM8958_HPF_SWITCH("AIF1DAC2 HPF2 Switch", 4),
  686. WM8958_HPF_SWITCH("AIF2DAC HPF2 Switch", 5),
  687. };
  688. static const struct snd_kcontrol_new wm8958_enh_eq_snd_controls[] = {
  689. WM8958_ENH_EQ_SWITCH("AIF1DAC1 Enhanced EQ Switch", 0),
  690. WM8958_ENH_EQ_SWITCH("AIF1DAC2 Enhanced EQ Switch", 1),
  691. WM8958_ENH_EQ_SWITCH("AIF2DAC Enhanced EQ Switch", 2),
  692. };
  693. static void wm8958_enh_eq_loaded(const struct firmware *fw, void *context)
  694. {
  695. struct snd_soc_codec *codec = context;
  696. struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
  697. if (fw && (wm8958_dsp2_fw(codec, "ENH_EQ", fw, true) == 0)) {
  698. mutex_lock(&codec->mutex);
  699. wm8994->enh_eq = fw;
  700. mutex_unlock(&codec->mutex);
  701. }
  702. }
  703. static void wm8958_mbc_vss_loaded(const struct firmware *fw, void *context)
  704. {
  705. struct snd_soc_codec *codec = context;
  706. struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
  707. if (fw && (wm8958_dsp2_fw(codec, "MBC+VSS", fw, true) == 0)) {
  708. mutex_lock(&codec->mutex);
  709. wm8994->mbc_vss = fw;
  710. mutex_unlock(&codec->mutex);
  711. }
  712. /* We can't have more than one request outstanding at once so
  713. * we daisy chain.
  714. */
  715. request_firmware_nowait(THIS_MODULE, FW_ACTION_HOTPLUG,
  716. "wm8958_enh_eq.wfw", codec->dev, GFP_KERNEL,
  717. codec, wm8958_enh_eq_loaded);
  718. }
  719. static void wm8958_mbc_loaded(const struct firmware *fw, void *context)
  720. {
  721. struct snd_soc_codec *codec = context;
  722. struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
  723. if (wm8958_dsp2_fw(codec, "MBC", fw, true) != 0)
  724. return;
  725. mutex_lock(&codec->mutex);
  726. wm8994->mbc = fw;
  727. mutex_unlock(&codec->mutex);
  728. /* We can't have more than one request outstanding at once so
  729. * we daisy chain.
  730. */
  731. request_firmware_nowait(THIS_MODULE, FW_ACTION_HOTPLUG,
  732. "wm8958_mbc_vss.wfw", codec->dev, GFP_KERNEL,
  733. codec, wm8958_mbc_vss_loaded);
  734. }
  735. void wm8958_dsp2_init(struct snd_soc_codec *codec)
  736. {
  737. struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
  738. struct wm8994_pdata *pdata = wm8994->pdata;
  739. int ret, i;
  740. wm8994->dsp_active = -1;
  741. snd_soc_add_controls(codec, wm8958_mbc_snd_controls,
  742. ARRAY_SIZE(wm8958_mbc_snd_controls));
  743. snd_soc_add_controls(codec, wm8958_vss_snd_controls,
  744. ARRAY_SIZE(wm8958_vss_snd_controls));
  745. snd_soc_add_controls(codec, wm8958_enh_eq_snd_controls,
  746. ARRAY_SIZE(wm8958_enh_eq_snd_controls));
  747. /* We don't *require* firmware and don't want to delay boot */
  748. request_firmware_nowait(THIS_MODULE, FW_ACTION_HOTPLUG,
  749. "wm8958_mbc.wfw", codec->dev, GFP_KERNEL,
  750. codec, wm8958_mbc_loaded);
  751. if (!pdata)
  752. return;
  753. if (pdata->num_mbc_cfgs) {
  754. struct snd_kcontrol_new control[] = {
  755. SOC_ENUM_EXT("MBC Mode", wm8994->mbc_enum,
  756. wm8958_get_mbc_enum, wm8958_put_mbc_enum),
  757. };
  758. /* We need an array of texts for the enum API */
  759. wm8994->mbc_texts = kmalloc(sizeof(char *)
  760. * pdata->num_mbc_cfgs, GFP_KERNEL);
  761. if (!wm8994->mbc_texts) {
  762. dev_err(wm8994->codec->dev,
  763. "Failed to allocate %d MBC config texts\n",
  764. pdata->num_mbc_cfgs);
  765. return;
  766. }
  767. for (i = 0; i < pdata->num_mbc_cfgs; i++)
  768. wm8994->mbc_texts[i] = pdata->mbc_cfgs[i].name;
  769. wm8994->mbc_enum.max = pdata->num_mbc_cfgs;
  770. wm8994->mbc_enum.texts = wm8994->mbc_texts;
  771. ret = snd_soc_add_controls(wm8994->codec, control, 1);
  772. if (ret != 0)
  773. dev_err(wm8994->codec->dev,
  774. "Failed to add MBC mode controls: %d\n", ret);
  775. }
  776. if (pdata->num_vss_cfgs) {
  777. struct snd_kcontrol_new control[] = {
  778. SOC_ENUM_EXT("VSS Mode", wm8994->vss_enum,
  779. wm8958_get_vss_enum, wm8958_put_vss_enum),
  780. };
  781. /* We need an array of texts for the enum API */
  782. wm8994->vss_texts = kmalloc(sizeof(char *)
  783. * pdata->num_vss_cfgs, GFP_KERNEL);
  784. if (!wm8994->vss_texts) {
  785. dev_err(wm8994->codec->dev,
  786. "Failed to allocate %d VSS config texts\n",
  787. pdata->num_vss_cfgs);
  788. return;
  789. }
  790. for (i = 0; i < pdata->num_vss_cfgs; i++)
  791. wm8994->vss_texts[i] = pdata->vss_cfgs[i].name;
  792. wm8994->vss_enum.max = pdata->num_vss_cfgs;
  793. wm8994->vss_enum.texts = wm8994->vss_texts;
  794. ret = snd_soc_add_controls(wm8994->codec, control, 1);
  795. if (ret != 0)
  796. dev_err(wm8994->codec->dev,
  797. "Failed to add VSS mode controls: %d\n", ret);
  798. }
  799. if (pdata->num_vss_hpf_cfgs) {
  800. struct snd_kcontrol_new control[] = {
  801. SOC_ENUM_EXT("VSS HPF Mode", wm8994->vss_hpf_enum,
  802. wm8958_get_vss_hpf_enum,
  803. wm8958_put_vss_hpf_enum),
  804. };
  805. /* We need an array of texts for the enum API */
  806. wm8994->vss_hpf_texts = kmalloc(sizeof(char *)
  807. * pdata->num_vss_hpf_cfgs, GFP_KERNEL);
  808. if (!wm8994->vss_hpf_texts) {
  809. dev_err(wm8994->codec->dev,
  810. "Failed to allocate %d VSS HPF config texts\n",
  811. pdata->num_vss_hpf_cfgs);
  812. return;
  813. }
  814. for (i = 0; i < pdata->num_vss_hpf_cfgs; i++)
  815. wm8994->vss_hpf_texts[i] = pdata->vss_hpf_cfgs[i].name;
  816. wm8994->vss_hpf_enum.max = pdata->num_vss_hpf_cfgs;
  817. wm8994->vss_hpf_enum.texts = wm8994->vss_hpf_texts;
  818. ret = snd_soc_add_controls(wm8994->codec, control, 1);
  819. if (ret != 0)
  820. dev_err(wm8994->codec->dev,
  821. "Failed to add VSS HPFmode controls: %d\n",
  822. ret);
  823. }
  824. if (pdata->num_enh_eq_cfgs) {
  825. struct snd_kcontrol_new control[] = {
  826. SOC_ENUM_EXT("Enhanced EQ Mode", wm8994->enh_eq_enum,
  827. wm8958_get_enh_eq_enum,
  828. wm8958_put_enh_eq_enum),
  829. };
  830. /* We need an array of texts for the enum API */
  831. wm8994->enh_eq_texts = kmalloc(sizeof(char *)
  832. * pdata->num_enh_eq_cfgs, GFP_KERNEL);
  833. if (!wm8994->enh_eq_texts) {
  834. dev_err(wm8994->codec->dev,
  835. "Failed to allocate %d enhanced EQ config texts\n",
  836. pdata->num_enh_eq_cfgs);
  837. return;
  838. }
  839. for (i = 0; i < pdata->num_enh_eq_cfgs; i++)
  840. wm8994->enh_eq_texts[i] = pdata->enh_eq_cfgs[i].name;
  841. wm8994->enh_eq_enum.max = pdata->num_enh_eq_cfgs;
  842. wm8994->enh_eq_enum.texts = wm8994->enh_eq_texts;
  843. ret = snd_soc_add_controls(wm8994->codec, control, 1);
  844. if (ret != 0)
  845. dev_err(wm8994->codec->dev,
  846. "Failed to add enhanced EQ controls: %d\n",
  847. ret);
  848. }
  849. }