ymfpci_main.c 71 KB

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  1. /*
  2. * Copyright (c) by Jaroslav Kysela <perex@perex.cz>
  3. * Routines for control of YMF724/740/744/754 chips
  4. *
  5. * This program is free software; you can redistribute it and/or modify
  6. * it under the terms of the GNU General Public License as published by
  7. * the Free Software Foundation; either version 2 of the License, or
  8. * (at your option) any later version.
  9. *
  10. * This program is distributed in the hope that it will be useful,
  11. * but WITHOUT ANY WARRANTY; without even the implied warranty of
  12. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  13. * GNU General Public License for more details.
  14. *
  15. * You should have received a copy of the GNU General Public License
  16. * along with this program; if not, write to the Free Software
  17. * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
  18. *
  19. */
  20. #include <linux/delay.h>
  21. #include <linux/firmware.h>
  22. #include <linux/init.h>
  23. #include <linux/interrupt.h>
  24. #include <linux/pci.h>
  25. #include <linux/sched.h>
  26. #include <linux/slab.h>
  27. #include <linux/vmalloc.h>
  28. #include <linux/mutex.h>
  29. #include <linux/module.h>
  30. #include <sound/core.h>
  31. #include <sound/control.h>
  32. #include <sound/info.h>
  33. #include <sound/tlv.h>
  34. #include <sound/ymfpci.h>
  35. #include <sound/asoundef.h>
  36. #include <sound/mpu401.h>
  37. #include <asm/io.h>
  38. #include <asm/byteorder.h>
  39. /*
  40. * common I/O routines
  41. */
  42. static void snd_ymfpci_irq_wait(struct snd_ymfpci *chip);
  43. static inline u8 snd_ymfpci_readb(struct snd_ymfpci *chip, u32 offset)
  44. {
  45. return readb(chip->reg_area_virt + offset);
  46. }
  47. static inline void snd_ymfpci_writeb(struct snd_ymfpci *chip, u32 offset, u8 val)
  48. {
  49. writeb(val, chip->reg_area_virt + offset);
  50. }
  51. static inline u16 snd_ymfpci_readw(struct snd_ymfpci *chip, u32 offset)
  52. {
  53. return readw(chip->reg_area_virt + offset);
  54. }
  55. static inline void snd_ymfpci_writew(struct snd_ymfpci *chip, u32 offset, u16 val)
  56. {
  57. writew(val, chip->reg_area_virt + offset);
  58. }
  59. static inline u32 snd_ymfpci_readl(struct snd_ymfpci *chip, u32 offset)
  60. {
  61. return readl(chip->reg_area_virt + offset);
  62. }
  63. static inline void snd_ymfpci_writel(struct snd_ymfpci *chip, u32 offset, u32 val)
  64. {
  65. writel(val, chip->reg_area_virt + offset);
  66. }
  67. static int snd_ymfpci_codec_ready(struct snd_ymfpci *chip, int secondary)
  68. {
  69. unsigned long end_time;
  70. u32 reg = secondary ? YDSXGR_SECSTATUSADR : YDSXGR_PRISTATUSADR;
  71. end_time = jiffies + msecs_to_jiffies(750);
  72. do {
  73. if ((snd_ymfpci_readw(chip, reg) & 0x8000) == 0)
  74. return 0;
  75. schedule_timeout_uninterruptible(1);
  76. } while (time_before(jiffies, end_time));
  77. snd_printk(KERN_ERR "codec_ready: codec %i is not ready [0x%x]\n", secondary, snd_ymfpci_readw(chip, reg));
  78. return -EBUSY;
  79. }
  80. static void snd_ymfpci_codec_write(struct snd_ac97 *ac97, u16 reg, u16 val)
  81. {
  82. struct snd_ymfpci *chip = ac97->private_data;
  83. u32 cmd;
  84. snd_ymfpci_codec_ready(chip, 0);
  85. cmd = ((YDSXG_AC97WRITECMD | reg) << 16) | val;
  86. snd_ymfpci_writel(chip, YDSXGR_AC97CMDDATA, cmd);
  87. }
  88. static u16 snd_ymfpci_codec_read(struct snd_ac97 *ac97, u16 reg)
  89. {
  90. struct snd_ymfpci *chip = ac97->private_data;
  91. if (snd_ymfpci_codec_ready(chip, 0))
  92. return ~0;
  93. snd_ymfpci_writew(chip, YDSXGR_AC97CMDADR, YDSXG_AC97READCMD | reg);
  94. if (snd_ymfpci_codec_ready(chip, 0))
  95. return ~0;
  96. if (chip->device_id == PCI_DEVICE_ID_YAMAHA_744 && chip->rev < 2) {
  97. int i;
  98. for (i = 0; i < 600; i++)
  99. snd_ymfpci_readw(chip, YDSXGR_PRISTATUSDATA);
  100. }
  101. return snd_ymfpci_readw(chip, YDSXGR_PRISTATUSDATA);
  102. }
  103. /*
  104. * Misc routines
  105. */
  106. static u32 snd_ymfpci_calc_delta(u32 rate)
  107. {
  108. switch (rate) {
  109. case 8000: return 0x02aaab00;
  110. case 11025: return 0x03accd00;
  111. case 16000: return 0x05555500;
  112. case 22050: return 0x07599a00;
  113. case 32000: return 0x0aaaab00;
  114. case 44100: return 0x0eb33300;
  115. default: return ((rate << 16) / 375) << 5;
  116. }
  117. }
  118. static u32 def_rate[8] = {
  119. 100, 2000, 8000, 11025, 16000, 22050, 32000, 48000
  120. };
  121. static u32 snd_ymfpci_calc_lpfK(u32 rate)
  122. {
  123. u32 i;
  124. static u32 val[8] = {
  125. 0x00570000, 0x06AA0000, 0x18B20000, 0x20930000,
  126. 0x2B9A0000, 0x35A10000, 0x3EAA0000, 0x40000000
  127. };
  128. if (rate == 44100)
  129. return 0x40000000; /* FIXME: What's the right value? */
  130. for (i = 0; i < 8; i++)
  131. if (rate <= def_rate[i])
  132. return val[i];
  133. return val[0];
  134. }
  135. static u32 snd_ymfpci_calc_lpfQ(u32 rate)
  136. {
  137. u32 i;
  138. static u32 val[8] = {
  139. 0x35280000, 0x34A70000, 0x32020000, 0x31770000,
  140. 0x31390000, 0x31C90000, 0x33D00000, 0x40000000
  141. };
  142. if (rate == 44100)
  143. return 0x370A0000;
  144. for (i = 0; i < 8; i++)
  145. if (rate <= def_rate[i])
  146. return val[i];
  147. return val[0];
  148. }
  149. /*
  150. * Hardware start management
  151. */
  152. static void snd_ymfpci_hw_start(struct snd_ymfpci *chip)
  153. {
  154. unsigned long flags;
  155. spin_lock_irqsave(&chip->reg_lock, flags);
  156. if (chip->start_count++ > 0)
  157. goto __end;
  158. snd_ymfpci_writel(chip, YDSXGR_MODE,
  159. snd_ymfpci_readl(chip, YDSXGR_MODE) | 3);
  160. chip->active_bank = snd_ymfpci_readl(chip, YDSXGR_CTRLSELECT) & 1;
  161. __end:
  162. spin_unlock_irqrestore(&chip->reg_lock, flags);
  163. }
  164. static void snd_ymfpci_hw_stop(struct snd_ymfpci *chip)
  165. {
  166. unsigned long flags;
  167. long timeout = 1000;
  168. spin_lock_irqsave(&chip->reg_lock, flags);
  169. if (--chip->start_count > 0)
  170. goto __end;
  171. snd_ymfpci_writel(chip, YDSXGR_MODE,
  172. snd_ymfpci_readl(chip, YDSXGR_MODE) & ~3);
  173. while (timeout-- > 0) {
  174. if ((snd_ymfpci_readl(chip, YDSXGR_STATUS) & 2) == 0)
  175. break;
  176. }
  177. if (atomic_read(&chip->interrupt_sleep_count)) {
  178. atomic_set(&chip->interrupt_sleep_count, 0);
  179. wake_up(&chip->interrupt_sleep);
  180. }
  181. __end:
  182. spin_unlock_irqrestore(&chip->reg_lock, flags);
  183. }
  184. /*
  185. * Playback voice management
  186. */
  187. static int voice_alloc(struct snd_ymfpci *chip,
  188. enum snd_ymfpci_voice_type type, int pair,
  189. struct snd_ymfpci_voice **rvoice)
  190. {
  191. struct snd_ymfpci_voice *voice, *voice2;
  192. int idx;
  193. *rvoice = NULL;
  194. for (idx = 0; idx < YDSXG_PLAYBACK_VOICES; idx += pair ? 2 : 1) {
  195. voice = &chip->voices[idx];
  196. voice2 = pair ? &chip->voices[idx+1] : NULL;
  197. if (voice->use || (voice2 && voice2->use))
  198. continue;
  199. voice->use = 1;
  200. if (voice2)
  201. voice2->use = 1;
  202. switch (type) {
  203. case YMFPCI_PCM:
  204. voice->pcm = 1;
  205. if (voice2)
  206. voice2->pcm = 1;
  207. break;
  208. case YMFPCI_SYNTH:
  209. voice->synth = 1;
  210. break;
  211. case YMFPCI_MIDI:
  212. voice->midi = 1;
  213. break;
  214. }
  215. snd_ymfpci_hw_start(chip);
  216. if (voice2)
  217. snd_ymfpci_hw_start(chip);
  218. *rvoice = voice;
  219. return 0;
  220. }
  221. return -ENOMEM;
  222. }
  223. static int snd_ymfpci_voice_alloc(struct snd_ymfpci *chip,
  224. enum snd_ymfpci_voice_type type, int pair,
  225. struct snd_ymfpci_voice **rvoice)
  226. {
  227. unsigned long flags;
  228. int result;
  229. if (snd_BUG_ON(!rvoice))
  230. return -EINVAL;
  231. if (snd_BUG_ON(pair && type != YMFPCI_PCM))
  232. return -EINVAL;
  233. spin_lock_irqsave(&chip->voice_lock, flags);
  234. for (;;) {
  235. result = voice_alloc(chip, type, pair, rvoice);
  236. if (result == 0 || type != YMFPCI_PCM)
  237. break;
  238. /* TODO: synth/midi voice deallocation */
  239. break;
  240. }
  241. spin_unlock_irqrestore(&chip->voice_lock, flags);
  242. return result;
  243. }
  244. static int snd_ymfpci_voice_free(struct snd_ymfpci *chip, struct snd_ymfpci_voice *pvoice)
  245. {
  246. unsigned long flags;
  247. if (snd_BUG_ON(!pvoice))
  248. return -EINVAL;
  249. snd_ymfpci_hw_stop(chip);
  250. spin_lock_irqsave(&chip->voice_lock, flags);
  251. if (pvoice->number == chip->src441_used) {
  252. chip->src441_used = -1;
  253. pvoice->ypcm->use_441_slot = 0;
  254. }
  255. pvoice->use = pvoice->pcm = pvoice->synth = pvoice->midi = 0;
  256. pvoice->ypcm = NULL;
  257. pvoice->interrupt = NULL;
  258. spin_unlock_irqrestore(&chip->voice_lock, flags);
  259. return 0;
  260. }
  261. /*
  262. * PCM part
  263. */
  264. static void snd_ymfpci_pcm_interrupt(struct snd_ymfpci *chip, struct snd_ymfpci_voice *voice)
  265. {
  266. struct snd_ymfpci_pcm *ypcm;
  267. u32 pos, delta;
  268. if ((ypcm = voice->ypcm) == NULL)
  269. return;
  270. if (ypcm->substream == NULL)
  271. return;
  272. spin_lock(&chip->reg_lock);
  273. if (ypcm->running) {
  274. pos = le32_to_cpu(voice->bank[chip->active_bank].start);
  275. if (pos < ypcm->last_pos)
  276. delta = pos + (ypcm->buffer_size - ypcm->last_pos);
  277. else
  278. delta = pos - ypcm->last_pos;
  279. ypcm->period_pos += delta;
  280. ypcm->last_pos = pos;
  281. if (ypcm->period_pos >= ypcm->period_size) {
  282. /*
  283. printk(KERN_DEBUG
  284. "done - active_bank = 0x%x, start = 0x%x\n",
  285. chip->active_bank,
  286. voice->bank[chip->active_bank].start);
  287. */
  288. ypcm->period_pos %= ypcm->period_size;
  289. spin_unlock(&chip->reg_lock);
  290. snd_pcm_period_elapsed(ypcm->substream);
  291. spin_lock(&chip->reg_lock);
  292. }
  293. if (unlikely(ypcm->update_pcm_vol)) {
  294. unsigned int subs = ypcm->substream->number;
  295. unsigned int next_bank = 1 - chip->active_bank;
  296. struct snd_ymfpci_playback_bank *bank;
  297. u32 volume;
  298. bank = &voice->bank[next_bank];
  299. volume = cpu_to_le32(chip->pcm_mixer[subs].left << 15);
  300. bank->left_gain_end = volume;
  301. if (ypcm->output_rear)
  302. bank->eff2_gain_end = volume;
  303. if (ypcm->voices[1])
  304. bank = &ypcm->voices[1]->bank[next_bank];
  305. volume = cpu_to_le32(chip->pcm_mixer[subs].right << 15);
  306. bank->right_gain_end = volume;
  307. if (ypcm->output_rear)
  308. bank->eff3_gain_end = volume;
  309. ypcm->update_pcm_vol--;
  310. }
  311. }
  312. spin_unlock(&chip->reg_lock);
  313. }
  314. static void snd_ymfpci_pcm_capture_interrupt(struct snd_pcm_substream *substream)
  315. {
  316. struct snd_pcm_runtime *runtime = substream->runtime;
  317. struct snd_ymfpci_pcm *ypcm = runtime->private_data;
  318. struct snd_ymfpci *chip = ypcm->chip;
  319. u32 pos, delta;
  320. spin_lock(&chip->reg_lock);
  321. if (ypcm->running) {
  322. pos = le32_to_cpu(chip->bank_capture[ypcm->capture_bank_number][chip->active_bank]->start) >> ypcm->shift;
  323. if (pos < ypcm->last_pos)
  324. delta = pos + (ypcm->buffer_size - ypcm->last_pos);
  325. else
  326. delta = pos - ypcm->last_pos;
  327. ypcm->period_pos += delta;
  328. ypcm->last_pos = pos;
  329. if (ypcm->period_pos >= ypcm->period_size) {
  330. ypcm->period_pos %= ypcm->period_size;
  331. /*
  332. printk(KERN_DEBUG
  333. "done - active_bank = 0x%x, start = 0x%x\n",
  334. chip->active_bank,
  335. voice->bank[chip->active_bank].start);
  336. */
  337. spin_unlock(&chip->reg_lock);
  338. snd_pcm_period_elapsed(substream);
  339. spin_lock(&chip->reg_lock);
  340. }
  341. }
  342. spin_unlock(&chip->reg_lock);
  343. }
  344. static int snd_ymfpci_playback_trigger(struct snd_pcm_substream *substream,
  345. int cmd)
  346. {
  347. struct snd_ymfpci *chip = snd_pcm_substream_chip(substream);
  348. struct snd_ymfpci_pcm *ypcm = substream->runtime->private_data;
  349. struct snd_kcontrol *kctl = NULL;
  350. int result = 0;
  351. spin_lock(&chip->reg_lock);
  352. if (ypcm->voices[0] == NULL) {
  353. result = -EINVAL;
  354. goto __unlock;
  355. }
  356. switch (cmd) {
  357. case SNDRV_PCM_TRIGGER_START:
  358. case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
  359. case SNDRV_PCM_TRIGGER_RESUME:
  360. chip->ctrl_playback[ypcm->voices[0]->number + 1] = cpu_to_le32(ypcm->voices[0]->bank_addr);
  361. if (ypcm->voices[1] != NULL && !ypcm->use_441_slot)
  362. chip->ctrl_playback[ypcm->voices[1]->number + 1] = cpu_to_le32(ypcm->voices[1]->bank_addr);
  363. ypcm->running = 1;
  364. break;
  365. case SNDRV_PCM_TRIGGER_STOP:
  366. if (substream->pcm == chip->pcm && !ypcm->use_441_slot) {
  367. kctl = chip->pcm_mixer[substream->number].ctl;
  368. kctl->vd[0].access |= SNDRV_CTL_ELEM_ACCESS_INACTIVE;
  369. }
  370. /* fall through */
  371. case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
  372. case SNDRV_PCM_TRIGGER_SUSPEND:
  373. chip->ctrl_playback[ypcm->voices[0]->number + 1] = 0;
  374. if (ypcm->voices[1] != NULL && !ypcm->use_441_slot)
  375. chip->ctrl_playback[ypcm->voices[1]->number + 1] = 0;
  376. ypcm->running = 0;
  377. break;
  378. default:
  379. result = -EINVAL;
  380. break;
  381. }
  382. __unlock:
  383. spin_unlock(&chip->reg_lock);
  384. if (kctl)
  385. snd_ctl_notify(chip->card, SNDRV_CTL_EVENT_MASK_INFO, &kctl->id);
  386. return result;
  387. }
  388. static int snd_ymfpci_capture_trigger(struct snd_pcm_substream *substream,
  389. int cmd)
  390. {
  391. struct snd_ymfpci *chip = snd_pcm_substream_chip(substream);
  392. struct snd_ymfpci_pcm *ypcm = substream->runtime->private_data;
  393. int result = 0;
  394. u32 tmp;
  395. spin_lock(&chip->reg_lock);
  396. switch (cmd) {
  397. case SNDRV_PCM_TRIGGER_START:
  398. case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
  399. case SNDRV_PCM_TRIGGER_RESUME:
  400. tmp = snd_ymfpci_readl(chip, YDSXGR_MAPOFREC) | (1 << ypcm->capture_bank_number);
  401. snd_ymfpci_writel(chip, YDSXGR_MAPOFREC, tmp);
  402. ypcm->running = 1;
  403. break;
  404. case SNDRV_PCM_TRIGGER_STOP:
  405. case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
  406. case SNDRV_PCM_TRIGGER_SUSPEND:
  407. tmp = snd_ymfpci_readl(chip, YDSXGR_MAPOFREC) & ~(1 << ypcm->capture_bank_number);
  408. snd_ymfpci_writel(chip, YDSXGR_MAPOFREC, tmp);
  409. ypcm->running = 0;
  410. break;
  411. default:
  412. result = -EINVAL;
  413. break;
  414. }
  415. spin_unlock(&chip->reg_lock);
  416. return result;
  417. }
  418. static int snd_ymfpci_pcm_voice_alloc(struct snd_ymfpci_pcm *ypcm, int voices)
  419. {
  420. int err;
  421. if (ypcm->voices[1] != NULL && voices < 2) {
  422. snd_ymfpci_voice_free(ypcm->chip, ypcm->voices[1]);
  423. ypcm->voices[1] = NULL;
  424. }
  425. if (voices == 1 && ypcm->voices[0] != NULL)
  426. return 0; /* already allocated */
  427. if (voices == 2 && ypcm->voices[0] != NULL && ypcm->voices[1] != NULL)
  428. return 0; /* already allocated */
  429. if (voices > 1) {
  430. if (ypcm->voices[0] != NULL && ypcm->voices[1] == NULL) {
  431. snd_ymfpci_voice_free(ypcm->chip, ypcm->voices[0]);
  432. ypcm->voices[0] = NULL;
  433. }
  434. }
  435. err = snd_ymfpci_voice_alloc(ypcm->chip, YMFPCI_PCM, voices > 1, &ypcm->voices[0]);
  436. if (err < 0)
  437. return err;
  438. ypcm->voices[0]->ypcm = ypcm;
  439. ypcm->voices[0]->interrupt = snd_ymfpci_pcm_interrupt;
  440. if (voices > 1) {
  441. ypcm->voices[1] = &ypcm->chip->voices[ypcm->voices[0]->number + 1];
  442. ypcm->voices[1]->ypcm = ypcm;
  443. }
  444. return 0;
  445. }
  446. static void snd_ymfpci_pcm_init_voice(struct snd_ymfpci_pcm *ypcm, unsigned int voiceidx,
  447. struct snd_pcm_runtime *runtime,
  448. int has_pcm_volume)
  449. {
  450. struct snd_ymfpci_voice *voice = ypcm->voices[voiceidx];
  451. u32 format;
  452. u32 delta = snd_ymfpci_calc_delta(runtime->rate);
  453. u32 lpfQ = snd_ymfpci_calc_lpfQ(runtime->rate);
  454. u32 lpfK = snd_ymfpci_calc_lpfK(runtime->rate);
  455. struct snd_ymfpci_playback_bank *bank;
  456. unsigned int nbank;
  457. u32 vol_left, vol_right;
  458. u8 use_left, use_right;
  459. unsigned long flags;
  460. if (snd_BUG_ON(!voice))
  461. return;
  462. if (runtime->channels == 1) {
  463. use_left = 1;
  464. use_right = 1;
  465. } else {
  466. use_left = (voiceidx & 1) == 0;
  467. use_right = !use_left;
  468. }
  469. if (has_pcm_volume) {
  470. vol_left = cpu_to_le32(ypcm->chip->pcm_mixer
  471. [ypcm->substream->number].left << 15);
  472. vol_right = cpu_to_le32(ypcm->chip->pcm_mixer
  473. [ypcm->substream->number].right << 15);
  474. } else {
  475. vol_left = cpu_to_le32(0x40000000);
  476. vol_right = cpu_to_le32(0x40000000);
  477. }
  478. spin_lock_irqsave(&ypcm->chip->voice_lock, flags);
  479. format = runtime->channels == 2 ? 0x00010000 : 0;
  480. if (snd_pcm_format_width(runtime->format) == 8)
  481. format |= 0x80000000;
  482. else if (ypcm->chip->device_id == PCI_DEVICE_ID_YAMAHA_754 &&
  483. runtime->rate == 44100 && runtime->channels == 2 &&
  484. voiceidx == 0 && (ypcm->chip->src441_used == -1 ||
  485. ypcm->chip->src441_used == voice->number)) {
  486. ypcm->chip->src441_used = voice->number;
  487. ypcm->use_441_slot = 1;
  488. format |= 0x10000000;
  489. }
  490. if (ypcm->chip->src441_used == voice->number &&
  491. (format & 0x10000000) == 0) {
  492. ypcm->chip->src441_used = -1;
  493. ypcm->use_441_slot = 0;
  494. }
  495. if (runtime->channels == 2 && (voiceidx & 1) != 0)
  496. format |= 1;
  497. spin_unlock_irqrestore(&ypcm->chip->voice_lock, flags);
  498. for (nbank = 0; nbank < 2; nbank++) {
  499. bank = &voice->bank[nbank];
  500. memset(bank, 0, sizeof(*bank));
  501. bank->format = cpu_to_le32(format);
  502. bank->base = cpu_to_le32(runtime->dma_addr);
  503. bank->loop_end = cpu_to_le32(ypcm->buffer_size);
  504. bank->lpfQ = cpu_to_le32(lpfQ);
  505. bank->delta =
  506. bank->delta_end = cpu_to_le32(delta);
  507. bank->lpfK =
  508. bank->lpfK_end = cpu_to_le32(lpfK);
  509. bank->eg_gain =
  510. bank->eg_gain_end = cpu_to_le32(0x40000000);
  511. if (ypcm->output_front) {
  512. if (use_left) {
  513. bank->left_gain =
  514. bank->left_gain_end = vol_left;
  515. }
  516. if (use_right) {
  517. bank->right_gain =
  518. bank->right_gain_end = vol_right;
  519. }
  520. }
  521. if (ypcm->output_rear) {
  522. if (!ypcm->swap_rear) {
  523. if (use_left) {
  524. bank->eff2_gain =
  525. bank->eff2_gain_end = vol_left;
  526. }
  527. if (use_right) {
  528. bank->eff3_gain =
  529. bank->eff3_gain_end = vol_right;
  530. }
  531. } else {
  532. /* The SPDIF out channels seem to be swapped, so we have
  533. * to swap them here, too. The rear analog out channels
  534. * will be wrong, but otherwise AC3 would not work.
  535. */
  536. if (use_left) {
  537. bank->eff3_gain =
  538. bank->eff3_gain_end = vol_left;
  539. }
  540. if (use_right) {
  541. bank->eff2_gain =
  542. bank->eff2_gain_end = vol_right;
  543. }
  544. }
  545. }
  546. }
  547. }
  548. static int __devinit snd_ymfpci_ac3_init(struct snd_ymfpci *chip)
  549. {
  550. if (snd_dma_alloc_pages(SNDRV_DMA_TYPE_DEV, snd_dma_pci_data(chip->pci),
  551. 4096, &chip->ac3_tmp_base) < 0)
  552. return -ENOMEM;
  553. chip->bank_effect[3][0]->base =
  554. chip->bank_effect[3][1]->base = cpu_to_le32(chip->ac3_tmp_base.addr);
  555. chip->bank_effect[3][0]->loop_end =
  556. chip->bank_effect[3][1]->loop_end = cpu_to_le32(1024);
  557. chip->bank_effect[4][0]->base =
  558. chip->bank_effect[4][1]->base = cpu_to_le32(chip->ac3_tmp_base.addr + 2048);
  559. chip->bank_effect[4][0]->loop_end =
  560. chip->bank_effect[4][1]->loop_end = cpu_to_le32(1024);
  561. spin_lock_irq(&chip->reg_lock);
  562. snd_ymfpci_writel(chip, YDSXGR_MAPOFEFFECT,
  563. snd_ymfpci_readl(chip, YDSXGR_MAPOFEFFECT) | 3 << 3);
  564. spin_unlock_irq(&chip->reg_lock);
  565. return 0;
  566. }
  567. static int snd_ymfpci_ac3_done(struct snd_ymfpci *chip)
  568. {
  569. spin_lock_irq(&chip->reg_lock);
  570. snd_ymfpci_writel(chip, YDSXGR_MAPOFEFFECT,
  571. snd_ymfpci_readl(chip, YDSXGR_MAPOFEFFECT) & ~(3 << 3));
  572. spin_unlock_irq(&chip->reg_lock);
  573. // snd_ymfpci_irq_wait(chip);
  574. if (chip->ac3_tmp_base.area) {
  575. snd_dma_free_pages(&chip->ac3_tmp_base);
  576. chip->ac3_tmp_base.area = NULL;
  577. }
  578. return 0;
  579. }
  580. static int snd_ymfpci_playback_hw_params(struct snd_pcm_substream *substream,
  581. struct snd_pcm_hw_params *hw_params)
  582. {
  583. struct snd_pcm_runtime *runtime = substream->runtime;
  584. struct snd_ymfpci_pcm *ypcm = runtime->private_data;
  585. int err;
  586. if ((err = snd_pcm_lib_malloc_pages(substream, params_buffer_bytes(hw_params))) < 0)
  587. return err;
  588. if ((err = snd_ymfpci_pcm_voice_alloc(ypcm, params_channels(hw_params))) < 0)
  589. return err;
  590. return 0;
  591. }
  592. static int snd_ymfpci_playback_hw_free(struct snd_pcm_substream *substream)
  593. {
  594. struct snd_ymfpci *chip = snd_pcm_substream_chip(substream);
  595. struct snd_pcm_runtime *runtime = substream->runtime;
  596. struct snd_ymfpci_pcm *ypcm;
  597. if (runtime->private_data == NULL)
  598. return 0;
  599. ypcm = runtime->private_data;
  600. /* wait, until the PCI operations are not finished */
  601. snd_ymfpci_irq_wait(chip);
  602. snd_pcm_lib_free_pages(substream);
  603. if (ypcm->voices[1]) {
  604. snd_ymfpci_voice_free(chip, ypcm->voices[1]);
  605. ypcm->voices[1] = NULL;
  606. }
  607. if (ypcm->voices[0]) {
  608. snd_ymfpci_voice_free(chip, ypcm->voices[0]);
  609. ypcm->voices[0] = NULL;
  610. }
  611. return 0;
  612. }
  613. static int snd_ymfpci_playback_prepare(struct snd_pcm_substream *substream)
  614. {
  615. struct snd_ymfpci *chip = snd_pcm_substream_chip(substream);
  616. struct snd_pcm_runtime *runtime = substream->runtime;
  617. struct snd_ymfpci_pcm *ypcm = runtime->private_data;
  618. struct snd_kcontrol *kctl;
  619. unsigned int nvoice;
  620. ypcm->period_size = runtime->period_size;
  621. ypcm->buffer_size = runtime->buffer_size;
  622. ypcm->period_pos = 0;
  623. ypcm->last_pos = 0;
  624. for (nvoice = 0; nvoice < runtime->channels; nvoice++)
  625. snd_ymfpci_pcm_init_voice(ypcm, nvoice, runtime,
  626. substream->pcm == chip->pcm);
  627. if (substream->pcm == chip->pcm && !ypcm->use_441_slot) {
  628. kctl = chip->pcm_mixer[substream->number].ctl;
  629. kctl->vd[0].access &= ~SNDRV_CTL_ELEM_ACCESS_INACTIVE;
  630. snd_ctl_notify(chip->card, SNDRV_CTL_EVENT_MASK_INFO, &kctl->id);
  631. }
  632. return 0;
  633. }
  634. static int snd_ymfpci_capture_hw_params(struct snd_pcm_substream *substream,
  635. struct snd_pcm_hw_params *hw_params)
  636. {
  637. return snd_pcm_lib_malloc_pages(substream, params_buffer_bytes(hw_params));
  638. }
  639. static int snd_ymfpci_capture_hw_free(struct snd_pcm_substream *substream)
  640. {
  641. struct snd_ymfpci *chip = snd_pcm_substream_chip(substream);
  642. /* wait, until the PCI operations are not finished */
  643. snd_ymfpci_irq_wait(chip);
  644. return snd_pcm_lib_free_pages(substream);
  645. }
  646. static int snd_ymfpci_capture_prepare(struct snd_pcm_substream *substream)
  647. {
  648. struct snd_ymfpci *chip = snd_pcm_substream_chip(substream);
  649. struct snd_pcm_runtime *runtime = substream->runtime;
  650. struct snd_ymfpci_pcm *ypcm = runtime->private_data;
  651. struct snd_ymfpci_capture_bank * bank;
  652. int nbank;
  653. u32 rate, format;
  654. ypcm->period_size = runtime->period_size;
  655. ypcm->buffer_size = runtime->buffer_size;
  656. ypcm->period_pos = 0;
  657. ypcm->last_pos = 0;
  658. ypcm->shift = 0;
  659. rate = ((48000 * 4096) / runtime->rate) - 1;
  660. format = 0;
  661. if (runtime->channels == 2) {
  662. format |= 2;
  663. ypcm->shift++;
  664. }
  665. if (snd_pcm_format_width(runtime->format) == 8)
  666. format |= 1;
  667. else
  668. ypcm->shift++;
  669. switch (ypcm->capture_bank_number) {
  670. case 0:
  671. snd_ymfpci_writel(chip, YDSXGR_RECFORMAT, format);
  672. snd_ymfpci_writel(chip, YDSXGR_RECSLOTSR, rate);
  673. break;
  674. case 1:
  675. snd_ymfpci_writel(chip, YDSXGR_ADCFORMAT, format);
  676. snd_ymfpci_writel(chip, YDSXGR_ADCSLOTSR, rate);
  677. break;
  678. }
  679. for (nbank = 0; nbank < 2; nbank++) {
  680. bank = chip->bank_capture[ypcm->capture_bank_number][nbank];
  681. bank->base = cpu_to_le32(runtime->dma_addr);
  682. bank->loop_end = cpu_to_le32(ypcm->buffer_size << ypcm->shift);
  683. bank->start = 0;
  684. bank->num_of_loops = 0;
  685. }
  686. return 0;
  687. }
  688. static snd_pcm_uframes_t snd_ymfpci_playback_pointer(struct snd_pcm_substream *substream)
  689. {
  690. struct snd_ymfpci *chip = snd_pcm_substream_chip(substream);
  691. struct snd_pcm_runtime *runtime = substream->runtime;
  692. struct snd_ymfpci_pcm *ypcm = runtime->private_data;
  693. struct snd_ymfpci_voice *voice = ypcm->voices[0];
  694. if (!(ypcm->running && voice))
  695. return 0;
  696. return le32_to_cpu(voice->bank[chip->active_bank].start);
  697. }
  698. static snd_pcm_uframes_t snd_ymfpci_capture_pointer(struct snd_pcm_substream *substream)
  699. {
  700. struct snd_ymfpci *chip = snd_pcm_substream_chip(substream);
  701. struct snd_pcm_runtime *runtime = substream->runtime;
  702. struct snd_ymfpci_pcm *ypcm = runtime->private_data;
  703. if (!ypcm->running)
  704. return 0;
  705. return le32_to_cpu(chip->bank_capture[ypcm->capture_bank_number][chip->active_bank]->start) >> ypcm->shift;
  706. }
  707. static void snd_ymfpci_irq_wait(struct snd_ymfpci *chip)
  708. {
  709. wait_queue_t wait;
  710. int loops = 4;
  711. while (loops-- > 0) {
  712. if ((snd_ymfpci_readl(chip, YDSXGR_MODE) & 3) == 0)
  713. continue;
  714. init_waitqueue_entry(&wait, current);
  715. add_wait_queue(&chip->interrupt_sleep, &wait);
  716. atomic_inc(&chip->interrupt_sleep_count);
  717. schedule_timeout_uninterruptible(msecs_to_jiffies(50));
  718. remove_wait_queue(&chip->interrupt_sleep, &wait);
  719. }
  720. }
  721. static irqreturn_t snd_ymfpci_interrupt(int irq, void *dev_id)
  722. {
  723. struct snd_ymfpci *chip = dev_id;
  724. u32 status, nvoice, mode;
  725. struct snd_ymfpci_voice *voice;
  726. status = snd_ymfpci_readl(chip, YDSXGR_STATUS);
  727. if (status & 0x80000000) {
  728. chip->active_bank = snd_ymfpci_readl(chip, YDSXGR_CTRLSELECT) & 1;
  729. spin_lock(&chip->voice_lock);
  730. for (nvoice = 0; nvoice < YDSXG_PLAYBACK_VOICES; nvoice++) {
  731. voice = &chip->voices[nvoice];
  732. if (voice->interrupt)
  733. voice->interrupt(chip, voice);
  734. }
  735. for (nvoice = 0; nvoice < YDSXG_CAPTURE_VOICES; nvoice++) {
  736. if (chip->capture_substream[nvoice])
  737. snd_ymfpci_pcm_capture_interrupt(chip->capture_substream[nvoice]);
  738. }
  739. #if 0
  740. for (nvoice = 0; nvoice < YDSXG_EFFECT_VOICES; nvoice++) {
  741. if (chip->effect_substream[nvoice])
  742. snd_ymfpci_pcm_effect_interrupt(chip->effect_substream[nvoice]);
  743. }
  744. #endif
  745. spin_unlock(&chip->voice_lock);
  746. spin_lock(&chip->reg_lock);
  747. snd_ymfpci_writel(chip, YDSXGR_STATUS, 0x80000000);
  748. mode = snd_ymfpci_readl(chip, YDSXGR_MODE) | 2;
  749. snd_ymfpci_writel(chip, YDSXGR_MODE, mode);
  750. spin_unlock(&chip->reg_lock);
  751. if (atomic_read(&chip->interrupt_sleep_count)) {
  752. atomic_set(&chip->interrupt_sleep_count, 0);
  753. wake_up(&chip->interrupt_sleep);
  754. }
  755. }
  756. status = snd_ymfpci_readw(chip, YDSXGR_INTFLAG);
  757. if (status & 1) {
  758. if (chip->timer)
  759. snd_timer_interrupt(chip->timer, chip->timer_ticks);
  760. }
  761. snd_ymfpci_writew(chip, YDSXGR_INTFLAG, status);
  762. if (chip->rawmidi)
  763. snd_mpu401_uart_interrupt(irq, chip->rawmidi->private_data);
  764. return IRQ_HANDLED;
  765. }
  766. static struct snd_pcm_hardware snd_ymfpci_playback =
  767. {
  768. .info = (SNDRV_PCM_INFO_MMAP |
  769. SNDRV_PCM_INFO_MMAP_VALID |
  770. SNDRV_PCM_INFO_INTERLEAVED |
  771. SNDRV_PCM_INFO_BLOCK_TRANSFER |
  772. SNDRV_PCM_INFO_PAUSE |
  773. SNDRV_PCM_INFO_RESUME),
  774. .formats = SNDRV_PCM_FMTBIT_U8 | SNDRV_PCM_FMTBIT_S16_LE,
  775. .rates = SNDRV_PCM_RATE_CONTINUOUS | SNDRV_PCM_RATE_8000_48000,
  776. .rate_min = 8000,
  777. .rate_max = 48000,
  778. .channels_min = 1,
  779. .channels_max = 2,
  780. .buffer_bytes_max = 256 * 1024, /* FIXME: enough? */
  781. .period_bytes_min = 64,
  782. .period_bytes_max = 256 * 1024, /* FIXME: enough? */
  783. .periods_min = 3,
  784. .periods_max = 1024,
  785. .fifo_size = 0,
  786. };
  787. static struct snd_pcm_hardware snd_ymfpci_capture =
  788. {
  789. .info = (SNDRV_PCM_INFO_MMAP |
  790. SNDRV_PCM_INFO_MMAP_VALID |
  791. SNDRV_PCM_INFO_INTERLEAVED |
  792. SNDRV_PCM_INFO_BLOCK_TRANSFER |
  793. SNDRV_PCM_INFO_PAUSE |
  794. SNDRV_PCM_INFO_RESUME),
  795. .formats = SNDRV_PCM_FMTBIT_U8 | SNDRV_PCM_FMTBIT_S16_LE,
  796. .rates = SNDRV_PCM_RATE_CONTINUOUS | SNDRV_PCM_RATE_8000_48000,
  797. .rate_min = 8000,
  798. .rate_max = 48000,
  799. .channels_min = 1,
  800. .channels_max = 2,
  801. .buffer_bytes_max = 256 * 1024, /* FIXME: enough? */
  802. .period_bytes_min = 64,
  803. .period_bytes_max = 256 * 1024, /* FIXME: enough? */
  804. .periods_min = 3,
  805. .periods_max = 1024,
  806. .fifo_size = 0,
  807. };
  808. static void snd_ymfpci_pcm_free_substream(struct snd_pcm_runtime *runtime)
  809. {
  810. kfree(runtime->private_data);
  811. }
  812. static int snd_ymfpci_playback_open_1(struct snd_pcm_substream *substream)
  813. {
  814. struct snd_ymfpci *chip = snd_pcm_substream_chip(substream);
  815. struct snd_pcm_runtime *runtime = substream->runtime;
  816. struct snd_ymfpci_pcm *ypcm;
  817. int err;
  818. runtime->hw = snd_ymfpci_playback;
  819. /* FIXME? True value is 256/48 = 5.33333 ms */
  820. err = snd_pcm_hw_constraint_minmax(runtime,
  821. SNDRV_PCM_HW_PARAM_PERIOD_TIME,
  822. 5334, UINT_MAX);
  823. if (err < 0)
  824. return err;
  825. err = snd_pcm_hw_rule_noresample(runtime, 48000);
  826. if (err < 0)
  827. return err;
  828. ypcm = kzalloc(sizeof(*ypcm), GFP_KERNEL);
  829. if (ypcm == NULL)
  830. return -ENOMEM;
  831. ypcm->chip = chip;
  832. ypcm->type = PLAYBACK_VOICE;
  833. ypcm->substream = substream;
  834. runtime->private_data = ypcm;
  835. runtime->private_free = snd_ymfpci_pcm_free_substream;
  836. return 0;
  837. }
  838. /* call with spinlock held */
  839. static void ymfpci_open_extension(struct snd_ymfpci *chip)
  840. {
  841. if (! chip->rear_opened) {
  842. if (! chip->spdif_opened) /* set AC3 */
  843. snd_ymfpci_writel(chip, YDSXGR_MODE,
  844. snd_ymfpci_readl(chip, YDSXGR_MODE) | (1 << 30));
  845. /* enable second codec (4CHEN) */
  846. snd_ymfpci_writew(chip, YDSXGR_SECCONFIG,
  847. (snd_ymfpci_readw(chip, YDSXGR_SECCONFIG) & ~0x0330) | 0x0010);
  848. }
  849. }
  850. /* call with spinlock held */
  851. static void ymfpci_close_extension(struct snd_ymfpci *chip)
  852. {
  853. if (! chip->rear_opened) {
  854. if (! chip->spdif_opened)
  855. snd_ymfpci_writel(chip, YDSXGR_MODE,
  856. snd_ymfpci_readl(chip, YDSXGR_MODE) & ~(1 << 30));
  857. snd_ymfpci_writew(chip, YDSXGR_SECCONFIG,
  858. (snd_ymfpci_readw(chip, YDSXGR_SECCONFIG) & ~0x0330) & ~0x0010);
  859. }
  860. }
  861. static int snd_ymfpci_playback_open(struct snd_pcm_substream *substream)
  862. {
  863. struct snd_ymfpci *chip = snd_pcm_substream_chip(substream);
  864. struct snd_pcm_runtime *runtime = substream->runtime;
  865. struct snd_ymfpci_pcm *ypcm;
  866. int err;
  867. if ((err = snd_ymfpci_playback_open_1(substream)) < 0)
  868. return err;
  869. ypcm = runtime->private_data;
  870. ypcm->output_front = 1;
  871. ypcm->output_rear = chip->mode_dup4ch ? 1 : 0;
  872. ypcm->swap_rear = 0;
  873. spin_lock_irq(&chip->reg_lock);
  874. if (ypcm->output_rear) {
  875. ymfpci_open_extension(chip);
  876. chip->rear_opened++;
  877. }
  878. spin_unlock_irq(&chip->reg_lock);
  879. return 0;
  880. }
  881. static int snd_ymfpci_playback_spdif_open(struct snd_pcm_substream *substream)
  882. {
  883. struct snd_ymfpci *chip = snd_pcm_substream_chip(substream);
  884. struct snd_pcm_runtime *runtime = substream->runtime;
  885. struct snd_ymfpci_pcm *ypcm;
  886. int err;
  887. if ((err = snd_ymfpci_playback_open_1(substream)) < 0)
  888. return err;
  889. ypcm = runtime->private_data;
  890. ypcm->output_front = 0;
  891. ypcm->output_rear = 1;
  892. ypcm->swap_rear = 1;
  893. spin_lock_irq(&chip->reg_lock);
  894. snd_ymfpci_writew(chip, YDSXGR_SPDIFOUTCTRL,
  895. snd_ymfpci_readw(chip, YDSXGR_SPDIFOUTCTRL) | 2);
  896. ymfpci_open_extension(chip);
  897. chip->spdif_pcm_bits = chip->spdif_bits;
  898. snd_ymfpci_writew(chip, YDSXGR_SPDIFOUTSTATUS, chip->spdif_pcm_bits);
  899. chip->spdif_opened++;
  900. spin_unlock_irq(&chip->reg_lock);
  901. chip->spdif_pcm_ctl->vd[0].access &= ~SNDRV_CTL_ELEM_ACCESS_INACTIVE;
  902. snd_ctl_notify(chip->card, SNDRV_CTL_EVENT_MASK_VALUE |
  903. SNDRV_CTL_EVENT_MASK_INFO, &chip->spdif_pcm_ctl->id);
  904. return 0;
  905. }
  906. static int snd_ymfpci_playback_4ch_open(struct snd_pcm_substream *substream)
  907. {
  908. struct snd_ymfpci *chip = snd_pcm_substream_chip(substream);
  909. struct snd_pcm_runtime *runtime = substream->runtime;
  910. struct snd_ymfpci_pcm *ypcm;
  911. int err;
  912. if ((err = snd_ymfpci_playback_open_1(substream)) < 0)
  913. return err;
  914. ypcm = runtime->private_data;
  915. ypcm->output_front = 0;
  916. ypcm->output_rear = 1;
  917. ypcm->swap_rear = 0;
  918. spin_lock_irq(&chip->reg_lock);
  919. ymfpci_open_extension(chip);
  920. chip->rear_opened++;
  921. spin_unlock_irq(&chip->reg_lock);
  922. return 0;
  923. }
  924. static int snd_ymfpci_capture_open(struct snd_pcm_substream *substream,
  925. u32 capture_bank_number)
  926. {
  927. struct snd_ymfpci *chip = snd_pcm_substream_chip(substream);
  928. struct snd_pcm_runtime *runtime = substream->runtime;
  929. struct snd_ymfpci_pcm *ypcm;
  930. int err;
  931. runtime->hw = snd_ymfpci_capture;
  932. /* FIXME? True value is 256/48 = 5.33333 ms */
  933. err = snd_pcm_hw_constraint_minmax(runtime,
  934. SNDRV_PCM_HW_PARAM_PERIOD_TIME,
  935. 5334, UINT_MAX);
  936. if (err < 0)
  937. return err;
  938. err = snd_pcm_hw_rule_noresample(runtime, 48000);
  939. if (err < 0)
  940. return err;
  941. ypcm = kzalloc(sizeof(*ypcm), GFP_KERNEL);
  942. if (ypcm == NULL)
  943. return -ENOMEM;
  944. ypcm->chip = chip;
  945. ypcm->type = capture_bank_number + CAPTURE_REC;
  946. ypcm->substream = substream;
  947. ypcm->capture_bank_number = capture_bank_number;
  948. chip->capture_substream[capture_bank_number] = substream;
  949. runtime->private_data = ypcm;
  950. runtime->private_free = snd_ymfpci_pcm_free_substream;
  951. snd_ymfpci_hw_start(chip);
  952. return 0;
  953. }
  954. static int snd_ymfpci_capture_rec_open(struct snd_pcm_substream *substream)
  955. {
  956. return snd_ymfpci_capture_open(substream, 0);
  957. }
  958. static int snd_ymfpci_capture_ac97_open(struct snd_pcm_substream *substream)
  959. {
  960. return snd_ymfpci_capture_open(substream, 1);
  961. }
  962. static int snd_ymfpci_playback_close_1(struct snd_pcm_substream *substream)
  963. {
  964. return 0;
  965. }
  966. static int snd_ymfpci_playback_close(struct snd_pcm_substream *substream)
  967. {
  968. struct snd_ymfpci *chip = snd_pcm_substream_chip(substream);
  969. struct snd_ymfpci_pcm *ypcm = substream->runtime->private_data;
  970. spin_lock_irq(&chip->reg_lock);
  971. if (ypcm->output_rear && chip->rear_opened > 0) {
  972. chip->rear_opened--;
  973. ymfpci_close_extension(chip);
  974. }
  975. spin_unlock_irq(&chip->reg_lock);
  976. return snd_ymfpci_playback_close_1(substream);
  977. }
  978. static int snd_ymfpci_playback_spdif_close(struct snd_pcm_substream *substream)
  979. {
  980. struct snd_ymfpci *chip = snd_pcm_substream_chip(substream);
  981. spin_lock_irq(&chip->reg_lock);
  982. chip->spdif_opened = 0;
  983. ymfpci_close_extension(chip);
  984. snd_ymfpci_writew(chip, YDSXGR_SPDIFOUTCTRL,
  985. snd_ymfpci_readw(chip, YDSXGR_SPDIFOUTCTRL) & ~2);
  986. snd_ymfpci_writew(chip, YDSXGR_SPDIFOUTSTATUS, chip->spdif_bits);
  987. spin_unlock_irq(&chip->reg_lock);
  988. chip->spdif_pcm_ctl->vd[0].access |= SNDRV_CTL_ELEM_ACCESS_INACTIVE;
  989. snd_ctl_notify(chip->card, SNDRV_CTL_EVENT_MASK_VALUE |
  990. SNDRV_CTL_EVENT_MASK_INFO, &chip->spdif_pcm_ctl->id);
  991. return snd_ymfpci_playback_close_1(substream);
  992. }
  993. static int snd_ymfpci_playback_4ch_close(struct snd_pcm_substream *substream)
  994. {
  995. struct snd_ymfpci *chip = snd_pcm_substream_chip(substream);
  996. spin_lock_irq(&chip->reg_lock);
  997. if (chip->rear_opened > 0) {
  998. chip->rear_opened--;
  999. ymfpci_close_extension(chip);
  1000. }
  1001. spin_unlock_irq(&chip->reg_lock);
  1002. return snd_ymfpci_playback_close_1(substream);
  1003. }
  1004. static int snd_ymfpci_capture_close(struct snd_pcm_substream *substream)
  1005. {
  1006. struct snd_ymfpci *chip = snd_pcm_substream_chip(substream);
  1007. struct snd_pcm_runtime *runtime = substream->runtime;
  1008. struct snd_ymfpci_pcm *ypcm = runtime->private_data;
  1009. if (ypcm != NULL) {
  1010. chip->capture_substream[ypcm->capture_bank_number] = NULL;
  1011. snd_ymfpci_hw_stop(chip);
  1012. }
  1013. return 0;
  1014. }
  1015. static struct snd_pcm_ops snd_ymfpci_playback_ops = {
  1016. .open = snd_ymfpci_playback_open,
  1017. .close = snd_ymfpci_playback_close,
  1018. .ioctl = snd_pcm_lib_ioctl,
  1019. .hw_params = snd_ymfpci_playback_hw_params,
  1020. .hw_free = snd_ymfpci_playback_hw_free,
  1021. .prepare = snd_ymfpci_playback_prepare,
  1022. .trigger = snd_ymfpci_playback_trigger,
  1023. .pointer = snd_ymfpci_playback_pointer,
  1024. };
  1025. static struct snd_pcm_ops snd_ymfpci_capture_rec_ops = {
  1026. .open = snd_ymfpci_capture_rec_open,
  1027. .close = snd_ymfpci_capture_close,
  1028. .ioctl = snd_pcm_lib_ioctl,
  1029. .hw_params = snd_ymfpci_capture_hw_params,
  1030. .hw_free = snd_ymfpci_capture_hw_free,
  1031. .prepare = snd_ymfpci_capture_prepare,
  1032. .trigger = snd_ymfpci_capture_trigger,
  1033. .pointer = snd_ymfpci_capture_pointer,
  1034. };
  1035. int __devinit snd_ymfpci_pcm(struct snd_ymfpci *chip, int device, struct snd_pcm ** rpcm)
  1036. {
  1037. struct snd_pcm *pcm;
  1038. int err;
  1039. if (rpcm)
  1040. *rpcm = NULL;
  1041. if ((err = snd_pcm_new(chip->card, "YMFPCI", device, 32, 1, &pcm)) < 0)
  1042. return err;
  1043. pcm->private_data = chip;
  1044. snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_PLAYBACK, &snd_ymfpci_playback_ops);
  1045. snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_CAPTURE, &snd_ymfpci_capture_rec_ops);
  1046. /* global setup */
  1047. pcm->info_flags = 0;
  1048. strcpy(pcm->name, "YMFPCI");
  1049. chip->pcm = pcm;
  1050. snd_pcm_lib_preallocate_pages_for_all(pcm, SNDRV_DMA_TYPE_DEV,
  1051. snd_dma_pci_data(chip->pci), 64*1024, 256*1024);
  1052. if (rpcm)
  1053. *rpcm = pcm;
  1054. return 0;
  1055. }
  1056. static struct snd_pcm_ops snd_ymfpci_capture_ac97_ops = {
  1057. .open = snd_ymfpci_capture_ac97_open,
  1058. .close = snd_ymfpci_capture_close,
  1059. .ioctl = snd_pcm_lib_ioctl,
  1060. .hw_params = snd_ymfpci_capture_hw_params,
  1061. .hw_free = snd_ymfpci_capture_hw_free,
  1062. .prepare = snd_ymfpci_capture_prepare,
  1063. .trigger = snd_ymfpci_capture_trigger,
  1064. .pointer = snd_ymfpci_capture_pointer,
  1065. };
  1066. int __devinit snd_ymfpci_pcm2(struct snd_ymfpci *chip, int device, struct snd_pcm ** rpcm)
  1067. {
  1068. struct snd_pcm *pcm;
  1069. int err;
  1070. if (rpcm)
  1071. *rpcm = NULL;
  1072. if ((err = snd_pcm_new(chip->card, "YMFPCI - PCM2", device, 0, 1, &pcm)) < 0)
  1073. return err;
  1074. pcm->private_data = chip;
  1075. snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_CAPTURE, &snd_ymfpci_capture_ac97_ops);
  1076. /* global setup */
  1077. pcm->info_flags = 0;
  1078. sprintf(pcm->name, "YMFPCI - %s",
  1079. chip->device_id == PCI_DEVICE_ID_YAMAHA_754 ? "Direct Recording" : "AC'97");
  1080. chip->pcm2 = pcm;
  1081. snd_pcm_lib_preallocate_pages_for_all(pcm, SNDRV_DMA_TYPE_DEV,
  1082. snd_dma_pci_data(chip->pci), 64*1024, 256*1024);
  1083. if (rpcm)
  1084. *rpcm = pcm;
  1085. return 0;
  1086. }
  1087. static struct snd_pcm_ops snd_ymfpci_playback_spdif_ops = {
  1088. .open = snd_ymfpci_playback_spdif_open,
  1089. .close = snd_ymfpci_playback_spdif_close,
  1090. .ioctl = snd_pcm_lib_ioctl,
  1091. .hw_params = snd_ymfpci_playback_hw_params,
  1092. .hw_free = snd_ymfpci_playback_hw_free,
  1093. .prepare = snd_ymfpci_playback_prepare,
  1094. .trigger = snd_ymfpci_playback_trigger,
  1095. .pointer = snd_ymfpci_playback_pointer,
  1096. };
  1097. int __devinit snd_ymfpci_pcm_spdif(struct snd_ymfpci *chip, int device, struct snd_pcm ** rpcm)
  1098. {
  1099. struct snd_pcm *pcm;
  1100. int err;
  1101. if (rpcm)
  1102. *rpcm = NULL;
  1103. if ((err = snd_pcm_new(chip->card, "YMFPCI - IEC958", device, 1, 0, &pcm)) < 0)
  1104. return err;
  1105. pcm->private_data = chip;
  1106. snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_PLAYBACK, &snd_ymfpci_playback_spdif_ops);
  1107. /* global setup */
  1108. pcm->info_flags = 0;
  1109. strcpy(pcm->name, "YMFPCI - IEC958");
  1110. chip->pcm_spdif = pcm;
  1111. snd_pcm_lib_preallocate_pages_for_all(pcm, SNDRV_DMA_TYPE_DEV,
  1112. snd_dma_pci_data(chip->pci), 64*1024, 256*1024);
  1113. if (rpcm)
  1114. *rpcm = pcm;
  1115. return 0;
  1116. }
  1117. static struct snd_pcm_ops snd_ymfpci_playback_4ch_ops = {
  1118. .open = snd_ymfpci_playback_4ch_open,
  1119. .close = snd_ymfpci_playback_4ch_close,
  1120. .ioctl = snd_pcm_lib_ioctl,
  1121. .hw_params = snd_ymfpci_playback_hw_params,
  1122. .hw_free = snd_ymfpci_playback_hw_free,
  1123. .prepare = snd_ymfpci_playback_prepare,
  1124. .trigger = snd_ymfpci_playback_trigger,
  1125. .pointer = snd_ymfpci_playback_pointer,
  1126. };
  1127. int __devinit snd_ymfpci_pcm_4ch(struct snd_ymfpci *chip, int device, struct snd_pcm ** rpcm)
  1128. {
  1129. struct snd_pcm *pcm;
  1130. int err;
  1131. if (rpcm)
  1132. *rpcm = NULL;
  1133. if ((err = snd_pcm_new(chip->card, "YMFPCI - Rear", device, 1, 0, &pcm)) < 0)
  1134. return err;
  1135. pcm->private_data = chip;
  1136. snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_PLAYBACK, &snd_ymfpci_playback_4ch_ops);
  1137. /* global setup */
  1138. pcm->info_flags = 0;
  1139. strcpy(pcm->name, "YMFPCI - Rear PCM");
  1140. chip->pcm_4ch = pcm;
  1141. snd_pcm_lib_preallocate_pages_for_all(pcm, SNDRV_DMA_TYPE_DEV,
  1142. snd_dma_pci_data(chip->pci), 64*1024, 256*1024);
  1143. if (rpcm)
  1144. *rpcm = pcm;
  1145. return 0;
  1146. }
  1147. static int snd_ymfpci_spdif_default_info(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_info *uinfo)
  1148. {
  1149. uinfo->type = SNDRV_CTL_ELEM_TYPE_IEC958;
  1150. uinfo->count = 1;
  1151. return 0;
  1152. }
  1153. static int snd_ymfpci_spdif_default_get(struct snd_kcontrol *kcontrol,
  1154. struct snd_ctl_elem_value *ucontrol)
  1155. {
  1156. struct snd_ymfpci *chip = snd_kcontrol_chip(kcontrol);
  1157. spin_lock_irq(&chip->reg_lock);
  1158. ucontrol->value.iec958.status[0] = (chip->spdif_bits >> 0) & 0xff;
  1159. ucontrol->value.iec958.status[1] = (chip->spdif_bits >> 8) & 0xff;
  1160. ucontrol->value.iec958.status[3] = IEC958_AES3_CON_FS_48000;
  1161. spin_unlock_irq(&chip->reg_lock);
  1162. return 0;
  1163. }
  1164. static int snd_ymfpci_spdif_default_put(struct snd_kcontrol *kcontrol,
  1165. struct snd_ctl_elem_value *ucontrol)
  1166. {
  1167. struct snd_ymfpci *chip = snd_kcontrol_chip(kcontrol);
  1168. unsigned int val;
  1169. int change;
  1170. val = ((ucontrol->value.iec958.status[0] & 0x3e) << 0) |
  1171. (ucontrol->value.iec958.status[1] << 8);
  1172. spin_lock_irq(&chip->reg_lock);
  1173. change = chip->spdif_bits != val;
  1174. chip->spdif_bits = val;
  1175. if ((snd_ymfpci_readw(chip, YDSXGR_SPDIFOUTCTRL) & 1) && chip->pcm_spdif == NULL)
  1176. snd_ymfpci_writew(chip, YDSXGR_SPDIFOUTSTATUS, chip->spdif_bits);
  1177. spin_unlock_irq(&chip->reg_lock);
  1178. return change;
  1179. }
  1180. static struct snd_kcontrol_new snd_ymfpci_spdif_default __devinitdata =
  1181. {
  1182. .iface = SNDRV_CTL_ELEM_IFACE_PCM,
  1183. .name = SNDRV_CTL_NAME_IEC958("",PLAYBACK,DEFAULT),
  1184. .info = snd_ymfpci_spdif_default_info,
  1185. .get = snd_ymfpci_spdif_default_get,
  1186. .put = snd_ymfpci_spdif_default_put
  1187. };
  1188. static int snd_ymfpci_spdif_mask_info(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_info *uinfo)
  1189. {
  1190. uinfo->type = SNDRV_CTL_ELEM_TYPE_IEC958;
  1191. uinfo->count = 1;
  1192. return 0;
  1193. }
  1194. static int snd_ymfpci_spdif_mask_get(struct snd_kcontrol *kcontrol,
  1195. struct snd_ctl_elem_value *ucontrol)
  1196. {
  1197. struct snd_ymfpci *chip = snd_kcontrol_chip(kcontrol);
  1198. spin_lock_irq(&chip->reg_lock);
  1199. ucontrol->value.iec958.status[0] = 0x3e;
  1200. ucontrol->value.iec958.status[1] = 0xff;
  1201. spin_unlock_irq(&chip->reg_lock);
  1202. return 0;
  1203. }
  1204. static struct snd_kcontrol_new snd_ymfpci_spdif_mask __devinitdata =
  1205. {
  1206. .access = SNDRV_CTL_ELEM_ACCESS_READ,
  1207. .iface = SNDRV_CTL_ELEM_IFACE_PCM,
  1208. .name = SNDRV_CTL_NAME_IEC958("",PLAYBACK,CON_MASK),
  1209. .info = snd_ymfpci_spdif_mask_info,
  1210. .get = snd_ymfpci_spdif_mask_get,
  1211. };
  1212. static int snd_ymfpci_spdif_stream_info(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_info *uinfo)
  1213. {
  1214. uinfo->type = SNDRV_CTL_ELEM_TYPE_IEC958;
  1215. uinfo->count = 1;
  1216. return 0;
  1217. }
  1218. static int snd_ymfpci_spdif_stream_get(struct snd_kcontrol *kcontrol,
  1219. struct snd_ctl_elem_value *ucontrol)
  1220. {
  1221. struct snd_ymfpci *chip = snd_kcontrol_chip(kcontrol);
  1222. spin_lock_irq(&chip->reg_lock);
  1223. ucontrol->value.iec958.status[0] = (chip->spdif_pcm_bits >> 0) & 0xff;
  1224. ucontrol->value.iec958.status[1] = (chip->spdif_pcm_bits >> 8) & 0xff;
  1225. ucontrol->value.iec958.status[3] = IEC958_AES3_CON_FS_48000;
  1226. spin_unlock_irq(&chip->reg_lock);
  1227. return 0;
  1228. }
  1229. static int snd_ymfpci_spdif_stream_put(struct snd_kcontrol *kcontrol,
  1230. struct snd_ctl_elem_value *ucontrol)
  1231. {
  1232. struct snd_ymfpci *chip = snd_kcontrol_chip(kcontrol);
  1233. unsigned int val;
  1234. int change;
  1235. val = ((ucontrol->value.iec958.status[0] & 0x3e) << 0) |
  1236. (ucontrol->value.iec958.status[1] << 8);
  1237. spin_lock_irq(&chip->reg_lock);
  1238. change = chip->spdif_pcm_bits != val;
  1239. chip->spdif_pcm_bits = val;
  1240. if ((snd_ymfpci_readw(chip, YDSXGR_SPDIFOUTCTRL) & 2))
  1241. snd_ymfpci_writew(chip, YDSXGR_SPDIFOUTSTATUS, chip->spdif_pcm_bits);
  1242. spin_unlock_irq(&chip->reg_lock);
  1243. return change;
  1244. }
  1245. static struct snd_kcontrol_new snd_ymfpci_spdif_stream __devinitdata =
  1246. {
  1247. .access = SNDRV_CTL_ELEM_ACCESS_READWRITE | SNDRV_CTL_ELEM_ACCESS_INACTIVE,
  1248. .iface = SNDRV_CTL_ELEM_IFACE_PCM,
  1249. .name = SNDRV_CTL_NAME_IEC958("",PLAYBACK,PCM_STREAM),
  1250. .info = snd_ymfpci_spdif_stream_info,
  1251. .get = snd_ymfpci_spdif_stream_get,
  1252. .put = snd_ymfpci_spdif_stream_put
  1253. };
  1254. static int snd_ymfpci_drec_source_info(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_info *info)
  1255. {
  1256. static const char *const texts[3] = {"AC'97", "IEC958", "ZV Port"};
  1257. return snd_ctl_enum_info(info, 1, 3, texts);
  1258. }
  1259. static int snd_ymfpci_drec_source_get(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *value)
  1260. {
  1261. struct snd_ymfpci *chip = snd_kcontrol_chip(kcontrol);
  1262. u16 reg;
  1263. spin_lock_irq(&chip->reg_lock);
  1264. reg = snd_ymfpci_readw(chip, YDSXGR_GLOBALCTRL);
  1265. spin_unlock_irq(&chip->reg_lock);
  1266. if (!(reg & 0x100))
  1267. value->value.enumerated.item[0] = 0;
  1268. else
  1269. value->value.enumerated.item[0] = 1 + ((reg & 0x200) != 0);
  1270. return 0;
  1271. }
  1272. static int snd_ymfpci_drec_source_put(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *value)
  1273. {
  1274. struct snd_ymfpci *chip = snd_kcontrol_chip(kcontrol);
  1275. u16 reg, old_reg;
  1276. spin_lock_irq(&chip->reg_lock);
  1277. old_reg = snd_ymfpci_readw(chip, YDSXGR_GLOBALCTRL);
  1278. if (value->value.enumerated.item[0] == 0)
  1279. reg = old_reg & ~0x100;
  1280. else
  1281. reg = (old_reg & ~0x300) | 0x100 | ((value->value.enumerated.item[0] == 2) << 9);
  1282. snd_ymfpci_writew(chip, YDSXGR_GLOBALCTRL, reg);
  1283. spin_unlock_irq(&chip->reg_lock);
  1284. return reg != old_reg;
  1285. }
  1286. static struct snd_kcontrol_new snd_ymfpci_drec_source __devinitdata = {
  1287. .access = SNDRV_CTL_ELEM_ACCESS_READWRITE,
  1288. .iface = SNDRV_CTL_ELEM_IFACE_MIXER,
  1289. .name = "Direct Recording Source",
  1290. .info = snd_ymfpci_drec_source_info,
  1291. .get = snd_ymfpci_drec_source_get,
  1292. .put = snd_ymfpci_drec_source_put
  1293. };
  1294. /*
  1295. * Mixer controls
  1296. */
  1297. #define YMFPCI_SINGLE(xname, xindex, reg, shift) \
  1298. { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = xname, .index = xindex, \
  1299. .info = snd_ymfpci_info_single, \
  1300. .get = snd_ymfpci_get_single, .put = snd_ymfpci_put_single, \
  1301. .private_value = ((reg) | ((shift) << 16)) }
  1302. #define snd_ymfpci_info_single snd_ctl_boolean_mono_info
  1303. static int snd_ymfpci_get_single(struct snd_kcontrol *kcontrol,
  1304. struct snd_ctl_elem_value *ucontrol)
  1305. {
  1306. struct snd_ymfpci *chip = snd_kcontrol_chip(kcontrol);
  1307. int reg = kcontrol->private_value & 0xffff;
  1308. unsigned int shift = (kcontrol->private_value >> 16) & 0xff;
  1309. unsigned int mask = 1;
  1310. switch (reg) {
  1311. case YDSXGR_SPDIFOUTCTRL: break;
  1312. case YDSXGR_SPDIFINCTRL: break;
  1313. default: return -EINVAL;
  1314. }
  1315. ucontrol->value.integer.value[0] =
  1316. (snd_ymfpci_readl(chip, reg) >> shift) & mask;
  1317. return 0;
  1318. }
  1319. static int snd_ymfpci_put_single(struct snd_kcontrol *kcontrol,
  1320. struct snd_ctl_elem_value *ucontrol)
  1321. {
  1322. struct snd_ymfpci *chip = snd_kcontrol_chip(kcontrol);
  1323. int reg = kcontrol->private_value & 0xffff;
  1324. unsigned int shift = (kcontrol->private_value >> 16) & 0xff;
  1325. unsigned int mask = 1;
  1326. int change;
  1327. unsigned int val, oval;
  1328. switch (reg) {
  1329. case YDSXGR_SPDIFOUTCTRL: break;
  1330. case YDSXGR_SPDIFINCTRL: break;
  1331. default: return -EINVAL;
  1332. }
  1333. val = (ucontrol->value.integer.value[0] & mask);
  1334. val <<= shift;
  1335. spin_lock_irq(&chip->reg_lock);
  1336. oval = snd_ymfpci_readl(chip, reg);
  1337. val = (oval & ~(mask << shift)) | val;
  1338. change = val != oval;
  1339. snd_ymfpci_writel(chip, reg, val);
  1340. spin_unlock_irq(&chip->reg_lock);
  1341. return change;
  1342. }
  1343. static const DECLARE_TLV_DB_LINEAR(db_scale_native, TLV_DB_GAIN_MUTE, 0);
  1344. #define YMFPCI_DOUBLE(xname, xindex, reg) \
  1345. { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = xname, .index = xindex, \
  1346. .access = SNDRV_CTL_ELEM_ACCESS_READWRITE | SNDRV_CTL_ELEM_ACCESS_TLV_READ, \
  1347. .info = snd_ymfpci_info_double, \
  1348. .get = snd_ymfpci_get_double, .put = snd_ymfpci_put_double, \
  1349. .private_value = reg, \
  1350. .tlv = { .p = db_scale_native } }
  1351. static int snd_ymfpci_info_double(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_info *uinfo)
  1352. {
  1353. unsigned int reg = kcontrol->private_value;
  1354. if (reg < 0x80 || reg >= 0xc0)
  1355. return -EINVAL;
  1356. uinfo->type = SNDRV_CTL_ELEM_TYPE_INTEGER;
  1357. uinfo->count = 2;
  1358. uinfo->value.integer.min = 0;
  1359. uinfo->value.integer.max = 16383;
  1360. return 0;
  1361. }
  1362. static int snd_ymfpci_get_double(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
  1363. {
  1364. struct snd_ymfpci *chip = snd_kcontrol_chip(kcontrol);
  1365. unsigned int reg = kcontrol->private_value;
  1366. unsigned int shift_left = 0, shift_right = 16, mask = 16383;
  1367. unsigned int val;
  1368. if (reg < 0x80 || reg >= 0xc0)
  1369. return -EINVAL;
  1370. spin_lock_irq(&chip->reg_lock);
  1371. val = snd_ymfpci_readl(chip, reg);
  1372. spin_unlock_irq(&chip->reg_lock);
  1373. ucontrol->value.integer.value[0] = (val >> shift_left) & mask;
  1374. ucontrol->value.integer.value[1] = (val >> shift_right) & mask;
  1375. return 0;
  1376. }
  1377. static int snd_ymfpci_put_double(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
  1378. {
  1379. struct snd_ymfpci *chip = snd_kcontrol_chip(kcontrol);
  1380. unsigned int reg = kcontrol->private_value;
  1381. unsigned int shift_left = 0, shift_right = 16, mask = 16383;
  1382. int change;
  1383. unsigned int val1, val2, oval;
  1384. if (reg < 0x80 || reg >= 0xc0)
  1385. return -EINVAL;
  1386. val1 = ucontrol->value.integer.value[0] & mask;
  1387. val2 = ucontrol->value.integer.value[1] & mask;
  1388. val1 <<= shift_left;
  1389. val2 <<= shift_right;
  1390. spin_lock_irq(&chip->reg_lock);
  1391. oval = snd_ymfpci_readl(chip, reg);
  1392. val1 = (oval & ~((mask << shift_left) | (mask << shift_right))) | val1 | val2;
  1393. change = val1 != oval;
  1394. snd_ymfpci_writel(chip, reg, val1);
  1395. spin_unlock_irq(&chip->reg_lock);
  1396. return change;
  1397. }
  1398. static int snd_ymfpci_put_nativedacvol(struct snd_kcontrol *kcontrol,
  1399. struct snd_ctl_elem_value *ucontrol)
  1400. {
  1401. struct snd_ymfpci *chip = snd_kcontrol_chip(kcontrol);
  1402. unsigned int reg = YDSXGR_NATIVEDACOUTVOL;
  1403. unsigned int reg2 = YDSXGR_BUF441OUTVOL;
  1404. int change;
  1405. unsigned int value, oval;
  1406. value = ucontrol->value.integer.value[0] & 0x3fff;
  1407. value |= (ucontrol->value.integer.value[1] & 0x3fff) << 16;
  1408. spin_lock_irq(&chip->reg_lock);
  1409. oval = snd_ymfpci_readl(chip, reg);
  1410. change = value != oval;
  1411. snd_ymfpci_writel(chip, reg, value);
  1412. snd_ymfpci_writel(chip, reg2, value);
  1413. spin_unlock_irq(&chip->reg_lock);
  1414. return change;
  1415. }
  1416. /*
  1417. * 4ch duplication
  1418. */
  1419. #define snd_ymfpci_info_dup4ch snd_ctl_boolean_mono_info
  1420. static int snd_ymfpci_get_dup4ch(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
  1421. {
  1422. struct snd_ymfpci *chip = snd_kcontrol_chip(kcontrol);
  1423. ucontrol->value.integer.value[0] = chip->mode_dup4ch;
  1424. return 0;
  1425. }
  1426. static int snd_ymfpci_put_dup4ch(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
  1427. {
  1428. struct snd_ymfpci *chip = snd_kcontrol_chip(kcontrol);
  1429. int change;
  1430. change = (ucontrol->value.integer.value[0] != chip->mode_dup4ch);
  1431. if (change)
  1432. chip->mode_dup4ch = !!ucontrol->value.integer.value[0];
  1433. return change;
  1434. }
  1435. static struct snd_kcontrol_new snd_ymfpci_controls[] __devinitdata = {
  1436. {
  1437. .iface = SNDRV_CTL_ELEM_IFACE_MIXER,
  1438. .name = "Wave Playback Volume",
  1439. .access = SNDRV_CTL_ELEM_ACCESS_READWRITE |
  1440. SNDRV_CTL_ELEM_ACCESS_TLV_READ,
  1441. .info = snd_ymfpci_info_double,
  1442. .get = snd_ymfpci_get_double,
  1443. .put = snd_ymfpci_put_nativedacvol,
  1444. .private_value = YDSXGR_NATIVEDACOUTVOL,
  1445. .tlv = { .p = db_scale_native },
  1446. },
  1447. YMFPCI_DOUBLE("Wave Capture Volume", 0, YDSXGR_NATIVEDACLOOPVOL),
  1448. YMFPCI_DOUBLE("Digital Capture Volume", 0, YDSXGR_NATIVEDACINVOL),
  1449. YMFPCI_DOUBLE("Digital Capture Volume", 1, YDSXGR_NATIVEADCINVOL),
  1450. YMFPCI_DOUBLE("ADC Playback Volume", 0, YDSXGR_PRIADCOUTVOL),
  1451. YMFPCI_DOUBLE("ADC Capture Volume", 0, YDSXGR_PRIADCLOOPVOL),
  1452. YMFPCI_DOUBLE("ADC Playback Volume", 1, YDSXGR_SECADCOUTVOL),
  1453. YMFPCI_DOUBLE("ADC Capture Volume", 1, YDSXGR_SECADCLOOPVOL),
  1454. YMFPCI_DOUBLE("FM Legacy Playback Volume", 0, YDSXGR_LEGACYOUTVOL),
  1455. YMFPCI_DOUBLE(SNDRV_CTL_NAME_IEC958("AC97 ", PLAYBACK,VOLUME), 0, YDSXGR_ZVOUTVOL),
  1456. YMFPCI_DOUBLE(SNDRV_CTL_NAME_IEC958("", CAPTURE,VOLUME), 0, YDSXGR_ZVLOOPVOL),
  1457. YMFPCI_DOUBLE(SNDRV_CTL_NAME_IEC958("AC97 ",PLAYBACK,VOLUME), 1, YDSXGR_SPDIFOUTVOL),
  1458. YMFPCI_DOUBLE(SNDRV_CTL_NAME_IEC958("",CAPTURE,VOLUME), 1, YDSXGR_SPDIFLOOPVOL),
  1459. YMFPCI_SINGLE(SNDRV_CTL_NAME_IEC958("",PLAYBACK,SWITCH), 0, YDSXGR_SPDIFOUTCTRL, 0),
  1460. YMFPCI_SINGLE(SNDRV_CTL_NAME_IEC958("",CAPTURE,SWITCH), 0, YDSXGR_SPDIFINCTRL, 0),
  1461. YMFPCI_SINGLE(SNDRV_CTL_NAME_IEC958("Loop",NONE,NONE), 0, YDSXGR_SPDIFINCTRL, 4),
  1462. {
  1463. .iface = SNDRV_CTL_ELEM_IFACE_MIXER,
  1464. .name = "4ch Duplication",
  1465. .info = snd_ymfpci_info_dup4ch,
  1466. .get = snd_ymfpci_get_dup4ch,
  1467. .put = snd_ymfpci_put_dup4ch,
  1468. },
  1469. };
  1470. /*
  1471. * GPIO
  1472. */
  1473. static int snd_ymfpci_get_gpio_out(struct snd_ymfpci *chip, int pin)
  1474. {
  1475. u16 reg, mode;
  1476. unsigned long flags;
  1477. spin_lock_irqsave(&chip->reg_lock, flags);
  1478. reg = snd_ymfpci_readw(chip, YDSXGR_GPIOFUNCENABLE);
  1479. reg &= ~(1 << (pin + 8));
  1480. reg |= (1 << pin);
  1481. snd_ymfpci_writew(chip, YDSXGR_GPIOFUNCENABLE, reg);
  1482. /* set the level mode for input line */
  1483. mode = snd_ymfpci_readw(chip, YDSXGR_GPIOTYPECONFIG);
  1484. mode &= ~(3 << (pin * 2));
  1485. snd_ymfpci_writew(chip, YDSXGR_GPIOTYPECONFIG, mode);
  1486. snd_ymfpci_writew(chip, YDSXGR_GPIOFUNCENABLE, reg | (1 << (pin + 8)));
  1487. mode = snd_ymfpci_readw(chip, YDSXGR_GPIOINSTATUS);
  1488. spin_unlock_irqrestore(&chip->reg_lock, flags);
  1489. return (mode >> pin) & 1;
  1490. }
  1491. static int snd_ymfpci_set_gpio_out(struct snd_ymfpci *chip, int pin, int enable)
  1492. {
  1493. u16 reg;
  1494. unsigned long flags;
  1495. spin_lock_irqsave(&chip->reg_lock, flags);
  1496. reg = snd_ymfpci_readw(chip, YDSXGR_GPIOFUNCENABLE);
  1497. reg &= ~(1 << pin);
  1498. reg &= ~(1 << (pin + 8));
  1499. snd_ymfpci_writew(chip, YDSXGR_GPIOFUNCENABLE, reg);
  1500. snd_ymfpci_writew(chip, YDSXGR_GPIOOUTCTRL, enable << pin);
  1501. snd_ymfpci_writew(chip, YDSXGR_GPIOFUNCENABLE, reg | (1 << (pin + 8)));
  1502. spin_unlock_irqrestore(&chip->reg_lock, flags);
  1503. return 0;
  1504. }
  1505. #define snd_ymfpci_gpio_sw_info snd_ctl_boolean_mono_info
  1506. static int snd_ymfpci_gpio_sw_get(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
  1507. {
  1508. struct snd_ymfpci *chip = snd_kcontrol_chip(kcontrol);
  1509. int pin = (int)kcontrol->private_value;
  1510. ucontrol->value.integer.value[0] = snd_ymfpci_get_gpio_out(chip, pin);
  1511. return 0;
  1512. }
  1513. static int snd_ymfpci_gpio_sw_put(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
  1514. {
  1515. struct snd_ymfpci *chip = snd_kcontrol_chip(kcontrol);
  1516. int pin = (int)kcontrol->private_value;
  1517. if (snd_ymfpci_get_gpio_out(chip, pin) != ucontrol->value.integer.value[0]) {
  1518. snd_ymfpci_set_gpio_out(chip, pin, !!ucontrol->value.integer.value[0]);
  1519. ucontrol->value.integer.value[0] = snd_ymfpci_get_gpio_out(chip, pin);
  1520. return 1;
  1521. }
  1522. return 0;
  1523. }
  1524. static struct snd_kcontrol_new snd_ymfpci_rear_shared __devinitdata = {
  1525. .name = "Shared Rear/Line-In Switch",
  1526. .iface = SNDRV_CTL_ELEM_IFACE_MIXER,
  1527. .info = snd_ymfpci_gpio_sw_info,
  1528. .get = snd_ymfpci_gpio_sw_get,
  1529. .put = snd_ymfpci_gpio_sw_put,
  1530. .private_value = 2,
  1531. };
  1532. /*
  1533. * PCM voice volume
  1534. */
  1535. static int snd_ymfpci_pcm_vol_info(struct snd_kcontrol *kcontrol,
  1536. struct snd_ctl_elem_info *uinfo)
  1537. {
  1538. uinfo->type = SNDRV_CTL_ELEM_TYPE_INTEGER;
  1539. uinfo->count = 2;
  1540. uinfo->value.integer.min = 0;
  1541. uinfo->value.integer.max = 0x8000;
  1542. return 0;
  1543. }
  1544. static int snd_ymfpci_pcm_vol_get(struct snd_kcontrol *kcontrol,
  1545. struct snd_ctl_elem_value *ucontrol)
  1546. {
  1547. struct snd_ymfpci *chip = snd_kcontrol_chip(kcontrol);
  1548. unsigned int subs = kcontrol->id.subdevice;
  1549. ucontrol->value.integer.value[0] = chip->pcm_mixer[subs].left;
  1550. ucontrol->value.integer.value[1] = chip->pcm_mixer[subs].right;
  1551. return 0;
  1552. }
  1553. static int snd_ymfpci_pcm_vol_put(struct snd_kcontrol *kcontrol,
  1554. struct snd_ctl_elem_value *ucontrol)
  1555. {
  1556. struct snd_ymfpci *chip = snd_kcontrol_chip(kcontrol);
  1557. unsigned int subs = kcontrol->id.subdevice;
  1558. struct snd_pcm_substream *substream;
  1559. unsigned long flags;
  1560. if (ucontrol->value.integer.value[0] != chip->pcm_mixer[subs].left ||
  1561. ucontrol->value.integer.value[1] != chip->pcm_mixer[subs].right) {
  1562. chip->pcm_mixer[subs].left = ucontrol->value.integer.value[0];
  1563. chip->pcm_mixer[subs].right = ucontrol->value.integer.value[1];
  1564. if (chip->pcm_mixer[subs].left > 0x8000)
  1565. chip->pcm_mixer[subs].left = 0x8000;
  1566. if (chip->pcm_mixer[subs].right > 0x8000)
  1567. chip->pcm_mixer[subs].right = 0x8000;
  1568. substream = (struct snd_pcm_substream *)kcontrol->private_value;
  1569. spin_lock_irqsave(&chip->voice_lock, flags);
  1570. if (substream->runtime && substream->runtime->private_data) {
  1571. struct snd_ymfpci_pcm *ypcm = substream->runtime->private_data;
  1572. if (!ypcm->use_441_slot)
  1573. ypcm->update_pcm_vol = 2;
  1574. }
  1575. spin_unlock_irqrestore(&chip->voice_lock, flags);
  1576. return 1;
  1577. }
  1578. return 0;
  1579. }
  1580. static struct snd_kcontrol_new snd_ymfpci_pcm_volume __devinitdata = {
  1581. .iface = SNDRV_CTL_ELEM_IFACE_PCM,
  1582. .name = "PCM Playback Volume",
  1583. .access = SNDRV_CTL_ELEM_ACCESS_READWRITE |
  1584. SNDRV_CTL_ELEM_ACCESS_INACTIVE,
  1585. .info = snd_ymfpci_pcm_vol_info,
  1586. .get = snd_ymfpci_pcm_vol_get,
  1587. .put = snd_ymfpci_pcm_vol_put,
  1588. };
  1589. /*
  1590. * Mixer routines
  1591. */
  1592. static void snd_ymfpci_mixer_free_ac97_bus(struct snd_ac97_bus *bus)
  1593. {
  1594. struct snd_ymfpci *chip = bus->private_data;
  1595. chip->ac97_bus = NULL;
  1596. }
  1597. static void snd_ymfpci_mixer_free_ac97(struct snd_ac97 *ac97)
  1598. {
  1599. struct snd_ymfpci *chip = ac97->private_data;
  1600. chip->ac97 = NULL;
  1601. }
  1602. int __devinit snd_ymfpci_mixer(struct snd_ymfpci *chip, int rear_switch)
  1603. {
  1604. struct snd_ac97_template ac97;
  1605. struct snd_kcontrol *kctl;
  1606. struct snd_pcm_substream *substream;
  1607. unsigned int idx;
  1608. int err;
  1609. static struct snd_ac97_bus_ops ops = {
  1610. .write = snd_ymfpci_codec_write,
  1611. .read = snd_ymfpci_codec_read,
  1612. };
  1613. if ((err = snd_ac97_bus(chip->card, 0, &ops, chip, &chip->ac97_bus)) < 0)
  1614. return err;
  1615. chip->ac97_bus->private_free = snd_ymfpci_mixer_free_ac97_bus;
  1616. chip->ac97_bus->no_vra = 1; /* YMFPCI doesn't need VRA */
  1617. memset(&ac97, 0, sizeof(ac97));
  1618. ac97.private_data = chip;
  1619. ac97.private_free = snd_ymfpci_mixer_free_ac97;
  1620. if ((err = snd_ac97_mixer(chip->ac97_bus, &ac97, &chip->ac97)) < 0)
  1621. return err;
  1622. /* to be sure */
  1623. snd_ac97_update_bits(chip->ac97, AC97_EXTENDED_STATUS,
  1624. AC97_EA_VRA|AC97_EA_VRM, 0);
  1625. for (idx = 0; idx < ARRAY_SIZE(snd_ymfpci_controls); idx++) {
  1626. if ((err = snd_ctl_add(chip->card, snd_ctl_new1(&snd_ymfpci_controls[idx], chip))) < 0)
  1627. return err;
  1628. }
  1629. /* add S/PDIF control */
  1630. if (snd_BUG_ON(!chip->pcm_spdif))
  1631. return -ENXIO;
  1632. if ((err = snd_ctl_add(chip->card, kctl = snd_ctl_new1(&snd_ymfpci_spdif_default, chip))) < 0)
  1633. return err;
  1634. kctl->id.device = chip->pcm_spdif->device;
  1635. if ((err = snd_ctl_add(chip->card, kctl = snd_ctl_new1(&snd_ymfpci_spdif_mask, chip))) < 0)
  1636. return err;
  1637. kctl->id.device = chip->pcm_spdif->device;
  1638. if ((err = snd_ctl_add(chip->card, kctl = snd_ctl_new1(&snd_ymfpci_spdif_stream, chip))) < 0)
  1639. return err;
  1640. kctl->id.device = chip->pcm_spdif->device;
  1641. chip->spdif_pcm_ctl = kctl;
  1642. /* direct recording source */
  1643. if (chip->device_id == PCI_DEVICE_ID_YAMAHA_754 &&
  1644. (err = snd_ctl_add(chip->card, kctl = snd_ctl_new1(&snd_ymfpci_drec_source, chip))) < 0)
  1645. return err;
  1646. /*
  1647. * shared rear/line-in
  1648. */
  1649. if (rear_switch) {
  1650. if ((err = snd_ctl_add(chip->card, snd_ctl_new1(&snd_ymfpci_rear_shared, chip))) < 0)
  1651. return err;
  1652. }
  1653. /* per-voice volume */
  1654. substream = chip->pcm->streams[SNDRV_PCM_STREAM_PLAYBACK].substream;
  1655. for (idx = 0; idx < 32; ++idx) {
  1656. kctl = snd_ctl_new1(&snd_ymfpci_pcm_volume, chip);
  1657. if (!kctl)
  1658. return -ENOMEM;
  1659. kctl->id.device = chip->pcm->device;
  1660. kctl->id.subdevice = idx;
  1661. kctl->private_value = (unsigned long)substream;
  1662. if ((err = snd_ctl_add(chip->card, kctl)) < 0)
  1663. return err;
  1664. chip->pcm_mixer[idx].left = 0x8000;
  1665. chip->pcm_mixer[idx].right = 0x8000;
  1666. chip->pcm_mixer[idx].ctl = kctl;
  1667. substream = substream->next;
  1668. }
  1669. return 0;
  1670. }
  1671. /*
  1672. * timer
  1673. */
  1674. static int snd_ymfpci_timer_start(struct snd_timer *timer)
  1675. {
  1676. struct snd_ymfpci *chip;
  1677. unsigned long flags;
  1678. unsigned int count;
  1679. chip = snd_timer_chip(timer);
  1680. spin_lock_irqsave(&chip->reg_lock, flags);
  1681. if (timer->sticks > 1) {
  1682. chip->timer_ticks = timer->sticks;
  1683. count = timer->sticks - 1;
  1684. } else {
  1685. /*
  1686. * Divisor 1 is not allowed; fake it by using divisor 2 and
  1687. * counting two ticks for each interrupt.
  1688. */
  1689. chip->timer_ticks = 2;
  1690. count = 2 - 1;
  1691. }
  1692. snd_ymfpci_writew(chip, YDSXGR_TIMERCOUNT, count);
  1693. snd_ymfpci_writeb(chip, YDSXGR_TIMERCTRL, 0x03);
  1694. spin_unlock_irqrestore(&chip->reg_lock, flags);
  1695. return 0;
  1696. }
  1697. static int snd_ymfpci_timer_stop(struct snd_timer *timer)
  1698. {
  1699. struct snd_ymfpci *chip;
  1700. unsigned long flags;
  1701. chip = snd_timer_chip(timer);
  1702. spin_lock_irqsave(&chip->reg_lock, flags);
  1703. snd_ymfpci_writeb(chip, YDSXGR_TIMERCTRL, 0x00);
  1704. spin_unlock_irqrestore(&chip->reg_lock, flags);
  1705. return 0;
  1706. }
  1707. static int snd_ymfpci_timer_precise_resolution(struct snd_timer *timer,
  1708. unsigned long *num, unsigned long *den)
  1709. {
  1710. *num = 1;
  1711. *den = 96000;
  1712. return 0;
  1713. }
  1714. static struct snd_timer_hardware snd_ymfpci_timer_hw = {
  1715. .flags = SNDRV_TIMER_HW_AUTO,
  1716. .resolution = 10417, /* 1 / 96 kHz = 10.41666...us */
  1717. .ticks = 0x10000,
  1718. .start = snd_ymfpci_timer_start,
  1719. .stop = snd_ymfpci_timer_stop,
  1720. .precise_resolution = snd_ymfpci_timer_precise_resolution,
  1721. };
  1722. int __devinit snd_ymfpci_timer(struct snd_ymfpci *chip, int device)
  1723. {
  1724. struct snd_timer *timer = NULL;
  1725. struct snd_timer_id tid;
  1726. int err;
  1727. tid.dev_class = SNDRV_TIMER_CLASS_CARD;
  1728. tid.dev_sclass = SNDRV_TIMER_SCLASS_NONE;
  1729. tid.card = chip->card->number;
  1730. tid.device = device;
  1731. tid.subdevice = 0;
  1732. if ((err = snd_timer_new(chip->card, "YMFPCI", &tid, &timer)) >= 0) {
  1733. strcpy(timer->name, "YMFPCI timer");
  1734. timer->private_data = chip;
  1735. timer->hw = snd_ymfpci_timer_hw;
  1736. }
  1737. chip->timer = timer;
  1738. return err;
  1739. }
  1740. /*
  1741. * proc interface
  1742. */
  1743. static void snd_ymfpci_proc_read(struct snd_info_entry *entry,
  1744. struct snd_info_buffer *buffer)
  1745. {
  1746. struct snd_ymfpci *chip = entry->private_data;
  1747. int i;
  1748. snd_iprintf(buffer, "YMFPCI\n\n");
  1749. for (i = 0; i <= YDSXGR_WORKBASE; i += 4)
  1750. snd_iprintf(buffer, "%04x: %04x\n", i, snd_ymfpci_readl(chip, i));
  1751. }
  1752. static int __devinit snd_ymfpci_proc_init(struct snd_card *card, struct snd_ymfpci *chip)
  1753. {
  1754. struct snd_info_entry *entry;
  1755. if (! snd_card_proc_new(card, "ymfpci", &entry))
  1756. snd_info_set_text_ops(entry, chip, snd_ymfpci_proc_read);
  1757. return 0;
  1758. }
  1759. /*
  1760. * initialization routines
  1761. */
  1762. static void snd_ymfpci_aclink_reset(struct pci_dev * pci)
  1763. {
  1764. u8 cmd;
  1765. pci_read_config_byte(pci, PCIR_DSXG_CTRL, &cmd);
  1766. #if 0 // force to reset
  1767. if (cmd & 0x03) {
  1768. #endif
  1769. pci_write_config_byte(pci, PCIR_DSXG_CTRL, cmd & 0xfc);
  1770. pci_write_config_byte(pci, PCIR_DSXG_CTRL, cmd | 0x03);
  1771. pci_write_config_byte(pci, PCIR_DSXG_CTRL, cmd & 0xfc);
  1772. pci_write_config_word(pci, PCIR_DSXG_PWRCTRL1, 0);
  1773. pci_write_config_word(pci, PCIR_DSXG_PWRCTRL2, 0);
  1774. #if 0
  1775. }
  1776. #endif
  1777. }
  1778. static void snd_ymfpci_enable_dsp(struct snd_ymfpci *chip)
  1779. {
  1780. snd_ymfpci_writel(chip, YDSXGR_CONFIG, 0x00000001);
  1781. }
  1782. static void snd_ymfpci_disable_dsp(struct snd_ymfpci *chip)
  1783. {
  1784. u32 val;
  1785. int timeout = 1000;
  1786. val = snd_ymfpci_readl(chip, YDSXGR_CONFIG);
  1787. if (val)
  1788. snd_ymfpci_writel(chip, YDSXGR_CONFIG, 0x00000000);
  1789. while (timeout-- > 0) {
  1790. val = snd_ymfpci_readl(chip, YDSXGR_STATUS);
  1791. if ((val & 0x00000002) == 0)
  1792. break;
  1793. }
  1794. }
  1795. static int snd_ymfpci_request_firmware(struct snd_ymfpci *chip)
  1796. {
  1797. int err, is_1e;
  1798. const char *name;
  1799. err = request_firmware(&chip->dsp_microcode, "yamaha/ds1_dsp.fw",
  1800. &chip->pci->dev);
  1801. if (err >= 0) {
  1802. if (chip->dsp_microcode->size != YDSXG_DSPLENGTH) {
  1803. snd_printk(KERN_ERR "DSP microcode has wrong size\n");
  1804. err = -EINVAL;
  1805. }
  1806. }
  1807. if (err < 0)
  1808. return err;
  1809. is_1e = chip->device_id == PCI_DEVICE_ID_YAMAHA_724F ||
  1810. chip->device_id == PCI_DEVICE_ID_YAMAHA_740C ||
  1811. chip->device_id == PCI_DEVICE_ID_YAMAHA_744 ||
  1812. chip->device_id == PCI_DEVICE_ID_YAMAHA_754;
  1813. name = is_1e ? "yamaha/ds1e_ctrl.fw" : "yamaha/ds1_ctrl.fw";
  1814. err = request_firmware(&chip->controller_microcode, name,
  1815. &chip->pci->dev);
  1816. if (err >= 0) {
  1817. if (chip->controller_microcode->size != YDSXG_CTRLLENGTH) {
  1818. snd_printk(KERN_ERR "controller microcode"
  1819. " has wrong size\n");
  1820. err = -EINVAL;
  1821. }
  1822. }
  1823. if (err < 0)
  1824. return err;
  1825. return 0;
  1826. }
  1827. MODULE_FIRMWARE("yamaha/ds1_dsp.fw");
  1828. MODULE_FIRMWARE("yamaha/ds1_ctrl.fw");
  1829. MODULE_FIRMWARE("yamaha/ds1e_ctrl.fw");
  1830. static void snd_ymfpci_download_image(struct snd_ymfpci *chip)
  1831. {
  1832. int i;
  1833. u16 ctrl;
  1834. const __le32 *inst;
  1835. snd_ymfpci_writel(chip, YDSXGR_NATIVEDACOUTVOL, 0x00000000);
  1836. snd_ymfpci_disable_dsp(chip);
  1837. snd_ymfpci_writel(chip, YDSXGR_MODE, 0x00010000);
  1838. snd_ymfpci_writel(chip, YDSXGR_MODE, 0x00000000);
  1839. snd_ymfpci_writel(chip, YDSXGR_MAPOFREC, 0x00000000);
  1840. snd_ymfpci_writel(chip, YDSXGR_MAPOFEFFECT, 0x00000000);
  1841. snd_ymfpci_writel(chip, YDSXGR_PLAYCTRLBASE, 0x00000000);
  1842. snd_ymfpci_writel(chip, YDSXGR_RECCTRLBASE, 0x00000000);
  1843. snd_ymfpci_writel(chip, YDSXGR_EFFCTRLBASE, 0x00000000);
  1844. ctrl = snd_ymfpci_readw(chip, YDSXGR_GLOBALCTRL);
  1845. snd_ymfpci_writew(chip, YDSXGR_GLOBALCTRL, ctrl & ~0x0007);
  1846. /* setup DSP instruction code */
  1847. inst = (const __le32 *)chip->dsp_microcode->data;
  1848. for (i = 0; i < YDSXG_DSPLENGTH / 4; i++)
  1849. snd_ymfpci_writel(chip, YDSXGR_DSPINSTRAM + (i << 2),
  1850. le32_to_cpu(inst[i]));
  1851. /* setup control instruction code */
  1852. inst = (const __le32 *)chip->controller_microcode->data;
  1853. for (i = 0; i < YDSXG_CTRLLENGTH / 4; i++)
  1854. snd_ymfpci_writel(chip, YDSXGR_CTRLINSTRAM + (i << 2),
  1855. le32_to_cpu(inst[i]));
  1856. snd_ymfpci_enable_dsp(chip);
  1857. }
  1858. static int __devinit snd_ymfpci_memalloc(struct snd_ymfpci *chip)
  1859. {
  1860. long size, playback_ctrl_size;
  1861. int voice, bank, reg;
  1862. u8 *ptr;
  1863. dma_addr_t ptr_addr;
  1864. playback_ctrl_size = 4 + 4 * YDSXG_PLAYBACK_VOICES;
  1865. chip->bank_size_playback = snd_ymfpci_readl(chip, YDSXGR_PLAYCTRLSIZE) << 2;
  1866. chip->bank_size_capture = snd_ymfpci_readl(chip, YDSXGR_RECCTRLSIZE) << 2;
  1867. chip->bank_size_effect = snd_ymfpci_readl(chip, YDSXGR_EFFCTRLSIZE) << 2;
  1868. chip->work_size = YDSXG_DEFAULT_WORK_SIZE;
  1869. size = ALIGN(playback_ctrl_size, 0x100) +
  1870. ALIGN(chip->bank_size_playback * 2 * YDSXG_PLAYBACK_VOICES, 0x100) +
  1871. ALIGN(chip->bank_size_capture * 2 * YDSXG_CAPTURE_VOICES, 0x100) +
  1872. ALIGN(chip->bank_size_effect * 2 * YDSXG_EFFECT_VOICES, 0x100) +
  1873. chip->work_size;
  1874. /* work_ptr must be aligned to 256 bytes, but it's already
  1875. covered with the kernel page allocation mechanism */
  1876. if (snd_dma_alloc_pages(SNDRV_DMA_TYPE_DEV, snd_dma_pci_data(chip->pci),
  1877. size, &chip->work_ptr) < 0)
  1878. return -ENOMEM;
  1879. ptr = chip->work_ptr.area;
  1880. ptr_addr = chip->work_ptr.addr;
  1881. memset(ptr, 0, size); /* for sure */
  1882. chip->bank_base_playback = ptr;
  1883. chip->bank_base_playback_addr = ptr_addr;
  1884. chip->ctrl_playback = (u32 *)ptr;
  1885. chip->ctrl_playback[0] = cpu_to_le32(YDSXG_PLAYBACK_VOICES);
  1886. ptr += ALIGN(playback_ctrl_size, 0x100);
  1887. ptr_addr += ALIGN(playback_ctrl_size, 0x100);
  1888. for (voice = 0; voice < YDSXG_PLAYBACK_VOICES; voice++) {
  1889. chip->voices[voice].number = voice;
  1890. chip->voices[voice].bank = (struct snd_ymfpci_playback_bank *)ptr;
  1891. chip->voices[voice].bank_addr = ptr_addr;
  1892. for (bank = 0; bank < 2; bank++) {
  1893. chip->bank_playback[voice][bank] = (struct snd_ymfpci_playback_bank *)ptr;
  1894. ptr += chip->bank_size_playback;
  1895. ptr_addr += chip->bank_size_playback;
  1896. }
  1897. }
  1898. ptr = (char *)ALIGN((unsigned long)ptr, 0x100);
  1899. ptr_addr = ALIGN(ptr_addr, 0x100);
  1900. chip->bank_base_capture = ptr;
  1901. chip->bank_base_capture_addr = ptr_addr;
  1902. for (voice = 0; voice < YDSXG_CAPTURE_VOICES; voice++)
  1903. for (bank = 0; bank < 2; bank++) {
  1904. chip->bank_capture[voice][bank] = (struct snd_ymfpci_capture_bank *)ptr;
  1905. ptr += chip->bank_size_capture;
  1906. ptr_addr += chip->bank_size_capture;
  1907. }
  1908. ptr = (char *)ALIGN((unsigned long)ptr, 0x100);
  1909. ptr_addr = ALIGN(ptr_addr, 0x100);
  1910. chip->bank_base_effect = ptr;
  1911. chip->bank_base_effect_addr = ptr_addr;
  1912. for (voice = 0; voice < YDSXG_EFFECT_VOICES; voice++)
  1913. for (bank = 0; bank < 2; bank++) {
  1914. chip->bank_effect[voice][bank] = (struct snd_ymfpci_effect_bank *)ptr;
  1915. ptr += chip->bank_size_effect;
  1916. ptr_addr += chip->bank_size_effect;
  1917. }
  1918. ptr = (char *)ALIGN((unsigned long)ptr, 0x100);
  1919. ptr_addr = ALIGN(ptr_addr, 0x100);
  1920. chip->work_base = ptr;
  1921. chip->work_base_addr = ptr_addr;
  1922. snd_BUG_ON(ptr + chip->work_size !=
  1923. chip->work_ptr.area + chip->work_ptr.bytes);
  1924. snd_ymfpci_writel(chip, YDSXGR_PLAYCTRLBASE, chip->bank_base_playback_addr);
  1925. snd_ymfpci_writel(chip, YDSXGR_RECCTRLBASE, chip->bank_base_capture_addr);
  1926. snd_ymfpci_writel(chip, YDSXGR_EFFCTRLBASE, chip->bank_base_effect_addr);
  1927. snd_ymfpci_writel(chip, YDSXGR_WORKBASE, chip->work_base_addr);
  1928. snd_ymfpci_writel(chip, YDSXGR_WORKSIZE, chip->work_size >> 2);
  1929. /* S/PDIF output initialization */
  1930. chip->spdif_bits = chip->spdif_pcm_bits = SNDRV_PCM_DEFAULT_CON_SPDIF & 0xffff;
  1931. snd_ymfpci_writew(chip, YDSXGR_SPDIFOUTCTRL, 0);
  1932. snd_ymfpci_writew(chip, YDSXGR_SPDIFOUTSTATUS, chip->spdif_bits);
  1933. /* S/PDIF input initialization */
  1934. snd_ymfpci_writew(chip, YDSXGR_SPDIFINCTRL, 0);
  1935. /* digital mixer setup */
  1936. for (reg = 0x80; reg < 0xc0; reg += 4)
  1937. snd_ymfpci_writel(chip, reg, 0);
  1938. snd_ymfpci_writel(chip, YDSXGR_NATIVEDACOUTVOL, 0x3fff3fff);
  1939. snd_ymfpci_writel(chip, YDSXGR_BUF441OUTVOL, 0x3fff3fff);
  1940. snd_ymfpci_writel(chip, YDSXGR_ZVOUTVOL, 0x3fff3fff);
  1941. snd_ymfpci_writel(chip, YDSXGR_SPDIFOUTVOL, 0x3fff3fff);
  1942. snd_ymfpci_writel(chip, YDSXGR_NATIVEADCINVOL, 0x3fff3fff);
  1943. snd_ymfpci_writel(chip, YDSXGR_NATIVEDACINVOL, 0x3fff3fff);
  1944. snd_ymfpci_writel(chip, YDSXGR_PRIADCLOOPVOL, 0x3fff3fff);
  1945. snd_ymfpci_writel(chip, YDSXGR_LEGACYOUTVOL, 0x3fff3fff);
  1946. return 0;
  1947. }
  1948. static int snd_ymfpci_free(struct snd_ymfpci *chip)
  1949. {
  1950. u16 ctrl;
  1951. if (snd_BUG_ON(!chip))
  1952. return -EINVAL;
  1953. if (chip->res_reg_area) { /* don't touch busy hardware */
  1954. snd_ymfpci_writel(chip, YDSXGR_NATIVEDACOUTVOL, 0);
  1955. snd_ymfpci_writel(chip, YDSXGR_BUF441OUTVOL, 0);
  1956. snd_ymfpci_writel(chip, YDSXGR_LEGACYOUTVOL, 0);
  1957. snd_ymfpci_writel(chip, YDSXGR_STATUS, ~0);
  1958. snd_ymfpci_disable_dsp(chip);
  1959. snd_ymfpci_writel(chip, YDSXGR_PLAYCTRLBASE, 0);
  1960. snd_ymfpci_writel(chip, YDSXGR_RECCTRLBASE, 0);
  1961. snd_ymfpci_writel(chip, YDSXGR_EFFCTRLBASE, 0);
  1962. snd_ymfpci_writel(chip, YDSXGR_WORKBASE, 0);
  1963. snd_ymfpci_writel(chip, YDSXGR_WORKSIZE, 0);
  1964. ctrl = snd_ymfpci_readw(chip, YDSXGR_GLOBALCTRL);
  1965. snd_ymfpci_writew(chip, YDSXGR_GLOBALCTRL, ctrl & ~0x0007);
  1966. }
  1967. snd_ymfpci_ac3_done(chip);
  1968. /* Set PCI device to D3 state */
  1969. #if 0
  1970. /* FIXME: temporarily disabled, otherwise we cannot fire up
  1971. * the chip again unless reboot. ACPI bug?
  1972. */
  1973. pci_set_power_state(chip->pci, 3);
  1974. #endif
  1975. #ifdef CONFIG_PM
  1976. vfree(chip->saved_regs);
  1977. #endif
  1978. if (chip->irq >= 0)
  1979. free_irq(chip->irq, chip);
  1980. release_and_free_resource(chip->mpu_res);
  1981. release_and_free_resource(chip->fm_res);
  1982. snd_ymfpci_free_gameport(chip);
  1983. if (chip->reg_area_virt)
  1984. iounmap(chip->reg_area_virt);
  1985. if (chip->work_ptr.area)
  1986. snd_dma_free_pages(&chip->work_ptr);
  1987. release_and_free_resource(chip->res_reg_area);
  1988. pci_write_config_word(chip->pci, 0x40, chip->old_legacy_ctrl);
  1989. pci_disable_device(chip->pci);
  1990. release_firmware(chip->dsp_microcode);
  1991. release_firmware(chip->controller_microcode);
  1992. kfree(chip);
  1993. return 0;
  1994. }
  1995. static int snd_ymfpci_dev_free(struct snd_device *device)
  1996. {
  1997. struct snd_ymfpci *chip = device->device_data;
  1998. return snd_ymfpci_free(chip);
  1999. }
  2000. #ifdef CONFIG_PM
  2001. static int saved_regs_index[] = {
  2002. /* spdif */
  2003. YDSXGR_SPDIFOUTCTRL,
  2004. YDSXGR_SPDIFOUTSTATUS,
  2005. YDSXGR_SPDIFINCTRL,
  2006. /* volumes */
  2007. YDSXGR_PRIADCLOOPVOL,
  2008. YDSXGR_NATIVEDACINVOL,
  2009. YDSXGR_NATIVEDACOUTVOL,
  2010. YDSXGR_BUF441OUTVOL,
  2011. YDSXGR_NATIVEADCINVOL,
  2012. YDSXGR_SPDIFLOOPVOL,
  2013. YDSXGR_SPDIFOUTVOL,
  2014. YDSXGR_ZVOUTVOL,
  2015. YDSXGR_LEGACYOUTVOL,
  2016. /* address bases */
  2017. YDSXGR_PLAYCTRLBASE,
  2018. YDSXGR_RECCTRLBASE,
  2019. YDSXGR_EFFCTRLBASE,
  2020. YDSXGR_WORKBASE,
  2021. /* capture set up */
  2022. YDSXGR_MAPOFREC,
  2023. YDSXGR_RECFORMAT,
  2024. YDSXGR_RECSLOTSR,
  2025. YDSXGR_ADCFORMAT,
  2026. YDSXGR_ADCSLOTSR,
  2027. };
  2028. #define YDSXGR_NUM_SAVED_REGS ARRAY_SIZE(saved_regs_index)
  2029. int snd_ymfpci_suspend(struct pci_dev *pci, pm_message_t state)
  2030. {
  2031. struct snd_card *card = pci_get_drvdata(pci);
  2032. struct snd_ymfpci *chip = card->private_data;
  2033. unsigned int i;
  2034. snd_power_change_state(card, SNDRV_CTL_POWER_D3hot);
  2035. snd_pcm_suspend_all(chip->pcm);
  2036. snd_pcm_suspend_all(chip->pcm2);
  2037. snd_pcm_suspend_all(chip->pcm_spdif);
  2038. snd_pcm_suspend_all(chip->pcm_4ch);
  2039. snd_ac97_suspend(chip->ac97);
  2040. for (i = 0; i < YDSXGR_NUM_SAVED_REGS; i++)
  2041. chip->saved_regs[i] = snd_ymfpci_readl(chip, saved_regs_index[i]);
  2042. chip->saved_ydsxgr_mode = snd_ymfpci_readl(chip, YDSXGR_MODE);
  2043. snd_ymfpci_writel(chip, YDSXGR_NATIVEDACOUTVOL, 0);
  2044. snd_ymfpci_writel(chip, YDSXGR_BUF441OUTVOL, 0);
  2045. snd_ymfpci_disable_dsp(chip);
  2046. pci_disable_device(pci);
  2047. pci_save_state(pci);
  2048. pci_set_power_state(pci, pci_choose_state(pci, state));
  2049. return 0;
  2050. }
  2051. int snd_ymfpci_resume(struct pci_dev *pci)
  2052. {
  2053. struct snd_card *card = pci_get_drvdata(pci);
  2054. struct snd_ymfpci *chip = card->private_data;
  2055. unsigned int i;
  2056. pci_set_power_state(pci, PCI_D0);
  2057. pci_restore_state(pci);
  2058. if (pci_enable_device(pci) < 0) {
  2059. printk(KERN_ERR "ymfpci: pci_enable_device failed, "
  2060. "disabling device\n");
  2061. snd_card_disconnect(card);
  2062. return -EIO;
  2063. }
  2064. pci_set_master(pci);
  2065. snd_ymfpci_aclink_reset(pci);
  2066. snd_ymfpci_codec_ready(chip, 0);
  2067. snd_ymfpci_download_image(chip);
  2068. udelay(100);
  2069. for (i = 0; i < YDSXGR_NUM_SAVED_REGS; i++)
  2070. snd_ymfpci_writel(chip, saved_regs_index[i], chip->saved_regs[i]);
  2071. snd_ac97_resume(chip->ac97);
  2072. /* start hw again */
  2073. if (chip->start_count > 0) {
  2074. spin_lock_irq(&chip->reg_lock);
  2075. snd_ymfpci_writel(chip, YDSXGR_MODE, chip->saved_ydsxgr_mode);
  2076. chip->active_bank = snd_ymfpci_readl(chip, YDSXGR_CTRLSELECT);
  2077. spin_unlock_irq(&chip->reg_lock);
  2078. }
  2079. snd_power_change_state(card, SNDRV_CTL_POWER_D0);
  2080. return 0;
  2081. }
  2082. #endif /* CONFIG_PM */
  2083. int __devinit snd_ymfpci_create(struct snd_card *card,
  2084. struct pci_dev * pci,
  2085. unsigned short old_legacy_ctrl,
  2086. struct snd_ymfpci ** rchip)
  2087. {
  2088. struct snd_ymfpci *chip;
  2089. int err;
  2090. static struct snd_device_ops ops = {
  2091. .dev_free = snd_ymfpci_dev_free,
  2092. };
  2093. *rchip = NULL;
  2094. /* enable PCI device */
  2095. if ((err = pci_enable_device(pci)) < 0)
  2096. return err;
  2097. chip = kzalloc(sizeof(*chip), GFP_KERNEL);
  2098. if (chip == NULL) {
  2099. pci_disable_device(pci);
  2100. return -ENOMEM;
  2101. }
  2102. chip->old_legacy_ctrl = old_legacy_ctrl;
  2103. spin_lock_init(&chip->reg_lock);
  2104. spin_lock_init(&chip->voice_lock);
  2105. init_waitqueue_head(&chip->interrupt_sleep);
  2106. atomic_set(&chip->interrupt_sleep_count, 0);
  2107. chip->card = card;
  2108. chip->pci = pci;
  2109. chip->irq = -1;
  2110. chip->device_id = pci->device;
  2111. chip->rev = pci->revision;
  2112. chip->reg_area_phys = pci_resource_start(pci, 0);
  2113. chip->reg_area_virt = ioremap_nocache(chip->reg_area_phys, 0x8000);
  2114. pci_set_master(pci);
  2115. chip->src441_used = -1;
  2116. if ((chip->res_reg_area = request_mem_region(chip->reg_area_phys, 0x8000, "YMFPCI")) == NULL) {
  2117. snd_printk(KERN_ERR "unable to grab memory region 0x%lx-0x%lx\n", chip->reg_area_phys, chip->reg_area_phys + 0x8000 - 1);
  2118. snd_ymfpci_free(chip);
  2119. return -EBUSY;
  2120. }
  2121. if (request_irq(pci->irq, snd_ymfpci_interrupt, IRQF_SHARED,
  2122. KBUILD_MODNAME, chip)) {
  2123. snd_printk(KERN_ERR "unable to grab IRQ %d\n", pci->irq);
  2124. snd_ymfpci_free(chip);
  2125. return -EBUSY;
  2126. }
  2127. chip->irq = pci->irq;
  2128. snd_ymfpci_aclink_reset(pci);
  2129. if (snd_ymfpci_codec_ready(chip, 0) < 0) {
  2130. snd_ymfpci_free(chip);
  2131. return -EIO;
  2132. }
  2133. err = snd_ymfpci_request_firmware(chip);
  2134. if (err < 0) {
  2135. snd_printk(KERN_ERR "firmware request failed: %d\n", err);
  2136. snd_ymfpci_free(chip);
  2137. return err;
  2138. }
  2139. snd_ymfpci_download_image(chip);
  2140. udelay(100); /* seems we need a delay after downloading image.. */
  2141. if (snd_ymfpci_memalloc(chip) < 0) {
  2142. snd_ymfpci_free(chip);
  2143. return -EIO;
  2144. }
  2145. if ((err = snd_ymfpci_ac3_init(chip)) < 0) {
  2146. snd_ymfpci_free(chip);
  2147. return err;
  2148. }
  2149. #ifdef CONFIG_PM
  2150. chip->saved_regs = vmalloc(YDSXGR_NUM_SAVED_REGS * sizeof(u32));
  2151. if (chip->saved_regs == NULL) {
  2152. snd_ymfpci_free(chip);
  2153. return -ENOMEM;
  2154. }
  2155. #endif
  2156. if ((err = snd_device_new(card, SNDRV_DEV_LOWLEVEL, chip, &ops)) < 0) {
  2157. snd_ymfpci_free(chip);
  2158. return err;
  2159. }
  2160. snd_ymfpci_proc_init(card, chip);
  2161. snd_card_set_dev(card, &pci->dev);
  2162. *rchip = chip;
  2163. return 0;
  2164. }