patch_hdmi.c 54 KB

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  1. /*
  2. *
  3. * patch_hdmi.c - routines for HDMI/DisplayPort codecs
  4. *
  5. * Copyright(c) 2008-2010 Intel Corporation. All rights reserved.
  6. * Copyright (c) 2006 ATI Technologies Inc.
  7. * Copyright (c) 2008 NVIDIA Corp. All rights reserved.
  8. * Copyright (c) 2008 Wei Ni <wni@nvidia.com>
  9. *
  10. * Authors:
  11. * Wu Fengguang <wfg@linux.intel.com>
  12. *
  13. * Maintained by:
  14. * Wu Fengguang <wfg@linux.intel.com>
  15. *
  16. * This program is free software; you can redistribute it and/or modify it
  17. * under the terms of the GNU General Public License as published by the Free
  18. * Software Foundation; either version 2 of the License, or (at your option)
  19. * any later version.
  20. *
  21. * This program is distributed in the hope that it will be useful, but
  22. * WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
  23. * or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
  24. * for more details.
  25. *
  26. * You should have received a copy of the GNU General Public License
  27. * along with this program; if not, write to the Free Software Foundation,
  28. * Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
  29. */
  30. #include <linux/init.h>
  31. #include <linux/delay.h>
  32. #include <linux/slab.h>
  33. #include <linux/module.h>
  34. #include <sound/core.h>
  35. #include <sound/jack.h>
  36. #include "hda_codec.h"
  37. #include "hda_local.h"
  38. static bool static_hdmi_pcm;
  39. module_param(static_hdmi_pcm, bool, 0644);
  40. MODULE_PARM_DESC(static_hdmi_pcm, "Don't restrict PCM parameters per ELD info");
  41. /*
  42. * The HDMI/DisplayPort configuration can be highly dynamic. A graphics device
  43. * could support N independent pipes, each of them can be connected to one or
  44. * more ports (DVI, HDMI or DisplayPort).
  45. *
  46. * The HDA correspondence of pipes/ports are converter/pin nodes.
  47. */
  48. #define MAX_HDMI_CVTS 4
  49. #define MAX_HDMI_PINS 4
  50. struct hdmi_spec_per_cvt {
  51. hda_nid_t cvt_nid;
  52. int assigned;
  53. unsigned int channels_min;
  54. unsigned int channels_max;
  55. u32 rates;
  56. u64 formats;
  57. unsigned int maxbps;
  58. };
  59. struct hdmi_spec_per_pin {
  60. hda_nid_t pin_nid;
  61. int num_mux_nids;
  62. hda_nid_t mux_nids[HDA_MAX_CONNECTIONS];
  63. struct hdmi_eld sink_eld;
  64. };
  65. struct hdmi_spec {
  66. int num_cvts;
  67. struct hdmi_spec_per_cvt cvts[MAX_HDMI_CVTS];
  68. int num_pins;
  69. struct hdmi_spec_per_pin pins[MAX_HDMI_PINS];
  70. struct hda_pcm pcm_rec[MAX_HDMI_PINS];
  71. /*
  72. * Non-generic ATI/NVIDIA specific
  73. */
  74. struct hda_multi_out multiout;
  75. const struct hda_pcm_stream *pcm_playback;
  76. };
  77. struct hdmi_audio_infoframe {
  78. u8 type; /* 0x84 */
  79. u8 ver; /* 0x01 */
  80. u8 len; /* 0x0a */
  81. u8 checksum;
  82. u8 CC02_CT47; /* CC in bits 0:2, CT in 4:7 */
  83. u8 SS01_SF24;
  84. u8 CXT04;
  85. u8 CA;
  86. u8 LFEPBL01_LSV36_DM_INH7;
  87. };
  88. struct dp_audio_infoframe {
  89. u8 type; /* 0x84 */
  90. u8 len; /* 0x1b */
  91. u8 ver; /* 0x11 << 2 */
  92. u8 CC02_CT47; /* match with HDMI infoframe from this on */
  93. u8 SS01_SF24;
  94. u8 CXT04;
  95. u8 CA;
  96. u8 LFEPBL01_LSV36_DM_INH7;
  97. };
  98. union audio_infoframe {
  99. struct hdmi_audio_infoframe hdmi;
  100. struct dp_audio_infoframe dp;
  101. u8 bytes[0];
  102. };
  103. /*
  104. * CEA speaker placement:
  105. *
  106. * FLH FCH FRH
  107. * FLW FL FLC FC FRC FR FRW
  108. *
  109. * LFE
  110. * TC
  111. *
  112. * RL RLC RC RRC RR
  113. *
  114. * The Left/Right Surround channel _notions_ LS/RS in SMPTE 320M corresponds to
  115. * CEA RL/RR; The SMPTE channel _assignment_ C/LFE is swapped to CEA LFE/FC.
  116. */
  117. enum cea_speaker_placement {
  118. FL = (1 << 0), /* Front Left */
  119. FC = (1 << 1), /* Front Center */
  120. FR = (1 << 2), /* Front Right */
  121. FLC = (1 << 3), /* Front Left Center */
  122. FRC = (1 << 4), /* Front Right Center */
  123. RL = (1 << 5), /* Rear Left */
  124. RC = (1 << 6), /* Rear Center */
  125. RR = (1 << 7), /* Rear Right */
  126. RLC = (1 << 8), /* Rear Left Center */
  127. RRC = (1 << 9), /* Rear Right Center */
  128. LFE = (1 << 10), /* Low Frequency Effect */
  129. FLW = (1 << 11), /* Front Left Wide */
  130. FRW = (1 << 12), /* Front Right Wide */
  131. FLH = (1 << 13), /* Front Left High */
  132. FCH = (1 << 14), /* Front Center High */
  133. FRH = (1 << 15), /* Front Right High */
  134. TC = (1 << 16), /* Top Center */
  135. };
  136. /*
  137. * ELD SA bits in the CEA Speaker Allocation data block
  138. */
  139. static int eld_speaker_allocation_bits[] = {
  140. [0] = FL | FR,
  141. [1] = LFE,
  142. [2] = FC,
  143. [3] = RL | RR,
  144. [4] = RC,
  145. [5] = FLC | FRC,
  146. [6] = RLC | RRC,
  147. /* the following are not defined in ELD yet */
  148. [7] = FLW | FRW,
  149. [8] = FLH | FRH,
  150. [9] = TC,
  151. [10] = FCH,
  152. };
  153. struct cea_channel_speaker_allocation {
  154. int ca_index;
  155. int speakers[8];
  156. /* derived values, just for convenience */
  157. int channels;
  158. int spk_mask;
  159. };
  160. /*
  161. * ALSA sequence is:
  162. *
  163. * surround40 surround41 surround50 surround51 surround71
  164. * ch0 front left = = = =
  165. * ch1 front right = = = =
  166. * ch2 rear left = = = =
  167. * ch3 rear right = = = =
  168. * ch4 LFE center center center
  169. * ch5 LFE LFE
  170. * ch6 side left
  171. * ch7 side right
  172. *
  173. * surround71 = {FL, FR, RLC, RRC, FC, LFE, RL, RR}
  174. */
  175. static int hdmi_channel_mapping[0x32][8] = {
  176. /* stereo */
  177. [0x00] = { 0x00, 0x11, 0xf2, 0xf3, 0xf4, 0xf5, 0xf6, 0xf7 },
  178. /* 2.1 */
  179. [0x01] = { 0x00, 0x11, 0x22, 0xf3, 0xf4, 0xf5, 0xf6, 0xf7 },
  180. /* Dolby Surround */
  181. [0x02] = { 0x00, 0x11, 0x23, 0xf2, 0xf4, 0xf5, 0xf6, 0xf7 },
  182. /* surround40 */
  183. [0x08] = { 0x00, 0x11, 0x24, 0x35, 0xf3, 0xf2, 0xf6, 0xf7 },
  184. /* 4ch */
  185. [0x03] = { 0x00, 0x11, 0x23, 0x32, 0x44, 0xf5, 0xf6, 0xf7 },
  186. /* surround41 */
  187. [0x09] = { 0x00, 0x11, 0x24, 0x35, 0x42, 0xf3, 0xf6, 0xf7 },
  188. /* surround50 */
  189. [0x0a] = { 0x00, 0x11, 0x24, 0x35, 0x43, 0xf2, 0xf6, 0xf7 },
  190. /* surround51 */
  191. [0x0b] = { 0x00, 0x11, 0x24, 0x35, 0x43, 0x52, 0xf6, 0xf7 },
  192. /* 7.1 */
  193. [0x13] = { 0x00, 0x11, 0x26, 0x37, 0x43, 0x52, 0x64, 0x75 },
  194. };
  195. /*
  196. * This is an ordered list!
  197. *
  198. * The preceding ones have better chances to be selected by
  199. * hdmi_channel_allocation().
  200. */
  201. static struct cea_channel_speaker_allocation channel_allocations[] = {
  202. /* channel: 7 6 5 4 3 2 1 0 */
  203. { .ca_index = 0x00, .speakers = { 0, 0, 0, 0, 0, 0, FR, FL } },
  204. /* 2.1 */
  205. { .ca_index = 0x01, .speakers = { 0, 0, 0, 0, 0, LFE, FR, FL } },
  206. /* Dolby Surround */
  207. { .ca_index = 0x02, .speakers = { 0, 0, 0, 0, FC, 0, FR, FL } },
  208. /* surround40 */
  209. { .ca_index = 0x08, .speakers = { 0, 0, RR, RL, 0, 0, FR, FL } },
  210. /* surround41 */
  211. { .ca_index = 0x09, .speakers = { 0, 0, RR, RL, 0, LFE, FR, FL } },
  212. /* surround50 */
  213. { .ca_index = 0x0a, .speakers = { 0, 0, RR, RL, FC, 0, FR, FL } },
  214. /* surround51 */
  215. { .ca_index = 0x0b, .speakers = { 0, 0, RR, RL, FC, LFE, FR, FL } },
  216. /* 6.1 */
  217. { .ca_index = 0x0f, .speakers = { 0, RC, RR, RL, FC, LFE, FR, FL } },
  218. /* surround71 */
  219. { .ca_index = 0x13, .speakers = { RRC, RLC, RR, RL, FC, LFE, FR, FL } },
  220. { .ca_index = 0x03, .speakers = { 0, 0, 0, 0, FC, LFE, FR, FL } },
  221. { .ca_index = 0x04, .speakers = { 0, 0, 0, RC, 0, 0, FR, FL } },
  222. { .ca_index = 0x05, .speakers = { 0, 0, 0, RC, 0, LFE, FR, FL } },
  223. { .ca_index = 0x06, .speakers = { 0, 0, 0, RC, FC, 0, FR, FL } },
  224. { .ca_index = 0x07, .speakers = { 0, 0, 0, RC, FC, LFE, FR, FL } },
  225. { .ca_index = 0x0c, .speakers = { 0, RC, RR, RL, 0, 0, FR, FL } },
  226. { .ca_index = 0x0d, .speakers = { 0, RC, RR, RL, 0, LFE, FR, FL } },
  227. { .ca_index = 0x0e, .speakers = { 0, RC, RR, RL, FC, 0, FR, FL } },
  228. { .ca_index = 0x10, .speakers = { RRC, RLC, RR, RL, 0, 0, FR, FL } },
  229. { .ca_index = 0x11, .speakers = { RRC, RLC, RR, RL, 0, LFE, FR, FL } },
  230. { .ca_index = 0x12, .speakers = { RRC, RLC, RR, RL, FC, 0, FR, FL } },
  231. { .ca_index = 0x14, .speakers = { FRC, FLC, 0, 0, 0, 0, FR, FL } },
  232. { .ca_index = 0x15, .speakers = { FRC, FLC, 0, 0, 0, LFE, FR, FL } },
  233. { .ca_index = 0x16, .speakers = { FRC, FLC, 0, 0, FC, 0, FR, FL } },
  234. { .ca_index = 0x17, .speakers = { FRC, FLC, 0, 0, FC, LFE, FR, FL } },
  235. { .ca_index = 0x18, .speakers = { FRC, FLC, 0, RC, 0, 0, FR, FL } },
  236. { .ca_index = 0x19, .speakers = { FRC, FLC, 0, RC, 0, LFE, FR, FL } },
  237. { .ca_index = 0x1a, .speakers = { FRC, FLC, 0, RC, FC, 0, FR, FL } },
  238. { .ca_index = 0x1b, .speakers = { FRC, FLC, 0, RC, FC, LFE, FR, FL } },
  239. { .ca_index = 0x1c, .speakers = { FRC, FLC, RR, RL, 0, 0, FR, FL } },
  240. { .ca_index = 0x1d, .speakers = { FRC, FLC, RR, RL, 0, LFE, FR, FL } },
  241. { .ca_index = 0x1e, .speakers = { FRC, FLC, RR, RL, FC, 0, FR, FL } },
  242. { .ca_index = 0x1f, .speakers = { FRC, FLC, RR, RL, FC, LFE, FR, FL } },
  243. { .ca_index = 0x20, .speakers = { 0, FCH, RR, RL, FC, 0, FR, FL } },
  244. { .ca_index = 0x21, .speakers = { 0, FCH, RR, RL, FC, LFE, FR, FL } },
  245. { .ca_index = 0x22, .speakers = { TC, 0, RR, RL, FC, 0, FR, FL } },
  246. { .ca_index = 0x23, .speakers = { TC, 0, RR, RL, FC, LFE, FR, FL } },
  247. { .ca_index = 0x24, .speakers = { FRH, FLH, RR, RL, 0, 0, FR, FL } },
  248. { .ca_index = 0x25, .speakers = { FRH, FLH, RR, RL, 0, LFE, FR, FL } },
  249. { .ca_index = 0x26, .speakers = { FRW, FLW, RR, RL, 0, 0, FR, FL } },
  250. { .ca_index = 0x27, .speakers = { FRW, FLW, RR, RL, 0, LFE, FR, FL } },
  251. { .ca_index = 0x28, .speakers = { TC, RC, RR, RL, FC, 0, FR, FL } },
  252. { .ca_index = 0x29, .speakers = { TC, RC, RR, RL, FC, LFE, FR, FL } },
  253. { .ca_index = 0x2a, .speakers = { FCH, RC, RR, RL, FC, 0, FR, FL } },
  254. { .ca_index = 0x2b, .speakers = { FCH, RC, RR, RL, FC, LFE, FR, FL } },
  255. { .ca_index = 0x2c, .speakers = { TC, FCH, RR, RL, FC, 0, FR, FL } },
  256. { .ca_index = 0x2d, .speakers = { TC, FCH, RR, RL, FC, LFE, FR, FL } },
  257. { .ca_index = 0x2e, .speakers = { FRH, FLH, RR, RL, FC, 0, FR, FL } },
  258. { .ca_index = 0x2f, .speakers = { FRH, FLH, RR, RL, FC, LFE, FR, FL } },
  259. { .ca_index = 0x30, .speakers = { FRW, FLW, RR, RL, FC, 0, FR, FL } },
  260. { .ca_index = 0x31, .speakers = { FRW, FLW, RR, RL, FC, LFE, FR, FL } },
  261. };
  262. /*
  263. * HDMI routines
  264. */
  265. static int pin_nid_to_pin_index(struct hdmi_spec *spec, hda_nid_t pin_nid)
  266. {
  267. int pin_idx;
  268. for (pin_idx = 0; pin_idx < spec->num_pins; pin_idx++)
  269. if (spec->pins[pin_idx].pin_nid == pin_nid)
  270. return pin_idx;
  271. snd_printk(KERN_WARNING "HDMI: pin nid %d not registered\n", pin_nid);
  272. return -EINVAL;
  273. }
  274. static int hinfo_to_pin_index(struct hdmi_spec *spec,
  275. struct hda_pcm_stream *hinfo)
  276. {
  277. int pin_idx;
  278. for (pin_idx = 0; pin_idx < spec->num_pins; pin_idx++)
  279. if (&spec->pcm_rec[pin_idx].stream[0] == hinfo)
  280. return pin_idx;
  281. snd_printk(KERN_WARNING "HDMI: hinfo %p not registered\n", hinfo);
  282. return -EINVAL;
  283. }
  284. static int cvt_nid_to_cvt_index(struct hdmi_spec *spec, hda_nid_t cvt_nid)
  285. {
  286. int cvt_idx;
  287. for (cvt_idx = 0; cvt_idx < spec->num_cvts; cvt_idx++)
  288. if (spec->cvts[cvt_idx].cvt_nid == cvt_nid)
  289. return cvt_idx;
  290. snd_printk(KERN_WARNING "HDMI: cvt nid %d not registered\n", cvt_nid);
  291. return -EINVAL;
  292. }
  293. static int hdmi_eld_ctl_info(struct snd_kcontrol *kcontrol,
  294. struct snd_ctl_elem_info *uinfo)
  295. {
  296. struct hda_codec *codec = snd_kcontrol_chip(kcontrol);
  297. struct hdmi_spec *spec;
  298. int pin_idx;
  299. spec = codec->spec;
  300. uinfo->type = SNDRV_CTL_ELEM_TYPE_BYTES;
  301. pin_idx = kcontrol->private_value;
  302. uinfo->count = spec->pins[pin_idx].sink_eld.eld_size;
  303. return 0;
  304. }
  305. static int hdmi_eld_ctl_get(struct snd_kcontrol *kcontrol,
  306. struct snd_ctl_elem_value *ucontrol)
  307. {
  308. struct hda_codec *codec = snd_kcontrol_chip(kcontrol);
  309. struct hdmi_spec *spec;
  310. int pin_idx;
  311. spec = codec->spec;
  312. pin_idx = kcontrol->private_value;
  313. memcpy(ucontrol->value.bytes.data,
  314. spec->pins[pin_idx].sink_eld.eld_buffer, ELD_MAX_SIZE);
  315. return 0;
  316. }
  317. static struct snd_kcontrol_new eld_bytes_ctl = {
  318. .access = SNDRV_CTL_ELEM_ACCESS_READ | SNDRV_CTL_ELEM_ACCESS_VOLATILE,
  319. .iface = SNDRV_CTL_ELEM_IFACE_PCM,
  320. .name = "ELD",
  321. .info = hdmi_eld_ctl_info,
  322. .get = hdmi_eld_ctl_get,
  323. };
  324. static int hdmi_create_eld_ctl(struct hda_codec *codec, int pin_idx,
  325. int device)
  326. {
  327. struct snd_kcontrol *kctl;
  328. struct hdmi_spec *spec = codec->spec;
  329. int err;
  330. kctl = snd_ctl_new1(&eld_bytes_ctl, codec);
  331. if (!kctl)
  332. return -ENOMEM;
  333. kctl->private_value = pin_idx;
  334. kctl->id.device = device;
  335. err = snd_hda_ctl_add(codec, spec->pins[pin_idx].pin_nid, kctl);
  336. if (err < 0)
  337. return err;
  338. return 0;
  339. }
  340. #ifdef BE_PARANOID
  341. static void hdmi_get_dip_index(struct hda_codec *codec, hda_nid_t pin_nid,
  342. int *packet_index, int *byte_index)
  343. {
  344. int val;
  345. val = snd_hda_codec_read(codec, pin_nid, 0,
  346. AC_VERB_GET_HDMI_DIP_INDEX, 0);
  347. *packet_index = val >> 5;
  348. *byte_index = val & 0x1f;
  349. }
  350. #endif
  351. static void hdmi_set_dip_index(struct hda_codec *codec, hda_nid_t pin_nid,
  352. int packet_index, int byte_index)
  353. {
  354. int val;
  355. val = (packet_index << 5) | (byte_index & 0x1f);
  356. snd_hda_codec_write(codec, pin_nid, 0, AC_VERB_SET_HDMI_DIP_INDEX, val);
  357. }
  358. static void hdmi_write_dip_byte(struct hda_codec *codec, hda_nid_t pin_nid,
  359. unsigned char val)
  360. {
  361. snd_hda_codec_write(codec, pin_nid, 0, AC_VERB_SET_HDMI_DIP_DATA, val);
  362. }
  363. static void hdmi_init_pin(struct hda_codec *codec, hda_nid_t pin_nid)
  364. {
  365. /* Unmute */
  366. if (get_wcaps(codec, pin_nid) & AC_WCAP_OUT_AMP)
  367. snd_hda_codec_write(codec, pin_nid, 0,
  368. AC_VERB_SET_AMP_GAIN_MUTE, AMP_OUT_UNMUTE);
  369. /* Disable pin out until stream is active*/
  370. snd_hda_codec_write(codec, pin_nid, 0,
  371. AC_VERB_SET_PIN_WIDGET_CONTROL, 0);
  372. }
  373. static int hdmi_get_channel_count(struct hda_codec *codec, hda_nid_t cvt_nid)
  374. {
  375. return 1 + snd_hda_codec_read(codec, cvt_nid, 0,
  376. AC_VERB_GET_CVT_CHAN_COUNT, 0);
  377. }
  378. static void hdmi_set_channel_count(struct hda_codec *codec,
  379. hda_nid_t cvt_nid, int chs)
  380. {
  381. if (chs != hdmi_get_channel_count(codec, cvt_nid))
  382. snd_hda_codec_write(codec, cvt_nid, 0,
  383. AC_VERB_SET_CVT_CHAN_COUNT, chs - 1);
  384. }
  385. /*
  386. * Channel mapping routines
  387. */
  388. /*
  389. * Compute derived values in channel_allocations[].
  390. */
  391. static void init_channel_allocations(void)
  392. {
  393. int i, j;
  394. struct cea_channel_speaker_allocation *p;
  395. for (i = 0; i < ARRAY_SIZE(channel_allocations); i++) {
  396. p = channel_allocations + i;
  397. p->channels = 0;
  398. p->spk_mask = 0;
  399. for (j = 0; j < ARRAY_SIZE(p->speakers); j++)
  400. if (p->speakers[j]) {
  401. p->channels++;
  402. p->spk_mask |= p->speakers[j];
  403. }
  404. }
  405. }
  406. /*
  407. * The transformation takes two steps:
  408. *
  409. * eld->spk_alloc => (eld_speaker_allocation_bits[]) => spk_mask
  410. * spk_mask => (channel_allocations[]) => ai->CA
  411. *
  412. * TODO: it could select the wrong CA from multiple candidates.
  413. */
  414. static int hdmi_channel_allocation(struct hdmi_eld *eld, int channels)
  415. {
  416. int i;
  417. int ca = 0;
  418. int spk_mask = 0;
  419. char buf[SND_PRINT_CHANNEL_ALLOCATION_ADVISED_BUFSIZE];
  420. /*
  421. * CA defaults to 0 for basic stereo audio
  422. */
  423. if (channels <= 2)
  424. return 0;
  425. /*
  426. * expand ELD's speaker allocation mask
  427. *
  428. * ELD tells the speaker mask in a compact(paired) form,
  429. * expand ELD's notions to match the ones used by Audio InfoFrame.
  430. */
  431. for (i = 0; i < ARRAY_SIZE(eld_speaker_allocation_bits); i++) {
  432. if (eld->spk_alloc & (1 << i))
  433. spk_mask |= eld_speaker_allocation_bits[i];
  434. }
  435. /* search for the first working match in the CA table */
  436. for (i = 0; i < ARRAY_SIZE(channel_allocations); i++) {
  437. if (channels == channel_allocations[i].channels &&
  438. (spk_mask & channel_allocations[i].spk_mask) ==
  439. channel_allocations[i].spk_mask) {
  440. ca = channel_allocations[i].ca_index;
  441. break;
  442. }
  443. }
  444. snd_print_channel_allocation(eld->spk_alloc, buf, sizeof(buf));
  445. snd_printdd("HDMI: select CA 0x%x for %d-channel allocation: %s\n",
  446. ca, channels, buf);
  447. return ca;
  448. }
  449. static void hdmi_debug_channel_mapping(struct hda_codec *codec,
  450. hda_nid_t pin_nid)
  451. {
  452. #ifdef CONFIG_SND_DEBUG_VERBOSE
  453. int i;
  454. int slot;
  455. for (i = 0; i < 8; i++) {
  456. slot = snd_hda_codec_read(codec, pin_nid, 0,
  457. AC_VERB_GET_HDMI_CHAN_SLOT, i);
  458. printk(KERN_DEBUG "HDMI: ASP channel %d => slot %d\n",
  459. slot >> 4, slot & 0xf);
  460. }
  461. #endif
  462. }
  463. static void hdmi_setup_channel_mapping(struct hda_codec *codec,
  464. hda_nid_t pin_nid,
  465. int ca)
  466. {
  467. int i;
  468. int err;
  469. if (hdmi_channel_mapping[ca][1] == 0) {
  470. for (i = 0; i < channel_allocations[ca].channels; i++)
  471. hdmi_channel_mapping[ca][i] = i | (i << 4);
  472. for (; i < 8; i++)
  473. hdmi_channel_mapping[ca][i] = 0xf | (i << 4);
  474. }
  475. for (i = 0; i < 8; i++) {
  476. err = snd_hda_codec_write(codec, pin_nid, 0,
  477. AC_VERB_SET_HDMI_CHAN_SLOT,
  478. hdmi_channel_mapping[ca][i]);
  479. if (err) {
  480. snd_printdd(KERN_NOTICE
  481. "HDMI: channel mapping failed\n");
  482. break;
  483. }
  484. }
  485. hdmi_debug_channel_mapping(codec, pin_nid);
  486. }
  487. /*
  488. * Audio InfoFrame routines
  489. */
  490. /*
  491. * Enable Audio InfoFrame Transmission
  492. */
  493. static void hdmi_start_infoframe_trans(struct hda_codec *codec,
  494. hda_nid_t pin_nid)
  495. {
  496. hdmi_set_dip_index(codec, pin_nid, 0x0, 0x0);
  497. snd_hda_codec_write(codec, pin_nid, 0, AC_VERB_SET_HDMI_DIP_XMIT,
  498. AC_DIPXMIT_BEST);
  499. }
  500. /*
  501. * Disable Audio InfoFrame Transmission
  502. */
  503. static void hdmi_stop_infoframe_trans(struct hda_codec *codec,
  504. hda_nid_t pin_nid)
  505. {
  506. hdmi_set_dip_index(codec, pin_nid, 0x0, 0x0);
  507. snd_hda_codec_write(codec, pin_nid, 0, AC_VERB_SET_HDMI_DIP_XMIT,
  508. AC_DIPXMIT_DISABLE);
  509. }
  510. static void hdmi_debug_dip_size(struct hda_codec *codec, hda_nid_t pin_nid)
  511. {
  512. #ifdef CONFIG_SND_DEBUG_VERBOSE
  513. int i;
  514. int size;
  515. size = snd_hdmi_get_eld_size(codec, pin_nid);
  516. printk(KERN_DEBUG "HDMI: ELD buf size is %d\n", size);
  517. for (i = 0; i < 8; i++) {
  518. size = snd_hda_codec_read(codec, pin_nid, 0,
  519. AC_VERB_GET_HDMI_DIP_SIZE, i);
  520. printk(KERN_DEBUG "HDMI: DIP GP[%d] buf size is %d\n", i, size);
  521. }
  522. #endif
  523. }
  524. static void hdmi_clear_dip_buffers(struct hda_codec *codec, hda_nid_t pin_nid)
  525. {
  526. #ifdef BE_PARANOID
  527. int i, j;
  528. int size;
  529. int pi, bi;
  530. for (i = 0; i < 8; i++) {
  531. size = snd_hda_codec_read(codec, pin_nid, 0,
  532. AC_VERB_GET_HDMI_DIP_SIZE, i);
  533. if (size == 0)
  534. continue;
  535. hdmi_set_dip_index(codec, pin_nid, i, 0x0);
  536. for (j = 1; j < 1000; j++) {
  537. hdmi_write_dip_byte(codec, pin_nid, 0x0);
  538. hdmi_get_dip_index(codec, pin_nid, &pi, &bi);
  539. if (pi != i)
  540. snd_printd(KERN_INFO "dip index %d: %d != %d\n",
  541. bi, pi, i);
  542. if (bi == 0) /* byte index wrapped around */
  543. break;
  544. }
  545. snd_printd(KERN_INFO
  546. "HDMI: DIP GP[%d] buf reported size=%d, written=%d\n",
  547. i, size, j);
  548. }
  549. #endif
  550. }
  551. static void hdmi_checksum_audio_infoframe(struct hdmi_audio_infoframe *hdmi_ai)
  552. {
  553. u8 *bytes = (u8 *)hdmi_ai;
  554. u8 sum = 0;
  555. int i;
  556. hdmi_ai->checksum = 0;
  557. for (i = 0; i < sizeof(*hdmi_ai); i++)
  558. sum += bytes[i];
  559. hdmi_ai->checksum = -sum;
  560. }
  561. static void hdmi_fill_audio_infoframe(struct hda_codec *codec,
  562. hda_nid_t pin_nid,
  563. u8 *dip, int size)
  564. {
  565. int i;
  566. hdmi_debug_dip_size(codec, pin_nid);
  567. hdmi_clear_dip_buffers(codec, pin_nid); /* be paranoid */
  568. hdmi_set_dip_index(codec, pin_nid, 0x0, 0x0);
  569. for (i = 0; i < size; i++)
  570. hdmi_write_dip_byte(codec, pin_nid, dip[i]);
  571. }
  572. static bool hdmi_infoframe_uptodate(struct hda_codec *codec, hda_nid_t pin_nid,
  573. u8 *dip, int size)
  574. {
  575. u8 val;
  576. int i;
  577. if (snd_hda_codec_read(codec, pin_nid, 0, AC_VERB_GET_HDMI_DIP_XMIT, 0)
  578. != AC_DIPXMIT_BEST)
  579. return false;
  580. hdmi_set_dip_index(codec, pin_nid, 0x0, 0x0);
  581. for (i = 0; i < size; i++) {
  582. val = snd_hda_codec_read(codec, pin_nid, 0,
  583. AC_VERB_GET_HDMI_DIP_DATA, 0);
  584. if (val != dip[i])
  585. return false;
  586. }
  587. return true;
  588. }
  589. static void hdmi_setup_audio_infoframe(struct hda_codec *codec, int pin_idx,
  590. struct snd_pcm_substream *substream)
  591. {
  592. struct hdmi_spec *spec = codec->spec;
  593. struct hdmi_spec_per_pin *per_pin = &spec->pins[pin_idx];
  594. hda_nid_t pin_nid = per_pin->pin_nid;
  595. int channels = substream->runtime->channels;
  596. struct hdmi_eld *eld;
  597. int ca;
  598. union audio_infoframe ai;
  599. eld = &spec->pins[pin_idx].sink_eld;
  600. if (!eld->monitor_present)
  601. return;
  602. ca = hdmi_channel_allocation(eld, channels);
  603. memset(&ai, 0, sizeof(ai));
  604. if (eld->conn_type == 0) { /* HDMI */
  605. struct hdmi_audio_infoframe *hdmi_ai = &ai.hdmi;
  606. hdmi_ai->type = 0x84;
  607. hdmi_ai->ver = 0x01;
  608. hdmi_ai->len = 0x0a;
  609. hdmi_ai->CC02_CT47 = channels - 1;
  610. hdmi_ai->CA = ca;
  611. hdmi_checksum_audio_infoframe(hdmi_ai);
  612. } else if (eld->conn_type == 1) { /* DisplayPort */
  613. struct dp_audio_infoframe *dp_ai = &ai.dp;
  614. dp_ai->type = 0x84;
  615. dp_ai->len = 0x1b;
  616. dp_ai->ver = 0x11 << 2;
  617. dp_ai->CC02_CT47 = channels - 1;
  618. dp_ai->CA = ca;
  619. } else {
  620. snd_printd("HDMI: unknown connection type at pin %d\n",
  621. pin_nid);
  622. return;
  623. }
  624. /*
  625. * sizeof(ai) is used instead of sizeof(*hdmi_ai) or
  626. * sizeof(*dp_ai) to avoid partial match/update problems when
  627. * the user switches between HDMI/DP monitors.
  628. */
  629. if (!hdmi_infoframe_uptodate(codec, pin_nid, ai.bytes,
  630. sizeof(ai))) {
  631. snd_printdd("hdmi_setup_audio_infoframe: "
  632. "pin=%d channels=%d\n",
  633. pin_nid,
  634. channels);
  635. hdmi_setup_channel_mapping(codec, pin_nid, ca);
  636. hdmi_stop_infoframe_trans(codec, pin_nid);
  637. hdmi_fill_audio_infoframe(codec, pin_nid,
  638. ai.bytes, sizeof(ai));
  639. hdmi_start_infoframe_trans(codec, pin_nid);
  640. }
  641. }
  642. /*
  643. * Unsolicited events
  644. */
  645. static void hdmi_present_sense(struct hda_codec *codec, hda_nid_t pin_nid,
  646. struct hdmi_eld *eld);
  647. static void hdmi_intrinsic_event(struct hda_codec *codec, unsigned int res)
  648. {
  649. struct hdmi_spec *spec = codec->spec;
  650. int pin_nid = res >> AC_UNSOL_RES_TAG_SHIFT;
  651. int pd = !!(res & AC_UNSOL_RES_PD);
  652. int eldv = !!(res & AC_UNSOL_RES_ELDV);
  653. int pin_idx;
  654. struct hdmi_eld *eld;
  655. printk(KERN_INFO
  656. "HDMI hot plug event: Codec=%d Pin=%d Presence_Detect=%d ELD_Valid=%d\n",
  657. codec->addr, pin_nid, pd, eldv);
  658. pin_idx = pin_nid_to_pin_index(spec, pin_nid);
  659. if (pin_idx < 0)
  660. return;
  661. eld = &spec->pins[pin_idx].sink_eld;
  662. hdmi_present_sense(codec, pin_nid, eld);
  663. /*
  664. * HDMI sink's ELD info cannot always be retrieved for now, e.g.
  665. * in console or for audio devices. Assume the highest speakers
  666. * configuration, to _not_ prohibit multi-channel audio playback.
  667. */
  668. if (!eld->spk_alloc)
  669. eld->spk_alloc = 0xffff;
  670. }
  671. static void hdmi_non_intrinsic_event(struct hda_codec *codec, unsigned int res)
  672. {
  673. int tag = res >> AC_UNSOL_RES_TAG_SHIFT;
  674. int subtag = (res & AC_UNSOL_RES_SUBTAG) >> AC_UNSOL_RES_SUBTAG_SHIFT;
  675. int cp_state = !!(res & AC_UNSOL_RES_CP_STATE);
  676. int cp_ready = !!(res & AC_UNSOL_RES_CP_READY);
  677. printk(KERN_INFO
  678. "HDMI CP event: CODEC=%d PIN=%d SUBTAG=0x%x CP_STATE=%d CP_READY=%d\n",
  679. codec->addr,
  680. tag,
  681. subtag,
  682. cp_state,
  683. cp_ready);
  684. /* TODO */
  685. if (cp_state)
  686. ;
  687. if (cp_ready)
  688. ;
  689. }
  690. static void hdmi_unsol_event(struct hda_codec *codec, unsigned int res)
  691. {
  692. struct hdmi_spec *spec = codec->spec;
  693. int tag = res >> AC_UNSOL_RES_TAG_SHIFT;
  694. int subtag = (res & AC_UNSOL_RES_SUBTAG) >> AC_UNSOL_RES_SUBTAG_SHIFT;
  695. if (pin_nid_to_pin_index(spec, tag) < 0) {
  696. snd_printd(KERN_INFO "Unexpected HDMI event tag 0x%x\n", tag);
  697. return;
  698. }
  699. if (subtag == 0)
  700. hdmi_intrinsic_event(codec, res);
  701. else
  702. hdmi_non_intrinsic_event(codec, res);
  703. }
  704. /*
  705. * Callbacks
  706. */
  707. /* HBR should be Non-PCM, 8 channels */
  708. #define is_hbr_format(format) \
  709. ((format & AC_FMT_TYPE_NON_PCM) && (format & AC_FMT_CHAN_MASK) == 7)
  710. static int hdmi_setup_stream(struct hda_codec *codec, hda_nid_t cvt_nid,
  711. hda_nid_t pin_nid, u32 stream_tag, int format)
  712. {
  713. int pinctl;
  714. int new_pinctl = 0;
  715. if (snd_hda_query_pin_caps(codec, pin_nid) & AC_PINCAP_HBR) {
  716. pinctl = snd_hda_codec_read(codec, pin_nid, 0,
  717. AC_VERB_GET_PIN_WIDGET_CONTROL, 0);
  718. new_pinctl = pinctl & ~AC_PINCTL_EPT;
  719. if (is_hbr_format(format))
  720. new_pinctl |= AC_PINCTL_EPT_HBR;
  721. else
  722. new_pinctl |= AC_PINCTL_EPT_NATIVE;
  723. snd_printdd("hdmi_setup_stream: "
  724. "NID=0x%x, %spinctl=0x%x\n",
  725. pin_nid,
  726. pinctl == new_pinctl ? "" : "new-",
  727. new_pinctl);
  728. if (pinctl != new_pinctl)
  729. snd_hda_codec_write(codec, pin_nid, 0,
  730. AC_VERB_SET_PIN_WIDGET_CONTROL,
  731. new_pinctl);
  732. }
  733. if (is_hbr_format(format) && !new_pinctl) {
  734. snd_printdd("hdmi_setup_stream: HBR is not supported\n");
  735. return -EINVAL;
  736. }
  737. snd_hda_codec_setup_stream(codec, cvt_nid, stream_tag, 0, format);
  738. return 0;
  739. }
  740. /*
  741. * HDA PCM callbacks
  742. */
  743. static int hdmi_pcm_open(struct hda_pcm_stream *hinfo,
  744. struct hda_codec *codec,
  745. struct snd_pcm_substream *substream)
  746. {
  747. struct hdmi_spec *spec = codec->spec;
  748. struct snd_pcm_runtime *runtime = substream->runtime;
  749. int pin_idx, cvt_idx, mux_idx = 0;
  750. struct hdmi_spec_per_pin *per_pin;
  751. struct hdmi_eld *eld;
  752. struct hdmi_spec_per_cvt *per_cvt = NULL;
  753. int pinctl;
  754. /* Validate hinfo */
  755. pin_idx = hinfo_to_pin_index(spec, hinfo);
  756. if (snd_BUG_ON(pin_idx < 0))
  757. return -EINVAL;
  758. per_pin = &spec->pins[pin_idx];
  759. eld = &per_pin->sink_eld;
  760. /* Dynamically assign converter to stream */
  761. for (cvt_idx = 0; cvt_idx < spec->num_cvts; cvt_idx++) {
  762. per_cvt = &spec->cvts[cvt_idx];
  763. /* Must not already be assigned */
  764. if (per_cvt->assigned)
  765. continue;
  766. /* Must be in pin's mux's list of converters */
  767. for (mux_idx = 0; mux_idx < per_pin->num_mux_nids; mux_idx++)
  768. if (per_pin->mux_nids[mux_idx] == per_cvt->cvt_nid)
  769. break;
  770. /* Not in mux list */
  771. if (mux_idx == per_pin->num_mux_nids)
  772. continue;
  773. break;
  774. }
  775. /* No free converters */
  776. if (cvt_idx == spec->num_cvts)
  777. return -ENODEV;
  778. /* Claim converter */
  779. per_cvt->assigned = 1;
  780. hinfo->nid = per_cvt->cvt_nid;
  781. snd_hda_codec_write(codec, per_pin->pin_nid, 0,
  782. AC_VERB_SET_CONNECT_SEL,
  783. mux_idx);
  784. pinctl = snd_hda_codec_read(codec, per_pin->pin_nid, 0,
  785. AC_VERB_GET_PIN_WIDGET_CONTROL, 0);
  786. snd_hda_codec_write(codec, per_pin->pin_nid, 0,
  787. AC_VERB_SET_PIN_WIDGET_CONTROL,
  788. pinctl | PIN_OUT);
  789. snd_hda_spdif_ctls_assign(codec, pin_idx, per_cvt->cvt_nid);
  790. /* Initially set the converter's capabilities */
  791. hinfo->channels_min = per_cvt->channels_min;
  792. hinfo->channels_max = per_cvt->channels_max;
  793. hinfo->rates = per_cvt->rates;
  794. hinfo->formats = per_cvt->formats;
  795. hinfo->maxbps = per_cvt->maxbps;
  796. /* Restrict capabilities by ELD if this isn't disabled */
  797. if (!static_hdmi_pcm && eld->eld_valid) {
  798. snd_hdmi_eld_update_pcm_info(eld, hinfo);
  799. if (hinfo->channels_min > hinfo->channels_max ||
  800. !hinfo->rates || !hinfo->formats)
  801. return -ENODEV;
  802. }
  803. /* Store the updated parameters */
  804. runtime->hw.channels_min = hinfo->channels_min;
  805. runtime->hw.channels_max = hinfo->channels_max;
  806. runtime->hw.formats = hinfo->formats;
  807. runtime->hw.rates = hinfo->rates;
  808. snd_pcm_hw_constraint_step(substream->runtime, 0,
  809. SNDRV_PCM_HW_PARAM_CHANNELS, 2);
  810. return 0;
  811. }
  812. /*
  813. * HDA/HDMI auto parsing
  814. */
  815. static int hdmi_read_pin_conn(struct hda_codec *codec, int pin_idx)
  816. {
  817. struct hdmi_spec *spec = codec->spec;
  818. struct hdmi_spec_per_pin *per_pin = &spec->pins[pin_idx];
  819. hda_nid_t pin_nid = per_pin->pin_nid;
  820. if (!(get_wcaps(codec, pin_nid) & AC_WCAP_CONN_LIST)) {
  821. snd_printk(KERN_WARNING
  822. "HDMI: pin %d wcaps %#x "
  823. "does not support connection list\n",
  824. pin_nid, get_wcaps(codec, pin_nid));
  825. return -EINVAL;
  826. }
  827. per_pin->num_mux_nids = snd_hda_get_connections(codec, pin_nid,
  828. per_pin->mux_nids,
  829. HDA_MAX_CONNECTIONS);
  830. return 0;
  831. }
  832. static void hdmi_present_sense(struct hda_codec *codec, hda_nid_t pin_nid,
  833. struct hdmi_eld *eld)
  834. {
  835. /*
  836. * Always execute a GetPinSense verb here, even when called from
  837. * hdmi_intrinsic_event; for some NVIDIA HW, the unsolicited
  838. * response's PD bit is not the real PD value, but indicates that
  839. * the real PD value changed. An older version of the HD-audio
  840. * specification worked this way. Hence, we just ignore the data in
  841. * the unsolicited response to avoid custom WARs.
  842. */
  843. int present = snd_hda_pin_sense(codec, pin_nid);
  844. memset(eld, 0, sizeof(*eld));
  845. eld->monitor_present = !!(present & AC_PINSENSE_PRESENCE);
  846. if (eld->monitor_present)
  847. eld->eld_valid = !!(present & AC_PINSENSE_ELDV);
  848. else
  849. eld->eld_valid = 0;
  850. printk(KERN_INFO
  851. "HDMI status: Codec=%d Pin=%d Presence_Detect=%d ELD_Valid=%d\n",
  852. codec->addr, pin_nid, eld->monitor_present, eld->eld_valid);
  853. if (eld->eld_valid)
  854. if (!snd_hdmi_get_eld(eld, codec, pin_nid))
  855. snd_hdmi_show_eld(eld);
  856. snd_hda_input_jack_report(codec, pin_nid);
  857. }
  858. static int hdmi_add_pin(struct hda_codec *codec, hda_nid_t pin_nid)
  859. {
  860. struct hdmi_spec *spec = codec->spec;
  861. unsigned int caps, config;
  862. int pin_idx;
  863. struct hdmi_spec_per_pin *per_pin;
  864. int err;
  865. caps = snd_hda_param_read(codec, pin_nid, AC_PAR_PIN_CAP);
  866. if (!(caps & (AC_PINCAP_HDMI | AC_PINCAP_DP)))
  867. return 0;
  868. config = snd_hda_codec_read(codec, pin_nid, 0,
  869. AC_VERB_GET_CONFIG_DEFAULT, 0);
  870. if (get_defcfg_connect(config) == AC_JACK_PORT_NONE)
  871. return 0;
  872. if (snd_BUG_ON(spec->num_pins >= MAX_HDMI_PINS))
  873. return -E2BIG;
  874. pin_idx = spec->num_pins;
  875. per_pin = &spec->pins[pin_idx];
  876. per_pin->pin_nid = pin_nid;
  877. err = hdmi_read_pin_conn(codec, pin_idx);
  878. if (err < 0)
  879. return err;
  880. spec->num_pins++;
  881. return 0;
  882. }
  883. static int hdmi_add_cvt(struct hda_codec *codec, hda_nid_t cvt_nid)
  884. {
  885. struct hdmi_spec *spec = codec->spec;
  886. int cvt_idx;
  887. struct hdmi_spec_per_cvt *per_cvt;
  888. unsigned int chans;
  889. int err;
  890. if (snd_BUG_ON(spec->num_cvts >= MAX_HDMI_CVTS))
  891. return -E2BIG;
  892. chans = get_wcaps(codec, cvt_nid);
  893. chans = get_wcaps_channels(chans);
  894. cvt_idx = spec->num_cvts;
  895. per_cvt = &spec->cvts[cvt_idx];
  896. per_cvt->cvt_nid = cvt_nid;
  897. per_cvt->channels_min = 2;
  898. if (chans <= 16)
  899. per_cvt->channels_max = chans;
  900. err = snd_hda_query_supported_pcm(codec, cvt_nid,
  901. &per_cvt->rates,
  902. &per_cvt->formats,
  903. &per_cvt->maxbps);
  904. if (err < 0)
  905. return err;
  906. spec->num_cvts++;
  907. return 0;
  908. }
  909. static int hdmi_parse_codec(struct hda_codec *codec)
  910. {
  911. hda_nid_t nid;
  912. int i, nodes;
  913. nodes = snd_hda_get_sub_nodes(codec, codec->afg, &nid);
  914. if (!nid || nodes < 0) {
  915. snd_printk(KERN_WARNING "HDMI: failed to get afg sub nodes\n");
  916. return -EINVAL;
  917. }
  918. for (i = 0; i < nodes; i++, nid++) {
  919. unsigned int caps;
  920. unsigned int type;
  921. caps = snd_hda_param_read(codec, nid, AC_PAR_AUDIO_WIDGET_CAP);
  922. type = get_wcaps_type(caps);
  923. if (!(caps & AC_WCAP_DIGITAL))
  924. continue;
  925. switch (type) {
  926. case AC_WID_AUD_OUT:
  927. hdmi_add_cvt(codec, nid);
  928. break;
  929. case AC_WID_PIN:
  930. hdmi_add_pin(codec, nid);
  931. break;
  932. }
  933. }
  934. /*
  935. * G45/IbexPeak don't support EPSS: the unsolicited pin hot plug event
  936. * can be lost and presence sense verb will become inaccurate if the
  937. * HDA link is powered off at hot plug or hw initialization time.
  938. */
  939. #ifdef CONFIG_SND_HDA_POWER_SAVE
  940. if (!(snd_hda_param_read(codec, codec->afg, AC_PAR_POWER_STATE) &
  941. AC_PWRST_EPSS))
  942. codec->bus->power_keep_link_on = 1;
  943. #endif
  944. return 0;
  945. }
  946. /*
  947. */
  948. static char *generic_hdmi_pcm_names[MAX_HDMI_PINS] = {
  949. "HDMI 0",
  950. "HDMI 1",
  951. "HDMI 2",
  952. "HDMI 3",
  953. };
  954. /*
  955. * HDMI callbacks
  956. */
  957. static int generic_hdmi_playback_pcm_prepare(struct hda_pcm_stream *hinfo,
  958. struct hda_codec *codec,
  959. unsigned int stream_tag,
  960. unsigned int format,
  961. struct snd_pcm_substream *substream)
  962. {
  963. hda_nid_t cvt_nid = hinfo->nid;
  964. struct hdmi_spec *spec = codec->spec;
  965. int pin_idx = hinfo_to_pin_index(spec, hinfo);
  966. hda_nid_t pin_nid = spec->pins[pin_idx].pin_nid;
  967. hdmi_set_channel_count(codec, cvt_nid, substream->runtime->channels);
  968. hdmi_setup_audio_infoframe(codec, pin_idx, substream);
  969. return hdmi_setup_stream(codec, cvt_nid, pin_nid, stream_tag, format);
  970. }
  971. static int generic_hdmi_playback_pcm_cleanup(struct hda_pcm_stream *hinfo,
  972. struct hda_codec *codec,
  973. struct snd_pcm_substream *substream)
  974. {
  975. struct hdmi_spec *spec = codec->spec;
  976. int cvt_idx, pin_idx;
  977. struct hdmi_spec_per_cvt *per_cvt;
  978. struct hdmi_spec_per_pin *per_pin;
  979. int pinctl;
  980. snd_hda_codec_cleanup_stream(codec, hinfo->nid);
  981. if (hinfo->nid) {
  982. cvt_idx = cvt_nid_to_cvt_index(spec, hinfo->nid);
  983. if (snd_BUG_ON(cvt_idx < 0))
  984. return -EINVAL;
  985. per_cvt = &spec->cvts[cvt_idx];
  986. snd_BUG_ON(!per_cvt->assigned);
  987. per_cvt->assigned = 0;
  988. hinfo->nid = 0;
  989. pin_idx = hinfo_to_pin_index(spec, hinfo);
  990. if (snd_BUG_ON(pin_idx < 0))
  991. return -EINVAL;
  992. per_pin = &spec->pins[pin_idx];
  993. pinctl = snd_hda_codec_read(codec, per_pin->pin_nid, 0,
  994. AC_VERB_GET_PIN_WIDGET_CONTROL, 0);
  995. snd_hda_codec_write(codec, per_pin->pin_nid, 0,
  996. AC_VERB_SET_PIN_WIDGET_CONTROL,
  997. pinctl & ~PIN_OUT);
  998. snd_hda_spdif_ctls_unassign(codec, pin_idx);
  999. }
  1000. return 0;
  1001. }
  1002. static const struct hda_pcm_ops generic_ops = {
  1003. .open = hdmi_pcm_open,
  1004. .prepare = generic_hdmi_playback_pcm_prepare,
  1005. .cleanup = generic_hdmi_playback_pcm_cleanup,
  1006. };
  1007. static int generic_hdmi_build_pcms(struct hda_codec *codec)
  1008. {
  1009. struct hdmi_spec *spec = codec->spec;
  1010. int pin_idx;
  1011. for (pin_idx = 0; pin_idx < spec->num_pins; pin_idx++) {
  1012. struct hda_pcm *info;
  1013. struct hda_pcm_stream *pstr;
  1014. info = &spec->pcm_rec[pin_idx];
  1015. info->name = generic_hdmi_pcm_names[pin_idx];
  1016. info->pcm_type = HDA_PCM_TYPE_HDMI;
  1017. pstr = &info->stream[SNDRV_PCM_STREAM_PLAYBACK];
  1018. pstr->substreams = 1;
  1019. pstr->ops = generic_ops;
  1020. /* other pstr fields are set in open */
  1021. }
  1022. codec->num_pcms = spec->num_pins;
  1023. codec->pcm_info = spec->pcm_rec;
  1024. return 0;
  1025. }
  1026. static int generic_hdmi_build_jack(struct hda_codec *codec, int pin_idx)
  1027. {
  1028. int err;
  1029. char hdmi_str[32];
  1030. struct hdmi_spec *spec = codec->spec;
  1031. struct hdmi_spec_per_pin *per_pin = &spec->pins[pin_idx];
  1032. int pcmdev = spec->pcm_rec[pin_idx].device;
  1033. snprintf(hdmi_str, sizeof(hdmi_str), "HDMI/DP,pcm=%d", pcmdev);
  1034. err = snd_hda_input_jack_add(codec, per_pin->pin_nid,
  1035. SND_JACK_VIDEOOUT, pcmdev > 0 ? hdmi_str : NULL);
  1036. if (err < 0)
  1037. return err;
  1038. hdmi_present_sense(codec, per_pin->pin_nid, &per_pin->sink_eld);
  1039. return 0;
  1040. }
  1041. static int generic_hdmi_build_controls(struct hda_codec *codec)
  1042. {
  1043. struct hdmi_spec *spec = codec->spec;
  1044. int err;
  1045. int pin_idx;
  1046. for (pin_idx = 0; pin_idx < spec->num_pins; pin_idx++) {
  1047. struct hdmi_spec_per_pin *per_pin = &spec->pins[pin_idx];
  1048. err = generic_hdmi_build_jack(codec, pin_idx);
  1049. if (err < 0)
  1050. return err;
  1051. err = snd_hda_create_spdif_out_ctls(codec,
  1052. per_pin->pin_nid,
  1053. per_pin->mux_nids[0]);
  1054. if (err < 0)
  1055. return err;
  1056. snd_hda_spdif_ctls_unassign(codec, pin_idx);
  1057. /* add control for ELD Bytes */
  1058. err = hdmi_create_eld_ctl(codec,
  1059. pin_idx,
  1060. spec->pcm_rec[pin_idx].device);
  1061. if (err < 0)
  1062. return err;
  1063. }
  1064. return 0;
  1065. }
  1066. static int generic_hdmi_init(struct hda_codec *codec)
  1067. {
  1068. struct hdmi_spec *spec = codec->spec;
  1069. int pin_idx;
  1070. for (pin_idx = 0; pin_idx < spec->num_pins; pin_idx++) {
  1071. struct hdmi_spec_per_pin *per_pin = &spec->pins[pin_idx];
  1072. hda_nid_t pin_nid = per_pin->pin_nid;
  1073. struct hdmi_eld *eld = &per_pin->sink_eld;
  1074. hdmi_init_pin(codec, pin_nid);
  1075. snd_hda_codec_write(codec, pin_nid, 0,
  1076. AC_VERB_SET_UNSOLICITED_ENABLE,
  1077. AC_USRSP_EN | pin_nid);
  1078. snd_hda_eld_proc_new(codec, eld, pin_idx);
  1079. }
  1080. return 0;
  1081. }
  1082. static void generic_hdmi_free(struct hda_codec *codec)
  1083. {
  1084. struct hdmi_spec *spec = codec->spec;
  1085. int pin_idx;
  1086. for (pin_idx = 0; pin_idx < spec->num_pins; pin_idx++) {
  1087. struct hdmi_spec_per_pin *per_pin = &spec->pins[pin_idx];
  1088. struct hdmi_eld *eld = &per_pin->sink_eld;
  1089. snd_hda_eld_proc_free(codec, eld);
  1090. }
  1091. snd_hda_input_jack_free(codec);
  1092. kfree(spec);
  1093. }
  1094. static const struct hda_codec_ops generic_hdmi_patch_ops = {
  1095. .init = generic_hdmi_init,
  1096. .free = generic_hdmi_free,
  1097. .build_pcms = generic_hdmi_build_pcms,
  1098. .build_controls = generic_hdmi_build_controls,
  1099. .unsol_event = hdmi_unsol_event,
  1100. };
  1101. static int patch_generic_hdmi(struct hda_codec *codec)
  1102. {
  1103. struct hdmi_spec *spec;
  1104. spec = kzalloc(sizeof(*spec), GFP_KERNEL);
  1105. if (spec == NULL)
  1106. return -ENOMEM;
  1107. codec->spec = spec;
  1108. if (hdmi_parse_codec(codec) < 0) {
  1109. codec->spec = NULL;
  1110. kfree(spec);
  1111. return -EINVAL;
  1112. }
  1113. codec->patch_ops = generic_hdmi_patch_ops;
  1114. init_channel_allocations();
  1115. return 0;
  1116. }
  1117. /*
  1118. * Shared non-generic implementations
  1119. */
  1120. static int simple_playback_build_pcms(struct hda_codec *codec)
  1121. {
  1122. struct hdmi_spec *spec = codec->spec;
  1123. struct hda_pcm *info = spec->pcm_rec;
  1124. int i;
  1125. codec->num_pcms = spec->num_cvts;
  1126. codec->pcm_info = info;
  1127. for (i = 0; i < codec->num_pcms; i++, info++) {
  1128. unsigned int chans;
  1129. struct hda_pcm_stream *pstr;
  1130. chans = get_wcaps(codec, spec->cvts[i].cvt_nid);
  1131. chans = get_wcaps_channels(chans);
  1132. info->name = generic_hdmi_pcm_names[i];
  1133. info->pcm_type = HDA_PCM_TYPE_HDMI;
  1134. pstr = &info->stream[SNDRV_PCM_STREAM_PLAYBACK];
  1135. snd_BUG_ON(!spec->pcm_playback);
  1136. *pstr = *spec->pcm_playback;
  1137. pstr->nid = spec->cvts[i].cvt_nid;
  1138. if (pstr->channels_max <= 2 && chans && chans <= 16)
  1139. pstr->channels_max = chans;
  1140. }
  1141. return 0;
  1142. }
  1143. static int simple_playback_build_controls(struct hda_codec *codec)
  1144. {
  1145. struct hdmi_spec *spec = codec->spec;
  1146. int err;
  1147. int i;
  1148. for (i = 0; i < codec->num_pcms; i++) {
  1149. err = snd_hda_create_spdif_out_ctls(codec,
  1150. spec->cvts[i].cvt_nid,
  1151. spec->cvts[i].cvt_nid);
  1152. if (err < 0)
  1153. return err;
  1154. }
  1155. return 0;
  1156. }
  1157. static void simple_playback_free(struct hda_codec *codec)
  1158. {
  1159. struct hdmi_spec *spec = codec->spec;
  1160. kfree(spec);
  1161. }
  1162. /*
  1163. * Nvidia specific implementations
  1164. */
  1165. #define Nv_VERB_SET_Channel_Allocation 0xF79
  1166. #define Nv_VERB_SET_Info_Frame_Checksum 0xF7A
  1167. #define Nv_VERB_SET_Audio_Protection_On 0xF98
  1168. #define Nv_VERB_SET_Audio_Protection_Off 0xF99
  1169. #define nvhdmi_master_con_nid_7x 0x04
  1170. #define nvhdmi_master_pin_nid_7x 0x05
  1171. static const hda_nid_t nvhdmi_con_nids_7x[4] = {
  1172. /*front, rear, clfe, rear_surr */
  1173. 0x6, 0x8, 0xa, 0xc,
  1174. };
  1175. static const struct hda_verb nvhdmi_basic_init_7x[] = {
  1176. /* set audio protect on */
  1177. { 0x1, Nv_VERB_SET_Audio_Protection_On, 0x1},
  1178. /* enable digital output on pin widget */
  1179. { 0x5, AC_VERB_SET_PIN_WIDGET_CONTROL, PIN_OUT | 0x5 },
  1180. { 0x7, AC_VERB_SET_PIN_WIDGET_CONTROL, PIN_OUT | 0x5 },
  1181. { 0x9, AC_VERB_SET_PIN_WIDGET_CONTROL, PIN_OUT | 0x5 },
  1182. { 0xb, AC_VERB_SET_PIN_WIDGET_CONTROL, PIN_OUT | 0x5 },
  1183. { 0xd, AC_VERB_SET_PIN_WIDGET_CONTROL, PIN_OUT | 0x5 },
  1184. {} /* terminator */
  1185. };
  1186. #ifdef LIMITED_RATE_FMT_SUPPORT
  1187. /* support only the safe format and rate */
  1188. #define SUPPORTED_RATES SNDRV_PCM_RATE_48000
  1189. #define SUPPORTED_MAXBPS 16
  1190. #define SUPPORTED_FORMATS SNDRV_PCM_FMTBIT_S16_LE
  1191. #else
  1192. /* support all rates and formats */
  1193. #define SUPPORTED_RATES \
  1194. (SNDRV_PCM_RATE_32000 | SNDRV_PCM_RATE_44100 | SNDRV_PCM_RATE_48000 |\
  1195. SNDRV_PCM_RATE_88200 | SNDRV_PCM_RATE_96000 | SNDRV_PCM_RATE_176400 |\
  1196. SNDRV_PCM_RATE_192000)
  1197. #define SUPPORTED_MAXBPS 24
  1198. #define SUPPORTED_FORMATS \
  1199. (SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S32_LE)
  1200. #endif
  1201. static int nvhdmi_7x_init(struct hda_codec *codec)
  1202. {
  1203. snd_hda_sequence_write(codec, nvhdmi_basic_init_7x);
  1204. return 0;
  1205. }
  1206. static unsigned int channels_2_6_8[] = {
  1207. 2, 6, 8
  1208. };
  1209. static unsigned int channels_2_8[] = {
  1210. 2, 8
  1211. };
  1212. static struct snd_pcm_hw_constraint_list hw_constraints_2_6_8_channels = {
  1213. .count = ARRAY_SIZE(channels_2_6_8),
  1214. .list = channels_2_6_8,
  1215. .mask = 0,
  1216. };
  1217. static struct snd_pcm_hw_constraint_list hw_constraints_2_8_channels = {
  1218. .count = ARRAY_SIZE(channels_2_8),
  1219. .list = channels_2_8,
  1220. .mask = 0,
  1221. };
  1222. static int simple_playback_pcm_open(struct hda_pcm_stream *hinfo,
  1223. struct hda_codec *codec,
  1224. struct snd_pcm_substream *substream)
  1225. {
  1226. struct hdmi_spec *spec = codec->spec;
  1227. struct snd_pcm_hw_constraint_list *hw_constraints_channels = NULL;
  1228. switch (codec->preset->id) {
  1229. case 0x10de0002:
  1230. case 0x10de0003:
  1231. case 0x10de0005:
  1232. case 0x10de0006:
  1233. hw_constraints_channels = &hw_constraints_2_8_channels;
  1234. break;
  1235. case 0x10de0007:
  1236. hw_constraints_channels = &hw_constraints_2_6_8_channels;
  1237. break;
  1238. default:
  1239. break;
  1240. }
  1241. if (hw_constraints_channels != NULL) {
  1242. snd_pcm_hw_constraint_list(substream->runtime, 0,
  1243. SNDRV_PCM_HW_PARAM_CHANNELS,
  1244. hw_constraints_channels);
  1245. } else {
  1246. snd_pcm_hw_constraint_step(substream->runtime, 0,
  1247. SNDRV_PCM_HW_PARAM_CHANNELS, 2);
  1248. }
  1249. return snd_hda_multi_out_dig_open(codec, &spec->multiout);
  1250. }
  1251. static int simple_playback_pcm_close(struct hda_pcm_stream *hinfo,
  1252. struct hda_codec *codec,
  1253. struct snd_pcm_substream *substream)
  1254. {
  1255. struct hdmi_spec *spec = codec->spec;
  1256. return snd_hda_multi_out_dig_close(codec, &spec->multiout);
  1257. }
  1258. static int simple_playback_pcm_prepare(struct hda_pcm_stream *hinfo,
  1259. struct hda_codec *codec,
  1260. unsigned int stream_tag,
  1261. unsigned int format,
  1262. struct snd_pcm_substream *substream)
  1263. {
  1264. struct hdmi_spec *spec = codec->spec;
  1265. return snd_hda_multi_out_dig_prepare(codec, &spec->multiout,
  1266. stream_tag, format, substream);
  1267. }
  1268. static void nvhdmi_8ch_7x_set_info_frame_parameters(struct hda_codec *codec,
  1269. int channels)
  1270. {
  1271. unsigned int chanmask;
  1272. int chan = channels ? (channels - 1) : 1;
  1273. switch (channels) {
  1274. default:
  1275. case 0:
  1276. case 2:
  1277. chanmask = 0x00;
  1278. break;
  1279. case 4:
  1280. chanmask = 0x08;
  1281. break;
  1282. case 6:
  1283. chanmask = 0x0b;
  1284. break;
  1285. case 8:
  1286. chanmask = 0x13;
  1287. break;
  1288. }
  1289. /* Set the audio infoframe channel allocation and checksum fields. The
  1290. * channel count is computed implicitly by the hardware. */
  1291. snd_hda_codec_write(codec, 0x1, 0,
  1292. Nv_VERB_SET_Channel_Allocation, chanmask);
  1293. snd_hda_codec_write(codec, 0x1, 0,
  1294. Nv_VERB_SET_Info_Frame_Checksum,
  1295. (0x71 - chan - chanmask));
  1296. }
  1297. static int nvhdmi_8ch_7x_pcm_close(struct hda_pcm_stream *hinfo,
  1298. struct hda_codec *codec,
  1299. struct snd_pcm_substream *substream)
  1300. {
  1301. struct hdmi_spec *spec = codec->spec;
  1302. int i;
  1303. snd_hda_codec_write(codec, nvhdmi_master_con_nid_7x,
  1304. 0, AC_VERB_SET_CHANNEL_STREAMID, 0);
  1305. for (i = 0; i < 4; i++) {
  1306. /* set the stream id */
  1307. snd_hda_codec_write(codec, nvhdmi_con_nids_7x[i], 0,
  1308. AC_VERB_SET_CHANNEL_STREAMID, 0);
  1309. /* set the stream format */
  1310. snd_hda_codec_write(codec, nvhdmi_con_nids_7x[i], 0,
  1311. AC_VERB_SET_STREAM_FORMAT, 0);
  1312. }
  1313. /* The audio hardware sends a channel count of 0x7 (8ch) when all the
  1314. * streams are disabled. */
  1315. nvhdmi_8ch_7x_set_info_frame_parameters(codec, 8);
  1316. return snd_hda_multi_out_dig_close(codec, &spec->multiout);
  1317. }
  1318. static int nvhdmi_8ch_7x_pcm_prepare(struct hda_pcm_stream *hinfo,
  1319. struct hda_codec *codec,
  1320. unsigned int stream_tag,
  1321. unsigned int format,
  1322. struct snd_pcm_substream *substream)
  1323. {
  1324. int chs;
  1325. unsigned int dataDCC2, channel_id;
  1326. int i;
  1327. struct hdmi_spec *spec = codec->spec;
  1328. struct hda_spdif_out *spdif =
  1329. snd_hda_spdif_out_of_nid(codec, spec->cvts[0].cvt_nid);
  1330. mutex_lock(&codec->spdif_mutex);
  1331. chs = substream->runtime->channels;
  1332. dataDCC2 = 0x2;
  1333. /* turn off SPDIF once; otherwise the IEC958 bits won't be updated */
  1334. if (codec->spdif_status_reset && (spdif->ctls & AC_DIG1_ENABLE))
  1335. snd_hda_codec_write(codec,
  1336. nvhdmi_master_con_nid_7x,
  1337. 0,
  1338. AC_VERB_SET_DIGI_CONVERT_1,
  1339. spdif->ctls & ~AC_DIG1_ENABLE & 0xff);
  1340. /* set the stream id */
  1341. snd_hda_codec_write(codec, nvhdmi_master_con_nid_7x, 0,
  1342. AC_VERB_SET_CHANNEL_STREAMID, (stream_tag << 4) | 0x0);
  1343. /* set the stream format */
  1344. snd_hda_codec_write(codec, nvhdmi_master_con_nid_7x, 0,
  1345. AC_VERB_SET_STREAM_FORMAT, format);
  1346. /* turn on again (if needed) */
  1347. /* enable and set the channel status audio/data flag */
  1348. if (codec->spdif_status_reset && (spdif->ctls & AC_DIG1_ENABLE)) {
  1349. snd_hda_codec_write(codec,
  1350. nvhdmi_master_con_nid_7x,
  1351. 0,
  1352. AC_VERB_SET_DIGI_CONVERT_1,
  1353. spdif->ctls & 0xff);
  1354. snd_hda_codec_write(codec,
  1355. nvhdmi_master_con_nid_7x,
  1356. 0,
  1357. AC_VERB_SET_DIGI_CONVERT_2, dataDCC2);
  1358. }
  1359. for (i = 0; i < 4; i++) {
  1360. if (chs == 2)
  1361. channel_id = 0;
  1362. else
  1363. channel_id = i * 2;
  1364. /* turn off SPDIF once;
  1365. *otherwise the IEC958 bits won't be updated
  1366. */
  1367. if (codec->spdif_status_reset &&
  1368. (spdif->ctls & AC_DIG1_ENABLE))
  1369. snd_hda_codec_write(codec,
  1370. nvhdmi_con_nids_7x[i],
  1371. 0,
  1372. AC_VERB_SET_DIGI_CONVERT_1,
  1373. spdif->ctls & ~AC_DIG1_ENABLE & 0xff);
  1374. /* set the stream id */
  1375. snd_hda_codec_write(codec,
  1376. nvhdmi_con_nids_7x[i],
  1377. 0,
  1378. AC_VERB_SET_CHANNEL_STREAMID,
  1379. (stream_tag << 4) | channel_id);
  1380. /* set the stream format */
  1381. snd_hda_codec_write(codec,
  1382. nvhdmi_con_nids_7x[i],
  1383. 0,
  1384. AC_VERB_SET_STREAM_FORMAT,
  1385. format);
  1386. /* turn on again (if needed) */
  1387. /* enable and set the channel status audio/data flag */
  1388. if (codec->spdif_status_reset &&
  1389. (spdif->ctls & AC_DIG1_ENABLE)) {
  1390. snd_hda_codec_write(codec,
  1391. nvhdmi_con_nids_7x[i],
  1392. 0,
  1393. AC_VERB_SET_DIGI_CONVERT_1,
  1394. spdif->ctls & 0xff);
  1395. snd_hda_codec_write(codec,
  1396. nvhdmi_con_nids_7x[i],
  1397. 0,
  1398. AC_VERB_SET_DIGI_CONVERT_2, dataDCC2);
  1399. }
  1400. }
  1401. nvhdmi_8ch_7x_set_info_frame_parameters(codec, chs);
  1402. mutex_unlock(&codec->spdif_mutex);
  1403. return 0;
  1404. }
  1405. static const struct hda_pcm_stream nvhdmi_pcm_playback_8ch_7x = {
  1406. .substreams = 1,
  1407. .channels_min = 2,
  1408. .channels_max = 8,
  1409. .nid = nvhdmi_master_con_nid_7x,
  1410. .rates = SUPPORTED_RATES,
  1411. .maxbps = SUPPORTED_MAXBPS,
  1412. .formats = SUPPORTED_FORMATS,
  1413. .ops = {
  1414. .open = simple_playback_pcm_open,
  1415. .close = nvhdmi_8ch_7x_pcm_close,
  1416. .prepare = nvhdmi_8ch_7x_pcm_prepare
  1417. },
  1418. };
  1419. static const struct hda_pcm_stream nvhdmi_pcm_playback_2ch = {
  1420. .substreams = 1,
  1421. .channels_min = 2,
  1422. .channels_max = 2,
  1423. .nid = nvhdmi_master_con_nid_7x,
  1424. .rates = SUPPORTED_RATES,
  1425. .maxbps = SUPPORTED_MAXBPS,
  1426. .formats = SUPPORTED_FORMATS,
  1427. .ops = {
  1428. .open = simple_playback_pcm_open,
  1429. .close = simple_playback_pcm_close,
  1430. .prepare = simple_playback_pcm_prepare
  1431. },
  1432. };
  1433. static const struct hda_codec_ops nvhdmi_patch_ops_8ch_7x = {
  1434. .build_controls = simple_playback_build_controls,
  1435. .build_pcms = simple_playback_build_pcms,
  1436. .init = nvhdmi_7x_init,
  1437. .free = simple_playback_free,
  1438. };
  1439. static const struct hda_codec_ops nvhdmi_patch_ops_2ch = {
  1440. .build_controls = simple_playback_build_controls,
  1441. .build_pcms = simple_playback_build_pcms,
  1442. .init = nvhdmi_7x_init,
  1443. .free = simple_playback_free,
  1444. };
  1445. static int patch_nvhdmi_2ch(struct hda_codec *codec)
  1446. {
  1447. struct hdmi_spec *spec;
  1448. spec = kzalloc(sizeof(*spec), GFP_KERNEL);
  1449. if (spec == NULL)
  1450. return -ENOMEM;
  1451. codec->spec = spec;
  1452. spec->multiout.num_dacs = 0; /* no analog */
  1453. spec->multiout.max_channels = 2;
  1454. spec->multiout.dig_out_nid = nvhdmi_master_con_nid_7x;
  1455. spec->num_cvts = 1;
  1456. spec->cvts[0].cvt_nid = nvhdmi_master_con_nid_7x;
  1457. spec->pcm_playback = &nvhdmi_pcm_playback_2ch;
  1458. codec->patch_ops = nvhdmi_patch_ops_2ch;
  1459. return 0;
  1460. }
  1461. static int patch_nvhdmi_8ch_7x(struct hda_codec *codec)
  1462. {
  1463. struct hdmi_spec *spec;
  1464. int err = patch_nvhdmi_2ch(codec);
  1465. if (err < 0)
  1466. return err;
  1467. spec = codec->spec;
  1468. spec->multiout.max_channels = 8;
  1469. spec->pcm_playback = &nvhdmi_pcm_playback_8ch_7x;
  1470. codec->patch_ops = nvhdmi_patch_ops_8ch_7x;
  1471. /* Initialize the audio infoframe channel mask and checksum to something
  1472. * valid */
  1473. nvhdmi_8ch_7x_set_info_frame_parameters(codec, 8);
  1474. return 0;
  1475. }
  1476. /*
  1477. * ATI-specific implementations
  1478. *
  1479. * FIXME: we may omit the whole this and use the generic code once after
  1480. * it's confirmed to work.
  1481. */
  1482. #define ATIHDMI_CVT_NID 0x02 /* audio converter */
  1483. #define ATIHDMI_PIN_NID 0x03 /* HDMI output pin */
  1484. static int atihdmi_playback_pcm_prepare(struct hda_pcm_stream *hinfo,
  1485. struct hda_codec *codec,
  1486. unsigned int stream_tag,
  1487. unsigned int format,
  1488. struct snd_pcm_substream *substream)
  1489. {
  1490. struct hdmi_spec *spec = codec->spec;
  1491. int chans = substream->runtime->channels;
  1492. int i, err;
  1493. err = simple_playback_pcm_prepare(hinfo, codec, stream_tag, format,
  1494. substream);
  1495. if (err < 0)
  1496. return err;
  1497. snd_hda_codec_write(codec, spec->cvts[0].cvt_nid, 0,
  1498. AC_VERB_SET_CVT_CHAN_COUNT, chans - 1);
  1499. /* FIXME: XXX */
  1500. for (i = 0; i < chans; i++) {
  1501. snd_hda_codec_write(codec, spec->cvts[0].cvt_nid, 0,
  1502. AC_VERB_SET_HDMI_CHAN_SLOT,
  1503. (i << 4) | i);
  1504. }
  1505. return 0;
  1506. }
  1507. static const struct hda_pcm_stream atihdmi_pcm_digital_playback = {
  1508. .substreams = 1,
  1509. .channels_min = 2,
  1510. .channels_max = 2,
  1511. .nid = ATIHDMI_CVT_NID,
  1512. .ops = {
  1513. .open = simple_playback_pcm_open,
  1514. .close = simple_playback_pcm_close,
  1515. .prepare = atihdmi_playback_pcm_prepare
  1516. },
  1517. };
  1518. static const struct hda_verb atihdmi_basic_init[] = {
  1519. /* enable digital output on pin widget */
  1520. { 0x03, AC_VERB_SET_PIN_WIDGET_CONTROL, PIN_OUT },
  1521. {} /* terminator */
  1522. };
  1523. static int atihdmi_init(struct hda_codec *codec)
  1524. {
  1525. struct hdmi_spec *spec = codec->spec;
  1526. snd_hda_sequence_write(codec, atihdmi_basic_init);
  1527. /* SI codec requires to unmute the pin */
  1528. if (get_wcaps(codec, spec->pins[0].pin_nid) & AC_WCAP_OUT_AMP)
  1529. snd_hda_codec_write(codec, spec->pins[0].pin_nid, 0,
  1530. AC_VERB_SET_AMP_GAIN_MUTE,
  1531. AMP_OUT_UNMUTE);
  1532. return 0;
  1533. }
  1534. static const struct hda_codec_ops atihdmi_patch_ops = {
  1535. .build_controls = simple_playback_build_controls,
  1536. .build_pcms = simple_playback_build_pcms,
  1537. .init = atihdmi_init,
  1538. .free = simple_playback_free,
  1539. };
  1540. static int patch_atihdmi(struct hda_codec *codec)
  1541. {
  1542. struct hdmi_spec *spec;
  1543. spec = kzalloc(sizeof(*spec), GFP_KERNEL);
  1544. if (spec == NULL)
  1545. return -ENOMEM;
  1546. codec->spec = spec;
  1547. spec->multiout.num_dacs = 0; /* no analog */
  1548. spec->multiout.max_channels = 2;
  1549. spec->multiout.dig_out_nid = ATIHDMI_CVT_NID;
  1550. spec->num_cvts = 1;
  1551. spec->cvts[0].cvt_nid = ATIHDMI_CVT_NID;
  1552. spec->pins[0].pin_nid = ATIHDMI_PIN_NID;
  1553. spec->pcm_playback = &atihdmi_pcm_digital_playback;
  1554. codec->patch_ops = atihdmi_patch_ops;
  1555. return 0;
  1556. }
  1557. /*
  1558. * patch entries
  1559. */
  1560. static const struct hda_codec_preset snd_hda_preset_hdmi[] = {
  1561. { .id = 0x1002793c, .name = "RS600 HDMI", .patch = patch_atihdmi },
  1562. { .id = 0x10027919, .name = "RS600 HDMI", .patch = patch_atihdmi },
  1563. { .id = 0x1002791a, .name = "RS690/780 HDMI", .patch = patch_atihdmi },
  1564. { .id = 0x1002aa01, .name = "R6xx HDMI", .patch = patch_generic_hdmi },
  1565. { .id = 0x10951390, .name = "SiI1390 HDMI", .patch = patch_generic_hdmi },
  1566. { .id = 0x10951392, .name = "SiI1392 HDMI", .patch = patch_generic_hdmi },
  1567. { .id = 0x17e80047, .name = "Chrontel HDMI", .patch = patch_generic_hdmi },
  1568. { .id = 0x10de0002, .name = "MCP77/78 HDMI", .patch = patch_nvhdmi_8ch_7x },
  1569. { .id = 0x10de0003, .name = "MCP77/78 HDMI", .patch = patch_nvhdmi_8ch_7x },
  1570. { .id = 0x10de0005, .name = "MCP77/78 HDMI", .patch = patch_nvhdmi_8ch_7x },
  1571. { .id = 0x10de0006, .name = "MCP77/78 HDMI", .patch = patch_nvhdmi_8ch_7x },
  1572. { .id = 0x10de0007, .name = "MCP79/7A HDMI", .patch = patch_nvhdmi_8ch_7x },
  1573. { .id = 0x10de000a, .name = "GPU 0a HDMI/DP", .patch = patch_generic_hdmi },
  1574. { .id = 0x10de000b, .name = "GPU 0b HDMI/DP", .patch = patch_generic_hdmi },
  1575. { .id = 0x10de000c, .name = "MCP89 HDMI", .patch = patch_generic_hdmi },
  1576. { .id = 0x10de000d, .name = "GPU 0d HDMI/DP", .patch = patch_generic_hdmi },
  1577. { .id = 0x10de0010, .name = "GPU 10 HDMI/DP", .patch = patch_generic_hdmi },
  1578. { .id = 0x10de0011, .name = "GPU 11 HDMI/DP", .patch = patch_generic_hdmi },
  1579. { .id = 0x10de0012, .name = "GPU 12 HDMI/DP", .patch = patch_generic_hdmi },
  1580. { .id = 0x10de0013, .name = "GPU 13 HDMI/DP", .patch = patch_generic_hdmi },
  1581. { .id = 0x10de0014, .name = "GPU 14 HDMI/DP", .patch = patch_generic_hdmi },
  1582. { .id = 0x10de0015, .name = "GPU 15 HDMI/DP", .patch = patch_generic_hdmi },
  1583. { .id = 0x10de0016, .name = "GPU 16 HDMI/DP", .patch = patch_generic_hdmi },
  1584. /* 17 is known to be absent */
  1585. { .id = 0x10de0018, .name = "GPU 18 HDMI/DP", .patch = patch_generic_hdmi },
  1586. { .id = 0x10de0019, .name = "GPU 19 HDMI/DP", .patch = patch_generic_hdmi },
  1587. { .id = 0x10de001a, .name = "GPU 1a HDMI/DP", .patch = patch_generic_hdmi },
  1588. { .id = 0x10de001b, .name = "GPU 1b HDMI/DP", .patch = patch_generic_hdmi },
  1589. { .id = 0x10de001c, .name = "GPU 1c HDMI/DP", .patch = patch_generic_hdmi },
  1590. { .id = 0x10de0040, .name = "GPU 40 HDMI/DP", .patch = patch_generic_hdmi },
  1591. { .id = 0x10de0041, .name = "GPU 41 HDMI/DP", .patch = patch_generic_hdmi },
  1592. { .id = 0x10de0042, .name = "GPU 42 HDMI/DP", .patch = patch_generic_hdmi },
  1593. { .id = 0x10de0043, .name = "GPU 43 HDMI/DP", .patch = patch_generic_hdmi },
  1594. { .id = 0x10de0044, .name = "GPU 44 HDMI/DP", .patch = patch_generic_hdmi },
  1595. { .id = 0x10de0067, .name = "MCP67 HDMI", .patch = patch_nvhdmi_2ch },
  1596. { .id = 0x10de8001, .name = "MCP73 HDMI", .patch = patch_nvhdmi_2ch },
  1597. { .id = 0x80860054, .name = "IbexPeak HDMI", .patch = patch_generic_hdmi },
  1598. { .id = 0x80862801, .name = "Bearlake HDMI", .patch = patch_generic_hdmi },
  1599. { .id = 0x80862802, .name = "Cantiga HDMI", .patch = patch_generic_hdmi },
  1600. { .id = 0x80862803, .name = "Eaglelake HDMI", .patch = patch_generic_hdmi },
  1601. { .id = 0x80862804, .name = "IbexPeak HDMI", .patch = patch_generic_hdmi },
  1602. { .id = 0x80862805, .name = "CougarPoint HDMI", .patch = patch_generic_hdmi },
  1603. { .id = 0x80862806, .name = "PantherPoint HDMI", .patch = patch_generic_hdmi },
  1604. { .id = 0x808629fb, .name = "Crestline HDMI", .patch = patch_generic_hdmi },
  1605. {} /* terminator */
  1606. };
  1607. MODULE_ALIAS("snd-hda-codec-id:1002793c");
  1608. MODULE_ALIAS("snd-hda-codec-id:10027919");
  1609. MODULE_ALIAS("snd-hda-codec-id:1002791a");
  1610. MODULE_ALIAS("snd-hda-codec-id:1002aa01");
  1611. MODULE_ALIAS("snd-hda-codec-id:10951390");
  1612. MODULE_ALIAS("snd-hda-codec-id:10951392");
  1613. MODULE_ALIAS("snd-hda-codec-id:10de0002");
  1614. MODULE_ALIAS("snd-hda-codec-id:10de0003");
  1615. MODULE_ALIAS("snd-hda-codec-id:10de0005");
  1616. MODULE_ALIAS("snd-hda-codec-id:10de0006");
  1617. MODULE_ALIAS("snd-hda-codec-id:10de0007");
  1618. MODULE_ALIAS("snd-hda-codec-id:10de000a");
  1619. MODULE_ALIAS("snd-hda-codec-id:10de000b");
  1620. MODULE_ALIAS("snd-hda-codec-id:10de000c");
  1621. MODULE_ALIAS("snd-hda-codec-id:10de000d");
  1622. MODULE_ALIAS("snd-hda-codec-id:10de0010");
  1623. MODULE_ALIAS("snd-hda-codec-id:10de0011");
  1624. MODULE_ALIAS("snd-hda-codec-id:10de0012");
  1625. MODULE_ALIAS("snd-hda-codec-id:10de0013");
  1626. MODULE_ALIAS("snd-hda-codec-id:10de0014");
  1627. MODULE_ALIAS("snd-hda-codec-id:10de0015");
  1628. MODULE_ALIAS("snd-hda-codec-id:10de0016");
  1629. MODULE_ALIAS("snd-hda-codec-id:10de0018");
  1630. MODULE_ALIAS("snd-hda-codec-id:10de0019");
  1631. MODULE_ALIAS("snd-hda-codec-id:10de001a");
  1632. MODULE_ALIAS("snd-hda-codec-id:10de001b");
  1633. MODULE_ALIAS("snd-hda-codec-id:10de001c");
  1634. MODULE_ALIAS("snd-hda-codec-id:10de0040");
  1635. MODULE_ALIAS("snd-hda-codec-id:10de0041");
  1636. MODULE_ALIAS("snd-hda-codec-id:10de0042");
  1637. MODULE_ALIAS("snd-hda-codec-id:10de0043");
  1638. MODULE_ALIAS("snd-hda-codec-id:10de0044");
  1639. MODULE_ALIAS("snd-hda-codec-id:10de0067");
  1640. MODULE_ALIAS("snd-hda-codec-id:10de8001");
  1641. MODULE_ALIAS("snd-hda-codec-id:17e80047");
  1642. MODULE_ALIAS("snd-hda-codec-id:80860054");
  1643. MODULE_ALIAS("snd-hda-codec-id:80862801");
  1644. MODULE_ALIAS("snd-hda-codec-id:80862802");
  1645. MODULE_ALIAS("snd-hda-codec-id:80862803");
  1646. MODULE_ALIAS("snd-hda-codec-id:80862804");
  1647. MODULE_ALIAS("snd-hda-codec-id:80862805");
  1648. MODULE_ALIAS("snd-hda-codec-id:80862806");
  1649. MODULE_ALIAS("snd-hda-codec-id:808629fb");
  1650. MODULE_LICENSE("GPL");
  1651. MODULE_DESCRIPTION("HDMI HD-audio codec");
  1652. MODULE_ALIAS("snd-hda-codec-intelhdmi");
  1653. MODULE_ALIAS("snd-hda-codec-nvhdmi");
  1654. MODULE_ALIAS("snd-hda-codec-atihdmi");
  1655. static struct hda_codec_preset_list intel_list = {
  1656. .preset = snd_hda_preset_hdmi,
  1657. .owner = THIS_MODULE,
  1658. };
  1659. static int __init patch_hdmi_init(void)
  1660. {
  1661. return snd_hda_add_codec_preset(&intel_list);
  1662. }
  1663. static void __exit patch_hdmi_exit(void)
  1664. {
  1665. snd_hda_delete_codec_preset(&intel_list);
  1666. }
  1667. module_init(patch_hdmi_init)
  1668. module_exit(patch_hdmi_exit)