patch_ca0132.c 28 KB

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  1. /*
  2. * HD audio interface patch for Creative CA0132 chip
  3. *
  4. * Copyright (c) 2011, Creative Technology Ltd.
  5. *
  6. * Based on patch_ca0110.c
  7. * Copyright (c) 2008 Takashi Iwai <tiwai@suse.de>
  8. *
  9. * This driver is free software; you can redistribute it and/or modify
  10. * it under the terms of the GNU General Public License as published by
  11. * the Free Software Foundation; either version 2 of the License, or
  12. * (at your option) any later version.
  13. *
  14. * This driver is distributed in the hope that it will be useful,
  15. * but WITHOUT ANY WARRANTY; without even the implied warranty of
  16. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  17. * GNU General Public License for more details.
  18. *
  19. * You should have received a copy of the GNU General Public License
  20. * along with this program; if not, write to the Free Software
  21. * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
  22. */
  23. #include <linux/init.h>
  24. #include <linux/delay.h>
  25. #include <linux/slab.h>
  26. #include <linux/pci.h>
  27. #include <linux/mutex.h>
  28. #include <linux/module.h>
  29. #include <sound/core.h>
  30. #include "hda_codec.h"
  31. #include "hda_local.h"
  32. #define WIDGET_CHIP_CTRL 0x15
  33. #define WIDGET_DSP_CTRL 0x16
  34. #define WUH_MEM_CONNID 10
  35. #define DSP_MEM_CONNID 16
  36. enum hda_cmd_vendor_io {
  37. /* for DspIO node */
  38. VENDOR_DSPIO_SCP_WRITE_DATA_LOW = 0x000,
  39. VENDOR_DSPIO_SCP_WRITE_DATA_HIGH = 0x100,
  40. VENDOR_DSPIO_STATUS = 0xF01,
  41. VENDOR_DSPIO_SCP_POST_READ_DATA = 0x702,
  42. VENDOR_DSPIO_SCP_READ_DATA = 0xF02,
  43. VENDOR_DSPIO_DSP_INIT = 0x703,
  44. VENDOR_DSPIO_SCP_POST_COUNT_QUERY = 0x704,
  45. VENDOR_DSPIO_SCP_READ_COUNT = 0xF04,
  46. /* for ChipIO node */
  47. VENDOR_CHIPIO_ADDRESS_LOW = 0x000,
  48. VENDOR_CHIPIO_ADDRESS_HIGH = 0x100,
  49. VENDOR_CHIPIO_STREAM_FORMAT = 0x200,
  50. VENDOR_CHIPIO_DATA_LOW = 0x300,
  51. VENDOR_CHIPIO_DATA_HIGH = 0x400,
  52. VENDOR_CHIPIO_GET_PARAMETER = 0xF00,
  53. VENDOR_CHIPIO_STATUS = 0xF01,
  54. VENDOR_CHIPIO_HIC_POST_READ = 0x702,
  55. VENDOR_CHIPIO_HIC_READ_DATA = 0xF03,
  56. VENDOR_CHIPIO_CT_EXTENSIONS_ENABLE = 0x70A,
  57. VENDOR_CHIPIO_PLL_PMU_WRITE = 0x70C,
  58. VENDOR_CHIPIO_PLL_PMU_READ = 0xF0C,
  59. VENDOR_CHIPIO_8051_ADDRESS_LOW = 0x70D,
  60. VENDOR_CHIPIO_8051_ADDRESS_HIGH = 0x70E,
  61. VENDOR_CHIPIO_FLAG_SET = 0x70F,
  62. VENDOR_CHIPIO_FLAGS_GET = 0xF0F,
  63. VENDOR_CHIPIO_PARAMETER_SET = 0x710,
  64. VENDOR_CHIPIO_PARAMETER_GET = 0xF10,
  65. VENDOR_CHIPIO_PORT_ALLOC_CONFIG_SET = 0x711,
  66. VENDOR_CHIPIO_PORT_ALLOC_SET = 0x712,
  67. VENDOR_CHIPIO_PORT_ALLOC_GET = 0xF12,
  68. VENDOR_CHIPIO_PORT_FREE_SET = 0x713,
  69. VENDOR_CHIPIO_PARAMETER_EX_ID_GET = 0xF17,
  70. VENDOR_CHIPIO_PARAMETER_EX_ID_SET = 0x717,
  71. VENDOR_CHIPIO_PARAMETER_EX_VALUE_GET = 0xF18,
  72. VENDOR_CHIPIO_PARAMETER_EX_VALUE_SET = 0x718
  73. };
  74. /*
  75. * Control flag IDs
  76. */
  77. enum control_flag_id {
  78. /* Connection manager stream setup is bypassed/enabled */
  79. CONTROL_FLAG_C_MGR = 0,
  80. /* DSP DMA is bypassed/enabled */
  81. CONTROL_FLAG_DMA = 1,
  82. /* 8051 'idle' mode is disabled/enabled */
  83. CONTROL_FLAG_IDLE_ENABLE = 2,
  84. /* Tracker for the SPDIF-in path is bypassed/enabled */
  85. CONTROL_FLAG_TRACKER = 3,
  86. /* DigitalOut to Spdif2Out connection is disabled/enabled */
  87. CONTROL_FLAG_SPDIF2OUT = 4,
  88. /* Digital Microphone is disabled/enabled */
  89. CONTROL_FLAG_DMIC = 5,
  90. /* ADC_B rate is 48 kHz/96 kHz */
  91. CONTROL_FLAG_ADC_B_96KHZ = 6,
  92. /* ADC_C rate is 48 kHz/96 kHz */
  93. CONTROL_FLAG_ADC_C_96KHZ = 7,
  94. /* DAC rate is 48 kHz/96 kHz (affects all DACs) */
  95. CONTROL_FLAG_DAC_96KHZ = 8,
  96. /* DSP rate is 48 kHz/96 kHz */
  97. CONTROL_FLAG_DSP_96KHZ = 9,
  98. /* SRC clock is 98 MHz/196 MHz (196 MHz forces rate to 96 KHz) */
  99. CONTROL_FLAG_SRC_CLOCK_196MHZ = 10,
  100. /* SRC rate is 48 kHz/96 kHz (48 kHz disabled when clock is 196 MHz) */
  101. CONTROL_FLAG_SRC_RATE_96KHZ = 11,
  102. /* Decode Loop (DSP->SRC->DSP) is disabled/enabled */
  103. CONTROL_FLAG_DECODE_LOOP = 12,
  104. /* De-emphasis filter on DAC-1 disabled/enabled */
  105. CONTROL_FLAG_DAC1_DEEMPHASIS = 13,
  106. /* De-emphasis filter on DAC-2 disabled/enabled */
  107. CONTROL_FLAG_DAC2_DEEMPHASIS = 14,
  108. /* De-emphasis filter on DAC-3 disabled/enabled */
  109. CONTROL_FLAG_DAC3_DEEMPHASIS = 15,
  110. /* High-pass filter on ADC_B disabled/enabled */
  111. CONTROL_FLAG_ADC_B_HIGH_PASS = 16,
  112. /* High-pass filter on ADC_C disabled/enabled */
  113. CONTROL_FLAG_ADC_C_HIGH_PASS = 17,
  114. /* Common mode on Port_A disabled/enabled */
  115. CONTROL_FLAG_PORT_A_COMMON_MODE = 18,
  116. /* Common mode on Port_D disabled/enabled */
  117. CONTROL_FLAG_PORT_D_COMMON_MODE = 19,
  118. /* Impedance for ramp generator on Port_A 16 Ohm/10K Ohm */
  119. CONTROL_FLAG_PORT_A_10KOHM_LOAD = 20,
  120. /* Impedance for ramp generator on Port_D, 16 Ohm/10K Ohm */
  121. CONTROL_FLAG_PORT_D_10K0HM_LOAD = 21,
  122. /* ASI rate is 48kHz/96kHz */
  123. CONTROL_FLAG_ASI_96KHZ = 22,
  124. /* DAC power settings able to control attached ports no/yes */
  125. CONTROL_FLAG_DACS_CONTROL_PORTS = 23,
  126. /* Clock Stop OK reporting is disabled/enabled */
  127. CONTROL_FLAG_CONTROL_STOP_OK_ENABLE = 24,
  128. /* Number of control flags */
  129. CONTROL_FLAGS_MAX = (CONTROL_FLAG_CONTROL_STOP_OK_ENABLE+1)
  130. };
  131. /*
  132. * Control parameter IDs
  133. */
  134. enum control_parameter_id {
  135. /* 0: force HDA, 1: allow DSP if HDA Spdif1Out stream is idle */
  136. CONTROL_PARAM_SPDIF1_SOURCE = 2,
  137. /* Stream Control */
  138. /* Select stream with the given ID */
  139. CONTROL_PARAM_STREAM_ID = 24,
  140. /* Source connection point for the selected stream */
  141. CONTROL_PARAM_STREAM_SOURCE_CONN_POINT = 25,
  142. /* Destination connection point for the selected stream */
  143. CONTROL_PARAM_STREAM_DEST_CONN_POINT = 26,
  144. /* Number of audio channels in the selected stream */
  145. CONTROL_PARAM_STREAMS_CHANNELS = 27,
  146. /*Enable control for the selected stream */
  147. CONTROL_PARAM_STREAM_CONTROL = 28,
  148. /* Connection Point Control */
  149. /* Select connection point with the given ID */
  150. CONTROL_PARAM_CONN_POINT_ID = 29,
  151. /* Connection point sample rate */
  152. CONTROL_PARAM_CONN_POINT_SAMPLE_RATE = 30,
  153. /* Node Control */
  154. /* Select HDA node with the given ID */
  155. CONTROL_PARAM_NODE_ID = 31
  156. };
  157. /*
  158. * Dsp Io Status codes
  159. */
  160. enum hda_vendor_status_dspio {
  161. /* Success */
  162. VENDOR_STATUS_DSPIO_OK = 0x00,
  163. /* Busy, unable to accept new command, the host must retry */
  164. VENDOR_STATUS_DSPIO_BUSY = 0x01,
  165. /* SCP command queue is full */
  166. VENDOR_STATUS_DSPIO_SCP_COMMAND_QUEUE_FULL = 0x02,
  167. /* SCP response queue is empty */
  168. VENDOR_STATUS_DSPIO_SCP_RESPONSE_QUEUE_EMPTY = 0x03
  169. };
  170. /*
  171. * Chip Io Status codes
  172. */
  173. enum hda_vendor_status_chipio {
  174. /* Success */
  175. VENDOR_STATUS_CHIPIO_OK = 0x00,
  176. /* Busy, unable to accept new command, the host must retry */
  177. VENDOR_STATUS_CHIPIO_BUSY = 0x01
  178. };
  179. /*
  180. * CA0132 sample rate
  181. */
  182. enum ca0132_sample_rate {
  183. SR_6_000 = 0x00,
  184. SR_8_000 = 0x01,
  185. SR_9_600 = 0x02,
  186. SR_11_025 = 0x03,
  187. SR_16_000 = 0x04,
  188. SR_22_050 = 0x05,
  189. SR_24_000 = 0x06,
  190. SR_32_000 = 0x07,
  191. SR_44_100 = 0x08,
  192. SR_48_000 = 0x09,
  193. SR_88_200 = 0x0A,
  194. SR_96_000 = 0x0B,
  195. SR_144_000 = 0x0C,
  196. SR_176_400 = 0x0D,
  197. SR_192_000 = 0x0E,
  198. SR_384_000 = 0x0F,
  199. SR_COUNT = 0x10,
  200. SR_RATE_UNKNOWN = 0x1F
  201. };
  202. /*
  203. * Scp Helper function
  204. */
  205. enum get_set {
  206. IS_SET = 0,
  207. IS_GET = 1,
  208. };
  209. /*
  210. * Duplicated from ca0110 codec
  211. */
  212. static void init_output(struct hda_codec *codec, hda_nid_t pin, hda_nid_t dac)
  213. {
  214. if (pin) {
  215. snd_hda_codec_write(codec, pin, 0,
  216. AC_VERB_SET_PIN_WIDGET_CONTROL, PIN_HP);
  217. if (get_wcaps(codec, pin) & AC_WCAP_OUT_AMP)
  218. snd_hda_codec_write(codec, pin, 0,
  219. AC_VERB_SET_AMP_GAIN_MUTE,
  220. AMP_OUT_UNMUTE);
  221. }
  222. if (dac)
  223. snd_hda_codec_write(codec, dac, 0,
  224. AC_VERB_SET_AMP_GAIN_MUTE, AMP_OUT_ZERO);
  225. }
  226. static void init_input(struct hda_codec *codec, hda_nid_t pin, hda_nid_t adc)
  227. {
  228. if (pin) {
  229. snd_hda_codec_write(codec, pin, 0,
  230. AC_VERB_SET_PIN_WIDGET_CONTROL,
  231. PIN_VREF80);
  232. if (get_wcaps(codec, pin) & AC_WCAP_IN_AMP)
  233. snd_hda_codec_write(codec, pin, 0,
  234. AC_VERB_SET_AMP_GAIN_MUTE,
  235. AMP_IN_UNMUTE(0));
  236. }
  237. if (adc)
  238. snd_hda_codec_write(codec, adc, 0, AC_VERB_SET_AMP_GAIN_MUTE,
  239. AMP_IN_UNMUTE(0));
  240. }
  241. static char *dirstr[2] = { "Playback", "Capture" };
  242. static int _add_switch(struct hda_codec *codec, hda_nid_t nid, const char *pfx,
  243. int chan, int dir)
  244. {
  245. char namestr[44];
  246. int type = dir ? HDA_INPUT : HDA_OUTPUT;
  247. struct snd_kcontrol_new knew =
  248. HDA_CODEC_MUTE_MONO(namestr, nid, chan, 0, type);
  249. sprintf(namestr, "%s %s Switch", pfx, dirstr[dir]);
  250. return snd_hda_ctl_add(codec, nid, snd_ctl_new1(&knew, codec));
  251. }
  252. static int _add_volume(struct hda_codec *codec, hda_nid_t nid, const char *pfx,
  253. int chan, int dir)
  254. {
  255. char namestr[44];
  256. int type = dir ? HDA_INPUT : HDA_OUTPUT;
  257. struct snd_kcontrol_new knew =
  258. HDA_CODEC_VOLUME_MONO(namestr, nid, chan, 0, type);
  259. sprintf(namestr, "%s %s Volume", pfx, dirstr[dir]);
  260. return snd_hda_ctl_add(codec, nid, snd_ctl_new1(&knew, codec));
  261. }
  262. #define add_out_switch(codec, nid, pfx) _add_switch(codec, nid, pfx, 3, 0)
  263. #define add_out_volume(codec, nid, pfx) _add_volume(codec, nid, pfx, 3, 0)
  264. #define add_in_switch(codec, nid, pfx) _add_switch(codec, nid, pfx, 3, 1)
  265. #define add_in_volume(codec, nid, pfx) _add_volume(codec, nid, pfx, 3, 1)
  266. #define add_mono_switch(codec, nid, pfx, chan) \
  267. _add_switch(codec, nid, pfx, chan, 0)
  268. #define add_mono_volume(codec, nid, pfx, chan) \
  269. _add_volume(codec, nid, pfx, chan, 0)
  270. #define add_in_mono_switch(codec, nid, pfx, chan) \
  271. _add_switch(codec, nid, pfx, chan, 1)
  272. #define add_in_mono_volume(codec, nid, pfx, chan) \
  273. _add_volume(codec, nid, pfx, chan, 1)
  274. /*
  275. * CA0132 specific
  276. */
  277. struct ca0132_spec {
  278. struct auto_pin_cfg autocfg;
  279. struct hda_multi_out multiout;
  280. hda_nid_t out_pins[AUTO_CFG_MAX_OUTS];
  281. hda_nid_t dacs[AUTO_CFG_MAX_OUTS];
  282. hda_nid_t hp_dac;
  283. hda_nid_t input_pins[AUTO_PIN_LAST];
  284. hda_nid_t adcs[AUTO_PIN_LAST];
  285. hda_nid_t dig_out;
  286. hda_nid_t dig_in;
  287. unsigned int num_inputs;
  288. long curr_hp_switch;
  289. long curr_hp_volume[2];
  290. long curr_speaker_switch;
  291. struct mutex chipio_mutex;
  292. const char *input_labels[AUTO_PIN_LAST];
  293. struct hda_pcm pcm_rec[2]; /* PCM information */
  294. };
  295. /* Chip access helper function */
  296. static int chipio_send(struct hda_codec *codec,
  297. unsigned int reg,
  298. unsigned int data)
  299. {
  300. unsigned int res;
  301. int retry = 50;
  302. /* send bits of data specified by reg */
  303. do {
  304. res = snd_hda_codec_read(codec, WIDGET_CHIP_CTRL, 0,
  305. reg, data);
  306. if (res == VENDOR_STATUS_CHIPIO_OK)
  307. return 0;
  308. } while (--retry);
  309. return -EIO;
  310. }
  311. /*
  312. * Write chip address through the vendor widget -- NOT protected by the Mutex!
  313. */
  314. static int chipio_write_address(struct hda_codec *codec,
  315. unsigned int chip_addx)
  316. {
  317. int res;
  318. /* send low 16 bits of the address */
  319. res = chipio_send(codec, VENDOR_CHIPIO_ADDRESS_LOW,
  320. chip_addx & 0xffff);
  321. if (res != -EIO) {
  322. /* send high 16 bits of the address */
  323. res = chipio_send(codec, VENDOR_CHIPIO_ADDRESS_HIGH,
  324. chip_addx >> 16);
  325. }
  326. return res;
  327. }
  328. /*
  329. * Write data through the vendor widget -- NOT protected by the Mutex!
  330. */
  331. static int chipio_write_data(struct hda_codec *codec, unsigned int data)
  332. {
  333. int res;
  334. /* send low 16 bits of the data */
  335. res = chipio_send(codec, VENDOR_CHIPIO_DATA_LOW, data & 0xffff);
  336. if (res != -EIO) {
  337. /* send high 16 bits of the data */
  338. res = chipio_send(codec, VENDOR_CHIPIO_DATA_HIGH,
  339. data >> 16);
  340. }
  341. return res;
  342. }
  343. /*
  344. * Read data through the vendor widget -- NOT protected by the Mutex!
  345. */
  346. static int chipio_read_data(struct hda_codec *codec, unsigned int *data)
  347. {
  348. int res;
  349. /* post read */
  350. res = chipio_send(codec, VENDOR_CHIPIO_HIC_POST_READ, 0);
  351. if (res != -EIO) {
  352. /* read status */
  353. res = chipio_send(codec, VENDOR_CHIPIO_STATUS, 0);
  354. }
  355. if (res != -EIO) {
  356. /* read data */
  357. *data = snd_hda_codec_read(codec, WIDGET_CHIP_CTRL, 0,
  358. VENDOR_CHIPIO_HIC_READ_DATA,
  359. 0);
  360. }
  361. return res;
  362. }
  363. /*
  364. * Write given value to the given address through the chip I/O widget.
  365. * protected by the Mutex
  366. */
  367. static int chipio_write(struct hda_codec *codec,
  368. unsigned int chip_addx, const unsigned int data)
  369. {
  370. struct ca0132_spec *spec = codec->spec;
  371. int err;
  372. mutex_lock(&spec->chipio_mutex);
  373. /* write the address, and if successful proceed to write data */
  374. err = chipio_write_address(codec, chip_addx);
  375. if (err < 0)
  376. goto exit;
  377. err = chipio_write_data(codec, data);
  378. if (err < 0)
  379. goto exit;
  380. exit:
  381. mutex_unlock(&spec->chipio_mutex);
  382. return err;
  383. }
  384. /*
  385. * Read the given address through the chip I/O widget
  386. * protected by the Mutex
  387. */
  388. static int chipio_read(struct hda_codec *codec,
  389. unsigned int chip_addx, unsigned int *data)
  390. {
  391. struct ca0132_spec *spec = codec->spec;
  392. int err;
  393. mutex_lock(&spec->chipio_mutex);
  394. /* write the address, and if successful proceed to write data */
  395. err = chipio_write_address(codec, chip_addx);
  396. if (err < 0)
  397. goto exit;
  398. err = chipio_read_data(codec, data);
  399. if (err < 0)
  400. goto exit;
  401. exit:
  402. mutex_unlock(&spec->chipio_mutex);
  403. return err;
  404. }
  405. /*
  406. * PCM stuffs
  407. */
  408. static void ca0132_setup_stream(struct hda_codec *codec, hda_nid_t nid,
  409. u32 stream_tag,
  410. int channel_id, int format)
  411. {
  412. unsigned int oldval, newval;
  413. if (!nid)
  414. return;
  415. snd_printdd("ca0132_setup_stream: "
  416. "NID=0x%x, stream=0x%x, channel=%d, format=0x%x\n",
  417. nid, stream_tag, channel_id, format);
  418. /* update the format-id if changed */
  419. oldval = snd_hda_codec_read(codec, nid, 0,
  420. AC_VERB_GET_STREAM_FORMAT,
  421. 0);
  422. if (oldval != format) {
  423. msleep(20);
  424. snd_hda_codec_write(codec, nid, 0,
  425. AC_VERB_SET_STREAM_FORMAT,
  426. format);
  427. }
  428. oldval = snd_hda_codec_read(codec, nid, 0, AC_VERB_GET_CONV, 0);
  429. newval = (stream_tag << 4) | channel_id;
  430. if (oldval != newval) {
  431. snd_hda_codec_write(codec, nid, 0,
  432. AC_VERB_SET_CHANNEL_STREAMID,
  433. newval);
  434. }
  435. }
  436. static void ca0132_cleanup_stream(struct hda_codec *codec, hda_nid_t nid)
  437. {
  438. snd_hda_codec_write(codec, nid, 0, AC_VERB_SET_STREAM_FORMAT, 0);
  439. snd_hda_codec_write(codec, nid, 0, AC_VERB_SET_CHANNEL_STREAMID, 0);
  440. }
  441. /*
  442. * PCM callbacks
  443. */
  444. static int ca0132_playback_pcm_prepare(struct hda_pcm_stream *hinfo,
  445. struct hda_codec *codec,
  446. unsigned int stream_tag,
  447. unsigned int format,
  448. struct snd_pcm_substream *substream)
  449. {
  450. struct ca0132_spec *spec = codec->spec;
  451. ca0132_setup_stream(codec, spec->dacs[0], stream_tag, 0, format);
  452. return 0;
  453. }
  454. static int ca0132_playback_pcm_cleanup(struct hda_pcm_stream *hinfo,
  455. struct hda_codec *codec,
  456. struct snd_pcm_substream *substream)
  457. {
  458. struct ca0132_spec *spec = codec->spec;
  459. ca0132_cleanup_stream(codec, spec->dacs[0]);
  460. return 0;
  461. }
  462. /*
  463. * Digital out
  464. */
  465. static int ca0132_dig_playback_pcm_prepare(struct hda_pcm_stream *hinfo,
  466. struct hda_codec *codec,
  467. unsigned int stream_tag,
  468. unsigned int format,
  469. struct snd_pcm_substream *substream)
  470. {
  471. struct ca0132_spec *spec = codec->spec;
  472. ca0132_setup_stream(codec, spec->dig_out, stream_tag, 0, format);
  473. return 0;
  474. }
  475. static int ca0132_dig_playback_pcm_cleanup(struct hda_pcm_stream *hinfo,
  476. struct hda_codec *codec,
  477. struct snd_pcm_substream *substream)
  478. {
  479. struct ca0132_spec *spec = codec->spec;
  480. ca0132_cleanup_stream(codec, spec->dig_out);
  481. return 0;
  482. }
  483. /*
  484. * Analog capture
  485. */
  486. static int ca0132_capture_pcm_prepare(struct hda_pcm_stream *hinfo,
  487. struct hda_codec *codec,
  488. unsigned int stream_tag,
  489. unsigned int format,
  490. struct snd_pcm_substream *substream)
  491. {
  492. struct ca0132_spec *spec = codec->spec;
  493. ca0132_setup_stream(codec, spec->adcs[substream->number],
  494. stream_tag, 0, format);
  495. return 0;
  496. }
  497. static int ca0132_capture_pcm_cleanup(struct hda_pcm_stream *hinfo,
  498. struct hda_codec *codec,
  499. struct snd_pcm_substream *substream)
  500. {
  501. struct ca0132_spec *spec = codec->spec;
  502. ca0132_cleanup_stream(codec, spec->adcs[substream->number]);
  503. return 0;
  504. }
  505. /*
  506. * Digital capture
  507. */
  508. static int ca0132_dig_capture_pcm_prepare(struct hda_pcm_stream *hinfo,
  509. struct hda_codec *codec,
  510. unsigned int stream_tag,
  511. unsigned int format,
  512. struct snd_pcm_substream *substream)
  513. {
  514. struct ca0132_spec *spec = codec->spec;
  515. ca0132_setup_stream(codec, spec->dig_in, stream_tag, 0, format);
  516. return 0;
  517. }
  518. static int ca0132_dig_capture_pcm_cleanup(struct hda_pcm_stream *hinfo,
  519. struct hda_codec *codec,
  520. struct snd_pcm_substream *substream)
  521. {
  522. struct ca0132_spec *spec = codec->spec;
  523. ca0132_cleanup_stream(codec, spec->dig_in);
  524. return 0;
  525. }
  526. /*
  527. */
  528. static struct hda_pcm_stream ca0132_pcm_analog_playback = {
  529. .substreams = 1,
  530. .channels_min = 2,
  531. .channels_max = 2,
  532. .ops = {
  533. .prepare = ca0132_playback_pcm_prepare,
  534. .cleanup = ca0132_playback_pcm_cleanup
  535. },
  536. };
  537. static struct hda_pcm_stream ca0132_pcm_analog_capture = {
  538. .substreams = 1,
  539. .channels_min = 2,
  540. .channels_max = 2,
  541. .ops = {
  542. .prepare = ca0132_capture_pcm_prepare,
  543. .cleanup = ca0132_capture_pcm_cleanup
  544. },
  545. };
  546. static struct hda_pcm_stream ca0132_pcm_digital_playback = {
  547. .substreams = 1,
  548. .channels_min = 2,
  549. .channels_max = 2,
  550. .ops = {
  551. .prepare = ca0132_dig_playback_pcm_prepare,
  552. .cleanup = ca0132_dig_playback_pcm_cleanup
  553. },
  554. };
  555. static struct hda_pcm_stream ca0132_pcm_digital_capture = {
  556. .substreams = 1,
  557. .channels_min = 2,
  558. .channels_max = 2,
  559. .ops = {
  560. .prepare = ca0132_dig_capture_pcm_prepare,
  561. .cleanup = ca0132_dig_capture_pcm_cleanup
  562. },
  563. };
  564. static int ca0132_build_pcms(struct hda_codec *codec)
  565. {
  566. struct ca0132_spec *spec = codec->spec;
  567. struct hda_pcm *info = spec->pcm_rec;
  568. codec->pcm_info = info;
  569. codec->num_pcms = 0;
  570. info->name = "CA0132 Analog";
  571. info->stream[SNDRV_PCM_STREAM_PLAYBACK] = ca0132_pcm_analog_playback;
  572. info->stream[SNDRV_PCM_STREAM_PLAYBACK].nid = spec->dacs[0];
  573. info->stream[SNDRV_PCM_STREAM_PLAYBACK].channels_max =
  574. spec->multiout.max_channels;
  575. info->stream[SNDRV_PCM_STREAM_CAPTURE] = ca0132_pcm_analog_capture;
  576. info->stream[SNDRV_PCM_STREAM_CAPTURE].substreams = spec->num_inputs;
  577. info->stream[SNDRV_PCM_STREAM_CAPTURE].nid = spec->adcs[0];
  578. codec->num_pcms++;
  579. if (!spec->dig_out && !spec->dig_in)
  580. return 0;
  581. info++;
  582. info->name = "CA0132 Digital";
  583. info->pcm_type = HDA_PCM_TYPE_SPDIF;
  584. if (spec->dig_out) {
  585. info->stream[SNDRV_PCM_STREAM_PLAYBACK] =
  586. ca0132_pcm_digital_playback;
  587. info->stream[SNDRV_PCM_STREAM_PLAYBACK].nid = spec->dig_out;
  588. }
  589. if (spec->dig_in) {
  590. info->stream[SNDRV_PCM_STREAM_CAPTURE] =
  591. ca0132_pcm_digital_capture;
  592. info->stream[SNDRV_PCM_STREAM_CAPTURE].nid = spec->dig_in;
  593. }
  594. codec->num_pcms++;
  595. return 0;
  596. }
  597. #define REG_CODEC_MUTE 0x18b014
  598. #define REG_CODEC_HP_VOL_L 0x18b070
  599. #define REG_CODEC_HP_VOL_R 0x18b074
  600. static int ca0132_hp_switch_get(struct snd_kcontrol *kcontrol,
  601. struct snd_ctl_elem_value *ucontrol)
  602. {
  603. struct hda_codec *codec = snd_kcontrol_chip(kcontrol);
  604. struct ca0132_spec *spec = codec->spec;
  605. long *valp = ucontrol->value.integer.value;
  606. *valp = spec->curr_hp_switch;
  607. return 0;
  608. }
  609. static int ca0132_hp_switch_put(struct snd_kcontrol *kcontrol,
  610. struct snd_ctl_elem_value *ucontrol)
  611. {
  612. struct hda_codec *codec = snd_kcontrol_chip(kcontrol);
  613. struct ca0132_spec *spec = codec->spec;
  614. long *valp = ucontrol->value.integer.value;
  615. unsigned int data;
  616. int err;
  617. /* any change? */
  618. if (spec->curr_hp_switch == *valp)
  619. return 0;
  620. snd_hda_power_up(codec);
  621. err = chipio_read(codec, REG_CODEC_MUTE, &data);
  622. if (err < 0)
  623. return err;
  624. /* *valp 0 is mute, 1 is unmute */
  625. data = (data & 0x7f) | (*valp ? 0 : 0x80);
  626. chipio_write(codec, REG_CODEC_MUTE, data);
  627. if (err < 0)
  628. return err;
  629. spec->curr_hp_switch = *valp;
  630. snd_hda_power_down(codec);
  631. return 1;
  632. }
  633. static int ca0132_speaker_switch_get(struct snd_kcontrol *kcontrol,
  634. struct snd_ctl_elem_value *ucontrol)
  635. {
  636. struct hda_codec *codec = snd_kcontrol_chip(kcontrol);
  637. struct ca0132_spec *spec = codec->spec;
  638. long *valp = ucontrol->value.integer.value;
  639. *valp = spec->curr_speaker_switch;
  640. return 0;
  641. }
  642. static int ca0132_speaker_switch_put(struct snd_kcontrol *kcontrol,
  643. struct snd_ctl_elem_value *ucontrol)
  644. {
  645. struct hda_codec *codec = snd_kcontrol_chip(kcontrol);
  646. struct ca0132_spec *spec = codec->spec;
  647. long *valp = ucontrol->value.integer.value;
  648. unsigned int data;
  649. int err;
  650. /* any change? */
  651. if (spec->curr_speaker_switch == *valp)
  652. return 0;
  653. snd_hda_power_up(codec);
  654. err = chipio_read(codec, REG_CODEC_MUTE, &data);
  655. if (err < 0)
  656. return err;
  657. /* *valp 0 is mute, 1 is unmute */
  658. data = (data & 0xef) | (*valp ? 0 : 0x10);
  659. chipio_write(codec, REG_CODEC_MUTE, data);
  660. if (err < 0)
  661. return err;
  662. spec->curr_speaker_switch = *valp;
  663. snd_hda_power_down(codec);
  664. return 1;
  665. }
  666. static int ca0132_hp_volume_get(struct snd_kcontrol *kcontrol,
  667. struct snd_ctl_elem_value *ucontrol)
  668. {
  669. struct hda_codec *codec = snd_kcontrol_chip(kcontrol);
  670. struct ca0132_spec *spec = codec->spec;
  671. long *valp = ucontrol->value.integer.value;
  672. *valp++ = spec->curr_hp_volume[0];
  673. *valp = spec->curr_hp_volume[1];
  674. return 0;
  675. }
  676. static int ca0132_hp_volume_put(struct snd_kcontrol *kcontrol,
  677. struct snd_ctl_elem_value *ucontrol)
  678. {
  679. struct hda_codec *codec = snd_kcontrol_chip(kcontrol);
  680. struct ca0132_spec *spec = codec->spec;
  681. long *valp = ucontrol->value.integer.value;
  682. long left_vol, right_vol;
  683. unsigned int data;
  684. int val;
  685. int err;
  686. left_vol = *valp++;
  687. right_vol = *valp;
  688. /* any change? */
  689. if ((spec->curr_hp_volume[0] == left_vol) &&
  690. (spec->curr_hp_volume[1] == right_vol))
  691. return 0;
  692. snd_hda_power_up(codec);
  693. err = chipio_read(codec, REG_CODEC_HP_VOL_L, &data);
  694. if (err < 0)
  695. return err;
  696. val = 31 - left_vol;
  697. data = (data & 0xe0) | val;
  698. chipio_write(codec, REG_CODEC_HP_VOL_L, data);
  699. if (err < 0)
  700. return err;
  701. val = 31 - right_vol;
  702. data = (data & 0xe0) | val;
  703. chipio_write(codec, REG_CODEC_HP_VOL_R, data);
  704. if (err < 0)
  705. return err;
  706. spec->curr_hp_volume[0] = left_vol;
  707. spec->curr_hp_volume[1] = right_vol;
  708. snd_hda_power_down(codec);
  709. return 1;
  710. }
  711. static int add_hp_switch(struct hda_codec *codec, hda_nid_t nid)
  712. {
  713. struct snd_kcontrol_new knew =
  714. HDA_CODEC_MUTE_MONO("Headphone Playback Switch",
  715. nid, 1, 0, HDA_OUTPUT);
  716. knew.get = ca0132_hp_switch_get;
  717. knew.put = ca0132_hp_switch_put;
  718. return snd_hda_ctl_add(codec, nid, snd_ctl_new1(&knew, codec));
  719. }
  720. static int add_hp_volume(struct hda_codec *codec, hda_nid_t nid)
  721. {
  722. struct snd_kcontrol_new knew =
  723. HDA_CODEC_VOLUME_MONO("Headphone Playback Volume",
  724. nid, 3, 0, HDA_OUTPUT);
  725. knew.get = ca0132_hp_volume_get;
  726. knew.put = ca0132_hp_volume_put;
  727. return snd_hda_ctl_add(codec, nid, snd_ctl_new1(&knew, codec));
  728. }
  729. static int add_speaker_switch(struct hda_codec *codec, hda_nid_t nid)
  730. {
  731. struct snd_kcontrol_new knew =
  732. HDA_CODEC_MUTE_MONO("Speaker Playback Switch",
  733. nid, 1, 0, HDA_OUTPUT);
  734. knew.get = ca0132_speaker_switch_get;
  735. knew.put = ca0132_speaker_switch_put;
  736. return snd_hda_ctl_add(codec, nid, snd_ctl_new1(&knew, codec));
  737. }
  738. static void ca0132_fix_hp_caps(struct hda_codec *codec)
  739. {
  740. struct ca0132_spec *spec = codec->spec;
  741. struct auto_pin_cfg *cfg = &spec->autocfg;
  742. unsigned int caps;
  743. /* set mute-capable, 1db step, 32 steps, ofs 6 */
  744. caps = 0x80031f06;
  745. snd_hda_override_amp_caps(codec, cfg->hp_pins[0], HDA_OUTPUT, caps);
  746. }
  747. static int ca0132_build_controls(struct hda_codec *codec)
  748. {
  749. struct ca0132_spec *spec = codec->spec;
  750. struct auto_pin_cfg *cfg = &spec->autocfg;
  751. int i, err;
  752. if (spec->multiout.num_dacs) {
  753. err = add_speaker_switch(codec, spec->out_pins[0]);
  754. if (err < 0)
  755. return err;
  756. }
  757. if (cfg->hp_outs) {
  758. ca0132_fix_hp_caps(codec);
  759. err = add_hp_switch(codec, cfg->hp_pins[0]);
  760. if (err < 0)
  761. return err;
  762. err = add_hp_volume(codec, cfg->hp_pins[0]);
  763. if (err < 0)
  764. return err;
  765. }
  766. for (i = 0; i < spec->num_inputs; i++) {
  767. const char *label = spec->input_labels[i];
  768. err = add_in_switch(codec, spec->adcs[i], label);
  769. if (err < 0)
  770. return err;
  771. err = add_in_volume(codec, spec->adcs[i], label);
  772. if (err < 0)
  773. return err;
  774. if (cfg->inputs[i].type == AUTO_PIN_MIC) {
  775. /* add Mic-Boost */
  776. err = add_in_mono_volume(codec, spec->input_pins[i],
  777. "Mic Boost", 1);
  778. if (err < 0)
  779. return err;
  780. }
  781. }
  782. if (spec->dig_out) {
  783. err = snd_hda_create_spdif_out_ctls(codec, spec->dig_out,
  784. spec->dig_out);
  785. if (err < 0)
  786. return err;
  787. err = add_out_volume(codec, spec->dig_out, "IEC958");
  788. if (err < 0)
  789. return err;
  790. }
  791. if (spec->dig_in) {
  792. err = snd_hda_create_spdif_in_ctls(codec, spec->dig_in);
  793. if (err < 0)
  794. return err;
  795. err = add_in_volume(codec, spec->dig_in, "IEC958");
  796. }
  797. return 0;
  798. }
  799. static void ca0132_set_ct_ext(struct hda_codec *codec, int enable)
  800. {
  801. /* Set Creative extension */
  802. snd_printdd("SET CREATIVE EXTENSION\n");
  803. snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0,
  804. VENDOR_CHIPIO_CT_EXTENSIONS_ENABLE,
  805. enable);
  806. msleep(20);
  807. }
  808. static void ca0132_config(struct hda_codec *codec)
  809. {
  810. struct ca0132_spec *spec = codec->spec;
  811. struct auto_pin_cfg *cfg = &spec->autocfg;
  812. /* line-outs */
  813. cfg->line_outs = 1;
  814. cfg->line_out_pins[0] = 0x0b; /* front */
  815. cfg->line_out_type = AUTO_PIN_LINE_OUT;
  816. spec->dacs[0] = 0x02;
  817. spec->out_pins[0] = 0x0b;
  818. spec->multiout.dac_nids = spec->dacs;
  819. spec->multiout.num_dacs = 1;
  820. spec->multiout.max_channels = 2;
  821. /* headphone */
  822. cfg->hp_outs = 1;
  823. cfg->hp_pins[0] = 0x0f;
  824. spec->hp_dac = 0;
  825. spec->multiout.hp_nid = 0;
  826. /* inputs */
  827. cfg->num_inputs = 2; /* Mic-in and line-in */
  828. cfg->inputs[0].pin = 0x12;
  829. cfg->inputs[0].type = AUTO_PIN_MIC;
  830. cfg->inputs[1].pin = 0x11;
  831. cfg->inputs[1].type = AUTO_PIN_LINE_IN;
  832. /* Mic-in */
  833. spec->input_pins[0] = 0x12;
  834. spec->input_labels[0] = "Mic-In";
  835. spec->adcs[0] = 0x07;
  836. /* Line-In */
  837. spec->input_pins[1] = 0x11;
  838. spec->input_labels[1] = "Line-In";
  839. spec->adcs[1] = 0x08;
  840. spec->num_inputs = 2;
  841. }
  842. static void ca0132_init_chip(struct hda_codec *codec)
  843. {
  844. struct ca0132_spec *spec = codec->spec;
  845. mutex_init(&spec->chipio_mutex);
  846. }
  847. static void ca0132_exit_chip(struct hda_codec *codec)
  848. {
  849. /* put any chip cleanup stuffs here. */
  850. }
  851. static int ca0132_init(struct hda_codec *codec)
  852. {
  853. struct ca0132_spec *spec = codec->spec;
  854. struct auto_pin_cfg *cfg = &spec->autocfg;
  855. int i;
  856. for (i = 0; i < spec->multiout.num_dacs; i++) {
  857. init_output(codec, spec->out_pins[i],
  858. spec->multiout.dac_nids[i]);
  859. }
  860. init_output(codec, cfg->hp_pins[0], spec->hp_dac);
  861. init_output(codec, cfg->dig_out_pins[0], spec->dig_out);
  862. for (i = 0; i < spec->num_inputs; i++)
  863. init_input(codec, spec->input_pins[i], spec->adcs[i]);
  864. init_input(codec, cfg->dig_in_pin, spec->dig_in);
  865. ca0132_set_ct_ext(codec, 1);
  866. return 0;
  867. }
  868. static void ca0132_free(struct hda_codec *codec)
  869. {
  870. ca0132_set_ct_ext(codec, 0);
  871. ca0132_exit_chip(codec);
  872. kfree(codec->spec);
  873. }
  874. static struct hda_codec_ops ca0132_patch_ops = {
  875. .build_controls = ca0132_build_controls,
  876. .build_pcms = ca0132_build_pcms,
  877. .init = ca0132_init,
  878. .free = ca0132_free,
  879. };
  880. static int patch_ca0132(struct hda_codec *codec)
  881. {
  882. struct ca0132_spec *spec;
  883. snd_printdd("patch_ca0132\n");
  884. spec = kzalloc(sizeof(*spec), GFP_KERNEL);
  885. if (!spec)
  886. return -ENOMEM;
  887. codec->spec = spec;
  888. ca0132_init_chip(codec);
  889. ca0132_config(codec);
  890. codec->patch_ops = ca0132_patch_ops;
  891. return 0;
  892. }
  893. /*
  894. * patch entries
  895. */
  896. static struct hda_codec_preset snd_hda_preset_ca0132[] = {
  897. { .id = 0x11020011, .name = "CA0132", .patch = patch_ca0132 },
  898. {} /* terminator */
  899. };
  900. MODULE_ALIAS("snd-hda-codec-id:11020011");
  901. MODULE_LICENSE("GPL");
  902. MODULE_DESCRIPTION("Creative CA0132, CA0132 HD-audio codec");
  903. static struct hda_codec_preset_list ca0132_list = {
  904. .preset = snd_hda_preset_ca0132,
  905. .owner = THIS_MODULE,
  906. };
  907. static int __init patch_ca0132_init(void)
  908. {
  909. return snd_hda_add_codec_preset(&ca0132_list);
  910. }
  911. static void __exit patch_ca0132_exit(void)
  912. {
  913. snd_hda_delete_codec_preset(&ca0132_list);
  914. }
  915. module_init(patch_ca0132_init)
  916. module_exit(patch_ca0132_exit)