qla_init.c 146 KB

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  1. /*
  2. * QLogic Fibre Channel HBA Driver
  3. * Copyright (c) 2003-2011 QLogic Corporation
  4. *
  5. * See LICENSE.qla2xxx for copyright and licensing details.
  6. */
  7. #include "qla_def.h"
  8. #include "qla_gbl.h"
  9. #include <linux/delay.h>
  10. #include <linux/slab.h>
  11. #include <linux/vmalloc.h>
  12. #include "qla_devtbl.h"
  13. #ifdef CONFIG_SPARC
  14. #include <asm/prom.h>
  15. #endif
  16. /*
  17. * QLogic ISP2x00 Hardware Support Function Prototypes.
  18. */
  19. static int qla2x00_isp_firmware(scsi_qla_host_t *);
  20. static int qla2x00_setup_chip(scsi_qla_host_t *);
  21. static int qla2x00_init_rings(scsi_qla_host_t *);
  22. static int qla2x00_fw_ready(scsi_qla_host_t *);
  23. static int qla2x00_configure_hba(scsi_qla_host_t *);
  24. static int qla2x00_configure_loop(scsi_qla_host_t *);
  25. static int qla2x00_configure_local_loop(scsi_qla_host_t *);
  26. static int qla2x00_configure_fabric(scsi_qla_host_t *);
  27. static int qla2x00_find_all_fabric_devs(scsi_qla_host_t *, struct list_head *);
  28. static int qla2x00_device_resync(scsi_qla_host_t *);
  29. static int qla2x00_fabric_dev_login(scsi_qla_host_t *, fc_port_t *,
  30. uint16_t *);
  31. static int qla2x00_restart_isp(scsi_qla_host_t *);
  32. static struct qla_chip_state_84xx *qla84xx_get_chip(struct scsi_qla_host *);
  33. static int qla84xx_init_chip(scsi_qla_host_t *);
  34. static int qla25xx_init_queues(struct qla_hw_data *);
  35. /* SRB Extensions ---------------------------------------------------------- */
  36. static void
  37. qla2x00_ctx_sp_timeout(unsigned long __data)
  38. {
  39. srb_t *sp = (srb_t *)__data;
  40. struct srb_ctx *ctx;
  41. struct srb_iocb *iocb;
  42. fc_port_t *fcport = sp->fcport;
  43. struct qla_hw_data *ha = fcport->vha->hw;
  44. struct req_que *req;
  45. unsigned long flags;
  46. spin_lock_irqsave(&ha->hardware_lock, flags);
  47. req = ha->req_q_map[0];
  48. req->outstanding_cmds[sp->handle] = NULL;
  49. ctx = sp->ctx;
  50. iocb = ctx->u.iocb_cmd;
  51. iocb->timeout(sp);
  52. iocb->free(sp);
  53. spin_unlock_irqrestore(&ha->hardware_lock, flags);
  54. }
  55. static void
  56. qla2x00_ctx_sp_free(srb_t *sp)
  57. {
  58. struct srb_ctx *ctx = sp->ctx;
  59. struct srb_iocb *iocb = ctx->u.iocb_cmd;
  60. struct scsi_qla_host *vha = sp->fcport->vha;
  61. del_timer(&iocb->timer);
  62. kfree(iocb);
  63. kfree(ctx);
  64. mempool_free(sp, sp->fcport->vha->hw->srb_mempool);
  65. QLA_VHA_MARK_NOT_BUSY(vha);
  66. }
  67. inline srb_t *
  68. qla2x00_get_ctx_sp(scsi_qla_host_t *vha, fc_port_t *fcport, size_t size,
  69. unsigned long tmo)
  70. {
  71. srb_t *sp = NULL;
  72. struct qla_hw_data *ha = vha->hw;
  73. struct srb_ctx *ctx;
  74. struct srb_iocb *iocb;
  75. uint8_t bail;
  76. QLA_VHA_MARK_BUSY(vha, bail);
  77. if (bail)
  78. return NULL;
  79. sp = mempool_alloc(ha->srb_mempool, GFP_KERNEL);
  80. if (!sp)
  81. goto done;
  82. ctx = kzalloc(size, GFP_KERNEL);
  83. if (!ctx) {
  84. mempool_free(sp, ha->srb_mempool);
  85. sp = NULL;
  86. goto done;
  87. }
  88. iocb = kzalloc(sizeof(struct srb_iocb), GFP_KERNEL);
  89. if (!iocb) {
  90. mempool_free(sp, ha->srb_mempool);
  91. sp = NULL;
  92. kfree(ctx);
  93. goto done;
  94. }
  95. memset(sp, 0, sizeof(*sp));
  96. sp->fcport = fcport;
  97. sp->ctx = ctx;
  98. ctx->u.iocb_cmd = iocb;
  99. iocb->free = qla2x00_ctx_sp_free;
  100. init_timer(&iocb->timer);
  101. if (!tmo)
  102. goto done;
  103. iocb->timer.expires = jiffies + tmo * HZ;
  104. iocb->timer.data = (unsigned long)sp;
  105. iocb->timer.function = qla2x00_ctx_sp_timeout;
  106. add_timer(&iocb->timer);
  107. done:
  108. if (!sp)
  109. QLA_VHA_MARK_NOT_BUSY(vha);
  110. return sp;
  111. }
  112. /* Asynchronous Login/Logout Routines -------------------------------------- */
  113. static inline unsigned long
  114. qla2x00_get_async_timeout(struct scsi_qla_host *vha)
  115. {
  116. unsigned long tmo;
  117. struct qla_hw_data *ha = vha->hw;
  118. /* Firmware should use switch negotiated r_a_tov for timeout. */
  119. tmo = ha->r_a_tov / 10 * 2;
  120. if (!IS_FWI2_CAPABLE(ha)) {
  121. /*
  122. * Except for earlier ISPs where the timeout is seeded from the
  123. * initialization control block.
  124. */
  125. tmo = ha->login_timeout;
  126. }
  127. return tmo;
  128. }
  129. static void
  130. qla2x00_async_iocb_timeout(srb_t *sp)
  131. {
  132. fc_port_t *fcport = sp->fcport;
  133. struct srb_ctx *ctx = sp->ctx;
  134. ql_dbg(ql_dbg_disc, fcport->vha, 0x2071,
  135. "Async-%s timeout - portid=%02x%02x%02x.\n",
  136. ctx->name, fcport->d_id.b.domain, fcport->d_id.b.area,
  137. fcport->d_id.b.al_pa);
  138. fcport->flags &= ~FCF_ASYNC_SENT;
  139. if (ctx->type == SRB_LOGIN_CMD) {
  140. struct srb_iocb *lio = ctx->u.iocb_cmd;
  141. qla2x00_post_async_logout_work(fcport->vha, fcport, NULL);
  142. /* Retry as needed. */
  143. lio->u.logio.data[0] = MBS_COMMAND_ERROR;
  144. lio->u.logio.data[1] = lio->u.logio.flags & SRB_LOGIN_RETRIED ?
  145. QLA_LOGIO_LOGIN_RETRIED : 0;
  146. qla2x00_post_async_login_done_work(fcport->vha, fcport,
  147. lio->u.logio.data);
  148. }
  149. }
  150. static void
  151. qla2x00_async_login_ctx_done(srb_t *sp)
  152. {
  153. struct srb_ctx *ctx = sp->ctx;
  154. struct srb_iocb *lio = ctx->u.iocb_cmd;
  155. qla2x00_post_async_login_done_work(sp->fcport->vha, sp->fcport,
  156. lio->u.logio.data);
  157. lio->free(sp);
  158. }
  159. int
  160. qla2x00_async_login(struct scsi_qla_host *vha, fc_port_t *fcport,
  161. uint16_t *data)
  162. {
  163. srb_t *sp;
  164. struct srb_ctx *ctx;
  165. struct srb_iocb *lio;
  166. int rval;
  167. rval = QLA_FUNCTION_FAILED;
  168. sp = qla2x00_get_ctx_sp(vha, fcport, sizeof(struct srb_ctx),
  169. qla2x00_get_async_timeout(vha) + 2);
  170. if (!sp)
  171. goto done;
  172. ctx = sp->ctx;
  173. ctx->type = SRB_LOGIN_CMD;
  174. ctx->name = "login";
  175. lio = ctx->u.iocb_cmd;
  176. lio->timeout = qla2x00_async_iocb_timeout;
  177. lio->done = qla2x00_async_login_ctx_done;
  178. lio->u.logio.flags |= SRB_LOGIN_COND_PLOGI;
  179. if (data[1] & QLA_LOGIO_LOGIN_RETRIED)
  180. lio->u.logio.flags |= SRB_LOGIN_RETRIED;
  181. rval = qla2x00_start_sp(sp);
  182. if (rval != QLA_SUCCESS)
  183. goto done_free_sp;
  184. ql_dbg(ql_dbg_disc, vha, 0x2072,
  185. "Async-login - loopid=%x portid=%02x%02x%02x retries=%d.\n",
  186. fcport->loop_id, fcport->d_id.b.domain, fcport->d_id.b.area,
  187. fcport->d_id.b.al_pa, fcport->login_retry);
  188. return rval;
  189. done_free_sp:
  190. lio->free(sp);
  191. done:
  192. return rval;
  193. }
  194. static void
  195. qla2x00_async_logout_ctx_done(srb_t *sp)
  196. {
  197. struct srb_ctx *ctx = sp->ctx;
  198. struct srb_iocb *lio = ctx->u.iocb_cmd;
  199. qla2x00_post_async_logout_done_work(sp->fcport->vha, sp->fcport,
  200. lio->u.logio.data);
  201. lio->free(sp);
  202. }
  203. int
  204. qla2x00_async_logout(struct scsi_qla_host *vha, fc_port_t *fcport)
  205. {
  206. srb_t *sp;
  207. struct srb_ctx *ctx;
  208. struct srb_iocb *lio;
  209. int rval;
  210. rval = QLA_FUNCTION_FAILED;
  211. sp = qla2x00_get_ctx_sp(vha, fcport, sizeof(struct srb_ctx),
  212. qla2x00_get_async_timeout(vha) + 2);
  213. if (!sp)
  214. goto done;
  215. ctx = sp->ctx;
  216. ctx->type = SRB_LOGOUT_CMD;
  217. ctx->name = "logout";
  218. lio = ctx->u.iocb_cmd;
  219. lio->timeout = qla2x00_async_iocb_timeout;
  220. lio->done = qla2x00_async_logout_ctx_done;
  221. rval = qla2x00_start_sp(sp);
  222. if (rval != QLA_SUCCESS)
  223. goto done_free_sp;
  224. ql_dbg(ql_dbg_disc, vha, 0x2070,
  225. "Async-logout - loop-id=%x portid=%02x%02x%02x.\n",
  226. fcport->loop_id, fcport->d_id.b.domain, fcport->d_id.b.area,
  227. fcport->d_id.b.al_pa);
  228. return rval;
  229. done_free_sp:
  230. lio->free(sp);
  231. done:
  232. return rval;
  233. }
  234. static void
  235. qla2x00_async_adisc_ctx_done(srb_t *sp)
  236. {
  237. struct srb_ctx *ctx = sp->ctx;
  238. struct srb_iocb *lio = ctx->u.iocb_cmd;
  239. qla2x00_post_async_adisc_done_work(sp->fcport->vha, sp->fcport,
  240. lio->u.logio.data);
  241. lio->free(sp);
  242. }
  243. int
  244. qla2x00_async_adisc(struct scsi_qla_host *vha, fc_port_t *fcport,
  245. uint16_t *data)
  246. {
  247. srb_t *sp;
  248. struct srb_ctx *ctx;
  249. struct srb_iocb *lio;
  250. int rval;
  251. rval = QLA_FUNCTION_FAILED;
  252. sp = qla2x00_get_ctx_sp(vha, fcport, sizeof(struct srb_ctx),
  253. qla2x00_get_async_timeout(vha) + 2);
  254. if (!sp)
  255. goto done;
  256. ctx = sp->ctx;
  257. ctx->type = SRB_ADISC_CMD;
  258. ctx->name = "adisc";
  259. lio = ctx->u.iocb_cmd;
  260. lio->timeout = qla2x00_async_iocb_timeout;
  261. lio->done = qla2x00_async_adisc_ctx_done;
  262. if (data[1] & QLA_LOGIO_LOGIN_RETRIED)
  263. lio->u.logio.flags |= SRB_LOGIN_RETRIED;
  264. rval = qla2x00_start_sp(sp);
  265. if (rval != QLA_SUCCESS)
  266. goto done_free_sp;
  267. ql_dbg(ql_dbg_disc, vha, 0x206f,
  268. "Async-adisc - loopid=%x portid=%02x%02x%02x.\n",
  269. fcport->loop_id, fcport->d_id.b.domain, fcport->d_id.b.area,
  270. fcport->d_id.b.al_pa);
  271. return rval;
  272. done_free_sp:
  273. lio->free(sp);
  274. done:
  275. return rval;
  276. }
  277. static void
  278. qla2x00_async_tm_cmd_ctx_done(srb_t *sp)
  279. {
  280. struct srb_ctx *ctx = sp->ctx;
  281. struct srb_iocb *iocb = (struct srb_iocb *)ctx->u.iocb_cmd;
  282. qla2x00_async_tm_cmd_done(sp->fcport->vha, sp->fcport, iocb);
  283. iocb->free(sp);
  284. }
  285. int
  286. qla2x00_async_tm_cmd(fc_port_t *fcport, uint32_t flags, uint32_t lun,
  287. uint32_t tag)
  288. {
  289. struct scsi_qla_host *vha = fcport->vha;
  290. srb_t *sp;
  291. struct srb_ctx *ctx;
  292. struct srb_iocb *tcf;
  293. int rval;
  294. rval = QLA_FUNCTION_FAILED;
  295. sp = qla2x00_get_ctx_sp(vha, fcport, sizeof(struct srb_ctx),
  296. qla2x00_get_async_timeout(vha) + 2);
  297. if (!sp)
  298. goto done;
  299. ctx = sp->ctx;
  300. ctx->type = SRB_TM_CMD;
  301. ctx->name = "tmf";
  302. tcf = ctx->u.iocb_cmd;
  303. tcf->u.tmf.flags = flags;
  304. tcf->u.tmf.lun = lun;
  305. tcf->u.tmf.data = tag;
  306. tcf->timeout = qla2x00_async_iocb_timeout;
  307. tcf->done = qla2x00_async_tm_cmd_ctx_done;
  308. rval = qla2x00_start_sp(sp);
  309. if (rval != QLA_SUCCESS)
  310. goto done_free_sp;
  311. ql_dbg(ql_dbg_taskm, vha, 0x802f,
  312. "Async-tmf loop-id=%x portid=%02x%02x%02x.\n",
  313. fcport->loop_id, fcport->d_id.b.domain, fcport->d_id.b.area,
  314. fcport->d_id.b.al_pa);
  315. return rval;
  316. done_free_sp:
  317. tcf->free(sp);
  318. done:
  319. return rval;
  320. }
  321. void
  322. qla2x00_async_login_done(struct scsi_qla_host *vha, fc_port_t *fcport,
  323. uint16_t *data)
  324. {
  325. int rval;
  326. switch (data[0]) {
  327. case MBS_COMMAND_COMPLETE:
  328. /*
  329. * Driver must validate login state - If PRLI not complete,
  330. * force a relogin attempt via implicit LOGO, PLOGI, and PRLI
  331. * requests.
  332. */
  333. rval = qla2x00_get_port_database(vha, fcport, 0);
  334. if (rval != QLA_SUCCESS) {
  335. qla2x00_post_async_logout_work(vha, fcport, NULL);
  336. qla2x00_post_async_login_work(vha, fcport, NULL);
  337. break;
  338. }
  339. if (fcport->flags & FCF_FCP2_DEVICE) {
  340. qla2x00_post_async_adisc_work(vha, fcport, data);
  341. break;
  342. }
  343. qla2x00_update_fcport(vha, fcport);
  344. break;
  345. case MBS_COMMAND_ERROR:
  346. fcport->flags &= ~FCF_ASYNC_SENT;
  347. if (data[1] & QLA_LOGIO_LOGIN_RETRIED)
  348. set_bit(RELOGIN_NEEDED, &vha->dpc_flags);
  349. else
  350. qla2x00_mark_device_lost(vha, fcport, 1, 0);
  351. break;
  352. case MBS_PORT_ID_USED:
  353. fcport->loop_id = data[1];
  354. qla2x00_post_async_logout_work(vha, fcport, NULL);
  355. qla2x00_post_async_login_work(vha, fcport, NULL);
  356. break;
  357. case MBS_LOOP_ID_USED:
  358. fcport->loop_id++;
  359. rval = qla2x00_find_new_loop_id(vha, fcport);
  360. if (rval != QLA_SUCCESS) {
  361. fcport->flags &= ~FCF_ASYNC_SENT;
  362. qla2x00_mark_device_lost(vha, fcport, 1, 0);
  363. break;
  364. }
  365. qla2x00_post_async_login_work(vha, fcport, NULL);
  366. break;
  367. }
  368. return;
  369. }
  370. void
  371. qla2x00_async_logout_done(struct scsi_qla_host *vha, fc_port_t *fcport,
  372. uint16_t *data)
  373. {
  374. qla2x00_mark_device_lost(vha, fcport, 1, 0);
  375. return;
  376. }
  377. void
  378. qla2x00_async_adisc_done(struct scsi_qla_host *vha, fc_port_t *fcport,
  379. uint16_t *data)
  380. {
  381. if (data[0] == MBS_COMMAND_COMPLETE) {
  382. qla2x00_update_fcport(vha, fcport);
  383. return;
  384. }
  385. /* Retry login. */
  386. fcport->flags &= ~FCF_ASYNC_SENT;
  387. if (data[1] & QLA_LOGIO_LOGIN_RETRIED)
  388. set_bit(RELOGIN_NEEDED, &vha->dpc_flags);
  389. else
  390. qla2x00_mark_device_lost(vha, fcport, 1, 0);
  391. return;
  392. }
  393. void
  394. qla2x00_async_tm_cmd_done(struct scsi_qla_host *vha, fc_port_t *fcport,
  395. struct srb_iocb *iocb)
  396. {
  397. int rval;
  398. uint32_t flags;
  399. uint16_t lun;
  400. flags = iocb->u.tmf.flags;
  401. lun = (uint16_t)iocb->u.tmf.lun;
  402. /* Issue Marker IOCB */
  403. rval = qla2x00_marker(vha, vha->hw->req_q_map[0],
  404. vha->hw->rsp_q_map[0], fcport->loop_id, lun,
  405. flags == TCF_LUN_RESET ? MK_SYNC_ID_LUN : MK_SYNC_ID);
  406. if ((rval != QLA_SUCCESS) || iocb->u.tmf.data) {
  407. ql_dbg(ql_dbg_taskm, vha, 0x8030,
  408. "TM IOCB failed (%x).\n", rval);
  409. }
  410. return;
  411. }
  412. /****************************************************************************/
  413. /* QLogic ISP2x00 Hardware Support Functions. */
  414. /****************************************************************************/
  415. /*
  416. * qla2x00_initialize_adapter
  417. * Initialize board.
  418. *
  419. * Input:
  420. * ha = adapter block pointer.
  421. *
  422. * Returns:
  423. * 0 = success
  424. */
  425. int
  426. qla2x00_initialize_adapter(scsi_qla_host_t *vha)
  427. {
  428. int rval;
  429. struct qla_hw_data *ha = vha->hw;
  430. struct req_que *req = ha->req_q_map[0];
  431. /* Clear adapter flags. */
  432. vha->flags.online = 0;
  433. ha->flags.chip_reset_done = 0;
  434. vha->flags.reset_active = 0;
  435. ha->flags.pci_channel_io_perm_failure = 0;
  436. ha->flags.eeh_busy = 0;
  437. ha->flags.thermal_supported = 1;
  438. atomic_set(&vha->loop_down_timer, LOOP_DOWN_TIME);
  439. atomic_set(&vha->loop_state, LOOP_DOWN);
  440. vha->device_flags = DFLG_NO_CABLE;
  441. vha->dpc_flags = 0;
  442. vha->flags.management_server_logged_in = 0;
  443. vha->marker_needed = 0;
  444. ha->isp_abort_cnt = 0;
  445. ha->beacon_blink_led = 0;
  446. set_bit(0, ha->req_qid_map);
  447. set_bit(0, ha->rsp_qid_map);
  448. ql_log(ql_log_info, vha, 0x0040,
  449. "Configuring PCI space...\n");
  450. rval = ha->isp_ops->pci_config(vha);
  451. if (rval) {
  452. ql_log(ql_log_warn, vha, 0x0044,
  453. "Unable to configure PCI space.\n");
  454. return (rval);
  455. }
  456. ha->isp_ops->reset_chip(vha);
  457. rval = qla2xxx_get_flash_info(vha);
  458. if (rval) {
  459. ql_log(ql_log_fatal, vha, 0x004f,
  460. "Unable to validate FLASH data.\n");
  461. return (rval);
  462. }
  463. ha->isp_ops->get_flash_version(vha, req->ring);
  464. ql_log(ql_log_info, vha, 0x0061,
  465. "Configure NVRAM parameters...\n");
  466. ha->isp_ops->nvram_config(vha);
  467. if (ha->flags.disable_serdes) {
  468. /* Mask HBA via NVRAM settings? */
  469. ql_log(ql_log_info, vha, 0x0077,
  470. "Masking HBA WWPN "
  471. "%02x%02x%02x%02x%02x%02x%02x%02x (via NVRAM).\n",
  472. vha->port_name[0], vha->port_name[1],
  473. vha->port_name[2], vha->port_name[3],
  474. vha->port_name[4], vha->port_name[5],
  475. vha->port_name[6], vha->port_name[7]);
  476. return QLA_FUNCTION_FAILED;
  477. }
  478. ql_log(ql_log_info, vha, 0x0078,
  479. "Verifying loaded RISC code...\n");
  480. if (qla2x00_isp_firmware(vha) != QLA_SUCCESS) {
  481. rval = ha->isp_ops->chip_diag(vha);
  482. if (rval)
  483. return (rval);
  484. rval = qla2x00_setup_chip(vha);
  485. if (rval)
  486. return (rval);
  487. }
  488. if (IS_QLA84XX(ha)) {
  489. ha->cs84xx = qla84xx_get_chip(vha);
  490. if (!ha->cs84xx) {
  491. ql_log(ql_log_warn, vha, 0x00d0,
  492. "Unable to configure ISP84XX.\n");
  493. return QLA_FUNCTION_FAILED;
  494. }
  495. }
  496. rval = qla2x00_init_rings(vha);
  497. ha->flags.chip_reset_done = 1;
  498. if (rval == QLA_SUCCESS && IS_QLA84XX(ha)) {
  499. /* Issue verify 84xx FW IOCB to complete 84xx initialization */
  500. rval = qla84xx_init_chip(vha);
  501. if (rval != QLA_SUCCESS) {
  502. ql_log(ql_log_warn, vha, 0x00d4,
  503. "Unable to initialize ISP84XX.\n");
  504. qla84xx_put_chip(vha);
  505. }
  506. }
  507. if (IS_QLA24XX_TYPE(ha) || IS_QLA25XX(ha))
  508. qla24xx_read_fcp_prio_cfg(vha);
  509. return (rval);
  510. }
  511. /**
  512. * qla2100_pci_config() - Setup ISP21xx PCI configuration registers.
  513. * @ha: HA context
  514. *
  515. * Returns 0 on success.
  516. */
  517. int
  518. qla2100_pci_config(scsi_qla_host_t *vha)
  519. {
  520. uint16_t w;
  521. unsigned long flags;
  522. struct qla_hw_data *ha = vha->hw;
  523. struct device_reg_2xxx __iomem *reg = &ha->iobase->isp;
  524. pci_set_master(ha->pdev);
  525. pci_try_set_mwi(ha->pdev);
  526. pci_read_config_word(ha->pdev, PCI_COMMAND, &w);
  527. w |= (PCI_COMMAND_PARITY | PCI_COMMAND_SERR);
  528. pci_write_config_word(ha->pdev, PCI_COMMAND, w);
  529. pci_disable_rom(ha->pdev);
  530. /* Get PCI bus information. */
  531. spin_lock_irqsave(&ha->hardware_lock, flags);
  532. ha->pci_attr = RD_REG_WORD(&reg->ctrl_status);
  533. spin_unlock_irqrestore(&ha->hardware_lock, flags);
  534. return QLA_SUCCESS;
  535. }
  536. /**
  537. * qla2300_pci_config() - Setup ISP23xx PCI configuration registers.
  538. * @ha: HA context
  539. *
  540. * Returns 0 on success.
  541. */
  542. int
  543. qla2300_pci_config(scsi_qla_host_t *vha)
  544. {
  545. uint16_t w;
  546. unsigned long flags = 0;
  547. uint32_t cnt;
  548. struct qla_hw_data *ha = vha->hw;
  549. struct device_reg_2xxx __iomem *reg = &ha->iobase->isp;
  550. pci_set_master(ha->pdev);
  551. pci_try_set_mwi(ha->pdev);
  552. pci_read_config_word(ha->pdev, PCI_COMMAND, &w);
  553. w |= (PCI_COMMAND_PARITY | PCI_COMMAND_SERR);
  554. if (IS_QLA2322(ha) || IS_QLA6322(ha))
  555. w &= ~PCI_COMMAND_INTX_DISABLE;
  556. pci_write_config_word(ha->pdev, PCI_COMMAND, w);
  557. /*
  558. * If this is a 2300 card and not 2312, reset the
  559. * COMMAND_INVALIDATE due to a bug in the 2300. Unfortunately,
  560. * the 2310 also reports itself as a 2300 so we need to get the
  561. * fb revision level -- a 6 indicates it really is a 2300 and
  562. * not a 2310.
  563. */
  564. if (IS_QLA2300(ha)) {
  565. spin_lock_irqsave(&ha->hardware_lock, flags);
  566. /* Pause RISC. */
  567. WRT_REG_WORD(&reg->hccr, HCCR_PAUSE_RISC);
  568. for (cnt = 0; cnt < 30000; cnt++) {
  569. if ((RD_REG_WORD(&reg->hccr) & HCCR_RISC_PAUSE) != 0)
  570. break;
  571. udelay(10);
  572. }
  573. /* Select FPM registers. */
  574. WRT_REG_WORD(&reg->ctrl_status, 0x20);
  575. RD_REG_WORD(&reg->ctrl_status);
  576. /* Get the fb rev level */
  577. ha->fb_rev = RD_FB_CMD_REG(ha, reg);
  578. if (ha->fb_rev == FPM_2300)
  579. pci_clear_mwi(ha->pdev);
  580. /* Deselect FPM registers. */
  581. WRT_REG_WORD(&reg->ctrl_status, 0x0);
  582. RD_REG_WORD(&reg->ctrl_status);
  583. /* Release RISC module. */
  584. WRT_REG_WORD(&reg->hccr, HCCR_RELEASE_RISC);
  585. for (cnt = 0; cnt < 30000; cnt++) {
  586. if ((RD_REG_WORD(&reg->hccr) & HCCR_RISC_PAUSE) == 0)
  587. break;
  588. udelay(10);
  589. }
  590. spin_unlock_irqrestore(&ha->hardware_lock, flags);
  591. }
  592. pci_write_config_byte(ha->pdev, PCI_LATENCY_TIMER, 0x80);
  593. pci_disable_rom(ha->pdev);
  594. /* Get PCI bus information. */
  595. spin_lock_irqsave(&ha->hardware_lock, flags);
  596. ha->pci_attr = RD_REG_WORD(&reg->ctrl_status);
  597. spin_unlock_irqrestore(&ha->hardware_lock, flags);
  598. return QLA_SUCCESS;
  599. }
  600. /**
  601. * qla24xx_pci_config() - Setup ISP24xx PCI configuration registers.
  602. * @ha: HA context
  603. *
  604. * Returns 0 on success.
  605. */
  606. int
  607. qla24xx_pci_config(scsi_qla_host_t *vha)
  608. {
  609. uint16_t w;
  610. unsigned long flags = 0;
  611. struct qla_hw_data *ha = vha->hw;
  612. struct device_reg_24xx __iomem *reg = &ha->iobase->isp24;
  613. pci_set_master(ha->pdev);
  614. pci_try_set_mwi(ha->pdev);
  615. pci_read_config_word(ha->pdev, PCI_COMMAND, &w);
  616. w |= (PCI_COMMAND_PARITY | PCI_COMMAND_SERR);
  617. w &= ~PCI_COMMAND_INTX_DISABLE;
  618. pci_write_config_word(ha->pdev, PCI_COMMAND, w);
  619. pci_write_config_byte(ha->pdev, PCI_LATENCY_TIMER, 0x80);
  620. /* PCI-X -- adjust Maximum Memory Read Byte Count (2048). */
  621. if (pci_find_capability(ha->pdev, PCI_CAP_ID_PCIX))
  622. pcix_set_mmrbc(ha->pdev, 2048);
  623. /* PCIe -- adjust Maximum Read Request Size (2048). */
  624. if (pci_find_capability(ha->pdev, PCI_CAP_ID_EXP))
  625. pcie_set_readrq(ha->pdev, 2048);
  626. pci_disable_rom(ha->pdev);
  627. ha->chip_revision = ha->pdev->revision;
  628. /* Get PCI bus information. */
  629. spin_lock_irqsave(&ha->hardware_lock, flags);
  630. ha->pci_attr = RD_REG_DWORD(&reg->ctrl_status);
  631. spin_unlock_irqrestore(&ha->hardware_lock, flags);
  632. return QLA_SUCCESS;
  633. }
  634. /**
  635. * qla25xx_pci_config() - Setup ISP25xx PCI configuration registers.
  636. * @ha: HA context
  637. *
  638. * Returns 0 on success.
  639. */
  640. int
  641. qla25xx_pci_config(scsi_qla_host_t *vha)
  642. {
  643. uint16_t w;
  644. struct qla_hw_data *ha = vha->hw;
  645. pci_set_master(ha->pdev);
  646. pci_try_set_mwi(ha->pdev);
  647. pci_read_config_word(ha->pdev, PCI_COMMAND, &w);
  648. w |= (PCI_COMMAND_PARITY | PCI_COMMAND_SERR);
  649. w &= ~PCI_COMMAND_INTX_DISABLE;
  650. pci_write_config_word(ha->pdev, PCI_COMMAND, w);
  651. /* PCIe -- adjust Maximum Read Request Size (2048). */
  652. if (pci_find_capability(ha->pdev, PCI_CAP_ID_EXP))
  653. pcie_set_readrq(ha->pdev, 2048);
  654. pci_disable_rom(ha->pdev);
  655. ha->chip_revision = ha->pdev->revision;
  656. return QLA_SUCCESS;
  657. }
  658. /**
  659. * qla2x00_isp_firmware() - Choose firmware image.
  660. * @ha: HA context
  661. *
  662. * Returns 0 on success.
  663. */
  664. static int
  665. qla2x00_isp_firmware(scsi_qla_host_t *vha)
  666. {
  667. int rval;
  668. uint16_t loop_id, topo, sw_cap;
  669. uint8_t domain, area, al_pa;
  670. struct qla_hw_data *ha = vha->hw;
  671. /* Assume loading risc code */
  672. rval = QLA_FUNCTION_FAILED;
  673. if (ha->flags.disable_risc_code_load) {
  674. ql_log(ql_log_info, vha, 0x0079, "RISC CODE NOT loaded.\n");
  675. /* Verify checksum of loaded RISC code. */
  676. rval = qla2x00_verify_checksum(vha, ha->fw_srisc_address);
  677. if (rval == QLA_SUCCESS) {
  678. /* And, verify we are not in ROM code. */
  679. rval = qla2x00_get_adapter_id(vha, &loop_id, &al_pa,
  680. &area, &domain, &topo, &sw_cap);
  681. }
  682. }
  683. if (rval)
  684. ql_dbg(ql_dbg_init, vha, 0x007a,
  685. "**** Load RISC code ****.\n");
  686. return (rval);
  687. }
  688. /**
  689. * qla2x00_reset_chip() - Reset ISP chip.
  690. * @ha: HA context
  691. *
  692. * Returns 0 on success.
  693. */
  694. void
  695. qla2x00_reset_chip(scsi_qla_host_t *vha)
  696. {
  697. unsigned long flags = 0;
  698. struct qla_hw_data *ha = vha->hw;
  699. struct device_reg_2xxx __iomem *reg = &ha->iobase->isp;
  700. uint32_t cnt;
  701. uint16_t cmd;
  702. if (unlikely(pci_channel_offline(ha->pdev)))
  703. return;
  704. ha->isp_ops->disable_intrs(ha);
  705. spin_lock_irqsave(&ha->hardware_lock, flags);
  706. /* Turn off master enable */
  707. cmd = 0;
  708. pci_read_config_word(ha->pdev, PCI_COMMAND, &cmd);
  709. cmd &= ~PCI_COMMAND_MASTER;
  710. pci_write_config_word(ha->pdev, PCI_COMMAND, cmd);
  711. if (!IS_QLA2100(ha)) {
  712. /* Pause RISC. */
  713. WRT_REG_WORD(&reg->hccr, HCCR_PAUSE_RISC);
  714. if (IS_QLA2200(ha) || IS_QLA2300(ha)) {
  715. for (cnt = 0; cnt < 30000; cnt++) {
  716. if ((RD_REG_WORD(&reg->hccr) &
  717. HCCR_RISC_PAUSE) != 0)
  718. break;
  719. udelay(100);
  720. }
  721. } else {
  722. RD_REG_WORD(&reg->hccr); /* PCI Posting. */
  723. udelay(10);
  724. }
  725. /* Select FPM registers. */
  726. WRT_REG_WORD(&reg->ctrl_status, 0x20);
  727. RD_REG_WORD(&reg->ctrl_status); /* PCI Posting. */
  728. /* FPM Soft Reset. */
  729. WRT_REG_WORD(&reg->fpm_diag_config, 0x100);
  730. RD_REG_WORD(&reg->fpm_diag_config); /* PCI Posting. */
  731. /* Toggle Fpm Reset. */
  732. if (!IS_QLA2200(ha)) {
  733. WRT_REG_WORD(&reg->fpm_diag_config, 0x0);
  734. RD_REG_WORD(&reg->fpm_diag_config); /* PCI Posting. */
  735. }
  736. /* Select frame buffer registers. */
  737. WRT_REG_WORD(&reg->ctrl_status, 0x10);
  738. RD_REG_WORD(&reg->ctrl_status); /* PCI Posting. */
  739. /* Reset frame buffer FIFOs. */
  740. if (IS_QLA2200(ha)) {
  741. WRT_FB_CMD_REG(ha, reg, 0xa000);
  742. RD_FB_CMD_REG(ha, reg); /* PCI Posting. */
  743. } else {
  744. WRT_FB_CMD_REG(ha, reg, 0x00fc);
  745. /* Read back fb_cmd until zero or 3 seconds max */
  746. for (cnt = 0; cnt < 3000; cnt++) {
  747. if ((RD_FB_CMD_REG(ha, reg) & 0xff) == 0)
  748. break;
  749. udelay(100);
  750. }
  751. }
  752. /* Select RISC module registers. */
  753. WRT_REG_WORD(&reg->ctrl_status, 0);
  754. RD_REG_WORD(&reg->ctrl_status); /* PCI Posting. */
  755. /* Reset RISC processor. */
  756. WRT_REG_WORD(&reg->hccr, HCCR_RESET_RISC);
  757. RD_REG_WORD(&reg->hccr); /* PCI Posting. */
  758. /* Release RISC processor. */
  759. WRT_REG_WORD(&reg->hccr, HCCR_RELEASE_RISC);
  760. RD_REG_WORD(&reg->hccr); /* PCI Posting. */
  761. }
  762. WRT_REG_WORD(&reg->hccr, HCCR_CLR_RISC_INT);
  763. WRT_REG_WORD(&reg->hccr, HCCR_CLR_HOST_INT);
  764. /* Reset ISP chip. */
  765. WRT_REG_WORD(&reg->ctrl_status, CSR_ISP_SOFT_RESET);
  766. /* Wait for RISC to recover from reset. */
  767. if (IS_QLA2100(ha) || IS_QLA2200(ha) || IS_QLA2300(ha)) {
  768. /*
  769. * It is necessary to for a delay here since the card doesn't
  770. * respond to PCI reads during a reset. On some architectures
  771. * this will result in an MCA.
  772. */
  773. udelay(20);
  774. for (cnt = 30000; cnt; cnt--) {
  775. if ((RD_REG_WORD(&reg->ctrl_status) &
  776. CSR_ISP_SOFT_RESET) == 0)
  777. break;
  778. udelay(100);
  779. }
  780. } else
  781. udelay(10);
  782. /* Reset RISC processor. */
  783. WRT_REG_WORD(&reg->hccr, HCCR_RESET_RISC);
  784. WRT_REG_WORD(&reg->semaphore, 0);
  785. /* Release RISC processor. */
  786. WRT_REG_WORD(&reg->hccr, HCCR_RELEASE_RISC);
  787. RD_REG_WORD(&reg->hccr); /* PCI Posting. */
  788. if (IS_QLA2100(ha) || IS_QLA2200(ha) || IS_QLA2300(ha)) {
  789. for (cnt = 0; cnt < 30000; cnt++) {
  790. if (RD_MAILBOX_REG(ha, reg, 0) != MBS_BUSY)
  791. break;
  792. udelay(100);
  793. }
  794. } else
  795. udelay(100);
  796. /* Turn on master enable */
  797. cmd |= PCI_COMMAND_MASTER;
  798. pci_write_config_word(ha->pdev, PCI_COMMAND, cmd);
  799. /* Disable RISC pause on FPM parity error. */
  800. if (!IS_QLA2100(ha)) {
  801. WRT_REG_WORD(&reg->hccr, HCCR_DISABLE_PARITY_PAUSE);
  802. RD_REG_WORD(&reg->hccr); /* PCI Posting. */
  803. }
  804. spin_unlock_irqrestore(&ha->hardware_lock, flags);
  805. }
  806. /**
  807. * qla81xx_reset_mpi() - Reset's MPI FW via Write MPI Register MBC.
  808. *
  809. * Returns 0 on success.
  810. */
  811. int
  812. qla81xx_reset_mpi(scsi_qla_host_t *vha)
  813. {
  814. uint16_t mb[4] = {0x1010, 0, 1, 0};
  815. return qla81xx_write_mpi_register(vha, mb);
  816. }
  817. /**
  818. * qla24xx_reset_risc() - Perform full reset of ISP24xx RISC.
  819. * @ha: HA context
  820. *
  821. * Returns 0 on success.
  822. */
  823. static inline void
  824. qla24xx_reset_risc(scsi_qla_host_t *vha)
  825. {
  826. unsigned long flags = 0;
  827. struct qla_hw_data *ha = vha->hw;
  828. struct device_reg_24xx __iomem *reg = &ha->iobase->isp24;
  829. uint32_t cnt, d2;
  830. uint16_t wd;
  831. static int abts_cnt; /* ISP abort retry counts */
  832. spin_lock_irqsave(&ha->hardware_lock, flags);
  833. /* Reset RISC. */
  834. WRT_REG_DWORD(&reg->ctrl_status, CSRX_DMA_SHUTDOWN|MWB_4096_BYTES);
  835. for (cnt = 0; cnt < 30000; cnt++) {
  836. if ((RD_REG_DWORD(&reg->ctrl_status) & CSRX_DMA_ACTIVE) == 0)
  837. break;
  838. udelay(10);
  839. }
  840. WRT_REG_DWORD(&reg->ctrl_status,
  841. CSRX_ISP_SOFT_RESET|CSRX_DMA_SHUTDOWN|MWB_4096_BYTES);
  842. pci_read_config_word(ha->pdev, PCI_COMMAND, &wd);
  843. udelay(100);
  844. /* Wait for firmware to complete NVRAM accesses. */
  845. d2 = (uint32_t) RD_REG_WORD(&reg->mailbox0);
  846. for (cnt = 10000 ; cnt && d2; cnt--) {
  847. udelay(5);
  848. d2 = (uint32_t) RD_REG_WORD(&reg->mailbox0);
  849. barrier();
  850. }
  851. /* Wait for soft-reset to complete. */
  852. d2 = RD_REG_DWORD(&reg->ctrl_status);
  853. for (cnt = 6000000 ; cnt && (d2 & CSRX_ISP_SOFT_RESET); cnt--) {
  854. udelay(5);
  855. d2 = RD_REG_DWORD(&reg->ctrl_status);
  856. barrier();
  857. }
  858. /* If required, do an MPI FW reset now */
  859. if (test_and_clear_bit(MPI_RESET_NEEDED, &vha->dpc_flags)) {
  860. if (qla81xx_reset_mpi(vha) != QLA_SUCCESS) {
  861. if (++abts_cnt < 5) {
  862. set_bit(ISP_ABORT_NEEDED, &vha->dpc_flags);
  863. set_bit(MPI_RESET_NEEDED, &vha->dpc_flags);
  864. } else {
  865. /*
  866. * We exhausted the ISP abort retries. We have to
  867. * set the board offline.
  868. */
  869. abts_cnt = 0;
  870. vha->flags.online = 0;
  871. }
  872. }
  873. }
  874. WRT_REG_DWORD(&reg->hccr, HCCRX_SET_RISC_RESET);
  875. RD_REG_DWORD(&reg->hccr);
  876. WRT_REG_DWORD(&reg->hccr, HCCRX_REL_RISC_PAUSE);
  877. RD_REG_DWORD(&reg->hccr);
  878. WRT_REG_DWORD(&reg->hccr, HCCRX_CLR_RISC_RESET);
  879. RD_REG_DWORD(&reg->hccr);
  880. d2 = (uint32_t) RD_REG_WORD(&reg->mailbox0);
  881. for (cnt = 6000000 ; cnt && d2; cnt--) {
  882. udelay(5);
  883. d2 = (uint32_t) RD_REG_WORD(&reg->mailbox0);
  884. barrier();
  885. }
  886. spin_unlock_irqrestore(&ha->hardware_lock, flags);
  887. if (IS_NOPOLLING_TYPE(ha))
  888. ha->isp_ops->enable_intrs(ha);
  889. }
  890. /**
  891. * qla24xx_reset_chip() - Reset ISP24xx chip.
  892. * @ha: HA context
  893. *
  894. * Returns 0 on success.
  895. */
  896. void
  897. qla24xx_reset_chip(scsi_qla_host_t *vha)
  898. {
  899. struct qla_hw_data *ha = vha->hw;
  900. if (pci_channel_offline(ha->pdev) &&
  901. ha->flags.pci_channel_io_perm_failure) {
  902. return;
  903. }
  904. ha->isp_ops->disable_intrs(ha);
  905. /* Perform RISC reset. */
  906. qla24xx_reset_risc(vha);
  907. }
  908. /**
  909. * qla2x00_chip_diag() - Test chip for proper operation.
  910. * @ha: HA context
  911. *
  912. * Returns 0 on success.
  913. */
  914. int
  915. qla2x00_chip_diag(scsi_qla_host_t *vha)
  916. {
  917. int rval;
  918. struct qla_hw_data *ha = vha->hw;
  919. struct device_reg_2xxx __iomem *reg = &ha->iobase->isp;
  920. unsigned long flags = 0;
  921. uint16_t data;
  922. uint32_t cnt;
  923. uint16_t mb[5];
  924. struct req_que *req = ha->req_q_map[0];
  925. /* Assume a failed state */
  926. rval = QLA_FUNCTION_FAILED;
  927. ql_dbg(ql_dbg_init, vha, 0x007b,
  928. "Testing device at %lx.\n", (u_long)&reg->flash_address);
  929. spin_lock_irqsave(&ha->hardware_lock, flags);
  930. /* Reset ISP chip. */
  931. WRT_REG_WORD(&reg->ctrl_status, CSR_ISP_SOFT_RESET);
  932. /*
  933. * We need to have a delay here since the card will not respond while
  934. * in reset causing an MCA on some architectures.
  935. */
  936. udelay(20);
  937. data = qla2x00_debounce_register(&reg->ctrl_status);
  938. for (cnt = 6000000 ; cnt && (data & CSR_ISP_SOFT_RESET); cnt--) {
  939. udelay(5);
  940. data = RD_REG_WORD(&reg->ctrl_status);
  941. barrier();
  942. }
  943. if (!cnt)
  944. goto chip_diag_failed;
  945. ql_dbg(ql_dbg_init, vha, 0x007c,
  946. "Reset register cleared by chip reset.\n");
  947. /* Reset RISC processor. */
  948. WRT_REG_WORD(&reg->hccr, HCCR_RESET_RISC);
  949. WRT_REG_WORD(&reg->hccr, HCCR_RELEASE_RISC);
  950. /* Workaround for QLA2312 PCI parity error */
  951. if (IS_QLA2100(ha) || IS_QLA2200(ha) || IS_QLA2300(ha)) {
  952. data = qla2x00_debounce_register(MAILBOX_REG(ha, reg, 0));
  953. for (cnt = 6000000; cnt && (data == MBS_BUSY); cnt--) {
  954. udelay(5);
  955. data = RD_MAILBOX_REG(ha, reg, 0);
  956. barrier();
  957. }
  958. } else
  959. udelay(10);
  960. if (!cnt)
  961. goto chip_diag_failed;
  962. /* Check product ID of chip */
  963. ql_dbg(ql_dbg_init, vha, 0x007d, "Checking product Id of chip.\n");
  964. mb[1] = RD_MAILBOX_REG(ha, reg, 1);
  965. mb[2] = RD_MAILBOX_REG(ha, reg, 2);
  966. mb[3] = RD_MAILBOX_REG(ha, reg, 3);
  967. mb[4] = qla2x00_debounce_register(MAILBOX_REG(ha, reg, 4));
  968. if (mb[1] != PROD_ID_1 || (mb[2] != PROD_ID_2 && mb[2] != PROD_ID_2a) ||
  969. mb[3] != PROD_ID_3) {
  970. ql_log(ql_log_warn, vha, 0x0062,
  971. "Wrong product ID = 0x%x,0x%x,0x%x.\n",
  972. mb[1], mb[2], mb[3]);
  973. goto chip_diag_failed;
  974. }
  975. ha->product_id[0] = mb[1];
  976. ha->product_id[1] = mb[2];
  977. ha->product_id[2] = mb[3];
  978. ha->product_id[3] = mb[4];
  979. /* Adjust fw RISC transfer size */
  980. if (req->length > 1024)
  981. ha->fw_transfer_size = REQUEST_ENTRY_SIZE * 1024;
  982. else
  983. ha->fw_transfer_size = REQUEST_ENTRY_SIZE *
  984. req->length;
  985. if (IS_QLA2200(ha) &&
  986. RD_MAILBOX_REG(ha, reg, 7) == QLA2200A_RISC_ROM_VER) {
  987. /* Limit firmware transfer size with a 2200A */
  988. ql_dbg(ql_dbg_init, vha, 0x007e, "Found QLA2200A Chip.\n");
  989. ha->device_type |= DT_ISP2200A;
  990. ha->fw_transfer_size = 128;
  991. }
  992. /* Wrap Incoming Mailboxes Test. */
  993. spin_unlock_irqrestore(&ha->hardware_lock, flags);
  994. ql_dbg(ql_dbg_init, vha, 0x007f, "Checking mailboxes.\n");
  995. rval = qla2x00_mbx_reg_test(vha);
  996. if (rval)
  997. ql_log(ql_log_warn, vha, 0x0080,
  998. "Failed mailbox send register test.\n");
  999. else
  1000. /* Flag a successful rval */
  1001. rval = QLA_SUCCESS;
  1002. spin_lock_irqsave(&ha->hardware_lock, flags);
  1003. chip_diag_failed:
  1004. if (rval)
  1005. ql_log(ql_log_info, vha, 0x0081,
  1006. "Chip diagnostics **** FAILED ****.\n");
  1007. spin_unlock_irqrestore(&ha->hardware_lock, flags);
  1008. return (rval);
  1009. }
  1010. /**
  1011. * qla24xx_chip_diag() - Test ISP24xx for proper operation.
  1012. * @ha: HA context
  1013. *
  1014. * Returns 0 on success.
  1015. */
  1016. int
  1017. qla24xx_chip_diag(scsi_qla_host_t *vha)
  1018. {
  1019. int rval;
  1020. struct qla_hw_data *ha = vha->hw;
  1021. struct req_que *req = ha->req_q_map[0];
  1022. if (IS_QLA82XX(ha))
  1023. return QLA_SUCCESS;
  1024. ha->fw_transfer_size = REQUEST_ENTRY_SIZE * req->length;
  1025. rval = qla2x00_mbx_reg_test(vha);
  1026. if (rval) {
  1027. ql_log(ql_log_warn, vha, 0x0082,
  1028. "Failed mailbox send register test.\n");
  1029. } else {
  1030. /* Flag a successful rval */
  1031. rval = QLA_SUCCESS;
  1032. }
  1033. return rval;
  1034. }
  1035. void
  1036. qla2x00_alloc_fw_dump(scsi_qla_host_t *vha)
  1037. {
  1038. int rval;
  1039. uint32_t dump_size, fixed_size, mem_size, req_q_size, rsp_q_size,
  1040. eft_size, fce_size, mq_size;
  1041. dma_addr_t tc_dma;
  1042. void *tc;
  1043. struct qla_hw_data *ha = vha->hw;
  1044. struct req_que *req = ha->req_q_map[0];
  1045. struct rsp_que *rsp = ha->rsp_q_map[0];
  1046. if (ha->fw_dump) {
  1047. ql_dbg(ql_dbg_init, vha, 0x00bd,
  1048. "Firmware dump already allocated.\n");
  1049. return;
  1050. }
  1051. ha->fw_dumped = 0;
  1052. fixed_size = mem_size = eft_size = fce_size = mq_size = 0;
  1053. if (IS_QLA2100(ha) || IS_QLA2200(ha)) {
  1054. fixed_size = sizeof(struct qla2100_fw_dump);
  1055. } else if (IS_QLA23XX(ha)) {
  1056. fixed_size = offsetof(struct qla2300_fw_dump, data_ram);
  1057. mem_size = (ha->fw_memory_size - 0x11000 + 1) *
  1058. sizeof(uint16_t);
  1059. } else if (IS_FWI2_CAPABLE(ha)) {
  1060. if (IS_QLA81XX(ha))
  1061. fixed_size = offsetof(struct qla81xx_fw_dump, ext_mem);
  1062. else if (IS_QLA25XX(ha))
  1063. fixed_size = offsetof(struct qla25xx_fw_dump, ext_mem);
  1064. else
  1065. fixed_size = offsetof(struct qla24xx_fw_dump, ext_mem);
  1066. mem_size = (ha->fw_memory_size - 0x100000 + 1) *
  1067. sizeof(uint32_t);
  1068. if (ha->mqenable)
  1069. mq_size = sizeof(struct qla2xxx_mq_chain);
  1070. /* Allocate memory for Fibre Channel Event Buffer. */
  1071. if (!IS_QLA25XX(ha) && !IS_QLA81XX(ha))
  1072. goto try_eft;
  1073. tc = dma_alloc_coherent(&ha->pdev->dev, FCE_SIZE, &tc_dma,
  1074. GFP_KERNEL);
  1075. if (!tc) {
  1076. ql_log(ql_log_warn, vha, 0x00be,
  1077. "Unable to allocate (%d KB) for FCE.\n",
  1078. FCE_SIZE / 1024);
  1079. goto try_eft;
  1080. }
  1081. memset(tc, 0, FCE_SIZE);
  1082. rval = qla2x00_enable_fce_trace(vha, tc_dma, FCE_NUM_BUFFERS,
  1083. ha->fce_mb, &ha->fce_bufs);
  1084. if (rval) {
  1085. ql_log(ql_log_warn, vha, 0x00bf,
  1086. "Unable to initialize FCE (%d).\n", rval);
  1087. dma_free_coherent(&ha->pdev->dev, FCE_SIZE, tc,
  1088. tc_dma);
  1089. ha->flags.fce_enabled = 0;
  1090. goto try_eft;
  1091. }
  1092. ql_log(ql_log_info, vha, 0x00c0,
  1093. "Allocate (%d KB) for FCE...\n", FCE_SIZE / 1024);
  1094. fce_size = sizeof(struct qla2xxx_fce_chain) + FCE_SIZE;
  1095. ha->flags.fce_enabled = 1;
  1096. ha->fce_dma = tc_dma;
  1097. ha->fce = tc;
  1098. try_eft:
  1099. /* Allocate memory for Extended Trace Buffer. */
  1100. tc = dma_alloc_coherent(&ha->pdev->dev, EFT_SIZE, &tc_dma,
  1101. GFP_KERNEL);
  1102. if (!tc) {
  1103. ql_log(ql_log_warn, vha, 0x00c1,
  1104. "Unable to allocate (%d KB) for EFT.\n",
  1105. EFT_SIZE / 1024);
  1106. goto cont_alloc;
  1107. }
  1108. memset(tc, 0, EFT_SIZE);
  1109. rval = qla2x00_enable_eft_trace(vha, tc_dma, EFT_NUM_BUFFERS);
  1110. if (rval) {
  1111. ql_log(ql_log_warn, vha, 0x00c2,
  1112. "Unable to initialize EFT (%d).\n", rval);
  1113. dma_free_coherent(&ha->pdev->dev, EFT_SIZE, tc,
  1114. tc_dma);
  1115. goto cont_alloc;
  1116. }
  1117. ql_log(ql_log_info, vha, 0x00c3,
  1118. "Allocated (%d KB) EFT ...\n", EFT_SIZE / 1024);
  1119. eft_size = EFT_SIZE;
  1120. ha->eft_dma = tc_dma;
  1121. ha->eft = tc;
  1122. }
  1123. cont_alloc:
  1124. req_q_size = req->length * sizeof(request_t);
  1125. rsp_q_size = rsp->length * sizeof(response_t);
  1126. dump_size = offsetof(struct qla2xxx_fw_dump, isp);
  1127. dump_size += fixed_size + mem_size + req_q_size + rsp_q_size + eft_size;
  1128. ha->chain_offset = dump_size;
  1129. dump_size += mq_size + fce_size;
  1130. ha->fw_dump = vmalloc(dump_size);
  1131. if (!ha->fw_dump) {
  1132. ql_log(ql_log_warn, vha, 0x00c4,
  1133. "Unable to allocate (%d KB) for firmware dump.\n",
  1134. dump_size / 1024);
  1135. if (ha->fce) {
  1136. dma_free_coherent(&ha->pdev->dev, FCE_SIZE, ha->fce,
  1137. ha->fce_dma);
  1138. ha->fce = NULL;
  1139. ha->fce_dma = 0;
  1140. }
  1141. if (ha->eft) {
  1142. dma_free_coherent(&ha->pdev->dev, eft_size, ha->eft,
  1143. ha->eft_dma);
  1144. ha->eft = NULL;
  1145. ha->eft_dma = 0;
  1146. }
  1147. return;
  1148. }
  1149. ql_log(ql_log_info, vha, 0x00c5,
  1150. "Allocated (%d KB) for firmware dump.\n", dump_size / 1024);
  1151. ha->fw_dump_len = dump_size;
  1152. ha->fw_dump->signature[0] = 'Q';
  1153. ha->fw_dump->signature[1] = 'L';
  1154. ha->fw_dump->signature[2] = 'G';
  1155. ha->fw_dump->signature[3] = 'C';
  1156. ha->fw_dump->version = __constant_htonl(1);
  1157. ha->fw_dump->fixed_size = htonl(fixed_size);
  1158. ha->fw_dump->mem_size = htonl(mem_size);
  1159. ha->fw_dump->req_q_size = htonl(req_q_size);
  1160. ha->fw_dump->rsp_q_size = htonl(rsp_q_size);
  1161. ha->fw_dump->eft_size = htonl(eft_size);
  1162. ha->fw_dump->eft_addr_l = htonl(LSD(ha->eft_dma));
  1163. ha->fw_dump->eft_addr_h = htonl(MSD(ha->eft_dma));
  1164. ha->fw_dump->header_size =
  1165. htonl(offsetof(struct qla2xxx_fw_dump, isp));
  1166. }
  1167. static int
  1168. qla81xx_mpi_sync(scsi_qla_host_t *vha)
  1169. {
  1170. #define MPS_MASK 0xe0
  1171. int rval;
  1172. uint16_t dc;
  1173. uint32_t dw;
  1174. if (!IS_QLA81XX(vha->hw))
  1175. return QLA_SUCCESS;
  1176. rval = qla2x00_write_ram_word(vha, 0x7c00, 1);
  1177. if (rval != QLA_SUCCESS) {
  1178. ql_log(ql_log_warn, vha, 0x0105,
  1179. "Unable to acquire semaphore.\n");
  1180. goto done;
  1181. }
  1182. pci_read_config_word(vha->hw->pdev, 0x54, &dc);
  1183. rval = qla2x00_read_ram_word(vha, 0x7a15, &dw);
  1184. if (rval != QLA_SUCCESS) {
  1185. ql_log(ql_log_warn, vha, 0x0067, "Unable to read sync.\n");
  1186. goto done_release;
  1187. }
  1188. dc &= MPS_MASK;
  1189. if (dc == (dw & MPS_MASK))
  1190. goto done_release;
  1191. dw &= ~MPS_MASK;
  1192. dw |= dc;
  1193. rval = qla2x00_write_ram_word(vha, 0x7a15, dw);
  1194. if (rval != QLA_SUCCESS) {
  1195. ql_log(ql_log_warn, vha, 0x0114, "Unable to gain sync.\n");
  1196. }
  1197. done_release:
  1198. rval = qla2x00_write_ram_word(vha, 0x7c00, 0);
  1199. if (rval != QLA_SUCCESS) {
  1200. ql_log(ql_log_warn, vha, 0x006d,
  1201. "Unable to release semaphore.\n");
  1202. }
  1203. done:
  1204. return rval;
  1205. }
  1206. /**
  1207. * qla2x00_setup_chip() - Load and start RISC firmware.
  1208. * @ha: HA context
  1209. *
  1210. * Returns 0 on success.
  1211. */
  1212. static int
  1213. qla2x00_setup_chip(scsi_qla_host_t *vha)
  1214. {
  1215. int rval;
  1216. uint32_t srisc_address = 0;
  1217. struct qla_hw_data *ha = vha->hw;
  1218. struct device_reg_2xxx __iomem *reg = &ha->iobase->isp;
  1219. unsigned long flags;
  1220. uint16_t fw_major_version;
  1221. if (IS_QLA82XX(ha)) {
  1222. rval = ha->isp_ops->load_risc(vha, &srisc_address);
  1223. if (rval == QLA_SUCCESS) {
  1224. qla2x00_stop_firmware(vha);
  1225. goto enable_82xx_npiv;
  1226. } else
  1227. goto failed;
  1228. }
  1229. if (!IS_FWI2_CAPABLE(ha) && !IS_QLA2100(ha) && !IS_QLA2200(ha)) {
  1230. /* Disable SRAM, Instruction RAM and GP RAM parity. */
  1231. spin_lock_irqsave(&ha->hardware_lock, flags);
  1232. WRT_REG_WORD(&reg->hccr, (HCCR_ENABLE_PARITY + 0x0));
  1233. RD_REG_WORD(&reg->hccr);
  1234. spin_unlock_irqrestore(&ha->hardware_lock, flags);
  1235. }
  1236. qla81xx_mpi_sync(vha);
  1237. /* Load firmware sequences */
  1238. rval = ha->isp_ops->load_risc(vha, &srisc_address);
  1239. if (rval == QLA_SUCCESS) {
  1240. ql_dbg(ql_dbg_init, vha, 0x00c9,
  1241. "Verifying Checksum of loaded RISC code.\n");
  1242. rval = qla2x00_verify_checksum(vha, srisc_address);
  1243. if (rval == QLA_SUCCESS) {
  1244. /* Start firmware execution. */
  1245. ql_dbg(ql_dbg_init, vha, 0x00ca,
  1246. "Starting firmware.\n");
  1247. rval = qla2x00_execute_fw(vha, srisc_address);
  1248. /* Retrieve firmware information. */
  1249. if (rval == QLA_SUCCESS) {
  1250. enable_82xx_npiv:
  1251. fw_major_version = ha->fw_major_version;
  1252. if (IS_QLA82XX(ha))
  1253. qla82xx_check_md_needed(vha);
  1254. else {
  1255. rval = qla2x00_get_fw_version(vha,
  1256. &ha->fw_major_version,
  1257. &ha->fw_minor_version,
  1258. &ha->fw_subminor_version,
  1259. &ha->fw_attributes,
  1260. &ha->fw_memory_size,
  1261. ha->mpi_version,
  1262. &ha->mpi_capabilities,
  1263. ha->phy_version);
  1264. }
  1265. if (rval != QLA_SUCCESS)
  1266. goto failed;
  1267. ha->flags.npiv_supported = 0;
  1268. if (IS_QLA2XXX_MIDTYPE(ha) &&
  1269. (ha->fw_attributes & BIT_2)) {
  1270. ha->flags.npiv_supported = 1;
  1271. if ((!ha->max_npiv_vports) ||
  1272. ((ha->max_npiv_vports + 1) %
  1273. MIN_MULTI_ID_FABRIC))
  1274. ha->max_npiv_vports =
  1275. MIN_MULTI_ID_FABRIC - 1;
  1276. }
  1277. qla2x00_get_resource_cnts(vha, NULL,
  1278. &ha->fw_xcb_count, NULL, NULL,
  1279. &ha->max_npiv_vports, NULL);
  1280. if (!fw_major_version && ql2xallocfwdump)
  1281. qla2x00_alloc_fw_dump(vha);
  1282. }
  1283. } else {
  1284. ql_log(ql_log_fatal, vha, 0x00cd,
  1285. "ISP Firmware failed checksum.\n");
  1286. goto failed;
  1287. }
  1288. }
  1289. if (!IS_FWI2_CAPABLE(ha) && !IS_QLA2100(ha) && !IS_QLA2200(ha)) {
  1290. /* Enable proper parity. */
  1291. spin_lock_irqsave(&ha->hardware_lock, flags);
  1292. if (IS_QLA2300(ha))
  1293. /* SRAM parity */
  1294. WRT_REG_WORD(&reg->hccr, HCCR_ENABLE_PARITY + 0x1);
  1295. else
  1296. /* SRAM, Instruction RAM and GP RAM parity */
  1297. WRT_REG_WORD(&reg->hccr, HCCR_ENABLE_PARITY + 0x7);
  1298. RD_REG_WORD(&reg->hccr);
  1299. spin_unlock_irqrestore(&ha->hardware_lock, flags);
  1300. }
  1301. if (rval == QLA_SUCCESS && IS_FAC_REQUIRED(ha)) {
  1302. uint32_t size;
  1303. rval = qla81xx_fac_get_sector_size(vha, &size);
  1304. if (rval == QLA_SUCCESS) {
  1305. ha->flags.fac_supported = 1;
  1306. ha->fdt_block_size = size << 2;
  1307. } else {
  1308. ql_log(ql_log_warn, vha, 0x00ce,
  1309. "Unsupported FAC firmware (%d.%02d.%02d).\n",
  1310. ha->fw_major_version, ha->fw_minor_version,
  1311. ha->fw_subminor_version);
  1312. }
  1313. }
  1314. failed:
  1315. if (rval) {
  1316. ql_log(ql_log_fatal, vha, 0x00cf,
  1317. "Setup chip ****FAILED****.\n");
  1318. }
  1319. return (rval);
  1320. }
  1321. /**
  1322. * qla2x00_init_response_q_entries() - Initializes response queue entries.
  1323. * @ha: HA context
  1324. *
  1325. * Beginning of request ring has initialization control block already built
  1326. * by nvram config routine.
  1327. *
  1328. * Returns 0 on success.
  1329. */
  1330. void
  1331. qla2x00_init_response_q_entries(struct rsp_que *rsp)
  1332. {
  1333. uint16_t cnt;
  1334. response_t *pkt;
  1335. rsp->ring_ptr = rsp->ring;
  1336. rsp->ring_index = 0;
  1337. rsp->status_srb = NULL;
  1338. pkt = rsp->ring_ptr;
  1339. for (cnt = 0; cnt < rsp->length; cnt++) {
  1340. pkt->signature = RESPONSE_PROCESSED;
  1341. pkt++;
  1342. }
  1343. }
  1344. /**
  1345. * qla2x00_update_fw_options() - Read and process firmware options.
  1346. * @ha: HA context
  1347. *
  1348. * Returns 0 on success.
  1349. */
  1350. void
  1351. qla2x00_update_fw_options(scsi_qla_host_t *vha)
  1352. {
  1353. uint16_t swing, emphasis, tx_sens, rx_sens;
  1354. struct qla_hw_data *ha = vha->hw;
  1355. memset(ha->fw_options, 0, sizeof(ha->fw_options));
  1356. qla2x00_get_fw_options(vha, ha->fw_options);
  1357. if (IS_QLA2100(ha) || IS_QLA2200(ha))
  1358. return;
  1359. /* Serial Link options. */
  1360. ql_dbg(ql_dbg_init + ql_dbg_buffer, vha, 0x0115,
  1361. "Serial link options.\n");
  1362. ql_dump_buffer(ql_dbg_init + ql_dbg_buffer, vha, 0x0109,
  1363. (uint8_t *)&ha->fw_seriallink_options,
  1364. sizeof(ha->fw_seriallink_options));
  1365. ha->fw_options[1] &= ~FO1_SET_EMPHASIS_SWING;
  1366. if (ha->fw_seriallink_options[3] & BIT_2) {
  1367. ha->fw_options[1] |= FO1_SET_EMPHASIS_SWING;
  1368. /* 1G settings */
  1369. swing = ha->fw_seriallink_options[2] & (BIT_2 | BIT_1 | BIT_0);
  1370. emphasis = (ha->fw_seriallink_options[2] &
  1371. (BIT_4 | BIT_3)) >> 3;
  1372. tx_sens = ha->fw_seriallink_options[0] &
  1373. (BIT_3 | BIT_2 | BIT_1 | BIT_0);
  1374. rx_sens = (ha->fw_seriallink_options[0] &
  1375. (BIT_7 | BIT_6 | BIT_5 | BIT_4)) >> 4;
  1376. ha->fw_options[10] = (emphasis << 14) | (swing << 8);
  1377. if (IS_QLA2300(ha) || IS_QLA2312(ha) || IS_QLA6312(ha)) {
  1378. if (rx_sens == 0x0)
  1379. rx_sens = 0x3;
  1380. ha->fw_options[10] |= (tx_sens << 4) | rx_sens;
  1381. } else if (IS_QLA2322(ha) || IS_QLA6322(ha))
  1382. ha->fw_options[10] |= BIT_5 |
  1383. ((rx_sens & (BIT_1 | BIT_0)) << 2) |
  1384. (tx_sens & (BIT_1 | BIT_0));
  1385. /* 2G settings */
  1386. swing = (ha->fw_seriallink_options[2] &
  1387. (BIT_7 | BIT_6 | BIT_5)) >> 5;
  1388. emphasis = ha->fw_seriallink_options[3] & (BIT_1 | BIT_0);
  1389. tx_sens = ha->fw_seriallink_options[1] &
  1390. (BIT_3 | BIT_2 | BIT_1 | BIT_0);
  1391. rx_sens = (ha->fw_seriallink_options[1] &
  1392. (BIT_7 | BIT_6 | BIT_5 | BIT_4)) >> 4;
  1393. ha->fw_options[11] = (emphasis << 14) | (swing << 8);
  1394. if (IS_QLA2300(ha) || IS_QLA2312(ha) || IS_QLA6312(ha)) {
  1395. if (rx_sens == 0x0)
  1396. rx_sens = 0x3;
  1397. ha->fw_options[11] |= (tx_sens << 4) | rx_sens;
  1398. } else if (IS_QLA2322(ha) || IS_QLA6322(ha))
  1399. ha->fw_options[11] |= BIT_5 |
  1400. ((rx_sens & (BIT_1 | BIT_0)) << 2) |
  1401. (tx_sens & (BIT_1 | BIT_0));
  1402. }
  1403. /* FCP2 options. */
  1404. /* Return command IOCBs without waiting for an ABTS to complete. */
  1405. ha->fw_options[3] |= BIT_13;
  1406. /* LED scheme. */
  1407. if (ha->flags.enable_led_scheme)
  1408. ha->fw_options[2] |= BIT_12;
  1409. /* Detect ISP6312. */
  1410. if (IS_QLA6312(ha))
  1411. ha->fw_options[2] |= BIT_13;
  1412. /* Update firmware options. */
  1413. qla2x00_set_fw_options(vha, ha->fw_options);
  1414. }
  1415. void
  1416. qla24xx_update_fw_options(scsi_qla_host_t *vha)
  1417. {
  1418. int rval;
  1419. struct qla_hw_data *ha = vha->hw;
  1420. if (IS_QLA82XX(ha))
  1421. return;
  1422. /* Update Serial Link options. */
  1423. if ((le16_to_cpu(ha->fw_seriallink_options24[0]) & BIT_0) == 0)
  1424. return;
  1425. rval = qla2x00_set_serdes_params(vha,
  1426. le16_to_cpu(ha->fw_seriallink_options24[1]),
  1427. le16_to_cpu(ha->fw_seriallink_options24[2]),
  1428. le16_to_cpu(ha->fw_seriallink_options24[3]));
  1429. if (rval != QLA_SUCCESS) {
  1430. ql_log(ql_log_warn, vha, 0x0104,
  1431. "Unable to update Serial Link options (%x).\n", rval);
  1432. }
  1433. }
  1434. void
  1435. qla2x00_config_rings(struct scsi_qla_host *vha)
  1436. {
  1437. struct qla_hw_data *ha = vha->hw;
  1438. struct device_reg_2xxx __iomem *reg = &ha->iobase->isp;
  1439. struct req_que *req = ha->req_q_map[0];
  1440. struct rsp_que *rsp = ha->rsp_q_map[0];
  1441. /* Setup ring parameters in initialization control block. */
  1442. ha->init_cb->request_q_outpointer = __constant_cpu_to_le16(0);
  1443. ha->init_cb->response_q_inpointer = __constant_cpu_to_le16(0);
  1444. ha->init_cb->request_q_length = cpu_to_le16(req->length);
  1445. ha->init_cb->response_q_length = cpu_to_le16(rsp->length);
  1446. ha->init_cb->request_q_address[0] = cpu_to_le32(LSD(req->dma));
  1447. ha->init_cb->request_q_address[1] = cpu_to_le32(MSD(req->dma));
  1448. ha->init_cb->response_q_address[0] = cpu_to_le32(LSD(rsp->dma));
  1449. ha->init_cb->response_q_address[1] = cpu_to_le32(MSD(rsp->dma));
  1450. WRT_REG_WORD(ISP_REQ_Q_IN(ha, reg), 0);
  1451. WRT_REG_WORD(ISP_REQ_Q_OUT(ha, reg), 0);
  1452. WRT_REG_WORD(ISP_RSP_Q_IN(ha, reg), 0);
  1453. WRT_REG_WORD(ISP_RSP_Q_OUT(ha, reg), 0);
  1454. RD_REG_WORD(ISP_RSP_Q_OUT(ha, reg)); /* PCI Posting. */
  1455. }
  1456. void
  1457. qla24xx_config_rings(struct scsi_qla_host *vha)
  1458. {
  1459. struct qla_hw_data *ha = vha->hw;
  1460. device_reg_t __iomem *reg = ISP_QUE_REG(ha, 0);
  1461. struct device_reg_2xxx __iomem *ioreg = &ha->iobase->isp;
  1462. struct qla_msix_entry *msix;
  1463. struct init_cb_24xx *icb;
  1464. uint16_t rid = 0;
  1465. struct req_que *req = ha->req_q_map[0];
  1466. struct rsp_que *rsp = ha->rsp_q_map[0];
  1467. /* Setup ring parameters in initialization control block. */
  1468. icb = (struct init_cb_24xx *)ha->init_cb;
  1469. icb->request_q_outpointer = __constant_cpu_to_le16(0);
  1470. icb->response_q_inpointer = __constant_cpu_to_le16(0);
  1471. icb->request_q_length = cpu_to_le16(req->length);
  1472. icb->response_q_length = cpu_to_le16(rsp->length);
  1473. icb->request_q_address[0] = cpu_to_le32(LSD(req->dma));
  1474. icb->request_q_address[1] = cpu_to_le32(MSD(req->dma));
  1475. icb->response_q_address[0] = cpu_to_le32(LSD(rsp->dma));
  1476. icb->response_q_address[1] = cpu_to_le32(MSD(rsp->dma));
  1477. if (ha->mqenable) {
  1478. icb->qos = __constant_cpu_to_le16(QLA_DEFAULT_QUE_QOS);
  1479. icb->rid = __constant_cpu_to_le16(rid);
  1480. if (ha->flags.msix_enabled) {
  1481. msix = &ha->msix_entries[1];
  1482. ql_dbg(ql_dbg_init, vha, 0x00fd,
  1483. "Registering vector 0x%x for base que.\n",
  1484. msix->entry);
  1485. icb->msix = cpu_to_le16(msix->entry);
  1486. }
  1487. /* Use alternate PCI bus number */
  1488. if (MSB(rid))
  1489. icb->firmware_options_2 |=
  1490. __constant_cpu_to_le32(BIT_19);
  1491. /* Use alternate PCI devfn */
  1492. if (LSB(rid))
  1493. icb->firmware_options_2 |=
  1494. __constant_cpu_to_le32(BIT_18);
  1495. /* Use Disable MSIX Handshake mode for capable adapters */
  1496. if (IS_MSIX_NACK_CAPABLE(ha)) {
  1497. icb->firmware_options_2 &=
  1498. __constant_cpu_to_le32(~BIT_22);
  1499. ha->flags.disable_msix_handshake = 1;
  1500. ql_dbg(ql_dbg_init, vha, 0x00fe,
  1501. "MSIX Handshake Disable Mode turned on.\n");
  1502. } else {
  1503. icb->firmware_options_2 |=
  1504. __constant_cpu_to_le32(BIT_22);
  1505. }
  1506. icb->firmware_options_2 |= __constant_cpu_to_le32(BIT_23);
  1507. WRT_REG_DWORD(&reg->isp25mq.req_q_in, 0);
  1508. WRT_REG_DWORD(&reg->isp25mq.req_q_out, 0);
  1509. WRT_REG_DWORD(&reg->isp25mq.rsp_q_in, 0);
  1510. WRT_REG_DWORD(&reg->isp25mq.rsp_q_out, 0);
  1511. } else {
  1512. WRT_REG_DWORD(&reg->isp24.req_q_in, 0);
  1513. WRT_REG_DWORD(&reg->isp24.req_q_out, 0);
  1514. WRT_REG_DWORD(&reg->isp24.rsp_q_in, 0);
  1515. WRT_REG_DWORD(&reg->isp24.rsp_q_out, 0);
  1516. }
  1517. /* PCI posting */
  1518. RD_REG_DWORD(&ioreg->hccr);
  1519. }
  1520. /**
  1521. * qla2x00_init_rings() - Initializes firmware.
  1522. * @ha: HA context
  1523. *
  1524. * Beginning of request ring has initialization control block already built
  1525. * by nvram config routine.
  1526. *
  1527. * Returns 0 on success.
  1528. */
  1529. static int
  1530. qla2x00_init_rings(scsi_qla_host_t *vha)
  1531. {
  1532. int rval;
  1533. unsigned long flags = 0;
  1534. int cnt, que;
  1535. struct qla_hw_data *ha = vha->hw;
  1536. struct req_que *req;
  1537. struct rsp_que *rsp;
  1538. struct scsi_qla_host *vp;
  1539. struct mid_init_cb_24xx *mid_init_cb =
  1540. (struct mid_init_cb_24xx *) ha->init_cb;
  1541. spin_lock_irqsave(&ha->hardware_lock, flags);
  1542. /* Clear outstanding commands array. */
  1543. for (que = 0; que < ha->max_req_queues; que++) {
  1544. req = ha->req_q_map[que];
  1545. if (!req)
  1546. continue;
  1547. for (cnt = 1; cnt < MAX_OUTSTANDING_COMMANDS; cnt++)
  1548. req->outstanding_cmds[cnt] = NULL;
  1549. req->current_outstanding_cmd = 1;
  1550. /* Initialize firmware. */
  1551. req->ring_ptr = req->ring;
  1552. req->ring_index = 0;
  1553. req->cnt = req->length;
  1554. }
  1555. for (que = 0; que < ha->max_rsp_queues; que++) {
  1556. rsp = ha->rsp_q_map[que];
  1557. if (!rsp)
  1558. continue;
  1559. /* Initialize response queue entries */
  1560. qla2x00_init_response_q_entries(rsp);
  1561. }
  1562. spin_lock(&ha->vport_slock);
  1563. /* Clear RSCN queue. */
  1564. list_for_each_entry(vp, &ha->vp_list, list) {
  1565. vp->rscn_in_ptr = 0;
  1566. vp->rscn_out_ptr = 0;
  1567. }
  1568. spin_unlock(&ha->vport_slock);
  1569. ha->isp_ops->config_rings(vha);
  1570. spin_unlock_irqrestore(&ha->hardware_lock, flags);
  1571. /* Update any ISP specific firmware options before initialization. */
  1572. ha->isp_ops->update_fw_options(vha);
  1573. ql_dbg(ql_dbg_init, vha, 0x00d1, "Issue init firmware.\n");
  1574. if (ha->flags.npiv_supported) {
  1575. if (ha->operating_mode == LOOP)
  1576. ha->max_npiv_vports = MIN_MULTI_ID_FABRIC - 1;
  1577. mid_init_cb->count = cpu_to_le16(ha->max_npiv_vports);
  1578. }
  1579. if (IS_FWI2_CAPABLE(ha)) {
  1580. mid_init_cb->options = __constant_cpu_to_le16(BIT_1);
  1581. mid_init_cb->init_cb.execution_throttle =
  1582. cpu_to_le16(ha->fw_xcb_count);
  1583. }
  1584. rval = qla2x00_init_firmware(vha, ha->init_cb_size);
  1585. if (rval) {
  1586. ql_log(ql_log_fatal, vha, 0x00d2,
  1587. "Init Firmware **** FAILED ****.\n");
  1588. } else {
  1589. ql_dbg(ql_dbg_init, vha, 0x00d3,
  1590. "Init Firmware -- success.\n");
  1591. }
  1592. return (rval);
  1593. }
  1594. /**
  1595. * qla2x00_fw_ready() - Waits for firmware ready.
  1596. * @ha: HA context
  1597. *
  1598. * Returns 0 on success.
  1599. */
  1600. static int
  1601. qla2x00_fw_ready(scsi_qla_host_t *vha)
  1602. {
  1603. int rval;
  1604. unsigned long wtime, mtime, cs84xx_time;
  1605. uint16_t min_wait; /* Minimum wait time if loop is down */
  1606. uint16_t wait_time; /* Wait time if loop is coming ready */
  1607. uint16_t state[5];
  1608. struct qla_hw_data *ha = vha->hw;
  1609. rval = QLA_SUCCESS;
  1610. /* 20 seconds for loop down. */
  1611. min_wait = 20;
  1612. /*
  1613. * Firmware should take at most one RATOV to login, plus 5 seconds for
  1614. * our own processing.
  1615. */
  1616. if ((wait_time = (ha->retry_count*ha->login_timeout) + 5) < min_wait) {
  1617. wait_time = min_wait;
  1618. }
  1619. /* Min wait time if loop down */
  1620. mtime = jiffies + (min_wait * HZ);
  1621. /* wait time before firmware ready */
  1622. wtime = jiffies + (wait_time * HZ);
  1623. /* Wait for ISP to finish LIP */
  1624. if (!vha->flags.init_done)
  1625. ql_log(ql_log_info, vha, 0x801e,
  1626. "Waiting for LIP to complete.\n");
  1627. do {
  1628. rval = qla2x00_get_firmware_state(vha, state);
  1629. if (rval == QLA_SUCCESS) {
  1630. if (state[0] < FSTATE_LOSS_OF_SYNC) {
  1631. vha->device_flags &= ~DFLG_NO_CABLE;
  1632. }
  1633. if (IS_QLA84XX(ha) && state[0] != FSTATE_READY) {
  1634. ql_dbg(ql_dbg_taskm, vha, 0x801f,
  1635. "fw_state=%x 84xx=%x.\n", state[0],
  1636. state[2]);
  1637. if ((state[2] & FSTATE_LOGGED_IN) &&
  1638. (state[2] & FSTATE_WAITING_FOR_VERIFY)) {
  1639. ql_dbg(ql_dbg_taskm, vha, 0x8028,
  1640. "Sending verify iocb.\n");
  1641. cs84xx_time = jiffies;
  1642. rval = qla84xx_init_chip(vha);
  1643. if (rval != QLA_SUCCESS) {
  1644. ql_log(ql_log_warn,
  1645. vha, 0x8026,
  1646. "Init chip failed.\n");
  1647. break;
  1648. }
  1649. /* Add time taken to initialize. */
  1650. cs84xx_time = jiffies - cs84xx_time;
  1651. wtime += cs84xx_time;
  1652. mtime += cs84xx_time;
  1653. ql_dbg(ql_dbg_taskm, vha, 0x8025,
  1654. "Increasing wait time by %ld. "
  1655. "New time %ld.\n", cs84xx_time,
  1656. wtime);
  1657. }
  1658. } else if (state[0] == FSTATE_READY) {
  1659. ql_dbg(ql_dbg_taskm, vha, 0x8037,
  1660. "F/W Ready - OK.\n");
  1661. qla2x00_get_retry_cnt(vha, &ha->retry_count,
  1662. &ha->login_timeout, &ha->r_a_tov);
  1663. rval = QLA_SUCCESS;
  1664. break;
  1665. }
  1666. rval = QLA_FUNCTION_FAILED;
  1667. if (atomic_read(&vha->loop_down_timer) &&
  1668. state[0] != FSTATE_READY) {
  1669. /* Loop down. Timeout on min_wait for states
  1670. * other than Wait for Login.
  1671. */
  1672. if (time_after_eq(jiffies, mtime)) {
  1673. ql_log(ql_log_info, vha, 0x8038,
  1674. "Cable is unplugged...\n");
  1675. vha->device_flags |= DFLG_NO_CABLE;
  1676. break;
  1677. }
  1678. }
  1679. } else {
  1680. /* Mailbox cmd failed. Timeout on min_wait. */
  1681. if (time_after_eq(jiffies, mtime) ||
  1682. ha->flags.isp82xx_fw_hung)
  1683. break;
  1684. }
  1685. if (time_after_eq(jiffies, wtime))
  1686. break;
  1687. /* Delay for a while */
  1688. msleep(500);
  1689. ql_dbg(ql_dbg_taskm, vha, 0x8039,
  1690. "fw_state=%x curr time=%lx.\n", state[0], jiffies);
  1691. } while (1);
  1692. ql_dbg(ql_dbg_taskm, vha, 0x803a,
  1693. "fw_state=%x (%x, %x, %x, %x) " "curr time=%lx.\n", state[0],
  1694. state[1], state[2], state[3], state[4], jiffies);
  1695. if (rval) {
  1696. ql_log(ql_log_warn, vha, 0x803b,
  1697. "Firmware ready **** FAILED ****.\n");
  1698. }
  1699. return (rval);
  1700. }
  1701. /*
  1702. * qla2x00_configure_hba
  1703. * Setup adapter context.
  1704. *
  1705. * Input:
  1706. * ha = adapter state pointer.
  1707. *
  1708. * Returns:
  1709. * 0 = success
  1710. *
  1711. * Context:
  1712. * Kernel context.
  1713. */
  1714. static int
  1715. qla2x00_configure_hba(scsi_qla_host_t *vha)
  1716. {
  1717. int rval;
  1718. uint16_t loop_id;
  1719. uint16_t topo;
  1720. uint16_t sw_cap;
  1721. uint8_t al_pa;
  1722. uint8_t area;
  1723. uint8_t domain;
  1724. char connect_type[22];
  1725. struct qla_hw_data *ha = vha->hw;
  1726. /* Get host addresses. */
  1727. rval = qla2x00_get_adapter_id(vha,
  1728. &loop_id, &al_pa, &area, &domain, &topo, &sw_cap);
  1729. if (rval != QLA_SUCCESS) {
  1730. if (LOOP_TRANSITION(vha) || atomic_read(&ha->loop_down_timer) ||
  1731. IS_QLA8XXX_TYPE(ha) ||
  1732. (rval == QLA_COMMAND_ERROR && loop_id == 0x7)) {
  1733. ql_dbg(ql_dbg_disc, vha, 0x2008,
  1734. "Loop is in a transition state.\n");
  1735. } else {
  1736. ql_log(ql_log_warn, vha, 0x2009,
  1737. "Unable to get host loop ID.\n");
  1738. set_bit(ISP_ABORT_NEEDED, &vha->dpc_flags);
  1739. }
  1740. return (rval);
  1741. }
  1742. if (topo == 4) {
  1743. ql_log(ql_log_info, vha, 0x200a,
  1744. "Cannot get topology - retrying.\n");
  1745. return (QLA_FUNCTION_FAILED);
  1746. }
  1747. vha->loop_id = loop_id;
  1748. /* initialize */
  1749. ha->min_external_loopid = SNS_FIRST_LOOP_ID;
  1750. ha->operating_mode = LOOP;
  1751. ha->switch_cap = 0;
  1752. switch (topo) {
  1753. case 0:
  1754. ql_dbg(ql_dbg_disc, vha, 0x200b, "HBA in NL topology.\n");
  1755. ha->current_topology = ISP_CFG_NL;
  1756. strcpy(connect_type, "(Loop)");
  1757. break;
  1758. case 1:
  1759. ql_dbg(ql_dbg_disc, vha, 0x200c, "HBA in FL topology.\n");
  1760. ha->switch_cap = sw_cap;
  1761. ha->current_topology = ISP_CFG_FL;
  1762. strcpy(connect_type, "(FL_Port)");
  1763. break;
  1764. case 2:
  1765. ql_dbg(ql_dbg_disc, vha, 0x200d, "HBA in N P2P topology.\n");
  1766. ha->operating_mode = P2P;
  1767. ha->current_topology = ISP_CFG_N;
  1768. strcpy(connect_type, "(N_Port-to-N_Port)");
  1769. break;
  1770. case 3:
  1771. ql_dbg(ql_dbg_disc, vha, 0x200e, "HBA in F P2P topology.\n");
  1772. ha->switch_cap = sw_cap;
  1773. ha->operating_mode = P2P;
  1774. ha->current_topology = ISP_CFG_F;
  1775. strcpy(connect_type, "(F_Port)");
  1776. break;
  1777. default:
  1778. ql_dbg(ql_dbg_disc, vha, 0x200f,
  1779. "HBA in unknown topology %x, using NL.\n", topo);
  1780. ha->current_topology = ISP_CFG_NL;
  1781. strcpy(connect_type, "(Loop)");
  1782. break;
  1783. }
  1784. /* Save Host port and loop ID. */
  1785. /* byte order - Big Endian */
  1786. vha->d_id.b.domain = domain;
  1787. vha->d_id.b.area = area;
  1788. vha->d_id.b.al_pa = al_pa;
  1789. if (!vha->flags.init_done)
  1790. ql_log(ql_log_info, vha, 0x2010,
  1791. "Topology - %s, Host Loop address 0x%x.\n",
  1792. connect_type, vha->loop_id);
  1793. if (rval) {
  1794. ql_log(ql_log_warn, vha, 0x2011,
  1795. "%s FAILED\n", __func__);
  1796. } else {
  1797. ql_dbg(ql_dbg_disc, vha, 0x2012,
  1798. "%s success\n", __func__);
  1799. }
  1800. return(rval);
  1801. }
  1802. inline void
  1803. qla2x00_set_model_info(scsi_qla_host_t *vha, uint8_t *model, size_t len,
  1804. char *def)
  1805. {
  1806. char *st, *en;
  1807. uint16_t index;
  1808. struct qla_hw_data *ha = vha->hw;
  1809. int use_tbl = !IS_QLA24XX_TYPE(ha) && !IS_QLA25XX(ha) &&
  1810. !IS_QLA8XXX_TYPE(ha);
  1811. if (memcmp(model, BINZERO, len) != 0) {
  1812. strncpy(ha->model_number, model, len);
  1813. st = en = ha->model_number;
  1814. en += len - 1;
  1815. while (en > st) {
  1816. if (*en != 0x20 && *en != 0x00)
  1817. break;
  1818. *en-- = '\0';
  1819. }
  1820. index = (ha->pdev->subsystem_device & 0xff);
  1821. if (use_tbl &&
  1822. ha->pdev->subsystem_vendor == PCI_VENDOR_ID_QLOGIC &&
  1823. index < QLA_MODEL_NAMES)
  1824. strncpy(ha->model_desc,
  1825. qla2x00_model_name[index * 2 + 1],
  1826. sizeof(ha->model_desc) - 1);
  1827. } else {
  1828. index = (ha->pdev->subsystem_device & 0xff);
  1829. if (use_tbl &&
  1830. ha->pdev->subsystem_vendor == PCI_VENDOR_ID_QLOGIC &&
  1831. index < QLA_MODEL_NAMES) {
  1832. strcpy(ha->model_number,
  1833. qla2x00_model_name[index * 2]);
  1834. strncpy(ha->model_desc,
  1835. qla2x00_model_name[index * 2 + 1],
  1836. sizeof(ha->model_desc) - 1);
  1837. } else {
  1838. strcpy(ha->model_number, def);
  1839. }
  1840. }
  1841. if (IS_FWI2_CAPABLE(ha))
  1842. qla2xxx_get_vpd_field(vha, "\x82", ha->model_desc,
  1843. sizeof(ha->model_desc));
  1844. }
  1845. /* On sparc systems, obtain port and node WWN from firmware
  1846. * properties.
  1847. */
  1848. static void qla2xxx_nvram_wwn_from_ofw(scsi_qla_host_t *vha, nvram_t *nv)
  1849. {
  1850. #ifdef CONFIG_SPARC
  1851. struct qla_hw_data *ha = vha->hw;
  1852. struct pci_dev *pdev = ha->pdev;
  1853. struct device_node *dp = pci_device_to_OF_node(pdev);
  1854. const u8 *val;
  1855. int len;
  1856. val = of_get_property(dp, "port-wwn", &len);
  1857. if (val && len >= WWN_SIZE)
  1858. memcpy(nv->port_name, val, WWN_SIZE);
  1859. val = of_get_property(dp, "node-wwn", &len);
  1860. if (val && len >= WWN_SIZE)
  1861. memcpy(nv->node_name, val, WWN_SIZE);
  1862. #endif
  1863. }
  1864. /*
  1865. * NVRAM configuration for ISP 2xxx
  1866. *
  1867. * Input:
  1868. * ha = adapter block pointer.
  1869. *
  1870. * Output:
  1871. * initialization control block in response_ring
  1872. * host adapters parameters in host adapter block
  1873. *
  1874. * Returns:
  1875. * 0 = success.
  1876. */
  1877. int
  1878. qla2x00_nvram_config(scsi_qla_host_t *vha)
  1879. {
  1880. int rval;
  1881. uint8_t chksum = 0;
  1882. uint16_t cnt;
  1883. uint8_t *dptr1, *dptr2;
  1884. struct qla_hw_data *ha = vha->hw;
  1885. init_cb_t *icb = ha->init_cb;
  1886. nvram_t *nv = ha->nvram;
  1887. uint8_t *ptr = ha->nvram;
  1888. struct device_reg_2xxx __iomem *reg = &ha->iobase->isp;
  1889. rval = QLA_SUCCESS;
  1890. /* Determine NVRAM starting address. */
  1891. ha->nvram_size = sizeof(nvram_t);
  1892. ha->nvram_base = 0;
  1893. if (!IS_QLA2100(ha) && !IS_QLA2200(ha) && !IS_QLA2300(ha))
  1894. if ((RD_REG_WORD(&reg->ctrl_status) >> 14) == 1)
  1895. ha->nvram_base = 0x80;
  1896. /* Get NVRAM data and calculate checksum. */
  1897. ha->isp_ops->read_nvram(vha, ptr, ha->nvram_base, ha->nvram_size);
  1898. for (cnt = 0, chksum = 0; cnt < ha->nvram_size; cnt++)
  1899. chksum += *ptr++;
  1900. ql_dbg(ql_dbg_init + ql_dbg_buffer, vha, 0x010f,
  1901. "Contents of NVRAM.\n");
  1902. ql_dump_buffer(ql_dbg_init + ql_dbg_buffer, vha, 0x0110,
  1903. (uint8_t *)nv, ha->nvram_size);
  1904. /* Bad NVRAM data, set defaults parameters. */
  1905. if (chksum || nv->id[0] != 'I' || nv->id[1] != 'S' ||
  1906. nv->id[2] != 'P' || nv->id[3] != ' ' || nv->nvram_version < 1) {
  1907. /* Reset NVRAM data. */
  1908. ql_log(ql_log_warn, vha, 0x0064,
  1909. "Inconisistent NVRAM "
  1910. "detected: checksum=0x%x id=%c version=0x%x.\n",
  1911. chksum, nv->id[0], nv->nvram_version);
  1912. ql_log(ql_log_warn, vha, 0x0065,
  1913. "Falling back to "
  1914. "functioning (yet invalid -- WWPN) defaults.\n");
  1915. /*
  1916. * Set default initialization control block.
  1917. */
  1918. memset(nv, 0, ha->nvram_size);
  1919. nv->parameter_block_version = ICB_VERSION;
  1920. if (IS_QLA23XX(ha)) {
  1921. nv->firmware_options[0] = BIT_2 | BIT_1;
  1922. nv->firmware_options[1] = BIT_7 | BIT_5;
  1923. nv->add_firmware_options[0] = BIT_5;
  1924. nv->add_firmware_options[1] = BIT_5 | BIT_4;
  1925. nv->frame_payload_size = __constant_cpu_to_le16(2048);
  1926. nv->special_options[1] = BIT_7;
  1927. } else if (IS_QLA2200(ha)) {
  1928. nv->firmware_options[0] = BIT_2 | BIT_1;
  1929. nv->firmware_options[1] = BIT_7 | BIT_5;
  1930. nv->add_firmware_options[0] = BIT_5;
  1931. nv->add_firmware_options[1] = BIT_5 | BIT_4;
  1932. nv->frame_payload_size = __constant_cpu_to_le16(1024);
  1933. } else if (IS_QLA2100(ha)) {
  1934. nv->firmware_options[0] = BIT_3 | BIT_1;
  1935. nv->firmware_options[1] = BIT_5;
  1936. nv->frame_payload_size = __constant_cpu_to_le16(1024);
  1937. }
  1938. nv->max_iocb_allocation = __constant_cpu_to_le16(256);
  1939. nv->execution_throttle = __constant_cpu_to_le16(16);
  1940. nv->retry_count = 8;
  1941. nv->retry_delay = 1;
  1942. nv->port_name[0] = 33;
  1943. nv->port_name[3] = 224;
  1944. nv->port_name[4] = 139;
  1945. qla2xxx_nvram_wwn_from_ofw(vha, nv);
  1946. nv->login_timeout = 4;
  1947. /*
  1948. * Set default host adapter parameters
  1949. */
  1950. nv->host_p[1] = BIT_2;
  1951. nv->reset_delay = 5;
  1952. nv->port_down_retry_count = 8;
  1953. nv->max_luns_per_target = __constant_cpu_to_le16(8);
  1954. nv->link_down_timeout = 60;
  1955. rval = 1;
  1956. }
  1957. #if defined(CONFIG_IA64_GENERIC) || defined(CONFIG_IA64_SGI_SN2)
  1958. /*
  1959. * The SN2 does not provide BIOS emulation which means you can't change
  1960. * potentially bogus BIOS settings. Force the use of default settings
  1961. * for link rate and frame size. Hope that the rest of the settings
  1962. * are valid.
  1963. */
  1964. if (ia64_platform_is("sn2")) {
  1965. nv->frame_payload_size = __constant_cpu_to_le16(2048);
  1966. if (IS_QLA23XX(ha))
  1967. nv->special_options[1] = BIT_7;
  1968. }
  1969. #endif
  1970. /* Reset Initialization control block */
  1971. memset(icb, 0, ha->init_cb_size);
  1972. /*
  1973. * Setup driver NVRAM options.
  1974. */
  1975. nv->firmware_options[0] |= (BIT_6 | BIT_1);
  1976. nv->firmware_options[0] &= ~(BIT_5 | BIT_4);
  1977. nv->firmware_options[1] |= (BIT_5 | BIT_0);
  1978. nv->firmware_options[1] &= ~BIT_4;
  1979. if (IS_QLA23XX(ha)) {
  1980. nv->firmware_options[0] |= BIT_2;
  1981. nv->firmware_options[0] &= ~BIT_3;
  1982. nv->firmware_options[0] &= ~BIT_6;
  1983. nv->add_firmware_options[1] |= BIT_5 | BIT_4;
  1984. if (IS_QLA2300(ha)) {
  1985. if (ha->fb_rev == FPM_2310) {
  1986. strcpy(ha->model_number, "QLA2310");
  1987. } else {
  1988. strcpy(ha->model_number, "QLA2300");
  1989. }
  1990. } else {
  1991. qla2x00_set_model_info(vha, nv->model_number,
  1992. sizeof(nv->model_number), "QLA23xx");
  1993. }
  1994. } else if (IS_QLA2200(ha)) {
  1995. nv->firmware_options[0] |= BIT_2;
  1996. /*
  1997. * 'Point-to-point preferred, else loop' is not a safe
  1998. * connection mode setting.
  1999. */
  2000. if ((nv->add_firmware_options[0] & (BIT_6 | BIT_5 | BIT_4)) ==
  2001. (BIT_5 | BIT_4)) {
  2002. /* Force 'loop preferred, else point-to-point'. */
  2003. nv->add_firmware_options[0] &= ~(BIT_6 | BIT_5 | BIT_4);
  2004. nv->add_firmware_options[0] |= BIT_5;
  2005. }
  2006. strcpy(ha->model_number, "QLA22xx");
  2007. } else /*if (IS_QLA2100(ha))*/ {
  2008. strcpy(ha->model_number, "QLA2100");
  2009. }
  2010. /*
  2011. * Copy over NVRAM RISC parameter block to initialization control block.
  2012. */
  2013. dptr1 = (uint8_t *)icb;
  2014. dptr2 = (uint8_t *)&nv->parameter_block_version;
  2015. cnt = (uint8_t *)&icb->request_q_outpointer - (uint8_t *)&icb->version;
  2016. while (cnt--)
  2017. *dptr1++ = *dptr2++;
  2018. /* Copy 2nd half. */
  2019. dptr1 = (uint8_t *)icb->add_firmware_options;
  2020. cnt = (uint8_t *)icb->reserved_3 - (uint8_t *)icb->add_firmware_options;
  2021. while (cnt--)
  2022. *dptr1++ = *dptr2++;
  2023. /* Use alternate WWN? */
  2024. if (nv->host_p[1] & BIT_7) {
  2025. memcpy(icb->node_name, nv->alternate_node_name, WWN_SIZE);
  2026. memcpy(icb->port_name, nv->alternate_port_name, WWN_SIZE);
  2027. }
  2028. /* Prepare nodename */
  2029. if ((icb->firmware_options[1] & BIT_6) == 0) {
  2030. /*
  2031. * Firmware will apply the following mask if the nodename was
  2032. * not provided.
  2033. */
  2034. memcpy(icb->node_name, icb->port_name, WWN_SIZE);
  2035. icb->node_name[0] &= 0xF0;
  2036. }
  2037. /*
  2038. * Set host adapter parameters.
  2039. */
  2040. /*
  2041. * BIT_7 in the host-parameters section allows for modification to
  2042. * internal driver logging.
  2043. */
  2044. if (nv->host_p[0] & BIT_7)
  2045. ql2xextended_error_logging = 0x7fffffff;
  2046. ha->flags.disable_risc_code_load = ((nv->host_p[0] & BIT_4) ? 1 : 0);
  2047. /* Always load RISC code on non ISP2[12]00 chips. */
  2048. if (!IS_QLA2100(ha) && !IS_QLA2200(ha))
  2049. ha->flags.disable_risc_code_load = 0;
  2050. ha->flags.enable_lip_reset = ((nv->host_p[1] & BIT_1) ? 1 : 0);
  2051. ha->flags.enable_lip_full_login = ((nv->host_p[1] & BIT_2) ? 1 : 0);
  2052. ha->flags.enable_target_reset = ((nv->host_p[1] & BIT_3) ? 1 : 0);
  2053. ha->flags.enable_led_scheme = (nv->special_options[1] & BIT_4) ? 1 : 0;
  2054. ha->flags.disable_serdes = 0;
  2055. ha->operating_mode =
  2056. (icb->add_firmware_options[0] & (BIT_6 | BIT_5 | BIT_4)) >> 4;
  2057. memcpy(ha->fw_seriallink_options, nv->seriallink_options,
  2058. sizeof(ha->fw_seriallink_options));
  2059. /* save HBA serial number */
  2060. ha->serial0 = icb->port_name[5];
  2061. ha->serial1 = icb->port_name[6];
  2062. ha->serial2 = icb->port_name[7];
  2063. memcpy(vha->node_name, icb->node_name, WWN_SIZE);
  2064. memcpy(vha->port_name, icb->port_name, WWN_SIZE);
  2065. icb->execution_throttle = __constant_cpu_to_le16(0xFFFF);
  2066. ha->retry_count = nv->retry_count;
  2067. /* Set minimum login_timeout to 4 seconds. */
  2068. if (nv->login_timeout != ql2xlogintimeout)
  2069. nv->login_timeout = ql2xlogintimeout;
  2070. if (nv->login_timeout < 4)
  2071. nv->login_timeout = 4;
  2072. ha->login_timeout = nv->login_timeout;
  2073. icb->login_timeout = nv->login_timeout;
  2074. /* Set minimum RATOV to 100 tenths of a second. */
  2075. ha->r_a_tov = 100;
  2076. ha->loop_reset_delay = nv->reset_delay;
  2077. /* Link Down Timeout = 0:
  2078. *
  2079. * When Port Down timer expires we will start returning
  2080. * I/O's to OS with "DID_NO_CONNECT".
  2081. *
  2082. * Link Down Timeout != 0:
  2083. *
  2084. * The driver waits for the link to come up after link down
  2085. * before returning I/Os to OS with "DID_NO_CONNECT".
  2086. */
  2087. if (nv->link_down_timeout == 0) {
  2088. ha->loop_down_abort_time =
  2089. (LOOP_DOWN_TIME - LOOP_DOWN_TIMEOUT);
  2090. } else {
  2091. ha->link_down_timeout = nv->link_down_timeout;
  2092. ha->loop_down_abort_time =
  2093. (LOOP_DOWN_TIME - ha->link_down_timeout);
  2094. }
  2095. /*
  2096. * Need enough time to try and get the port back.
  2097. */
  2098. ha->port_down_retry_count = nv->port_down_retry_count;
  2099. if (qlport_down_retry)
  2100. ha->port_down_retry_count = qlport_down_retry;
  2101. /* Set login_retry_count */
  2102. ha->login_retry_count = nv->retry_count;
  2103. if (ha->port_down_retry_count == nv->port_down_retry_count &&
  2104. ha->port_down_retry_count > 3)
  2105. ha->login_retry_count = ha->port_down_retry_count;
  2106. else if (ha->port_down_retry_count > (int)ha->login_retry_count)
  2107. ha->login_retry_count = ha->port_down_retry_count;
  2108. if (ql2xloginretrycount)
  2109. ha->login_retry_count = ql2xloginretrycount;
  2110. icb->lun_enables = __constant_cpu_to_le16(0);
  2111. icb->command_resource_count = 0;
  2112. icb->immediate_notify_resource_count = 0;
  2113. icb->timeout = __constant_cpu_to_le16(0);
  2114. if (IS_QLA2100(ha) || IS_QLA2200(ha)) {
  2115. /* Enable RIO */
  2116. icb->firmware_options[0] &= ~BIT_3;
  2117. icb->add_firmware_options[0] &=
  2118. ~(BIT_3 | BIT_2 | BIT_1 | BIT_0);
  2119. icb->add_firmware_options[0] |= BIT_2;
  2120. icb->response_accumulation_timer = 3;
  2121. icb->interrupt_delay_timer = 5;
  2122. vha->flags.process_response_queue = 1;
  2123. } else {
  2124. /* Enable ZIO. */
  2125. if (!vha->flags.init_done) {
  2126. ha->zio_mode = icb->add_firmware_options[0] &
  2127. (BIT_3 | BIT_2 | BIT_1 | BIT_0);
  2128. ha->zio_timer = icb->interrupt_delay_timer ?
  2129. icb->interrupt_delay_timer: 2;
  2130. }
  2131. icb->add_firmware_options[0] &=
  2132. ~(BIT_3 | BIT_2 | BIT_1 | BIT_0);
  2133. vha->flags.process_response_queue = 0;
  2134. if (ha->zio_mode != QLA_ZIO_DISABLED) {
  2135. ha->zio_mode = QLA_ZIO_MODE_6;
  2136. ql_log(ql_log_info, vha, 0x0068,
  2137. "ZIO mode %d enabled; timer delay (%d us).\n",
  2138. ha->zio_mode, ha->zio_timer * 100);
  2139. icb->add_firmware_options[0] |= (uint8_t)ha->zio_mode;
  2140. icb->interrupt_delay_timer = (uint8_t)ha->zio_timer;
  2141. vha->flags.process_response_queue = 1;
  2142. }
  2143. }
  2144. if (rval) {
  2145. ql_log(ql_log_warn, vha, 0x0069,
  2146. "NVRAM configuration failed.\n");
  2147. }
  2148. return (rval);
  2149. }
  2150. static void
  2151. qla2x00_rport_del(void *data)
  2152. {
  2153. fc_port_t *fcport = data;
  2154. struct fc_rport *rport;
  2155. unsigned long flags;
  2156. spin_lock_irqsave(fcport->vha->host->host_lock, flags);
  2157. rport = fcport->drport ? fcport->drport: fcport->rport;
  2158. fcport->drport = NULL;
  2159. spin_unlock_irqrestore(fcport->vha->host->host_lock, flags);
  2160. if (rport)
  2161. fc_remote_port_delete(rport);
  2162. }
  2163. /**
  2164. * qla2x00_alloc_fcport() - Allocate a generic fcport.
  2165. * @ha: HA context
  2166. * @flags: allocation flags
  2167. *
  2168. * Returns a pointer to the allocated fcport, or NULL, if none available.
  2169. */
  2170. fc_port_t *
  2171. qla2x00_alloc_fcport(scsi_qla_host_t *vha, gfp_t flags)
  2172. {
  2173. fc_port_t *fcport;
  2174. fcport = kzalloc(sizeof(fc_port_t), flags);
  2175. if (!fcport)
  2176. return NULL;
  2177. /* Setup fcport template structure. */
  2178. fcport->vha = vha;
  2179. fcport->vp_idx = vha->vp_idx;
  2180. fcport->port_type = FCT_UNKNOWN;
  2181. fcport->loop_id = FC_NO_LOOP_ID;
  2182. qla2x00_set_fcport_state(fcport, FCS_UNCONFIGURED);
  2183. fcport->supported_classes = FC_COS_UNSPECIFIED;
  2184. return fcport;
  2185. }
  2186. /*
  2187. * qla2x00_configure_loop
  2188. * Updates Fibre Channel Device Database with what is actually on loop.
  2189. *
  2190. * Input:
  2191. * ha = adapter block pointer.
  2192. *
  2193. * Returns:
  2194. * 0 = success.
  2195. * 1 = error.
  2196. * 2 = database was full and device was not configured.
  2197. */
  2198. static int
  2199. qla2x00_configure_loop(scsi_qla_host_t *vha)
  2200. {
  2201. int rval;
  2202. unsigned long flags, save_flags;
  2203. struct qla_hw_data *ha = vha->hw;
  2204. rval = QLA_SUCCESS;
  2205. /* Get Initiator ID */
  2206. if (test_bit(LOCAL_LOOP_UPDATE, &vha->dpc_flags)) {
  2207. rval = qla2x00_configure_hba(vha);
  2208. if (rval != QLA_SUCCESS) {
  2209. ql_dbg(ql_dbg_disc, vha, 0x2013,
  2210. "Unable to configure HBA.\n");
  2211. return (rval);
  2212. }
  2213. }
  2214. save_flags = flags = vha->dpc_flags;
  2215. ql_dbg(ql_dbg_disc, vha, 0x2014,
  2216. "Configure loop -- dpc flags = 0x%lx.\n", flags);
  2217. /*
  2218. * If we have both an RSCN and PORT UPDATE pending then handle them
  2219. * both at the same time.
  2220. */
  2221. clear_bit(LOCAL_LOOP_UPDATE, &vha->dpc_flags);
  2222. clear_bit(RSCN_UPDATE, &vha->dpc_flags);
  2223. qla2x00_get_data_rate(vha);
  2224. /* Determine what we need to do */
  2225. if (ha->current_topology == ISP_CFG_FL &&
  2226. (test_bit(LOCAL_LOOP_UPDATE, &flags))) {
  2227. vha->flags.rscn_queue_overflow = 1;
  2228. set_bit(RSCN_UPDATE, &flags);
  2229. } else if (ha->current_topology == ISP_CFG_F &&
  2230. (test_bit(LOCAL_LOOP_UPDATE, &flags))) {
  2231. vha->flags.rscn_queue_overflow = 1;
  2232. set_bit(RSCN_UPDATE, &flags);
  2233. clear_bit(LOCAL_LOOP_UPDATE, &flags);
  2234. } else if (ha->current_topology == ISP_CFG_N) {
  2235. clear_bit(RSCN_UPDATE, &flags);
  2236. } else if (!vha->flags.online ||
  2237. (test_bit(ABORT_ISP_ACTIVE, &flags))) {
  2238. vha->flags.rscn_queue_overflow = 1;
  2239. set_bit(RSCN_UPDATE, &flags);
  2240. set_bit(LOCAL_LOOP_UPDATE, &flags);
  2241. }
  2242. if (test_bit(LOCAL_LOOP_UPDATE, &flags)) {
  2243. if (test_bit(LOOP_RESYNC_NEEDED, &vha->dpc_flags)) {
  2244. ql_dbg(ql_dbg_disc, vha, 0x2015,
  2245. "Loop resync needed, failing.\n");
  2246. rval = QLA_FUNCTION_FAILED;
  2247. }
  2248. else
  2249. rval = qla2x00_configure_local_loop(vha);
  2250. }
  2251. if (rval == QLA_SUCCESS && test_bit(RSCN_UPDATE, &flags)) {
  2252. if (LOOP_TRANSITION(vha)) {
  2253. ql_dbg(ql_dbg_disc, vha, 0x201e,
  2254. "Needs RSCN update and loop transition.\n");
  2255. rval = QLA_FUNCTION_FAILED;
  2256. }
  2257. else
  2258. rval = qla2x00_configure_fabric(vha);
  2259. }
  2260. if (rval == QLA_SUCCESS) {
  2261. if (atomic_read(&vha->loop_down_timer) ||
  2262. test_bit(LOOP_RESYNC_NEEDED, &vha->dpc_flags)) {
  2263. rval = QLA_FUNCTION_FAILED;
  2264. } else {
  2265. atomic_set(&vha->loop_state, LOOP_READY);
  2266. ql_dbg(ql_dbg_disc, vha, 0x2069,
  2267. "LOOP READY.\n");
  2268. }
  2269. }
  2270. if (rval) {
  2271. ql_dbg(ql_dbg_disc, vha, 0x206a,
  2272. "%s *** FAILED ***.\n", __func__);
  2273. } else {
  2274. ql_dbg(ql_dbg_disc, vha, 0x206b,
  2275. "%s: exiting normally.\n", __func__);
  2276. }
  2277. /* Restore state if a resync event occurred during processing */
  2278. if (test_bit(LOOP_RESYNC_NEEDED, &vha->dpc_flags)) {
  2279. if (test_bit(LOCAL_LOOP_UPDATE, &save_flags))
  2280. set_bit(LOCAL_LOOP_UPDATE, &vha->dpc_flags);
  2281. if (test_bit(RSCN_UPDATE, &save_flags)) {
  2282. set_bit(RSCN_UPDATE, &vha->dpc_flags);
  2283. if (!IS_ALOGIO_CAPABLE(ha))
  2284. vha->flags.rscn_queue_overflow = 1;
  2285. }
  2286. }
  2287. return (rval);
  2288. }
  2289. /*
  2290. * qla2x00_configure_local_loop
  2291. * Updates Fibre Channel Device Database with local loop devices.
  2292. *
  2293. * Input:
  2294. * ha = adapter block pointer.
  2295. *
  2296. * Returns:
  2297. * 0 = success.
  2298. */
  2299. static int
  2300. qla2x00_configure_local_loop(scsi_qla_host_t *vha)
  2301. {
  2302. int rval, rval2;
  2303. int found_devs;
  2304. int found;
  2305. fc_port_t *fcport, *new_fcport;
  2306. uint16_t index;
  2307. uint16_t entries;
  2308. char *id_iter;
  2309. uint16_t loop_id;
  2310. uint8_t domain, area, al_pa;
  2311. struct qla_hw_data *ha = vha->hw;
  2312. found_devs = 0;
  2313. new_fcport = NULL;
  2314. entries = MAX_FIBRE_DEVICES;
  2315. ql_dbg(ql_dbg_disc, vha, 0x2016,
  2316. "Getting FCAL position map.\n");
  2317. if (ql2xextended_error_logging & ql_dbg_disc)
  2318. qla2x00_get_fcal_position_map(vha, NULL);
  2319. /* Get list of logged in devices. */
  2320. memset(ha->gid_list, 0, GID_LIST_SIZE);
  2321. rval = qla2x00_get_id_list(vha, ha->gid_list, ha->gid_list_dma,
  2322. &entries);
  2323. if (rval != QLA_SUCCESS)
  2324. goto cleanup_allocation;
  2325. ql_dbg(ql_dbg_disc, vha, 0x2017,
  2326. "Entries in ID list (%d).\n", entries);
  2327. ql_dump_buffer(ql_dbg_disc + ql_dbg_buffer, vha, 0x2075,
  2328. (uint8_t *)ha->gid_list,
  2329. entries * sizeof(struct gid_list_info));
  2330. /* Allocate temporary fcport for any new fcports discovered. */
  2331. new_fcport = qla2x00_alloc_fcport(vha, GFP_KERNEL);
  2332. if (new_fcport == NULL) {
  2333. ql_log(ql_log_warn, vha, 0x2018,
  2334. "Memory allocation failed for fcport.\n");
  2335. rval = QLA_MEMORY_ALLOC_FAILED;
  2336. goto cleanup_allocation;
  2337. }
  2338. new_fcport->flags &= ~FCF_FABRIC_DEVICE;
  2339. /*
  2340. * Mark local devices that were present with FCF_DEVICE_LOST for now.
  2341. */
  2342. list_for_each_entry(fcport, &vha->vp_fcports, list) {
  2343. if (atomic_read(&fcport->state) == FCS_ONLINE &&
  2344. fcport->port_type != FCT_BROADCAST &&
  2345. (fcport->flags & FCF_FABRIC_DEVICE) == 0) {
  2346. ql_dbg(ql_dbg_disc, vha, 0x2019,
  2347. "Marking port lost loop_id=0x%04x.\n",
  2348. fcport->loop_id);
  2349. qla2x00_set_fcport_state(fcport, FCS_DEVICE_LOST);
  2350. }
  2351. }
  2352. /* Add devices to port list. */
  2353. id_iter = (char *)ha->gid_list;
  2354. for (index = 0; index < entries; index++) {
  2355. domain = ((struct gid_list_info *)id_iter)->domain;
  2356. area = ((struct gid_list_info *)id_iter)->area;
  2357. al_pa = ((struct gid_list_info *)id_iter)->al_pa;
  2358. if (IS_QLA2100(ha) || IS_QLA2200(ha))
  2359. loop_id = (uint16_t)
  2360. ((struct gid_list_info *)id_iter)->loop_id_2100;
  2361. else
  2362. loop_id = le16_to_cpu(
  2363. ((struct gid_list_info *)id_iter)->loop_id);
  2364. id_iter += ha->gid_list_info_size;
  2365. /* Bypass reserved domain fields. */
  2366. if ((domain & 0xf0) == 0xf0)
  2367. continue;
  2368. /* Bypass if not same domain and area of adapter. */
  2369. if (area && domain &&
  2370. (area != vha->d_id.b.area || domain != vha->d_id.b.domain))
  2371. continue;
  2372. /* Bypass invalid local loop ID. */
  2373. if (loop_id > LAST_LOCAL_LOOP_ID)
  2374. continue;
  2375. /* Fill in member data. */
  2376. new_fcport->d_id.b.domain = domain;
  2377. new_fcport->d_id.b.area = area;
  2378. new_fcport->d_id.b.al_pa = al_pa;
  2379. new_fcport->loop_id = loop_id;
  2380. new_fcport->vp_idx = vha->vp_idx;
  2381. rval2 = qla2x00_get_port_database(vha, new_fcport, 0);
  2382. if (rval2 != QLA_SUCCESS) {
  2383. ql_dbg(ql_dbg_disc, vha, 0x201a,
  2384. "Failed to retrieve fcport information "
  2385. "-- get_port_database=%x, loop_id=0x%04x.\n",
  2386. rval2, new_fcport->loop_id);
  2387. ql_dbg(ql_dbg_disc, vha, 0x201b,
  2388. "Scheduling resync.\n");
  2389. set_bit(LOOP_RESYNC_NEEDED, &vha->dpc_flags);
  2390. continue;
  2391. }
  2392. /* Check for matching device in port list. */
  2393. found = 0;
  2394. fcport = NULL;
  2395. list_for_each_entry(fcport, &vha->vp_fcports, list) {
  2396. if (memcmp(new_fcport->port_name, fcport->port_name,
  2397. WWN_SIZE))
  2398. continue;
  2399. fcport->flags &= ~FCF_FABRIC_DEVICE;
  2400. fcport->loop_id = new_fcport->loop_id;
  2401. fcport->port_type = new_fcport->port_type;
  2402. fcport->d_id.b24 = new_fcport->d_id.b24;
  2403. memcpy(fcport->node_name, new_fcport->node_name,
  2404. WWN_SIZE);
  2405. found++;
  2406. break;
  2407. }
  2408. if (!found) {
  2409. /* New device, add to fcports list. */
  2410. if (vha->vp_idx) {
  2411. new_fcport->vha = vha;
  2412. new_fcport->vp_idx = vha->vp_idx;
  2413. }
  2414. list_add_tail(&new_fcport->list, &vha->vp_fcports);
  2415. /* Allocate a new replacement fcport. */
  2416. fcport = new_fcport;
  2417. new_fcport = qla2x00_alloc_fcport(vha, GFP_KERNEL);
  2418. if (new_fcport == NULL) {
  2419. ql_log(ql_log_warn, vha, 0x201c,
  2420. "Failed to allocate memory for fcport.\n");
  2421. rval = QLA_MEMORY_ALLOC_FAILED;
  2422. goto cleanup_allocation;
  2423. }
  2424. new_fcport->flags &= ~FCF_FABRIC_DEVICE;
  2425. }
  2426. /* Base iIDMA settings on HBA port speed. */
  2427. fcport->fp_speed = ha->link_data_rate;
  2428. qla2x00_update_fcport(vha, fcport);
  2429. found_devs++;
  2430. }
  2431. cleanup_allocation:
  2432. kfree(new_fcport);
  2433. if (rval != QLA_SUCCESS) {
  2434. ql_dbg(ql_dbg_disc, vha, 0x201d,
  2435. "Configure local loop error exit: rval=%x.\n", rval);
  2436. }
  2437. return (rval);
  2438. }
  2439. static void
  2440. qla2x00_iidma_fcport(scsi_qla_host_t *vha, fc_port_t *fcport)
  2441. {
  2442. #define LS_UNKNOWN 2
  2443. static char *link_speeds[] = { "1", "2", "?", "4", "8", "10" };
  2444. char *link_speed;
  2445. int rval;
  2446. uint16_t mb[4];
  2447. struct qla_hw_data *ha = vha->hw;
  2448. if (!IS_IIDMA_CAPABLE(ha))
  2449. return;
  2450. if (atomic_read(&fcport->state) != FCS_ONLINE)
  2451. return;
  2452. if (fcport->fp_speed == PORT_SPEED_UNKNOWN ||
  2453. fcport->fp_speed > ha->link_data_rate)
  2454. return;
  2455. rval = qla2x00_set_idma_speed(vha, fcport->loop_id, fcport->fp_speed,
  2456. mb);
  2457. if (rval != QLA_SUCCESS) {
  2458. ql_dbg(ql_dbg_disc, vha, 0x2004,
  2459. "Unable to adjust iIDMA "
  2460. "%02x%02x%02x%02x%02x%02x%02x%02x -- %04x %x %04x "
  2461. "%04x.\n", fcport->port_name[0], fcport->port_name[1],
  2462. fcport->port_name[2], fcport->port_name[3],
  2463. fcport->port_name[4], fcport->port_name[5],
  2464. fcport->port_name[6], fcport->port_name[7], rval,
  2465. fcport->fp_speed, mb[0], mb[1]);
  2466. } else {
  2467. link_speed = link_speeds[LS_UNKNOWN];
  2468. if (fcport->fp_speed < 5)
  2469. link_speed = link_speeds[fcport->fp_speed];
  2470. else if (fcport->fp_speed == 0x13)
  2471. link_speed = link_speeds[5];
  2472. ql_dbg(ql_dbg_disc, vha, 0x2005,
  2473. "iIDMA adjusted to %s GB/s "
  2474. "on %02x%02x%02x%02x%02x%02x%02x%02x.\n", link_speed,
  2475. fcport->port_name[0], fcport->port_name[1],
  2476. fcport->port_name[2], fcport->port_name[3],
  2477. fcport->port_name[4], fcport->port_name[5],
  2478. fcport->port_name[6], fcport->port_name[7]);
  2479. }
  2480. }
  2481. static void
  2482. qla2x00_reg_remote_port(scsi_qla_host_t *vha, fc_port_t *fcport)
  2483. {
  2484. struct fc_rport_identifiers rport_ids;
  2485. struct fc_rport *rport;
  2486. unsigned long flags;
  2487. qla2x00_rport_del(fcport);
  2488. rport_ids.node_name = wwn_to_u64(fcport->node_name);
  2489. rport_ids.port_name = wwn_to_u64(fcport->port_name);
  2490. rport_ids.port_id = fcport->d_id.b.domain << 16 |
  2491. fcport->d_id.b.area << 8 | fcport->d_id.b.al_pa;
  2492. rport_ids.roles = FC_RPORT_ROLE_UNKNOWN;
  2493. fcport->rport = rport = fc_remote_port_add(vha->host, 0, &rport_ids);
  2494. if (!rport) {
  2495. ql_log(ql_log_warn, vha, 0x2006,
  2496. "Unable to allocate fc remote port.\n");
  2497. return;
  2498. }
  2499. spin_lock_irqsave(fcport->vha->host->host_lock, flags);
  2500. *((fc_port_t **)rport->dd_data) = fcport;
  2501. spin_unlock_irqrestore(fcport->vha->host->host_lock, flags);
  2502. rport->supported_classes = fcport->supported_classes;
  2503. rport_ids.roles = FC_RPORT_ROLE_UNKNOWN;
  2504. if (fcport->port_type == FCT_INITIATOR)
  2505. rport_ids.roles |= FC_RPORT_ROLE_FCP_INITIATOR;
  2506. if (fcport->port_type == FCT_TARGET)
  2507. rport_ids.roles |= FC_RPORT_ROLE_FCP_TARGET;
  2508. fc_remote_port_rolechg(rport, rport_ids.roles);
  2509. }
  2510. /*
  2511. * qla2x00_update_fcport
  2512. * Updates device on list.
  2513. *
  2514. * Input:
  2515. * ha = adapter block pointer.
  2516. * fcport = port structure pointer.
  2517. *
  2518. * Return:
  2519. * 0 - Success
  2520. * BIT_0 - error
  2521. *
  2522. * Context:
  2523. * Kernel context.
  2524. */
  2525. void
  2526. qla2x00_update_fcport(scsi_qla_host_t *vha, fc_port_t *fcport)
  2527. {
  2528. fcport->vha = vha;
  2529. fcport->login_retry = 0;
  2530. fcport->flags &= ~(FCF_LOGIN_NEEDED | FCF_ASYNC_SENT);
  2531. qla2x00_iidma_fcport(vha, fcport);
  2532. qla24xx_update_fcport_fcp_prio(vha, fcport);
  2533. qla2x00_reg_remote_port(vha, fcport);
  2534. qla2x00_set_fcport_state(fcport, FCS_ONLINE);
  2535. }
  2536. /*
  2537. * qla2x00_configure_fabric
  2538. * Setup SNS devices with loop ID's.
  2539. *
  2540. * Input:
  2541. * ha = adapter block pointer.
  2542. *
  2543. * Returns:
  2544. * 0 = success.
  2545. * BIT_0 = error
  2546. */
  2547. static int
  2548. qla2x00_configure_fabric(scsi_qla_host_t *vha)
  2549. {
  2550. int rval, rval2;
  2551. fc_port_t *fcport, *fcptemp;
  2552. uint16_t next_loopid;
  2553. uint16_t mb[MAILBOX_REGISTER_COUNT];
  2554. uint16_t loop_id;
  2555. LIST_HEAD(new_fcports);
  2556. struct qla_hw_data *ha = vha->hw;
  2557. struct scsi_qla_host *base_vha = pci_get_drvdata(ha->pdev);
  2558. /* If FL port exists, then SNS is present */
  2559. if (IS_FWI2_CAPABLE(ha))
  2560. loop_id = NPH_F_PORT;
  2561. else
  2562. loop_id = SNS_FL_PORT;
  2563. rval = qla2x00_get_port_name(vha, loop_id, vha->fabric_node_name, 1);
  2564. if (rval != QLA_SUCCESS) {
  2565. ql_dbg(ql_dbg_disc, vha, 0x201f,
  2566. "MBX_GET_PORT_NAME failed, No FL Port.\n");
  2567. vha->device_flags &= ~SWITCH_FOUND;
  2568. return (QLA_SUCCESS);
  2569. }
  2570. vha->device_flags |= SWITCH_FOUND;
  2571. /* Mark devices that need re-synchronization. */
  2572. rval2 = qla2x00_device_resync(vha);
  2573. if (rval2 == QLA_RSCNS_HANDLED) {
  2574. /* No point doing the scan, just continue. */
  2575. return (QLA_SUCCESS);
  2576. }
  2577. do {
  2578. /* FDMI support. */
  2579. if (ql2xfdmienable &&
  2580. test_and_clear_bit(REGISTER_FDMI_NEEDED, &vha->dpc_flags))
  2581. qla2x00_fdmi_register(vha);
  2582. /* Ensure we are logged into the SNS. */
  2583. if (IS_FWI2_CAPABLE(ha))
  2584. loop_id = NPH_SNS;
  2585. else
  2586. loop_id = SIMPLE_NAME_SERVER;
  2587. ha->isp_ops->fabric_login(vha, loop_id, 0xff, 0xff,
  2588. 0xfc, mb, BIT_1 | BIT_0);
  2589. if (mb[0] != MBS_COMMAND_COMPLETE) {
  2590. ql_dbg(ql_dbg_disc, vha, 0x2042,
  2591. "Failed SNS login: loop_id=%x mb[0]=%x mb[1]=%x mb[2]=%x "
  2592. "mb[6]=%x mb[7]=%x.\n", loop_id, mb[0], mb[1],
  2593. mb[2], mb[6], mb[7]);
  2594. return (QLA_SUCCESS);
  2595. }
  2596. if (test_and_clear_bit(REGISTER_FC4_NEEDED, &vha->dpc_flags)) {
  2597. if (qla2x00_rft_id(vha)) {
  2598. /* EMPTY */
  2599. ql_dbg(ql_dbg_disc, vha, 0x2045,
  2600. "Register FC-4 TYPE failed.\n");
  2601. }
  2602. if (qla2x00_rff_id(vha)) {
  2603. /* EMPTY */
  2604. ql_dbg(ql_dbg_disc, vha, 0x2049,
  2605. "Register FC-4 Features failed.\n");
  2606. }
  2607. if (qla2x00_rnn_id(vha)) {
  2608. /* EMPTY */
  2609. ql_dbg(ql_dbg_disc, vha, 0x204f,
  2610. "Register Node Name failed.\n");
  2611. } else if (qla2x00_rsnn_nn(vha)) {
  2612. /* EMPTY */
  2613. ql_dbg(ql_dbg_disc, vha, 0x2053,
  2614. "Register Symobilic Node Name failed.\n");
  2615. }
  2616. }
  2617. rval = qla2x00_find_all_fabric_devs(vha, &new_fcports);
  2618. if (rval != QLA_SUCCESS)
  2619. break;
  2620. /*
  2621. * Logout all previous fabric devices marked lost, except
  2622. * FCP2 devices.
  2623. */
  2624. list_for_each_entry(fcport, &vha->vp_fcports, list) {
  2625. if (test_bit(LOOP_RESYNC_NEEDED, &vha->dpc_flags))
  2626. break;
  2627. if ((fcport->flags & FCF_FABRIC_DEVICE) == 0)
  2628. continue;
  2629. if (atomic_read(&fcport->state) == FCS_DEVICE_LOST) {
  2630. qla2x00_mark_device_lost(vha, fcport,
  2631. ql2xplogiabsentdevice, 0);
  2632. if (fcport->loop_id != FC_NO_LOOP_ID &&
  2633. (fcport->flags & FCF_FCP2_DEVICE) == 0 &&
  2634. fcport->port_type != FCT_INITIATOR &&
  2635. fcport->port_type != FCT_BROADCAST) {
  2636. ha->isp_ops->fabric_logout(vha,
  2637. fcport->loop_id,
  2638. fcport->d_id.b.domain,
  2639. fcport->d_id.b.area,
  2640. fcport->d_id.b.al_pa);
  2641. fcport->loop_id = FC_NO_LOOP_ID;
  2642. }
  2643. }
  2644. }
  2645. /* Starting free loop ID. */
  2646. next_loopid = ha->min_external_loopid;
  2647. /*
  2648. * Scan through our port list and login entries that need to be
  2649. * logged in.
  2650. */
  2651. list_for_each_entry(fcport, &vha->vp_fcports, list) {
  2652. if (atomic_read(&vha->loop_down_timer) ||
  2653. test_bit(LOOP_RESYNC_NEEDED, &vha->dpc_flags))
  2654. break;
  2655. if ((fcport->flags & FCF_FABRIC_DEVICE) == 0 ||
  2656. (fcport->flags & FCF_LOGIN_NEEDED) == 0)
  2657. continue;
  2658. if (fcport->loop_id == FC_NO_LOOP_ID) {
  2659. fcport->loop_id = next_loopid;
  2660. rval = qla2x00_find_new_loop_id(
  2661. base_vha, fcport);
  2662. if (rval != QLA_SUCCESS) {
  2663. /* Ran out of IDs to use */
  2664. break;
  2665. }
  2666. }
  2667. /* Login and update database */
  2668. qla2x00_fabric_dev_login(vha, fcport, &next_loopid);
  2669. }
  2670. /* Exit if out of loop IDs. */
  2671. if (rval != QLA_SUCCESS) {
  2672. break;
  2673. }
  2674. /*
  2675. * Login and add the new devices to our port list.
  2676. */
  2677. list_for_each_entry_safe(fcport, fcptemp, &new_fcports, list) {
  2678. if (atomic_read(&vha->loop_down_timer) ||
  2679. test_bit(LOOP_RESYNC_NEEDED, &vha->dpc_flags))
  2680. break;
  2681. /* Find a new loop ID to use. */
  2682. fcport->loop_id = next_loopid;
  2683. rval = qla2x00_find_new_loop_id(base_vha, fcport);
  2684. if (rval != QLA_SUCCESS) {
  2685. /* Ran out of IDs to use */
  2686. break;
  2687. }
  2688. /* Login and update database */
  2689. qla2x00_fabric_dev_login(vha, fcport, &next_loopid);
  2690. if (vha->vp_idx) {
  2691. fcport->vha = vha;
  2692. fcport->vp_idx = vha->vp_idx;
  2693. }
  2694. list_move_tail(&fcport->list, &vha->vp_fcports);
  2695. }
  2696. } while (0);
  2697. /* Free all new device structures not processed. */
  2698. list_for_each_entry_safe(fcport, fcptemp, &new_fcports, list) {
  2699. list_del(&fcport->list);
  2700. kfree(fcport);
  2701. }
  2702. if (rval) {
  2703. ql_dbg(ql_dbg_disc, vha, 0x2068,
  2704. "Configure fabric error exit rval=%d.\n", rval);
  2705. }
  2706. return (rval);
  2707. }
  2708. /*
  2709. * qla2x00_find_all_fabric_devs
  2710. *
  2711. * Input:
  2712. * ha = adapter block pointer.
  2713. * dev = database device entry pointer.
  2714. *
  2715. * Returns:
  2716. * 0 = success.
  2717. *
  2718. * Context:
  2719. * Kernel context.
  2720. */
  2721. static int
  2722. qla2x00_find_all_fabric_devs(scsi_qla_host_t *vha,
  2723. struct list_head *new_fcports)
  2724. {
  2725. int rval;
  2726. uint16_t loop_id;
  2727. fc_port_t *fcport, *new_fcport, *fcptemp;
  2728. int found;
  2729. sw_info_t *swl;
  2730. int swl_idx;
  2731. int first_dev, last_dev;
  2732. port_id_t wrap = {}, nxt_d_id;
  2733. struct qla_hw_data *ha = vha->hw;
  2734. struct scsi_qla_host *vp, *base_vha = pci_get_drvdata(ha->pdev);
  2735. struct scsi_qla_host *tvp;
  2736. rval = QLA_SUCCESS;
  2737. /* Try GID_PT to get device list, else GAN. */
  2738. swl = kcalloc(MAX_FIBRE_DEVICES, sizeof(sw_info_t), GFP_KERNEL);
  2739. if (!swl) {
  2740. /*EMPTY*/
  2741. ql_dbg(ql_dbg_disc, vha, 0x2054,
  2742. "GID_PT allocations failed, fallback on GA_NXT.\n");
  2743. } else {
  2744. if (qla2x00_gid_pt(vha, swl) != QLA_SUCCESS) {
  2745. kfree(swl);
  2746. swl = NULL;
  2747. } else if (qla2x00_gpn_id(vha, swl) != QLA_SUCCESS) {
  2748. kfree(swl);
  2749. swl = NULL;
  2750. } else if (qla2x00_gnn_id(vha, swl) != QLA_SUCCESS) {
  2751. kfree(swl);
  2752. swl = NULL;
  2753. } else if (ql2xiidmaenable &&
  2754. qla2x00_gfpn_id(vha, swl) == QLA_SUCCESS) {
  2755. qla2x00_gpsc(vha, swl);
  2756. }
  2757. /* If other queries succeeded probe for FC-4 type */
  2758. if (swl)
  2759. qla2x00_gff_id(vha, swl);
  2760. }
  2761. swl_idx = 0;
  2762. /* Allocate temporary fcport for any new fcports discovered. */
  2763. new_fcport = qla2x00_alloc_fcport(vha, GFP_KERNEL);
  2764. if (new_fcport == NULL) {
  2765. ql_log(ql_log_warn, vha, 0x205e,
  2766. "Failed to allocate memory for fcport.\n");
  2767. kfree(swl);
  2768. return (QLA_MEMORY_ALLOC_FAILED);
  2769. }
  2770. new_fcport->flags |= (FCF_FABRIC_DEVICE | FCF_LOGIN_NEEDED);
  2771. /* Set start port ID scan at adapter ID. */
  2772. first_dev = 1;
  2773. last_dev = 0;
  2774. /* Starting free loop ID. */
  2775. loop_id = ha->min_external_loopid;
  2776. for (; loop_id <= ha->max_loop_id; loop_id++) {
  2777. if (qla2x00_is_reserved_id(vha, loop_id))
  2778. continue;
  2779. if (ha->current_topology == ISP_CFG_FL &&
  2780. (atomic_read(&vha->loop_down_timer) ||
  2781. LOOP_TRANSITION(vha))) {
  2782. atomic_set(&vha->loop_down_timer, 0);
  2783. set_bit(LOOP_RESYNC_NEEDED, &vha->dpc_flags);
  2784. set_bit(LOCAL_LOOP_UPDATE, &vha->dpc_flags);
  2785. break;
  2786. }
  2787. if (swl != NULL) {
  2788. if (last_dev) {
  2789. wrap.b24 = new_fcport->d_id.b24;
  2790. } else {
  2791. new_fcport->d_id.b24 = swl[swl_idx].d_id.b24;
  2792. memcpy(new_fcport->node_name,
  2793. swl[swl_idx].node_name, WWN_SIZE);
  2794. memcpy(new_fcport->port_name,
  2795. swl[swl_idx].port_name, WWN_SIZE);
  2796. memcpy(new_fcport->fabric_port_name,
  2797. swl[swl_idx].fabric_port_name, WWN_SIZE);
  2798. new_fcport->fp_speed = swl[swl_idx].fp_speed;
  2799. new_fcport->fc4_type = swl[swl_idx].fc4_type;
  2800. if (swl[swl_idx].d_id.b.rsvd_1 != 0) {
  2801. last_dev = 1;
  2802. }
  2803. swl_idx++;
  2804. }
  2805. } else {
  2806. /* Send GA_NXT to the switch */
  2807. rval = qla2x00_ga_nxt(vha, new_fcport);
  2808. if (rval != QLA_SUCCESS) {
  2809. ql_log(ql_log_warn, vha, 0x2064,
  2810. "SNS scan failed -- assuming "
  2811. "zero-entry result.\n");
  2812. list_for_each_entry_safe(fcport, fcptemp,
  2813. new_fcports, list) {
  2814. list_del(&fcport->list);
  2815. kfree(fcport);
  2816. }
  2817. rval = QLA_SUCCESS;
  2818. break;
  2819. }
  2820. }
  2821. /* If wrap on switch device list, exit. */
  2822. if (first_dev) {
  2823. wrap.b24 = new_fcport->d_id.b24;
  2824. first_dev = 0;
  2825. } else if (new_fcport->d_id.b24 == wrap.b24) {
  2826. ql_dbg(ql_dbg_disc, vha, 0x2065,
  2827. "Device wrap (%02x%02x%02x).\n",
  2828. new_fcport->d_id.b.domain,
  2829. new_fcport->d_id.b.area,
  2830. new_fcport->d_id.b.al_pa);
  2831. break;
  2832. }
  2833. /* Bypass if same physical adapter. */
  2834. if (new_fcport->d_id.b24 == base_vha->d_id.b24)
  2835. continue;
  2836. /* Bypass virtual ports of the same host. */
  2837. found = 0;
  2838. if (ha->num_vhosts) {
  2839. unsigned long flags;
  2840. spin_lock_irqsave(&ha->vport_slock, flags);
  2841. list_for_each_entry_safe(vp, tvp, &ha->vp_list, list) {
  2842. if (new_fcport->d_id.b24 == vp->d_id.b24) {
  2843. found = 1;
  2844. break;
  2845. }
  2846. }
  2847. spin_unlock_irqrestore(&ha->vport_slock, flags);
  2848. if (found)
  2849. continue;
  2850. }
  2851. /* Bypass if same domain and area of adapter. */
  2852. if (((new_fcport->d_id.b24 & 0xffff00) ==
  2853. (vha->d_id.b24 & 0xffff00)) && ha->current_topology ==
  2854. ISP_CFG_FL)
  2855. continue;
  2856. /* Bypass reserved domain fields. */
  2857. if ((new_fcport->d_id.b.domain & 0xf0) == 0xf0)
  2858. continue;
  2859. /* Bypass ports whose FCP-4 type is not FCP_SCSI */
  2860. if (ql2xgffidenable &&
  2861. (new_fcport->fc4_type != FC4_TYPE_FCP_SCSI &&
  2862. new_fcport->fc4_type != FC4_TYPE_UNKNOWN))
  2863. continue;
  2864. /* Locate matching device in database. */
  2865. found = 0;
  2866. list_for_each_entry(fcport, &vha->vp_fcports, list) {
  2867. if (memcmp(new_fcport->port_name, fcport->port_name,
  2868. WWN_SIZE))
  2869. continue;
  2870. found++;
  2871. /* Update port state. */
  2872. memcpy(fcport->fabric_port_name,
  2873. new_fcport->fabric_port_name, WWN_SIZE);
  2874. fcport->fp_speed = new_fcport->fp_speed;
  2875. /*
  2876. * If address the same and state FCS_ONLINE, nothing
  2877. * changed.
  2878. */
  2879. if (fcport->d_id.b24 == new_fcport->d_id.b24 &&
  2880. atomic_read(&fcport->state) == FCS_ONLINE) {
  2881. break;
  2882. }
  2883. /*
  2884. * If device was not a fabric device before.
  2885. */
  2886. if ((fcport->flags & FCF_FABRIC_DEVICE) == 0) {
  2887. fcport->d_id.b24 = new_fcport->d_id.b24;
  2888. fcport->loop_id = FC_NO_LOOP_ID;
  2889. fcport->flags |= (FCF_FABRIC_DEVICE |
  2890. FCF_LOGIN_NEEDED);
  2891. break;
  2892. }
  2893. /*
  2894. * Port ID changed or device was marked to be updated;
  2895. * Log it out if still logged in and mark it for
  2896. * relogin later.
  2897. */
  2898. fcport->d_id.b24 = new_fcport->d_id.b24;
  2899. fcport->flags |= FCF_LOGIN_NEEDED;
  2900. if (fcport->loop_id != FC_NO_LOOP_ID &&
  2901. (fcport->flags & FCF_FCP2_DEVICE) == 0 &&
  2902. fcport->port_type != FCT_INITIATOR &&
  2903. fcport->port_type != FCT_BROADCAST) {
  2904. ha->isp_ops->fabric_logout(vha, fcport->loop_id,
  2905. fcport->d_id.b.domain, fcport->d_id.b.area,
  2906. fcport->d_id.b.al_pa);
  2907. fcport->loop_id = FC_NO_LOOP_ID;
  2908. }
  2909. break;
  2910. }
  2911. if (found)
  2912. continue;
  2913. /* If device was not in our fcports list, then add it. */
  2914. list_add_tail(&new_fcport->list, new_fcports);
  2915. /* Allocate a new replacement fcport. */
  2916. nxt_d_id.b24 = new_fcport->d_id.b24;
  2917. new_fcport = qla2x00_alloc_fcport(vha, GFP_KERNEL);
  2918. if (new_fcport == NULL) {
  2919. ql_log(ql_log_warn, vha, 0x2066,
  2920. "Memory allocation failed for fcport.\n");
  2921. kfree(swl);
  2922. return (QLA_MEMORY_ALLOC_FAILED);
  2923. }
  2924. new_fcport->flags |= (FCF_FABRIC_DEVICE | FCF_LOGIN_NEEDED);
  2925. new_fcport->d_id.b24 = nxt_d_id.b24;
  2926. }
  2927. kfree(swl);
  2928. kfree(new_fcport);
  2929. return (rval);
  2930. }
  2931. /*
  2932. * qla2x00_find_new_loop_id
  2933. * Scan through our port list and find a new usable loop ID.
  2934. *
  2935. * Input:
  2936. * ha: adapter state pointer.
  2937. * dev: port structure pointer.
  2938. *
  2939. * Returns:
  2940. * qla2x00 local function return status code.
  2941. *
  2942. * Context:
  2943. * Kernel context.
  2944. */
  2945. int
  2946. qla2x00_find_new_loop_id(scsi_qla_host_t *vha, fc_port_t *dev)
  2947. {
  2948. int rval;
  2949. int found;
  2950. fc_port_t *fcport;
  2951. uint16_t first_loop_id;
  2952. struct qla_hw_data *ha = vha->hw;
  2953. struct scsi_qla_host *vp;
  2954. struct scsi_qla_host *tvp;
  2955. unsigned long flags = 0;
  2956. rval = QLA_SUCCESS;
  2957. /* Save starting loop ID. */
  2958. first_loop_id = dev->loop_id;
  2959. for (;;) {
  2960. /* Skip loop ID if already used by adapter. */
  2961. if (dev->loop_id == vha->loop_id)
  2962. dev->loop_id++;
  2963. /* Skip reserved loop IDs. */
  2964. while (qla2x00_is_reserved_id(vha, dev->loop_id))
  2965. dev->loop_id++;
  2966. /* Reset loop ID if passed the end. */
  2967. if (dev->loop_id > ha->max_loop_id) {
  2968. /* first loop ID. */
  2969. dev->loop_id = ha->min_external_loopid;
  2970. }
  2971. /* Check for loop ID being already in use. */
  2972. found = 0;
  2973. fcport = NULL;
  2974. spin_lock_irqsave(&ha->vport_slock, flags);
  2975. list_for_each_entry_safe(vp, tvp, &ha->vp_list, list) {
  2976. list_for_each_entry(fcport, &vp->vp_fcports, list) {
  2977. if (fcport->loop_id == dev->loop_id &&
  2978. fcport != dev) {
  2979. /* ID possibly in use */
  2980. found++;
  2981. break;
  2982. }
  2983. }
  2984. if (found)
  2985. break;
  2986. }
  2987. spin_unlock_irqrestore(&ha->vport_slock, flags);
  2988. /* If not in use then it is free to use. */
  2989. if (!found) {
  2990. break;
  2991. }
  2992. /* ID in use. Try next value. */
  2993. dev->loop_id++;
  2994. /* If wrap around. No free ID to use. */
  2995. if (dev->loop_id == first_loop_id) {
  2996. dev->loop_id = FC_NO_LOOP_ID;
  2997. rval = QLA_FUNCTION_FAILED;
  2998. break;
  2999. }
  3000. }
  3001. return (rval);
  3002. }
  3003. /*
  3004. * qla2x00_device_resync
  3005. * Marks devices in the database that needs resynchronization.
  3006. *
  3007. * Input:
  3008. * ha = adapter block pointer.
  3009. *
  3010. * Context:
  3011. * Kernel context.
  3012. */
  3013. static int
  3014. qla2x00_device_resync(scsi_qla_host_t *vha)
  3015. {
  3016. int rval;
  3017. uint32_t mask;
  3018. fc_port_t *fcport;
  3019. uint32_t rscn_entry;
  3020. uint8_t rscn_out_iter;
  3021. uint8_t format;
  3022. port_id_t d_id = {};
  3023. rval = QLA_RSCNS_HANDLED;
  3024. while (vha->rscn_out_ptr != vha->rscn_in_ptr ||
  3025. vha->flags.rscn_queue_overflow) {
  3026. rscn_entry = vha->rscn_queue[vha->rscn_out_ptr];
  3027. format = MSB(MSW(rscn_entry));
  3028. d_id.b.domain = LSB(MSW(rscn_entry));
  3029. d_id.b.area = MSB(LSW(rscn_entry));
  3030. d_id.b.al_pa = LSB(LSW(rscn_entry));
  3031. ql_dbg(ql_dbg_disc, vha, 0x2020,
  3032. "RSCN queue entry[%d] = [%02x/%02x%02x%02x].\n",
  3033. vha->rscn_out_ptr, format, d_id.b.domain, d_id.b.area,
  3034. d_id.b.al_pa);
  3035. vha->rscn_out_ptr++;
  3036. if (vha->rscn_out_ptr == MAX_RSCN_COUNT)
  3037. vha->rscn_out_ptr = 0;
  3038. /* Skip duplicate entries. */
  3039. for (rscn_out_iter = vha->rscn_out_ptr;
  3040. !vha->flags.rscn_queue_overflow &&
  3041. rscn_out_iter != vha->rscn_in_ptr;
  3042. rscn_out_iter = (rscn_out_iter ==
  3043. (MAX_RSCN_COUNT - 1)) ? 0: rscn_out_iter + 1) {
  3044. if (rscn_entry != vha->rscn_queue[rscn_out_iter])
  3045. break;
  3046. ql_dbg(ql_dbg_disc, vha, 0x2021,
  3047. "Skipping duplicate RSCN queue entry found at "
  3048. "[%d].\n", rscn_out_iter);
  3049. vha->rscn_out_ptr = rscn_out_iter;
  3050. }
  3051. /* Queue overflow, set switch default case. */
  3052. if (vha->flags.rscn_queue_overflow) {
  3053. ql_dbg(ql_dbg_disc, vha, 0x2022,
  3054. "device_resync: rscn overflow.\n");
  3055. format = 3;
  3056. vha->flags.rscn_queue_overflow = 0;
  3057. }
  3058. switch (format) {
  3059. case 0:
  3060. mask = 0xffffff;
  3061. break;
  3062. case 1:
  3063. mask = 0xffff00;
  3064. break;
  3065. case 2:
  3066. mask = 0xff0000;
  3067. break;
  3068. default:
  3069. mask = 0x0;
  3070. d_id.b24 = 0;
  3071. vha->rscn_out_ptr = vha->rscn_in_ptr;
  3072. break;
  3073. }
  3074. rval = QLA_SUCCESS;
  3075. list_for_each_entry(fcport, &vha->vp_fcports, list) {
  3076. if ((fcport->flags & FCF_FABRIC_DEVICE) == 0 ||
  3077. (fcport->d_id.b24 & mask) != d_id.b24 ||
  3078. fcport->port_type == FCT_BROADCAST)
  3079. continue;
  3080. if (atomic_read(&fcport->state) == FCS_ONLINE) {
  3081. if (format != 3 ||
  3082. fcport->port_type != FCT_INITIATOR) {
  3083. qla2x00_mark_device_lost(vha, fcport,
  3084. 0, 0);
  3085. }
  3086. }
  3087. }
  3088. }
  3089. return (rval);
  3090. }
  3091. /*
  3092. * qla2x00_fabric_dev_login
  3093. * Login fabric target device and update FC port database.
  3094. *
  3095. * Input:
  3096. * ha: adapter state pointer.
  3097. * fcport: port structure list pointer.
  3098. * next_loopid: contains value of a new loop ID that can be used
  3099. * by the next login attempt.
  3100. *
  3101. * Returns:
  3102. * qla2x00 local function return status code.
  3103. *
  3104. * Context:
  3105. * Kernel context.
  3106. */
  3107. static int
  3108. qla2x00_fabric_dev_login(scsi_qla_host_t *vha, fc_port_t *fcport,
  3109. uint16_t *next_loopid)
  3110. {
  3111. int rval;
  3112. int retry;
  3113. uint8_t opts;
  3114. struct qla_hw_data *ha = vha->hw;
  3115. rval = QLA_SUCCESS;
  3116. retry = 0;
  3117. if (IS_ALOGIO_CAPABLE(ha)) {
  3118. if (fcport->flags & FCF_ASYNC_SENT)
  3119. return rval;
  3120. fcport->flags |= FCF_ASYNC_SENT;
  3121. rval = qla2x00_post_async_login_work(vha, fcport, NULL);
  3122. if (!rval)
  3123. return rval;
  3124. }
  3125. fcport->flags &= ~FCF_ASYNC_SENT;
  3126. rval = qla2x00_fabric_login(vha, fcport, next_loopid);
  3127. if (rval == QLA_SUCCESS) {
  3128. /* Send an ADISC to FCP2 devices.*/
  3129. opts = 0;
  3130. if (fcport->flags & FCF_FCP2_DEVICE)
  3131. opts |= BIT_1;
  3132. rval = qla2x00_get_port_database(vha, fcport, opts);
  3133. if (rval != QLA_SUCCESS) {
  3134. ha->isp_ops->fabric_logout(vha, fcport->loop_id,
  3135. fcport->d_id.b.domain, fcport->d_id.b.area,
  3136. fcport->d_id.b.al_pa);
  3137. qla2x00_mark_device_lost(vha, fcport, 1, 0);
  3138. } else {
  3139. qla2x00_update_fcport(vha, fcport);
  3140. }
  3141. }
  3142. return (rval);
  3143. }
  3144. /*
  3145. * qla2x00_fabric_login
  3146. * Issue fabric login command.
  3147. *
  3148. * Input:
  3149. * ha = adapter block pointer.
  3150. * device = pointer to FC device type structure.
  3151. *
  3152. * Returns:
  3153. * 0 - Login successfully
  3154. * 1 - Login failed
  3155. * 2 - Initiator device
  3156. * 3 - Fatal error
  3157. */
  3158. int
  3159. qla2x00_fabric_login(scsi_qla_host_t *vha, fc_port_t *fcport,
  3160. uint16_t *next_loopid)
  3161. {
  3162. int rval;
  3163. int retry;
  3164. uint16_t tmp_loopid;
  3165. uint16_t mb[MAILBOX_REGISTER_COUNT];
  3166. struct qla_hw_data *ha = vha->hw;
  3167. retry = 0;
  3168. tmp_loopid = 0;
  3169. for (;;) {
  3170. ql_dbg(ql_dbg_disc, vha, 0x2000,
  3171. "Trying Fabric Login w/loop id 0x%04x for port "
  3172. "%02x%02x%02x.\n",
  3173. fcport->loop_id, fcport->d_id.b.domain,
  3174. fcport->d_id.b.area, fcport->d_id.b.al_pa);
  3175. /* Login fcport on switch. */
  3176. ha->isp_ops->fabric_login(vha, fcport->loop_id,
  3177. fcport->d_id.b.domain, fcport->d_id.b.area,
  3178. fcport->d_id.b.al_pa, mb, BIT_0);
  3179. if (mb[0] == MBS_PORT_ID_USED) {
  3180. /*
  3181. * Device has another loop ID. The firmware team
  3182. * recommends the driver perform an implicit login with
  3183. * the specified ID again. The ID we just used is save
  3184. * here so we return with an ID that can be tried by
  3185. * the next login.
  3186. */
  3187. retry++;
  3188. tmp_loopid = fcport->loop_id;
  3189. fcport->loop_id = mb[1];
  3190. ql_dbg(ql_dbg_disc, vha, 0x2001,
  3191. "Fabric Login: port in use - next loop "
  3192. "id=0x%04x, port id= %02x%02x%02x.\n",
  3193. fcport->loop_id, fcport->d_id.b.domain,
  3194. fcport->d_id.b.area, fcport->d_id.b.al_pa);
  3195. } else if (mb[0] == MBS_COMMAND_COMPLETE) {
  3196. /*
  3197. * Login succeeded.
  3198. */
  3199. if (retry) {
  3200. /* A retry occurred before. */
  3201. *next_loopid = tmp_loopid;
  3202. } else {
  3203. /*
  3204. * No retry occurred before. Just increment the
  3205. * ID value for next login.
  3206. */
  3207. *next_loopid = (fcport->loop_id + 1);
  3208. }
  3209. if (mb[1] & BIT_0) {
  3210. fcport->port_type = FCT_INITIATOR;
  3211. } else {
  3212. fcport->port_type = FCT_TARGET;
  3213. if (mb[1] & BIT_1) {
  3214. fcport->flags |= FCF_FCP2_DEVICE;
  3215. }
  3216. }
  3217. if (mb[10] & BIT_0)
  3218. fcport->supported_classes |= FC_COS_CLASS2;
  3219. if (mb[10] & BIT_1)
  3220. fcport->supported_classes |= FC_COS_CLASS3;
  3221. rval = QLA_SUCCESS;
  3222. break;
  3223. } else if (mb[0] == MBS_LOOP_ID_USED) {
  3224. /*
  3225. * Loop ID already used, try next loop ID.
  3226. */
  3227. fcport->loop_id++;
  3228. rval = qla2x00_find_new_loop_id(vha, fcport);
  3229. if (rval != QLA_SUCCESS) {
  3230. /* Ran out of loop IDs to use */
  3231. break;
  3232. }
  3233. } else if (mb[0] == MBS_COMMAND_ERROR) {
  3234. /*
  3235. * Firmware possibly timed out during login. If NO
  3236. * retries are left to do then the device is declared
  3237. * dead.
  3238. */
  3239. *next_loopid = fcport->loop_id;
  3240. ha->isp_ops->fabric_logout(vha, fcport->loop_id,
  3241. fcport->d_id.b.domain, fcport->d_id.b.area,
  3242. fcport->d_id.b.al_pa);
  3243. qla2x00_mark_device_lost(vha, fcport, 1, 0);
  3244. rval = 1;
  3245. break;
  3246. } else {
  3247. /*
  3248. * unrecoverable / not handled error
  3249. */
  3250. ql_dbg(ql_dbg_disc, vha, 0x2002,
  3251. "Failed=%x port_id=%02x%02x%02x loop_id=%x "
  3252. "jiffies=%lx.\n", mb[0], fcport->d_id.b.domain,
  3253. fcport->d_id.b.area, fcport->d_id.b.al_pa,
  3254. fcport->loop_id, jiffies);
  3255. *next_loopid = fcport->loop_id;
  3256. ha->isp_ops->fabric_logout(vha, fcport->loop_id,
  3257. fcport->d_id.b.domain, fcport->d_id.b.area,
  3258. fcport->d_id.b.al_pa);
  3259. fcport->loop_id = FC_NO_LOOP_ID;
  3260. fcport->login_retry = 0;
  3261. rval = 3;
  3262. break;
  3263. }
  3264. }
  3265. return (rval);
  3266. }
  3267. /*
  3268. * qla2x00_local_device_login
  3269. * Issue local device login command.
  3270. *
  3271. * Input:
  3272. * ha = adapter block pointer.
  3273. * loop_id = loop id of device to login to.
  3274. *
  3275. * Returns (Where's the #define!!!!):
  3276. * 0 - Login successfully
  3277. * 1 - Login failed
  3278. * 3 - Fatal error
  3279. */
  3280. int
  3281. qla2x00_local_device_login(scsi_qla_host_t *vha, fc_port_t *fcport)
  3282. {
  3283. int rval;
  3284. uint16_t mb[MAILBOX_REGISTER_COUNT];
  3285. memset(mb, 0, sizeof(mb));
  3286. rval = qla2x00_login_local_device(vha, fcport, mb, BIT_0);
  3287. if (rval == QLA_SUCCESS) {
  3288. /* Interrogate mailbox registers for any errors */
  3289. if (mb[0] == MBS_COMMAND_ERROR)
  3290. rval = 1;
  3291. else if (mb[0] == MBS_COMMAND_PARAMETER_ERROR)
  3292. /* device not in PCB table */
  3293. rval = 3;
  3294. }
  3295. return (rval);
  3296. }
  3297. /*
  3298. * qla2x00_loop_resync
  3299. * Resync with fibre channel devices.
  3300. *
  3301. * Input:
  3302. * ha = adapter block pointer.
  3303. *
  3304. * Returns:
  3305. * 0 = success
  3306. */
  3307. int
  3308. qla2x00_loop_resync(scsi_qla_host_t *vha)
  3309. {
  3310. int rval = QLA_SUCCESS;
  3311. uint32_t wait_time;
  3312. struct req_que *req;
  3313. struct rsp_que *rsp;
  3314. if (vha->hw->flags.cpu_affinity_enabled)
  3315. req = vha->hw->req_q_map[0];
  3316. else
  3317. req = vha->req;
  3318. rsp = req->rsp;
  3319. clear_bit(ISP_ABORT_RETRY, &vha->dpc_flags);
  3320. if (vha->flags.online) {
  3321. if (!(rval = qla2x00_fw_ready(vha))) {
  3322. /* Wait at most MAX_TARGET RSCNs for a stable link. */
  3323. wait_time = 256;
  3324. do {
  3325. /* Issue a marker after FW becomes ready. */
  3326. qla2x00_marker(vha, req, rsp, 0, 0,
  3327. MK_SYNC_ALL);
  3328. vha->marker_needed = 0;
  3329. /* Remap devices on Loop. */
  3330. clear_bit(LOOP_RESYNC_NEEDED, &vha->dpc_flags);
  3331. qla2x00_configure_loop(vha);
  3332. wait_time--;
  3333. } while (!atomic_read(&vha->loop_down_timer) &&
  3334. !(test_bit(ISP_ABORT_NEEDED, &vha->dpc_flags))
  3335. && wait_time && (test_bit(LOOP_RESYNC_NEEDED,
  3336. &vha->dpc_flags)));
  3337. }
  3338. }
  3339. if (test_bit(ISP_ABORT_NEEDED, &vha->dpc_flags))
  3340. return (QLA_FUNCTION_FAILED);
  3341. if (rval)
  3342. ql_dbg(ql_dbg_disc, vha, 0x206c,
  3343. "%s *** FAILED ***.\n", __func__);
  3344. return (rval);
  3345. }
  3346. /*
  3347. * qla2x00_perform_loop_resync
  3348. * Description: This function will set the appropriate flags and call
  3349. * qla2x00_loop_resync. If successful loop will be resynced
  3350. * Arguments : scsi_qla_host_t pointer
  3351. * returm : Success or Failure
  3352. */
  3353. int qla2x00_perform_loop_resync(scsi_qla_host_t *ha)
  3354. {
  3355. int32_t rval = 0;
  3356. if (!test_and_set_bit(LOOP_RESYNC_ACTIVE, &ha->dpc_flags)) {
  3357. /*Configure the flags so that resync happens properly*/
  3358. atomic_set(&ha->loop_down_timer, 0);
  3359. if (!(ha->device_flags & DFLG_NO_CABLE)) {
  3360. atomic_set(&ha->loop_state, LOOP_UP);
  3361. set_bit(LOCAL_LOOP_UPDATE, &ha->dpc_flags);
  3362. set_bit(REGISTER_FC4_NEEDED, &ha->dpc_flags);
  3363. set_bit(LOOP_RESYNC_NEEDED, &ha->dpc_flags);
  3364. rval = qla2x00_loop_resync(ha);
  3365. } else
  3366. atomic_set(&ha->loop_state, LOOP_DEAD);
  3367. clear_bit(LOOP_RESYNC_ACTIVE, &ha->dpc_flags);
  3368. }
  3369. return rval;
  3370. }
  3371. void
  3372. qla2x00_update_fcports(scsi_qla_host_t *base_vha)
  3373. {
  3374. fc_port_t *fcport;
  3375. struct scsi_qla_host *vha;
  3376. struct qla_hw_data *ha = base_vha->hw;
  3377. unsigned long flags;
  3378. spin_lock_irqsave(&ha->vport_slock, flags);
  3379. /* Go with deferred removal of rport references. */
  3380. list_for_each_entry(vha, &base_vha->hw->vp_list, list) {
  3381. atomic_inc(&vha->vref_count);
  3382. list_for_each_entry(fcport, &vha->vp_fcports, list) {
  3383. if (fcport->drport &&
  3384. atomic_read(&fcport->state) != FCS_UNCONFIGURED) {
  3385. spin_unlock_irqrestore(&ha->vport_slock, flags);
  3386. qla2x00_rport_del(fcport);
  3387. spin_lock_irqsave(&ha->vport_slock, flags);
  3388. }
  3389. }
  3390. atomic_dec(&vha->vref_count);
  3391. }
  3392. spin_unlock_irqrestore(&ha->vport_slock, flags);
  3393. }
  3394. /*
  3395. * qla82xx_quiescent_state_cleanup
  3396. * Description: This function will block the new I/Os
  3397. * Its not aborting any I/Os as context
  3398. * is not destroyed during quiescence
  3399. * Arguments: scsi_qla_host_t
  3400. * return : void
  3401. */
  3402. void
  3403. qla82xx_quiescent_state_cleanup(scsi_qla_host_t *vha)
  3404. {
  3405. struct qla_hw_data *ha = vha->hw;
  3406. struct scsi_qla_host *vp;
  3407. ql_dbg(ql_dbg_p3p, vha, 0xb002,
  3408. "Performing ISP error recovery - ha=%p.\n", ha);
  3409. atomic_set(&ha->loop_down_timer, LOOP_DOWN_TIME);
  3410. if (atomic_read(&vha->loop_state) != LOOP_DOWN) {
  3411. atomic_set(&vha->loop_state, LOOP_DOWN);
  3412. qla2x00_mark_all_devices_lost(vha, 0);
  3413. list_for_each_entry(vp, &ha->vp_list, list)
  3414. qla2x00_mark_all_devices_lost(vha, 0);
  3415. } else {
  3416. if (!atomic_read(&vha->loop_down_timer))
  3417. atomic_set(&vha->loop_down_timer,
  3418. LOOP_DOWN_TIME);
  3419. }
  3420. /* Wait for pending cmds to complete */
  3421. qla2x00_eh_wait_for_pending_commands(vha, 0, 0, WAIT_HOST);
  3422. }
  3423. void
  3424. qla2x00_abort_isp_cleanup(scsi_qla_host_t *vha)
  3425. {
  3426. struct qla_hw_data *ha = vha->hw;
  3427. struct scsi_qla_host *vp;
  3428. unsigned long flags;
  3429. fc_port_t *fcport;
  3430. /* For ISP82XX, driver waits for completion of the commands.
  3431. * online flag should be set.
  3432. */
  3433. if (!IS_QLA82XX(ha))
  3434. vha->flags.online = 0;
  3435. ha->flags.chip_reset_done = 0;
  3436. clear_bit(ISP_ABORT_NEEDED, &vha->dpc_flags);
  3437. ha->qla_stats.total_isp_aborts++;
  3438. ql_log(ql_log_info, vha, 0x00af,
  3439. "Performing ISP error recovery - ha=%p.\n", ha);
  3440. /* For ISP82XX, reset_chip is just disabling interrupts.
  3441. * Driver waits for the completion of the commands.
  3442. * the interrupts need to be enabled.
  3443. */
  3444. if (!IS_QLA82XX(ha))
  3445. ha->isp_ops->reset_chip(vha);
  3446. atomic_set(&vha->loop_down_timer, LOOP_DOWN_TIME);
  3447. if (atomic_read(&vha->loop_state) != LOOP_DOWN) {
  3448. atomic_set(&vha->loop_state, LOOP_DOWN);
  3449. qla2x00_mark_all_devices_lost(vha, 0);
  3450. spin_lock_irqsave(&ha->vport_slock, flags);
  3451. list_for_each_entry(vp, &ha->vp_list, list) {
  3452. atomic_inc(&vp->vref_count);
  3453. spin_unlock_irqrestore(&ha->vport_slock, flags);
  3454. qla2x00_mark_all_devices_lost(vp, 0);
  3455. spin_lock_irqsave(&ha->vport_slock, flags);
  3456. atomic_dec(&vp->vref_count);
  3457. }
  3458. spin_unlock_irqrestore(&ha->vport_slock, flags);
  3459. } else {
  3460. if (!atomic_read(&vha->loop_down_timer))
  3461. atomic_set(&vha->loop_down_timer,
  3462. LOOP_DOWN_TIME);
  3463. }
  3464. /* Clear all async request states across all VPs. */
  3465. list_for_each_entry(fcport, &vha->vp_fcports, list)
  3466. fcport->flags &= ~(FCF_LOGIN_NEEDED | FCF_ASYNC_SENT);
  3467. spin_lock_irqsave(&ha->vport_slock, flags);
  3468. list_for_each_entry(vp, &ha->vp_list, list) {
  3469. atomic_inc(&vp->vref_count);
  3470. spin_unlock_irqrestore(&ha->vport_slock, flags);
  3471. list_for_each_entry(fcport, &vp->vp_fcports, list)
  3472. fcport->flags &= ~(FCF_LOGIN_NEEDED | FCF_ASYNC_SENT);
  3473. spin_lock_irqsave(&ha->vport_slock, flags);
  3474. atomic_dec(&vp->vref_count);
  3475. }
  3476. spin_unlock_irqrestore(&ha->vport_slock, flags);
  3477. if (!ha->flags.eeh_busy) {
  3478. /* Make sure for ISP 82XX IO DMA is complete */
  3479. if (IS_QLA82XX(ha)) {
  3480. qla82xx_chip_reset_cleanup(vha);
  3481. ql_log(ql_log_info, vha, 0x00b4,
  3482. "Done chip reset cleanup.\n");
  3483. /* Done waiting for pending commands.
  3484. * Reset the online flag.
  3485. */
  3486. vha->flags.online = 0;
  3487. }
  3488. /* Requeue all commands in outstanding command list. */
  3489. qla2x00_abort_all_cmds(vha, DID_RESET << 16);
  3490. }
  3491. }
  3492. /*
  3493. * qla2x00_abort_isp
  3494. * Resets ISP and aborts all outstanding commands.
  3495. *
  3496. * Input:
  3497. * ha = adapter block pointer.
  3498. *
  3499. * Returns:
  3500. * 0 = success
  3501. */
  3502. int
  3503. qla2x00_abort_isp(scsi_qla_host_t *vha)
  3504. {
  3505. int rval;
  3506. uint8_t status = 0;
  3507. struct qla_hw_data *ha = vha->hw;
  3508. struct scsi_qla_host *vp;
  3509. struct req_que *req = ha->req_q_map[0];
  3510. unsigned long flags;
  3511. if (vha->flags.online) {
  3512. qla2x00_abort_isp_cleanup(vha);
  3513. if (unlikely(pci_channel_offline(ha->pdev) &&
  3514. ha->flags.pci_channel_io_perm_failure)) {
  3515. clear_bit(ISP_ABORT_RETRY, &vha->dpc_flags);
  3516. status = 0;
  3517. return status;
  3518. }
  3519. ha->isp_ops->get_flash_version(vha, req->ring);
  3520. ha->isp_ops->nvram_config(vha);
  3521. if (!qla2x00_restart_isp(vha)) {
  3522. clear_bit(RESET_MARKER_NEEDED, &vha->dpc_flags);
  3523. if (!atomic_read(&vha->loop_down_timer)) {
  3524. /*
  3525. * Issue marker command only when we are going
  3526. * to start the I/O .
  3527. */
  3528. vha->marker_needed = 1;
  3529. }
  3530. vha->flags.online = 1;
  3531. ha->isp_ops->enable_intrs(ha);
  3532. ha->isp_abort_cnt = 0;
  3533. clear_bit(ISP_ABORT_RETRY, &vha->dpc_flags);
  3534. if (IS_QLA81XX(ha))
  3535. qla2x00_get_fw_version(vha,
  3536. &ha->fw_major_version,
  3537. &ha->fw_minor_version,
  3538. &ha->fw_subminor_version,
  3539. &ha->fw_attributes, &ha->fw_memory_size,
  3540. ha->mpi_version, &ha->mpi_capabilities,
  3541. ha->phy_version);
  3542. if (ha->fce) {
  3543. ha->flags.fce_enabled = 1;
  3544. memset(ha->fce, 0,
  3545. fce_calc_size(ha->fce_bufs));
  3546. rval = qla2x00_enable_fce_trace(vha,
  3547. ha->fce_dma, ha->fce_bufs, ha->fce_mb,
  3548. &ha->fce_bufs);
  3549. if (rval) {
  3550. ql_log(ql_log_warn, vha, 0x8033,
  3551. "Unable to reinitialize FCE "
  3552. "(%d).\n", rval);
  3553. ha->flags.fce_enabled = 0;
  3554. }
  3555. }
  3556. if (ha->eft) {
  3557. memset(ha->eft, 0, EFT_SIZE);
  3558. rval = qla2x00_enable_eft_trace(vha,
  3559. ha->eft_dma, EFT_NUM_BUFFERS);
  3560. if (rval) {
  3561. ql_log(ql_log_warn, vha, 0x8034,
  3562. "Unable to reinitialize EFT "
  3563. "(%d).\n", rval);
  3564. }
  3565. }
  3566. } else { /* failed the ISP abort */
  3567. vha->flags.online = 1;
  3568. if (test_bit(ISP_ABORT_RETRY, &vha->dpc_flags)) {
  3569. if (ha->isp_abort_cnt == 0) {
  3570. ql_log(ql_log_fatal, vha, 0x8035,
  3571. "ISP error recover failed - "
  3572. "board disabled.\n");
  3573. /*
  3574. * The next call disables the board
  3575. * completely.
  3576. */
  3577. ha->isp_ops->reset_adapter(vha);
  3578. vha->flags.online = 0;
  3579. clear_bit(ISP_ABORT_RETRY,
  3580. &vha->dpc_flags);
  3581. status = 0;
  3582. } else { /* schedule another ISP abort */
  3583. ha->isp_abort_cnt--;
  3584. ql_dbg(ql_dbg_taskm, vha, 0x8020,
  3585. "ISP abort - retry remaining %d.\n",
  3586. ha->isp_abort_cnt);
  3587. status = 1;
  3588. }
  3589. } else {
  3590. ha->isp_abort_cnt = MAX_RETRIES_OF_ISP_ABORT;
  3591. ql_dbg(ql_dbg_taskm, vha, 0x8021,
  3592. "ISP error recovery - retrying (%d) "
  3593. "more times.\n", ha->isp_abort_cnt);
  3594. set_bit(ISP_ABORT_RETRY, &vha->dpc_flags);
  3595. status = 1;
  3596. }
  3597. }
  3598. }
  3599. if (!status) {
  3600. ql_dbg(ql_dbg_taskm, vha, 0x8022, "%s succeeded.\n", __func__);
  3601. spin_lock_irqsave(&ha->vport_slock, flags);
  3602. list_for_each_entry(vp, &ha->vp_list, list) {
  3603. if (vp->vp_idx) {
  3604. atomic_inc(&vp->vref_count);
  3605. spin_unlock_irqrestore(&ha->vport_slock, flags);
  3606. qla2x00_vp_abort_isp(vp);
  3607. spin_lock_irqsave(&ha->vport_slock, flags);
  3608. atomic_dec(&vp->vref_count);
  3609. }
  3610. }
  3611. spin_unlock_irqrestore(&ha->vport_slock, flags);
  3612. } else {
  3613. ql_log(ql_log_warn, vha, 0x8023, "%s **** FAILED ****.\n");
  3614. }
  3615. return(status);
  3616. }
  3617. /*
  3618. * qla2x00_restart_isp
  3619. * restarts the ISP after a reset
  3620. *
  3621. * Input:
  3622. * ha = adapter block pointer.
  3623. *
  3624. * Returns:
  3625. * 0 = success
  3626. */
  3627. static int
  3628. qla2x00_restart_isp(scsi_qla_host_t *vha)
  3629. {
  3630. int status = 0;
  3631. uint32_t wait_time;
  3632. struct qla_hw_data *ha = vha->hw;
  3633. struct req_que *req = ha->req_q_map[0];
  3634. struct rsp_que *rsp = ha->rsp_q_map[0];
  3635. /* If firmware needs to be loaded */
  3636. if (qla2x00_isp_firmware(vha)) {
  3637. vha->flags.online = 0;
  3638. status = ha->isp_ops->chip_diag(vha);
  3639. if (!status)
  3640. status = qla2x00_setup_chip(vha);
  3641. }
  3642. if (!status && !(status = qla2x00_init_rings(vha))) {
  3643. clear_bit(RESET_MARKER_NEEDED, &vha->dpc_flags);
  3644. ha->flags.chip_reset_done = 1;
  3645. /* Initialize the queues in use */
  3646. qla25xx_init_queues(ha);
  3647. status = qla2x00_fw_ready(vha);
  3648. if (!status) {
  3649. ql_dbg(ql_dbg_taskm, vha, 0x8031,
  3650. "Start configure loop status = %d.\n", status);
  3651. /* Issue a marker after FW becomes ready. */
  3652. qla2x00_marker(vha, req, rsp, 0, 0, MK_SYNC_ALL);
  3653. vha->flags.online = 1;
  3654. /* Wait at most MAX_TARGET RSCNs for a stable link. */
  3655. wait_time = 256;
  3656. do {
  3657. clear_bit(LOOP_RESYNC_NEEDED, &vha->dpc_flags);
  3658. qla2x00_configure_loop(vha);
  3659. wait_time--;
  3660. } while (!atomic_read(&vha->loop_down_timer) &&
  3661. !(test_bit(ISP_ABORT_NEEDED, &vha->dpc_flags))
  3662. && wait_time && (test_bit(LOOP_RESYNC_NEEDED,
  3663. &vha->dpc_flags)));
  3664. }
  3665. /* if no cable then assume it's good */
  3666. if ((vha->device_flags & DFLG_NO_CABLE))
  3667. status = 0;
  3668. ql_dbg(ql_dbg_taskm, vha, 0x8032,
  3669. "Configure loop done, status = 0x%x.\n", status);
  3670. }
  3671. return (status);
  3672. }
  3673. static int
  3674. qla25xx_init_queues(struct qla_hw_data *ha)
  3675. {
  3676. struct rsp_que *rsp = NULL;
  3677. struct req_que *req = NULL;
  3678. struct scsi_qla_host *base_vha = pci_get_drvdata(ha->pdev);
  3679. int ret = -1;
  3680. int i;
  3681. for (i = 1; i < ha->max_rsp_queues; i++) {
  3682. rsp = ha->rsp_q_map[i];
  3683. if (rsp) {
  3684. rsp->options &= ~BIT_0;
  3685. ret = qla25xx_init_rsp_que(base_vha, rsp);
  3686. if (ret != QLA_SUCCESS)
  3687. ql_dbg(ql_dbg_init, base_vha, 0x00ff,
  3688. "%s Rsp que: %d init failed.\n",
  3689. __func__, rsp->id);
  3690. else
  3691. ql_dbg(ql_dbg_init, base_vha, 0x0100,
  3692. "%s Rsp que: %d inited.\n",
  3693. __func__, rsp->id);
  3694. }
  3695. }
  3696. for (i = 1; i < ha->max_req_queues; i++) {
  3697. req = ha->req_q_map[i];
  3698. if (req) {
  3699. /* Clear outstanding commands array. */
  3700. req->options &= ~BIT_0;
  3701. ret = qla25xx_init_req_que(base_vha, req);
  3702. if (ret != QLA_SUCCESS)
  3703. ql_dbg(ql_dbg_init, base_vha, 0x0101,
  3704. "%s Req que: %d init failed.\n",
  3705. __func__, req->id);
  3706. else
  3707. ql_dbg(ql_dbg_init, base_vha, 0x0102,
  3708. "%s Req que: %d inited.\n",
  3709. __func__, req->id);
  3710. }
  3711. }
  3712. return ret;
  3713. }
  3714. /*
  3715. * qla2x00_reset_adapter
  3716. * Reset adapter.
  3717. *
  3718. * Input:
  3719. * ha = adapter block pointer.
  3720. */
  3721. void
  3722. qla2x00_reset_adapter(scsi_qla_host_t *vha)
  3723. {
  3724. unsigned long flags = 0;
  3725. struct qla_hw_data *ha = vha->hw;
  3726. struct device_reg_2xxx __iomem *reg = &ha->iobase->isp;
  3727. vha->flags.online = 0;
  3728. ha->isp_ops->disable_intrs(ha);
  3729. spin_lock_irqsave(&ha->hardware_lock, flags);
  3730. WRT_REG_WORD(&reg->hccr, HCCR_RESET_RISC);
  3731. RD_REG_WORD(&reg->hccr); /* PCI Posting. */
  3732. WRT_REG_WORD(&reg->hccr, HCCR_RELEASE_RISC);
  3733. RD_REG_WORD(&reg->hccr); /* PCI Posting. */
  3734. spin_unlock_irqrestore(&ha->hardware_lock, flags);
  3735. }
  3736. void
  3737. qla24xx_reset_adapter(scsi_qla_host_t *vha)
  3738. {
  3739. unsigned long flags = 0;
  3740. struct qla_hw_data *ha = vha->hw;
  3741. struct device_reg_24xx __iomem *reg = &ha->iobase->isp24;
  3742. if (IS_QLA82XX(ha))
  3743. return;
  3744. vha->flags.online = 0;
  3745. ha->isp_ops->disable_intrs(ha);
  3746. spin_lock_irqsave(&ha->hardware_lock, flags);
  3747. WRT_REG_DWORD(&reg->hccr, HCCRX_SET_RISC_RESET);
  3748. RD_REG_DWORD(&reg->hccr);
  3749. WRT_REG_DWORD(&reg->hccr, HCCRX_REL_RISC_PAUSE);
  3750. RD_REG_DWORD(&reg->hccr);
  3751. spin_unlock_irqrestore(&ha->hardware_lock, flags);
  3752. if (IS_NOPOLLING_TYPE(ha))
  3753. ha->isp_ops->enable_intrs(ha);
  3754. }
  3755. /* On sparc systems, obtain port and node WWN from firmware
  3756. * properties.
  3757. */
  3758. static void qla24xx_nvram_wwn_from_ofw(scsi_qla_host_t *vha,
  3759. struct nvram_24xx *nv)
  3760. {
  3761. #ifdef CONFIG_SPARC
  3762. struct qla_hw_data *ha = vha->hw;
  3763. struct pci_dev *pdev = ha->pdev;
  3764. struct device_node *dp = pci_device_to_OF_node(pdev);
  3765. const u8 *val;
  3766. int len;
  3767. val = of_get_property(dp, "port-wwn", &len);
  3768. if (val && len >= WWN_SIZE)
  3769. memcpy(nv->port_name, val, WWN_SIZE);
  3770. val = of_get_property(dp, "node-wwn", &len);
  3771. if (val && len >= WWN_SIZE)
  3772. memcpy(nv->node_name, val, WWN_SIZE);
  3773. #endif
  3774. }
  3775. int
  3776. qla24xx_nvram_config(scsi_qla_host_t *vha)
  3777. {
  3778. int rval;
  3779. struct init_cb_24xx *icb;
  3780. struct nvram_24xx *nv;
  3781. uint32_t *dptr;
  3782. uint8_t *dptr1, *dptr2;
  3783. uint32_t chksum;
  3784. uint16_t cnt;
  3785. struct qla_hw_data *ha = vha->hw;
  3786. rval = QLA_SUCCESS;
  3787. icb = (struct init_cb_24xx *)ha->init_cb;
  3788. nv = ha->nvram;
  3789. /* Determine NVRAM starting address. */
  3790. if (ha->flags.port0) {
  3791. ha->nvram_base = FA_NVRAM_FUNC0_ADDR;
  3792. ha->vpd_base = FA_NVRAM_VPD0_ADDR;
  3793. } else {
  3794. ha->nvram_base = FA_NVRAM_FUNC1_ADDR;
  3795. ha->vpd_base = FA_NVRAM_VPD1_ADDR;
  3796. }
  3797. ha->nvram_size = sizeof(struct nvram_24xx);
  3798. ha->vpd_size = FA_NVRAM_VPD_SIZE;
  3799. if (IS_QLA82XX(ha))
  3800. ha->vpd_size = FA_VPD_SIZE_82XX;
  3801. /* Get VPD data into cache */
  3802. ha->vpd = ha->nvram + VPD_OFFSET;
  3803. ha->isp_ops->read_nvram(vha, (uint8_t *)ha->vpd,
  3804. ha->nvram_base - FA_NVRAM_FUNC0_ADDR, FA_NVRAM_VPD_SIZE * 4);
  3805. /* Get NVRAM data into cache and calculate checksum. */
  3806. dptr = (uint32_t *)nv;
  3807. ha->isp_ops->read_nvram(vha, (uint8_t *)dptr, ha->nvram_base,
  3808. ha->nvram_size);
  3809. for (cnt = 0, chksum = 0; cnt < ha->nvram_size >> 2; cnt++)
  3810. chksum += le32_to_cpu(*dptr++);
  3811. ql_dbg(ql_dbg_init + ql_dbg_buffer, vha, 0x006a,
  3812. "Contents of NVRAM\n");
  3813. ql_dump_buffer(ql_dbg_init + ql_dbg_buffer, vha, 0x010d,
  3814. (uint8_t *)nv, ha->nvram_size);
  3815. /* Bad NVRAM data, set defaults parameters. */
  3816. if (chksum || nv->id[0] != 'I' || nv->id[1] != 'S' || nv->id[2] != 'P'
  3817. || nv->id[3] != ' ' ||
  3818. nv->nvram_version < __constant_cpu_to_le16(ICB_VERSION)) {
  3819. /* Reset NVRAM data. */
  3820. ql_log(ql_log_warn, vha, 0x006b,
  3821. "Inconisistent NVRAM detected: checksum=0x%x id=%c "
  3822. "version=0x%x.\n", chksum, nv->id[0], nv->nvram_version);
  3823. ql_log(ql_log_warn, vha, 0x006c,
  3824. "Falling back to functioning (yet invalid -- WWPN) "
  3825. "defaults.\n");
  3826. /*
  3827. * Set default initialization control block.
  3828. */
  3829. memset(nv, 0, ha->nvram_size);
  3830. nv->nvram_version = __constant_cpu_to_le16(ICB_VERSION);
  3831. nv->version = __constant_cpu_to_le16(ICB_VERSION);
  3832. nv->frame_payload_size = __constant_cpu_to_le16(2048);
  3833. nv->execution_throttle = __constant_cpu_to_le16(0xFFFF);
  3834. nv->exchange_count = __constant_cpu_to_le16(0);
  3835. nv->hard_address = __constant_cpu_to_le16(124);
  3836. nv->port_name[0] = 0x21;
  3837. nv->port_name[1] = 0x00 + ha->port_no;
  3838. nv->port_name[2] = 0x00;
  3839. nv->port_name[3] = 0xe0;
  3840. nv->port_name[4] = 0x8b;
  3841. nv->port_name[5] = 0x1c;
  3842. nv->port_name[6] = 0x55;
  3843. nv->port_name[7] = 0x86;
  3844. nv->node_name[0] = 0x20;
  3845. nv->node_name[1] = 0x00;
  3846. nv->node_name[2] = 0x00;
  3847. nv->node_name[3] = 0xe0;
  3848. nv->node_name[4] = 0x8b;
  3849. nv->node_name[5] = 0x1c;
  3850. nv->node_name[6] = 0x55;
  3851. nv->node_name[7] = 0x86;
  3852. qla24xx_nvram_wwn_from_ofw(vha, nv);
  3853. nv->login_retry_count = __constant_cpu_to_le16(8);
  3854. nv->interrupt_delay_timer = __constant_cpu_to_le16(0);
  3855. nv->login_timeout = __constant_cpu_to_le16(0);
  3856. nv->firmware_options_1 =
  3857. __constant_cpu_to_le32(BIT_14|BIT_13|BIT_2|BIT_1);
  3858. nv->firmware_options_2 = __constant_cpu_to_le32(2 << 4);
  3859. nv->firmware_options_2 |= __constant_cpu_to_le32(BIT_12);
  3860. nv->firmware_options_3 = __constant_cpu_to_le32(2 << 13);
  3861. nv->host_p = __constant_cpu_to_le32(BIT_11|BIT_10);
  3862. nv->efi_parameters = __constant_cpu_to_le32(0);
  3863. nv->reset_delay = 5;
  3864. nv->max_luns_per_target = __constant_cpu_to_le16(128);
  3865. nv->port_down_retry_count = __constant_cpu_to_le16(30);
  3866. nv->link_down_timeout = __constant_cpu_to_le16(30);
  3867. rval = 1;
  3868. }
  3869. /* Reset Initialization control block */
  3870. memset(icb, 0, ha->init_cb_size);
  3871. /* Copy 1st segment. */
  3872. dptr1 = (uint8_t *)icb;
  3873. dptr2 = (uint8_t *)&nv->version;
  3874. cnt = (uint8_t *)&icb->response_q_inpointer - (uint8_t *)&icb->version;
  3875. while (cnt--)
  3876. *dptr1++ = *dptr2++;
  3877. icb->login_retry_count = nv->login_retry_count;
  3878. icb->link_down_on_nos = nv->link_down_on_nos;
  3879. /* Copy 2nd segment. */
  3880. dptr1 = (uint8_t *)&icb->interrupt_delay_timer;
  3881. dptr2 = (uint8_t *)&nv->interrupt_delay_timer;
  3882. cnt = (uint8_t *)&icb->reserved_3 -
  3883. (uint8_t *)&icb->interrupt_delay_timer;
  3884. while (cnt--)
  3885. *dptr1++ = *dptr2++;
  3886. /*
  3887. * Setup driver NVRAM options.
  3888. */
  3889. qla2x00_set_model_info(vha, nv->model_name, sizeof(nv->model_name),
  3890. "QLA2462");
  3891. /* Use alternate WWN? */
  3892. if (nv->host_p & __constant_cpu_to_le32(BIT_15)) {
  3893. memcpy(icb->node_name, nv->alternate_node_name, WWN_SIZE);
  3894. memcpy(icb->port_name, nv->alternate_port_name, WWN_SIZE);
  3895. }
  3896. /* Prepare nodename */
  3897. if ((icb->firmware_options_1 & __constant_cpu_to_le32(BIT_14)) == 0) {
  3898. /*
  3899. * Firmware will apply the following mask if the nodename was
  3900. * not provided.
  3901. */
  3902. memcpy(icb->node_name, icb->port_name, WWN_SIZE);
  3903. icb->node_name[0] &= 0xF0;
  3904. }
  3905. /* Set host adapter parameters. */
  3906. ha->flags.disable_risc_code_load = 0;
  3907. ha->flags.enable_lip_reset = 0;
  3908. ha->flags.enable_lip_full_login =
  3909. le32_to_cpu(nv->host_p) & BIT_10 ? 1: 0;
  3910. ha->flags.enable_target_reset =
  3911. le32_to_cpu(nv->host_p) & BIT_11 ? 1: 0;
  3912. ha->flags.enable_led_scheme = 0;
  3913. ha->flags.disable_serdes = le32_to_cpu(nv->host_p) & BIT_5 ? 1: 0;
  3914. ha->operating_mode = (le32_to_cpu(icb->firmware_options_2) &
  3915. (BIT_6 | BIT_5 | BIT_4)) >> 4;
  3916. memcpy(ha->fw_seriallink_options24, nv->seriallink_options,
  3917. sizeof(ha->fw_seriallink_options24));
  3918. /* save HBA serial number */
  3919. ha->serial0 = icb->port_name[5];
  3920. ha->serial1 = icb->port_name[6];
  3921. ha->serial2 = icb->port_name[7];
  3922. memcpy(vha->node_name, icb->node_name, WWN_SIZE);
  3923. memcpy(vha->port_name, icb->port_name, WWN_SIZE);
  3924. icb->execution_throttle = __constant_cpu_to_le16(0xFFFF);
  3925. ha->retry_count = le16_to_cpu(nv->login_retry_count);
  3926. /* Set minimum login_timeout to 4 seconds. */
  3927. if (le16_to_cpu(nv->login_timeout) < ql2xlogintimeout)
  3928. nv->login_timeout = cpu_to_le16(ql2xlogintimeout);
  3929. if (le16_to_cpu(nv->login_timeout) < 4)
  3930. nv->login_timeout = __constant_cpu_to_le16(4);
  3931. ha->login_timeout = le16_to_cpu(nv->login_timeout);
  3932. icb->login_timeout = nv->login_timeout;
  3933. /* Set minimum RATOV to 100 tenths of a second. */
  3934. ha->r_a_tov = 100;
  3935. ha->loop_reset_delay = nv->reset_delay;
  3936. /* Link Down Timeout = 0:
  3937. *
  3938. * When Port Down timer expires we will start returning
  3939. * I/O's to OS with "DID_NO_CONNECT".
  3940. *
  3941. * Link Down Timeout != 0:
  3942. *
  3943. * The driver waits for the link to come up after link down
  3944. * before returning I/Os to OS with "DID_NO_CONNECT".
  3945. */
  3946. if (le16_to_cpu(nv->link_down_timeout) == 0) {
  3947. ha->loop_down_abort_time =
  3948. (LOOP_DOWN_TIME - LOOP_DOWN_TIMEOUT);
  3949. } else {
  3950. ha->link_down_timeout = le16_to_cpu(nv->link_down_timeout);
  3951. ha->loop_down_abort_time =
  3952. (LOOP_DOWN_TIME - ha->link_down_timeout);
  3953. }
  3954. /* Need enough time to try and get the port back. */
  3955. ha->port_down_retry_count = le16_to_cpu(nv->port_down_retry_count);
  3956. if (qlport_down_retry)
  3957. ha->port_down_retry_count = qlport_down_retry;
  3958. /* Set login_retry_count */
  3959. ha->login_retry_count = le16_to_cpu(nv->login_retry_count);
  3960. if (ha->port_down_retry_count ==
  3961. le16_to_cpu(nv->port_down_retry_count) &&
  3962. ha->port_down_retry_count > 3)
  3963. ha->login_retry_count = ha->port_down_retry_count;
  3964. else if (ha->port_down_retry_count > (int)ha->login_retry_count)
  3965. ha->login_retry_count = ha->port_down_retry_count;
  3966. if (ql2xloginretrycount)
  3967. ha->login_retry_count = ql2xloginretrycount;
  3968. /* Enable ZIO. */
  3969. if (!vha->flags.init_done) {
  3970. ha->zio_mode = le32_to_cpu(icb->firmware_options_2) &
  3971. (BIT_3 | BIT_2 | BIT_1 | BIT_0);
  3972. ha->zio_timer = le16_to_cpu(icb->interrupt_delay_timer) ?
  3973. le16_to_cpu(icb->interrupt_delay_timer): 2;
  3974. }
  3975. icb->firmware_options_2 &= __constant_cpu_to_le32(
  3976. ~(BIT_3 | BIT_2 | BIT_1 | BIT_0));
  3977. vha->flags.process_response_queue = 0;
  3978. if (ha->zio_mode != QLA_ZIO_DISABLED) {
  3979. ha->zio_mode = QLA_ZIO_MODE_6;
  3980. ql_log(ql_log_info, vha, 0x006f,
  3981. "ZIO mode %d enabled; timer delay (%d us).\n",
  3982. ha->zio_mode, ha->zio_timer * 100);
  3983. icb->firmware_options_2 |= cpu_to_le32(
  3984. (uint32_t)ha->zio_mode);
  3985. icb->interrupt_delay_timer = cpu_to_le16(ha->zio_timer);
  3986. vha->flags.process_response_queue = 1;
  3987. }
  3988. if (rval) {
  3989. ql_log(ql_log_warn, vha, 0x0070,
  3990. "NVRAM configuration failed.\n");
  3991. }
  3992. return (rval);
  3993. }
  3994. static int
  3995. qla24xx_load_risc_flash(scsi_qla_host_t *vha, uint32_t *srisc_addr,
  3996. uint32_t faddr)
  3997. {
  3998. int rval = QLA_SUCCESS;
  3999. int segments, fragment;
  4000. uint32_t *dcode, dlen;
  4001. uint32_t risc_addr;
  4002. uint32_t risc_size;
  4003. uint32_t i;
  4004. struct qla_hw_data *ha = vha->hw;
  4005. struct req_que *req = ha->req_q_map[0];
  4006. ql_dbg(ql_dbg_init, vha, 0x008b,
  4007. "Loading firmware from flash (%x).\n", faddr);
  4008. rval = QLA_SUCCESS;
  4009. segments = FA_RISC_CODE_SEGMENTS;
  4010. dcode = (uint32_t *)req->ring;
  4011. *srisc_addr = 0;
  4012. /* Validate firmware image by checking version. */
  4013. qla24xx_read_flash_data(vha, dcode, faddr + 4, 4);
  4014. for (i = 0; i < 4; i++)
  4015. dcode[i] = be32_to_cpu(dcode[i]);
  4016. if ((dcode[0] == 0xffffffff && dcode[1] == 0xffffffff &&
  4017. dcode[2] == 0xffffffff && dcode[3] == 0xffffffff) ||
  4018. (dcode[0] == 0 && dcode[1] == 0 && dcode[2] == 0 &&
  4019. dcode[3] == 0)) {
  4020. ql_log(ql_log_fatal, vha, 0x008c,
  4021. "Unable to verify the integrity of flash firmware "
  4022. "image.\n");
  4023. ql_log(ql_log_fatal, vha, 0x008d,
  4024. "Firmware data: %08x %08x %08x %08x.\n",
  4025. dcode[0], dcode[1], dcode[2], dcode[3]);
  4026. return QLA_FUNCTION_FAILED;
  4027. }
  4028. while (segments && rval == QLA_SUCCESS) {
  4029. /* Read segment's load information. */
  4030. qla24xx_read_flash_data(vha, dcode, faddr, 4);
  4031. risc_addr = be32_to_cpu(dcode[2]);
  4032. *srisc_addr = *srisc_addr == 0 ? risc_addr : *srisc_addr;
  4033. risc_size = be32_to_cpu(dcode[3]);
  4034. fragment = 0;
  4035. while (risc_size > 0 && rval == QLA_SUCCESS) {
  4036. dlen = (uint32_t)(ha->fw_transfer_size >> 2);
  4037. if (dlen > risc_size)
  4038. dlen = risc_size;
  4039. ql_dbg(ql_dbg_init, vha, 0x008e,
  4040. "Loading risc segment@ risc addr %x "
  4041. "number of dwords 0x%x offset 0x%x.\n",
  4042. risc_addr, dlen, faddr);
  4043. qla24xx_read_flash_data(vha, dcode, faddr, dlen);
  4044. for (i = 0; i < dlen; i++)
  4045. dcode[i] = swab32(dcode[i]);
  4046. rval = qla2x00_load_ram(vha, req->dma, risc_addr,
  4047. dlen);
  4048. if (rval) {
  4049. ql_log(ql_log_fatal, vha, 0x008f,
  4050. "Failed to load segment %d of firmware.\n",
  4051. fragment);
  4052. break;
  4053. }
  4054. faddr += dlen;
  4055. risc_addr += dlen;
  4056. risc_size -= dlen;
  4057. fragment++;
  4058. }
  4059. /* Next segment. */
  4060. segments--;
  4061. }
  4062. return rval;
  4063. }
  4064. #define QLA_FW_URL "ftp://ftp.qlogic.com/outgoing/linux/firmware/"
  4065. int
  4066. qla2x00_load_risc(scsi_qla_host_t *vha, uint32_t *srisc_addr)
  4067. {
  4068. int rval;
  4069. int i, fragment;
  4070. uint16_t *wcode, *fwcode;
  4071. uint32_t risc_addr, risc_size, fwclen, wlen, *seg;
  4072. struct fw_blob *blob;
  4073. struct qla_hw_data *ha = vha->hw;
  4074. struct req_que *req = ha->req_q_map[0];
  4075. /* Load firmware blob. */
  4076. blob = qla2x00_request_firmware(vha);
  4077. if (!blob) {
  4078. ql_log(ql_log_info, vha, 0x0083,
  4079. "Fimware image unavailable.\n");
  4080. ql_log(ql_log_info, vha, 0x0084,
  4081. "Firmware images can be retrieved from: "QLA_FW_URL ".\n");
  4082. return QLA_FUNCTION_FAILED;
  4083. }
  4084. rval = QLA_SUCCESS;
  4085. wcode = (uint16_t *)req->ring;
  4086. *srisc_addr = 0;
  4087. fwcode = (uint16_t *)blob->fw->data;
  4088. fwclen = 0;
  4089. /* Validate firmware image by checking version. */
  4090. if (blob->fw->size < 8 * sizeof(uint16_t)) {
  4091. ql_log(ql_log_fatal, vha, 0x0085,
  4092. "Unable to verify integrity of firmware image (%Zd).\n",
  4093. blob->fw->size);
  4094. goto fail_fw_integrity;
  4095. }
  4096. for (i = 0; i < 4; i++)
  4097. wcode[i] = be16_to_cpu(fwcode[i + 4]);
  4098. if ((wcode[0] == 0xffff && wcode[1] == 0xffff && wcode[2] == 0xffff &&
  4099. wcode[3] == 0xffff) || (wcode[0] == 0 && wcode[1] == 0 &&
  4100. wcode[2] == 0 && wcode[3] == 0)) {
  4101. ql_log(ql_log_fatal, vha, 0x0086,
  4102. "Unable to verify integrity of firmware image.\n");
  4103. ql_log(ql_log_fatal, vha, 0x0087,
  4104. "Firmware data: %04x %04x %04x %04x.\n",
  4105. wcode[0], wcode[1], wcode[2], wcode[3]);
  4106. goto fail_fw_integrity;
  4107. }
  4108. seg = blob->segs;
  4109. while (*seg && rval == QLA_SUCCESS) {
  4110. risc_addr = *seg;
  4111. *srisc_addr = *srisc_addr == 0 ? *seg : *srisc_addr;
  4112. risc_size = be16_to_cpu(fwcode[3]);
  4113. /* Validate firmware image size. */
  4114. fwclen += risc_size * sizeof(uint16_t);
  4115. if (blob->fw->size < fwclen) {
  4116. ql_log(ql_log_fatal, vha, 0x0088,
  4117. "Unable to verify integrity of firmware image "
  4118. "(%Zd).\n", blob->fw->size);
  4119. goto fail_fw_integrity;
  4120. }
  4121. fragment = 0;
  4122. while (risc_size > 0 && rval == QLA_SUCCESS) {
  4123. wlen = (uint16_t)(ha->fw_transfer_size >> 1);
  4124. if (wlen > risc_size)
  4125. wlen = risc_size;
  4126. ql_dbg(ql_dbg_init, vha, 0x0089,
  4127. "Loading risc segment@ risc addr %x number of "
  4128. "words 0x%x.\n", risc_addr, wlen);
  4129. for (i = 0; i < wlen; i++)
  4130. wcode[i] = swab16(fwcode[i]);
  4131. rval = qla2x00_load_ram(vha, req->dma, risc_addr,
  4132. wlen);
  4133. if (rval) {
  4134. ql_log(ql_log_fatal, vha, 0x008a,
  4135. "Failed to load segment %d of firmware.\n",
  4136. fragment);
  4137. break;
  4138. }
  4139. fwcode += wlen;
  4140. risc_addr += wlen;
  4141. risc_size -= wlen;
  4142. fragment++;
  4143. }
  4144. /* Next segment. */
  4145. seg++;
  4146. }
  4147. return rval;
  4148. fail_fw_integrity:
  4149. return QLA_FUNCTION_FAILED;
  4150. }
  4151. static int
  4152. qla24xx_load_risc_blob(scsi_qla_host_t *vha, uint32_t *srisc_addr)
  4153. {
  4154. int rval;
  4155. int segments, fragment;
  4156. uint32_t *dcode, dlen;
  4157. uint32_t risc_addr;
  4158. uint32_t risc_size;
  4159. uint32_t i;
  4160. struct fw_blob *blob;
  4161. uint32_t *fwcode, fwclen;
  4162. struct qla_hw_data *ha = vha->hw;
  4163. struct req_que *req = ha->req_q_map[0];
  4164. /* Load firmware blob. */
  4165. blob = qla2x00_request_firmware(vha);
  4166. if (!blob) {
  4167. ql_log(ql_log_warn, vha, 0x0090,
  4168. "Fimware image unavailable.\n");
  4169. ql_log(ql_log_warn, vha, 0x0091,
  4170. "Firmware images can be retrieved from: "
  4171. QLA_FW_URL ".\n");
  4172. return QLA_FUNCTION_FAILED;
  4173. }
  4174. ql_log(ql_log_info, vha, 0x0092,
  4175. "Loading via request-firmware.\n");
  4176. rval = QLA_SUCCESS;
  4177. segments = FA_RISC_CODE_SEGMENTS;
  4178. dcode = (uint32_t *)req->ring;
  4179. *srisc_addr = 0;
  4180. fwcode = (uint32_t *)blob->fw->data;
  4181. fwclen = 0;
  4182. /* Validate firmware image by checking version. */
  4183. if (blob->fw->size < 8 * sizeof(uint32_t)) {
  4184. ql_log(ql_log_fatal, vha, 0x0093,
  4185. "Unable to verify integrity of firmware image (%Zd).\n",
  4186. blob->fw->size);
  4187. goto fail_fw_integrity;
  4188. }
  4189. for (i = 0; i < 4; i++)
  4190. dcode[i] = be32_to_cpu(fwcode[i + 4]);
  4191. if ((dcode[0] == 0xffffffff && dcode[1] == 0xffffffff &&
  4192. dcode[2] == 0xffffffff && dcode[3] == 0xffffffff) ||
  4193. (dcode[0] == 0 && dcode[1] == 0 && dcode[2] == 0 &&
  4194. dcode[3] == 0)) {
  4195. ql_log(ql_log_fatal, vha, 0x0094,
  4196. "Unable to verify integrity of firmware image (%Zd).\n",
  4197. blob->fw->size);
  4198. ql_log(ql_log_fatal, vha, 0x0095,
  4199. "Firmware data: %08x %08x %08x %08x.\n",
  4200. dcode[0], dcode[1], dcode[2], dcode[3]);
  4201. goto fail_fw_integrity;
  4202. }
  4203. while (segments && rval == QLA_SUCCESS) {
  4204. risc_addr = be32_to_cpu(fwcode[2]);
  4205. *srisc_addr = *srisc_addr == 0 ? risc_addr : *srisc_addr;
  4206. risc_size = be32_to_cpu(fwcode[3]);
  4207. /* Validate firmware image size. */
  4208. fwclen += risc_size * sizeof(uint32_t);
  4209. if (blob->fw->size < fwclen) {
  4210. ql_log(ql_log_fatal, vha, 0x0096,
  4211. "Unable to verify integrity of firmware image "
  4212. "(%Zd).\n", blob->fw->size);
  4213. goto fail_fw_integrity;
  4214. }
  4215. fragment = 0;
  4216. while (risc_size > 0 && rval == QLA_SUCCESS) {
  4217. dlen = (uint32_t)(ha->fw_transfer_size >> 2);
  4218. if (dlen > risc_size)
  4219. dlen = risc_size;
  4220. ql_dbg(ql_dbg_init, vha, 0x0097,
  4221. "Loading risc segment@ risc addr %x "
  4222. "number of dwords 0x%x.\n", risc_addr, dlen);
  4223. for (i = 0; i < dlen; i++)
  4224. dcode[i] = swab32(fwcode[i]);
  4225. rval = qla2x00_load_ram(vha, req->dma, risc_addr,
  4226. dlen);
  4227. if (rval) {
  4228. ql_log(ql_log_fatal, vha, 0x0098,
  4229. "Failed to load segment %d of firmware.\n",
  4230. fragment);
  4231. break;
  4232. }
  4233. fwcode += dlen;
  4234. risc_addr += dlen;
  4235. risc_size -= dlen;
  4236. fragment++;
  4237. }
  4238. /* Next segment. */
  4239. segments--;
  4240. }
  4241. return rval;
  4242. fail_fw_integrity:
  4243. return QLA_FUNCTION_FAILED;
  4244. }
  4245. int
  4246. qla24xx_load_risc(scsi_qla_host_t *vha, uint32_t *srisc_addr)
  4247. {
  4248. int rval;
  4249. if (ql2xfwloadbin == 1)
  4250. return qla81xx_load_risc(vha, srisc_addr);
  4251. /*
  4252. * FW Load priority:
  4253. * 1) Firmware via request-firmware interface (.bin file).
  4254. * 2) Firmware residing in flash.
  4255. */
  4256. rval = qla24xx_load_risc_blob(vha, srisc_addr);
  4257. if (rval == QLA_SUCCESS)
  4258. return rval;
  4259. return qla24xx_load_risc_flash(vha, srisc_addr,
  4260. vha->hw->flt_region_fw);
  4261. }
  4262. int
  4263. qla81xx_load_risc(scsi_qla_host_t *vha, uint32_t *srisc_addr)
  4264. {
  4265. int rval;
  4266. struct qla_hw_data *ha = vha->hw;
  4267. if (ql2xfwloadbin == 2)
  4268. goto try_blob_fw;
  4269. /*
  4270. * FW Load priority:
  4271. * 1) Firmware residing in flash.
  4272. * 2) Firmware via request-firmware interface (.bin file).
  4273. * 3) Golden-Firmware residing in flash -- limited operation.
  4274. */
  4275. rval = qla24xx_load_risc_flash(vha, srisc_addr, ha->flt_region_fw);
  4276. if (rval == QLA_SUCCESS)
  4277. return rval;
  4278. try_blob_fw:
  4279. rval = qla24xx_load_risc_blob(vha, srisc_addr);
  4280. if (rval == QLA_SUCCESS || !ha->flt_region_gold_fw)
  4281. return rval;
  4282. ql_log(ql_log_info, vha, 0x0099,
  4283. "Attempting to fallback to golden firmware.\n");
  4284. rval = qla24xx_load_risc_flash(vha, srisc_addr, ha->flt_region_gold_fw);
  4285. if (rval != QLA_SUCCESS)
  4286. return rval;
  4287. ql_log(ql_log_info, vha, 0x009a, "Update operational firmware.\n");
  4288. ha->flags.running_gold_fw = 1;
  4289. return rval;
  4290. }
  4291. void
  4292. qla2x00_try_to_stop_firmware(scsi_qla_host_t *vha)
  4293. {
  4294. int ret, retries;
  4295. struct qla_hw_data *ha = vha->hw;
  4296. if (ha->flags.pci_channel_io_perm_failure)
  4297. return;
  4298. if (!IS_FWI2_CAPABLE(ha))
  4299. return;
  4300. if (!ha->fw_major_version)
  4301. return;
  4302. ret = qla2x00_stop_firmware(vha);
  4303. for (retries = 5; ret != QLA_SUCCESS && ret != QLA_FUNCTION_TIMEOUT &&
  4304. ret != QLA_INVALID_COMMAND && retries ; retries--) {
  4305. ha->isp_ops->reset_chip(vha);
  4306. if (ha->isp_ops->chip_diag(vha) != QLA_SUCCESS)
  4307. continue;
  4308. if (qla2x00_setup_chip(vha) != QLA_SUCCESS)
  4309. continue;
  4310. ql_log(ql_log_info, vha, 0x8015,
  4311. "Attempting retry of stop-firmware command.\n");
  4312. ret = qla2x00_stop_firmware(vha);
  4313. }
  4314. }
  4315. int
  4316. qla24xx_configure_vhba(scsi_qla_host_t *vha)
  4317. {
  4318. int rval = QLA_SUCCESS;
  4319. uint16_t mb[MAILBOX_REGISTER_COUNT];
  4320. struct qla_hw_data *ha = vha->hw;
  4321. struct scsi_qla_host *base_vha = pci_get_drvdata(ha->pdev);
  4322. struct req_que *req;
  4323. struct rsp_que *rsp;
  4324. if (!vha->vp_idx)
  4325. return -EINVAL;
  4326. rval = qla2x00_fw_ready(base_vha);
  4327. if (ha->flags.cpu_affinity_enabled)
  4328. req = ha->req_q_map[0];
  4329. else
  4330. req = vha->req;
  4331. rsp = req->rsp;
  4332. if (rval == QLA_SUCCESS) {
  4333. clear_bit(RESET_MARKER_NEEDED, &vha->dpc_flags);
  4334. qla2x00_marker(vha, req, rsp, 0, 0, MK_SYNC_ALL);
  4335. }
  4336. vha->flags.management_server_logged_in = 0;
  4337. /* Login to SNS first */
  4338. ha->isp_ops->fabric_login(vha, NPH_SNS, 0xff, 0xff, 0xfc, mb, BIT_1);
  4339. if (mb[0] != MBS_COMMAND_COMPLETE) {
  4340. ql_dbg(ql_dbg_init, vha, 0x0103,
  4341. "Failed SNS login: loop_id=%x mb[0]=%x mb[1]=%x mb[2]=%x "
  4342. "mb[6]=%x mb[7]=%x.\n",
  4343. NPH_SNS, mb[0], mb[1], mb[2], mb[6], mb[7]);
  4344. return (QLA_FUNCTION_FAILED);
  4345. }
  4346. atomic_set(&vha->loop_down_timer, 0);
  4347. atomic_set(&vha->loop_state, LOOP_UP);
  4348. set_bit(LOOP_RESYNC_NEEDED, &vha->dpc_flags);
  4349. set_bit(LOCAL_LOOP_UPDATE, &vha->dpc_flags);
  4350. rval = qla2x00_loop_resync(base_vha);
  4351. return rval;
  4352. }
  4353. /* 84XX Support **************************************************************/
  4354. static LIST_HEAD(qla_cs84xx_list);
  4355. static DEFINE_MUTEX(qla_cs84xx_mutex);
  4356. static struct qla_chip_state_84xx *
  4357. qla84xx_get_chip(struct scsi_qla_host *vha)
  4358. {
  4359. struct qla_chip_state_84xx *cs84xx;
  4360. struct qla_hw_data *ha = vha->hw;
  4361. mutex_lock(&qla_cs84xx_mutex);
  4362. /* Find any shared 84xx chip. */
  4363. list_for_each_entry(cs84xx, &qla_cs84xx_list, list) {
  4364. if (cs84xx->bus == ha->pdev->bus) {
  4365. kref_get(&cs84xx->kref);
  4366. goto done;
  4367. }
  4368. }
  4369. cs84xx = kzalloc(sizeof(*cs84xx), GFP_KERNEL);
  4370. if (!cs84xx)
  4371. goto done;
  4372. kref_init(&cs84xx->kref);
  4373. spin_lock_init(&cs84xx->access_lock);
  4374. mutex_init(&cs84xx->fw_update_mutex);
  4375. cs84xx->bus = ha->pdev->bus;
  4376. list_add_tail(&cs84xx->list, &qla_cs84xx_list);
  4377. done:
  4378. mutex_unlock(&qla_cs84xx_mutex);
  4379. return cs84xx;
  4380. }
  4381. static void
  4382. __qla84xx_chip_release(struct kref *kref)
  4383. {
  4384. struct qla_chip_state_84xx *cs84xx =
  4385. container_of(kref, struct qla_chip_state_84xx, kref);
  4386. mutex_lock(&qla_cs84xx_mutex);
  4387. list_del(&cs84xx->list);
  4388. mutex_unlock(&qla_cs84xx_mutex);
  4389. kfree(cs84xx);
  4390. }
  4391. void
  4392. qla84xx_put_chip(struct scsi_qla_host *vha)
  4393. {
  4394. struct qla_hw_data *ha = vha->hw;
  4395. if (ha->cs84xx)
  4396. kref_put(&ha->cs84xx->kref, __qla84xx_chip_release);
  4397. }
  4398. static int
  4399. qla84xx_init_chip(scsi_qla_host_t *vha)
  4400. {
  4401. int rval;
  4402. uint16_t status[2];
  4403. struct qla_hw_data *ha = vha->hw;
  4404. mutex_lock(&ha->cs84xx->fw_update_mutex);
  4405. rval = qla84xx_verify_chip(vha, status);
  4406. mutex_unlock(&ha->cs84xx->fw_update_mutex);
  4407. return rval != QLA_SUCCESS || status[0] ? QLA_FUNCTION_FAILED:
  4408. QLA_SUCCESS;
  4409. }
  4410. /* 81XX Support **************************************************************/
  4411. int
  4412. qla81xx_nvram_config(scsi_qla_host_t *vha)
  4413. {
  4414. int rval;
  4415. struct init_cb_81xx *icb;
  4416. struct nvram_81xx *nv;
  4417. uint32_t *dptr;
  4418. uint8_t *dptr1, *dptr2;
  4419. uint32_t chksum;
  4420. uint16_t cnt;
  4421. struct qla_hw_data *ha = vha->hw;
  4422. rval = QLA_SUCCESS;
  4423. icb = (struct init_cb_81xx *)ha->init_cb;
  4424. nv = ha->nvram;
  4425. /* Determine NVRAM starting address. */
  4426. ha->nvram_size = sizeof(struct nvram_81xx);
  4427. ha->vpd_size = FA_NVRAM_VPD_SIZE;
  4428. /* Get VPD data into cache */
  4429. ha->vpd = ha->nvram + VPD_OFFSET;
  4430. ha->isp_ops->read_optrom(vha, ha->vpd, ha->flt_region_vpd << 2,
  4431. ha->vpd_size);
  4432. /* Get NVRAM data into cache and calculate checksum. */
  4433. ha->isp_ops->read_optrom(vha, ha->nvram, ha->flt_region_nvram << 2,
  4434. ha->nvram_size);
  4435. dptr = (uint32_t *)nv;
  4436. for (cnt = 0, chksum = 0; cnt < ha->nvram_size >> 2; cnt++)
  4437. chksum += le32_to_cpu(*dptr++);
  4438. ql_dbg(ql_dbg_init + ql_dbg_buffer, vha, 0x0111,
  4439. "Contents of NVRAM:\n");
  4440. ql_dump_buffer(ql_dbg_init + ql_dbg_buffer, vha, 0x0112,
  4441. (uint8_t *)nv, ha->nvram_size);
  4442. /* Bad NVRAM data, set defaults parameters. */
  4443. if (chksum || nv->id[0] != 'I' || nv->id[1] != 'S' || nv->id[2] != 'P'
  4444. || nv->id[3] != ' ' ||
  4445. nv->nvram_version < __constant_cpu_to_le16(ICB_VERSION)) {
  4446. /* Reset NVRAM data. */
  4447. ql_log(ql_log_info, vha, 0x0073,
  4448. "Inconisistent NVRAM detected: checksum=0x%x id=%c "
  4449. "version=0x%x.\n", chksum, nv->id[0],
  4450. le16_to_cpu(nv->nvram_version));
  4451. ql_log(ql_log_info, vha, 0x0074,
  4452. "Falling back to functioning (yet invalid -- WWPN) "
  4453. "defaults.\n");
  4454. /*
  4455. * Set default initialization control block.
  4456. */
  4457. memset(nv, 0, ha->nvram_size);
  4458. nv->nvram_version = __constant_cpu_to_le16(ICB_VERSION);
  4459. nv->version = __constant_cpu_to_le16(ICB_VERSION);
  4460. nv->frame_payload_size = __constant_cpu_to_le16(2048);
  4461. nv->execution_throttle = __constant_cpu_to_le16(0xFFFF);
  4462. nv->exchange_count = __constant_cpu_to_le16(0);
  4463. nv->port_name[0] = 0x21;
  4464. nv->port_name[1] = 0x00 + ha->port_no;
  4465. nv->port_name[2] = 0x00;
  4466. nv->port_name[3] = 0xe0;
  4467. nv->port_name[4] = 0x8b;
  4468. nv->port_name[5] = 0x1c;
  4469. nv->port_name[6] = 0x55;
  4470. nv->port_name[7] = 0x86;
  4471. nv->node_name[0] = 0x20;
  4472. nv->node_name[1] = 0x00;
  4473. nv->node_name[2] = 0x00;
  4474. nv->node_name[3] = 0xe0;
  4475. nv->node_name[4] = 0x8b;
  4476. nv->node_name[5] = 0x1c;
  4477. nv->node_name[6] = 0x55;
  4478. nv->node_name[7] = 0x86;
  4479. nv->login_retry_count = __constant_cpu_to_le16(8);
  4480. nv->interrupt_delay_timer = __constant_cpu_to_le16(0);
  4481. nv->login_timeout = __constant_cpu_to_le16(0);
  4482. nv->firmware_options_1 =
  4483. __constant_cpu_to_le32(BIT_14|BIT_13|BIT_2|BIT_1);
  4484. nv->firmware_options_2 = __constant_cpu_to_le32(2 << 4);
  4485. nv->firmware_options_2 |= __constant_cpu_to_le32(BIT_12);
  4486. nv->firmware_options_3 = __constant_cpu_to_le32(2 << 13);
  4487. nv->host_p = __constant_cpu_to_le32(BIT_11|BIT_10);
  4488. nv->efi_parameters = __constant_cpu_to_le32(0);
  4489. nv->reset_delay = 5;
  4490. nv->max_luns_per_target = __constant_cpu_to_le16(128);
  4491. nv->port_down_retry_count = __constant_cpu_to_le16(30);
  4492. nv->link_down_timeout = __constant_cpu_to_le16(30);
  4493. nv->enode_mac[0] = 0x00;
  4494. nv->enode_mac[1] = 0x02;
  4495. nv->enode_mac[2] = 0x03;
  4496. nv->enode_mac[3] = 0x04;
  4497. nv->enode_mac[4] = 0x05;
  4498. nv->enode_mac[5] = 0x06 + ha->port_no;
  4499. rval = 1;
  4500. }
  4501. /* Reset Initialization control block */
  4502. memset(icb, 0, ha->init_cb_size);
  4503. /* Copy 1st segment. */
  4504. dptr1 = (uint8_t *)icb;
  4505. dptr2 = (uint8_t *)&nv->version;
  4506. cnt = (uint8_t *)&icb->response_q_inpointer - (uint8_t *)&icb->version;
  4507. while (cnt--)
  4508. *dptr1++ = *dptr2++;
  4509. icb->login_retry_count = nv->login_retry_count;
  4510. /* Copy 2nd segment. */
  4511. dptr1 = (uint8_t *)&icb->interrupt_delay_timer;
  4512. dptr2 = (uint8_t *)&nv->interrupt_delay_timer;
  4513. cnt = (uint8_t *)&icb->reserved_5 -
  4514. (uint8_t *)&icb->interrupt_delay_timer;
  4515. while (cnt--)
  4516. *dptr1++ = *dptr2++;
  4517. memcpy(icb->enode_mac, nv->enode_mac, sizeof(icb->enode_mac));
  4518. /* Some boards (with valid NVRAMs) still have NULL enode_mac!! */
  4519. if (!memcmp(icb->enode_mac, "\0\0\0\0\0\0", sizeof(icb->enode_mac))) {
  4520. icb->enode_mac[0] = 0x01;
  4521. icb->enode_mac[1] = 0x02;
  4522. icb->enode_mac[2] = 0x03;
  4523. icb->enode_mac[3] = 0x04;
  4524. icb->enode_mac[4] = 0x05;
  4525. icb->enode_mac[5] = 0x06 + ha->port_no;
  4526. }
  4527. /* Use extended-initialization control block. */
  4528. memcpy(ha->ex_init_cb, &nv->ex_version, sizeof(*ha->ex_init_cb));
  4529. /*
  4530. * Setup driver NVRAM options.
  4531. */
  4532. qla2x00_set_model_info(vha, nv->model_name, sizeof(nv->model_name),
  4533. "QLE8XXX");
  4534. /* Use alternate WWN? */
  4535. if (nv->host_p & __constant_cpu_to_le32(BIT_15)) {
  4536. memcpy(icb->node_name, nv->alternate_node_name, WWN_SIZE);
  4537. memcpy(icb->port_name, nv->alternate_port_name, WWN_SIZE);
  4538. }
  4539. /* Prepare nodename */
  4540. if ((icb->firmware_options_1 & __constant_cpu_to_le32(BIT_14)) == 0) {
  4541. /*
  4542. * Firmware will apply the following mask if the nodename was
  4543. * not provided.
  4544. */
  4545. memcpy(icb->node_name, icb->port_name, WWN_SIZE);
  4546. icb->node_name[0] &= 0xF0;
  4547. }
  4548. /* Set host adapter parameters. */
  4549. ha->flags.disable_risc_code_load = 0;
  4550. ha->flags.enable_lip_reset = 0;
  4551. ha->flags.enable_lip_full_login =
  4552. le32_to_cpu(nv->host_p) & BIT_10 ? 1: 0;
  4553. ha->flags.enable_target_reset =
  4554. le32_to_cpu(nv->host_p) & BIT_11 ? 1: 0;
  4555. ha->flags.enable_led_scheme = 0;
  4556. ha->flags.disable_serdes = le32_to_cpu(nv->host_p) & BIT_5 ? 1: 0;
  4557. ha->operating_mode = (le32_to_cpu(icb->firmware_options_2) &
  4558. (BIT_6 | BIT_5 | BIT_4)) >> 4;
  4559. /* save HBA serial number */
  4560. ha->serial0 = icb->port_name[5];
  4561. ha->serial1 = icb->port_name[6];
  4562. ha->serial2 = icb->port_name[7];
  4563. memcpy(vha->node_name, icb->node_name, WWN_SIZE);
  4564. memcpy(vha->port_name, icb->port_name, WWN_SIZE);
  4565. icb->execution_throttle = __constant_cpu_to_le16(0xFFFF);
  4566. ha->retry_count = le16_to_cpu(nv->login_retry_count);
  4567. /* Set minimum login_timeout to 4 seconds. */
  4568. if (le16_to_cpu(nv->login_timeout) < ql2xlogintimeout)
  4569. nv->login_timeout = cpu_to_le16(ql2xlogintimeout);
  4570. if (le16_to_cpu(nv->login_timeout) < 4)
  4571. nv->login_timeout = __constant_cpu_to_le16(4);
  4572. ha->login_timeout = le16_to_cpu(nv->login_timeout);
  4573. icb->login_timeout = nv->login_timeout;
  4574. /* Set minimum RATOV to 100 tenths of a second. */
  4575. ha->r_a_tov = 100;
  4576. ha->loop_reset_delay = nv->reset_delay;
  4577. /* Link Down Timeout = 0:
  4578. *
  4579. * When Port Down timer expires we will start returning
  4580. * I/O's to OS with "DID_NO_CONNECT".
  4581. *
  4582. * Link Down Timeout != 0:
  4583. *
  4584. * The driver waits for the link to come up after link down
  4585. * before returning I/Os to OS with "DID_NO_CONNECT".
  4586. */
  4587. if (le16_to_cpu(nv->link_down_timeout) == 0) {
  4588. ha->loop_down_abort_time =
  4589. (LOOP_DOWN_TIME - LOOP_DOWN_TIMEOUT);
  4590. } else {
  4591. ha->link_down_timeout = le16_to_cpu(nv->link_down_timeout);
  4592. ha->loop_down_abort_time =
  4593. (LOOP_DOWN_TIME - ha->link_down_timeout);
  4594. }
  4595. /* Need enough time to try and get the port back. */
  4596. ha->port_down_retry_count = le16_to_cpu(nv->port_down_retry_count);
  4597. if (qlport_down_retry)
  4598. ha->port_down_retry_count = qlport_down_retry;
  4599. /* Set login_retry_count */
  4600. ha->login_retry_count = le16_to_cpu(nv->login_retry_count);
  4601. if (ha->port_down_retry_count ==
  4602. le16_to_cpu(nv->port_down_retry_count) &&
  4603. ha->port_down_retry_count > 3)
  4604. ha->login_retry_count = ha->port_down_retry_count;
  4605. else if (ha->port_down_retry_count > (int)ha->login_retry_count)
  4606. ha->login_retry_count = ha->port_down_retry_count;
  4607. if (ql2xloginretrycount)
  4608. ha->login_retry_count = ql2xloginretrycount;
  4609. /* Enable ZIO. */
  4610. if (!vha->flags.init_done) {
  4611. ha->zio_mode = le32_to_cpu(icb->firmware_options_2) &
  4612. (BIT_3 | BIT_2 | BIT_1 | BIT_0);
  4613. ha->zio_timer = le16_to_cpu(icb->interrupt_delay_timer) ?
  4614. le16_to_cpu(icb->interrupt_delay_timer): 2;
  4615. }
  4616. icb->firmware_options_2 &= __constant_cpu_to_le32(
  4617. ~(BIT_3 | BIT_2 | BIT_1 | BIT_0));
  4618. vha->flags.process_response_queue = 0;
  4619. if (ha->zio_mode != QLA_ZIO_DISABLED) {
  4620. ha->zio_mode = QLA_ZIO_MODE_6;
  4621. ql_log(ql_log_info, vha, 0x0075,
  4622. "ZIO mode %d enabled; timer delay (%d us).\n",
  4623. ha->zio_mode,
  4624. ha->zio_timer * 100);
  4625. icb->firmware_options_2 |= cpu_to_le32(
  4626. (uint32_t)ha->zio_mode);
  4627. icb->interrupt_delay_timer = cpu_to_le16(ha->zio_timer);
  4628. vha->flags.process_response_queue = 1;
  4629. }
  4630. if (rval) {
  4631. ql_log(ql_log_warn, vha, 0x0076,
  4632. "NVRAM configuration failed.\n");
  4633. }
  4634. return (rval);
  4635. }
  4636. int
  4637. qla82xx_restart_isp(scsi_qla_host_t *vha)
  4638. {
  4639. int status, rval;
  4640. uint32_t wait_time;
  4641. struct qla_hw_data *ha = vha->hw;
  4642. struct req_que *req = ha->req_q_map[0];
  4643. struct rsp_que *rsp = ha->rsp_q_map[0];
  4644. struct scsi_qla_host *vp;
  4645. unsigned long flags;
  4646. status = qla2x00_init_rings(vha);
  4647. if (!status) {
  4648. clear_bit(RESET_MARKER_NEEDED, &vha->dpc_flags);
  4649. ha->flags.chip_reset_done = 1;
  4650. status = qla2x00_fw_ready(vha);
  4651. if (!status) {
  4652. ql_log(ql_log_info, vha, 0x803c,
  4653. "Start configure loop, status =%d.\n", status);
  4654. /* Issue a marker after FW becomes ready. */
  4655. qla2x00_marker(vha, req, rsp, 0, 0, MK_SYNC_ALL);
  4656. vha->flags.online = 1;
  4657. /* Wait at most MAX_TARGET RSCNs for a stable link. */
  4658. wait_time = 256;
  4659. do {
  4660. clear_bit(LOOP_RESYNC_NEEDED, &vha->dpc_flags);
  4661. qla2x00_configure_loop(vha);
  4662. wait_time--;
  4663. } while (!atomic_read(&vha->loop_down_timer) &&
  4664. !(test_bit(ISP_ABORT_NEEDED, &vha->dpc_flags)) &&
  4665. wait_time &&
  4666. (test_bit(LOOP_RESYNC_NEEDED, &vha->dpc_flags)));
  4667. }
  4668. /* if no cable then assume it's good */
  4669. if ((vha->device_flags & DFLG_NO_CABLE))
  4670. status = 0;
  4671. ql_log(ql_log_info, vha, 0x803d,
  4672. "Configure loop done, status = 0x%x.\n", status);
  4673. }
  4674. if (!status) {
  4675. clear_bit(RESET_MARKER_NEEDED, &vha->dpc_flags);
  4676. if (!atomic_read(&vha->loop_down_timer)) {
  4677. /*
  4678. * Issue marker command only when we are going
  4679. * to start the I/O .
  4680. */
  4681. vha->marker_needed = 1;
  4682. }
  4683. vha->flags.online = 1;
  4684. ha->isp_ops->enable_intrs(ha);
  4685. ha->isp_abort_cnt = 0;
  4686. clear_bit(ISP_ABORT_RETRY, &vha->dpc_flags);
  4687. /* Update the firmware version */
  4688. status = qla82xx_check_md_needed(vha);
  4689. if (ha->fce) {
  4690. ha->flags.fce_enabled = 1;
  4691. memset(ha->fce, 0,
  4692. fce_calc_size(ha->fce_bufs));
  4693. rval = qla2x00_enable_fce_trace(vha,
  4694. ha->fce_dma, ha->fce_bufs, ha->fce_mb,
  4695. &ha->fce_bufs);
  4696. if (rval) {
  4697. ql_log(ql_log_warn, vha, 0x803e,
  4698. "Unable to reinitialize FCE (%d).\n",
  4699. rval);
  4700. ha->flags.fce_enabled = 0;
  4701. }
  4702. }
  4703. if (ha->eft) {
  4704. memset(ha->eft, 0, EFT_SIZE);
  4705. rval = qla2x00_enable_eft_trace(vha,
  4706. ha->eft_dma, EFT_NUM_BUFFERS);
  4707. if (rval) {
  4708. ql_log(ql_log_warn, vha, 0x803f,
  4709. "Unable to reinitialize EFT (%d).\n",
  4710. rval);
  4711. }
  4712. }
  4713. }
  4714. if (!status) {
  4715. ql_dbg(ql_dbg_taskm, vha, 0x8040,
  4716. "qla82xx_restart_isp succeeded.\n");
  4717. spin_lock_irqsave(&ha->vport_slock, flags);
  4718. list_for_each_entry(vp, &ha->vp_list, list) {
  4719. if (vp->vp_idx) {
  4720. atomic_inc(&vp->vref_count);
  4721. spin_unlock_irqrestore(&ha->vport_slock, flags);
  4722. qla2x00_vp_abort_isp(vp);
  4723. spin_lock_irqsave(&ha->vport_slock, flags);
  4724. atomic_dec(&vp->vref_count);
  4725. }
  4726. }
  4727. spin_unlock_irqrestore(&ha->vport_slock, flags);
  4728. } else {
  4729. ql_log(ql_log_warn, vha, 0x8041,
  4730. "qla82xx_restart_isp **** FAILED ****.\n");
  4731. }
  4732. return status;
  4733. }
  4734. void
  4735. qla81xx_update_fw_options(scsi_qla_host_t *vha)
  4736. {
  4737. struct qla_hw_data *ha = vha->hw;
  4738. if (!ql2xetsenable)
  4739. return;
  4740. /* Enable ETS Burst. */
  4741. memset(ha->fw_options, 0, sizeof(ha->fw_options));
  4742. ha->fw_options[2] |= BIT_9;
  4743. qla2x00_set_fw_options(vha, ha->fw_options);
  4744. }
  4745. /*
  4746. * qla24xx_get_fcp_prio
  4747. * Gets the fcp cmd priority value for the logged in port.
  4748. * Looks for a match of the port descriptors within
  4749. * each of the fcp prio config entries. If a match is found,
  4750. * the tag (priority) value is returned.
  4751. *
  4752. * Input:
  4753. * vha = scsi host structure pointer.
  4754. * fcport = port structure pointer.
  4755. *
  4756. * Return:
  4757. * non-zero (if found)
  4758. * -1 (if not found)
  4759. *
  4760. * Context:
  4761. * Kernel context
  4762. */
  4763. static int
  4764. qla24xx_get_fcp_prio(scsi_qla_host_t *vha, fc_port_t *fcport)
  4765. {
  4766. int i, entries;
  4767. uint8_t pid_match, wwn_match;
  4768. int priority;
  4769. uint32_t pid1, pid2;
  4770. uint64_t wwn1, wwn2;
  4771. struct qla_fcp_prio_entry *pri_entry;
  4772. struct qla_hw_data *ha = vha->hw;
  4773. if (!ha->fcp_prio_cfg || !ha->flags.fcp_prio_enabled)
  4774. return -1;
  4775. priority = -1;
  4776. entries = ha->fcp_prio_cfg->num_entries;
  4777. pri_entry = &ha->fcp_prio_cfg->entry[0];
  4778. for (i = 0; i < entries; i++) {
  4779. pid_match = wwn_match = 0;
  4780. if (!(pri_entry->flags & FCP_PRIO_ENTRY_VALID)) {
  4781. pri_entry++;
  4782. continue;
  4783. }
  4784. /* check source pid for a match */
  4785. if (pri_entry->flags & FCP_PRIO_ENTRY_SPID_VALID) {
  4786. pid1 = pri_entry->src_pid & INVALID_PORT_ID;
  4787. pid2 = vha->d_id.b24 & INVALID_PORT_ID;
  4788. if (pid1 == INVALID_PORT_ID)
  4789. pid_match++;
  4790. else if (pid1 == pid2)
  4791. pid_match++;
  4792. }
  4793. /* check destination pid for a match */
  4794. if (pri_entry->flags & FCP_PRIO_ENTRY_DPID_VALID) {
  4795. pid1 = pri_entry->dst_pid & INVALID_PORT_ID;
  4796. pid2 = fcport->d_id.b24 & INVALID_PORT_ID;
  4797. if (pid1 == INVALID_PORT_ID)
  4798. pid_match++;
  4799. else if (pid1 == pid2)
  4800. pid_match++;
  4801. }
  4802. /* check source WWN for a match */
  4803. if (pri_entry->flags & FCP_PRIO_ENTRY_SWWN_VALID) {
  4804. wwn1 = wwn_to_u64(vha->port_name);
  4805. wwn2 = wwn_to_u64(pri_entry->src_wwpn);
  4806. if (wwn2 == (uint64_t)-1)
  4807. wwn_match++;
  4808. else if (wwn1 == wwn2)
  4809. wwn_match++;
  4810. }
  4811. /* check destination WWN for a match */
  4812. if (pri_entry->flags & FCP_PRIO_ENTRY_DWWN_VALID) {
  4813. wwn1 = wwn_to_u64(fcport->port_name);
  4814. wwn2 = wwn_to_u64(pri_entry->dst_wwpn);
  4815. if (wwn2 == (uint64_t)-1)
  4816. wwn_match++;
  4817. else if (wwn1 == wwn2)
  4818. wwn_match++;
  4819. }
  4820. if (pid_match == 2 || wwn_match == 2) {
  4821. /* Found a matching entry */
  4822. if (pri_entry->flags & FCP_PRIO_ENTRY_TAG_VALID)
  4823. priority = pri_entry->tag;
  4824. break;
  4825. }
  4826. pri_entry++;
  4827. }
  4828. return priority;
  4829. }
  4830. /*
  4831. * qla24xx_update_fcport_fcp_prio
  4832. * Activates fcp priority for the logged in fc port
  4833. *
  4834. * Input:
  4835. * vha = scsi host structure pointer.
  4836. * fcp = port structure pointer.
  4837. *
  4838. * Return:
  4839. * QLA_SUCCESS or QLA_FUNCTION_FAILED
  4840. *
  4841. * Context:
  4842. * Kernel context.
  4843. */
  4844. int
  4845. qla24xx_update_fcport_fcp_prio(scsi_qla_host_t *vha, fc_port_t *fcport)
  4846. {
  4847. int ret;
  4848. int priority;
  4849. uint16_t mb[5];
  4850. if (fcport->port_type != FCT_TARGET ||
  4851. fcport->loop_id == FC_NO_LOOP_ID)
  4852. return QLA_FUNCTION_FAILED;
  4853. priority = qla24xx_get_fcp_prio(vha, fcport);
  4854. if (priority < 0)
  4855. return QLA_FUNCTION_FAILED;
  4856. ret = qla24xx_set_fcp_prio(vha, fcport->loop_id, priority, mb);
  4857. if (ret == QLA_SUCCESS)
  4858. fcport->fcp_prio = priority;
  4859. else
  4860. ql_dbg(ql_dbg_user, vha, 0x704f,
  4861. "Unable to activate fcp priority, ret=0x%x.\n", ret);
  4862. return ret;
  4863. }
  4864. /*
  4865. * qla24xx_update_all_fcp_prio
  4866. * Activates fcp priority for all the logged in ports
  4867. *
  4868. * Input:
  4869. * ha = adapter block pointer.
  4870. *
  4871. * Return:
  4872. * QLA_SUCCESS or QLA_FUNCTION_FAILED
  4873. *
  4874. * Context:
  4875. * Kernel context.
  4876. */
  4877. int
  4878. qla24xx_update_all_fcp_prio(scsi_qla_host_t *vha)
  4879. {
  4880. int ret;
  4881. fc_port_t *fcport;
  4882. ret = QLA_FUNCTION_FAILED;
  4883. /* We need to set priority for all logged in ports */
  4884. list_for_each_entry(fcport, &vha->vp_fcports, list)
  4885. ret = qla24xx_update_fcport_fcp_prio(vha, fcport);
  4886. return ret;
  4887. }