qeth_core_main.c 149 KB

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  1. /*
  2. * drivers/s390/net/qeth_core_main.c
  3. *
  4. * Copyright IBM Corp. 2007, 2009
  5. * Author(s): Utz Bacher <utz.bacher@de.ibm.com>,
  6. * Frank Pavlic <fpavlic@de.ibm.com>,
  7. * Thomas Spatzier <tspat@de.ibm.com>,
  8. * Frank Blaschka <frank.blaschka@de.ibm.com>
  9. */
  10. #define KMSG_COMPONENT "qeth"
  11. #define pr_fmt(fmt) KMSG_COMPONENT ": " fmt
  12. #include <linux/module.h>
  13. #include <linux/moduleparam.h>
  14. #include <linux/string.h>
  15. #include <linux/errno.h>
  16. #include <linux/kernel.h>
  17. #include <linux/ip.h>
  18. #include <linux/tcp.h>
  19. #include <linux/mii.h>
  20. #include <linux/kthread.h>
  21. #include <linux/slab.h>
  22. #include <net/iucv/af_iucv.h>
  23. #include <asm/ebcdic.h>
  24. #include <asm/io.h>
  25. #include <asm/sysinfo.h>
  26. #include "qeth_core.h"
  27. struct qeth_dbf_info qeth_dbf[QETH_DBF_INFOS] = {
  28. /* define dbf - Name, Pages, Areas, Maxlen, Level, View, Handle */
  29. /* N P A M L V H */
  30. [QETH_DBF_SETUP] = {"qeth_setup",
  31. 8, 1, 8, 5, &debug_hex_ascii_view, NULL},
  32. [QETH_DBF_MSG] = {"qeth_msg",
  33. 8, 1, 128, 3, &debug_sprintf_view, NULL},
  34. [QETH_DBF_CTRL] = {"qeth_control",
  35. 8, 1, QETH_DBF_CTRL_LEN, 5, &debug_hex_ascii_view, NULL},
  36. };
  37. EXPORT_SYMBOL_GPL(qeth_dbf);
  38. struct qeth_card_list_struct qeth_core_card_list;
  39. EXPORT_SYMBOL_GPL(qeth_core_card_list);
  40. struct kmem_cache *qeth_core_header_cache;
  41. EXPORT_SYMBOL_GPL(qeth_core_header_cache);
  42. static struct kmem_cache *qeth_qdio_outbuf_cache;
  43. static struct device *qeth_core_root_dev;
  44. static unsigned int known_devices[][6] = QETH_MODELLIST_ARRAY;
  45. static struct lock_class_key qdio_out_skb_queue_key;
  46. static void qeth_send_control_data_cb(struct qeth_channel *,
  47. struct qeth_cmd_buffer *);
  48. static int qeth_issue_next_read(struct qeth_card *);
  49. static struct qeth_cmd_buffer *qeth_get_buffer(struct qeth_channel *);
  50. static void qeth_setup_ccw(struct qeth_channel *, unsigned char *, __u32);
  51. static void qeth_free_buffer_pool(struct qeth_card *);
  52. static int qeth_qdio_establish(struct qeth_card *);
  53. static void qeth_free_qdio_buffers(struct qeth_card *);
  54. static void qeth_notify_skbs(struct qeth_qdio_out_q *queue,
  55. struct qeth_qdio_out_buffer *buf,
  56. enum iucv_tx_notify notification);
  57. static void qeth_release_skbs(struct qeth_qdio_out_buffer *buf);
  58. static void qeth_clear_output_buffer(struct qeth_qdio_out_q *queue,
  59. struct qeth_qdio_out_buffer *buf,
  60. enum qeth_qdio_buffer_states newbufstate);
  61. static inline const char *qeth_get_cardname(struct qeth_card *card)
  62. {
  63. if (card->info.guestlan) {
  64. switch (card->info.type) {
  65. case QETH_CARD_TYPE_OSD:
  66. return " Guest LAN QDIO";
  67. case QETH_CARD_TYPE_IQD:
  68. return " Guest LAN Hiper";
  69. case QETH_CARD_TYPE_OSM:
  70. return " Guest LAN QDIO - OSM";
  71. case QETH_CARD_TYPE_OSX:
  72. return " Guest LAN QDIO - OSX";
  73. default:
  74. return " unknown";
  75. }
  76. } else {
  77. switch (card->info.type) {
  78. case QETH_CARD_TYPE_OSD:
  79. return " OSD Express";
  80. case QETH_CARD_TYPE_IQD:
  81. return " HiperSockets";
  82. case QETH_CARD_TYPE_OSN:
  83. return " OSN QDIO";
  84. case QETH_CARD_TYPE_OSM:
  85. return " OSM QDIO";
  86. case QETH_CARD_TYPE_OSX:
  87. return " OSX QDIO";
  88. default:
  89. return " unknown";
  90. }
  91. }
  92. return " n/a";
  93. }
  94. /* max length to be returned: 14 */
  95. const char *qeth_get_cardname_short(struct qeth_card *card)
  96. {
  97. if (card->info.guestlan) {
  98. switch (card->info.type) {
  99. case QETH_CARD_TYPE_OSD:
  100. return "GuestLAN QDIO";
  101. case QETH_CARD_TYPE_IQD:
  102. return "GuestLAN Hiper";
  103. case QETH_CARD_TYPE_OSM:
  104. return "GuestLAN OSM";
  105. case QETH_CARD_TYPE_OSX:
  106. return "GuestLAN OSX";
  107. default:
  108. return "unknown";
  109. }
  110. } else {
  111. switch (card->info.type) {
  112. case QETH_CARD_TYPE_OSD:
  113. switch (card->info.link_type) {
  114. case QETH_LINK_TYPE_FAST_ETH:
  115. return "OSD_100";
  116. case QETH_LINK_TYPE_HSTR:
  117. return "HSTR";
  118. case QETH_LINK_TYPE_GBIT_ETH:
  119. return "OSD_1000";
  120. case QETH_LINK_TYPE_10GBIT_ETH:
  121. return "OSD_10GIG";
  122. case QETH_LINK_TYPE_LANE_ETH100:
  123. return "OSD_FE_LANE";
  124. case QETH_LINK_TYPE_LANE_TR:
  125. return "OSD_TR_LANE";
  126. case QETH_LINK_TYPE_LANE_ETH1000:
  127. return "OSD_GbE_LANE";
  128. case QETH_LINK_TYPE_LANE:
  129. return "OSD_ATM_LANE";
  130. default:
  131. return "OSD_Express";
  132. }
  133. case QETH_CARD_TYPE_IQD:
  134. return "HiperSockets";
  135. case QETH_CARD_TYPE_OSN:
  136. return "OSN";
  137. case QETH_CARD_TYPE_OSM:
  138. return "OSM_1000";
  139. case QETH_CARD_TYPE_OSX:
  140. return "OSX_10GIG";
  141. default:
  142. return "unknown";
  143. }
  144. }
  145. return "n/a";
  146. }
  147. void qeth_set_allowed_threads(struct qeth_card *card, unsigned long threads,
  148. int clear_start_mask)
  149. {
  150. unsigned long flags;
  151. spin_lock_irqsave(&card->thread_mask_lock, flags);
  152. card->thread_allowed_mask = threads;
  153. if (clear_start_mask)
  154. card->thread_start_mask &= threads;
  155. spin_unlock_irqrestore(&card->thread_mask_lock, flags);
  156. wake_up(&card->wait_q);
  157. }
  158. EXPORT_SYMBOL_GPL(qeth_set_allowed_threads);
  159. int qeth_threads_running(struct qeth_card *card, unsigned long threads)
  160. {
  161. unsigned long flags;
  162. int rc = 0;
  163. spin_lock_irqsave(&card->thread_mask_lock, flags);
  164. rc = (card->thread_running_mask & threads);
  165. spin_unlock_irqrestore(&card->thread_mask_lock, flags);
  166. return rc;
  167. }
  168. EXPORT_SYMBOL_GPL(qeth_threads_running);
  169. int qeth_wait_for_threads(struct qeth_card *card, unsigned long threads)
  170. {
  171. return wait_event_interruptible(card->wait_q,
  172. qeth_threads_running(card, threads) == 0);
  173. }
  174. EXPORT_SYMBOL_GPL(qeth_wait_for_threads);
  175. void qeth_clear_working_pool_list(struct qeth_card *card)
  176. {
  177. struct qeth_buffer_pool_entry *pool_entry, *tmp;
  178. QETH_CARD_TEXT(card, 5, "clwrklst");
  179. list_for_each_entry_safe(pool_entry, tmp,
  180. &card->qdio.in_buf_pool.entry_list, list){
  181. list_del(&pool_entry->list);
  182. }
  183. }
  184. EXPORT_SYMBOL_GPL(qeth_clear_working_pool_list);
  185. static int qeth_alloc_buffer_pool(struct qeth_card *card)
  186. {
  187. struct qeth_buffer_pool_entry *pool_entry;
  188. void *ptr;
  189. int i, j;
  190. QETH_CARD_TEXT(card, 5, "alocpool");
  191. for (i = 0; i < card->qdio.init_pool.buf_count; ++i) {
  192. pool_entry = kzalloc(sizeof(*pool_entry), GFP_KERNEL);
  193. if (!pool_entry) {
  194. qeth_free_buffer_pool(card);
  195. return -ENOMEM;
  196. }
  197. for (j = 0; j < QETH_MAX_BUFFER_ELEMENTS(card); ++j) {
  198. ptr = (void *) __get_free_page(GFP_KERNEL);
  199. if (!ptr) {
  200. while (j > 0)
  201. free_page((unsigned long)
  202. pool_entry->elements[--j]);
  203. kfree(pool_entry);
  204. qeth_free_buffer_pool(card);
  205. return -ENOMEM;
  206. }
  207. pool_entry->elements[j] = ptr;
  208. }
  209. list_add(&pool_entry->init_list,
  210. &card->qdio.init_pool.entry_list);
  211. }
  212. return 0;
  213. }
  214. int qeth_realloc_buffer_pool(struct qeth_card *card, int bufcnt)
  215. {
  216. QETH_CARD_TEXT(card, 2, "realcbp");
  217. if ((card->state != CARD_STATE_DOWN) &&
  218. (card->state != CARD_STATE_RECOVER))
  219. return -EPERM;
  220. /* TODO: steel/add buffers from/to a running card's buffer pool (?) */
  221. qeth_clear_working_pool_list(card);
  222. qeth_free_buffer_pool(card);
  223. card->qdio.in_buf_pool.buf_count = bufcnt;
  224. card->qdio.init_pool.buf_count = bufcnt;
  225. return qeth_alloc_buffer_pool(card);
  226. }
  227. EXPORT_SYMBOL_GPL(qeth_realloc_buffer_pool);
  228. static inline int qeth_cq_init(struct qeth_card *card)
  229. {
  230. int rc;
  231. if (card->options.cq == QETH_CQ_ENABLED) {
  232. QETH_DBF_TEXT(SETUP, 2, "cqinit");
  233. memset(card->qdio.c_q->qdio_bufs, 0,
  234. QDIO_MAX_BUFFERS_PER_Q * sizeof(struct qdio_buffer));
  235. card->qdio.c_q->next_buf_to_init = 127;
  236. rc = do_QDIO(CARD_DDEV(card), QDIO_FLAG_SYNC_INPUT,
  237. card->qdio.no_in_queues - 1, 0,
  238. 127);
  239. if (rc) {
  240. QETH_DBF_TEXT_(SETUP, 2, "1err%d", rc);
  241. goto out;
  242. }
  243. }
  244. rc = 0;
  245. out:
  246. return rc;
  247. }
  248. static inline int qeth_alloc_cq(struct qeth_card *card)
  249. {
  250. int rc;
  251. if (card->options.cq == QETH_CQ_ENABLED) {
  252. int i;
  253. struct qdio_outbuf_state *outbuf_states;
  254. QETH_DBF_TEXT(SETUP, 2, "cqon");
  255. card->qdio.c_q = kzalloc(sizeof(struct qeth_qdio_q),
  256. GFP_KERNEL);
  257. if (!card->qdio.c_q) {
  258. rc = -1;
  259. goto kmsg_out;
  260. }
  261. QETH_DBF_HEX(SETUP, 2, &card->qdio.c_q, sizeof(void *));
  262. for (i = 0; i < QDIO_MAX_BUFFERS_PER_Q; ++i) {
  263. card->qdio.c_q->bufs[i].buffer =
  264. &card->qdio.c_q->qdio_bufs[i];
  265. }
  266. card->qdio.no_in_queues = 2;
  267. card->qdio.out_bufstates = (struct qdio_outbuf_state *)
  268. kzalloc(card->qdio.no_out_queues *
  269. QDIO_MAX_BUFFERS_PER_Q *
  270. sizeof(struct qdio_outbuf_state), GFP_KERNEL);
  271. outbuf_states = card->qdio.out_bufstates;
  272. if (outbuf_states == NULL) {
  273. rc = -1;
  274. goto free_cq_out;
  275. }
  276. for (i = 0; i < card->qdio.no_out_queues; ++i) {
  277. card->qdio.out_qs[i]->bufstates = outbuf_states;
  278. outbuf_states += QDIO_MAX_BUFFERS_PER_Q;
  279. }
  280. } else {
  281. QETH_DBF_TEXT(SETUP, 2, "nocq");
  282. card->qdio.c_q = NULL;
  283. card->qdio.no_in_queues = 1;
  284. }
  285. QETH_DBF_TEXT_(SETUP, 2, "iqc%d", card->qdio.no_in_queues);
  286. rc = 0;
  287. out:
  288. return rc;
  289. free_cq_out:
  290. kfree(card->qdio.c_q);
  291. card->qdio.c_q = NULL;
  292. kmsg_out:
  293. dev_err(&card->gdev->dev, "Failed to create completion queue\n");
  294. goto out;
  295. }
  296. static inline void qeth_free_cq(struct qeth_card *card)
  297. {
  298. if (card->qdio.c_q) {
  299. --card->qdio.no_in_queues;
  300. kfree(card->qdio.c_q);
  301. card->qdio.c_q = NULL;
  302. }
  303. kfree(card->qdio.out_bufstates);
  304. card->qdio.out_bufstates = NULL;
  305. }
  306. static inline enum iucv_tx_notify qeth_compute_cq_notification(int sbalf15,
  307. int delayed) {
  308. enum iucv_tx_notify n;
  309. switch (sbalf15) {
  310. case 0:
  311. n = delayed ? TX_NOTIFY_DELAYED_OK : TX_NOTIFY_OK;
  312. break;
  313. case 4:
  314. case 16:
  315. case 17:
  316. case 18:
  317. n = delayed ? TX_NOTIFY_DELAYED_UNREACHABLE :
  318. TX_NOTIFY_UNREACHABLE;
  319. break;
  320. default:
  321. n = delayed ? TX_NOTIFY_DELAYED_GENERALERROR :
  322. TX_NOTIFY_GENERALERROR;
  323. break;
  324. }
  325. return n;
  326. }
  327. static inline void qeth_cleanup_handled_pending(struct qeth_qdio_out_q *q,
  328. int bidx, int forced_cleanup)
  329. {
  330. if (q->bufs[bidx]->next_pending != NULL) {
  331. struct qeth_qdio_out_buffer *head = q->bufs[bidx];
  332. struct qeth_qdio_out_buffer *c = q->bufs[bidx]->next_pending;
  333. while (c) {
  334. if (forced_cleanup ||
  335. atomic_read(&c->state) ==
  336. QETH_QDIO_BUF_HANDLED_DELAYED) {
  337. struct qeth_qdio_out_buffer *f = c;
  338. QETH_CARD_TEXT(f->q->card, 5, "fp");
  339. QETH_CARD_TEXT_(f->q->card, 5, "%lx", (long) f);
  340. /* release here to avoid interleaving between
  341. outbound tasklet and inbound tasklet
  342. regarding notifications and lifecycle */
  343. qeth_release_skbs(c);
  344. c = f->next_pending;
  345. BUG_ON(head->next_pending != f);
  346. head->next_pending = c;
  347. kmem_cache_free(qeth_qdio_outbuf_cache, f);
  348. } else {
  349. head = c;
  350. c = c->next_pending;
  351. }
  352. }
  353. }
  354. }
  355. static inline void qeth_qdio_handle_aob(struct qeth_card *card,
  356. unsigned long phys_aob_addr) {
  357. struct qaob *aob;
  358. struct qeth_qdio_out_buffer *buffer;
  359. enum iucv_tx_notify notification;
  360. aob = (struct qaob *) phys_to_virt(phys_aob_addr);
  361. QETH_CARD_TEXT(card, 5, "haob");
  362. QETH_CARD_TEXT_(card, 5, "%lx", phys_aob_addr);
  363. buffer = (struct qeth_qdio_out_buffer *) aob->user1;
  364. QETH_CARD_TEXT_(card, 5, "%lx", aob->user1);
  365. BUG_ON(buffer == NULL);
  366. if (atomic_cmpxchg(&buffer->state, QETH_QDIO_BUF_PRIMED,
  367. QETH_QDIO_BUF_IN_CQ) == QETH_QDIO_BUF_PRIMED) {
  368. notification = TX_NOTIFY_OK;
  369. } else {
  370. BUG_ON(atomic_read(&buffer->state) != QETH_QDIO_BUF_PENDING);
  371. atomic_set(&buffer->state, QETH_QDIO_BUF_IN_CQ);
  372. notification = TX_NOTIFY_DELAYED_OK;
  373. }
  374. if (aob->aorc != 0) {
  375. QETH_CARD_TEXT_(card, 2, "aorc%02X", aob->aorc);
  376. notification = qeth_compute_cq_notification(aob->aorc, 1);
  377. }
  378. qeth_notify_skbs(buffer->q, buffer, notification);
  379. buffer->aob = NULL;
  380. qeth_clear_output_buffer(buffer->q, buffer,
  381. QETH_QDIO_BUF_HANDLED_DELAYED);
  382. /* from here on: do not touch buffer anymore */
  383. qdio_release_aob(aob);
  384. }
  385. static inline int qeth_is_cq(struct qeth_card *card, unsigned int queue)
  386. {
  387. return card->options.cq == QETH_CQ_ENABLED &&
  388. card->qdio.c_q != NULL &&
  389. queue != 0 &&
  390. queue == card->qdio.no_in_queues - 1;
  391. }
  392. static int qeth_issue_next_read(struct qeth_card *card)
  393. {
  394. int rc;
  395. struct qeth_cmd_buffer *iob;
  396. QETH_CARD_TEXT(card, 5, "issnxrd");
  397. if (card->read.state != CH_STATE_UP)
  398. return -EIO;
  399. iob = qeth_get_buffer(&card->read);
  400. if (!iob) {
  401. dev_warn(&card->gdev->dev, "The qeth device driver "
  402. "failed to recover an error on the device\n");
  403. QETH_DBF_MESSAGE(2, "%s issue_next_read failed: no iob "
  404. "available\n", dev_name(&card->gdev->dev));
  405. return -ENOMEM;
  406. }
  407. qeth_setup_ccw(&card->read, iob->data, QETH_BUFSIZE);
  408. QETH_CARD_TEXT(card, 6, "noirqpnd");
  409. rc = ccw_device_start(card->read.ccwdev, &card->read.ccw,
  410. (addr_t) iob, 0, 0);
  411. if (rc) {
  412. QETH_DBF_MESSAGE(2, "%s error in starting next read ccw! "
  413. "rc=%i\n", dev_name(&card->gdev->dev), rc);
  414. atomic_set(&card->read.irq_pending, 0);
  415. card->read_or_write_problem = 1;
  416. qeth_schedule_recovery(card);
  417. wake_up(&card->wait_q);
  418. }
  419. return rc;
  420. }
  421. static struct qeth_reply *qeth_alloc_reply(struct qeth_card *card)
  422. {
  423. struct qeth_reply *reply;
  424. reply = kzalloc(sizeof(struct qeth_reply), GFP_ATOMIC);
  425. if (reply) {
  426. atomic_set(&reply->refcnt, 1);
  427. atomic_set(&reply->received, 0);
  428. reply->card = card;
  429. };
  430. return reply;
  431. }
  432. static void qeth_get_reply(struct qeth_reply *reply)
  433. {
  434. WARN_ON(atomic_read(&reply->refcnt) <= 0);
  435. atomic_inc(&reply->refcnt);
  436. }
  437. static void qeth_put_reply(struct qeth_reply *reply)
  438. {
  439. WARN_ON(atomic_read(&reply->refcnt) <= 0);
  440. if (atomic_dec_and_test(&reply->refcnt))
  441. kfree(reply);
  442. }
  443. static void qeth_issue_ipa_msg(struct qeth_ipa_cmd *cmd, int rc,
  444. struct qeth_card *card)
  445. {
  446. char *ipa_name;
  447. int com = cmd->hdr.command;
  448. ipa_name = qeth_get_ipa_cmd_name(com);
  449. if (rc)
  450. QETH_DBF_MESSAGE(2, "IPA: %s(x%X) for %s/%s returned "
  451. "x%X \"%s\"\n",
  452. ipa_name, com, dev_name(&card->gdev->dev),
  453. QETH_CARD_IFNAME(card), rc,
  454. qeth_get_ipa_msg(rc));
  455. else
  456. QETH_DBF_MESSAGE(5, "IPA: %s(x%X) for %s/%s succeeded\n",
  457. ipa_name, com, dev_name(&card->gdev->dev),
  458. QETH_CARD_IFNAME(card));
  459. }
  460. static struct qeth_ipa_cmd *qeth_check_ipa_data(struct qeth_card *card,
  461. struct qeth_cmd_buffer *iob)
  462. {
  463. struct qeth_ipa_cmd *cmd = NULL;
  464. QETH_CARD_TEXT(card, 5, "chkipad");
  465. if (IS_IPA(iob->data)) {
  466. cmd = (struct qeth_ipa_cmd *) PDU_ENCAPSULATION(iob->data);
  467. if (IS_IPA_REPLY(cmd)) {
  468. if (cmd->hdr.command != IPA_CMD_SETCCID &&
  469. cmd->hdr.command != IPA_CMD_DELCCID &&
  470. cmd->hdr.command != IPA_CMD_MODCCID &&
  471. cmd->hdr.command != IPA_CMD_SET_DIAG_ASS)
  472. qeth_issue_ipa_msg(cmd,
  473. cmd->hdr.return_code, card);
  474. return cmd;
  475. } else {
  476. switch (cmd->hdr.command) {
  477. case IPA_CMD_STOPLAN:
  478. dev_warn(&card->gdev->dev,
  479. "The link for interface %s on CHPID"
  480. " 0x%X failed\n",
  481. QETH_CARD_IFNAME(card),
  482. card->info.chpid);
  483. card->lan_online = 0;
  484. if (card->dev && netif_carrier_ok(card->dev))
  485. netif_carrier_off(card->dev);
  486. return NULL;
  487. case IPA_CMD_STARTLAN:
  488. dev_info(&card->gdev->dev,
  489. "The link for %s on CHPID 0x%X has"
  490. " been restored\n",
  491. QETH_CARD_IFNAME(card),
  492. card->info.chpid);
  493. netif_carrier_on(card->dev);
  494. card->lan_online = 1;
  495. if (card->info.hwtrap)
  496. card->info.hwtrap = 2;
  497. qeth_schedule_recovery(card);
  498. return NULL;
  499. case IPA_CMD_MODCCID:
  500. return cmd;
  501. case IPA_CMD_REGISTER_LOCAL_ADDR:
  502. QETH_CARD_TEXT(card, 3, "irla");
  503. break;
  504. case IPA_CMD_UNREGISTER_LOCAL_ADDR:
  505. QETH_CARD_TEXT(card, 3, "urla");
  506. break;
  507. default:
  508. QETH_DBF_MESSAGE(2, "Received data is IPA "
  509. "but not a reply!\n");
  510. break;
  511. }
  512. }
  513. }
  514. return cmd;
  515. }
  516. void qeth_clear_ipacmd_list(struct qeth_card *card)
  517. {
  518. struct qeth_reply *reply, *r;
  519. unsigned long flags;
  520. QETH_CARD_TEXT(card, 4, "clipalst");
  521. spin_lock_irqsave(&card->lock, flags);
  522. list_for_each_entry_safe(reply, r, &card->cmd_waiter_list, list) {
  523. qeth_get_reply(reply);
  524. reply->rc = -EIO;
  525. atomic_inc(&reply->received);
  526. list_del_init(&reply->list);
  527. wake_up(&reply->wait_q);
  528. qeth_put_reply(reply);
  529. }
  530. spin_unlock_irqrestore(&card->lock, flags);
  531. atomic_set(&card->write.irq_pending, 0);
  532. }
  533. EXPORT_SYMBOL_GPL(qeth_clear_ipacmd_list);
  534. static int qeth_check_idx_response(struct qeth_card *card,
  535. unsigned char *buffer)
  536. {
  537. if (!buffer)
  538. return 0;
  539. QETH_DBF_HEX(CTRL, 2, buffer, QETH_DBF_CTRL_LEN);
  540. if ((buffer[2] & 0xc0) == 0xc0) {
  541. QETH_DBF_MESSAGE(2, "received an IDX TERMINATE "
  542. "with cause code 0x%02x%s\n",
  543. buffer[4],
  544. ((buffer[4] == 0x22) ?
  545. " -- try another portname" : ""));
  546. QETH_CARD_TEXT(card, 2, "ckidxres");
  547. QETH_CARD_TEXT(card, 2, " idxterm");
  548. QETH_CARD_TEXT_(card, 2, " rc%d", -EIO);
  549. if (buffer[4] == 0xf6) {
  550. dev_err(&card->gdev->dev,
  551. "The qeth device is not configured "
  552. "for the OSI layer required by z/VM\n");
  553. return -EPERM;
  554. }
  555. return -EIO;
  556. }
  557. return 0;
  558. }
  559. static void qeth_setup_ccw(struct qeth_channel *channel, unsigned char *iob,
  560. __u32 len)
  561. {
  562. struct qeth_card *card;
  563. card = CARD_FROM_CDEV(channel->ccwdev);
  564. QETH_CARD_TEXT(card, 4, "setupccw");
  565. if (channel == &card->read)
  566. memcpy(&channel->ccw, READ_CCW, sizeof(struct ccw1));
  567. else
  568. memcpy(&channel->ccw, WRITE_CCW, sizeof(struct ccw1));
  569. channel->ccw.count = len;
  570. channel->ccw.cda = (__u32) __pa(iob);
  571. }
  572. static struct qeth_cmd_buffer *__qeth_get_buffer(struct qeth_channel *channel)
  573. {
  574. __u8 index;
  575. QETH_CARD_TEXT(CARD_FROM_CDEV(channel->ccwdev), 6, "getbuff");
  576. index = channel->io_buf_no;
  577. do {
  578. if (channel->iob[index].state == BUF_STATE_FREE) {
  579. channel->iob[index].state = BUF_STATE_LOCKED;
  580. channel->io_buf_no = (channel->io_buf_no + 1) %
  581. QETH_CMD_BUFFER_NO;
  582. memset(channel->iob[index].data, 0, QETH_BUFSIZE);
  583. return channel->iob + index;
  584. }
  585. index = (index + 1) % QETH_CMD_BUFFER_NO;
  586. } while (index != channel->io_buf_no);
  587. return NULL;
  588. }
  589. void qeth_release_buffer(struct qeth_channel *channel,
  590. struct qeth_cmd_buffer *iob)
  591. {
  592. unsigned long flags;
  593. QETH_CARD_TEXT(CARD_FROM_CDEV(channel->ccwdev), 6, "relbuff");
  594. spin_lock_irqsave(&channel->iob_lock, flags);
  595. memset(iob->data, 0, QETH_BUFSIZE);
  596. iob->state = BUF_STATE_FREE;
  597. iob->callback = qeth_send_control_data_cb;
  598. iob->rc = 0;
  599. spin_unlock_irqrestore(&channel->iob_lock, flags);
  600. }
  601. EXPORT_SYMBOL_GPL(qeth_release_buffer);
  602. static struct qeth_cmd_buffer *qeth_get_buffer(struct qeth_channel *channel)
  603. {
  604. struct qeth_cmd_buffer *buffer = NULL;
  605. unsigned long flags;
  606. spin_lock_irqsave(&channel->iob_lock, flags);
  607. buffer = __qeth_get_buffer(channel);
  608. spin_unlock_irqrestore(&channel->iob_lock, flags);
  609. return buffer;
  610. }
  611. struct qeth_cmd_buffer *qeth_wait_for_buffer(struct qeth_channel *channel)
  612. {
  613. struct qeth_cmd_buffer *buffer;
  614. wait_event(channel->wait_q,
  615. ((buffer = qeth_get_buffer(channel)) != NULL));
  616. return buffer;
  617. }
  618. EXPORT_SYMBOL_GPL(qeth_wait_for_buffer);
  619. void qeth_clear_cmd_buffers(struct qeth_channel *channel)
  620. {
  621. int cnt;
  622. for (cnt = 0; cnt < QETH_CMD_BUFFER_NO; cnt++)
  623. qeth_release_buffer(channel, &channel->iob[cnt]);
  624. channel->buf_no = 0;
  625. channel->io_buf_no = 0;
  626. }
  627. EXPORT_SYMBOL_GPL(qeth_clear_cmd_buffers);
  628. static void qeth_send_control_data_cb(struct qeth_channel *channel,
  629. struct qeth_cmd_buffer *iob)
  630. {
  631. struct qeth_card *card;
  632. struct qeth_reply *reply, *r;
  633. struct qeth_ipa_cmd *cmd;
  634. unsigned long flags;
  635. int keep_reply;
  636. int rc = 0;
  637. card = CARD_FROM_CDEV(channel->ccwdev);
  638. QETH_CARD_TEXT(card, 4, "sndctlcb");
  639. rc = qeth_check_idx_response(card, iob->data);
  640. switch (rc) {
  641. case 0:
  642. break;
  643. case -EIO:
  644. qeth_clear_ipacmd_list(card);
  645. qeth_schedule_recovery(card);
  646. /* fall through */
  647. default:
  648. goto out;
  649. }
  650. cmd = qeth_check_ipa_data(card, iob);
  651. if ((cmd == NULL) && (card->state != CARD_STATE_DOWN))
  652. goto out;
  653. /*in case of OSN : check if cmd is set */
  654. if (card->info.type == QETH_CARD_TYPE_OSN &&
  655. cmd &&
  656. cmd->hdr.command != IPA_CMD_STARTLAN &&
  657. card->osn_info.assist_cb != NULL) {
  658. card->osn_info.assist_cb(card->dev, cmd);
  659. goto out;
  660. }
  661. spin_lock_irqsave(&card->lock, flags);
  662. list_for_each_entry_safe(reply, r, &card->cmd_waiter_list, list) {
  663. if ((reply->seqno == QETH_IDX_COMMAND_SEQNO) ||
  664. ((cmd) && (reply->seqno == cmd->hdr.seqno))) {
  665. qeth_get_reply(reply);
  666. list_del_init(&reply->list);
  667. spin_unlock_irqrestore(&card->lock, flags);
  668. keep_reply = 0;
  669. if (reply->callback != NULL) {
  670. if (cmd) {
  671. reply->offset = (__u16)((char *)cmd -
  672. (char *)iob->data);
  673. keep_reply = reply->callback(card,
  674. reply,
  675. (unsigned long)cmd);
  676. } else
  677. keep_reply = reply->callback(card,
  678. reply,
  679. (unsigned long)iob);
  680. }
  681. if (cmd)
  682. reply->rc = (u16) cmd->hdr.return_code;
  683. else if (iob->rc)
  684. reply->rc = iob->rc;
  685. if (keep_reply) {
  686. spin_lock_irqsave(&card->lock, flags);
  687. list_add_tail(&reply->list,
  688. &card->cmd_waiter_list);
  689. spin_unlock_irqrestore(&card->lock, flags);
  690. } else {
  691. atomic_inc(&reply->received);
  692. wake_up(&reply->wait_q);
  693. }
  694. qeth_put_reply(reply);
  695. goto out;
  696. }
  697. }
  698. spin_unlock_irqrestore(&card->lock, flags);
  699. out:
  700. memcpy(&card->seqno.pdu_hdr_ack,
  701. QETH_PDU_HEADER_SEQ_NO(iob->data),
  702. QETH_SEQ_NO_LENGTH);
  703. qeth_release_buffer(channel, iob);
  704. }
  705. static int qeth_setup_channel(struct qeth_channel *channel)
  706. {
  707. int cnt;
  708. QETH_DBF_TEXT(SETUP, 2, "setupch");
  709. for (cnt = 0; cnt < QETH_CMD_BUFFER_NO; cnt++) {
  710. channel->iob[cnt].data =
  711. kzalloc(QETH_BUFSIZE, GFP_DMA|GFP_KERNEL);
  712. if (channel->iob[cnt].data == NULL)
  713. break;
  714. channel->iob[cnt].state = BUF_STATE_FREE;
  715. channel->iob[cnt].channel = channel;
  716. channel->iob[cnt].callback = qeth_send_control_data_cb;
  717. channel->iob[cnt].rc = 0;
  718. }
  719. if (cnt < QETH_CMD_BUFFER_NO) {
  720. while (cnt-- > 0)
  721. kfree(channel->iob[cnt].data);
  722. return -ENOMEM;
  723. }
  724. channel->buf_no = 0;
  725. channel->io_buf_no = 0;
  726. atomic_set(&channel->irq_pending, 0);
  727. spin_lock_init(&channel->iob_lock);
  728. init_waitqueue_head(&channel->wait_q);
  729. return 0;
  730. }
  731. static int qeth_set_thread_start_bit(struct qeth_card *card,
  732. unsigned long thread)
  733. {
  734. unsigned long flags;
  735. spin_lock_irqsave(&card->thread_mask_lock, flags);
  736. if (!(card->thread_allowed_mask & thread) ||
  737. (card->thread_start_mask & thread)) {
  738. spin_unlock_irqrestore(&card->thread_mask_lock, flags);
  739. return -EPERM;
  740. }
  741. card->thread_start_mask |= thread;
  742. spin_unlock_irqrestore(&card->thread_mask_lock, flags);
  743. return 0;
  744. }
  745. void qeth_clear_thread_start_bit(struct qeth_card *card, unsigned long thread)
  746. {
  747. unsigned long flags;
  748. spin_lock_irqsave(&card->thread_mask_lock, flags);
  749. card->thread_start_mask &= ~thread;
  750. spin_unlock_irqrestore(&card->thread_mask_lock, flags);
  751. wake_up(&card->wait_q);
  752. }
  753. EXPORT_SYMBOL_GPL(qeth_clear_thread_start_bit);
  754. void qeth_clear_thread_running_bit(struct qeth_card *card, unsigned long thread)
  755. {
  756. unsigned long flags;
  757. spin_lock_irqsave(&card->thread_mask_lock, flags);
  758. card->thread_running_mask &= ~thread;
  759. spin_unlock_irqrestore(&card->thread_mask_lock, flags);
  760. wake_up(&card->wait_q);
  761. }
  762. EXPORT_SYMBOL_GPL(qeth_clear_thread_running_bit);
  763. static int __qeth_do_run_thread(struct qeth_card *card, unsigned long thread)
  764. {
  765. unsigned long flags;
  766. int rc = 0;
  767. spin_lock_irqsave(&card->thread_mask_lock, flags);
  768. if (card->thread_start_mask & thread) {
  769. if ((card->thread_allowed_mask & thread) &&
  770. !(card->thread_running_mask & thread)) {
  771. rc = 1;
  772. card->thread_start_mask &= ~thread;
  773. card->thread_running_mask |= thread;
  774. } else
  775. rc = -EPERM;
  776. }
  777. spin_unlock_irqrestore(&card->thread_mask_lock, flags);
  778. return rc;
  779. }
  780. int qeth_do_run_thread(struct qeth_card *card, unsigned long thread)
  781. {
  782. int rc = 0;
  783. wait_event(card->wait_q,
  784. (rc = __qeth_do_run_thread(card, thread)) >= 0);
  785. return rc;
  786. }
  787. EXPORT_SYMBOL_GPL(qeth_do_run_thread);
  788. void qeth_schedule_recovery(struct qeth_card *card)
  789. {
  790. QETH_CARD_TEXT(card, 2, "startrec");
  791. WARN_ON(1);
  792. if (qeth_set_thread_start_bit(card, QETH_RECOVER_THREAD) == 0)
  793. schedule_work(&card->kernel_thread_starter);
  794. }
  795. EXPORT_SYMBOL_GPL(qeth_schedule_recovery);
  796. static int qeth_get_problem(struct ccw_device *cdev, struct irb *irb)
  797. {
  798. int dstat, cstat;
  799. char *sense;
  800. struct qeth_card *card;
  801. sense = (char *) irb->ecw;
  802. cstat = irb->scsw.cmd.cstat;
  803. dstat = irb->scsw.cmd.dstat;
  804. card = CARD_FROM_CDEV(cdev);
  805. if (cstat & (SCHN_STAT_CHN_CTRL_CHK | SCHN_STAT_INTF_CTRL_CHK |
  806. SCHN_STAT_CHN_DATA_CHK | SCHN_STAT_CHAIN_CHECK |
  807. SCHN_STAT_PROT_CHECK | SCHN_STAT_PROG_CHECK)) {
  808. QETH_CARD_TEXT(card, 2, "CGENCHK");
  809. dev_warn(&cdev->dev, "The qeth device driver "
  810. "failed to recover an error on the device\n");
  811. QETH_DBF_MESSAGE(2, "%s check on device dstat=x%x, cstat=x%x\n",
  812. dev_name(&cdev->dev), dstat, cstat);
  813. print_hex_dump(KERN_WARNING, "qeth: irb ", DUMP_PREFIX_OFFSET,
  814. 16, 1, irb, 64, 1);
  815. return 1;
  816. }
  817. if (dstat & DEV_STAT_UNIT_CHECK) {
  818. if (sense[SENSE_RESETTING_EVENT_BYTE] &
  819. SENSE_RESETTING_EVENT_FLAG) {
  820. QETH_CARD_TEXT(card, 2, "REVIND");
  821. return 1;
  822. }
  823. if (sense[SENSE_COMMAND_REJECT_BYTE] &
  824. SENSE_COMMAND_REJECT_FLAG) {
  825. QETH_CARD_TEXT(card, 2, "CMDREJi");
  826. return 1;
  827. }
  828. if ((sense[2] == 0xaf) && (sense[3] == 0xfe)) {
  829. QETH_CARD_TEXT(card, 2, "AFFE");
  830. return 1;
  831. }
  832. if ((!sense[0]) && (!sense[1]) && (!sense[2]) && (!sense[3])) {
  833. QETH_CARD_TEXT(card, 2, "ZEROSEN");
  834. return 0;
  835. }
  836. QETH_CARD_TEXT(card, 2, "DGENCHK");
  837. return 1;
  838. }
  839. return 0;
  840. }
  841. static long __qeth_check_irb_error(struct ccw_device *cdev,
  842. unsigned long intparm, struct irb *irb)
  843. {
  844. struct qeth_card *card;
  845. card = CARD_FROM_CDEV(cdev);
  846. if (!IS_ERR(irb))
  847. return 0;
  848. switch (PTR_ERR(irb)) {
  849. case -EIO:
  850. QETH_DBF_MESSAGE(2, "%s i/o-error on device\n",
  851. dev_name(&cdev->dev));
  852. QETH_CARD_TEXT(card, 2, "ckirberr");
  853. QETH_CARD_TEXT_(card, 2, " rc%d", -EIO);
  854. break;
  855. case -ETIMEDOUT:
  856. dev_warn(&cdev->dev, "A hardware operation timed out"
  857. " on the device\n");
  858. QETH_CARD_TEXT(card, 2, "ckirberr");
  859. QETH_CARD_TEXT_(card, 2, " rc%d", -ETIMEDOUT);
  860. if (intparm == QETH_RCD_PARM) {
  861. if (card && (card->data.ccwdev == cdev)) {
  862. card->data.state = CH_STATE_DOWN;
  863. wake_up(&card->wait_q);
  864. }
  865. }
  866. break;
  867. default:
  868. QETH_DBF_MESSAGE(2, "%s unknown error %ld on device\n",
  869. dev_name(&cdev->dev), PTR_ERR(irb));
  870. QETH_CARD_TEXT(card, 2, "ckirberr");
  871. QETH_CARD_TEXT(card, 2, " rc???");
  872. }
  873. return PTR_ERR(irb);
  874. }
  875. static void qeth_irq(struct ccw_device *cdev, unsigned long intparm,
  876. struct irb *irb)
  877. {
  878. int rc;
  879. int cstat, dstat;
  880. struct qeth_cmd_buffer *buffer;
  881. struct qeth_channel *channel;
  882. struct qeth_card *card;
  883. struct qeth_cmd_buffer *iob;
  884. __u8 index;
  885. if (__qeth_check_irb_error(cdev, intparm, irb))
  886. return;
  887. cstat = irb->scsw.cmd.cstat;
  888. dstat = irb->scsw.cmd.dstat;
  889. card = CARD_FROM_CDEV(cdev);
  890. if (!card)
  891. return;
  892. QETH_CARD_TEXT(card, 5, "irq");
  893. if (card->read.ccwdev == cdev) {
  894. channel = &card->read;
  895. QETH_CARD_TEXT(card, 5, "read");
  896. } else if (card->write.ccwdev == cdev) {
  897. channel = &card->write;
  898. QETH_CARD_TEXT(card, 5, "write");
  899. } else {
  900. channel = &card->data;
  901. QETH_CARD_TEXT(card, 5, "data");
  902. }
  903. atomic_set(&channel->irq_pending, 0);
  904. if (irb->scsw.cmd.fctl & (SCSW_FCTL_CLEAR_FUNC))
  905. channel->state = CH_STATE_STOPPED;
  906. if (irb->scsw.cmd.fctl & (SCSW_FCTL_HALT_FUNC))
  907. channel->state = CH_STATE_HALTED;
  908. /*let's wake up immediately on data channel*/
  909. if ((channel == &card->data) && (intparm != 0) &&
  910. (intparm != QETH_RCD_PARM))
  911. goto out;
  912. if (intparm == QETH_CLEAR_CHANNEL_PARM) {
  913. QETH_CARD_TEXT(card, 6, "clrchpar");
  914. /* we don't have to handle this further */
  915. intparm = 0;
  916. }
  917. if (intparm == QETH_HALT_CHANNEL_PARM) {
  918. QETH_CARD_TEXT(card, 6, "hltchpar");
  919. /* we don't have to handle this further */
  920. intparm = 0;
  921. }
  922. if ((dstat & DEV_STAT_UNIT_EXCEP) ||
  923. (dstat & DEV_STAT_UNIT_CHECK) ||
  924. (cstat)) {
  925. if (irb->esw.esw0.erw.cons) {
  926. dev_warn(&channel->ccwdev->dev,
  927. "The qeth device driver failed to recover "
  928. "an error on the device\n");
  929. QETH_DBF_MESSAGE(2, "%s sense data available. cstat "
  930. "0x%X dstat 0x%X\n",
  931. dev_name(&channel->ccwdev->dev), cstat, dstat);
  932. print_hex_dump(KERN_WARNING, "qeth: irb ",
  933. DUMP_PREFIX_OFFSET, 16, 1, irb, 32, 1);
  934. print_hex_dump(KERN_WARNING, "qeth: sense data ",
  935. DUMP_PREFIX_OFFSET, 16, 1, irb->ecw, 32, 1);
  936. }
  937. if (intparm == QETH_RCD_PARM) {
  938. channel->state = CH_STATE_DOWN;
  939. goto out;
  940. }
  941. rc = qeth_get_problem(cdev, irb);
  942. if (rc) {
  943. qeth_clear_ipacmd_list(card);
  944. qeth_schedule_recovery(card);
  945. goto out;
  946. }
  947. }
  948. if (intparm == QETH_RCD_PARM) {
  949. channel->state = CH_STATE_RCD_DONE;
  950. goto out;
  951. }
  952. if (intparm) {
  953. buffer = (struct qeth_cmd_buffer *) __va((addr_t)intparm);
  954. buffer->state = BUF_STATE_PROCESSED;
  955. }
  956. if (channel == &card->data)
  957. return;
  958. if (channel == &card->read &&
  959. channel->state == CH_STATE_UP)
  960. qeth_issue_next_read(card);
  961. iob = channel->iob;
  962. index = channel->buf_no;
  963. while (iob[index].state == BUF_STATE_PROCESSED) {
  964. if (iob[index].callback != NULL)
  965. iob[index].callback(channel, iob + index);
  966. index = (index + 1) % QETH_CMD_BUFFER_NO;
  967. }
  968. channel->buf_no = index;
  969. out:
  970. wake_up(&card->wait_q);
  971. return;
  972. }
  973. static void qeth_notify_skbs(struct qeth_qdio_out_q *q,
  974. struct qeth_qdio_out_buffer *buf,
  975. enum iucv_tx_notify notification)
  976. {
  977. struct sk_buff *skb;
  978. if (skb_queue_empty(&buf->skb_list))
  979. goto out;
  980. skb = skb_peek(&buf->skb_list);
  981. while (skb) {
  982. QETH_CARD_TEXT_(q->card, 5, "skbn%d", notification);
  983. QETH_CARD_TEXT_(q->card, 5, "%lx", (long) skb);
  984. if (skb->protocol == ETH_P_AF_IUCV) {
  985. if (skb->sk) {
  986. struct iucv_sock *iucv = iucv_sk(skb->sk);
  987. iucv->sk_txnotify(skb, notification);
  988. }
  989. }
  990. if (skb_queue_is_last(&buf->skb_list, skb))
  991. skb = NULL;
  992. else
  993. skb = skb_queue_next(&buf->skb_list, skb);
  994. }
  995. out:
  996. return;
  997. }
  998. static void qeth_release_skbs(struct qeth_qdio_out_buffer *buf)
  999. {
  1000. struct sk_buff *skb;
  1001. skb = skb_dequeue(&buf->skb_list);
  1002. while (skb) {
  1003. QETH_CARD_TEXT(buf->q->card, 5, "skbr");
  1004. QETH_CARD_TEXT_(buf->q->card, 5, "%lx", (long) skb);
  1005. atomic_dec(&skb->users);
  1006. dev_kfree_skb_any(skb);
  1007. skb = skb_dequeue(&buf->skb_list);
  1008. }
  1009. }
  1010. static void qeth_clear_output_buffer(struct qeth_qdio_out_q *queue,
  1011. struct qeth_qdio_out_buffer *buf,
  1012. enum qeth_qdio_buffer_states newbufstate)
  1013. {
  1014. int i;
  1015. /* is PCI flag set on buffer? */
  1016. if (buf->buffer->element[0].sflags & SBAL_SFLAGS0_PCI_REQ)
  1017. atomic_dec(&queue->set_pci_flags_count);
  1018. if (newbufstate == QETH_QDIO_BUF_EMPTY) {
  1019. qeth_release_skbs(buf);
  1020. }
  1021. for (i = 0; i < QETH_MAX_BUFFER_ELEMENTS(queue->card); ++i) {
  1022. if (buf->buffer->element[i].addr && buf->is_header[i])
  1023. kmem_cache_free(qeth_core_header_cache,
  1024. buf->buffer->element[i].addr);
  1025. buf->is_header[i] = 0;
  1026. buf->buffer->element[i].length = 0;
  1027. buf->buffer->element[i].addr = NULL;
  1028. buf->buffer->element[i].eflags = 0;
  1029. buf->buffer->element[i].sflags = 0;
  1030. }
  1031. buf->buffer->element[15].eflags = 0;
  1032. buf->buffer->element[15].sflags = 0;
  1033. buf->next_element_to_fill = 0;
  1034. atomic_set(&buf->state, newbufstate);
  1035. }
  1036. static void qeth_clear_outq_buffers(struct qeth_qdio_out_q *q, int free)
  1037. {
  1038. int j;
  1039. for (j = 0; j < QDIO_MAX_BUFFERS_PER_Q; ++j) {
  1040. if (!q->bufs[j])
  1041. continue;
  1042. qeth_cleanup_handled_pending(q, j, free);
  1043. qeth_clear_output_buffer(q, q->bufs[j], QETH_QDIO_BUF_EMPTY);
  1044. if (free) {
  1045. kmem_cache_free(qeth_qdio_outbuf_cache, q->bufs[j]);
  1046. q->bufs[j] = NULL;
  1047. }
  1048. }
  1049. }
  1050. void qeth_clear_qdio_buffers(struct qeth_card *card)
  1051. {
  1052. int i;
  1053. QETH_CARD_TEXT(card, 2, "clearqdbf");
  1054. /* clear outbound buffers to free skbs */
  1055. for (i = 0; i < card->qdio.no_out_queues; ++i) {
  1056. if (card->qdio.out_qs[i]) {
  1057. qeth_clear_outq_buffers(card->qdio.out_qs[i], 0);
  1058. }
  1059. }
  1060. }
  1061. EXPORT_SYMBOL_GPL(qeth_clear_qdio_buffers);
  1062. static void qeth_free_buffer_pool(struct qeth_card *card)
  1063. {
  1064. struct qeth_buffer_pool_entry *pool_entry, *tmp;
  1065. int i = 0;
  1066. list_for_each_entry_safe(pool_entry, tmp,
  1067. &card->qdio.init_pool.entry_list, init_list){
  1068. for (i = 0; i < QETH_MAX_BUFFER_ELEMENTS(card); ++i)
  1069. free_page((unsigned long)pool_entry->elements[i]);
  1070. list_del(&pool_entry->init_list);
  1071. kfree(pool_entry);
  1072. }
  1073. }
  1074. static void qeth_free_qdio_buffers(struct qeth_card *card)
  1075. {
  1076. int i, j;
  1077. if (atomic_xchg(&card->qdio.state, QETH_QDIO_UNINITIALIZED) ==
  1078. QETH_QDIO_UNINITIALIZED)
  1079. return;
  1080. qeth_free_cq(card);
  1081. cancel_delayed_work_sync(&card->buffer_reclaim_work);
  1082. for (j = 0; j < QDIO_MAX_BUFFERS_PER_Q; ++j)
  1083. kfree_skb(card->qdio.in_q->bufs[j].rx_skb);
  1084. kfree(card->qdio.in_q);
  1085. card->qdio.in_q = NULL;
  1086. /* inbound buffer pool */
  1087. qeth_free_buffer_pool(card);
  1088. /* free outbound qdio_qs */
  1089. if (card->qdio.out_qs) {
  1090. for (i = 0; i < card->qdio.no_out_queues; ++i) {
  1091. qeth_clear_outq_buffers(card->qdio.out_qs[i], 1);
  1092. kfree(card->qdio.out_qs[i]);
  1093. }
  1094. kfree(card->qdio.out_qs);
  1095. card->qdio.out_qs = NULL;
  1096. }
  1097. }
  1098. static void qeth_clean_channel(struct qeth_channel *channel)
  1099. {
  1100. int cnt;
  1101. QETH_DBF_TEXT(SETUP, 2, "freech");
  1102. for (cnt = 0; cnt < QETH_CMD_BUFFER_NO; cnt++)
  1103. kfree(channel->iob[cnt].data);
  1104. }
  1105. static void qeth_get_channel_path_desc(struct qeth_card *card)
  1106. {
  1107. struct ccw_device *ccwdev;
  1108. struct channelPath_dsc {
  1109. u8 flags;
  1110. u8 lsn;
  1111. u8 desc;
  1112. u8 chpid;
  1113. u8 swla;
  1114. u8 zeroes;
  1115. u8 chla;
  1116. u8 chpp;
  1117. } *chp_dsc;
  1118. QETH_DBF_TEXT(SETUP, 2, "chp_desc");
  1119. ccwdev = card->data.ccwdev;
  1120. chp_dsc = (struct channelPath_dsc *)ccw_device_get_chp_desc(ccwdev, 0);
  1121. if (chp_dsc != NULL) {
  1122. if (card->info.type != QETH_CARD_TYPE_IQD) {
  1123. /* CHPP field bit 6 == 1 -> single queue */
  1124. if ((chp_dsc->chpp & 0x02) == 0x02) {
  1125. if ((atomic_read(&card->qdio.state) !=
  1126. QETH_QDIO_UNINITIALIZED) &&
  1127. (card->qdio.no_out_queues == 4))
  1128. /* change from 4 to 1 outbound queues */
  1129. qeth_free_qdio_buffers(card);
  1130. card->qdio.no_out_queues = 1;
  1131. if (card->qdio.default_out_queue != 0)
  1132. dev_info(&card->gdev->dev,
  1133. "Priority Queueing not supported\n");
  1134. card->qdio.default_out_queue = 0;
  1135. } else {
  1136. if ((atomic_read(&card->qdio.state) !=
  1137. QETH_QDIO_UNINITIALIZED) &&
  1138. (card->qdio.no_out_queues == 1)) {
  1139. /* change from 1 to 4 outbound queues */
  1140. qeth_free_qdio_buffers(card);
  1141. card->qdio.default_out_queue = 2;
  1142. }
  1143. card->qdio.no_out_queues = 4;
  1144. }
  1145. }
  1146. card->info.func_level = 0x4100 + chp_dsc->desc;
  1147. kfree(chp_dsc);
  1148. }
  1149. QETH_DBF_TEXT_(SETUP, 2, "nr:%x", card->qdio.no_out_queues);
  1150. QETH_DBF_TEXT_(SETUP, 2, "lvl:%02x", card->info.func_level);
  1151. return;
  1152. }
  1153. static void qeth_init_qdio_info(struct qeth_card *card)
  1154. {
  1155. QETH_DBF_TEXT(SETUP, 4, "intqdinf");
  1156. atomic_set(&card->qdio.state, QETH_QDIO_UNINITIALIZED);
  1157. /* inbound */
  1158. card->qdio.in_buf_size = QETH_IN_BUF_SIZE_DEFAULT;
  1159. if (card->info.type == QETH_CARD_TYPE_IQD)
  1160. card->qdio.init_pool.buf_count = QETH_IN_BUF_COUNT_HSDEFAULT;
  1161. else
  1162. card->qdio.init_pool.buf_count = QETH_IN_BUF_COUNT_DEFAULT;
  1163. card->qdio.in_buf_pool.buf_count = card->qdio.init_pool.buf_count;
  1164. INIT_LIST_HEAD(&card->qdio.in_buf_pool.entry_list);
  1165. INIT_LIST_HEAD(&card->qdio.init_pool.entry_list);
  1166. }
  1167. static void qeth_set_intial_options(struct qeth_card *card)
  1168. {
  1169. card->options.route4.type = NO_ROUTER;
  1170. card->options.route6.type = NO_ROUTER;
  1171. card->options.broadcast_mode = QETH_TR_BROADCAST_ALLRINGS;
  1172. card->options.macaddr_mode = QETH_TR_MACADDR_NONCANONICAL;
  1173. card->options.fake_broadcast = 0;
  1174. card->options.add_hhlen = DEFAULT_ADD_HHLEN;
  1175. card->options.performance_stats = 0;
  1176. card->options.rx_sg_cb = QETH_RX_SG_CB;
  1177. card->options.isolation = ISOLATION_MODE_NONE;
  1178. card->options.cq = QETH_CQ_DISABLED;
  1179. }
  1180. static int qeth_do_start_thread(struct qeth_card *card, unsigned long thread)
  1181. {
  1182. unsigned long flags;
  1183. int rc = 0;
  1184. spin_lock_irqsave(&card->thread_mask_lock, flags);
  1185. QETH_CARD_TEXT_(card, 4, " %02x%02x%02x",
  1186. (u8) card->thread_start_mask,
  1187. (u8) card->thread_allowed_mask,
  1188. (u8) card->thread_running_mask);
  1189. rc = (card->thread_start_mask & thread);
  1190. spin_unlock_irqrestore(&card->thread_mask_lock, flags);
  1191. return rc;
  1192. }
  1193. static void qeth_start_kernel_thread(struct work_struct *work)
  1194. {
  1195. struct qeth_card *card = container_of(work, struct qeth_card,
  1196. kernel_thread_starter);
  1197. QETH_CARD_TEXT(card , 2, "strthrd");
  1198. if (card->read.state != CH_STATE_UP &&
  1199. card->write.state != CH_STATE_UP)
  1200. return;
  1201. if (qeth_do_start_thread(card, QETH_RECOVER_THREAD))
  1202. kthread_run(card->discipline.recover, (void *) card,
  1203. "qeth_recover");
  1204. }
  1205. static int qeth_setup_card(struct qeth_card *card)
  1206. {
  1207. QETH_DBF_TEXT(SETUP, 2, "setupcrd");
  1208. QETH_DBF_HEX(SETUP, 2, &card, sizeof(void *));
  1209. card->read.state = CH_STATE_DOWN;
  1210. card->write.state = CH_STATE_DOWN;
  1211. card->data.state = CH_STATE_DOWN;
  1212. card->state = CARD_STATE_DOWN;
  1213. card->lan_online = 0;
  1214. card->read_or_write_problem = 0;
  1215. card->dev = NULL;
  1216. spin_lock_init(&card->vlanlock);
  1217. spin_lock_init(&card->mclock);
  1218. spin_lock_init(&card->lock);
  1219. spin_lock_init(&card->ip_lock);
  1220. spin_lock_init(&card->thread_mask_lock);
  1221. mutex_init(&card->conf_mutex);
  1222. mutex_init(&card->discipline_mutex);
  1223. card->thread_start_mask = 0;
  1224. card->thread_allowed_mask = 0;
  1225. card->thread_running_mask = 0;
  1226. INIT_WORK(&card->kernel_thread_starter, qeth_start_kernel_thread);
  1227. INIT_LIST_HEAD(&card->ip_list);
  1228. INIT_LIST_HEAD(card->ip_tbd_list);
  1229. INIT_LIST_HEAD(&card->cmd_waiter_list);
  1230. init_waitqueue_head(&card->wait_q);
  1231. /* initial options */
  1232. qeth_set_intial_options(card);
  1233. /* IP address takeover */
  1234. INIT_LIST_HEAD(&card->ipato.entries);
  1235. card->ipato.enabled = 0;
  1236. card->ipato.invert4 = 0;
  1237. card->ipato.invert6 = 0;
  1238. /* init QDIO stuff */
  1239. qeth_init_qdio_info(card);
  1240. INIT_DELAYED_WORK(&card->buffer_reclaim_work, qeth_buffer_reclaim_work);
  1241. return 0;
  1242. }
  1243. static void qeth_core_sl_print(struct seq_file *m, struct service_level *slr)
  1244. {
  1245. struct qeth_card *card = container_of(slr, struct qeth_card,
  1246. qeth_service_level);
  1247. if (card->info.mcl_level[0])
  1248. seq_printf(m, "qeth: %s firmware level %s\n",
  1249. CARD_BUS_ID(card), card->info.mcl_level);
  1250. }
  1251. static struct qeth_card *qeth_alloc_card(void)
  1252. {
  1253. struct qeth_card *card;
  1254. QETH_DBF_TEXT(SETUP, 2, "alloccrd");
  1255. card = kzalloc(sizeof(struct qeth_card), GFP_DMA|GFP_KERNEL);
  1256. if (!card)
  1257. goto out;
  1258. QETH_DBF_HEX(SETUP, 2, &card, sizeof(void *));
  1259. card->ip_tbd_list = kzalloc(sizeof(struct list_head), GFP_KERNEL);
  1260. if (!card->ip_tbd_list) {
  1261. QETH_DBF_TEXT(SETUP, 0, "iptbdnom");
  1262. goto out_card;
  1263. }
  1264. if (qeth_setup_channel(&card->read))
  1265. goto out_ip;
  1266. if (qeth_setup_channel(&card->write))
  1267. goto out_channel;
  1268. card->options.layer2 = -1;
  1269. card->qeth_service_level.seq_print = qeth_core_sl_print;
  1270. register_service_level(&card->qeth_service_level);
  1271. return card;
  1272. out_channel:
  1273. qeth_clean_channel(&card->read);
  1274. out_ip:
  1275. kfree(card->ip_tbd_list);
  1276. out_card:
  1277. kfree(card);
  1278. out:
  1279. return NULL;
  1280. }
  1281. static int qeth_determine_card_type(struct qeth_card *card)
  1282. {
  1283. int i = 0;
  1284. QETH_DBF_TEXT(SETUP, 2, "detcdtyp");
  1285. card->qdio.do_prio_queueing = QETH_PRIOQ_DEFAULT;
  1286. card->qdio.default_out_queue = QETH_DEFAULT_QUEUE;
  1287. while (known_devices[i][QETH_DEV_MODEL_IND]) {
  1288. if ((CARD_RDEV(card)->id.dev_type ==
  1289. known_devices[i][QETH_DEV_TYPE_IND]) &&
  1290. (CARD_RDEV(card)->id.dev_model ==
  1291. known_devices[i][QETH_DEV_MODEL_IND])) {
  1292. card->info.type = known_devices[i][QETH_DEV_MODEL_IND];
  1293. card->qdio.no_out_queues =
  1294. known_devices[i][QETH_QUEUE_NO_IND];
  1295. card->qdio.no_in_queues = 1;
  1296. card->info.is_multicast_different =
  1297. known_devices[i][QETH_MULTICAST_IND];
  1298. qeth_get_channel_path_desc(card);
  1299. return 0;
  1300. }
  1301. i++;
  1302. }
  1303. card->info.type = QETH_CARD_TYPE_UNKNOWN;
  1304. dev_err(&card->gdev->dev, "The adapter hardware is of an "
  1305. "unknown type\n");
  1306. return -ENOENT;
  1307. }
  1308. static int qeth_clear_channel(struct qeth_channel *channel)
  1309. {
  1310. unsigned long flags;
  1311. struct qeth_card *card;
  1312. int rc;
  1313. card = CARD_FROM_CDEV(channel->ccwdev);
  1314. QETH_CARD_TEXT(card, 3, "clearch");
  1315. spin_lock_irqsave(get_ccwdev_lock(channel->ccwdev), flags);
  1316. rc = ccw_device_clear(channel->ccwdev, QETH_CLEAR_CHANNEL_PARM);
  1317. spin_unlock_irqrestore(get_ccwdev_lock(channel->ccwdev), flags);
  1318. if (rc)
  1319. return rc;
  1320. rc = wait_event_interruptible_timeout(card->wait_q,
  1321. channel->state == CH_STATE_STOPPED, QETH_TIMEOUT);
  1322. if (rc == -ERESTARTSYS)
  1323. return rc;
  1324. if (channel->state != CH_STATE_STOPPED)
  1325. return -ETIME;
  1326. channel->state = CH_STATE_DOWN;
  1327. return 0;
  1328. }
  1329. static int qeth_halt_channel(struct qeth_channel *channel)
  1330. {
  1331. unsigned long flags;
  1332. struct qeth_card *card;
  1333. int rc;
  1334. card = CARD_FROM_CDEV(channel->ccwdev);
  1335. QETH_CARD_TEXT(card, 3, "haltch");
  1336. spin_lock_irqsave(get_ccwdev_lock(channel->ccwdev), flags);
  1337. rc = ccw_device_halt(channel->ccwdev, QETH_HALT_CHANNEL_PARM);
  1338. spin_unlock_irqrestore(get_ccwdev_lock(channel->ccwdev), flags);
  1339. if (rc)
  1340. return rc;
  1341. rc = wait_event_interruptible_timeout(card->wait_q,
  1342. channel->state == CH_STATE_HALTED, QETH_TIMEOUT);
  1343. if (rc == -ERESTARTSYS)
  1344. return rc;
  1345. if (channel->state != CH_STATE_HALTED)
  1346. return -ETIME;
  1347. return 0;
  1348. }
  1349. static int qeth_halt_channels(struct qeth_card *card)
  1350. {
  1351. int rc1 = 0, rc2 = 0, rc3 = 0;
  1352. QETH_CARD_TEXT(card, 3, "haltchs");
  1353. rc1 = qeth_halt_channel(&card->read);
  1354. rc2 = qeth_halt_channel(&card->write);
  1355. rc3 = qeth_halt_channel(&card->data);
  1356. if (rc1)
  1357. return rc1;
  1358. if (rc2)
  1359. return rc2;
  1360. return rc3;
  1361. }
  1362. static int qeth_clear_channels(struct qeth_card *card)
  1363. {
  1364. int rc1 = 0, rc2 = 0, rc3 = 0;
  1365. QETH_CARD_TEXT(card, 3, "clearchs");
  1366. rc1 = qeth_clear_channel(&card->read);
  1367. rc2 = qeth_clear_channel(&card->write);
  1368. rc3 = qeth_clear_channel(&card->data);
  1369. if (rc1)
  1370. return rc1;
  1371. if (rc2)
  1372. return rc2;
  1373. return rc3;
  1374. }
  1375. static int qeth_clear_halt_card(struct qeth_card *card, int halt)
  1376. {
  1377. int rc = 0;
  1378. QETH_CARD_TEXT(card, 3, "clhacrd");
  1379. if (halt)
  1380. rc = qeth_halt_channels(card);
  1381. if (rc)
  1382. return rc;
  1383. return qeth_clear_channels(card);
  1384. }
  1385. int qeth_qdio_clear_card(struct qeth_card *card, int use_halt)
  1386. {
  1387. int rc = 0;
  1388. QETH_CARD_TEXT(card, 3, "qdioclr");
  1389. switch (atomic_cmpxchg(&card->qdio.state, QETH_QDIO_ESTABLISHED,
  1390. QETH_QDIO_CLEANING)) {
  1391. case QETH_QDIO_ESTABLISHED:
  1392. if (card->info.type == QETH_CARD_TYPE_IQD)
  1393. rc = qdio_shutdown(CARD_DDEV(card),
  1394. QDIO_FLAG_CLEANUP_USING_HALT);
  1395. else
  1396. rc = qdio_shutdown(CARD_DDEV(card),
  1397. QDIO_FLAG_CLEANUP_USING_CLEAR);
  1398. if (rc)
  1399. QETH_CARD_TEXT_(card, 3, "1err%d", rc);
  1400. qdio_free(CARD_DDEV(card));
  1401. atomic_set(&card->qdio.state, QETH_QDIO_ALLOCATED);
  1402. break;
  1403. case QETH_QDIO_CLEANING:
  1404. return rc;
  1405. default:
  1406. break;
  1407. }
  1408. rc = qeth_clear_halt_card(card, use_halt);
  1409. if (rc)
  1410. QETH_CARD_TEXT_(card, 3, "2err%d", rc);
  1411. card->state = CARD_STATE_DOWN;
  1412. return rc;
  1413. }
  1414. EXPORT_SYMBOL_GPL(qeth_qdio_clear_card);
  1415. static int qeth_read_conf_data(struct qeth_card *card, void **buffer,
  1416. int *length)
  1417. {
  1418. struct ciw *ciw;
  1419. char *rcd_buf;
  1420. int ret;
  1421. struct qeth_channel *channel = &card->data;
  1422. unsigned long flags;
  1423. /*
  1424. * scan for RCD command in extended SenseID data
  1425. */
  1426. ciw = ccw_device_get_ciw(channel->ccwdev, CIW_TYPE_RCD);
  1427. if (!ciw || ciw->cmd == 0)
  1428. return -EOPNOTSUPP;
  1429. rcd_buf = kzalloc(ciw->count, GFP_KERNEL | GFP_DMA);
  1430. if (!rcd_buf)
  1431. return -ENOMEM;
  1432. channel->ccw.cmd_code = ciw->cmd;
  1433. channel->ccw.cda = (__u32) __pa(rcd_buf);
  1434. channel->ccw.count = ciw->count;
  1435. channel->ccw.flags = CCW_FLAG_SLI;
  1436. channel->state = CH_STATE_RCD;
  1437. spin_lock_irqsave(get_ccwdev_lock(channel->ccwdev), flags);
  1438. ret = ccw_device_start_timeout(channel->ccwdev, &channel->ccw,
  1439. QETH_RCD_PARM, LPM_ANYPATH, 0,
  1440. QETH_RCD_TIMEOUT);
  1441. spin_unlock_irqrestore(get_ccwdev_lock(channel->ccwdev), flags);
  1442. if (!ret)
  1443. wait_event(card->wait_q,
  1444. (channel->state == CH_STATE_RCD_DONE ||
  1445. channel->state == CH_STATE_DOWN));
  1446. if (channel->state == CH_STATE_DOWN)
  1447. ret = -EIO;
  1448. else
  1449. channel->state = CH_STATE_DOWN;
  1450. if (ret) {
  1451. kfree(rcd_buf);
  1452. *buffer = NULL;
  1453. *length = 0;
  1454. } else {
  1455. *length = ciw->count;
  1456. *buffer = rcd_buf;
  1457. }
  1458. return ret;
  1459. }
  1460. static void qeth_configure_unitaddr(struct qeth_card *card, char *prcd)
  1461. {
  1462. QETH_DBF_TEXT(SETUP, 2, "cfgunit");
  1463. card->info.chpid = prcd[30];
  1464. card->info.unit_addr2 = prcd[31];
  1465. card->info.cula = prcd[63];
  1466. card->info.guestlan = ((prcd[0x10] == _ascebc['V']) &&
  1467. (prcd[0x11] == _ascebc['M']));
  1468. }
  1469. static void qeth_configure_blkt_default(struct qeth_card *card, char *prcd)
  1470. {
  1471. QETH_DBF_TEXT(SETUP, 2, "cfgblkt");
  1472. if (prcd[74] == 0xF0 && prcd[75] == 0xF0 && prcd[76] == 0xF5) {
  1473. card->info.blkt.time_total = 250;
  1474. card->info.blkt.inter_packet = 5;
  1475. card->info.blkt.inter_packet_jumbo = 15;
  1476. } else {
  1477. card->info.blkt.time_total = 0;
  1478. card->info.blkt.inter_packet = 0;
  1479. card->info.blkt.inter_packet_jumbo = 0;
  1480. }
  1481. }
  1482. static void qeth_init_tokens(struct qeth_card *card)
  1483. {
  1484. card->token.issuer_rm_w = 0x00010103UL;
  1485. card->token.cm_filter_w = 0x00010108UL;
  1486. card->token.cm_connection_w = 0x0001010aUL;
  1487. card->token.ulp_filter_w = 0x0001010bUL;
  1488. card->token.ulp_connection_w = 0x0001010dUL;
  1489. }
  1490. static void qeth_init_func_level(struct qeth_card *card)
  1491. {
  1492. switch (card->info.type) {
  1493. case QETH_CARD_TYPE_IQD:
  1494. card->info.func_level = QETH_IDX_FUNC_LEVEL_IQD;
  1495. break;
  1496. case QETH_CARD_TYPE_OSD:
  1497. case QETH_CARD_TYPE_OSN:
  1498. card->info.func_level = QETH_IDX_FUNC_LEVEL_OSD;
  1499. break;
  1500. default:
  1501. break;
  1502. }
  1503. }
  1504. static int qeth_idx_activate_get_answer(struct qeth_channel *channel,
  1505. void (*idx_reply_cb)(struct qeth_channel *,
  1506. struct qeth_cmd_buffer *))
  1507. {
  1508. struct qeth_cmd_buffer *iob;
  1509. unsigned long flags;
  1510. int rc;
  1511. struct qeth_card *card;
  1512. QETH_DBF_TEXT(SETUP, 2, "idxanswr");
  1513. card = CARD_FROM_CDEV(channel->ccwdev);
  1514. iob = qeth_get_buffer(channel);
  1515. iob->callback = idx_reply_cb;
  1516. memcpy(&channel->ccw, READ_CCW, sizeof(struct ccw1));
  1517. channel->ccw.count = QETH_BUFSIZE;
  1518. channel->ccw.cda = (__u32) __pa(iob->data);
  1519. wait_event(card->wait_q,
  1520. atomic_cmpxchg(&channel->irq_pending, 0, 1) == 0);
  1521. QETH_DBF_TEXT(SETUP, 6, "noirqpnd");
  1522. spin_lock_irqsave(get_ccwdev_lock(channel->ccwdev), flags);
  1523. rc = ccw_device_start(channel->ccwdev,
  1524. &channel->ccw, (addr_t) iob, 0, 0);
  1525. spin_unlock_irqrestore(get_ccwdev_lock(channel->ccwdev), flags);
  1526. if (rc) {
  1527. QETH_DBF_MESSAGE(2, "Error2 in activating channel rc=%d\n", rc);
  1528. QETH_DBF_TEXT_(SETUP, 2, "2err%d", rc);
  1529. atomic_set(&channel->irq_pending, 0);
  1530. wake_up(&card->wait_q);
  1531. return rc;
  1532. }
  1533. rc = wait_event_interruptible_timeout(card->wait_q,
  1534. channel->state == CH_STATE_UP, QETH_TIMEOUT);
  1535. if (rc == -ERESTARTSYS)
  1536. return rc;
  1537. if (channel->state != CH_STATE_UP) {
  1538. rc = -ETIME;
  1539. QETH_DBF_TEXT_(SETUP, 2, "3err%d", rc);
  1540. qeth_clear_cmd_buffers(channel);
  1541. } else
  1542. rc = 0;
  1543. return rc;
  1544. }
  1545. static int qeth_idx_activate_channel(struct qeth_channel *channel,
  1546. void (*idx_reply_cb)(struct qeth_channel *,
  1547. struct qeth_cmd_buffer *))
  1548. {
  1549. struct qeth_card *card;
  1550. struct qeth_cmd_buffer *iob;
  1551. unsigned long flags;
  1552. __u16 temp;
  1553. __u8 tmp;
  1554. int rc;
  1555. struct ccw_dev_id temp_devid;
  1556. card = CARD_FROM_CDEV(channel->ccwdev);
  1557. QETH_DBF_TEXT(SETUP, 2, "idxactch");
  1558. iob = qeth_get_buffer(channel);
  1559. iob->callback = idx_reply_cb;
  1560. memcpy(&channel->ccw, WRITE_CCW, sizeof(struct ccw1));
  1561. channel->ccw.count = IDX_ACTIVATE_SIZE;
  1562. channel->ccw.cda = (__u32) __pa(iob->data);
  1563. if (channel == &card->write) {
  1564. memcpy(iob->data, IDX_ACTIVATE_WRITE, IDX_ACTIVATE_SIZE);
  1565. memcpy(QETH_TRANSPORT_HEADER_SEQ_NO(iob->data),
  1566. &card->seqno.trans_hdr, QETH_SEQ_NO_LENGTH);
  1567. card->seqno.trans_hdr++;
  1568. } else {
  1569. memcpy(iob->data, IDX_ACTIVATE_READ, IDX_ACTIVATE_SIZE);
  1570. memcpy(QETH_TRANSPORT_HEADER_SEQ_NO(iob->data),
  1571. &card->seqno.trans_hdr, QETH_SEQ_NO_LENGTH);
  1572. }
  1573. tmp = ((__u8)card->info.portno) | 0x80;
  1574. memcpy(QETH_IDX_ACT_PNO(iob->data), &tmp, 1);
  1575. memcpy(QETH_IDX_ACT_ISSUER_RM_TOKEN(iob->data),
  1576. &card->token.issuer_rm_w, QETH_MPC_TOKEN_LENGTH);
  1577. memcpy(QETH_IDX_ACT_FUNC_LEVEL(iob->data),
  1578. &card->info.func_level, sizeof(__u16));
  1579. ccw_device_get_id(CARD_DDEV(card), &temp_devid);
  1580. memcpy(QETH_IDX_ACT_QDIO_DEV_CUA(iob->data), &temp_devid.devno, 2);
  1581. temp = (card->info.cula << 8) + card->info.unit_addr2;
  1582. memcpy(QETH_IDX_ACT_QDIO_DEV_REALADDR(iob->data), &temp, 2);
  1583. wait_event(card->wait_q,
  1584. atomic_cmpxchg(&channel->irq_pending, 0, 1) == 0);
  1585. QETH_DBF_TEXT(SETUP, 6, "noirqpnd");
  1586. spin_lock_irqsave(get_ccwdev_lock(channel->ccwdev), flags);
  1587. rc = ccw_device_start(channel->ccwdev,
  1588. &channel->ccw, (addr_t) iob, 0, 0);
  1589. spin_unlock_irqrestore(get_ccwdev_lock(channel->ccwdev), flags);
  1590. if (rc) {
  1591. QETH_DBF_MESSAGE(2, "Error1 in activating channel. rc=%d\n",
  1592. rc);
  1593. QETH_DBF_TEXT_(SETUP, 2, "1err%d", rc);
  1594. atomic_set(&channel->irq_pending, 0);
  1595. wake_up(&card->wait_q);
  1596. return rc;
  1597. }
  1598. rc = wait_event_interruptible_timeout(card->wait_q,
  1599. channel->state == CH_STATE_ACTIVATING, QETH_TIMEOUT);
  1600. if (rc == -ERESTARTSYS)
  1601. return rc;
  1602. if (channel->state != CH_STATE_ACTIVATING) {
  1603. dev_warn(&channel->ccwdev->dev, "The qeth device driver"
  1604. " failed to recover an error on the device\n");
  1605. QETH_DBF_MESSAGE(2, "%s IDX activate timed out\n",
  1606. dev_name(&channel->ccwdev->dev));
  1607. QETH_DBF_TEXT_(SETUP, 2, "2err%d", -ETIME);
  1608. qeth_clear_cmd_buffers(channel);
  1609. return -ETIME;
  1610. }
  1611. return qeth_idx_activate_get_answer(channel, idx_reply_cb);
  1612. }
  1613. static int qeth_peer_func_level(int level)
  1614. {
  1615. if ((level & 0xff) == 8)
  1616. return (level & 0xff) + 0x400;
  1617. if (((level >> 8) & 3) == 1)
  1618. return (level & 0xff) + 0x200;
  1619. return level;
  1620. }
  1621. static void qeth_idx_write_cb(struct qeth_channel *channel,
  1622. struct qeth_cmd_buffer *iob)
  1623. {
  1624. struct qeth_card *card;
  1625. __u16 temp;
  1626. QETH_DBF_TEXT(SETUP , 2, "idxwrcb");
  1627. if (channel->state == CH_STATE_DOWN) {
  1628. channel->state = CH_STATE_ACTIVATING;
  1629. goto out;
  1630. }
  1631. card = CARD_FROM_CDEV(channel->ccwdev);
  1632. if (!(QETH_IS_IDX_ACT_POS_REPLY(iob->data))) {
  1633. if (QETH_IDX_ACT_CAUSE_CODE(iob->data) == QETH_IDX_ACT_ERR_EXCL)
  1634. dev_err(&card->write.ccwdev->dev,
  1635. "The adapter is used exclusively by another "
  1636. "host\n");
  1637. else
  1638. QETH_DBF_MESSAGE(2, "%s IDX_ACTIVATE on write channel:"
  1639. " negative reply\n",
  1640. dev_name(&card->write.ccwdev->dev));
  1641. goto out;
  1642. }
  1643. memcpy(&temp, QETH_IDX_ACT_FUNC_LEVEL(iob->data), 2);
  1644. if ((temp & ~0x0100) != qeth_peer_func_level(card->info.func_level)) {
  1645. QETH_DBF_MESSAGE(2, "%s IDX_ACTIVATE on write channel: "
  1646. "function level mismatch (sent: 0x%x, received: "
  1647. "0x%x)\n", dev_name(&card->write.ccwdev->dev),
  1648. card->info.func_level, temp);
  1649. goto out;
  1650. }
  1651. channel->state = CH_STATE_UP;
  1652. out:
  1653. qeth_release_buffer(channel, iob);
  1654. }
  1655. static void qeth_idx_read_cb(struct qeth_channel *channel,
  1656. struct qeth_cmd_buffer *iob)
  1657. {
  1658. struct qeth_card *card;
  1659. __u16 temp;
  1660. QETH_DBF_TEXT(SETUP , 2, "idxrdcb");
  1661. if (channel->state == CH_STATE_DOWN) {
  1662. channel->state = CH_STATE_ACTIVATING;
  1663. goto out;
  1664. }
  1665. card = CARD_FROM_CDEV(channel->ccwdev);
  1666. if (qeth_check_idx_response(card, iob->data))
  1667. goto out;
  1668. if (!(QETH_IS_IDX_ACT_POS_REPLY(iob->data))) {
  1669. switch (QETH_IDX_ACT_CAUSE_CODE(iob->data)) {
  1670. case QETH_IDX_ACT_ERR_EXCL:
  1671. dev_err(&card->write.ccwdev->dev,
  1672. "The adapter is used exclusively by another "
  1673. "host\n");
  1674. break;
  1675. case QETH_IDX_ACT_ERR_AUTH:
  1676. case QETH_IDX_ACT_ERR_AUTH_USER:
  1677. dev_err(&card->read.ccwdev->dev,
  1678. "Setting the device online failed because of "
  1679. "insufficient authorization\n");
  1680. break;
  1681. default:
  1682. QETH_DBF_MESSAGE(2, "%s IDX_ACTIVATE on read channel:"
  1683. " negative reply\n",
  1684. dev_name(&card->read.ccwdev->dev));
  1685. }
  1686. QETH_CARD_TEXT_(card, 2, "idxread%c",
  1687. QETH_IDX_ACT_CAUSE_CODE(iob->data));
  1688. goto out;
  1689. }
  1690. /**
  1691. * * temporary fix for microcode bug
  1692. * * to revert it,replace OR by AND
  1693. * */
  1694. if ((!QETH_IDX_NO_PORTNAME_REQUIRED(iob->data)) ||
  1695. (card->info.type == QETH_CARD_TYPE_OSD))
  1696. card->info.portname_required = 1;
  1697. memcpy(&temp, QETH_IDX_ACT_FUNC_LEVEL(iob->data), 2);
  1698. if (temp != qeth_peer_func_level(card->info.func_level)) {
  1699. QETH_DBF_MESSAGE(2, "%s IDX_ACTIVATE on read channel: function "
  1700. "level mismatch (sent: 0x%x, received: 0x%x)\n",
  1701. dev_name(&card->read.ccwdev->dev),
  1702. card->info.func_level, temp);
  1703. goto out;
  1704. }
  1705. memcpy(&card->token.issuer_rm_r,
  1706. QETH_IDX_ACT_ISSUER_RM_TOKEN(iob->data),
  1707. QETH_MPC_TOKEN_LENGTH);
  1708. memcpy(&card->info.mcl_level[0],
  1709. QETH_IDX_REPLY_LEVEL(iob->data), QETH_MCL_LENGTH);
  1710. channel->state = CH_STATE_UP;
  1711. out:
  1712. qeth_release_buffer(channel, iob);
  1713. }
  1714. void qeth_prepare_control_data(struct qeth_card *card, int len,
  1715. struct qeth_cmd_buffer *iob)
  1716. {
  1717. qeth_setup_ccw(&card->write, iob->data, len);
  1718. iob->callback = qeth_release_buffer;
  1719. memcpy(QETH_TRANSPORT_HEADER_SEQ_NO(iob->data),
  1720. &card->seqno.trans_hdr, QETH_SEQ_NO_LENGTH);
  1721. card->seqno.trans_hdr++;
  1722. memcpy(QETH_PDU_HEADER_SEQ_NO(iob->data),
  1723. &card->seqno.pdu_hdr, QETH_SEQ_NO_LENGTH);
  1724. card->seqno.pdu_hdr++;
  1725. memcpy(QETH_PDU_HEADER_ACK_SEQ_NO(iob->data),
  1726. &card->seqno.pdu_hdr_ack, QETH_SEQ_NO_LENGTH);
  1727. QETH_DBF_HEX(CTRL, 2, iob->data, QETH_DBF_CTRL_LEN);
  1728. }
  1729. EXPORT_SYMBOL_GPL(qeth_prepare_control_data);
  1730. int qeth_send_control_data(struct qeth_card *card, int len,
  1731. struct qeth_cmd_buffer *iob,
  1732. int (*reply_cb)(struct qeth_card *, struct qeth_reply *,
  1733. unsigned long),
  1734. void *reply_param)
  1735. {
  1736. int rc;
  1737. unsigned long flags;
  1738. struct qeth_reply *reply = NULL;
  1739. unsigned long timeout, event_timeout;
  1740. struct qeth_ipa_cmd *cmd;
  1741. QETH_CARD_TEXT(card, 2, "sendctl");
  1742. if (card->read_or_write_problem) {
  1743. qeth_release_buffer(iob->channel, iob);
  1744. return -EIO;
  1745. }
  1746. reply = qeth_alloc_reply(card);
  1747. if (!reply) {
  1748. return -ENOMEM;
  1749. }
  1750. reply->callback = reply_cb;
  1751. reply->param = reply_param;
  1752. if (card->state == CARD_STATE_DOWN)
  1753. reply->seqno = QETH_IDX_COMMAND_SEQNO;
  1754. else
  1755. reply->seqno = card->seqno.ipa++;
  1756. init_waitqueue_head(&reply->wait_q);
  1757. spin_lock_irqsave(&card->lock, flags);
  1758. list_add_tail(&reply->list, &card->cmd_waiter_list);
  1759. spin_unlock_irqrestore(&card->lock, flags);
  1760. QETH_DBF_HEX(CTRL, 2, iob->data, QETH_DBF_CTRL_LEN);
  1761. while (atomic_cmpxchg(&card->write.irq_pending, 0, 1)) ;
  1762. qeth_prepare_control_data(card, len, iob);
  1763. if (IS_IPA(iob->data))
  1764. event_timeout = QETH_IPA_TIMEOUT;
  1765. else
  1766. event_timeout = QETH_TIMEOUT;
  1767. timeout = jiffies + event_timeout;
  1768. QETH_CARD_TEXT(card, 6, "noirqpnd");
  1769. spin_lock_irqsave(get_ccwdev_lock(card->write.ccwdev), flags);
  1770. rc = ccw_device_start(card->write.ccwdev, &card->write.ccw,
  1771. (addr_t) iob, 0, 0);
  1772. spin_unlock_irqrestore(get_ccwdev_lock(card->write.ccwdev), flags);
  1773. if (rc) {
  1774. QETH_DBF_MESSAGE(2, "%s qeth_send_control_data: "
  1775. "ccw_device_start rc = %i\n",
  1776. dev_name(&card->write.ccwdev->dev), rc);
  1777. QETH_CARD_TEXT_(card, 2, " err%d", rc);
  1778. spin_lock_irqsave(&card->lock, flags);
  1779. list_del_init(&reply->list);
  1780. qeth_put_reply(reply);
  1781. spin_unlock_irqrestore(&card->lock, flags);
  1782. qeth_release_buffer(iob->channel, iob);
  1783. atomic_set(&card->write.irq_pending, 0);
  1784. wake_up(&card->wait_q);
  1785. return rc;
  1786. }
  1787. /* we have only one long running ipassist, since we can ensure
  1788. process context of this command we can sleep */
  1789. cmd = (struct qeth_ipa_cmd *)(iob->data+IPA_PDU_HEADER_SIZE);
  1790. if ((cmd->hdr.command == IPA_CMD_SETIP) &&
  1791. (cmd->hdr.prot_version == QETH_PROT_IPV4)) {
  1792. if (!wait_event_timeout(reply->wait_q,
  1793. atomic_read(&reply->received), event_timeout))
  1794. goto time_err;
  1795. } else {
  1796. while (!atomic_read(&reply->received)) {
  1797. if (time_after(jiffies, timeout))
  1798. goto time_err;
  1799. cpu_relax();
  1800. };
  1801. }
  1802. if (reply->rc == -EIO)
  1803. goto error;
  1804. rc = reply->rc;
  1805. qeth_put_reply(reply);
  1806. return rc;
  1807. time_err:
  1808. reply->rc = -ETIME;
  1809. spin_lock_irqsave(&reply->card->lock, flags);
  1810. list_del_init(&reply->list);
  1811. spin_unlock_irqrestore(&reply->card->lock, flags);
  1812. atomic_inc(&reply->received);
  1813. error:
  1814. atomic_set(&card->write.irq_pending, 0);
  1815. qeth_release_buffer(iob->channel, iob);
  1816. card->write.buf_no = (card->write.buf_no + 1) % QETH_CMD_BUFFER_NO;
  1817. rc = reply->rc;
  1818. qeth_put_reply(reply);
  1819. return rc;
  1820. }
  1821. EXPORT_SYMBOL_GPL(qeth_send_control_data);
  1822. static int qeth_cm_enable_cb(struct qeth_card *card, struct qeth_reply *reply,
  1823. unsigned long data)
  1824. {
  1825. struct qeth_cmd_buffer *iob;
  1826. QETH_DBF_TEXT(SETUP, 2, "cmenblcb");
  1827. iob = (struct qeth_cmd_buffer *) data;
  1828. memcpy(&card->token.cm_filter_r,
  1829. QETH_CM_ENABLE_RESP_FILTER_TOKEN(iob->data),
  1830. QETH_MPC_TOKEN_LENGTH);
  1831. QETH_DBF_TEXT_(SETUP, 2, " rc%d", iob->rc);
  1832. return 0;
  1833. }
  1834. static int qeth_cm_enable(struct qeth_card *card)
  1835. {
  1836. int rc;
  1837. struct qeth_cmd_buffer *iob;
  1838. QETH_DBF_TEXT(SETUP, 2, "cmenable");
  1839. iob = qeth_wait_for_buffer(&card->write);
  1840. memcpy(iob->data, CM_ENABLE, CM_ENABLE_SIZE);
  1841. memcpy(QETH_CM_ENABLE_ISSUER_RM_TOKEN(iob->data),
  1842. &card->token.issuer_rm_r, QETH_MPC_TOKEN_LENGTH);
  1843. memcpy(QETH_CM_ENABLE_FILTER_TOKEN(iob->data),
  1844. &card->token.cm_filter_w, QETH_MPC_TOKEN_LENGTH);
  1845. rc = qeth_send_control_data(card, CM_ENABLE_SIZE, iob,
  1846. qeth_cm_enable_cb, NULL);
  1847. return rc;
  1848. }
  1849. static int qeth_cm_setup_cb(struct qeth_card *card, struct qeth_reply *reply,
  1850. unsigned long data)
  1851. {
  1852. struct qeth_cmd_buffer *iob;
  1853. QETH_DBF_TEXT(SETUP, 2, "cmsetpcb");
  1854. iob = (struct qeth_cmd_buffer *) data;
  1855. memcpy(&card->token.cm_connection_r,
  1856. QETH_CM_SETUP_RESP_DEST_ADDR(iob->data),
  1857. QETH_MPC_TOKEN_LENGTH);
  1858. QETH_DBF_TEXT_(SETUP, 2, " rc%d", iob->rc);
  1859. return 0;
  1860. }
  1861. static int qeth_cm_setup(struct qeth_card *card)
  1862. {
  1863. int rc;
  1864. struct qeth_cmd_buffer *iob;
  1865. QETH_DBF_TEXT(SETUP, 2, "cmsetup");
  1866. iob = qeth_wait_for_buffer(&card->write);
  1867. memcpy(iob->data, CM_SETUP, CM_SETUP_SIZE);
  1868. memcpy(QETH_CM_SETUP_DEST_ADDR(iob->data),
  1869. &card->token.issuer_rm_r, QETH_MPC_TOKEN_LENGTH);
  1870. memcpy(QETH_CM_SETUP_CONNECTION_TOKEN(iob->data),
  1871. &card->token.cm_connection_w, QETH_MPC_TOKEN_LENGTH);
  1872. memcpy(QETH_CM_SETUP_FILTER_TOKEN(iob->data),
  1873. &card->token.cm_filter_r, QETH_MPC_TOKEN_LENGTH);
  1874. rc = qeth_send_control_data(card, CM_SETUP_SIZE, iob,
  1875. qeth_cm_setup_cb, NULL);
  1876. return rc;
  1877. }
  1878. static inline int qeth_get_initial_mtu_for_card(struct qeth_card *card)
  1879. {
  1880. switch (card->info.type) {
  1881. case QETH_CARD_TYPE_UNKNOWN:
  1882. return 1500;
  1883. case QETH_CARD_TYPE_IQD:
  1884. return card->info.max_mtu;
  1885. case QETH_CARD_TYPE_OSD:
  1886. switch (card->info.link_type) {
  1887. case QETH_LINK_TYPE_HSTR:
  1888. case QETH_LINK_TYPE_LANE_TR:
  1889. return 2000;
  1890. default:
  1891. return 1492;
  1892. }
  1893. case QETH_CARD_TYPE_OSM:
  1894. case QETH_CARD_TYPE_OSX:
  1895. return 1492;
  1896. default:
  1897. return 1500;
  1898. }
  1899. }
  1900. static inline int qeth_get_mtu_outof_framesize(int framesize)
  1901. {
  1902. switch (framesize) {
  1903. case 0x4000:
  1904. return 8192;
  1905. case 0x6000:
  1906. return 16384;
  1907. case 0xa000:
  1908. return 32768;
  1909. case 0xffff:
  1910. return 57344;
  1911. default:
  1912. return 0;
  1913. }
  1914. }
  1915. static inline int qeth_mtu_is_valid(struct qeth_card *card, int mtu)
  1916. {
  1917. switch (card->info.type) {
  1918. case QETH_CARD_TYPE_OSD:
  1919. case QETH_CARD_TYPE_OSM:
  1920. case QETH_CARD_TYPE_OSX:
  1921. case QETH_CARD_TYPE_IQD:
  1922. return ((mtu >= 576) &&
  1923. (mtu <= card->info.max_mtu));
  1924. case QETH_CARD_TYPE_OSN:
  1925. case QETH_CARD_TYPE_UNKNOWN:
  1926. default:
  1927. return 1;
  1928. }
  1929. }
  1930. static int qeth_ulp_enable_cb(struct qeth_card *card, struct qeth_reply *reply,
  1931. unsigned long data)
  1932. {
  1933. __u16 mtu, framesize;
  1934. __u16 len;
  1935. __u8 link_type;
  1936. struct qeth_cmd_buffer *iob;
  1937. QETH_DBF_TEXT(SETUP, 2, "ulpenacb");
  1938. iob = (struct qeth_cmd_buffer *) data;
  1939. memcpy(&card->token.ulp_filter_r,
  1940. QETH_ULP_ENABLE_RESP_FILTER_TOKEN(iob->data),
  1941. QETH_MPC_TOKEN_LENGTH);
  1942. if (card->info.type == QETH_CARD_TYPE_IQD) {
  1943. memcpy(&framesize, QETH_ULP_ENABLE_RESP_MAX_MTU(iob->data), 2);
  1944. mtu = qeth_get_mtu_outof_framesize(framesize);
  1945. if (!mtu) {
  1946. iob->rc = -EINVAL;
  1947. QETH_DBF_TEXT_(SETUP, 2, " rc%d", iob->rc);
  1948. return 0;
  1949. }
  1950. if (card->info.initial_mtu && (card->info.initial_mtu != mtu)) {
  1951. /* frame size has changed */
  1952. if (card->dev &&
  1953. ((card->dev->mtu == card->info.initial_mtu) ||
  1954. (card->dev->mtu > mtu)))
  1955. card->dev->mtu = mtu;
  1956. qeth_free_qdio_buffers(card);
  1957. }
  1958. card->info.initial_mtu = mtu;
  1959. card->info.max_mtu = mtu;
  1960. card->qdio.in_buf_size = mtu + 2 * PAGE_SIZE;
  1961. } else {
  1962. card->info.initial_mtu = qeth_get_initial_mtu_for_card(card);
  1963. card->info.max_mtu = *(__u16 *)QETH_ULP_ENABLE_RESP_MAX_MTU(
  1964. iob->data);
  1965. card->qdio.in_buf_size = QETH_IN_BUF_SIZE_DEFAULT;
  1966. }
  1967. memcpy(&len, QETH_ULP_ENABLE_RESP_DIFINFO_LEN(iob->data), 2);
  1968. if (len >= QETH_MPC_DIFINFO_LEN_INDICATES_LINK_TYPE) {
  1969. memcpy(&link_type,
  1970. QETH_ULP_ENABLE_RESP_LINK_TYPE(iob->data), 1);
  1971. card->info.link_type = link_type;
  1972. } else
  1973. card->info.link_type = 0;
  1974. QETH_DBF_TEXT_(SETUP, 2, "link%d", card->info.link_type);
  1975. QETH_DBF_TEXT_(SETUP, 2, " rc%d", iob->rc);
  1976. return 0;
  1977. }
  1978. static int qeth_ulp_enable(struct qeth_card *card)
  1979. {
  1980. int rc;
  1981. char prot_type;
  1982. struct qeth_cmd_buffer *iob;
  1983. /*FIXME: trace view callbacks*/
  1984. QETH_DBF_TEXT(SETUP, 2, "ulpenabl");
  1985. iob = qeth_wait_for_buffer(&card->write);
  1986. memcpy(iob->data, ULP_ENABLE, ULP_ENABLE_SIZE);
  1987. *(QETH_ULP_ENABLE_LINKNUM(iob->data)) =
  1988. (__u8) card->info.portno;
  1989. if (card->options.layer2)
  1990. if (card->info.type == QETH_CARD_TYPE_OSN)
  1991. prot_type = QETH_PROT_OSN2;
  1992. else
  1993. prot_type = QETH_PROT_LAYER2;
  1994. else
  1995. prot_type = QETH_PROT_TCPIP;
  1996. memcpy(QETH_ULP_ENABLE_PROT_TYPE(iob->data), &prot_type, 1);
  1997. memcpy(QETH_ULP_ENABLE_DEST_ADDR(iob->data),
  1998. &card->token.cm_connection_r, QETH_MPC_TOKEN_LENGTH);
  1999. memcpy(QETH_ULP_ENABLE_FILTER_TOKEN(iob->data),
  2000. &card->token.ulp_filter_w, QETH_MPC_TOKEN_LENGTH);
  2001. memcpy(QETH_ULP_ENABLE_PORTNAME_AND_LL(iob->data),
  2002. card->info.portname, 9);
  2003. rc = qeth_send_control_data(card, ULP_ENABLE_SIZE, iob,
  2004. qeth_ulp_enable_cb, NULL);
  2005. return rc;
  2006. }
  2007. static int qeth_ulp_setup_cb(struct qeth_card *card, struct qeth_reply *reply,
  2008. unsigned long data)
  2009. {
  2010. struct qeth_cmd_buffer *iob;
  2011. int rc = 0;
  2012. QETH_DBF_TEXT(SETUP, 2, "ulpstpcb");
  2013. iob = (struct qeth_cmd_buffer *) data;
  2014. memcpy(&card->token.ulp_connection_r,
  2015. QETH_ULP_SETUP_RESP_CONNECTION_TOKEN(iob->data),
  2016. QETH_MPC_TOKEN_LENGTH);
  2017. if (!strncmp("00S", QETH_ULP_SETUP_RESP_CONNECTION_TOKEN(iob->data),
  2018. 3)) {
  2019. QETH_DBF_TEXT(SETUP, 2, "olmlimit");
  2020. dev_err(&card->gdev->dev, "A connection could not be "
  2021. "established because of an OLM limit\n");
  2022. iob->rc = -EMLINK;
  2023. }
  2024. QETH_DBF_TEXT_(SETUP, 2, " rc%d", iob->rc);
  2025. return rc;
  2026. }
  2027. static int qeth_ulp_setup(struct qeth_card *card)
  2028. {
  2029. int rc;
  2030. __u16 temp;
  2031. struct qeth_cmd_buffer *iob;
  2032. struct ccw_dev_id dev_id;
  2033. QETH_DBF_TEXT(SETUP, 2, "ulpsetup");
  2034. iob = qeth_wait_for_buffer(&card->write);
  2035. memcpy(iob->data, ULP_SETUP, ULP_SETUP_SIZE);
  2036. memcpy(QETH_ULP_SETUP_DEST_ADDR(iob->data),
  2037. &card->token.cm_connection_r, QETH_MPC_TOKEN_LENGTH);
  2038. memcpy(QETH_ULP_SETUP_CONNECTION_TOKEN(iob->data),
  2039. &card->token.ulp_connection_w, QETH_MPC_TOKEN_LENGTH);
  2040. memcpy(QETH_ULP_SETUP_FILTER_TOKEN(iob->data),
  2041. &card->token.ulp_filter_r, QETH_MPC_TOKEN_LENGTH);
  2042. ccw_device_get_id(CARD_DDEV(card), &dev_id);
  2043. memcpy(QETH_ULP_SETUP_CUA(iob->data), &dev_id.devno, 2);
  2044. temp = (card->info.cula << 8) + card->info.unit_addr2;
  2045. memcpy(QETH_ULP_SETUP_REAL_DEVADDR(iob->data), &temp, 2);
  2046. rc = qeth_send_control_data(card, ULP_SETUP_SIZE, iob,
  2047. qeth_ulp_setup_cb, NULL);
  2048. return rc;
  2049. }
  2050. static int qeth_init_qdio_out_buf(struct qeth_qdio_out_q *q, int bidx)
  2051. {
  2052. int rc;
  2053. struct qeth_qdio_out_buffer *newbuf;
  2054. rc = 0;
  2055. newbuf = kmem_cache_zalloc(qeth_qdio_outbuf_cache, GFP_ATOMIC);
  2056. if (!newbuf) {
  2057. rc = -ENOMEM;
  2058. goto out;
  2059. }
  2060. newbuf->buffer = &q->qdio_bufs[bidx];
  2061. skb_queue_head_init(&newbuf->skb_list);
  2062. lockdep_set_class(&newbuf->skb_list.lock, &qdio_out_skb_queue_key);
  2063. newbuf->q = q;
  2064. newbuf->aob = NULL;
  2065. newbuf->next_pending = q->bufs[bidx];
  2066. atomic_set(&newbuf->state, QETH_QDIO_BUF_EMPTY);
  2067. q->bufs[bidx] = newbuf;
  2068. if (q->bufstates) {
  2069. q->bufstates[bidx].user = newbuf;
  2070. QETH_CARD_TEXT_(q->card, 2, "nbs%d", bidx);
  2071. QETH_CARD_TEXT_(q->card, 2, "%lx", (long) newbuf);
  2072. QETH_CARD_TEXT_(q->card, 2, "%lx",
  2073. (long) newbuf->next_pending);
  2074. }
  2075. out:
  2076. return rc;
  2077. }
  2078. static int qeth_alloc_qdio_buffers(struct qeth_card *card)
  2079. {
  2080. int i, j;
  2081. QETH_DBF_TEXT(SETUP, 2, "allcqdbf");
  2082. if (atomic_cmpxchg(&card->qdio.state, QETH_QDIO_UNINITIALIZED,
  2083. QETH_QDIO_ALLOCATED) != QETH_QDIO_UNINITIALIZED)
  2084. return 0;
  2085. card->qdio.in_q = kzalloc(sizeof(struct qeth_qdio_q),
  2086. GFP_KERNEL);
  2087. if (!card->qdio.in_q)
  2088. goto out_nomem;
  2089. QETH_DBF_TEXT(SETUP, 2, "inq");
  2090. QETH_DBF_HEX(SETUP, 2, &card->qdio.in_q, sizeof(void *));
  2091. memset(card->qdio.in_q, 0, sizeof(struct qeth_qdio_q));
  2092. /* give inbound qeth_qdio_buffers their qdio_buffers */
  2093. for (i = 0; i < QDIO_MAX_BUFFERS_PER_Q; ++i) {
  2094. card->qdio.in_q->bufs[i].buffer =
  2095. &card->qdio.in_q->qdio_bufs[i];
  2096. card->qdio.in_q->bufs[i].rx_skb = NULL;
  2097. }
  2098. /* inbound buffer pool */
  2099. if (qeth_alloc_buffer_pool(card))
  2100. goto out_freeinq;
  2101. /* outbound */
  2102. card->qdio.out_qs =
  2103. kzalloc(card->qdio.no_out_queues *
  2104. sizeof(struct qeth_qdio_out_q *), GFP_KERNEL);
  2105. if (!card->qdio.out_qs)
  2106. goto out_freepool;
  2107. for (i = 0; i < card->qdio.no_out_queues; ++i) {
  2108. card->qdio.out_qs[i] = kzalloc(sizeof(struct qeth_qdio_out_q),
  2109. GFP_KERNEL);
  2110. if (!card->qdio.out_qs[i])
  2111. goto out_freeoutq;
  2112. QETH_DBF_TEXT_(SETUP, 2, "outq %i", i);
  2113. QETH_DBF_HEX(SETUP, 2, &card->qdio.out_qs[i], sizeof(void *));
  2114. card->qdio.out_qs[i]->queue_no = i;
  2115. /* give outbound qeth_qdio_buffers their qdio_buffers */
  2116. for (j = 0; j < QDIO_MAX_BUFFERS_PER_Q; ++j) {
  2117. BUG_ON(card->qdio.out_qs[i]->bufs[j] != NULL);
  2118. if (qeth_init_qdio_out_buf(card->qdio.out_qs[i], j))
  2119. goto out_freeoutqbufs;
  2120. }
  2121. }
  2122. /* completion */
  2123. if (qeth_alloc_cq(card))
  2124. goto out_freeoutq;
  2125. return 0;
  2126. out_freeoutqbufs:
  2127. while (j > 0) {
  2128. --j;
  2129. kmem_cache_free(qeth_qdio_outbuf_cache,
  2130. card->qdio.out_qs[i]->bufs[j]);
  2131. card->qdio.out_qs[i]->bufs[j] = NULL;
  2132. }
  2133. out_freeoutq:
  2134. while (i > 0) {
  2135. kfree(card->qdio.out_qs[--i]);
  2136. qeth_clear_outq_buffers(card->qdio.out_qs[i], 1);
  2137. }
  2138. kfree(card->qdio.out_qs);
  2139. card->qdio.out_qs = NULL;
  2140. out_freepool:
  2141. qeth_free_buffer_pool(card);
  2142. out_freeinq:
  2143. kfree(card->qdio.in_q);
  2144. card->qdio.in_q = NULL;
  2145. out_nomem:
  2146. atomic_set(&card->qdio.state, QETH_QDIO_UNINITIALIZED);
  2147. return -ENOMEM;
  2148. }
  2149. static void qeth_create_qib_param_field(struct qeth_card *card,
  2150. char *param_field)
  2151. {
  2152. param_field[0] = _ascebc['P'];
  2153. param_field[1] = _ascebc['C'];
  2154. param_field[2] = _ascebc['I'];
  2155. param_field[3] = _ascebc['T'];
  2156. *((unsigned int *) (&param_field[4])) = QETH_PCI_THRESHOLD_A(card);
  2157. *((unsigned int *) (&param_field[8])) = QETH_PCI_THRESHOLD_B(card);
  2158. *((unsigned int *) (&param_field[12])) = QETH_PCI_TIMER_VALUE(card);
  2159. }
  2160. static void qeth_create_qib_param_field_blkt(struct qeth_card *card,
  2161. char *param_field)
  2162. {
  2163. param_field[16] = _ascebc['B'];
  2164. param_field[17] = _ascebc['L'];
  2165. param_field[18] = _ascebc['K'];
  2166. param_field[19] = _ascebc['T'];
  2167. *((unsigned int *) (&param_field[20])) = card->info.blkt.time_total;
  2168. *((unsigned int *) (&param_field[24])) = card->info.blkt.inter_packet;
  2169. *((unsigned int *) (&param_field[28])) =
  2170. card->info.blkt.inter_packet_jumbo;
  2171. }
  2172. static int qeth_qdio_activate(struct qeth_card *card)
  2173. {
  2174. QETH_DBF_TEXT(SETUP, 3, "qdioact");
  2175. return qdio_activate(CARD_DDEV(card));
  2176. }
  2177. static int qeth_dm_act(struct qeth_card *card)
  2178. {
  2179. int rc;
  2180. struct qeth_cmd_buffer *iob;
  2181. QETH_DBF_TEXT(SETUP, 2, "dmact");
  2182. iob = qeth_wait_for_buffer(&card->write);
  2183. memcpy(iob->data, DM_ACT, DM_ACT_SIZE);
  2184. memcpy(QETH_DM_ACT_DEST_ADDR(iob->data),
  2185. &card->token.cm_connection_r, QETH_MPC_TOKEN_LENGTH);
  2186. memcpy(QETH_DM_ACT_CONNECTION_TOKEN(iob->data),
  2187. &card->token.ulp_connection_r, QETH_MPC_TOKEN_LENGTH);
  2188. rc = qeth_send_control_data(card, DM_ACT_SIZE, iob, NULL, NULL);
  2189. return rc;
  2190. }
  2191. static int qeth_mpc_initialize(struct qeth_card *card)
  2192. {
  2193. int rc;
  2194. QETH_DBF_TEXT(SETUP, 2, "mpcinit");
  2195. rc = qeth_issue_next_read(card);
  2196. if (rc) {
  2197. QETH_DBF_TEXT_(SETUP, 2, "1err%d", rc);
  2198. return rc;
  2199. }
  2200. rc = qeth_cm_enable(card);
  2201. if (rc) {
  2202. QETH_DBF_TEXT_(SETUP, 2, "2err%d", rc);
  2203. goto out_qdio;
  2204. }
  2205. rc = qeth_cm_setup(card);
  2206. if (rc) {
  2207. QETH_DBF_TEXT_(SETUP, 2, "3err%d", rc);
  2208. goto out_qdio;
  2209. }
  2210. rc = qeth_ulp_enable(card);
  2211. if (rc) {
  2212. QETH_DBF_TEXT_(SETUP, 2, "4err%d", rc);
  2213. goto out_qdio;
  2214. }
  2215. rc = qeth_ulp_setup(card);
  2216. if (rc) {
  2217. QETH_DBF_TEXT_(SETUP, 2, "5err%d", rc);
  2218. goto out_qdio;
  2219. }
  2220. rc = qeth_alloc_qdio_buffers(card);
  2221. if (rc) {
  2222. QETH_DBF_TEXT_(SETUP, 2, "5err%d", rc);
  2223. goto out_qdio;
  2224. }
  2225. rc = qeth_qdio_establish(card);
  2226. if (rc) {
  2227. QETH_DBF_TEXT_(SETUP, 2, "6err%d", rc);
  2228. qeth_free_qdio_buffers(card);
  2229. goto out_qdio;
  2230. }
  2231. rc = qeth_qdio_activate(card);
  2232. if (rc) {
  2233. QETH_DBF_TEXT_(SETUP, 2, "7err%d", rc);
  2234. goto out_qdio;
  2235. }
  2236. rc = qeth_dm_act(card);
  2237. if (rc) {
  2238. QETH_DBF_TEXT_(SETUP, 2, "8err%d", rc);
  2239. goto out_qdio;
  2240. }
  2241. return 0;
  2242. out_qdio:
  2243. qeth_qdio_clear_card(card, card->info.type != QETH_CARD_TYPE_IQD);
  2244. return rc;
  2245. }
  2246. static void qeth_print_status_with_portname(struct qeth_card *card)
  2247. {
  2248. char dbf_text[15];
  2249. int i;
  2250. sprintf(dbf_text, "%s", card->info.portname + 1);
  2251. for (i = 0; i < 8; i++)
  2252. dbf_text[i] =
  2253. (char) _ebcasc[(__u8) dbf_text[i]];
  2254. dbf_text[8] = 0;
  2255. dev_info(&card->gdev->dev, "Device is a%s card%s%s%s\n"
  2256. "with link type %s (portname: %s)\n",
  2257. qeth_get_cardname(card),
  2258. (card->info.mcl_level[0]) ? " (level: " : "",
  2259. (card->info.mcl_level[0]) ? card->info.mcl_level : "",
  2260. (card->info.mcl_level[0]) ? ")" : "",
  2261. qeth_get_cardname_short(card),
  2262. dbf_text);
  2263. }
  2264. static void qeth_print_status_no_portname(struct qeth_card *card)
  2265. {
  2266. if (card->info.portname[0])
  2267. dev_info(&card->gdev->dev, "Device is a%s "
  2268. "card%s%s%s\nwith link type %s "
  2269. "(no portname needed by interface).\n",
  2270. qeth_get_cardname(card),
  2271. (card->info.mcl_level[0]) ? " (level: " : "",
  2272. (card->info.mcl_level[0]) ? card->info.mcl_level : "",
  2273. (card->info.mcl_level[0]) ? ")" : "",
  2274. qeth_get_cardname_short(card));
  2275. else
  2276. dev_info(&card->gdev->dev, "Device is a%s "
  2277. "card%s%s%s\nwith link type %s.\n",
  2278. qeth_get_cardname(card),
  2279. (card->info.mcl_level[0]) ? " (level: " : "",
  2280. (card->info.mcl_level[0]) ? card->info.mcl_level : "",
  2281. (card->info.mcl_level[0]) ? ")" : "",
  2282. qeth_get_cardname_short(card));
  2283. }
  2284. void qeth_print_status_message(struct qeth_card *card)
  2285. {
  2286. switch (card->info.type) {
  2287. case QETH_CARD_TYPE_OSD:
  2288. case QETH_CARD_TYPE_OSM:
  2289. case QETH_CARD_TYPE_OSX:
  2290. /* VM will use a non-zero first character
  2291. * to indicate a HiperSockets like reporting
  2292. * of the level OSA sets the first character to zero
  2293. * */
  2294. if (!card->info.mcl_level[0]) {
  2295. sprintf(card->info.mcl_level, "%02x%02x",
  2296. card->info.mcl_level[2],
  2297. card->info.mcl_level[3]);
  2298. card->info.mcl_level[QETH_MCL_LENGTH] = 0;
  2299. break;
  2300. }
  2301. /* fallthrough */
  2302. case QETH_CARD_TYPE_IQD:
  2303. if ((card->info.guestlan) ||
  2304. (card->info.mcl_level[0] & 0x80)) {
  2305. card->info.mcl_level[0] = (char) _ebcasc[(__u8)
  2306. card->info.mcl_level[0]];
  2307. card->info.mcl_level[1] = (char) _ebcasc[(__u8)
  2308. card->info.mcl_level[1]];
  2309. card->info.mcl_level[2] = (char) _ebcasc[(__u8)
  2310. card->info.mcl_level[2]];
  2311. card->info.mcl_level[3] = (char) _ebcasc[(__u8)
  2312. card->info.mcl_level[3]];
  2313. card->info.mcl_level[QETH_MCL_LENGTH] = 0;
  2314. }
  2315. break;
  2316. default:
  2317. memset(&card->info.mcl_level[0], 0, QETH_MCL_LENGTH + 1);
  2318. }
  2319. if (card->info.portname_required)
  2320. qeth_print_status_with_portname(card);
  2321. else
  2322. qeth_print_status_no_portname(card);
  2323. }
  2324. EXPORT_SYMBOL_GPL(qeth_print_status_message);
  2325. static void qeth_initialize_working_pool_list(struct qeth_card *card)
  2326. {
  2327. struct qeth_buffer_pool_entry *entry;
  2328. QETH_CARD_TEXT(card, 5, "inwrklst");
  2329. list_for_each_entry(entry,
  2330. &card->qdio.init_pool.entry_list, init_list) {
  2331. qeth_put_buffer_pool_entry(card, entry);
  2332. }
  2333. }
  2334. static inline struct qeth_buffer_pool_entry *qeth_find_free_buffer_pool_entry(
  2335. struct qeth_card *card)
  2336. {
  2337. struct list_head *plh;
  2338. struct qeth_buffer_pool_entry *entry;
  2339. int i, free;
  2340. struct page *page;
  2341. if (list_empty(&card->qdio.in_buf_pool.entry_list))
  2342. return NULL;
  2343. list_for_each(plh, &card->qdio.in_buf_pool.entry_list) {
  2344. entry = list_entry(plh, struct qeth_buffer_pool_entry, list);
  2345. free = 1;
  2346. for (i = 0; i < QETH_MAX_BUFFER_ELEMENTS(card); ++i) {
  2347. if (page_count(virt_to_page(entry->elements[i])) > 1) {
  2348. free = 0;
  2349. break;
  2350. }
  2351. }
  2352. if (free) {
  2353. list_del_init(&entry->list);
  2354. return entry;
  2355. }
  2356. }
  2357. /* no free buffer in pool so take first one and swap pages */
  2358. entry = list_entry(card->qdio.in_buf_pool.entry_list.next,
  2359. struct qeth_buffer_pool_entry, list);
  2360. for (i = 0; i < QETH_MAX_BUFFER_ELEMENTS(card); ++i) {
  2361. if (page_count(virt_to_page(entry->elements[i])) > 1) {
  2362. page = alloc_page(GFP_ATOMIC);
  2363. if (!page) {
  2364. return NULL;
  2365. } else {
  2366. free_page((unsigned long)entry->elements[i]);
  2367. entry->elements[i] = page_address(page);
  2368. if (card->options.performance_stats)
  2369. card->perf_stats.sg_alloc_page_rx++;
  2370. }
  2371. }
  2372. }
  2373. list_del_init(&entry->list);
  2374. return entry;
  2375. }
  2376. static int qeth_init_input_buffer(struct qeth_card *card,
  2377. struct qeth_qdio_buffer *buf)
  2378. {
  2379. struct qeth_buffer_pool_entry *pool_entry;
  2380. int i;
  2381. if ((card->options.cq == QETH_CQ_ENABLED) && (!buf->rx_skb)) {
  2382. buf->rx_skb = dev_alloc_skb(QETH_RX_PULL_LEN + ETH_HLEN);
  2383. if (!buf->rx_skb)
  2384. return 1;
  2385. }
  2386. pool_entry = qeth_find_free_buffer_pool_entry(card);
  2387. if (!pool_entry)
  2388. return 1;
  2389. /*
  2390. * since the buffer is accessed only from the input_tasklet
  2391. * there shouldn't be a need to synchronize; also, since we use
  2392. * the QETH_IN_BUF_REQUEUE_THRESHOLD we should never run out off
  2393. * buffers
  2394. */
  2395. buf->pool_entry = pool_entry;
  2396. for (i = 0; i < QETH_MAX_BUFFER_ELEMENTS(card); ++i) {
  2397. buf->buffer->element[i].length = PAGE_SIZE;
  2398. buf->buffer->element[i].addr = pool_entry->elements[i];
  2399. if (i == QETH_MAX_BUFFER_ELEMENTS(card) - 1)
  2400. buf->buffer->element[i].eflags = SBAL_EFLAGS_LAST_ENTRY;
  2401. else
  2402. buf->buffer->element[i].eflags = 0;
  2403. buf->buffer->element[i].sflags = 0;
  2404. }
  2405. return 0;
  2406. }
  2407. int qeth_init_qdio_queues(struct qeth_card *card)
  2408. {
  2409. int i, j;
  2410. int rc;
  2411. QETH_DBF_TEXT(SETUP, 2, "initqdqs");
  2412. /* inbound queue */
  2413. memset(card->qdio.in_q->qdio_bufs, 0,
  2414. QDIO_MAX_BUFFERS_PER_Q * sizeof(struct qdio_buffer));
  2415. qeth_initialize_working_pool_list(card);
  2416. /*give only as many buffers to hardware as we have buffer pool entries*/
  2417. for (i = 0; i < card->qdio.in_buf_pool.buf_count - 1; ++i)
  2418. qeth_init_input_buffer(card, &card->qdio.in_q->bufs[i]);
  2419. card->qdio.in_q->next_buf_to_init =
  2420. card->qdio.in_buf_pool.buf_count - 1;
  2421. rc = do_QDIO(CARD_DDEV(card), QDIO_FLAG_SYNC_INPUT, 0, 0,
  2422. card->qdio.in_buf_pool.buf_count - 1);
  2423. if (rc) {
  2424. QETH_DBF_TEXT_(SETUP, 2, "1err%d", rc);
  2425. return rc;
  2426. }
  2427. /* completion */
  2428. rc = qeth_cq_init(card);
  2429. if (rc) {
  2430. return rc;
  2431. }
  2432. /* outbound queue */
  2433. for (i = 0; i < card->qdio.no_out_queues; ++i) {
  2434. memset(card->qdio.out_qs[i]->qdio_bufs, 0,
  2435. QDIO_MAX_BUFFERS_PER_Q * sizeof(struct qdio_buffer));
  2436. for (j = 0; j < QDIO_MAX_BUFFERS_PER_Q; ++j) {
  2437. qeth_clear_output_buffer(card->qdio.out_qs[i],
  2438. card->qdio.out_qs[i]->bufs[j],
  2439. QETH_QDIO_BUF_EMPTY);
  2440. }
  2441. card->qdio.out_qs[i]->card = card;
  2442. card->qdio.out_qs[i]->next_buf_to_fill = 0;
  2443. card->qdio.out_qs[i]->do_pack = 0;
  2444. atomic_set(&card->qdio.out_qs[i]->used_buffers, 0);
  2445. atomic_set(&card->qdio.out_qs[i]->set_pci_flags_count, 0);
  2446. atomic_set(&card->qdio.out_qs[i]->state,
  2447. QETH_OUT_Q_UNLOCKED);
  2448. }
  2449. return 0;
  2450. }
  2451. EXPORT_SYMBOL_GPL(qeth_init_qdio_queues);
  2452. static inline __u8 qeth_get_ipa_adp_type(enum qeth_link_types link_type)
  2453. {
  2454. switch (link_type) {
  2455. case QETH_LINK_TYPE_HSTR:
  2456. return 2;
  2457. default:
  2458. return 1;
  2459. }
  2460. }
  2461. static void qeth_fill_ipacmd_header(struct qeth_card *card,
  2462. struct qeth_ipa_cmd *cmd, __u8 command,
  2463. enum qeth_prot_versions prot)
  2464. {
  2465. memset(cmd, 0, sizeof(struct qeth_ipa_cmd));
  2466. cmd->hdr.command = command;
  2467. cmd->hdr.initiator = IPA_CMD_INITIATOR_HOST;
  2468. cmd->hdr.seqno = card->seqno.ipa;
  2469. cmd->hdr.adapter_type = qeth_get_ipa_adp_type(card->info.link_type);
  2470. cmd->hdr.rel_adapter_no = (__u8) card->info.portno;
  2471. if (card->options.layer2)
  2472. cmd->hdr.prim_version_no = 2;
  2473. else
  2474. cmd->hdr.prim_version_no = 1;
  2475. cmd->hdr.param_count = 1;
  2476. cmd->hdr.prot_version = prot;
  2477. cmd->hdr.ipa_supported = 0;
  2478. cmd->hdr.ipa_enabled = 0;
  2479. }
  2480. struct qeth_cmd_buffer *qeth_get_ipacmd_buffer(struct qeth_card *card,
  2481. enum qeth_ipa_cmds ipacmd, enum qeth_prot_versions prot)
  2482. {
  2483. struct qeth_cmd_buffer *iob;
  2484. struct qeth_ipa_cmd *cmd;
  2485. iob = qeth_wait_for_buffer(&card->write);
  2486. cmd = (struct qeth_ipa_cmd *)(iob->data+IPA_PDU_HEADER_SIZE);
  2487. qeth_fill_ipacmd_header(card, cmd, ipacmd, prot);
  2488. return iob;
  2489. }
  2490. EXPORT_SYMBOL_GPL(qeth_get_ipacmd_buffer);
  2491. void qeth_prepare_ipa_cmd(struct qeth_card *card, struct qeth_cmd_buffer *iob,
  2492. char prot_type)
  2493. {
  2494. memcpy(iob->data, IPA_PDU_HEADER, IPA_PDU_HEADER_SIZE);
  2495. memcpy(QETH_IPA_CMD_PROT_TYPE(iob->data), &prot_type, 1);
  2496. memcpy(QETH_IPA_CMD_DEST_ADDR(iob->data),
  2497. &card->token.ulp_connection_r, QETH_MPC_TOKEN_LENGTH);
  2498. }
  2499. EXPORT_SYMBOL_GPL(qeth_prepare_ipa_cmd);
  2500. int qeth_send_ipa_cmd(struct qeth_card *card, struct qeth_cmd_buffer *iob,
  2501. int (*reply_cb)(struct qeth_card *, struct qeth_reply*,
  2502. unsigned long),
  2503. void *reply_param)
  2504. {
  2505. int rc;
  2506. char prot_type;
  2507. QETH_CARD_TEXT(card, 4, "sendipa");
  2508. if (card->options.layer2)
  2509. if (card->info.type == QETH_CARD_TYPE_OSN)
  2510. prot_type = QETH_PROT_OSN2;
  2511. else
  2512. prot_type = QETH_PROT_LAYER2;
  2513. else
  2514. prot_type = QETH_PROT_TCPIP;
  2515. qeth_prepare_ipa_cmd(card, iob, prot_type);
  2516. rc = qeth_send_control_data(card, IPA_CMD_LENGTH,
  2517. iob, reply_cb, reply_param);
  2518. if (rc == -ETIME) {
  2519. qeth_clear_ipacmd_list(card);
  2520. qeth_schedule_recovery(card);
  2521. }
  2522. return rc;
  2523. }
  2524. EXPORT_SYMBOL_GPL(qeth_send_ipa_cmd);
  2525. int qeth_send_startlan(struct qeth_card *card)
  2526. {
  2527. int rc;
  2528. struct qeth_cmd_buffer *iob;
  2529. QETH_DBF_TEXT(SETUP, 2, "strtlan");
  2530. iob = qeth_get_ipacmd_buffer(card, IPA_CMD_STARTLAN, 0);
  2531. rc = qeth_send_ipa_cmd(card, iob, NULL, NULL);
  2532. return rc;
  2533. }
  2534. EXPORT_SYMBOL_GPL(qeth_send_startlan);
  2535. int qeth_default_setadapterparms_cb(struct qeth_card *card,
  2536. struct qeth_reply *reply, unsigned long data)
  2537. {
  2538. struct qeth_ipa_cmd *cmd;
  2539. QETH_CARD_TEXT(card, 4, "defadpcb");
  2540. cmd = (struct qeth_ipa_cmd *) data;
  2541. if (cmd->hdr.return_code == 0)
  2542. cmd->hdr.return_code =
  2543. cmd->data.setadapterparms.hdr.return_code;
  2544. return 0;
  2545. }
  2546. EXPORT_SYMBOL_GPL(qeth_default_setadapterparms_cb);
  2547. static int qeth_query_setadapterparms_cb(struct qeth_card *card,
  2548. struct qeth_reply *reply, unsigned long data)
  2549. {
  2550. struct qeth_ipa_cmd *cmd;
  2551. QETH_CARD_TEXT(card, 3, "quyadpcb");
  2552. cmd = (struct qeth_ipa_cmd *) data;
  2553. if (cmd->data.setadapterparms.data.query_cmds_supp.lan_type & 0x7f) {
  2554. card->info.link_type =
  2555. cmd->data.setadapterparms.data.query_cmds_supp.lan_type;
  2556. QETH_DBF_TEXT_(SETUP, 2, "lnk %d", card->info.link_type);
  2557. }
  2558. card->options.adp.supported_funcs =
  2559. cmd->data.setadapterparms.data.query_cmds_supp.supported_cmds;
  2560. return qeth_default_setadapterparms_cb(card, reply, (unsigned long)cmd);
  2561. }
  2562. struct qeth_cmd_buffer *qeth_get_adapter_cmd(struct qeth_card *card,
  2563. __u32 command, __u32 cmdlen)
  2564. {
  2565. struct qeth_cmd_buffer *iob;
  2566. struct qeth_ipa_cmd *cmd;
  2567. iob = qeth_get_ipacmd_buffer(card, IPA_CMD_SETADAPTERPARMS,
  2568. QETH_PROT_IPV4);
  2569. cmd = (struct qeth_ipa_cmd *)(iob->data+IPA_PDU_HEADER_SIZE);
  2570. cmd->data.setadapterparms.hdr.cmdlength = cmdlen;
  2571. cmd->data.setadapterparms.hdr.command_code = command;
  2572. cmd->data.setadapterparms.hdr.used_total = 1;
  2573. cmd->data.setadapterparms.hdr.seq_no = 1;
  2574. return iob;
  2575. }
  2576. EXPORT_SYMBOL_GPL(qeth_get_adapter_cmd);
  2577. int qeth_query_setadapterparms(struct qeth_card *card)
  2578. {
  2579. int rc;
  2580. struct qeth_cmd_buffer *iob;
  2581. QETH_CARD_TEXT(card, 3, "queryadp");
  2582. iob = qeth_get_adapter_cmd(card, IPA_SETADP_QUERY_COMMANDS_SUPPORTED,
  2583. sizeof(struct qeth_ipacmd_setadpparms));
  2584. rc = qeth_send_ipa_cmd(card, iob, qeth_query_setadapterparms_cb, NULL);
  2585. return rc;
  2586. }
  2587. EXPORT_SYMBOL_GPL(qeth_query_setadapterparms);
  2588. static int qeth_query_ipassists_cb(struct qeth_card *card,
  2589. struct qeth_reply *reply, unsigned long data)
  2590. {
  2591. struct qeth_ipa_cmd *cmd;
  2592. QETH_DBF_TEXT(SETUP, 2, "qipasscb");
  2593. cmd = (struct qeth_ipa_cmd *) data;
  2594. if (cmd->hdr.prot_version == QETH_PROT_IPV4) {
  2595. card->options.ipa4.supported_funcs = cmd->hdr.ipa_supported;
  2596. card->options.ipa4.enabled_funcs = cmd->hdr.ipa_enabled;
  2597. } else {
  2598. card->options.ipa6.supported_funcs = cmd->hdr.ipa_supported;
  2599. card->options.ipa6.enabled_funcs = cmd->hdr.ipa_enabled;
  2600. }
  2601. QETH_DBF_TEXT(SETUP, 2, "suppenbl");
  2602. QETH_DBF_TEXT_(SETUP, 2, "%x", cmd->hdr.ipa_supported);
  2603. QETH_DBF_TEXT_(SETUP, 2, "%x", cmd->hdr.ipa_enabled);
  2604. return 0;
  2605. }
  2606. int qeth_query_ipassists(struct qeth_card *card, enum qeth_prot_versions prot)
  2607. {
  2608. int rc;
  2609. struct qeth_cmd_buffer *iob;
  2610. QETH_DBF_TEXT_(SETUP, 2, "qipassi%i", prot);
  2611. iob = qeth_get_ipacmd_buffer(card, IPA_CMD_QIPASSIST, prot);
  2612. rc = qeth_send_ipa_cmd(card, iob, qeth_query_ipassists_cb, NULL);
  2613. return rc;
  2614. }
  2615. EXPORT_SYMBOL_GPL(qeth_query_ipassists);
  2616. static int qeth_query_setdiagass_cb(struct qeth_card *card,
  2617. struct qeth_reply *reply, unsigned long data)
  2618. {
  2619. struct qeth_ipa_cmd *cmd;
  2620. __u16 rc;
  2621. cmd = (struct qeth_ipa_cmd *)data;
  2622. rc = cmd->hdr.return_code;
  2623. if (rc)
  2624. QETH_CARD_TEXT_(card, 2, "diagq:%x", rc);
  2625. else
  2626. card->info.diagass_support = cmd->data.diagass.ext;
  2627. return 0;
  2628. }
  2629. static int qeth_query_setdiagass(struct qeth_card *card)
  2630. {
  2631. struct qeth_cmd_buffer *iob;
  2632. struct qeth_ipa_cmd *cmd;
  2633. QETH_DBF_TEXT(SETUP, 2, "qdiagass");
  2634. iob = qeth_get_ipacmd_buffer(card, IPA_CMD_SET_DIAG_ASS, 0);
  2635. cmd = (struct qeth_ipa_cmd *)(iob->data+IPA_PDU_HEADER_SIZE);
  2636. cmd->data.diagass.subcmd_len = 16;
  2637. cmd->data.diagass.subcmd = QETH_DIAGS_CMD_QUERY;
  2638. return qeth_send_ipa_cmd(card, iob, qeth_query_setdiagass_cb, NULL);
  2639. }
  2640. static void qeth_get_trap_id(struct qeth_card *card, struct qeth_trap_id *tid)
  2641. {
  2642. unsigned long info = get_zeroed_page(GFP_KERNEL);
  2643. struct sysinfo_2_2_2 *info222 = (struct sysinfo_2_2_2 *)info;
  2644. struct sysinfo_3_2_2 *info322 = (struct sysinfo_3_2_2 *)info;
  2645. struct ccw_dev_id ccwid;
  2646. int level, rc;
  2647. tid->chpid = card->info.chpid;
  2648. ccw_device_get_id(CARD_RDEV(card), &ccwid);
  2649. tid->ssid = ccwid.ssid;
  2650. tid->devno = ccwid.devno;
  2651. if (!info)
  2652. return;
  2653. rc = stsi(NULL, 0, 0, 0);
  2654. if (rc == -ENOSYS)
  2655. level = rc;
  2656. else
  2657. level = (((unsigned int) rc) >> 28);
  2658. if ((level >= 2) && (stsi(info222, 2, 2, 2) != -ENOSYS))
  2659. tid->lparnr = info222->lpar_number;
  2660. if ((level >= 3) && (stsi(info322, 3, 2, 2) != -ENOSYS)) {
  2661. EBCASC(info322->vm[0].name, sizeof(info322->vm[0].name));
  2662. memcpy(tid->vmname, info322->vm[0].name, sizeof(tid->vmname));
  2663. }
  2664. free_page(info);
  2665. return;
  2666. }
  2667. static int qeth_hw_trap_cb(struct qeth_card *card,
  2668. struct qeth_reply *reply, unsigned long data)
  2669. {
  2670. struct qeth_ipa_cmd *cmd;
  2671. __u16 rc;
  2672. cmd = (struct qeth_ipa_cmd *)data;
  2673. rc = cmd->hdr.return_code;
  2674. if (rc)
  2675. QETH_CARD_TEXT_(card, 2, "trapc:%x", rc);
  2676. return 0;
  2677. }
  2678. int qeth_hw_trap(struct qeth_card *card, enum qeth_diags_trap_action action)
  2679. {
  2680. struct qeth_cmd_buffer *iob;
  2681. struct qeth_ipa_cmd *cmd;
  2682. QETH_DBF_TEXT(SETUP, 2, "diagtrap");
  2683. iob = qeth_get_ipacmd_buffer(card, IPA_CMD_SET_DIAG_ASS, 0);
  2684. cmd = (struct qeth_ipa_cmd *)(iob->data+IPA_PDU_HEADER_SIZE);
  2685. cmd->data.diagass.subcmd_len = 80;
  2686. cmd->data.diagass.subcmd = QETH_DIAGS_CMD_TRAP;
  2687. cmd->data.diagass.type = 1;
  2688. cmd->data.diagass.action = action;
  2689. switch (action) {
  2690. case QETH_DIAGS_TRAP_ARM:
  2691. cmd->data.diagass.options = 0x0003;
  2692. cmd->data.diagass.ext = 0x00010000 +
  2693. sizeof(struct qeth_trap_id);
  2694. qeth_get_trap_id(card,
  2695. (struct qeth_trap_id *)cmd->data.diagass.cdata);
  2696. break;
  2697. case QETH_DIAGS_TRAP_DISARM:
  2698. cmd->data.diagass.options = 0x0001;
  2699. break;
  2700. case QETH_DIAGS_TRAP_CAPTURE:
  2701. break;
  2702. }
  2703. return qeth_send_ipa_cmd(card, iob, qeth_hw_trap_cb, NULL);
  2704. }
  2705. EXPORT_SYMBOL_GPL(qeth_hw_trap);
  2706. int qeth_check_qdio_errors(struct qeth_card *card, struct qdio_buffer *buf,
  2707. unsigned int qdio_error, const char *dbftext)
  2708. {
  2709. if (qdio_error) {
  2710. QETH_CARD_TEXT(card, 2, dbftext);
  2711. QETH_CARD_TEXT_(card, 2, " F15=%02X",
  2712. buf->element[15].sflags);
  2713. QETH_CARD_TEXT_(card, 2, " F14=%02X",
  2714. buf->element[14].sflags);
  2715. QETH_CARD_TEXT_(card, 2, " qerr=%X", qdio_error);
  2716. if ((buf->element[15].sflags) == 0x12) {
  2717. card->stats.rx_dropped++;
  2718. return 0;
  2719. } else
  2720. return 1;
  2721. }
  2722. return 0;
  2723. }
  2724. EXPORT_SYMBOL_GPL(qeth_check_qdio_errors);
  2725. void qeth_buffer_reclaim_work(struct work_struct *work)
  2726. {
  2727. struct qeth_card *card = container_of(work, struct qeth_card,
  2728. buffer_reclaim_work.work);
  2729. QETH_CARD_TEXT_(card, 2, "brw:%x", card->reclaim_index);
  2730. qeth_queue_input_buffer(card, card->reclaim_index);
  2731. }
  2732. void qeth_queue_input_buffer(struct qeth_card *card, int index)
  2733. {
  2734. struct qeth_qdio_q *queue = card->qdio.in_q;
  2735. struct list_head *lh;
  2736. int count;
  2737. int i;
  2738. int rc;
  2739. int newcount = 0;
  2740. count = (index < queue->next_buf_to_init)?
  2741. card->qdio.in_buf_pool.buf_count -
  2742. (queue->next_buf_to_init - index) :
  2743. card->qdio.in_buf_pool.buf_count -
  2744. (queue->next_buf_to_init + QDIO_MAX_BUFFERS_PER_Q - index);
  2745. /* only requeue at a certain threshold to avoid SIGAs */
  2746. if (count >= QETH_IN_BUF_REQUEUE_THRESHOLD(card)) {
  2747. for (i = queue->next_buf_to_init;
  2748. i < queue->next_buf_to_init + count; ++i) {
  2749. if (qeth_init_input_buffer(card,
  2750. &queue->bufs[i % QDIO_MAX_BUFFERS_PER_Q])) {
  2751. break;
  2752. } else {
  2753. newcount++;
  2754. }
  2755. }
  2756. if (newcount < count) {
  2757. /* we are in memory shortage so we switch back to
  2758. traditional skb allocation and drop packages */
  2759. atomic_set(&card->force_alloc_skb, 3);
  2760. count = newcount;
  2761. } else {
  2762. atomic_add_unless(&card->force_alloc_skb, -1, 0);
  2763. }
  2764. if (!count) {
  2765. i = 0;
  2766. list_for_each(lh, &card->qdio.in_buf_pool.entry_list)
  2767. i++;
  2768. if (i == card->qdio.in_buf_pool.buf_count) {
  2769. QETH_CARD_TEXT(card, 2, "qsarbw");
  2770. card->reclaim_index = index;
  2771. schedule_delayed_work(
  2772. &card->buffer_reclaim_work,
  2773. QETH_RECLAIM_WORK_TIME);
  2774. }
  2775. return;
  2776. }
  2777. /*
  2778. * according to old code it should be avoided to requeue all
  2779. * 128 buffers in order to benefit from PCI avoidance.
  2780. * this function keeps at least one buffer (the buffer at
  2781. * 'index') un-requeued -> this buffer is the first buffer that
  2782. * will be requeued the next time
  2783. */
  2784. if (card->options.performance_stats) {
  2785. card->perf_stats.inbound_do_qdio_cnt++;
  2786. card->perf_stats.inbound_do_qdio_start_time =
  2787. qeth_get_micros();
  2788. }
  2789. rc = do_QDIO(CARD_DDEV(card), QDIO_FLAG_SYNC_INPUT, 0,
  2790. queue->next_buf_to_init, count);
  2791. if (card->options.performance_stats)
  2792. card->perf_stats.inbound_do_qdio_time +=
  2793. qeth_get_micros() -
  2794. card->perf_stats.inbound_do_qdio_start_time;
  2795. if (rc) {
  2796. QETH_CARD_TEXT(card, 2, "qinberr");
  2797. }
  2798. queue->next_buf_to_init = (queue->next_buf_to_init + count) %
  2799. QDIO_MAX_BUFFERS_PER_Q;
  2800. }
  2801. }
  2802. EXPORT_SYMBOL_GPL(qeth_queue_input_buffer);
  2803. static int qeth_handle_send_error(struct qeth_card *card,
  2804. struct qeth_qdio_out_buffer *buffer, unsigned int qdio_err)
  2805. {
  2806. int sbalf15 = buffer->buffer->element[15].sflags;
  2807. QETH_CARD_TEXT(card, 6, "hdsnderr");
  2808. if (card->info.type == QETH_CARD_TYPE_IQD) {
  2809. if (sbalf15 == 0) {
  2810. qdio_err = 0;
  2811. } else {
  2812. qdio_err = 1;
  2813. }
  2814. }
  2815. qeth_check_qdio_errors(card, buffer->buffer, qdio_err, "qouterr");
  2816. if (!qdio_err)
  2817. return QETH_SEND_ERROR_NONE;
  2818. if ((sbalf15 >= 15) && (sbalf15 <= 31))
  2819. return QETH_SEND_ERROR_RETRY;
  2820. QETH_CARD_TEXT(card, 1, "lnkfail");
  2821. QETH_CARD_TEXT_(card, 1, "%04x %02x",
  2822. (u16)qdio_err, (u8)sbalf15);
  2823. return QETH_SEND_ERROR_LINK_FAILURE;
  2824. }
  2825. /*
  2826. * Switched to packing state if the number of used buffers on a queue
  2827. * reaches a certain limit.
  2828. */
  2829. static void qeth_switch_to_packing_if_needed(struct qeth_qdio_out_q *queue)
  2830. {
  2831. if (!queue->do_pack) {
  2832. if (atomic_read(&queue->used_buffers)
  2833. >= QETH_HIGH_WATERMARK_PACK){
  2834. /* switch non-PACKING -> PACKING */
  2835. QETH_CARD_TEXT(queue->card, 6, "np->pack");
  2836. if (queue->card->options.performance_stats)
  2837. queue->card->perf_stats.sc_dp_p++;
  2838. queue->do_pack = 1;
  2839. }
  2840. }
  2841. }
  2842. /*
  2843. * Switches from packing to non-packing mode. If there is a packing
  2844. * buffer on the queue this buffer will be prepared to be flushed.
  2845. * In that case 1 is returned to inform the caller. If no buffer
  2846. * has to be flushed, zero is returned.
  2847. */
  2848. static int qeth_switch_to_nonpacking_if_needed(struct qeth_qdio_out_q *queue)
  2849. {
  2850. struct qeth_qdio_out_buffer *buffer;
  2851. int flush_count = 0;
  2852. if (queue->do_pack) {
  2853. if (atomic_read(&queue->used_buffers)
  2854. <= QETH_LOW_WATERMARK_PACK) {
  2855. /* switch PACKING -> non-PACKING */
  2856. QETH_CARD_TEXT(queue->card, 6, "pack->np");
  2857. if (queue->card->options.performance_stats)
  2858. queue->card->perf_stats.sc_p_dp++;
  2859. queue->do_pack = 0;
  2860. /* flush packing buffers */
  2861. buffer = queue->bufs[queue->next_buf_to_fill];
  2862. if ((atomic_read(&buffer->state) ==
  2863. QETH_QDIO_BUF_EMPTY) &&
  2864. (buffer->next_element_to_fill > 0)) {
  2865. atomic_set(&buffer->state,
  2866. QETH_QDIO_BUF_PRIMED);
  2867. flush_count++;
  2868. queue->next_buf_to_fill =
  2869. (queue->next_buf_to_fill + 1) %
  2870. QDIO_MAX_BUFFERS_PER_Q;
  2871. }
  2872. }
  2873. }
  2874. return flush_count;
  2875. }
  2876. /*
  2877. * Called to flush a packing buffer if no more pci flags are on the queue.
  2878. * Checks if there is a packing buffer and prepares it to be flushed.
  2879. * In that case returns 1, otherwise zero.
  2880. */
  2881. static int qeth_flush_buffers_on_no_pci(struct qeth_qdio_out_q *queue)
  2882. {
  2883. struct qeth_qdio_out_buffer *buffer;
  2884. buffer = queue->bufs[queue->next_buf_to_fill];
  2885. if ((atomic_read(&buffer->state) == QETH_QDIO_BUF_EMPTY) &&
  2886. (buffer->next_element_to_fill > 0)) {
  2887. /* it's a packing buffer */
  2888. atomic_set(&buffer->state, QETH_QDIO_BUF_PRIMED);
  2889. queue->next_buf_to_fill =
  2890. (queue->next_buf_to_fill + 1) % QDIO_MAX_BUFFERS_PER_Q;
  2891. return 1;
  2892. }
  2893. return 0;
  2894. }
  2895. static void qeth_flush_buffers(struct qeth_qdio_out_q *queue, int index,
  2896. int count)
  2897. {
  2898. struct qeth_qdio_out_buffer *buf;
  2899. int rc;
  2900. int i;
  2901. unsigned int qdio_flags;
  2902. for (i = index; i < index + count; ++i) {
  2903. int bidx = i % QDIO_MAX_BUFFERS_PER_Q;
  2904. buf = queue->bufs[bidx];
  2905. buf->buffer->element[buf->next_element_to_fill - 1].eflags |=
  2906. SBAL_EFLAGS_LAST_ENTRY;
  2907. if (queue->bufstates)
  2908. queue->bufstates[bidx].user = buf;
  2909. if (queue->card->info.type == QETH_CARD_TYPE_IQD)
  2910. continue;
  2911. if (!queue->do_pack) {
  2912. if ((atomic_read(&queue->used_buffers) >=
  2913. (QETH_HIGH_WATERMARK_PACK -
  2914. QETH_WATERMARK_PACK_FUZZ)) &&
  2915. !atomic_read(&queue->set_pci_flags_count)) {
  2916. /* it's likely that we'll go to packing
  2917. * mode soon */
  2918. atomic_inc(&queue->set_pci_flags_count);
  2919. buf->buffer->element[0].sflags |= SBAL_SFLAGS0_PCI_REQ;
  2920. }
  2921. } else {
  2922. if (!atomic_read(&queue->set_pci_flags_count)) {
  2923. /*
  2924. * there's no outstanding PCI any more, so we
  2925. * have to request a PCI to be sure the the PCI
  2926. * will wake at some time in the future then we
  2927. * can flush packed buffers that might still be
  2928. * hanging around, which can happen if no
  2929. * further send was requested by the stack
  2930. */
  2931. atomic_inc(&queue->set_pci_flags_count);
  2932. buf->buffer->element[0].sflags |= SBAL_SFLAGS0_PCI_REQ;
  2933. }
  2934. }
  2935. }
  2936. queue->card->dev->trans_start = jiffies;
  2937. if (queue->card->options.performance_stats) {
  2938. queue->card->perf_stats.outbound_do_qdio_cnt++;
  2939. queue->card->perf_stats.outbound_do_qdio_start_time =
  2940. qeth_get_micros();
  2941. }
  2942. qdio_flags = QDIO_FLAG_SYNC_OUTPUT;
  2943. if (atomic_read(&queue->set_pci_flags_count))
  2944. qdio_flags |= QDIO_FLAG_PCI_OUT;
  2945. rc = do_QDIO(CARD_DDEV(queue->card), qdio_flags,
  2946. queue->queue_no, index, count);
  2947. if (queue->card->options.performance_stats)
  2948. queue->card->perf_stats.outbound_do_qdio_time +=
  2949. qeth_get_micros() -
  2950. queue->card->perf_stats.outbound_do_qdio_start_time;
  2951. atomic_add(count, &queue->used_buffers);
  2952. if (rc) {
  2953. queue->card->stats.tx_errors += count;
  2954. /* ignore temporary SIGA errors without busy condition */
  2955. if (rc == QDIO_ERROR_SIGA_TARGET)
  2956. return;
  2957. QETH_CARD_TEXT(queue->card, 2, "flushbuf");
  2958. QETH_CARD_TEXT_(queue->card, 2, " q%d", queue->queue_no);
  2959. QETH_CARD_TEXT_(queue->card, 2, " idx%d", index);
  2960. QETH_CARD_TEXT_(queue->card, 2, " c%d", count);
  2961. QETH_CARD_TEXT_(queue->card, 2, " err%d", rc);
  2962. /* this must not happen under normal circumstances. if it
  2963. * happens something is really wrong -> recover */
  2964. qeth_schedule_recovery(queue->card);
  2965. return;
  2966. }
  2967. if (queue->card->options.performance_stats)
  2968. queue->card->perf_stats.bufs_sent += count;
  2969. }
  2970. static void qeth_check_outbound_queue(struct qeth_qdio_out_q *queue)
  2971. {
  2972. int index;
  2973. int flush_cnt = 0;
  2974. int q_was_packing = 0;
  2975. /*
  2976. * check if weed have to switch to non-packing mode or if
  2977. * we have to get a pci flag out on the queue
  2978. */
  2979. if ((atomic_read(&queue->used_buffers) <= QETH_LOW_WATERMARK_PACK) ||
  2980. !atomic_read(&queue->set_pci_flags_count)) {
  2981. if (atomic_xchg(&queue->state, QETH_OUT_Q_LOCKED_FLUSH) ==
  2982. QETH_OUT_Q_UNLOCKED) {
  2983. /*
  2984. * If we get in here, there was no action in
  2985. * do_send_packet. So, we check if there is a
  2986. * packing buffer to be flushed here.
  2987. */
  2988. netif_stop_queue(queue->card->dev);
  2989. index = queue->next_buf_to_fill;
  2990. q_was_packing = queue->do_pack;
  2991. /* queue->do_pack may change */
  2992. barrier();
  2993. flush_cnt += qeth_switch_to_nonpacking_if_needed(queue);
  2994. if (!flush_cnt &&
  2995. !atomic_read(&queue->set_pci_flags_count))
  2996. flush_cnt +=
  2997. qeth_flush_buffers_on_no_pci(queue);
  2998. if (queue->card->options.performance_stats &&
  2999. q_was_packing)
  3000. queue->card->perf_stats.bufs_sent_pack +=
  3001. flush_cnt;
  3002. if (flush_cnt)
  3003. qeth_flush_buffers(queue, index, flush_cnt);
  3004. atomic_set(&queue->state, QETH_OUT_Q_UNLOCKED);
  3005. }
  3006. }
  3007. }
  3008. void qeth_qdio_start_poll(struct ccw_device *ccwdev, int queue,
  3009. unsigned long card_ptr)
  3010. {
  3011. struct qeth_card *card = (struct qeth_card *)card_ptr;
  3012. if (card->dev && (card->dev->flags & IFF_UP))
  3013. napi_schedule(&card->napi);
  3014. }
  3015. EXPORT_SYMBOL_GPL(qeth_qdio_start_poll);
  3016. int qeth_configure_cq(struct qeth_card *card, enum qeth_cq cq)
  3017. {
  3018. int rc;
  3019. if (card->options.cq == QETH_CQ_NOTAVAILABLE) {
  3020. rc = -1;
  3021. goto out;
  3022. } else {
  3023. if (card->options.cq == cq) {
  3024. rc = 0;
  3025. goto out;
  3026. }
  3027. if (card->state != CARD_STATE_DOWN &&
  3028. card->state != CARD_STATE_RECOVER) {
  3029. rc = -1;
  3030. goto out;
  3031. }
  3032. qeth_free_qdio_buffers(card);
  3033. card->options.cq = cq;
  3034. rc = 0;
  3035. }
  3036. out:
  3037. return rc;
  3038. }
  3039. EXPORT_SYMBOL_GPL(qeth_configure_cq);
  3040. static void qeth_qdio_cq_handler(struct qeth_card *card,
  3041. unsigned int qdio_err,
  3042. unsigned int queue, int first_element, int count) {
  3043. struct qeth_qdio_q *cq = card->qdio.c_q;
  3044. int i;
  3045. int rc;
  3046. if (!qeth_is_cq(card, queue))
  3047. goto out;
  3048. QETH_CARD_TEXT_(card, 5, "qcqhe%d", first_element);
  3049. QETH_CARD_TEXT_(card, 5, "qcqhc%d", count);
  3050. QETH_CARD_TEXT_(card, 5, "qcqherr%d", qdio_err);
  3051. if (qdio_err) {
  3052. netif_stop_queue(card->dev);
  3053. qeth_schedule_recovery(card);
  3054. goto out;
  3055. }
  3056. if (card->options.performance_stats) {
  3057. card->perf_stats.cq_cnt++;
  3058. card->perf_stats.cq_start_time = qeth_get_micros();
  3059. }
  3060. for (i = first_element; i < first_element + count; ++i) {
  3061. int bidx = i % QDIO_MAX_BUFFERS_PER_Q;
  3062. struct qdio_buffer *buffer = &cq->qdio_bufs[bidx];
  3063. int e;
  3064. e = 0;
  3065. while (buffer->element[e].addr) {
  3066. unsigned long phys_aob_addr;
  3067. phys_aob_addr = (unsigned long) buffer->element[e].addr;
  3068. qeth_qdio_handle_aob(card, phys_aob_addr);
  3069. buffer->element[e].addr = NULL;
  3070. buffer->element[e].eflags = 0;
  3071. buffer->element[e].sflags = 0;
  3072. buffer->element[e].length = 0;
  3073. ++e;
  3074. }
  3075. buffer->element[15].eflags = 0;
  3076. buffer->element[15].sflags = 0;
  3077. }
  3078. rc = do_QDIO(CARD_DDEV(card), QDIO_FLAG_SYNC_INPUT, queue,
  3079. card->qdio.c_q->next_buf_to_init,
  3080. count);
  3081. if (rc) {
  3082. dev_warn(&card->gdev->dev,
  3083. "QDIO reported an error, rc=%i\n", rc);
  3084. QETH_CARD_TEXT(card, 2, "qcqherr");
  3085. }
  3086. card->qdio.c_q->next_buf_to_init = (card->qdio.c_q->next_buf_to_init
  3087. + count) % QDIO_MAX_BUFFERS_PER_Q;
  3088. netif_wake_queue(card->dev);
  3089. if (card->options.performance_stats) {
  3090. int delta_t = qeth_get_micros();
  3091. delta_t -= card->perf_stats.cq_start_time;
  3092. card->perf_stats.cq_time += delta_t;
  3093. }
  3094. out:
  3095. return;
  3096. }
  3097. void qeth_qdio_input_handler(struct ccw_device *ccwdev, unsigned int qdio_err,
  3098. unsigned int queue, int first_elem, int count,
  3099. unsigned long card_ptr)
  3100. {
  3101. struct qeth_card *card = (struct qeth_card *)card_ptr;
  3102. QETH_CARD_TEXT_(card, 2, "qihq%d", queue);
  3103. QETH_CARD_TEXT_(card, 2, "qiec%d", qdio_err);
  3104. if (qeth_is_cq(card, queue))
  3105. qeth_qdio_cq_handler(card, qdio_err, queue, first_elem, count);
  3106. else if (qdio_err)
  3107. qeth_schedule_recovery(card);
  3108. }
  3109. EXPORT_SYMBOL_GPL(qeth_qdio_input_handler);
  3110. void qeth_qdio_output_handler(struct ccw_device *ccwdev,
  3111. unsigned int qdio_error, int __queue, int first_element,
  3112. int count, unsigned long card_ptr)
  3113. {
  3114. struct qeth_card *card = (struct qeth_card *) card_ptr;
  3115. struct qeth_qdio_out_q *queue = card->qdio.out_qs[__queue];
  3116. struct qeth_qdio_out_buffer *buffer;
  3117. int i;
  3118. QETH_CARD_TEXT(card, 6, "qdouhdl");
  3119. if (qdio_error & QDIO_ERROR_ACTIVATE_CHECK_CONDITION) {
  3120. QETH_CARD_TEXT(card, 2, "achkcond");
  3121. netif_stop_queue(card->dev);
  3122. qeth_schedule_recovery(card);
  3123. return;
  3124. }
  3125. if (card->options.performance_stats) {
  3126. card->perf_stats.outbound_handler_cnt++;
  3127. card->perf_stats.outbound_handler_start_time =
  3128. qeth_get_micros();
  3129. }
  3130. for (i = first_element; i < (first_element + count); ++i) {
  3131. int bidx = i % QDIO_MAX_BUFFERS_PER_Q;
  3132. buffer = queue->bufs[bidx];
  3133. qeth_handle_send_error(card, buffer, qdio_error);
  3134. if (queue->bufstates &&
  3135. (queue->bufstates[bidx].flags &
  3136. QDIO_OUTBUF_STATE_FLAG_PENDING) != 0) {
  3137. BUG_ON(card->options.cq != QETH_CQ_ENABLED);
  3138. if (atomic_cmpxchg(&buffer->state,
  3139. QETH_QDIO_BUF_PRIMED,
  3140. QETH_QDIO_BUF_PENDING) ==
  3141. QETH_QDIO_BUF_PRIMED) {
  3142. qeth_notify_skbs(queue, buffer,
  3143. TX_NOTIFY_PENDING);
  3144. }
  3145. buffer->aob = queue->bufstates[bidx].aob;
  3146. QETH_CARD_TEXT_(queue->card, 5, "pel%d", bidx);
  3147. QETH_CARD_TEXT(queue->card, 5, "aob");
  3148. QETH_CARD_TEXT_(queue->card, 5, "%lx",
  3149. virt_to_phys(buffer->aob));
  3150. BUG_ON(bidx < 0 || bidx >= QDIO_MAX_BUFFERS_PER_Q);
  3151. if (qeth_init_qdio_out_buf(queue, bidx)) {
  3152. QETH_CARD_TEXT(card, 2, "outofbuf");
  3153. qeth_schedule_recovery(card);
  3154. }
  3155. } else {
  3156. if (card->options.cq == QETH_CQ_ENABLED) {
  3157. enum iucv_tx_notify n;
  3158. n = qeth_compute_cq_notification(
  3159. buffer->buffer->element[15].sflags, 0);
  3160. qeth_notify_skbs(queue, buffer, n);
  3161. }
  3162. qeth_clear_output_buffer(queue, buffer,
  3163. QETH_QDIO_BUF_EMPTY);
  3164. }
  3165. qeth_cleanup_handled_pending(queue, bidx, 0);
  3166. }
  3167. atomic_sub(count, &queue->used_buffers);
  3168. /* check if we need to do something on this outbound queue */
  3169. if (card->info.type != QETH_CARD_TYPE_IQD)
  3170. qeth_check_outbound_queue(queue);
  3171. netif_wake_queue(queue->card->dev);
  3172. if (card->options.performance_stats)
  3173. card->perf_stats.outbound_handler_time += qeth_get_micros() -
  3174. card->perf_stats.outbound_handler_start_time;
  3175. }
  3176. EXPORT_SYMBOL_GPL(qeth_qdio_output_handler);
  3177. int qeth_get_priority_queue(struct qeth_card *card, struct sk_buff *skb,
  3178. int ipv, int cast_type)
  3179. {
  3180. if (!ipv && (card->info.type == QETH_CARD_TYPE_OSD ||
  3181. card->info.type == QETH_CARD_TYPE_OSX))
  3182. return card->qdio.default_out_queue;
  3183. switch (card->qdio.no_out_queues) {
  3184. case 4:
  3185. if (cast_type && card->info.is_multicast_different)
  3186. return card->info.is_multicast_different &
  3187. (card->qdio.no_out_queues - 1);
  3188. if (card->qdio.do_prio_queueing && (ipv == 4)) {
  3189. const u8 tos = ip_hdr(skb)->tos;
  3190. if (card->qdio.do_prio_queueing ==
  3191. QETH_PRIO_Q_ING_TOS) {
  3192. if (tos & IP_TOS_NOTIMPORTANT)
  3193. return 3;
  3194. if (tos & IP_TOS_HIGHRELIABILITY)
  3195. return 2;
  3196. if (tos & IP_TOS_HIGHTHROUGHPUT)
  3197. return 1;
  3198. if (tos & IP_TOS_LOWDELAY)
  3199. return 0;
  3200. }
  3201. if (card->qdio.do_prio_queueing ==
  3202. QETH_PRIO_Q_ING_PREC)
  3203. return 3 - (tos >> 6);
  3204. } else if (card->qdio.do_prio_queueing && (ipv == 6)) {
  3205. /* TODO: IPv6!!! */
  3206. }
  3207. return card->qdio.default_out_queue;
  3208. case 1: /* fallthrough for single-out-queue 1920-device */
  3209. default:
  3210. return card->qdio.default_out_queue;
  3211. }
  3212. }
  3213. EXPORT_SYMBOL_GPL(qeth_get_priority_queue);
  3214. int qeth_get_elements_no(struct qeth_card *card, void *hdr,
  3215. struct sk_buff *skb, int elems)
  3216. {
  3217. int dlen = skb->len - skb->data_len;
  3218. int elements_needed = PFN_UP((unsigned long)skb->data + dlen - 1) -
  3219. PFN_DOWN((unsigned long)skb->data);
  3220. elements_needed += skb_shinfo(skb)->nr_frags;
  3221. if ((elements_needed + elems) > QETH_MAX_BUFFER_ELEMENTS(card)) {
  3222. QETH_DBF_MESSAGE(2, "Invalid size of IP packet "
  3223. "(Number=%d / Length=%d). Discarded.\n",
  3224. (elements_needed+elems), skb->len);
  3225. return 0;
  3226. }
  3227. return elements_needed;
  3228. }
  3229. EXPORT_SYMBOL_GPL(qeth_get_elements_no);
  3230. int qeth_hdr_chk_and_bounce(struct sk_buff *skb, int len)
  3231. {
  3232. int hroom, inpage, rest;
  3233. if (((unsigned long)skb->data & PAGE_MASK) !=
  3234. (((unsigned long)skb->data + len - 1) & PAGE_MASK)) {
  3235. hroom = skb_headroom(skb);
  3236. inpage = PAGE_SIZE - ((unsigned long) skb->data % PAGE_SIZE);
  3237. rest = len - inpage;
  3238. if (rest > hroom)
  3239. return 1;
  3240. memmove(skb->data - rest, skb->data, skb->len - skb->data_len);
  3241. skb->data -= rest;
  3242. QETH_DBF_MESSAGE(2, "skb bounce len: %d rest: %d\n", len, rest);
  3243. }
  3244. return 0;
  3245. }
  3246. EXPORT_SYMBOL_GPL(qeth_hdr_chk_and_bounce);
  3247. static inline void __qeth_fill_buffer(struct sk_buff *skb,
  3248. struct qdio_buffer *buffer, int is_tso, int *next_element_to_fill,
  3249. int offset)
  3250. {
  3251. int length = skb->len - skb->data_len;
  3252. int length_here;
  3253. int element;
  3254. char *data;
  3255. int first_lap, cnt;
  3256. struct skb_frag_struct *frag;
  3257. element = *next_element_to_fill;
  3258. data = skb->data;
  3259. first_lap = (is_tso == 0 ? 1 : 0);
  3260. if (offset >= 0) {
  3261. data = skb->data + offset;
  3262. length -= offset;
  3263. first_lap = 0;
  3264. }
  3265. while (length > 0) {
  3266. /* length_here is the remaining amount of data in this page */
  3267. length_here = PAGE_SIZE - ((unsigned long) data % PAGE_SIZE);
  3268. if (length < length_here)
  3269. length_here = length;
  3270. buffer->element[element].addr = data;
  3271. buffer->element[element].length = length_here;
  3272. length -= length_here;
  3273. if (!length) {
  3274. if (first_lap)
  3275. if (skb_shinfo(skb)->nr_frags)
  3276. buffer->element[element].eflags =
  3277. SBAL_EFLAGS_FIRST_FRAG;
  3278. else
  3279. buffer->element[element].eflags = 0;
  3280. else
  3281. buffer->element[element].eflags =
  3282. SBAL_EFLAGS_MIDDLE_FRAG;
  3283. } else {
  3284. if (first_lap)
  3285. buffer->element[element].eflags =
  3286. SBAL_EFLAGS_FIRST_FRAG;
  3287. else
  3288. buffer->element[element].eflags =
  3289. SBAL_EFLAGS_MIDDLE_FRAG;
  3290. }
  3291. data += length_here;
  3292. element++;
  3293. first_lap = 0;
  3294. }
  3295. for (cnt = 0; cnt < skb_shinfo(skb)->nr_frags; cnt++) {
  3296. frag = &skb_shinfo(skb)->frags[cnt];
  3297. buffer->element[element].addr = (char *)
  3298. page_to_phys(skb_frag_page(frag))
  3299. + frag->page_offset;
  3300. buffer->element[element].length = frag->size;
  3301. buffer->element[element].eflags = SBAL_EFLAGS_MIDDLE_FRAG;
  3302. element++;
  3303. }
  3304. if (buffer->element[element - 1].eflags)
  3305. buffer->element[element - 1].eflags = SBAL_EFLAGS_LAST_FRAG;
  3306. *next_element_to_fill = element;
  3307. }
  3308. static inline int qeth_fill_buffer(struct qeth_qdio_out_q *queue,
  3309. struct qeth_qdio_out_buffer *buf, struct sk_buff *skb,
  3310. struct qeth_hdr *hdr, int offset, int hd_len)
  3311. {
  3312. struct qdio_buffer *buffer;
  3313. int flush_cnt = 0, hdr_len, large_send = 0;
  3314. buffer = buf->buffer;
  3315. atomic_inc(&skb->users);
  3316. skb_queue_tail(&buf->skb_list, skb);
  3317. /*check first on TSO ....*/
  3318. if (hdr->hdr.l3.id == QETH_HEADER_TYPE_TSO) {
  3319. int element = buf->next_element_to_fill;
  3320. hdr_len = sizeof(struct qeth_hdr_tso) +
  3321. ((struct qeth_hdr_tso *)hdr)->ext.dg_hdr_len;
  3322. /*fill first buffer entry only with header information */
  3323. buffer->element[element].addr = skb->data;
  3324. buffer->element[element].length = hdr_len;
  3325. buffer->element[element].eflags = SBAL_EFLAGS_FIRST_FRAG;
  3326. buf->next_element_to_fill++;
  3327. skb->data += hdr_len;
  3328. skb->len -= hdr_len;
  3329. large_send = 1;
  3330. }
  3331. if (offset >= 0) {
  3332. int element = buf->next_element_to_fill;
  3333. buffer->element[element].addr = hdr;
  3334. buffer->element[element].length = sizeof(struct qeth_hdr) +
  3335. hd_len;
  3336. buffer->element[element].eflags = SBAL_EFLAGS_FIRST_FRAG;
  3337. buf->is_header[element] = 1;
  3338. buf->next_element_to_fill++;
  3339. }
  3340. __qeth_fill_buffer(skb, buffer, large_send,
  3341. (int *)&buf->next_element_to_fill, offset);
  3342. if (!queue->do_pack) {
  3343. QETH_CARD_TEXT(queue->card, 6, "fillbfnp");
  3344. /* set state to PRIMED -> will be flushed */
  3345. atomic_set(&buf->state, QETH_QDIO_BUF_PRIMED);
  3346. flush_cnt = 1;
  3347. } else {
  3348. QETH_CARD_TEXT(queue->card, 6, "fillbfpa");
  3349. if (queue->card->options.performance_stats)
  3350. queue->card->perf_stats.skbs_sent_pack++;
  3351. if (buf->next_element_to_fill >=
  3352. QETH_MAX_BUFFER_ELEMENTS(queue->card)) {
  3353. /*
  3354. * packed buffer if full -> set state PRIMED
  3355. * -> will be flushed
  3356. */
  3357. atomic_set(&buf->state, QETH_QDIO_BUF_PRIMED);
  3358. flush_cnt = 1;
  3359. }
  3360. }
  3361. return flush_cnt;
  3362. }
  3363. int qeth_do_send_packet_fast(struct qeth_card *card,
  3364. struct qeth_qdio_out_q *queue, struct sk_buff *skb,
  3365. struct qeth_hdr *hdr, int elements_needed,
  3366. int offset, int hd_len)
  3367. {
  3368. struct qeth_qdio_out_buffer *buffer;
  3369. int index;
  3370. /* spin until we get the queue ... */
  3371. while (atomic_cmpxchg(&queue->state, QETH_OUT_Q_UNLOCKED,
  3372. QETH_OUT_Q_LOCKED) != QETH_OUT_Q_UNLOCKED);
  3373. /* ... now we've got the queue */
  3374. index = queue->next_buf_to_fill;
  3375. buffer = queue->bufs[queue->next_buf_to_fill];
  3376. /*
  3377. * check if buffer is empty to make sure that we do not 'overtake'
  3378. * ourselves and try to fill a buffer that is already primed
  3379. */
  3380. if (atomic_read(&buffer->state) != QETH_QDIO_BUF_EMPTY)
  3381. goto out;
  3382. queue->next_buf_to_fill = (queue->next_buf_to_fill + 1) %
  3383. QDIO_MAX_BUFFERS_PER_Q;
  3384. atomic_set(&queue->state, QETH_OUT_Q_UNLOCKED);
  3385. qeth_fill_buffer(queue, buffer, skb, hdr, offset, hd_len);
  3386. qeth_flush_buffers(queue, index, 1);
  3387. return 0;
  3388. out:
  3389. atomic_set(&queue->state, QETH_OUT_Q_UNLOCKED);
  3390. return -EBUSY;
  3391. }
  3392. EXPORT_SYMBOL_GPL(qeth_do_send_packet_fast);
  3393. int qeth_do_send_packet(struct qeth_card *card, struct qeth_qdio_out_q *queue,
  3394. struct sk_buff *skb, struct qeth_hdr *hdr,
  3395. int elements_needed)
  3396. {
  3397. struct qeth_qdio_out_buffer *buffer;
  3398. int start_index;
  3399. int flush_count = 0;
  3400. int do_pack = 0;
  3401. int tmp;
  3402. int rc = 0;
  3403. /* spin until we get the queue ... */
  3404. while (atomic_cmpxchg(&queue->state, QETH_OUT_Q_UNLOCKED,
  3405. QETH_OUT_Q_LOCKED) != QETH_OUT_Q_UNLOCKED);
  3406. start_index = queue->next_buf_to_fill;
  3407. buffer = queue->bufs[queue->next_buf_to_fill];
  3408. /*
  3409. * check if buffer is empty to make sure that we do not 'overtake'
  3410. * ourselves and try to fill a buffer that is already primed
  3411. */
  3412. if (atomic_read(&buffer->state) != QETH_QDIO_BUF_EMPTY) {
  3413. atomic_set(&queue->state, QETH_OUT_Q_UNLOCKED);
  3414. return -EBUSY;
  3415. }
  3416. /* check if we need to switch packing state of this queue */
  3417. qeth_switch_to_packing_if_needed(queue);
  3418. if (queue->do_pack) {
  3419. do_pack = 1;
  3420. /* does packet fit in current buffer? */
  3421. if ((QETH_MAX_BUFFER_ELEMENTS(card) -
  3422. buffer->next_element_to_fill) < elements_needed) {
  3423. /* ... no -> set state PRIMED */
  3424. atomic_set(&buffer->state, QETH_QDIO_BUF_PRIMED);
  3425. flush_count++;
  3426. queue->next_buf_to_fill =
  3427. (queue->next_buf_to_fill + 1) %
  3428. QDIO_MAX_BUFFERS_PER_Q;
  3429. buffer = queue->bufs[queue->next_buf_to_fill];
  3430. /* we did a step forward, so check buffer state
  3431. * again */
  3432. if (atomic_read(&buffer->state) !=
  3433. QETH_QDIO_BUF_EMPTY) {
  3434. qeth_flush_buffers(queue, start_index,
  3435. flush_count);
  3436. atomic_set(&queue->state,
  3437. QETH_OUT_Q_UNLOCKED);
  3438. return -EBUSY;
  3439. }
  3440. }
  3441. }
  3442. tmp = qeth_fill_buffer(queue, buffer, skb, hdr, -1, 0);
  3443. queue->next_buf_to_fill = (queue->next_buf_to_fill + tmp) %
  3444. QDIO_MAX_BUFFERS_PER_Q;
  3445. flush_count += tmp;
  3446. if (flush_count)
  3447. qeth_flush_buffers(queue, start_index, flush_count);
  3448. else if (!atomic_read(&queue->set_pci_flags_count))
  3449. atomic_xchg(&queue->state, QETH_OUT_Q_LOCKED_FLUSH);
  3450. /*
  3451. * queue->state will go from LOCKED -> UNLOCKED or from
  3452. * LOCKED_FLUSH -> LOCKED if output_handler wanted to 'notify' us
  3453. * (switch packing state or flush buffer to get another pci flag out).
  3454. * In that case we will enter this loop
  3455. */
  3456. while (atomic_dec_return(&queue->state)) {
  3457. flush_count = 0;
  3458. start_index = queue->next_buf_to_fill;
  3459. /* check if we can go back to non-packing state */
  3460. flush_count += qeth_switch_to_nonpacking_if_needed(queue);
  3461. /*
  3462. * check if we need to flush a packing buffer to get a pci
  3463. * flag out on the queue
  3464. */
  3465. if (!flush_count && !atomic_read(&queue->set_pci_flags_count))
  3466. flush_count += qeth_flush_buffers_on_no_pci(queue);
  3467. if (flush_count)
  3468. qeth_flush_buffers(queue, start_index, flush_count);
  3469. }
  3470. /* at this point the queue is UNLOCKED again */
  3471. if (queue->card->options.performance_stats && do_pack)
  3472. queue->card->perf_stats.bufs_sent_pack += flush_count;
  3473. return rc;
  3474. }
  3475. EXPORT_SYMBOL_GPL(qeth_do_send_packet);
  3476. static int qeth_setadp_promisc_mode_cb(struct qeth_card *card,
  3477. struct qeth_reply *reply, unsigned long data)
  3478. {
  3479. struct qeth_ipa_cmd *cmd;
  3480. struct qeth_ipacmd_setadpparms *setparms;
  3481. QETH_CARD_TEXT(card, 4, "prmadpcb");
  3482. cmd = (struct qeth_ipa_cmd *) data;
  3483. setparms = &(cmd->data.setadapterparms);
  3484. qeth_default_setadapterparms_cb(card, reply, (unsigned long)cmd);
  3485. if (cmd->hdr.return_code) {
  3486. QETH_CARD_TEXT_(card, 4, "prmrc%2.2x", cmd->hdr.return_code);
  3487. setparms->data.mode = SET_PROMISC_MODE_OFF;
  3488. }
  3489. card->info.promisc_mode = setparms->data.mode;
  3490. return 0;
  3491. }
  3492. void qeth_setadp_promisc_mode(struct qeth_card *card)
  3493. {
  3494. enum qeth_ipa_promisc_modes mode;
  3495. struct net_device *dev = card->dev;
  3496. struct qeth_cmd_buffer *iob;
  3497. struct qeth_ipa_cmd *cmd;
  3498. QETH_CARD_TEXT(card, 4, "setprom");
  3499. if (((dev->flags & IFF_PROMISC) &&
  3500. (card->info.promisc_mode == SET_PROMISC_MODE_ON)) ||
  3501. (!(dev->flags & IFF_PROMISC) &&
  3502. (card->info.promisc_mode == SET_PROMISC_MODE_OFF)))
  3503. return;
  3504. mode = SET_PROMISC_MODE_OFF;
  3505. if (dev->flags & IFF_PROMISC)
  3506. mode = SET_PROMISC_MODE_ON;
  3507. QETH_CARD_TEXT_(card, 4, "mode:%x", mode);
  3508. iob = qeth_get_adapter_cmd(card, IPA_SETADP_SET_PROMISC_MODE,
  3509. sizeof(struct qeth_ipacmd_setadpparms));
  3510. cmd = (struct qeth_ipa_cmd *)(iob->data + IPA_PDU_HEADER_SIZE);
  3511. cmd->data.setadapterparms.data.mode = mode;
  3512. qeth_send_ipa_cmd(card, iob, qeth_setadp_promisc_mode_cb, NULL);
  3513. }
  3514. EXPORT_SYMBOL_GPL(qeth_setadp_promisc_mode);
  3515. int qeth_change_mtu(struct net_device *dev, int new_mtu)
  3516. {
  3517. struct qeth_card *card;
  3518. char dbf_text[15];
  3519. card = dev->ml_priv;
  3520. QETH_CARD_TEXT(card, 4, "chgmtu");
  3521. sprintf(dbf_text, "%8x", new_mtu);
  3522. QETH_CARD_TEXT(card, 4, dbf_text);
  3523. if (new_mtu < 64)
  3524. return -EINVAL;
  3525. if (new_mtu > 65535)
  3526. return -EINVAL;
  3527. if ((!qeth_is_supported(card, IPA_IP_FRAGMENTATION)) &&
  3528. (!qeth_mtu_is_valid(card, new_mtu)))
  3529. return -EINVAL;
  3530. dev->mtu = new_mtu;
  3531. return 0;
  3532. }
  3533. EXPORT_SYMBOL_GPL(qeth_change_mtu);
  3534. struct net_device_stats *qeth_get_stats(struct net_device *dev)
  3535. {
  3536. struct qeth_card *card;
  3537. card = dev->ml_priv;
  3538. QETH_CARD_TEXT(card, 5, "getstat");
  3539. return &card->stats;
  3540. }
  3541. EXPORT_SYMBOL_GPL(qeth_get_stats);
  3542. static int qeth_setadpparms_change_macaddr_cb(struct qeth_card *card,
  3543. struct qeth_reply *reply, unsigned long data)
  3544. {
  3545. struct qeth_ipa_cmd *cmd;
  3546. QETH_CARD_TEXT(card, 4, "chgmaccb");
  3547. cmd = (struct qeth_ipa_cmd *) data;
  3548. if (!card->options.layer2 ||
  3549. !(card->info.mac_bits & QETH_LAYER2_MAC_READ)) {
  3550. memcpy(card->dev->dev_addr,
  3551. &cmd->data.setadapterparms.data.change_addr.addr,
  3552. OSA_ADDR_LEN);
  3553. card->info.mac_bits |= QETH_LAYER2_MAC_READ;
  3554. }
  3555. qeth_default_setadapterparms_cb(card, reply, (unsigned long) cmd);
  3556. return 0;
  3557. }
  3558. int qeth_setadpparms_change_macaddr(struct qeth_card *card)
  3559. {
  3560. int rc;
  3561. struct qeth_cmd_buffer *iob;
  3562. struct qeth_ipa_cmd *cmd;
  3563. QETH_CARD_TEXT(card, 4, "chgmac");
  3564. iob = qeth_get_adapter_cmd(card, IPA_SETADP_ALTER_MAC_ADDRESS,
  3565. sizeof(struct qeth_ipacmd_setadpparms));
  3566. cmd = (struct qeth_ipa_cmd *)(iob->data+IPA_PDU_HEADER_SIZE);
  3567. cmd->data.setadapterparms.data.change_addr.cmd = CHANGE_ADDR_READ_MAC;
  3568. cmd->data.setadapterparms.data.change_addr.addr_size = OSA_ADDR_LEN;
  3569. memcpy(&cmd->data.setadapterparms.data.change_addr.addr,
  3570. card->dev->dev_addr, OSA_ADDR_LEN);
  3571. rc = qeth_send_ipa_cmd(card, iob, qeth_setadpparms_change_macaddr_cb,
  3572. NULL);
  3573. return rc;
  3574. }
  3575. EXPORT_SYMBOL_GPL(qeth_setadpparms_change_macaddr);
  3576. static int qeth_setadpparms_set_access_ctrl_cb(struct qeth_card *card,
  3577. struct qeth_reply *reply, unsigned long data)
  3578. {
  3579. struct qeth_ipa_cmd *cmd;
  3580. struct qeth_set_access_ctrl *access_ctrl_req;
  3581. QETH_CARD_TEXT(card, 4, "setaccb");
  3582. cmd = (struct qeth_ipa_cmd *) data;
  3583. access_ctrl_req = &cmd->data.setadapterparms.data.set_access_ctrl;
  3584. QETH_DBF_TEXT_(SETUP, 2, "setaccb");
  3585. QETH_DBF_TEXT_(SETUP, 2, "%s", card->gdev->dev.kobj.name);
  3586. QETH_DBF_TEXT_(SETUP, 2, "rc=%d",
  3587. cmd->data.setadapterparms.hdr.return_code);
  3588. switch (cmd->data.setadapterparms.hdr.return_code) {
  3589. case SET_ACCESS_CTRL_RC_SUCCESS:
  3590. case SET_ACCESS_CTRL_RC_ALREADY_NOT_ISOLATED:
  3591. case SET_ACCESS_CTRL_RC_ALREADY_ISOLATED:
  3592. {
  3593. card->options.isolation = access_ctrl_req->subcmd_code;
  3594. if (card->options.isolation == ISOLATION_MODE_NONE) {
  3595. dev_info(&card->gdev->dev,
  3596. "QDIO data connection isolation is deactivated\n");
  3597. } else {
  3598. dev_info(&card->gdev->dev,
  3599. "QDIO data connection isolation is activated\n");
  3600. }
  3601. QETH_DBF_MESSAGE(3, "OK:SET_ACCESS_CTRL(%s, %d)==%d\n",
  3602. card->gdev->dev.kobj.name,
  3603. access_ctrl_req->subcmd_code,
  3604. cmd->data.setadapterparms.hdr.return_code);
  3605. break;
  3606. }
  3607. case SET_ACCESS_CTRL_RC_NOT_SUPPORTED:
  3608. {
  3609. QETH_DBF_MESSAGE(3, "ERR:SET_ACCESS_CTRL(%s,%d)==%d\n",
  3610. card->gdev->dev.kobj.name,
  3611. access_ctrl_req->subcmd_code,
  3612. cmd->data.setadapterparms.hdr.return_code);
  3613. dev_err(&card->gdev->dev, "Adapter does not "
  3614. "support QDIO data connection isolation\n");
  3615. /* ensure isolation mode is "none" */
  3616. card->options.isolation = ISOLATION_MODE_NONE;
  3617. break;
  3618. }
  3619. case SET_ACCESS_CTRL_RC_NONE_SHARED_ADAPTER:
  3620. {
  3621. QETH_DBF_MESSAGE(3, "ERR:SET_ACCESS_MODE(%s,%d)==%d\n",
  3622. card->gdev->dev.kobj.name,
  3623. access_ctrl_req->subcmd_code,
  3624. cmd->data.setadapterparms.hdr.return_code);
  3625. dev_err(&card->gdev->dev,
  3626. "Adapter is dedicated. "
  3627. "QDIO data connection isolation not supported\n");
  3628. /* ensure isolation mode is "none" */
  3629. card->options.isolation = ISOLATION_MODE_NONE;
  3630. break;
  3631. }
  3632. case SET_ACCESS_CTRL_RC_ACTIVE_CHECKSUM_OFF:
  3633. {
  3634. QETH_DBF_MESSAGE(3, "ERR:SET_ACCESS_MODE(%s,%d)==%d\n",
  3635. card->gdev->dev.kobj.name,
  3636. access_ctrl_req->subcmd_code,
  3637. cmd->data.setadapterparms.hdr.return_code);
  3638. dev_err(&card->gdev->dev,
  3639. "TSO does not permit QDIO data connection isolation\n");
  3640. /* ensure isolation mode is "none" */
  3641. card->options.isolation = ISOLATION_MODE_NONE;
  3642. break;
  3643. }
  3644. default:
  3645. {
  3646. /* this should never happen */
  3647. QETH_DBF_MESSAGE(3, "ERR:SET_ACCESS_MODE(%s,%d)==%d"
  3648. "==UNKNOWN\n",
  3649. card->gdev->dev.kobj.name,
  3650. access_ctrl_req->subcmd_code,
  3651. cmd->data.setadapterparms.hdr.return_code);
  3652. /* ensure isolation mode is "none" */
  3653. card->options.isolation = ISOLATION_MODE_NONE;
  3654. break;
  3655. }
  3656. }
  3657. qeth_default_setadapterparms_cb(card, reply, (unsigned long) cmd);
  3658. return 0;
  3659. }
  3660. static int qeth_setadpparms_set_access_ctrl(struct qeth_card *card,
  3661. enum qeth_ipa_isolation_modes isolation)
  3662. {
  3663. int rc;
  3664. struct qeth_cmd_buffer *iob;
  3665. struct qeth_ipa_cmd *cmd;
  3666. struct qeth_set_access_ctrl *access_ctrl_req;
  3667. QETH_CARD_TEXT(card, 4, "setacctl");
  3668. QETH_DBF_TEXT_(SETUP, 2, "setacctl");
  3669. QETH_DBF_TEXT_(SETUP, 2, "%s", card->gdev->dev.kobj.name);
  3670. iob = qeth_get_adapter_cmd(card, IPA_SETADP_SET_ACCESS_CONTROL,
  3671. sizeof(struct qeth_ipacmd_setadpparms_hdr) +
  3672. sizeof(struct qeth_set_access_ctrl));
  3673. cmd = (struct qeth_ipa_cmd *)(iob->data+IPA_PDU_HEADER_SIZE);
  3674. access_ctrl_req = &cmd->data.setadapterparms.data.set_access_ctrl;
  3675. access_ctrl_req->subcmd_code = isolation;
  3676. rc = qeth_send_ipa_cmd(card, iob, qeth_setadpparms_set_access_ctrl_cb,
  3677. NULL);
  3678. QETH_DBF_TEXT_(SETUP, 2, "rc=%d", rc);
  3679. return rc;
  3680. }
  3681. int qeth_set_access_ctrl_online(struct qeth_card *card)
  3682. {
  3683. int rc = 0;
  3684. QETH_CARD_TEXT(card, 4, "setactlo");
  3685. if ((card->info.type == QETH_CARD_TYPE_OSD ||
  3686. card->info.type == QETH_CARD_TYPE_OSX) &&
  3687. qeth_adp_supported(card, IPA_SETADP_SET_ACCESS_CONTROL)) {
  3688. rc = qeth_setadpparms_set_access_ctrl(card,
  3689. card->options.isolation);
  3690. if (rc) {
  3691. QETH_DBF_MESSAGE(3,
  3692. "IPA(SET_ACCESS_CTRL,%s,%d) sent failed\n",
  3693. card->gdev->dev.kobj.name,
  3694. rc);
  3695. }
  3696. } else if (card->options.isolation != ISOLATION_MODE_NONE) {
  3697. card->options.isolation = ISOLATION_MODE_NONE;
  3698. dev_err(&card->gdev->dev, "Adapter does not "
  3699. "support QDIO data connection isolation\n");
  3700. rc = -EOPNOTSUPP;
  3701. }
  3702. return rc;
  3703. }
  3704. EXPORT_SYMBOL_GPL(qeth_set_access_ctrl_online);
  3705. void qeth_tx_timeout(struct net_device *dev)
  3706. {
  3707. struct qeth_card *card;
  3708. card = dev->ml_priv;
  3709. QETH_CARD_TEXT(card, 4, "txtimeo");
  3710. card->stats.tx_errors++;
  3711. qeth_schedule_recovery(card);
  3712. }
  3713. EXPORT_SYMBOL_GPL(qeth_tx_timeout);
  3714. int qeth_mdio_read(struct net_device *dev, int phy_id, int regnum)
  3715. {
  3716. struct qeth_card *card = dev->ml_priv;
  3717. int rc = 0;
  3718. switch (regnum) {
  3719. case MII_BMCR: /* Basic mode control register */
  3720. rc = BMCR_FULLDPLX;
  3721. if ((card->info.link_type != QETH_LINK_TYPE_GBIT_ETH) &&
  3722. (card->info.link_type != QETH_LINK_TYPE_OSN) &&
  3723. (card->info.link_type != QETH_LINK_TYPE_10GBIT_ETH))
  3724. rc |= BMCR_SPEED100;
  3725. break;
  3726. case MII_BMSR: /* Basic mode status register */
  3727. rc = BMSR_ERCAP | BMSR_ANEGCOMPLETE | BMSR_LSTATUS |
  3728. BMSR_10HALF | BMSR_10FULL | BMSR_100HALF | BMSR_100FULL |
  3729. BMSR_100BASE4;
  3730. break;
  3731. case MII_PHYSID1: /* PHYS ID 1 */
  3732. rc = (dev->dev_addr[0] << 16) | (dev->dev_addr[1] << 8) |
  3733. dev->dev_addr[2];
  3734. rc = (rc >> 5) & 0xFFFF;
  3735. break;
  3736. case MII_PHYSID2: /* PHYS ID 2 */
  3737. rc = (dev->dev_addr[2] << 10) & 0xFFFF;
  3738. break;
  3739. case MII_ADVERTISE: /* Advertisement control reg */
  3740. rc = ADVERTISE_ALL;
  3741. break;
  3742. case MII_LPA: /* Link partner ability reg */
  3743. rc = LPA_10HALF | LPA_10FULL | LPA_100HALF | LPA_100FULL |
  3744. LPA_100BASE4 | LPA_LPACK;
  3745. break;
  3746. case MII_EXPANSION: /* Expansion register */
  3747. break;
  3748. case MII_DCOUNTER: /* disconnect counter */
  3749. break;
  3750. case MII_FCSCOUNTER: /* false carrier counter */
  3751. break;
  3752. case MII_NWAYTEST: /* N-way auto-neg test register */
  3753. break;
  3754. case MII_RERRCOUNTER: /* rx error counter */
  3755. rc = card->stats.rx_errors;
  3756. break;
  3757. case MII_SREVISION: /* silicon revision */
  3758. break;
  3759. case MII_RESV1: /* reserved 1 */
  3760. break;
  3761. case MII_LBRERROR: /* loopback, rx, bypass error */
  3762. break;
  3763. case MII_PHYADDR: /* physical address */
  3764. break;
  3765. case MII_RESV2: /* reserved 2 */
  3766. break;
  3767. case MII_TPISTATUS: /* TPI status for 10mbps */
  3768. break;
  3769. case MII_NCONFIG: /* network interface config */
  3770. break;
  3771. default:
  3772. break;
  3773. }
  3774. return rc;
  3775. }
  3776. EXPORT_SYMBOL_GPL(qeth_mdio_read);
  3777. static int qeth_send_ipa_snmp_cmd(struct qeth_card *card,
  3778. struct qeth_cmd_buffer *iob, int len,
  3779. int (*reply_cb)(struct qeth_card *, struct qeth_reply *,
  3780. unsigned long),
  3781. void *reply_param)
  3782. {
  3783. u16 s1, s2;
  3784. QETH_CARD_TEXT(card, 4, "sendsnmp");
  3785. memcpy(iob->data, IPA_PDU_HEADER, IPA_PDU_HEADER_SIZE);
  3786. memcpy(QETH_IPA_CMD_DEST_ADDR(iob->data),
  3787. &card->token.ulp_connection_r, QETH_MPC_TOKEN_LENGTH);
  3788. /* adjust PDU length fields in IPA_PDU_HEADER */
  3789. s1 = (u32) IPA_PDU_HEADER_SIZE + len;
  3790. s2 = (u32) len;
  3791. memcpy(QETH_IPA_PDU_LEN_TOTAL(iob->data), &s1, 2);
  3792. memcpy(QETH_IPA_PDU_LEN_PDU1(iob->data), &s2, 2);
  3793. memcpy(QETH_IPA_PDU_LEN_PDU2(iob->data), &s2, 2);
  3794. memcpy(QETH_IPA_PDU_LEN_PDU3(iob->data), &s2, 2);
  3795. return qeth_send_control_data(card, IPA_PDU_HEADER_SIZE + len, iob,
  3796. reply_cb, reply_param);
  3797. }
  3798. static int qeth_snmp_command_cb(struct qeth_card *card,
  3799. struct qeth_reply *reply, unsigned long sdata)
  3800. {
  3801. struct qeth_ipa_cmd *cmd;
  3802. struct qeth_arp_query_info *qinfo;
  3803. struct qeth_snmp_cmd *snmp;
  3804. unsigned char *data;
  3805. __u16 data_len;
  3806. QETH_CARD_TEXT(card, 3, "snpcmdcb");
  3807. cmd = (struct qeth_ipa_cmd *) sdata;
  3808. data = (unsigned char *)((char *)cmd - reply->offset);
  3809. qinfo = (struct qeth_arp_query_info *) reply->param;
  3810. snmp = &cmd->data.setadapterparms.data.snmp;
  3811. if (cmd->hdr.return_code) {
  3812. QETH_CARD_TEXT_(card, 4, "scer1%i", cmd->hdr.return_code);
  3813. return 0;
  3814. }
  3815. if (cmd->data.setadapterparms.hdr.return_code) {
  3816. cmd->hdr.return_code =
  3817. cmd->data.setadapterparms.hdr.return_code;
  3818. QETH_CARD_TEXT_(card, 4, "scer2%i", cmd->hdr.return_code);
  3819. return 0;
  3820. }
  3821. data_len = *((__u16 *)QETH_IPA_PDU_LEN_PDU1(data));
  3822. if (cmd->data.setadapterparms.hdr.seq_no == 1)
  3823. data_len -= (__u16)((char *)&snmp->data - (char *)cmd);
  3824. else
  3825. data_len -= (__u16)((char *)&snmp->request - (char *)cmd);
  3826. /* check if there is enough room in userspace */
  3827. if ((qinfo->udata_len - qinfo->udata_offset) < data_len) {
  3828. QETH_CARD_TEXT_(card, 4, "scer3%i", -ENOMEM);
  3829. cmd->hdr.return_code = -ENOMEM;
  3830. return 0;
  3831. }
  3832. QETH_CARD_TEXT_(card, 4, "snore%i",
  3833. cmd->data.setadapterparms.hdr.used_total);
  3834. QETH_CARD_TEXT_(card, 4, "sseqn%i",
  3835. cmd->data.setadapterparms.hdr.seq_no);
  3836. /*copy entries to user buffer*/
  3837. if (cmd->data.setadapterparms.hdr.seq_no == 1) {
  3838. memcpy(qinfo->udata + qinfo->udata_offset,
  3839. (char *)snmp,
  3840. data_len + offsetof(struct qeth_snmp_cmd, data));
  3841. qinfo->udata_offset += offsetof(struct qeth_snmp_cmd, data);
  3842. } else {
  3843. memcpy(qinfo->udata + qinfo->udata_offset,
  3844. (char *)&snmp->request, data_len);
  3845. }
  3846. qinfo->udata_offset += data_len;
  3847. /* check if all replies received ... */
  3848. QETH_CARD_TEXT_(card, 4, "srtot%i",
  3849. cmd->data.setadapterparms.hdr.used_total);
  3850. QETH_CARD_TEXT_(card, 4, "srseq%i",
  3851. cmd->data.setadapterparms.hdr.seq_no);
  3852. if (cmd->data.setadapterparms.hdr.seq_no <
  3853. cmd->data.setadapterparms.hdr.used_total)
  3854. return 1;
  3855. return 0;
  3856. }
  3857. int qeth_snmp_command(struct qeth_card *card, char __user *udata)
  3858. {
  3859. struct qeth_cmd_buffer *iob;
  3860. struct qeth_ipa_cmd *cmd;
  3861. struct qeth_snmp_ureq *ureq;
  3862. int req_len;
  3863. struct qeth_arp_query_info qinfo = {0, };
  3864. int rc = 0;
  3865. QETH_CARD_TEXT(card, 3, "snmpcmd");
  3866. if (card->info.guestlan)
  3867. return -EOPNOTSUPP;
  3868. if ((!qeth_adp_supported(card, IPA_SETADP_SET_SNMP_CONTROL)) &&
  3869. (!card->options.layer2)) {
  3870. return -EOPNOTSUPP;
  3871. }
  3872. /* skip 4 bytes (data_len struct member) to get req_len */
  3873. if (copy_from_user(&req_len, udata + sizeof(int), sizeof(int)))
  3874. return -EFAULT;
  3875. ureq = memdup_user(udata, req_len + sizeof(struct qeth_snmp_ureq_hdr));
  3876. if (IS_ERR(ureq)) {
  3877. QETH_CARD_TEXT(card, 2, "snmpnome");
  3878. return PTR_ERR(ureq);
  3879. }
  3880. qinfo.udata_len = ureq->hdr.data_len;
  3881. qinfo.udata = kzalloc(qinfo.udata_len, GFP_KERNEL);
  3882. if (!qinfo.udata) {
  3883. kfree(ureq);
  3884. return -ENOMEM;
  3885. }
  3886. qinfo.udata_offset = sizeof(struct qeth_snmp_ureq_hdr);
  3887. iob = qeth_get_adapter_cmd(card, IPA_SETADP_SET_SNMP_CONTROL,
  3888. QETH_SNMP_SETADP_CMDLENGTH + req_len);
  3889. cmd = (struct qeth_ipa_cmd *)(iob->data+IPA_PDU_HEADER_SIZE);
  3890. memcpy(&cmd->data.setadapterparms.data.snmp, &ureq->cmd, req_len);
  3891. rc = qeth_send_ipa_snmp_cmd(card, iob, QETH_SETADP_BASE_LEN + req_len,
  3892. qeth_snmp_command_cb, (void *)&qinfo);
  3893. if (rc)
  3894. QETH_DBF_MESSAGE(2, "SNMP command failed on %s: (0x%x)\n",
  3895. QETH_CARD_IFNAME(card), rc);
  3896. else {
  3897. if (copy_to_user(udata, qinfo.udata, qinfo.udata_len))
  3898. rc = -EFAULT;
  3899. }
  3900. kfree(ureq);
  3901. kfree(qinfo.udata);
  3902. return rc;
  3903. }
  3904. EXPORT_SYMBOL_GPL(qeth_snmp_command);
  3905. static inline int qeth_get_qdio_q_format(struct qeth_card *card)
  3906. {
  3907. switch (card->info.type) {
  3908. case QETH_CARD_TYPE_IQD:
  3909. return 2;
  3910. default:
  3911. return 0;
  3912. }
  3913. }
  3914. static void qeth_determine_capabilities(struct qeth_card *card)
  3915. {
  3916. int rc;
  3917. int length;
  3918. char *prcd;
  3919. struct ccw_device *ddev;
  3920. int ddev_offline = 0;
  3921. QETH_DBF_TEXT(SETUP, 2, "detcapab");
  3922. ddev = CARD_DDEV(card);
  3923. if (!ddev->online) {
  3924. ddev_offline = 1;
  3925. rc = ccw_device_set_online(ddev);
  3926. if (rc) {
  3927. QETH_DBF_TEXT_(SETUP, 2, "3err%d", rc);
  3928. goto out;
  3929. }
  3930. }
  3931. rc = qeth_read_conf_data(card, (void **) &prcd, &length);
  3932. if (rc) {
  3933. QETH_DBF_MESSAGE(2, "%s qeth_read_conf_data returned %i\n",
  3934. dev_name(&card->gdev->dev), rc);
  3935. QETH_DBF_TEXT_(SETUP, 2, "5err%d", rc);
  3936. goto out_offline;
  3937. }
  3938. qeth_configure_unitaddr(card, prcd);
  3939. qeth_configure_blkt_default(card, prcd);
  3940. kfree(prcd);
  3941. rc = qdio_get_ssqd_desc(ddev, &card->ssqd);
  3942. if (rc)
  3943. QETH_DBF_TEXT_(SETUP, 2, "6err%d", rc);
  3944. QETH_DBF_TEXT_(SETUP, 2, "qfmt%d", card->ssqd.qfmt);
  3945. QETH_DBF_TEXT_(SETUP, 2, "%d", card->ssqd.qdioac1);
  3946. QETH_DBF_TEXT_(SETUP, 2, "%d", card->ssqd.qdioac3);
  3947. QETH_DBF_TEXT_(SETUP, 2, "icnt%d", card->ssqd.icnt);
  3948. if (!((card->ssqd.qfmt != QDIO_IQDIO_QFMT) ||
  3949. ((card->ssqd.qdioac1 & CHSC_AC1_INITIATE_INPUTQ) == 0) ||
  3950. ((card->ssqd.qdioac3 & CHSC_AC3_FORMAT2_CQ_AVAILABLE) == 0))) {
  3951. dev_info(&card->gdev->dev,
  3952. "Completion Queueing supported\n");
  3953. } else {
  3954. card->options.cq = QETH_CQ_NOTAVAILABLE;
  3955. }
  3956. out_offline:
  3957. if (ddev_offline == 1)
  3958. ccw_device_set_offline(ddev);
  3959. out:
  3960. return;
  3961. }
  3962. static inline void qeth_qdio_establish_cq(struct qeth_card *card,
  3963. struct qdio_buffer **in_sbal_ptrs,
  3964. void (**queue_start_poll) (struct ccw_device *, int, unsigned long)) {
  3965. int i;
  3966. if (card->options.cq == QETH_CQ_ENABLED) {
  3967. int offset = QDIO_MAX_BUFFERS_PER_Q *
  3968. (card->qdio.no_in_queues - 1);
  3969. i = QDIO_MAX_BUFFERS_PER_Q * (card->qdio.no_in_queues - 1);
  3970. for (i = 0; i < QDIO_MAX_BUFFERS_PER_Q; ++i) {
  3971. in_sbal_ptrs[offset + i] = (struct qdio_buffer *)
  3972. virt_to_phys(card->qdio.c_q->bufs[i].buffer);
  3973. }
  3974. queue_start_poll[card->qdio.no_in_queues - 1] = NULL;
  3975. }
  3976. }
  3977. static int qeth_qdio_establish(struct qeth_card *card)
  3978. {
  3979. struct qdio_initialize init_data;
  3980. char *qib_param_field;
  3981. struct qdio_buffer **in_sbal_ptrs;
  3982. void (**queue_start_poll) (struct ccw_device *, int, unsigned long);
  3983. struct qdio_buffer **out_sbal_ptrs;
  3984. int i, j, k;
  3985. int rc = 0;
  3986. QETH_DBF_TEXT(SETUP, 2, "qdioest");
  3987. qib_param_field = kzalloc(QDIO_MAX_BUFFERS_PER_Q * sizeof(char),
  3988. GFP_KERNEL);
  3989. if (!qib_param_field) {
  3990. rc = -ENOMEM;
  3991. goto out_free_nothing;
  3992. }
  3993. qeth_create_qib_param_field(card, qib_param_field);
  3994. qeth_create_qib_param_field_blkt(card, qib_param_field);
  3995. in_sbal_ptrs = kzalloc(card->qdio.no_in_queues *
  3996. QDIO_MAX_BUFFERS_PER_Q * sizeof(void *),
  3997. GFP_KERNEL);
  3998. if (!in_sbal_ptrs) {
  3999. rc = -ENOMEM;
  4000. goto out_free_qib_param;
  4001. }
  4002. for (i = 0; i < QDIO_MAX_BUFFERS_PER_Q; ++i) {
  4003. in_sbal_ptrs[i] = (struct qdio_buffer *)
  4004. virt_to_phys(card->qdio.in_q->bufs[i].buffer);
  4005. }
  4006. queue_start_poll = kzalloc(sizeof(void *) * card->qdio.no_in_queues,
  4007. GFP_KERNEL);
  4008. if (!queue_start_poll) {
  4009. rc = -ENOMEM;
  4010. goto out_free_in_sbals;
  4011. }
  4012. for (i = 0; i < card->qdio.no_in_queues; ++i)
  4013. queue_start_poll[i] = card->discipline.start_poll;
  4014. qeth_qdio_establish_cq(card, in_sbal_ptrs, queue_start_poll);
  4015. out_sbal_ptrs =
  4016. kzalloc(card->qdio.no_out_queues * QDIO_MAX_BUFFERS_PER_Q *
  4017. sizeof(void *), GFP_KERNEL);
  4018. if (!out_sbal_ptrs) {
  4019. rc = -ENOMEM;
  4020. goto out_free_queue_start_poll;
  4021. }
  4022. for (i = 0, k = 0; i < card->qdio.no_out_queues; ++i)
  4023. for (j = 0; j < QDIO_MAX_BUFFERS_PER_Q; ++j, ++k) {
  4024. out_sbal_ptrs[k] = (struct qdio_buffer *)virt_to_phys(
  4025. card->qdio.out_qs[i]->bufs[j]->buffer);
  4026. }
  4027. memset(&init_data, 0, sizeof(struct qdio_initialize));
  4028. init_data.cdev = CARD_DDEV(card);
  4029. init_data.q_format = qeth_get_qdio_q_format(card);
  4030. init_data.qib_param_field_format = 0;
  4031. init_data.qib_param_field = qib_param_field;
  4032. init_data.no_input_qs = card->qdio.no_in_queues;
  4033. init_data.no_output_qs = card->qdio.no_out_queues;
  4034. init_data.input_handler = card->discipline.input_handler;
  4035. init_data.output_handler = card->discipline.output_handler;
  4036. init_data.queue_start_poll = queue_start_poll;
  4037. init_data.int_parm = (unsigned long) card;
  4038. init_data.input_sbal_addr_array = (void **) in_sbal_ptrs;
  4039. init_data.output_sbal_addr_array = (void **) out_sbal_ptrs;
  4040. init_data.output_sbal_state_array = card->qdio.out_bufstates;
  4041. init_data.scan_threshold =
  4042. (card->info.type == QETH_CARD_TYPE_IQD) ? 8 : 32;
  4043. if (atomic_cmpxchg(&card->qdio.state, QETH_QDIO_ALLOCATED,
  4044. QETH_QDIO_ESTABLISHED) == QETH_QDIO_ALLOCATED) {
  4045. rc = qdio_allocate(&init_data);
  4046. if (rc) {
  4047. atomic_set(&card->qdio.state, QETH_QDIO_ALLOCATED);
  4048. goto out;
  4049. }
  4050. rc = qdio_establish(&init_data);
  4051. if (rc) {
  4052. atomic_set(&card->qdio.state, QETH_QDIO_ALLOCATED);
  4053. qdio_free(CARD_DDEV(card));
  4054. }
  4055. }
  4056. switch (card->options.cq) {
  4057. case QETH_CQ_ENABLED:
  4058. dev_info(&card->gdev->dev, "Completion Queue support enabled");
  4059. break;
  4060. case QETH_CQ_DISABLED:
  4061. dev_info(&card->gdev->dev, "Completion Queue support disabled");
  4062. break;
  4063. default:
  4064. break;
  4065. }
  4066. out:
  4067. kfree(out_sbal_ptrs);
  4068. out_free_queue_start_poll:
  4069. kfree(queue_start_poll);
  4070. out_free_in_sbals:
  4071. kfree(in_sbal_ptrs);
  4072. out_free_qib_param:
  4073. kfree(qib_param_field);
  4074. out_free_nothing:
  4075. return rc;
  4076. }
  4077. static void qeth_core_free_card(struct qeth_card *card)
  4078. {
  4079. QETH_DBF_TEXT(SETUP, 2, "freecrd");
  4080. QETH_DBF_HEX(SETUP, 2, &card, sizeof(void *));
  4081. qeth_clean_channel(&card->read);
  4082. qeth_clean_channel(&card->write);
  4083. if (card->dev)
  4084. free_netdev(card->dev);
  4085. kfree(card->ip_tbd_list);
  4086. qeth_free_qdio_buffers(card);
  4087. unregister_service_level(&card->qeth_service_level);
  4088. kfree(card);
  4089. }
  4090. static struct ccw_device_id qeth_ids[] = {
  4091. {CCW_DEVICE_DEVTYPE(0x1731, 0x01, 0x1732, 0x01),
  4092. .driver_info = QETH_CARD_TYPE_OSD},
  4093. {CCW_DEVICE_DEVTYPE(0x1731, 0x05, 0x1732, 0x05),
  4094. .driver_info = QETH_CARD_TYPE_IQD},
  4095. {CCW_DEVICE_DEVTYPE(0x1731, 0x06, 0x1732, 0x06),
  4096. .driver_info = QETH_CARD_TYPE_OSN},
  4097. {CCW_DEVICE_DEVTYPE(0x1731, 0x02, 0x1732, 0x03),
  4098. .driver_info = QETH_CARD_TYPE_OSM},
  4099. {CCW_DEVICE_DEVTYPE(0x1731, 0x02, 0x1732, 0x02),
  4100. .driver_info = QETH_CARD_TYPE_OSX},
  4101. {},
  4102. };
  4103. MODULE_DEVICE_TABLE(ccw, qeth_ids);
  4104. static struct ccw_driver qeth_ccw_driver = {
  4105. .driver = {
  4106. .owner = THIS_MODULE,
  4107. .name = "qeth",
  4108. },
  4109. .ids = qeth_ids,
  4110. .probe = ccwgroup_probe_ccwdev,
  4111. .remove = ccwgroup_remove_ccwdev,
  4112. };
  4113. static int qeth_core_driver_group(const char *buf, struct device *root_dev,
  4114. unsigned long driver_id)
  4115. {
  4116. return ccwgroup_create_from_string(root_dev, driver_id,
  4117. &qeth_ccw_driver, 3, buf);
  4118. }
  4119. int qeth_core_hardsetup_card(struct qeth_card *card)
  4120. {
  4121. int retries = 0;
  4122. int rc;
  4123. QETH_DBF_TEXT(SETUP, 2, "hrdsetup");
  4124. atomic_set(&card->force_alloc_skb, 0);
  4125. qeth_get_channel_path_desc(card);
  4126. retry:
  4127. if (retries)
  4128. QETH_DBF_MESSAGE(2, "%s Retrying to do IDX activates.\n",
  4129. dev_name(&card->gdev->dev));
  4130. ccw_device_set_offline(CARD_DDEV(card));
  4131. ccw_device_set_offline(CARD_WDEV(card));
  4132. ccw_device_set_offline(CARD_RDEV(card));
  4133. rc = ccw_device_set_online(CARD_RDEV(card));
  4134. if (rc)
  4135. goto retriable;
  4136. rc = ccw_device_set_online(CARD_WDEV(card));
  4137. if (rc)
  4138. goto retriable;
  4139. rc = ccw_device_set_online(CARD_DDEV(card));
  4140. if (rc)
  4141. goto retriable;
  4142. rc = qeth_qdio_clear_card(card, card->info.type != QETH_CARD_TYPE_IQD);
  4143. retriable:
  4144. if (rc == -ERESTARTSYS) {
  4145. QETH_DBF_TEXT(SETUP, 2, "break1");
  4146. return rc;
  4147. } else if (rc) {
  4148. QETH_DBF_TEXT_(SETUP, 2, "1err%d", rc);
  4149. if (++retries > 3)
  4150. goto out;
  4151. else
  4152. goto retry;
  4153. }
  4154. qeth_determine_capabilities(card);
  4155. qeth_init_tokens(card);
  4156. qeth_init_func_level(card);
  4157. rc = qeth_idx_activate_channel(&card->read, qeth_idx_read_cb);
  4158. if (rc == -ERESTARTSYS) {
  4159. QETH_DBF_TEXT(SETUP, 2, "break2");
  4160. return rc;
  4161. } else if (rc) {
  4162. QETH_DBF_TEXT_(SETUP, 2, "3err%d", rc);
  4163. if (--retries < 0)
  4164. goto out;
  4165. else
  4166. goto retry;
  4167. }
  4168. rc = qeth_idx_activate_channel(&card->write, qeth_idx_write_cb);
  4169. if (rc == -ERESTARTSYS) {
  4170. QETH_DBF_TEXT(SETUP, 2, "break3");
  4171. return rc;
  4172. } else if (rc) {
  4173. QETH_DBF_TEXT_(SETUP, 2, "4err%d", rc);
  4174. if (--retries < 0)
  4175. goto out;
  4176. else
  4177. goto retry;
  4178. }
  4179. card->read_or_write_problem = 0;
  4180. rc = qeth_mpc_initialize(card);
  4181. if (rc) {
  4182. QETH_DBF_TEXT_(SETUP, 2, "5err%d", rc);
  4183. goto out;
  4184. }
  4185. card->options.ipa4.supported_funcs = 0;
  4186. card->options.adp.supported_funcs = 0;
  4187. card->info.diagass_support = 0;
  4188. qeth_query_ipassists(card, QETH_PROT_IPV4);
  4189. if (qeth_is_supported(card, IPA_SETADAPTERPARMS))
  4190. qeth_query_setadapterparms(card);
  4191. if (qeth_adp_supported(card, IPA_SETADP_SET_DIAG_ASSIST))
  4192. qeth_query_setdiagass(card);
  4193. return 0;
  4194. out:
  4195. dev_warn(&card->gdev->dev, "The qeth device driver failed to recover "
  4196. "an error on the device\n");
  4197. QETH_DBF_MESSAGE(2, "%s Initialization in hardsetup failed! rc=%d\n",
  4198. dev_name(&card->gdev->dev), rc);
  4199. return rc;
  4200. }
  4201. EXPORT_SYMBOL_GPL(qeth_core_hardsetup_card);
  4202. static inline int qeth_create_skb_frag(struct qeth_qdio_buffer *qethbuffer,
  4203. struct qdio_buffer_element *element,
  4204. struct sk_buff **pskb, int offset, int *pfrag, int data_len)
  4205. {
  4206. struct page *page = virt_to_page(element->addr);
  4207. if (*pskb == NULL) {
  4208. if (qethbuffer->rx_skb) {
  4209. /* only if qeth_card.options.cq == QETH_CQ_ENABLED */
  4210. *pskb = qethbuffer->rx_skb;
  4211. qethbuffer->rx_skb = NULL;
  4212. } else {
  4213. *pskb = dev_alloc_skb(QETH_RX_PULL_LEN + ETH_HLEN);
  4214. if (!(*pskb))
  4215. return -ENOMEM;
  4216. }
  4217. skb_reserve(*pskb, ETH_HLEN);
  4218. if (data_len <= QETH_RX_PULL_LEN) {
  4219. memcpy(skb_put(*pskb, data_len), element->addr + offset,
  4220. data_len);
  4221. } else {
  4222. get_page(page);
  4223. memcpy(skb_put(*pskb, QETH_RX_PULL_LEN),
  4224. element->addr + offset, QETH_RX_PULL_LEN);
  4225. skb_fill_page_desc(*pskb, *pfrag, page,
  4226. offset + QETH_RX_PULL_LEN,
  4227. data_len - QETH_RX_PULL_LEN);
  4228. (*pskb)->data_len += data_len - QETH_RX_PULL_LEN;
  4229. (*pskb)->len += data_len - QETH_RX_PULL_LEN;
  4230. (*pskb)->truesize += data_len - QETH_RX_PULL_LEN;
  4231. (*pfrag)++;
  4232. }
  4233. } else {
  4234. get_page(page);
  4235. skb_fill_page_desc(*pskb, *pfrag, page, offset, data_len);
  4236. (*pskb)->data_len += data_len;
  4237. (*pskb)->len += data_len;
  4238. (*pskb)->truesize += data_len;
  4239. (*pfrag)++;
  4240. }
  4241. return 0;
  4242. }
  4243. struct sk_buff *qeth_core_get_next_skb(struct qeth_card *card,
  4244. struct qeth_qdio_buffer *qethbuffer,
  4245. struct qdio_buffer_element **__element, int *__offset,
  4246. struct qeth_hdr **hdr)
  4247. {
  4248. struct qdio_buffer_element *element = *__element;
  4249. struct qdio_buffer *buffer = qethbuffer->buffer;
  4250. int offset = *__offset;
  4251. struct sk_buff *skb = NULL;
  4252. int skb_len = 0;
  4253. void *data_ptr;
  4254. int data_len;
  4255. int headroom = 0;
  4256. int use_rx_sg = 0;
  4257. int frag = 0;
  4258. /* qeth_hdr must not cross element boundaries */
  4259. if (element->length < offset + sizeof(struct qeth_hdr)) {
  4260. if (qeth_is_last_sbale(element))
  4261. return NULL;
  4262. element++;
  4263. offset = 0;
  4264. if (element->length < sizeof(struct qeth_hdr))
  4265. return NULL;
  4266. }
  4267. *hdr = element->addr + offset;
  4268. offset += sizeof(struct qeth_hdr);
  4269. switch ((*hdr)->hdr.l2.id) {
  4270. case QETH_HEADER_TYPE_LAYER2:
  4271. skb_len = (*hdr)->hdr.l2.pkt_length;
  4272. break;
  4273. case QETH_HEADER_TYPE_LAYER3:
  4274. skb_len = (*hdr)->hdr.l3.length;
  4275. if ((card->info.link_type == QETH_LINK_TYPE_LANE_TR) ||
  4276. (card->info.link_type == QETH_LINK_TYPE_HSTR))
  4277. headroom = TR_HLEN;
  4278. else
  4279. headroom = ETH_HLEN;
  4280. break;
  4281. case QETH_HEADER_TYPE_OSN:
  4282. skb_len = (*hdr)->hdr.osn.pdu_length;
  4283. headroom = sizeof(struct qeth_hdr);
  4284. break;
  4285. default:
  4286. break;
  4287. }
  4288. if (!skb_len)
  4289. return NULL;
  4290. if (((skb_len >= card->options.rx_sg_cb) &&
  4291. (!(card->info.type == QETH_CARD_TYPE_OSN)) &&
  4292. (!atomic_read(&card->force_alloc_skb))) ||
  4293. (card->options.cq == QETH_CQ_ENABLED)) {
  4294. use_rx_sg = 1;
  4295. } else {
  4296. skb = dev_alloc_skb(skb_len + headroom);
  4297. if (!skb)
  4298. goto no_mem;
  4299. if (headroom)
  4300. skb_reserve(skb, headroom);
  4301. }
  4302. data_ptr = element->addr + offset;
  4303. while (skb_len) {
  4304. data_len = min(skb_len, (int)(element->length - offset));
  4305. if (data_len) {
  4306. if (use_rx_sg) {
  4307. if (qeth_create_skb_frag(qethbuffer, element,
  4308. &skb, offset, &frag, data_len))
  4309. goto no_mem;
  4310. } else {
  4311. memcpy(skb_put(skb, data_len), data_ptr,
  4312. data_len);
  4313. }
  4314. }
  4315. skb_len -= data_len;
  4316. if (skb_len) {
  4317. if (qeth_is_last_sbale(element)) {
  4318. QETH_CARD_TEXT(card, 4, "unexeob");
  4319. QETH_CARD_HEX(card, 2, buffer, sizeof(void *));
  4320. dev_kfree_skb_any(skb);
  4321. card->stats.rx_errors++;
  4322. return NULL;
  4323. }
  4324. element++;
  4325. offset = 0;
  4326. data_ptr = element->addr;
  4327. } else {
  4328. offset += data_len;
  4329. }
  4330. }
  4331. *__element = element;
  4332. *__offset = offset;
  4333. if (use_rx_sg && card->options.performance_stats) {
  4334. card->perf_stats.sg_skbs_rx++;
  4335. card->perf_stats.sg_frags_rx += skb_shinfo(skb)->nr_frags;
  4336. }
  4337. return skb;
  4338. no_mem:
  4339. if (net_ratelimit()) {
  4340. QETH_CARD_TEXT(card, 2, "noskbmem");
  4341. }
  4342. card->stats.rx_dropped++;
  4343. return NULL;
  4344. }
  4345. EXPORT_SYMBOL_GPL(qeth_core_get_next_skb);
  4346. static void qeth_unregister_dbf_views(void)
  4347. {
  4348. int x;
  4349. for (x = 0; x < QETH_DBF_INFOS; x++) {
  4350. debug_unregister(qeth_dbf[x].id);
  4351. qeth_dbf[x].id = NULL;
  4352. }
  4353. }
  4354. void qeth_dbf_longtext(debug_info_t *id, int level, char *fmt, ...)
  4355. {
  4356. char dbf_txt_buf[32];
  4357. va_list args;
  4358. if (level > id->level)
  4359. return;
  4360. va_start(args, fmt);
  4361. vsnprintf(dbf_txt_buf, sizeof(dbf_txt_buf), fmt, args);
  4362. va_end(args);
  4363. debug_text_event(id, level, dbf_txt_buf);
  4364. }
  4365. EXPORT_SYMBOL_GPL(qeth_dbf_longtext);
  4366. static int qeth_register_dbf_views(void)
  4367. {
  4368. int ret;
  4369. int x;
  4370. for (x = 0; x < QETH_DBF_INFOS; x++) {
  4371. /* register the areas */
  4372. qeth_dbf[x].id = debug_register(qeth_dbf[x].name,
  4373. qeth_dbf[x].pages,
  4374. qeth_dbf[x].areas,
  4375. qeth_dbf[x].len);
  4376. if (qeth_dbf[x].id == NULL) {
  4377. qeth_unregister_dbf_views();
  4378. return -ENOMEM;
  4379. }
  4380. /* register a view */
  4381. ret = debug_register_view(qeth_dbf[x].id, qeth_dbf[x].view);
  4382. if (ret) {
  4383. qeth_unregister_dbf_views();
  4384. return ret;
  4385. }
  4386. /* set a passing level */
  4387. debug_set_level(qeth_dbf[x].id, qeth_dbf[x].level);
  4388. }
  4389. return 0;
  4390. }
  4391. int qeth_core_load_discipline(struct qeth_card *card,
  4392. enum qeth_discipline_id discipline)
  4393. {
  4394. int rc = 0;
  4395. switch (discipline) {
  4396. case QETH_DISCIPLINE_LAYER3:
  4397. card->discipline.ccwgdriver = try_then_request_module(
  4398. symbol_get(qeth_l3_ccwgroup_driver),
  4399. "qeth_l3");
  4400. break;
  4401. case QETH_DISCIPLINE_LAYER2:
  4402. card->discipline.ccwgdriver = try_then_request_module(
  4403. symbol_get(qeth_l2_ccwgroup_driver),
  4404. "qeth_l2");
  4405. break;
  4406. }
  4407. if (!card->discipline.ccwgdriver) {
  4408. dev_err(&card->gdev->dev, "There is no kernel module to "
  4409. "support discipline %d\n", discipline);
  4410. rc = -EINVAL;
  4411. }
  4412. return rc;
  4413. }
  4414. void qeth_core_free_discipline(struct qeth_card *card)
  4415. {
  4416. if (card->options.layer2)
  4417. symbol_put(qeth_l2_ccwgroup_driver);
  4418. else
  4419. symbol_put(qeth_l3_ccwgroup_driver);
  4420. card->discipline.ccwgdriver = NULL;
  4421. }
  4422. static int qeth_core_probe_device(struct ccwgroup_device *gdev)
  4423. {
  4424. struct qeth_card *card;
  4425. struct device *dev;
  4426. int rc;
  4427. unsigned long flags;
  4428. char dbf_name[20];
  4429. QETH_DBF_TEXT(SETUP, 2, "probedev");
  4430. dev = &gdev->dev;
  4431. if (!get_device(dev))
  4432. return -ENODEV;
  4433. QETH_DBF_TEXT_(SETUP, 2, "%s", dev_name(&gdev->dev));
  4434. card = qeth_alloc_card();
  4435. if (!card) {
  4436. QETH_DBF_TEXT_(SETUP, 2, "1err%d", -ENOMEM);
  4437. rc = -ENOMEM;
  4438. goto err_dev;
  4439. }
  4440. snprintf(dbf_name, sizeof(dbf_name), "qeth_card_%s",
  4441. dev_name(&gdev->dev));
  4442. card->debug = debug_register(dbf_name, 2, 1, 8);
  4443. if (!card->debug) {
  4444. QETH_DBF_TEXT_(SETUP, 2, "%s", "qcdbf");
  4445. rc = -ENOMEM;
  4446. goto err_card;
  4447. }
  4448. debug_register_view(card->debug, &debug_hex_ascii_view);
  4449. card->read.ccwdev = gdev->cdev[0];
  4450. card->write.ccwdev = gdev->cdev[1];
  4451. card->data.ccwdev = gdev->cdev[2];
  4452. dev_set_drvdata(&gdev->dev, card);
  4453. card->gdev = gdev;
  4454. gdev->cdev[0]->handler = qeth_irq;
  4455. gdev->cdev[1]->handler = qeth_irq;
  4456. gdev->cdev[2]->handler = qeth_irq;
  4457. rc = qeth_determine_card_type(card);
  4458. if (rc) {
  4459. QETH_DBF_TEXT_(SETUP, 2, "3err%d", rc);
  4460. goto err_dbf;
  4461. }
  4462. rc = qeth_setup_card(card);
  4463. if (rc) {
  4464. QETH_DBF_TEXT_(SETUP, 2, "2err%d", rc);
  4465. goto err_dbf;
  4466. }
  4467. if (card->info.type == QETH_CARD_TYPE_OSN)
  4468. rc = qeth_core_create_osn_attributes(dev);
  4469. else
  4470. rc = qeth_core_create_device_attributes(dev);
  4471. if (rc)
  4472. goto err_dbf;
  4473. switch (card->info.type) {
  4474. case QETH_CARD_TYPE_OSN:
  4475. case QETH_CARD_TYPE_OSM:
  4476. rc = qeth_core_load_discipline(card, QETH_DISCIPLINE_LAYER2);
  4477. if (rc)
  4478. goto err_attr;
  4479. rc = card->discipline.ccwgdriver->probe(card->gdev);
  4480. if (rc)
  4481. goto err_disc;
  4482. case QETH_CARD_TYPE_OSD:
  4483. case QETH_CARD_TYPE_OSX:
  4484. default:
  4485. break;
  4486. }
  4487. write_lock_irqsave(&qeth_core_card_list.rwlock, flags);
  4488. list_add_tail(&card->list, &qeth_core_card_list.list);
  4489. write_unlock_irqrestore(&qeth_core_card_list.rwlock, flags);
  4490. qeth_determine_capabilities(card);
  4491. return 0;
  4492. err_disc:
  4493. qeth_core_free_discipline(card);
  4494. err_attr:
  4495. if (card->info.type == QETH_CARD_TYPE_OSN)
  4496. qeth_core_remove_osn_attributes(dev);
  4497. else
  4498. qeth_core_remove_device_attributes(dev);
  4499. err_dbf:
  4500. debug_unregister(card->debug);
  4501. err_card:
  4502. qeth_core_free_card(card);
  4503. err_dev:
  4504. put_device(dev);
  4505. return rc;
  4506. }
  4507. static void qeth_core_remove_device(struct ccwgroup_device *gdev)
  4508. {
  4509. unsigned long flags;
  4510. struct qeth_card *card = dev_get_drvdata(&gdev->dev);
  4511. QETH_DBF_TEXT(SETUP, 2, "removedv");
  4512. if (card->info.type == QETH_CARD_TYPE_OSN) {
  4513. qeth_core_remove_osn_attributes(&gdev->dev);
  4514. } else {
  4515. qeth_core_remove_device_attributes(&gdev->dev);
  4516. }
  4517. if (card->discipline.ccwgdriver) {
  4518. card->discipline.ccwgdriver->remove(gdev);
  4519. qeth_core_free_discipline(card);
  4520. }
  4521. debug_unregister(card->debug);
  4522. write_lock_irqsave(&qeth_core_card_list.rwlock, flags);
  4523. list_del(&card->list);
  4524. write_unlock_irqrestore(&qeth_core_card_list.rwlock, flags);
  4525. qeth_core_free_card(card);
  4526. dev_set_drvdata(&gdev->dev, NULL);
  4527. put_device(&gdev->dev);
  4528. return;
  4529. }
  4530. static int qeth_core_set_online(struct ccwgroup_device *gdev)
  4531. {
  4532. struct qeth_card *card = dev_get_drvdata(&gdev->dev);
  4533. int rc = 0;
  4534. int def_discipline;
  4535. if (!card->discipline.ccwgdriver) {
  4536. if (card->info.type == QETH_CARD_TYPE_IQD)
  4537. def_discipline = QETH_DISCIPLINE_LAYER3;
  4538. else
  4539. def_discipline = QETH_DISCIPLINE_LAYER2;
  4540. rc = qeth_core_load_discipline(card, def_discipline);
  4541. if (rc)
  4542. goto err;
  4543. rc = card->discipline.ccwgdriver->probe(card->gdev);
  4544. if (rc)
  4545. goto err;
  4546. }
  4547. rc = card->discipline.ccwgdriver->set_online(gdev);
  4548. err:
  4549. return rc;
  4550. }
  4551. static int qeth_core_set_offline(struct ccwgroup_device *gdev)
  4552. {
  4553. struct qeth_card *card = dev_get_drvdata(&gdev->dev);
  4554. return card->discipline.ccwgdriver->set_offline(gdev);
  4555. }
  4556. static void qeth_core_shutdown(struct ccwgroup_device *gdev)
  4557. {
  4558. struct qeth_card *card = dev_get_drvdata(&gdev->dev);
  4559. if (card->discipline.ccwgdriver &&
  4560. card->discipline.ccwgdriver->shutdown)
  4561. card->discipline.ccwgdriver->shutdown(gdev);
  4562. }
  4563. static int qeth_core_prepare(struct ccwgroup_device *gdev)
  4564. {
  4565. struct qeth_card *card = dev_get_drvdata(&gdev->dev);
  4566. if (card->discipline.ccwgdriver &&
  4567. card->discipline.ccwgdriver->prepare)
  4568. return card->discipline.ccwgdriver->prepare(gdev);
  4569. return 0;
  4570. }
  4571. static void qeth_core_complete(struct ccwgroup_device *gdev)
  4572. {
  4573. struct qeth_card *card = dev_get_drvdata(&gdev->dev);
  4574. if (card->discipline.ccwgdriver &&
  4575. card->discipline.ccwgdriver->complete)
  4576. card->discipline.ccwgdriver->complete(gdev);
  4577. }
  4578. static int qeth_core_freeze(struct ccwgroup_device *gdev)
  4579. {
  4580. struct qeth_card *card = dev_get_drvdata(&gdev->dev);
  4581. if (card->discipline.ccwgdriver &&
  4582. card->discipline.ccwgdriver->freeze)
  4583. return card->discipline.ccwgdriver->freeze(gdev);
  4584. return 0;
  4585. }
  4586. static int qeth_core_thaw(struct ccwgroup_device *gdev)
  4587. {
  4588. struct qeth_card *card = dev_get_drvdata(&gdev->dev);
  4589. if (card->discipline.ccwgdriver &&
  4590. card->discipline.ccwgdriver->thaw)
  4591. return card->discipline.ccwgdriver->thaw(gdev);
  4592. return 0;
  4593. }
  4594. static int qeth_core_restore(struct ccwgroup_device *gdev)
  4595. {
  4596. struct qeth_card *card = dev_get_drvdata(&gdev->dev);
  4597. if (card->discipline.ccwgdriver &&
  4598. card->discipline.ccwgdriver->restore)
  4599. return card->discipline.ccwgdriver->restore(gdev);
  4600. return 0;
  4601. }
  4602. static struct ccwgroup_driver qeth_core_ccwgroup_driver = {
  4603. .driver = {
  4604. .owner = THIS_MODULE,
  4605. .name = "qeth",
  4606. },
  4607. .driver_id = 0xD8C5E3C8,
  4608. .probe = qeth_core_probe_device,
  4609. .remove = qeth_core_remove_device,
  4610. .set_online = qeth_core_set_online,
  4611. .set_offline = qeth_core_set_offline,
  4612. .shutdown = qeth_core_shutdown,
  4613. .prepare = qeth_core_prepare,
  4614. .complete = qeth_core_complete,
  4615. .freeze = qeth_core_freeze,
  4616. .thaw = qeth_core_thaw,
  4617. .restore = qeth_core_restore,
  4618. };
  4619. static ssize_t
  4620. qeth_core_driver_group_store(struct device_driver *ddrv, const char *buf,
  4621. size_t count)
  4622. {
  4623. int err;
  4624. err = qeth_core_driver_group(buf, qeth_core_root_dev,
  4625. qeth_core_ccwgroup_driver.driver_id);
  4626. if (err)
  4627. return err;
  4628. else
  4629. return count;
  4630. }
  4631. static DRIVER_ATTR(group, 0200, NULL, qeth_core_driver_group_store);
  4632. static struct {
  4633. const char str[ETH_GSTRING_LEN];
  4634. } qeth_ethtool_stats_keys[] = {
  4635. /* 0 */{"rx skbs"},
  4636. {"rx buffers"},
  4637. {"tx skbs"},
  4638. {"tx buffers"},
  4639. {"tx skbs no packing"},
  4640. {"tx buffers no packing"},
  4641. {"tx skbs packing"},
  4642. {"tx buffers packing"},
  4643. {"tx sg skbs"},
  4644. {"tx sg frags"},
  4645. /* 10 */{"rx sg skbs"},
  4646. {"rx sg frags"},
  4647. {"rx sg page allocs"},
  4648. {"tx large kbytes"},
  4649. {"tx large count"},
  4650. {"tx pk state ch n->p"},
  4651. {"tx pk state ch p->n"},
  4652. {"tx pk watermark low"},
  4653. {"tx pk watermark high"},
  4654. {"queue 0 buffer usage"},
  4655. /* 20 */{"queue 1 buffer usage"},
  4656. {"queue 2 buffer usage"},
  4657. {"queue 3 buffer usage"},
  4658. {"rx poll time"},
  4659. {"rx poll count"},
  4660. {"rx do_QDIO time"},
  4661. {"rx do_QDIO count"},
  4662. {"tx handler time"},
  4663. {"tx handler count"},
  4664. {"tx time"},
  4665. /* 30 */{"tx count"},
  4666. {"tx do_QDIO time"},
  4667. {"tx do_QDIO count"},
  4668. {"tx csum"},
  4669. {"tx lin"},
  4670. {"cq handler count"},
  4671. {"cq handler time"}
  4672. };
  4673. int qeth_core_get_sset_count(struct net_device *dev, int stringset)
  4674. {
  4675. switch (stringset) {
  4676. case ETH_SS_STATS:
  4677. return (sizeof(qeth_ethtool_stats_keys) / ETH_GSTRING_LEN);
  4678. default:
  4679. return -EINVAL;
  4680. }
  4681. }
  4682. EXPORT_SYMBOL_GPL(qeth_core_get_sset_count);
  4683. void qeth_core_get_ethtool_stats(struct net_device *dev,
  4684. struct ethtool_stats *stats, u64 *data)
  4685. {
  4686. struct qeth_card *card = dev->ml_priv;
  4687. data[0] = card->stats.rx_packets -
  4688. card->perf_stats.initial_rx_packets;
  4689. data[1] = card->perf_stats.bufs_rec;
  4690. data[2] = card->stats.tx_packets -
  4691. card->perf_stats.initial_tx_packets;
  4692. data[3] = card->perf_stats.bufs_sent;
  4693. data[4] = card->stats.tx_packets - card->perf_stats.initial_tx_packets
  4694. - card->perf_stats.skbs_sent_pack;
  4695. data[5] = card->perf_stats.bufs_sent - card->perf_stats.bufs_sent_pack;
  4696. data[6] = card->perf_stats.skbs_sent_pack;
  4697. data[7] = card->perf_stats.bufs_sent_pack;
  4698. data[8] = card->perf_stats.sg_skbs_sent;
  4699. data[9] = card->perf_stats.sg_frags_sent;
  4700. data[10] = card->perf_stats.sg_skbs_rx;
  4701. data[11] = card->perf_stats.sg_frags_rx;
  4702. data[12] = card->perf_stats.sg_alloc_page_rx;
  4703. data[13] = (card->perf_stats.large_send_bytes >> 10);
  4704. data[14] = card->perf_stats.large_send_cnt;
  4705. data[15] = card->perf_stats.sc_dp_p;
  4706. data[16] = card->perf_stats.sc_p_dp;
  4707. data[17] = QETH_LOW_WATERMARK_PACK;
  4708. data[18] = QETH_HIGH_WATERMARK_PACK;
  4709. data[19] = atomic_read(&card->qdio.out_qs[0]->used_buffers);
  4710. data[20] = (card->qdio.no_out_queues > 1) ?
  4711. atomic_read(&card->qdio.out_qs[1]->used_buffers) : 0;
  4712. data[21] = (card->qdio.no_out_queues > 2) ?
  4713. atomic_read(&card->qdio.out_qs[2]->used_buffers) : 0;
  4714. data[22] = (card->qdio.no_out_queues > 3) ?
  4715. atomic_read(&card->qdio.out_qs[3]->used_buffers) : 0;
  4716. data[23] = card->perf_stats.inbound_time;
  4717. data[24] = card->perf_stats.inbound_cnt;
  4718. data[25] = card->perf_stats.inbound_do_qdio_time;
  4719. data[26] = card->perf_stats.inbound_do_qdio_cnt;
  4720. data[27] = card->perf_stats.outbound_handler_time;
  4721. data[28] = card->perf_stats.outbound_handler_cnt;
  4722. data[29] = card->perf_stats.outbound_time;
  4723. data[30] = card->perf_stats.outbound_cnt;
  4724. data[31] = card->perf_stats.outbound_do_qdio_time;
  4725. data[32] = card->perf_stats.outbound_do_qdio_cnt;
  4726. data[33] = card->perf_stats.tx_csum;
  4727. data[34] = card->perf_stats.tx_lin;
  4728. data[35] = card->perf_stats.cq_cnt;
  4729. data[36] = card->perf_stats.cq_time;
  4730. }
  4731. EXPORT_SYMBOL_GPL(qeth_core_get_ethtool_stats);
  4732. void qeth_core_get_strings(struct net_device *dev, u32 stringset, u8 *data)
  4733. {
  4734. switch (stringset) {
  4735. case ETH_SS_STATS:
  4736. memcpy(data, &qeth_ethtool_stats_keys,
  4737. sizeof(qeth_ethtool_stats_keys));
  4738. break;
  4739. default:
  4740. WARN_ON(1);
  4741. break;
  4742. }
  4743. }
  4744. EXPORT_SYMBOL_GPL(qeth_core_get_strings);
  4745. void qeth_core_get_drvinfo(struct net_device *dev,
  4746. struct ethtool_drvinfo *info)
  4747. {
  4748. struct qeth_card *card = dev->ml_priv;
  4749. if (card->options.layer2)
  4750. strcpy(info->driver, "qeth_l2");
  4751. else
  4752. strcpy(info->driver, "qeth_l3");
  4753. strcpy(info->version, "1.0");
  4754. strcpy(info->fw_version, card->info.mcl_level);
  4755. sprintf(info->bus_info, "%s/%s/%s",
  4756. CARD_RDEV_ID(card),
  4757. CARD_WDEV_ID(card),
  4758. CARD_DDEV_ID(card));
  4759. }
  4760. EXPORT_SYMBOL_GPL(qeth_core_get_drvinfo);
  4761. int qeth_core_ethtool_get_settings(struct net_device *netdev,
  4762. struct ethtool_cmd *ecmd)
  4763. {
  4764. struct qeth_card *card = netdev->ml_priv;
  4765. enum qeth_link_types link_type;
  4766. if ((card->info.type == QETH_CARD_TYPE_IQD) || (card->info.guestlan))
  4767. link_type = QETH_LINK_TYPE_10GBIT_ETH;
  4768. else
  4769. link_type = card->info.link_type;
  4770. ecmd->transceiver = XCVR_INTERNAL;
  4771. ecmd->supported = SUPPORTED_Autoneg;
  4772. ecmd->advertising = ADVERTISED_Autoneg;
  4773. ecmd->duplex = DUPLEX_FULL;
  4774. ecmd->autoneg = AUTONEG_ENABLE;
  4775. switch (link_type) {
  4776. case QETH_LINK_TYPE_FAST_ETH:
  4777. case QETH_LINK_TYPE_LANE_ETH100:
  4778. ecmd->supported |= SUPPORTED_10baseT_Half |
  4779. SUPPORTED_10baseT_Full |
  4780. SUPPORTED_100baseT_Half |
  4781. SUPPORTED_100baseT_Full |
  4782. SUPPORTED_TP;
  4783. ecmd->advertising |= ADVERTISED_10baseT_Half |
  4784. ADVERTISED_10baseT_Full |
  4785. ADVERTISED_100baseT_Half |
  4786. ADVERTISED_100baseT_Full |
  4787. ADVERTISED_TP;
  4788. ecmd->speed = SPEED_100;
  4789. ecmd->port = PORT_TP;
  4790. break;
  4791. case QETH_LINK_TYPE_GBIT_ETH:
  4792. case QETH_LINK_TYPE_LANE_ETH1000:
  4793. ecmd->supported |= SUPPORTED_10baseT_Half |
  4794. SUPPORTED_10baseT_Full |
  4795. SUPPORTED_100baseT_Half |
  4796. SUPPORTED_100baseT_Full |
  4797. SUPPORTED_1000baseT_Half |
  4798. SUPPORTED_1000baseT_Full |
  4799. SUPPORTED_FIBRE;
  4800. ecmd->advertising |= ADVERTISED_10baseT_Half |
  4801. ADVERTISED_10baseT_Full |
  4802. ADVERTISED_100baseT_Half |
  4803. ADVERTISED_100baseT_Full |
  4804. ADVERTISED_1000baseT_Half |
  4805. ADVERTISED_1000baseT_Full |
  4806. ADVERTISED_FIBRE;
  4807. ecmd->speed = SPEED_1000;
  4808. ecmd->port = PORT_FIBRE;
  4809. break;
  4810. case QETH_LINK_TYPE_10GBIT_ETH:
  4811. ecmd->supported |= SUPPORTED_10baseT_Half |
  4812. SUPPORTED_10baseT_Full |
  4813. SUPPORTED_100baseT_Half |
  4814. SUPPORTED_100baseT_Full |
  4815. SUPPORTED_1000baseT_Half |
  4816. SUPPORTED_1000baseT_Full |
  4817. SUPPORTED_10000baseT_Full |
  4818. SUPPORTED_FIBRE;
  4819. ecmd->advertising |= ADVERTISED_10baseT_Half |
  4820. ADVERTISED_10baseT_Full |
  4821. ADVERTISED_100baseT_Half |
  4822. ADVERTISED_100baseT_Full |
  4823. ADVERTISED_1000baseT_Half |
  4824. ADVERTISED_1000baseT_Full |
  4825. ADVERTISED_10000baseT_Full |
  4826. ADVERTISED_FIBRE;
  4827. ecmd->speed = SPEED_10000;
  4828. ecmd->port = PORT_FIBRE;
  4829. break;
  4830. default:
  4831. ecmd->supported |= SUPPORTED_10baseT_Half |
  4832. SUPPORTED_10baseT_Full |
  4833. SUPPORTED_TP;
  4834. ecmd->advertising |= ADVERTISED_10baseT_Half |
  4835. ADVERTISED_10baseT_Full |
  4836. ADVERTISED_TP;
  4837. ecmd->speed = SPEED_10;
  4838. ecmd->port = PORT_TP;
  4839. }
  4840. return 0;
  4841. }
  4842. EXPORT_SYMBOL_GPL(qeth_core_ethtool_get_settings);
  4843. static int __init qeth_core_init(void)
  4844. {
  4845. int rc;
  4846. pr_info("loading core functions\n");
  4847. INIT_LIST_HEAD(&qeth_core_card_list.list);
  4848. rwlock_init(&qeth_core_card_list.rwlock);
  4849. rc = qeth_register_dbf_views();
  4850. if (rc)
  4851. goto out_err;
  4852. rc = ccw_driver_register(&qeth_ccw_driver);
  4853. if (rc)
  4854. goto ccw_err;
  4855. rc = ccwgroup_driver_register(&qeth_core_ccwgroup_driver);
  4856. if (rc)
  4857. goto ccwgroup_err;
  4858. rc = driver_create_file(&qeth_core_ccwgroup_driver.driver,
  4859. &driver_attr_group);
  4860. if (rc)
  4861. goto driver_err;
  4862. qeth_core_root_dev = root_device_register("qeth");
  4863. rc = IS_ERR(qeth_core_root_dev) ? PTR_ERR(qeth_core_root_dev) : 0;
  4864. if (rc)
  4865. goto register_err;
  4866. qeth_core_header_cache = kmem_cache_create("qeth_hdr",
  4867. sizeof(struct qeth_hdr) + ETH_HLEN, 64, 0, NULL);
  4868. if (!qeth_core_header_cache) {
  4869. rc = -ENOMEM;
  4870. goto slab_err;
  4871. }
  4872. qeth_qdio_outbuf_cache = kmem_cache_create("qeth_buf",
  4873. sizeof(struct qeth_qdio_out_buffer), 0, 0, NULL);
  4874. if (!qeth_qdio_outbuf_cache) {
  4875. rc = -ENOMEM;
  4876. goto cqslab_err;
  4877. }
  4878. return 0;
  4879. cqslab_err:
  4880. kmem_cache_destroy(qeth_core_header_cache);
  4881. slab_err:
  4882. root_device_unregister(qeth_core_root_dev);
  4883. register_err:
  4884. driver_remove_file(&qeth_core_ccwgroup_driver.driver,
  4885. &driver_attr_group);
  4886. driver_err:
  4887. ccwgroup_driver_unregister(&qeth_core_ccwgroup_driver);
  4888. ccwgroup_err:
  4889. ccw_driver_unregister(&qeth_ccw_driver);
  4890. ccw_err:
  4891. QETH_DBF_MESSAGE(2, "Initialization failed with code %d\n", rc);
  4892. qeth_unregister_dbf_views();
  4893. out_err:
  4894. pr_err("Initializing the qeth device driver failed\n");
  4895. return rc;
  4896. }
  4897. static void __exit qeth_core_exit(void)
  4898. {
  4899. root_device_unregister(qeth_core_root_dev);
  4900. driver_remove_file(&qeth_core_ccwgroup_driver.driver,
  4901. &driver_attr_group);
  4902. ccwgroup_driver_unregister(&qeth_core_ccwgroup_driver);
  4903. ccw_driver_unregister(&qeth_ccw_driver);
  4904. kmem_cache_destroy(qeth_qdio_outbuf_cache);
  4905. kmem_cache_destroy(qeth_core_header_cache);
  4906. qeth_unregister_dbf_views();
  4907. pr_info("core functions removed\n");
  4908. }
  4909. module_init(qeth_core_init);
  4910. module_exit(qeth_core_exit);
  4911. MODULE_AUTHOR("Frank Blaschka <frank.blaschka@de.ibm.com>");
  4912. MODULE_DESCRIPTION("qeth core functions");
  4913. MODULE_LICENSE("GPL");