iwl-agn-ucode.c 18 KB

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  1. /******************************************************************************
  2. *
  3. * GPL LICENSE SUMMARY
  4. *
  5. * Copyright(c) 2008 - 2011 Intel Corporation. All rights reserved.
  6. *
  7. * This program is free software; you can redistribute it and/or modify
  8. * it under the terms of version 2 of the GNU General Public License as
  9. * published by the Free Software Foundation.
  10. *
  11. * This program is distributed in the hope that it will be useful, but
  12. * WITHOUT ANY WARRANTY; without even the implied warranty of
  13. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
  14. * General Public License for more details.
  15. *
  16. * You should have received a copy of the GNU General Public License
  17. * along with this program; if not, write to the Free Software
  18. * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110,
  19. * USA
  20. *
  21. * The full GNU General Public License is included in this distribution
  22. * in the file called LICENSE.GPL.
  23. *
  24. * Contact Information:
  25. * Intel Linux Wireless <ilw@linux.intel.com>
  26. * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
  27. *
  28. *****************************************************************************/
  29. #include <linux/kernel.h>
  30. #include <linux/module.h>
  31. #include <linux/init.h>
  32. #include <linux/sched.h>
  33. #include "iwl-dev.h"
  34. #include "iwl-core.h"
  35. #include "iwl-io.h"
  36. #include "iwl-agn-hw.h"
  37. #include "iwl-agn.h"
  38. #include "iwl-agn-calib.h"
  39. #include "iwl-trans.h"
  40. #include "iwl-fh.h"
  41. static struct iwl_wimax_coex_event_entry cu_priorities[COEX_NUM_OF_EVENTS] = {
  42. {COEX_CU_UNASSOC_IDLE_RP, COEX_CU_UNASSOC_IDLE_WP,
  43. 0, COEX_UNASSOC_IDLE_FLAGS},
  44. {COEX_CU_UNASSOC_MANUAL_SCAN_RP, COEX_CU_UNASSOC_MANUAL_SCAN_WP,
  45. 0, COEX_UNASSOC_MANUAL_SCAN_FLAGS},
  46. {COEX_CU_UNASSOC_AUTO_SCAN_RP, COEX_CU_UNASSOC_AUTO_SCAN_WP,
  47. 0, COEX_UNASSOC_AUTO_SCAN_FLAGS},
  48. {COEX_CU_CALIBRATION_RP, COEX_CU_CALIBRATION_WP,
  49. 0, COEX_CALIBRATION_FLAGS},
  50. {COEX_CU_PERIODIC_CALIBRATION_RP, COEX_CU_PERIODIC_CALIBRATION_WP,
  51. 0, COEX_PERIODIC_CALIBRATION_FLAGS},
  52. {COEX_CU_CONNECTION_ESTAB_RP, COEX_CU_CONNECTION_ESTAB_WP,
  53. 0, COEX_CONNECTION_ESTAB_FLAGS},
  54. {COEX_CU_ASSOCIATED_IDLE_RP, COEX_CU_ASSOCIATED_IDLE_WP,
  55. 0, COEX_ASSOCIATED_IDLE_FLAGS},
  56. {COEX_CU_ASSOC_MANUAL_SCAN_RP, COEX_CU_ASSOC_MANUAL_SCAN_WP,
  57. 0, COEX_ASSOC_MANUAL_SCAN_FLAGS},
  58. {COEX_CU_ASSOC_AUTO_SCAN_RP, COEX_CU_ASSOC_AUTO_SCAN_WP,
  59. 0, COEX_ASSOC_AUTO_SCAN_FLAGS},
  60. {COEX_CU_ASSOC_ACTIVE_LEVEL_RP, COEX_CU_ASSOC_ACTIVE_LEVEL_WP,
  61. 0, COEX_ASSOC_ACTIVE_LEVEL_FLAGS},
  62. {COEX_CU_RF_ON_RP, COEX_CU_RF_ON_WP, 0, COEX_CU_RF_ON_FLAGS},
  63. {COEX_CU_RF_OFF_RP, COEX_CU_RF_OFF_WP, 0, COEX_RF_OFF_FLAGS},
  64. {COEX_CU_STAND_ALONE_DEBUG_RP, COEX_CU_STAND_ALONE_DEBUG_WP,
  65. 0, COEX_STAND_ALONE_DEBUG_FLAGS},
  66. {COEX_CU_IPAN_ASSOC_LEVEL_RP, COEX_CU_IPAN_ASSOC_LEVEL_WP,
  67. 0, COEX_IPAN_ASSOC_LEVEL_FLAGS},
  68. {COEX_CU_RSRVD1_RP, COEX_CU_RSRVD1_WP, 0, COEX_RSRVD1_FLAGS},
  69. {COEX_CU_RSRVD2_RP, COEX_CU_RSRVD2_WP, 0, COEX_RSRVD2_FLAGS}
  70. };
  71. /*
  72. * ucode
  73. */
  74. static int iwlagn_load_section(struct iwl_priv *priv, const char *name,
  75. struct fw_desc *image, u32 dst_addr)
  76. {
  77. dma_addr_t phy_addr = image->p_addr;
  78. u32 byte_cnt = image->len;
  79. int ret;
  80. priv->ucode_write_complete = 0;
  81. iwl_write_direct32(bus(priv),
  82. FH_TCSR_CHNL_TX_CONFIG_REG(FH_SRVC_CHNL),
  83. FH_TCSR_TX_CONFIG_REG_VAL_DMA_CHNL_PAUSE);
  84. iwl_write_direct32(bus(priv),
  85. FH_SRVC_CHNL_SRAM_ADDR_REG(FH_SRVC_CHNL), dst_addr);
  86. iwl_write_direct32(bus(priv),
  87. FH_TFDIB_CTRL0_REG(FH_SRVC_CHNL),
  88. phy_addr & FH_MEM_TFDIB_DRAM_ADDR_LSB_MSK);
  89. iwl_write_direct32(bus(priv),
  90. FH_TFDIB_CTRL1_REG(FH_SRVC_CHNL),
  91. (iwl_get_dma_hi_addr(phy_addr)
  92. << FH_MEM_TFDIB_REG1_ADDR_BITSHIFT) | byte_cnt);
  93. iwl_write_direct32(bus(priv),
  94. FH_TCSR_CHNL_TX_BUF_STS_REG(FH_SRVC_CHNL),
  95. 1 << FH_TCSR_CHNL_TX_BUF_STS_REG_POS_TB_NUM |
  96. 1 << FH_TCSR_CHNL_TX_BUF_STS_REG_POS_TB_IDX |
  97. FH_TCSR_CHNL_TX_BUF_STS_REG_VAL_TFDB_VALID);
  98. iwl_write_direct32(bus(priv),
  99. FH_TCSR_CHNL_TX_CONFIG_REG(FH_SRVC_CHNL),
  100. FH_TCSR_TX_CONFIG_REG_VAL_DMA_CHNL_ENABLE |
  101. FH_TCSR_TX_CONFIG_REG_VAL_DMA_CREDIT_DISABLE |
  102. FH_TCSR_TX_CONFIG_REG_VAL_CIRQ_HOST_ENDTFD);
  103. IWL_DEBUG_FW(priv, "%s uCode section being loaded...\n", name);
  104. ret = wait_event_timeout(priv->shrd->wait_command_queue,
  105. priv->ucode_write_complete, 5 * HZ);
  106. if (!ret) {
  107. IWL_ERR(priv, "Could not load the %s uCode section\n",
  108. name);
  109. return -ETIMEDOUT;
  110. }
  111. return 0;
  112. }
  113. static int iwlagn_load_given_ucode(struct iwl_priv *priv,
  114. struct fw_img *image)
  115. {
  116. int ret = 0;
  117. ret = iwlagn_load_section(priv, "INST", &image->code,
  118. IWLAGN_RTC_INST_LOWER_BOUND);
  119. if (ret)
  120. return ret;
  121. return iwlagn_load_section(priv, "DATA", &image->data,
  122. IWLAGN_RTC_DATA_LOWER_BOUND);
  123. }
  124. /*
  125. * Calibration
  126. */
  127. static int iwlagn_set_Xtal_calib(struct iwl_priv *priv)
  128. {
  129. struct iwl_calib_xtal_freq_cmd cmd;
  130. __le16 *xtal_calib =
  131. (__le16 *)iwl_eeprom_query_addr(priv, EEPROM_XTAL);
  132. iwl_set_calib_hdr(&cmd.hdr, IWL_PHY_CALIBRATE_CRYSTAL_FRQ_CMD);
  133. cmd.cap_pin1 = le16_to_cpu(xtal_calib[0]);
  134. cmd.cap_pin2 = le16_to_cpu(xtal_calib[1]);
  135. return iwl_calib_set(&priv->calib_results[IWL_CALIB_XTAL],
  136. (u8 *)&cmd, sizeof(cmd));
  137. }
  138. static int iwlagn_set_temperature_offset_calib(struct iwl_priv *priv)
  139. {
  140. struct iwl_calib_temperature_offset_cmd cmd;
  141. __le16 *offset_calib =
  142. (__le16 *)iwl_eeprom_query_addr(priv, EEPROM_RAW_TEMPERATURE);
  143. memset(&cmd, 0, sizeof(cmd));
  144. iwl_set_calib_hdr(&cmd.hdr, IWL_PHY_CALIBRATE_TEMP_OFFSET_CMD);
  145. memcpy(&cmd.radio_sensor_offset, offset_calib, sizeof(*offset_calib));
  146. if (!(cmd.radio_sensor_offset))
  147. cmd.radio_sensor_offset = DEFAULT_RADIO_SENSOR_OFFSET;
  148. IWL_DEBUG_CALIB(priv, "Radio sensor offset: %d\n",
  149. le16_to_cpu(cmd.radio_sensor_offset));
  150. return iwl_calib_set(&priv->calib_results[IWL_CALIB_TEMP_OFFSET],
  151. (u8 *)&cmd, sizeof(cmd));
  152. }
  153. static int iwlagn_set_temperature_offset_calib_v2(struct iwl_priv *priv)
  154. {
  155. struct iwl_calib_temperature_offset_v2_cmd cmd;
  156. __le16 *offset_calib_high = (__le16 *)iwl_eeprom_query_addr(priv,
  157. EEPROM_KELVIN_TEMPERATURE);
  158. __le16 *offset_calib_low =
  159. (__le16 *)iwl_eeprom_query_addr(priv, EEPROM_RAW_TEMPERATURE);
  160. struct iwl_eeprom_calib_hdr *hdr;
  161. memset(&cmd, 0, sizeof(cmd));
  162. iwl_set_calib_hdr(&cmd.hdr, IWL_PHY_CALIBRATE_TEMP_OFFSET_CMD);
  163. hdr = (struct iwl_eeprom_calib_hdr *)iwl_eeprom_query_addr(priv,
  164. EEPROM_CALIB_ALL);
  165. memcpy(&cmd.radio_sensor_offset_high, offset_calib_high,
  166. sizeof(*offset_calib_high));
  167. memcpy(&cmd.radio_sensor_offset_low, offset_calib_low,
  168. sizeof(*offset_calib_low));
  169. if (!(cmd.radio_sensor_offset_low)) {
  170. IWL_DEBUG_CALIB(priv, "no info in EEPROM, use default\n");
  171. cmd.radio_sensor_offset_low = DEFAULT_RADIO_SENSOR_OFFSET;
  172. cmd.radio_sensor_offset_high = DEFAULT_RADIO_SENSOR_OFFSET;
  173. }
  174. memcpy(&cmd.burntVoltageRef, &hdr->voltage,
  175. sizeof(hdr->voltage));
  176. IWL_DEBUG_CALIB(priv, "Radio sensor offset high: %d\n",
  177. le16_to_cpu(cmd.radio_sensor_offset_high));
  178. IWL_DEBUG_CALIB(priv, "Radio sensor offset low: %d\n",
  179. le16_to_cpu(cmd.radio_sensor_offset_low));
  180. IWL_DEBUG_CALIB(priv, "Voltage Ref: %d\n",
  181. le16_to_cpu(cmd.burntVoltageRef));
  182. return iwl_calib_set(&priv->calib_results[IWL_CALIB_TEMP_OFFSET],
  183. (u8 *)&cmd, sizeof(cmd));
  184. }
  185. static int iwlagn_send_calib_cfg(struct iwl_priv *priv)
  186. {
  187. struct iwl_calib_cfg_cmd calib_cfg_cmd;
  188. struct iwl_host_cmd cmd = {
  189. .id = CALIBRATION_CFG_CMD,
  190. .len = { sizeof(struct iwl_calib_cfg_cmd), },
  191. .data = { &calib_cfg_cmd, },
  192. };
  193. memset(&calib_cfg_cmd, 0, sizeof(calib_cfg_cmd));
  194. calib_cfg_cmd.ucd_calib_cfg.once.is_enable = IWL_CALIB_INIT_CFG_ALL;
  195. calib_cfg_cmd.ucd_calib_cfg.once.start = IWL_CALIB_INIT_CFG_ALL;
  196. calib_cfg_cmd.ucd_calib_cfg.once.send_res = IWL_CALIB_INIT_CFG_ALL;
  197. calib_cfg_cmd.ucd_calib_cfg.flags =
  198. IWL_CALIB_CFG_FLAG_SEND_COMPLETE_NTFY_MSK;
  199. return iwl_trans_send_cmd(trans(priv), &cmd);
  200. }
  201. int iwlagn_rx_calib_result(struct iwl_priv *priv,
  202. struct iwl_rx_mem_buffer *rxb,
  203. struct iwl_device_cmd *cmd)
  204. {
  205. struct iwl_rx_packet *pkt = rxb_addr(rxb);
  206. struct iwl_calib_hdr *hdr = (struct iwl_calib_hdr *)pkt->u.raw;
  207. int len = le32_to_cpu(pkt->len_n_flags) & FH_RSCSR_FRAME_SIZE_MSK;
  208. int index;
  209. /* reduce the size of the length field itself */
  210. len -= 4;
  211. /* Define the order in which the results will be sent to the runtime
  212. * uCode. iwl_send_calib_results sends them in a row according to
  213. * their index. We sort them here
  214. */
  215. switch (hdr->op_code) {
  216. case IWL_PHY_CALIBRATE_DC_CMD:
  217. index = IWL_CALIB_DC;
  218. break;
  219. case IWL_PHY_CALIBRATE_LO_CMD:
  220. index = IWL_CALIB_LO;
  221. break;
  222. case IWL_PHY_CALIBRATE_TX_IQ_CMD:
  223. index = IWL_CALIB_TX_IQ;
  224. break;
  225. case IWL_PHY_CALIBRATE_TX_IQ_PERD_CMD:
  226. index = IWL_CALIB_TX_IQ_PERD;
  227. break;
  228. case IWL_PHY_CALIBRATE_BASE_BAND_CMD:
  229. index = IWL_CALIB_BASE_BAND;
  230. break;
  231. default:
  232. IWL_ERR(priv, "Unknown calibration notification %d\n",
  233. hdr->op_code);
  234. return -1;
  235. }
  236. iwl_calib_set(&priv->calib_results[index], pkt->u.raw, len);
  237. return 0;
  238. }
  239. int iwlagn_init_alive_start(struct iwl_priv *priv)
  240. {
  241. int ret;
  242. if (priv->cfg->bt_params &&
  243. priv->cfg->bt_params->advanced_bt_coexist) {
  244. /*
  245. * Tell uCode we are ready to perform calibration
  246. * need to perform this before any calibration
  247. * no need to close the envlope since we are going
  248. * to load the runtime uCode later.
  249. */
  250. ret = iwlagn_send_bt_env(priv, IWL_BT_COEX_ENV_OPEN,
  251. BT_COEX_PRIO_TBL_EVT_INIT_CALIB2);
  252. if (ret)
  253. return ret;
  254. }
  255. ret = iwlagn_send_calib_cfg(priv);
  256. if (ret)
  257. return ret;
  258. /**
  259. * temperature offset calibration is only needed for runtime ucode,
  260. * so prepare the value now.
  261. */
  262. if (priv->cfg->need_temp_offset_calib) {
  263. if (priv->cfg->temp_offset_v2)
  264. return iwlagn_set_temperature_offset_calib_v2(priv);
  265. else
  266. return iwlagn_set_temperature_offset_calib(priv);
  267. }
  268. return 0;
  269. }
  270. static int iwlagn_send_wimax_coex(struct iwl_priv *priv)
  271. {
  272. struct iwl_wimax_coex_cmd coex_cmd;
  273. if (priv->cfg->base_params->support_wimax_coexist) {
  274. /* UnMask wake up src at associated sleep */
  275. coex_cmd.flags = COEX_FLAGS_ASSOC_WA_UNMASK_MSK;
  276. /* UnMask wake up src at unassociated sleep */
  277. coex_cmd.flags |= COEX_FLAGS_UNASSOC_WA_UNMASK_MSK;
  278. memcpy(coex_cmd.sta_prio, cu_priorities,
  279. sizeof(struct iwl_wimax_coex_event_entry) *
  280. COEX_NUM_OF_EVENTS);
  281. /* enabling the coexistence feature */
  282. coex_cmd.flags |= COEX_FLAGS_COEX_ENABLE_MSK;
  283. /* enabling the priorities tables */
  284. coex_cmd.flags |= COEX_FLAGS_STA_TABLE_VALID_MSK;
  285. } else {
  286. /* coexistence is disabled */
  287. memset(&coex_cmd, 0, sizeof(coex_cmd));
  288. }
  289. return iwl_trans_send_cmd_pdu(trans(priv),
  290. COEX_PRIORITY_TABLE_CMD, CMD_SYNC,
  291. sizeof(coex_cmd), &coex_cmd);
  292. }
  293. static const u8 iwlagn_bt_prio_tbl[BT_COEX_PRIO_TBL_EVT_MAX] = {
  294. ((BT_COEX_PRIO_TBL_PRIO_BYPASS << IWL_BT_COEX_PRIO_TBL_PRIO_POS) |
  295. (0 << IWL_BT_COEX_PRIO_TBL_SHARED_ANTENNA_POS)),
  296. ((BT_COEX_PRIO_TBL_PRIO_BYPASS << IWL_BT_COEX_PRIO_TBL_PRIO_POS) |
  297. (1 << IWL_BT_COEX_PRIO_TBL_SHARED_ANTENNA_POS)),
  298. ((BT_COEX_PRIO_TBL_PRIO_LOW << IWL_BT_COEX_PRIO_TBL_PRIO_POS) |
  299. (0 << IWL_BT_COEX_PRIO_TBL_SHARED_ANTENNA_POS)),
  300. ((BT_COEX_PRIO_TBL_PRIO_LOW << IWL_BT_COEX_PRIO_TBL_PRIO_POS) |
  301. (1 << IWL_BT_COEX_PRIO_TBL_SHARED_ANTENNA_POS)),
  302. ((BT_COEX_PRIO_TBL_PRIO_HIGH << IWL_BT_COEX_PRIO_TBL_PRIO_POS) |
  303. (0 << IWL_BT_COEX_PRIO_TBL_SHARED_ANTENNA_POS)),
  304. ((BT_COEX_PRIO_TBL_PRIO_HIGH << IWL_BT_COEX_PRIO_TBL_PRIO_POS) |
  305. (1 << IWL_BT_COEX_PRIO_TBL_SHARED_ANTENNA_POS)),
  306. ((BT_COEX_PRIO_TBL_PRIO_BYPASS << IWL_BT_COEX_PRIO_TBL_PRIO_POS) |
  307. (0 << IWL_BT_COEX_PRIO_TBL_SHARED_ANTENNA_POS)),
  308. ((BT_COEX_PRIO_TBL_PRIO_COEX_OFF << IWL_BT_COEX_PRIO_TBL_PRIO_POS) |
  309. (0 << IWL_BT_COEX_PRIO_TBL_SHARED_ANTENNA_POS)),
  310. ((BT_COEX_PRIO_TBL_PRIO_COEX_ON << IWL_BT_COEX_PRIO_TBL_PRIO_POS) |
  311. (0 << IWL_BT_COEX_PRIO_TBL_SHARED_ANTENNA_POS)),
  312. 0, 0, 0, 0, 0, 0, 0
  313. };
  314. void iwlagn_send_prio_tbl(struct iwl_priv *priv)
  315. {
  316. struct iwl_bt_coex_prio_table_cmd prio_tbl_cmd;
  317. memcpy(prio_tbl_cmd.prio_tbl, iwlagn_bt_prio_tbl,
  318. sizeof(iwlagn_bt_prio_tbl));
  319. if (iwl_trans_send_cmd_pdu(trans(priv),
  320. REPLY_BT_COEX_PRIO_TABLE, CMD_SYNC,
  321. sizeof(prio_tbl_cmd), &prio_tbl_cmd))
  322. IWL_ERR(priv, "failed to send BT prio tbl command\n");
  323. }
  324. int iwlagn_send_bt_env(struct iwl_priv *priv, u8 action, u8 type)
  325. {
  326. struct iwl_bt_coex_prot_env_cmd env_cmd;
  327. int ret;
  328. env_cmd.action = action;
  329. env_cmd.type = type;
  330. ret = iwl_trans_send_cmd_pdu(trans(priv),
  331. REPLY_BT_COEX_PROT_ENV, CMD_SYNC,
  332. sizeof(env_cmd), &env_cmd);
  333. if (ret)
  334. IWL_ERR(priv, "failed to send BT env command\n");
  335. return ret;
  336. }
  337. static int iwlagn_alive_notify(struct iwl_priv *priv)
  338. {
  339. struct iwl_rxon_context *ctx;
  340. int ret;
  341. if (!priv->tx_cmd_pool)
  342. priv->tx_cmd_pool =
  343. kmem_cache_create("iwlagn_dev_cmd",
  344. sizeof(struct iwl_device_cmd),
  345. sizeof(void *), 0, NULL);
  346. if (!priv->tx_cmd_pool)
  347. return -ENOMEM;
  348. iwl_trans_tx_start(trans(priv));
  349. for_each_context(priv, ctx)
  350. ctx->last_tx_rejected = false;
  351. ret = iwlagn_send_wimax_coex(priv);
  352. if (ret)
  353. return ret;
  354. ret = iwlagn_set_Xtal_calib(priv);
  355. if (ret)
  356. return ret;
  357. return iwl_send_calib_results(priv);
  358. }
  359. /**
  360. * iwl_verify_inst_sparse - verify runtime uCode image in card vs. host,
  361. * using sample data 100 bytes apart. If these sample points are good,
  362. * it's a pretty good bet that everything between them is good, too.
  363. */
  364. static int iwl_verify_inst_sparse(struct iwl_priv *priv,
  365. struct fw_desc *fw_desc)
  366. {
  367. __le32 *image = (__le32 *)fw_desc->v_addr;
  368. u32 len = fw_desc->len;
  369. u32 val;
  370. u32 i;
  371. IWL_DEBUG_FW(priv, "ucode inst image size is %u\n", len);
  372. for (i = 0; i < len; i += 100, image += 100/sizeof(u32)) {
  373. /* read data comes through single port, auto-incr addr */
  374. /* NOTE: Use the debugless read so we don't flood kernel log
  375. * if IWL_DL_IO is set */
  376. iwl_write_direct32(bus(priv), HBUS_TARG_MEM_RADDR,
  377. i + IWLAGN_RTC_INST_LOWER_BOUND);
  378. val = iwl_read32(bus(priv), HBUS_TARG_MEM_RDAT);
  379. if (val != le32_to_cpu(*image))
  380. return -EIO;
  381. }
  382. return 0;
  383. }
  384. static void iwl_print_mismatch_inst(struct iwl_priv *priv,
  385. struct fw_desc *fw_desc)
  386. {
  387. __le32 *image = (__le32 *)fw_desc->v_addr;
  388. u32 len = fw_desc->len;
  389. u32 val;
  390. u32 offs;
  391. int errors = 0;
  392. IWL_DEBUG_FW(priv, "ucode inst image size is %u\n", len);
  393. iwl_write_direct32(bus(priv), HBUS_TARG_MEM_RADDR,
  394. IWLAGN_RTC_INST_LOWER_BOUND);
  395. for (offs = 0;
  396. offs < len && errors < 20;
  397. offs += sizeof(u32), image++) {
  398. /* read data comes through single port, auto-incr addr */
  399. val = iwl_read32(bus(priv), HBUS_TARG_MEM_RDAT);
  400. if (val != le32_to_cpu(*image)) {
  401. IWL_ERR(priv, "uCode INST section at "
  402. "offset 0x%x, is 0x%x, s/b 0x%x\n",
  403. offs, val, le32_to_cpu(*image));
  404. errors++;
  405. }
  406. }
  407. }
  408. /**
  409. * iwl_verify_ucode - determine which instruction image is in SRAM,
  410. * and verify its contents
  411. */
  412. static int iwl_verify_ucode(struct iwl_priv *priv, struct fw_img *img)
  413. {
  414. if (!iwl_verify_inst_sparse(priv, &img->code)) {
  415. IWL_DEBUG_FW(priv, "uCode is good in inst SRAM\n");
  416. return 0;
  417. }
  418. IWL_ERR(priv, "UCODE IMAGE IN INSTRUCTION SRAM NOT VALID!!\n");
  419. iwl_print_mismatch_inst(priv, &img->code);
  420. return -EIO;
  421. }
  422. struct iwlagn_alive_data {
  423. bool valid;
  424. u8 subtype;
  425. };
  426. static void iwlagn_alive_fn(struct iwl_priv *priv,
  427. struct iwl_rx_packet *pkt,
  428. void *data)
  429. {
  430. struct iwlagn_alive_data *alive_data = data;
  431. struct iwl_alive_resp *palive;
  432. palive = &pkt->u.alive_frame;
  433. IWL_DEBUG_FW(priv, "Alive ucode status 0x%08X revision "
  434. "0x%01X 0x%01X\n",
  435. palive->is_valid, palive->ver_type,
  436. palive->ver_subtype);
  437. priv->device_pointers.error_event_table =
  438. le32_to_cpu(palive->error_event_table_ptr);
  439. priv->device_pointers.log_event_table =
  440. le32_to_cpu(palive->log_event_table_ptr);
  441. alive_data->subtype = palive->ver_subtype;
  442. alive_data->valid = palive->is_valid == UCODE_VALID_OK;
  443. }
  444. #define UCODE_ALIVE_TIMEOUT HZ
  445. #define UCODE_CALIB_TIMEOUT (2*HZ)
  446. int iwlagn_load_ucode_wait_alive(struct iwl_priv *priv,
  447. struct fw_img *image,
  448. enum iwlagn_ucode_type ucode_type)
  449. {
  450. struct iwl_notification_wait alive_wait;
  451. struct iwlagn_alive_data alive_data;
  452. int ret;
  453. enum iwlagn_ucode_type old_type;
  454. ret = iwl_trans_start_device(trans(priv));
  455. if (ret)
  456. return ret;
  457. iwlagn_init_notification_wait(priv, &alive_wait, REPLY_ALIVE,
  458. iwlagn_alive_fn, &alive_data);
  459. old_type = priv->ucode_type;
  460. priv->ucode_type = ucode_type;
  461. ret = iwlagn_load_given_ucode(priv, image);
  462. if (ret) {
  463. priv->ucode_type = old_type;
  464. iwlagn_remove_notification(priv, &alive_wait);
  465. return ret;
  466. }
  467. iwl_trans_kick_nic(trans(priv));
  468. /*
  469. * Some things may run in the background now, but we
  470. * just wait for the ALIVE notification here.
  471. */
  472. ret = iwlagn_wait_notification(priv, &alive_wait, UCODE_ALIVE_TIMEOUT);
  473. if (ret) {
  474. priv->ucode_type = old_type;
  475. return ret;
  476. }
  477. if (!alive_data.valid) {
  478. IWL_ERR(priv, "Loaded ucode is not valid!\n");
  479. priv->ucode_type = old_type;
  480. return -EIO;
  481. }
  482. /*
  483. * This step takes a long time (60-80ms!!) and
  484. * WoWLAN image should be loaded quickly, so
  485. * skip it for WoWLAN.
  486. */
  487. if (ucode_type != IWL_UCODE_WOWLAN) {
  488. ret = iwl_verify_ucode(priv, image);
  489. if (ret) {
  490. priv->ucode_type = old_type;
  491. return ret;
  492. }
  493. /* delay a bit to give rfkill time to run */
  494. msleep(5);
  495. }
  496. ret = iwlagn_alive_notify(priv);
  497. if (ret) {
  498. IWL_WARN(priv,
  499. "Could not complete ALIVE transition: %d\n", ret);
  500. priv->ucode_type = old_type;
  501. return ret;
  502. }
  503. return 0;
  504. }
  505. int iwlagn_run_init_ucode(struct iwl_priv *priv)
  506. {
  507. struct iwl_notification_wait calib_wait;
  508. int ret;
  509. lockdep_assert_held(&priv->shrd->mutex);
  510. /* No init ucode required? Curious, but maybe ok */
  511. if (!priv->ucode_init.code.len)
  512. return 0;
  513. if (priv->ucode_type != IWL_UCODE_NONE)
  514. return 0;
  515. iwlagn_init_notification_wait(priv, &calib_wait,
  516. CALIBRATION_COMPLETE_NOTIFICATION,
  517. NULL, NULL);
  518. /* Will also start the device */
  519. ret = iwlagn_load_ucode_wait_alive(priv, &priv->ucode_init,
  520. IWL_UCODE_INIT);
  521. if (ret)
  522. goto error;
  523. ret = iwlagn_init_alive_start(priv);
  524. if (ret)
  525. goto error;
  526. /*
  527. * Some things may run in the background now, but we
  528. * just wait for the calibration complete notification.
  529. */
  530. ret = iwlagn_wait_notification(priv, &calib_wait, UCODE_CALIB_TIMEOUT);
  531. goto out;
  532. error:
  533. iwlagn_remove_notification(priv, &calib_wait);
  534. out:
  535. /* Whatever happened, stop the device */
  536. iwl_trans_stop_device(trans(priv));
  537. return ret;
  538. }