iwl4965-base.c 91 KB

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  1. /******************************************************************************
  2. *
  3. * Copyright(c) 2003 - 2011 Intel Corporation. All rights reserved.
  4. *
  5. * Portions of this file are derived from the ipw3945 project, as well
  6. * as portions of the ieee80211 subsystem header files.
  7. *
  8. * This program is free software; you can redistribute it and/or modify it
  9. * under the terms of version 2 of the GNU General Public License as
  10. * published by the Free Software Foundation.
  11. *
  12. * This program is distributed in the hope that it will be useful, but WITHOUT
  13. * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  14. * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
  15. * more details.
  16. *
  17. * You should have received a copy of the GNU General Public License along with
  18. * this program; if not, write to the Free Software Foundation, Inc.,
  19. * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
  20. *
  21. * The full GNU General Public License is included in this distribution in the
  22. * file called LICENSE.
  23. *
  24. * Contact Information:
  25. * Intel Linux Wireless <ilw@linux.intel.com>
  26. * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
  27. *
  28. *****************************************************************************/
  29. #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
  30. #include <linux/kernel.h>
  31. #include <linux/module.h>
  32. #include <linux/init.h>
  33. #include <linux/pci.h>
  34. #include <linux/pci-aspm.h>
  35. #include <linux/slab.h>
  36. #include <linux/dma-mapping.h>
  37. #include <linux/delay.h>
  38. #include <linux/sched.h>
  39. #include <linux/skbuff.h>
  40. #include <linux/netdevice.h>
  41. #include <linux/firmware.h>
  42. #include <linux/etherdevice.h>
  43. #include <linux/if_arp.h>
  44. #include <net/mac80211.h>
  45. #include <asm/div64.h>
  46. #define DRV_NAME "iwl4965"
  47. #include "iwl-eeprom.h"
  48. #include "iwl-dev.h"
  49. #include "iwl-core.h"
  50. #include "iwl-io.h"
  51. #include "iwl-helpers.h"
  52. #include "iwl-sta.h"
  53. #include "iwl-4965-calib.h"
  54. #include "iwl-4965.h"
  55. #include "iwl-4965-led.h"
  56. /******************************************************************************
  57. *
  58. * module boiler plate
  59. *
  60. ******************************************************************************/
  61. /*
  62. * module name, copyright, version, etc.
  63. */
  64. #define DRV_DESCRIPTION "Intel(R) Wireless WiFi 4965 driver for Linux"
  65. #ifdef CONFIG_IWLWIFI_LEGACY_DEBUG
  66. #define VD "d"
  67. #else
  68. #define VD
  69. #endif
  70. #define DRV_VERSION IWLWIFI_VERSION VD
  71. MODULE_DESCRIPTION(DRV_DESCRIPTION);
  72. MODULE_VERSION(DRV_VERSION);
  73. MODULE_AUTHOR(DRV_COPYRIGHT " " DRV_AUTHOR);
  74. MODULE_LICENSE("GPL");
  75. MODULE_ALIAS("iwl4965");
  76. void iwl4965_update_chain_flags(struct iwl_priv *priv)
  77. {
  78. struct iwl_rxon_context *ctx;
  79. if (priv->cfg->ops->hcmd->set_rxon_chain) {
  80. for_each_context(priv, ctx) {
  81. priv->cfg->ops->hcmd->set_rxon_chain(priv, ctx);
  82. if (ctx->active.rx_chain != ctx->staging.rx_chain)
  83. iwl_legacy_commit_rxon(priv, ctx);
  84. }
  85. }
  86. }
  87. static void iwl4965_clear_free_frames(struct iwl_priv *priv)
  88. {
  89. struct list_head *element;
  90. IWL_DEBUG_INFO(priv, "%d frames on pre-allocated heap on clear.\n",
  91. priv->frames_count);
  92. while (!list_empty(&priv->free_frames)) {
  93. element = priv->free_frames.next;
  94. list_del(element);
  95. kfree(list_entry(element, struct iwl_frame, list));
  96. priv->frames_count--;
  97. }
  98. if (priv->frames_count) {
  99. IWL_WARN(priv, "%d frames still in use. Did we lose one?\n",
  100. priv->frames_count);
  101. priv->frames_count = 0;
  102. }
  103. }
  104. static struct iwl_frame *iwl4965_get_free_frame(struct iwl_priv *priv)
  105. {
  106. struct iwl_frame *frame;
  107. struct list_head *element;
  108. if (list_empty(&priv->free_frames)) {
  109. frame = kzalloc(sizeof(*frame), GFP_KERNEL);
  110. if (!frame) {
  111. IWL_ERR(priv, "Could not allocate frame!\n");
  112. return NULL;
  113. }
  114. priv->frames_count++;
  115. return frame;
  116. }
  117. element = priv->free_frames.next;
  118. list_del(element);
  119. return list_entry(element, struct iwl_frame, list);
  120. }
  121. static void iwl4965_free_frame(struct iwl_priv *priv, struct iwl_frame *frame)
  122. {
  123. memset(frame, 0, sizeof(*frame));
  124. list_add(&frame->list, &priv->free_frames);
  125. }
  126. static u32 iwl4965_fill_beacon_frame(struct iwl_priv *priv,
  127. struct ieee80211_hdr *hdr,
  128. int left)
  129. {
  130. lockdep_assert_held(&priv->mutex);
  131. if (!priv->beacon_skb)
  132. return 0;
  133. if (priv->beacon_skb->len > left)
  134. return 0;
  135. memcpy(hdr, priv->beacon_skb->data, priv->beacon_skb->len);
  136. return priv->beacon_skb->len;
  137. }
  138. /* Parse the beacon frame to find the TIM element and set tim_idx & tim_size */
  139. static void iwl4965_set_beacon_tim(struct iwl_priv *priv,
  140. struct iwl_tx_beacon_cmd *tx_beacon_cmd,
  141. u8 *beacon, u32 frame_size)
  142. {
  143. u16 tim_idx;
  144. struct ieee80211_mgmt *mgmt = (struct ieee80211_mgmt *)beacon;
  145. /*
  146. * The index is relative to frame start but we start looking at the
  147. * variable-length part of the beacon.
  148. */
  149. tim_idx = mgmt->u.beacon.variable - beacon;
  150. /* Parse variable-length elements of beacon to find WLAN_EID_TIM */
  151. while ((tim_idx < (frame_size - 2)) &&
  152. (beacon[tim_idx] != WLAN_EID_TIM))
  153. tim_idx += beacon[tim_idx+1] + 2;
  154. /* If TIM field was found, set variables */
  155. if ((tim_idx < (frame_size - 1)) && (beacon[tim_idx] == WLAN_EID_TIM)) {
  156. tx_beacon_cmd->tim_idx = cpu_to_le16(tim_idx);
  157. tx_beacon_cmd->tim_size = beacon[tim_idx+1];
  158. } else
  159. IWL_WARN(priv, "Unable to find TIM Element in beacon\n");
  160. }
  161. static unsigned int iwl4965_hw_get_beacon_cmd(struct iwl_priv *priv,
  162. struct iwl_frame *frame)
  163. {
  164. struct iwl_tx_beacon_cmd *tx_beacon_cmd;
  165. u32 frame_size;
  166. u32 rate_flags;
  167. u32 rate;
  168. /*
  169. * We have to set up the TX command, the TX Beacon command, and the
  170. * beacon contents.
  171. */
  172. lockdep_assert_held(&priv->mutex);
  173. if (!priv->beacon_ctx) {
  174. IWL_ERR(priv, "trying to build beacon w/o beacon context!\n");
  175. return 0;
  176. }
  177. /* Initialize memory */
  178. tx_beacon_cmd = &frame->u.beacon;
  179. memset(tx_beacon_cmd, 0, sizeof(*tx_beacon_cmd));
  180. /* Set up TX beacon contents */
  181. frame_size = iwl4965_fill_beacon_frame(priv, tx_beacon_cmd->frame,
  182. sizeof(frame->u) - sizeof(*tx_beacon_cmd));
  183. if (WARN_ON_ONCE(frame_size > MAX_MPDU_SIZE))
  184. return 0;
  185. if (!frame_size)
  186. return 0;
  187. /* Set up TX command fields */
  188. tx_beacon_cmd->tx.len = cpu_to_le16((u16)frame_size);
  189. tx_beacon_cmd->tx.sta_id = priv->beacon_ctx->bcast_sta_id;
  190. tx_beacon_cmd->tx.stop_time.life_time = TX_CMD_LIFE_TIME_INFINITE;
  191. tx_beacon_cmd->tx.tx_flags = TX_CMD_FLG_SEQ_CTL_MSK |
  192. TX_CMD_FLG_TSF_MSK | TX_CMD_FLG_STA_RATE_MSK;
  193. /* Set up TX beacon command fields */
  194. iwl4965_set_beacon_tim(priv, tx_beacon_cmd, (u8 *)tx_beacon_cmd->frame,
  195. frame_size);
  196. /* Set up packet rate and flags */
  197. rate = iwl_legacy_get_lowest_plcp(priv, priv->beacon_ctx);
  198. priv->mgmt_tx_ant = iwl4965_toggle_tx_ant(priv, priv->mgmt_tx_ant,
  199. priv->hw_params.valid_tx_ant);
  200. rate_flags = iwl4965_ant_idx_to_flags(priv->mgmt_tx_ant);
  201. if ((rate >= IWL_FIRST_CCK_RATE) && (rate <= IWL_LAST_CCK_RATE))
  202. rate_flags |= RATE_MCS_CCK_MSK;
  203. tx_beacon_cmd->tx.rate_n_flags = iwl4965_hw_set_rate_n_flags(rate,
  204. rate_flags);
  205. return sizeof(*tx_beacon_cmd) + frame_size;
  206. }
  207. int iwl4965_send_beacon_cmd(struct iwl_priv *priv)
  208. {
  209. struct iwl_frame *frame;
  210. unsigned int frame_size;
  211. int rc;
  212. frame = iwl4965_get_free_frame(priv);
  213. if (!frame) {
  214. IWL_ERR(priv, "Could not obtain free frame buffer for beacon "
  215. "command.\n");
  216. return -ENOMEM;
  217. }
  218. frame_size = iwl4965_hw_get_beacon_cmd(priv, frame);
  219. if (!frame_size) {
  220. IWL_ERR(priv, "Error configuring the beacon command\n");
  221. iwl4965_free_frame(priv, frame);
  222. return -EINVAL;
  223. }
  224. rc = iwl_legacy_send_cmd_pdu(priv, REPLY_TX_BEACON, frame_size,
  225. &frame->u.cmd[0]);
  226. iwl4965_free_frame(priv, frame);
  227. return rc;
  228. }
  229. static inline dma_addr_t iwl4965_tfd_tb_get_addr(struct iwl_tfd *tfd, u8 idx)
  230. {
  231. struct iwl_tfd_tb *tb = &tfd->tbs[idx];
  232. dma_addr_t addr = get_unaligned_le32(&tb->lo);
  233. if (sizeof(dma_addr_t) > sizeof(u32))
  234. addr |=
  235. ((dma_addr_t)(le16_to_cpu(tb->hi_n_len) & 0xF) << 16) << 16;
  236. return addr;
  237. }
  238. static inline u16 iwl4965_tfd_tb_get_len(struct iwl_tfd *tfd, u8 idx)
  239. {
  240. struct iwl_tfd_tb *tb = &tfd->tbs[idx];
  241. return le16_to_cpu(tb->hi_n_len) >> 4;
  242. }
  243. static inline void iwl4965_tfd_set_tb(struct iwl_tfd *tfd, u8 idx,
  244. dma_addr_t addr, u16 len)
  245. {
  246. struct iwl_tfd_tb *tb = &tfd->tbs[idx];
  247. u16 hi_n_len = len << 4;
  248. put_unaligned_le32(addr, &tb->lo);
  249. if (sizeof(dma_addr_t) > sizeof(u32))
  250. hi_n_len |= ((addr >> 16) >> 16) & 0xF;
  251. tb->hi_n_len = cpu_to_le16(hi_n_len);
  252. tfd->num_tbs = idx + 1;
  253. }
  254. static inline u8 iwl4965_tfd_get_num_tbs(struct iwl_tfd *tfd)
  255. {
  256. return tfd->num_tbs & 0x1f;
  257. }
  258. /**
  259. * iwl4965_hw_txq_free_tfd - Free all chunks referenced by TFD [txq->q.read_ptr]
  260. * @priv - driver private data
  261. * @txq - tx queue
  262. *
  263. * Does NOT advance any TFD circular buffer read/write indexes
  264. * Does NOT free the TFD itself (which is within circular buffer)
  265. */
  266. void iwl4965_hw_txq_free_tfd(struct iwl_priv *priv, struct iwl_tx_queue *txq)
  267. {
  268. struct iwl_tfd *tfd_tmp = (struct iwl_tfd *)txq->tfds;
  269. struct iwl_tfd *tfd;
  270. struct pci_dev *dev = priv->pci_dev;
  271. int index = txq->q.read_ptr;
  272. int i;
  273. int num_tbs;
  274. tfd = &tfd_tmp[index];
  275. /* Sanity check on number of chunks */
  276. num_tbs = iwl4965_tfd_get_num_tbs(tfd);
  277. if (num_tbs >= IWL_NUM_OF_TBS) {
  278. IWL_ERR(priv, "Too many chunks: %i\n", num_tbs);
  279. /* @todo issue fatal error, it is quite serious situation */
  280. return;
  281. }
  282. /* Unmap tx_cmd */
  283. if (num_tbs)
  284. pci_unmap_single(dev,
  285. dma_unmap_addr(&txq->meta[index], mapping),
  286. dma_unmap_len(&txq->meta[index], len),
  287. PCI_DMA_BIDIRECTIONAL);
  288. /* Unmap chunks, if any. */
  289. for (i = 1; i < num_tbs; i++)
  290. pci_unmap_single(dev, iwl4965_tfd_tb_get_addr(tfd, i),
  291. iwl4965_tfd_tb_get_len(tfd, i),
  292. PCI_DMA_TODEVICE);
  293. /* free SKB */
  294. if (txq->txb) {
  295. struct sk_buff *skb;
  296. skb = txq->txb[txq->q.read_ptr].skb;
  297. /* can be called from irqs-disabled context */
  298. if (skb) {
  299. dev_kfree_skb_any(skb);
  300. txq->txb[txq->q.read_ptr].skb = NULL;
  301. }
  302. }
  303. }
  304. int iwl4965_hw_txq_attach_buf_to_tfd(struct iwl_priv *priv,
  305. struct iwl_tx_queue *txq,
  306. dma_addr_t addr, u16 len,
  307. u8 reset, u8 pad)
  308. {
  309. struct iwl_queue *q;
  310. struct iwl_tfd *tfd, *tfd_tmp;
  311. u32 num_tbs;
  312. q = &txq->q;
  313. tfd_tmp = (struct iwl_tfd *)txq->tfds;
  314. tfd = &tfd_tmp[q->write_ptr];
  315. if (reset)
  316. memset(tfd, 0, sizeof(*tfd));
  317. num_tbs = iwl4965_tfd_get_num_tbs(tfd);
  318. /* Each TFD can point to a maximum 20 Tx buffers */
  319. if (num_tbs >= IWL_NUM_OF_TBS) {
  320. IWL_ERR(priv, "Error can not send more than %d chunks\n",
  321. IWL_NUM_OF_TBS);
  322. return -EINVAL;
  323. }
  324. BUG_ON(addr & ~DMA_BIT_MASK(36));
  325. if (unlikely(addr & ~IWL_TX_DMA_MASK))
  326. IWL_ERR(priv, "Unaligned address = %llx\n",
  327. (unsigned long long)addr);
  328. iwl4965_tfd_set_tb(tfd, num_tbs, addr, len);
  329. return 0;
  330. }
  331. /*
  332. * Tell nic where to find circular buffer of Tx Frame Descriptors for
  333. * given Tx queue, and enable the DMA channel used for that queue.
  334. *
  335. * 4965 supports up to 16 Tx queues in DRAM, mapped to up to 8 Tx DMA
  336. * channels supported in hardware.
  337. */
  338. int iwl4965_hw_tx_queue_init(struct iwl_priv *priv,
  339. struct iwl_tx_queue *txq)
  340. {
  341. int txq_id = txq->q.id;
  342. /* Circular buffer (TFD queue in DRAM) physical base address */
  343. iwl_legacy_write_direct32(priv, FH_MEM_CBBC_QUEUE(txq_id),
  344. txq->q.dma_addr >> 8);
  345. return 0;
  346. }
  347. /******************************************************************************
  348. *
  349. * Generic RX handler implementations
  350. *
  351. ******************************************************************************/
  352. static void iwl4965_rx_reply_alive(struct iwl_priv *priv,
  353. struct iwl_rx_mem_buffer *rxb)
  354. {
  355. struct iwl_rx_packet *pkt = rxb_addr(rxb);
  356. struct iwl_alive_resp *palive;
  357. struct delayed_work *pwork;
  358. palive = &pkt->u.alive_frame;
  359. IWL_DEBUG_INFO(priv, "Alive ucode status 0x%08X revision "
  360. "0x%01X 0x%01X\n",
  361. palive->is_valid, palive->ver_type,
  362. palive->ver_subtype);
  363. if (palive->ver_subtype == INITIALIZE_SUBTYPE) {
  364. IWL_DEBUG_INFO(priv, "Initialization Alive received.\n");
  365. memcpy(&priv->card_alive_init,
  366. &pkt->u.alive_frame,
  367. sizeof(struct iwl_init_alive_resp));
  368. pwork = &priv->init_alive_start;
  369. } else {
  370. IWL_DEBUG_INFO(priv, "Runtime Alive received.\n");
  371. memcpy(&priv->card_alive, &pkt->u.alive_frame,
  372. sizeof(struct iwl_alive_resp));
  373. pwork = &priv->alive_start;
  374. }
  375. /* We delay the ALIVE response by 5ms to
  376. * give the HW RF Kill time to activate... */
  377. if (palive->is_valid == UCODE_VALID_OK)
  378. queue_delayed_work(priv->workqueue, pwork,
  379. msecs_to_jiffies(5));
  380. else
  381. IWL_WARN(priv, "uCode did not respond OK.\n");
  382. }
  383. /**
  384. * iwl4965_bg_statistics_periodic - Timer callback to queue statistics
  385. *
  386. * This callback is provided in order to send a statistics request.
  387. *
  388. * This timer function is continually reset to execute within
  389. * REG_RECALIB_PERIOD seconds since the last STATISTICS_NOTIFICATION
  390. * was received. We need to ensure we receive the statistics in order
  391. * to update the temperature used for calibrating the TXPOWER.
  392. */
  393. static void iwl4965_bg_statistics_periodic(unsigned long data)
  394. {
  395. struct iwl_priv *priv = (struct iwl_priv *)data;
  396. if (test_bit(STATUS_EXIT_PENDING, &priv->status))
  397. return;
  398. /* dont send host command if rf-kill is on */
  399. if (!iwl_legacy_is_ready_rf(priv))
  400. return;
  401. iwl_legacy_send_statistics_request(priv, CMD_ASYNC, false);
  402. }
  403. static void iwl4965_rx_beacon_notif(struct iwl_priv *priv,
  404. struct iwl_rx_mem_buffer *rxb)
  405. {
  406. struct iwl_rx_packet *pkt = rxb_addr(rxb);
  407. struct iwl4965_beacon_notif *beacon =
  408. (struct iwl4965_beacon_notif *)pkt->u.raw;
  409. #ifdef CONFIG_IWLWIFI_LEGACY_DEBUG
  410. u8 rate = iwl4965_hw_get_rate(beacon->beacon_notify_hdr.rate_n_flags);
  411. IWL_DEBUG_RX(priv, "beacon status %x retries %d iss %d "
  412. "tsf %d %d rate %d\n",
  413. le32_to_cpu(beacon->beacon_notify_hdr.u.status) & TX_STATUS_MSK,
  414. beacon->beacon_notify_hdr.failure_frame,
  415. le32_to_cpu(beacon->ibss_mgr_status),
  416. le32_to_cpu(beacon->high_tsf),
  417. le32_to_cpu(beacon->low_tsf), rate);
  418. #endif
  419. priv->ibss_manager = le32_to_cpu(beacon->ibss_mgr_status);
  420. }
  421. static void iwl4965_perform_ct_kill_task(struct iwl_priv *priv)
  422. {
  423. unsigned long flags;
  424. IWL_DEBUG_POWER(priv, "Stop all queues\n");
  425. if (priv->mac80211_registered)
  426. ieee80211_stop_queues(priv->hw);
  427. iwl_write32(priv, CSR_UCODE_DRV_GP1_SET,
  428. CSR_UCODE_DRV_GP1_REG_BIT_CT_KILL_EXIT);
  429. iwl_read32(priv, CSR_UCODE_DRV_GP1);
  430. spin_lock_irqsave(&priv->reg_lock, flags);
  431. if (!iwl_grab_nic_access(priv))
  432. iwl_release_nic_access(priv);
  433. spin_unlock_irqrestore(&priv->reg_lock, flags);
  434. }
  435. /* Handle notification from uCode that card's power state is changing
  436. * due to software, hardware, or critical temperature RFKILL */
  437. static void iwl4965_rx_card_state_notif(struct iwl_priv *priv,
  438. struct iwl_rx_mem_buffer *rxb)
  439. {
  440. struct iwl_rx_packet *pkt = rxb_addr(rxb);
  441. u32 flags = le32_to_cpu(pkt->u.card_state_notif.flags);
  442. unsigned long status = priv->status;
  443. IWL_DEBUG_RF_KILL(priv, "Card state received: HW:%s SW:%s CT:%s\n",
  444. (flags & HW_CARD_DISABLED) ? "Kill" : "On",
  445. (flags & SW_CARD_DISABLED) ? "Kill" : "On",
  446. (flags & CT_CARD_DISABLED) ?
  447. "Reached" : "Not reached");
  448. if (flags & (SW_CARD_DISABLED | HW_CARD_DISABLED |
  449. CT_CARD_DISABLED)) {
  450. iwl_write32(priv, CSR_UCODE_DRV_GP1_SET,
  451. CSR_UCODE_DRV_GP1_BIT_CMD_BLOCKED);
  452. iwl_legacy_write_direct32(priv, HBUS_TARG_MBX_C,
  453. HBUS_TARG_MBX_C_REG_BIT_CMD_BLOCKED);
  454. if (!(flags & RXON_CARD_DISABLED)) {
  455. iwl_write32(priv, CSR_UCODE_DRV_GP1_CLR,
  456. CSR_UCODE_DRV_GP1_BIT_CMD_BLOCKED);
  457. iwl_legacy_write_direct32(priv, HBUS_TARG_MBX_C,
  458. HBUS_TARG_MBX_C_REG_BIT_CMD_BLOCKED);
  459. }
  460. }
  461. if (flags & CT_CARD_DISABLED)
  462. iwl4965_perform_ct_kill_task(priv);
  463. if (flags & HW_CARD_DISABLED)
  464. set_bit(STATUS_RF_KILL_HW, &priv->status);
  465. else
  466. clear_bit(STATUS_RF_KILL_HW, &priv->status);
  467. if (!(flags & RXON_CARD_DISABLED))
  468. iwl_legacy_scan_cancel(priv);
  469. if ((test_bit(STATUS_RF_KILL_HW, &status) !=
  470. test_bit(STATUS_RF_KILL_HW, &priv->status)))
  471. wiphy_rfkill_set_hw_state(priv->hw->wiphy,
  472. test_bit(STATUS_RF_KILL_HW, &priv->status));
  473. else
  474. wake_up(&priv->wait_command_queue);
  475. }
  476. /**
  477. * iwl4965_setup_rx_handlers - Initialize Rx handler callbacks
  478. *
  479. * Setup the RX handlers for each of the reply types sent from the uCode
  480. * to the host.
  481. *
  482. * This function chains into the hardware specific files for them to setup
  483. * any hardware specific handlers as well.
  484. */
  485. static void iwl4965_setup_rx_handlers(struct iwl_priv *priv)
  486. {
  487. priv->rx_handlers[REPLY_ALIVE] = iwl4965_rx_reply_alive;
  488. priv->rx_handlers[REPLY_ERROR] = iwl_legacy_rx_reply_error;
  489. priv->rx_handlers[CHANNEL_SWITCH_NOTIFICATION] = iwl_legacy_rx_csa;
  490. priv->rx_handlers[SPECTRUM_MEASURE_NOTIFICATION] =
  491. iwl_legacy_rx_spectrum_measure_notif;
  492. priv->rx_handlers[PM_SLEEP_NOTIFICATION] = iwl_legacy_rx_pm_sleep_notif;
  493. priv->rx_handlers[PM_DEBUG_STATISTIC_NOTIFIC] =
  494. iwl_legacy_rx_pm_debug_statistics_notif;
  495. priv->rx_handlers[BEACON_NOTIFICATION] = iwl4965_rx_beacon_notif;
  496. /*
  497. * The same handler is used for both the REPLY to a discrete
  498. * statistics request from the host as well as for the periodic
  499. * statistics notifications (after received beacons) from the uCode.
  500. */
  501. priv->rx_handlers[REPLY_STATISTICS_CMD] = iwl4965_reply_statistics;
  502. priv->rx_handlers[STATISTICS_NOTIFICATION] = iwl4965_rx_statistics;
  503. iwl_legacy_setup_rx_scan_handlers(priv);
  504. /* status change handler */
  505. priv->rx_handlers[CARD_STATE_NOTIFICATION] =
  506. iwl4965_rx_card_state_notif;
  507. priv->rx_handlers[MISSED_BEACONS_NOTIFICATION] =
  508. iwl4965_rx_missed_beacon_notif;
  509. /* Rx handlers */
  510. priv->rx_handlers[REPLY_RX_PHY_CMD] = iwl4965_rx_reply_rx_phy;
  511. priv->rx_handlers[REPLY_RX_MPDU_CMD] = iwl4965_rx_reply_rx;
  512. /* block ack */
  513. priv->rx_handlers[REPLY_COMPRESSED_BA] = iwl4965_rx_reply_compressed_ba;
  514. /* Set up hardware specific Rx handlers */
  515. priv->cfg->ops->lib->rx_handler_setup(priv);
  516. }
  517. /**
  518. * iwl4965_rx_handle - Main entry function for receiving responses from uCode
  519. *
  520. * Uses the priv->rx_handlers callback function array to invoke
  521. * the appropriate handlers, including command responses,
  522. * frame-received notifications, and other notifications.
  523. */
  524. void iwl4965_rx_handle(struct iwl_priv *priv)
  525. {
  526. struct iwl_rx_mem_buffer *rxb;
  527. struct iwl_rx_packet *pkt;
  528. struct iwl_rx_queue *rxq = &priv->rxq;
  529. u32 r, i;
  530. int reclaim;
  531. unsigned long flags;
  532. u8 fill_rx = 0;
  533. u32 count = 8;
  534. int total_empty;
  535. /* uCode's read index (stored in shared DRAM) indicates the last Rx
  536. * buffer that the driver may process (last buffer filled by ucode). */
  537. r = le16_to_cpu(rxq->rb_stts->closed_rb_num) & 0x0FFF;
  538. i = rxq->read;
  539. /* Rx interrupt, but nothing sent from uCode */
  540. if (i == r)
  541. IWL_DEBUG_RX(priv, "r = %d, i = %d\n", r, i);
  542. /* calculate total frames need to be restock after handling RX */
  543. total_empty = r - rxq->write_actual;
  544. if (total_empty < 0)
  545. total_empty += RX_QUEUE_SIZE;
  546. if (total_empty > (RX_QUEUE_SIZE / 2))
  547. fill_rx = 1;
  548. while (i != r) {
  549. int len;
  550. rxb = rxq->queue[i];
  551. /* If an RXB doesn't have a Rx queue slot associated with it,
  552. * then a bug has been introduced in the queue refilling
  553. * routines -- catch it here */
  554. BUG_ON(rxb == NULL);
  555. rxq->queue[i] = NULL;
  556. pci_unmap_page(priv->pci_dev, rxb->page_dma,
  557. PAGE_SIZE << priv->hw_params.rx_page_order,
  558. PCI_DMA_FROMDEVICE);
  559. pkt = rxb_addr(rxb);
  560. len = le32_to_cpu(pkt->len_n_flags) & FH_RSCSR_FRAME_SIZE_MSK;
  561. len += sizeof(u32); /* account for status word */
  562. trace_iwlwifi_legacy_dev_rx(priv, pkt, len);
  563. /* Reclaim a command buffer only if this packet is a response
  564. * to a (driver-originated) command.
  565. * If the packet (e.g. Rx frame) originated from uCode,
  566. * there is no command buffer to reclaim.
  567. * Ucode should set SEQ_RX_FRAME bit if ucode-originated,
  568. * but apparently a few don't get set; catch them here. */
  569. reclaim = !(pkt->hdr.sequence & SEQ_RX_FRAME) &&
  570. (pkt->hdr.cmd != REPLY_RX_PHY_CMD) &&
  571. (pkt->hdr.cmd != REPLY_RX) &&
  572. (pkt->hdr.cmd != REPLY_RX_MPDU_CMD) &&
  573. (pkt->hdr.cmd != REPLY_COMPRESSED_BA) &&
  574. (pkt->hdr.cmd != STATISTICS_NOTIFICATION) &&
  575. (pkt->hdr.cmd != REPLY_TX);
  576. /* Based on type of command response or notification,
  577. * handle those that need handling via function in
  578. * rx_handlers table. See iwl4965_setup_rx_handlers() */
  579. if (priv->rx_handlers[pkt->hdr.cmd]) {
  580. IWL_DEBUG_RX(priv, "r = %d, i = %d, %s, 0x%02x\n", r,
  581. i, iwl_legacy_get_cmd_string(pkt->hdr.cmd),
  582. pkt->hdr.cmd);
  583. priv->isr_stats.rx_handlers[pkt->hdr.cmd]++;
  584. priv->rx_handlers[pkt->hdr.cmd] (priv, rxb);
  585. } else {
  586. /* No handling needed */
  587. IWL_DEBUG_RX(priv,
  588. "r %d i %d No handler needed for %s, 0x%02x\n",
  589. r, i, iwl_legacy_get_cmd_string(pkt->hdr.cmd),
  590. pkt->hdr.cmd);
  591. }
  592. /*
  593. * XXX: After here, we should always check rxb->page
  594. * against NULL before touching it or its virtual
  595. * memory (pkt). Because some rx_handler might have
  596. * already taken or freed the pages.
  597. */
  598. if (reclaim) {
  599. /* Invoke any callbacks, transfer the buffer to caller,
  600. * and fire off the (possibly) blocking iwl_legacy_send_cmd()
  601. * as we reclaim the driver command queue */
  602. if (rxb->page)
  603. iwl_legacy_tx_cmd_complete(priv, rxb);
  604. else
  605. IWL_WARN(priv, "Claim null rxb?\n");
  606. }
  607. /* Reuse the page if possible. For notification packets and
  608. * SKBs that fail to Rx correctly, add them back into the
  609. * rx_free list for reuse later. */
  610. spin_lock_irqsave(&rxq->lock, flags);
  611. if (rxb->page != NULL) {
  612. rxb->page_dma = pci_map_page(priv->pci_dev, rxb->page,
  613. 0, PAGE_SIZE << priv->hw_params.rx_page_order,
  614. PCI_DMA_FROMDEVICE);
  615. list_add_tail(&rxb->list, &rxq->rx_free);
  616. rxq->free_count++;
  617. } else
  618. list_add_tail(&rxb->list, &rxq->rx_used);
  619. spin_unlock_irqrestore(&rxq->lock, flags);
  620. i = (i + 1) & RX_QUEUE_MASK;
  621. /* If there are a lot of unused frames,
  622. * restock the Rx queue so ucode wont assert. */
  623. if (fill_rx) {
  624. count++;
  625. if (count >= 8) {
  626. rxq->read = i;
  627. iwl4965_rx_replenish_now(priv);
  628. count = 0;
  629. }
  630. }
  631. }
  632. /* Backtrack one entry */
  633. rxq->read = i;
  634. if (fill_rx)
  635. iwl4965_rx_replenish_now(priv);
  636. else
  637. iwl4965_rx_queue_restock(priv);
  638. }
  639. /* call this function to flush any scheduled tasklet */
  640. static inline void iwl4965_synchronize_irq(struct iwl_priv *priv)
  641. {
  642. /* wait to make sure we flush pending tasklet*/
  643. synchronize_irq(priv->pci_dev->irq);
  644. tasklet_kill(&priv->irq_tasklet);
  645. }
  646. static void iwl4965_irq_tasklet(struct iwl_priv *priv)
  647. {
  648. u32 inta, handled = 0;
  649. u32 inta_fh;
  650. unsigned long flags;
  651. u32 i;
  652. #ifdef CONFIG_IWLWIFI_LEGACY_DEBUG
  653. u32 inta_mask;
  654. #endif
  655. spin_lock_irqsave(&priv->lock, flags);
  656. /* Ack/clear/reset pending uCode interrupts.
  657. * Note: Some bits in CSR_INT are "OR" of bits in CSR_FH_INT_STATUS,
  658. * and will clear only when CSR_FH_INT_STATUS gets cleared. */
  659. inta = iwl_read32(priv, CSR_INT);
  660. iwl_write32(priv, CSR_INT, inta);
  661. /* Ack/clear/reset pending flow-handler (DMA) interrupts.
  662. * Any new interrupts that happen after this, either while we're
  663. * in this tasklet, or later, will show up in next ISR/tasklet. */
  664. inta_fh = iwl_read32(priv, CSR_FH_INT_STATUS);
  665. iwl_write32(priv, CSR_FH_INT_STATUS, inta_fh);
  666. #ifdef CONFIG_IWLWIFI_LEGACY_DEBUG
  667. if (iwl_legacy_get_debug_level(priv) & IWL_DL_ISR) {
  668. /* just for debug */
  669. inta_mask = iwl_read32(priv, CSR_INT_MASK);
  670. IWL_DEBUG_ISR(priv, "inta 0x%08x, enabled 0x%08x, fh 0x%08x\n",
  671. inta, inta_mask, inta_fh);
  672. }
  673. #endif
  674. spin_unlock_irqrestore(&priv->lock, flags);
  675. /* Since CSR_INT and CSR_FH_INT_STATUS reads and clears are not
  676. * atomic, make sure that inta covers all the interrupts that
  677. * we've discovered, even if FH interrupt came in just after
  678. * reading CSR_INT. */
  679. if (inta_fh & CSR49_FH_INT_RX_MASK)
  680. inta |= CSR_INT_BIT_FH_RX;
  681. if (inta_fh & CSR49_FH_INT_TX_MASK)
  682. inta |= CSR_INT_BIT_FH_TX;
  683. /* Now service all interrupt bits discovered above. */
  684. if (inta & CSR_INT_BIT_HW_ERR) {
  685. IWL_ERR(priv, "Hardware error detected. Restarting.\n");
  686. /* Tell the device to stop sending interrupts */
  687. iwl_legacy_disable_interrupts(priv);
  688. priv->isr_stats.hw++;
  689. iwl_legacy_irq_handle_error(priv);
  690. handled |= CSR_INT_BIT_HW_ERR;
  691. return;
  692. }
  693. #ifdef CONFIG_IWLWIFI_LEGACY_DEBUG
  694. if (iwl_legacy_get_debug_level(priv) & (IWL_DL_ISR)) {
  695. /* NIC fires this, but we don't use it, redundant with WAKEUP */
  696. if (inta & CSR_INT_BIT_SCD) {
  697. IWL_DEBUG_ISR(priv, "Scheduler finished to transmit "
  698. "the frame/frames.\n");
  699. priv->isr_stats.sch++;
  700. }
  701. /* Alive notification via Rx interrupt will do the real work */
  702. if (inta & CSR_INT_BIT_ALIVE) {
  703. IWL_DEBUG_ISR(priv, "Alive interrupt\n");
  704. priv->isr_stats.alive++;
  705. }
  706. }
  707. #endif
  708. /* Safely ignore these bits for debug checks below */
  709. inta &= ~(CSR_INT_BIT_SCD | CSR_INT_BIT_ALIVE);
  710. /* HW RF KILL switch toggled */
  711. if (inta & CSR_INT_BIT_RF_KILL) {
  712. int hw_rf_kill = 0;
  713. if (!(iwl_read32(priv, CSR_GP_CNTRL) &
  714. CSR_GP_CNTRL_REG_FLAG_HW_RF_KILL_SW))
  715. hw_rf_kill = 1;
  716. IWL_WARN(priv, "RF_KILL bit toggled to %s.\n",
  717. hw_rf_kill ? "disable radio" : "enable radio");
  718. priv->isr_stats.rfkill++;
  719. /* driver only loads ucode once setting the interface up.
  720. * the driver allows loading the ucode even if the radio
  721. * is killed. Hence update the killswitch state here. The
  722. * rfkill handler will care about restarting if needed.
  723. */
  724. if (!test_bit(STATUS_ALIVE, &priv->status)) {
  725. if (hw_rf_kill)
  726. set_bit(STATUS_RF_KILL_HW, &priv->status);
  727. else
  728. clear_bit(STATUS_RF_KILL_HW, &priv->status);
  729. wiphy_rfkill_set_hw_state(priv->hw->wiphy, hw_rf_kill);
  730. }
  731. handled |= CSR_INT_BIT_RF_KILL;
  732. }
  733. /* Chip got too hot and stopped itself */
  734. if (inta & CSR_INT_BIT_CT_KILL) {
  735. IWL_ERR(priv, "Microcode CT kill error detected.\n");
  736. priv->isr_stats.ctkill++;
  737. handled |= CSR_INT_BIT_CT_KILL;
  738. }
  739. /* Error detected by uCode */
  740. if (inta & CSR_INT_BIT_SW_ERR) {
  741. IWL_ERR(priv, "Microcode SW error detected. "
  742. " Restarting 0x%X.\n", inta);
  743. priv->isr_stats.sw++;
  744. iwl_legacy_irq_handle_error(priv);
  745. handled |= CSR_INT_BIT_SW_ERR;
  746. }
  747. /*
  748. * uCode wakes up after power-down sleep.
  749. * Tell device about any new tx or host commands enqueued,
  750. * and about any Rx buffers made available while asleep.
  751. */
  752. if (inta & CSR_INT_BIT_WAKEUP) {
  753. IWL_DEBUG_ISR(priv, "Wakeup interrupt\n");
  754. iwl_legacy_rx_queue_update_write_ptr(priv, &priv->rxq);
  755. for (i = 0; i < priv->hw_params.max_txq_num; i++)
  756. iwl_legacy_txq_update_write_ptr(priv, &priv->txq[i]);
  757. priv->isr_stats.wakeup++;
  758. handled |= CSR_INT_BIT_WAKEUP;
  759. }
  760. /* All uCode command responses, including Tx command responses,
  761. * Rx "responses" (frame-received notification), and other
  762. * notifications from uCode come through here*/
  763. if (inta & (CSR_INT_BIT_FH_RX | CSR_INT_BIT_SW_RX)) {
  764. iwl4965_rx_handle(priv);
  765. priv->isr_stats.rx++;
  766. handled |= (CSR_INT_BIT_FH_RX | CSR_INT_BIT_SW_RX);
  767. }
  768. /* This "Tx" DMA channel is used only for loading uCode */
  769. if (inta & CSR_INT_BIT_FH_TX) {
  770. IWL_DEBUG_ISR(priv, "uCode load interrupt\n");
  771. priv->isr_stats.tx++;
  772. handled |= CSR_INT_BIT_FH_TX;
  773. /* Wake up uCode load routine, now that load is complete */
  774. priv->ucode_write_complete = 1;
  775. wake_up(&priv->wait_command_queue);
  776. }
  777. if (inta & ~handled) {
  778. IWL_ERR(priv, "Unhandled INTA bits 0x%08x\n", inta & ~handled);
  779. priv->isr_stats.unhandled++;
  780. }
  781. if (inta & ~(priv->inta_mask)) {
  782. IWL_WARN(priv, "Disabled INTA bits 0x%08x were pending\n",
  783. inta & ~priv->inta_mask);
  784. IWL_WARN(priv, " with FH_INT = 0x%08x\n", inta_fh);
  785. }
  786. /* Re-enable all interrupts */
  787. /* only Re-enable if disabled by irq */
  788. if (test_bit(STATUS_INT_ENABLED, &priv->status))
  789. iwl_legacy_enable_interrupts(priv);
  790. /* Re-enable RF_KILL if it occurred */
  791. else if (handled & CSR_INT_BIT_RF_KILL)
  792. iwl_legacy_enable_rfkill_int(priv);
  793. #ifdef CONFIG_IWLWIFI_LEGACY_DEBUG
  794. if (iwl_legacy_get_debug_level(priv) & (IWL_DL_ISR)) {
  795. inta = iwl_read32(priv, CSR_INT);
  796. inta_mask = iwl_read32(priv, CSR_INT_MASK);
  797. inta_fh = iwl_read32(priv, CSR_FH_INT_STATUS);
  798. IWL_DEBUG_ISR(priv,
  799. "End inta 0x%08x, enabled 0x%08x, fh 0x%08x, "
  800. "flags 0x%08lx\n", inta, inta_mask, inta_fh, flags);
  801. }
  802. #endif
  803. }
  804. /*****************************************************************************
  805. *
  806. * sysfs attributes
  807. *
  808. *****************************************************************************/
  809. #ifdef CONFIG_IWLWIFI_LEGACY_DEBUG
  810. /*
  811. * The following adds a new attribute to the sysfs representation
  812. * of this device driver (i.e. a new file in /sys/class/net/wlan0/device/)
  813. * used for controlling the debug level.
  814. *
  815. * See the level definitions in iwl for details.
  816. *
  817. * The debug_level being managed using sysfs below is a per device debug
  818. * level that is used instead of the global debug level if it (the per
  819. * device debug level) is set.
  820. */
  821. static ssize_t iwl4965_show_debug_level(struct device *d,
  822. struct device_attribute *attr, char *buf)
  823. {
  824. struct iwl_priv *priv = dev_get_drvdata(d);
  825. return sprintf(buf, "0x%08X\n", iwl_legacy_get_debug_level(priv));
  826. }
  827. static ssize_t iwl4965_store_debug_level(struct device *d,
  828. struct device_attribute *attr,
  829. const char *buf, size_t count)
  830. {
  831. struct iwl_priv *priv = dev_get_drvdata(d);
  832. unsigned long val;
  833. int ret;
  834. ret = strict_strtoul(buf, 0, &val);
  835. if (ret)
  836. IWL_ERR(priv, "%s is not in hex or decimal form.\n", buf);
  837. else {
  838. priv->debug_level = val;
  839. if (iwl_legacy_alloc_traffic_mem(priv))
  840. IWL_ERR(priv,
  841. "Not enough memory to generate traffic log\n");
  842. }
  843. return strnlen(buf, count);
  844. }
  845. static DEVICE_ATTR(debug_level, S_IWUSR | S_IRUGO,
  846. iwl4965_show_debug_level, iwl4965_store_debug_level);
  847. #endif /* CONFIG_IWLWIFI_LEGACY_DEBUG */
  848. static ssize_t iwl4965_show_temperature(struct device *d,
  849. struct device_attribute *attr, char *buf)
  850. {
  851. struct iwl_priv *priv = dev_get_drvdata(d);
  852. if (!iwl_legacy_is_alive(priv))
  853. return -EAGAIN;
  854. return sprintf(buf, "%d\n", priv->temperature);
  855. }
  856. static DEVICE_ATTR(temperature, S_IRUGO, iwl4965_show_temperature, NULL);
  857. static ssize_t iwl4965_show_tx_power(struct device *d,
  858. struct device_attribute *attr, char *buf)
  859. {
  860. struct iwl_priv *priv = dev_get_drvdata(d);
  861. if (!iwl_legacy_is_ready_rf(priv))
  862. return sprintf(buf, "off\n");
  863. else
  864. return sprintf(buf, "%d\n", priv->tx_power_user_lmt);
  865. }
  866. static ssize_t iwl4965_store_tx_power(struct device *d,
  867. struct device_attribute *attr,
  868. const char *buf, size_t count)
  869. {
  870. struct iwl_priv *priv = dev_get_drvdata(d);
  871. unsigned long val;
  872. int ret;
  873. ret = strict_strtoul(buf, 10, &val);
  874. if (ret)
  875. IWL_INFO(priv, "%s is not in decimal form.\n", buf);
  876. else {
  877. ret = iwl_legacy_set_tx_power(priv, val, false);
  878. if (ret)
  879. IWL_ERR(priv, "failed setting tx power (0x%d).\n",
  880. ret);
  881. else
  882. ret = count;
  883. }
  884. return ret;
  885. }
  886. static DEVICE_ATTR(tx_power, S_IWUSR | S_IRUGO,
  887. iwl4965_show_tx_power, iwl4965_store_tx_power);
  888. static struct attribute *iwl_sysfs_entries[] = {
  889. &dev_attr_temperature.attr,
  890. &dev_attr_tx_power.attr,
  891. #ifdef CONFIG_IWLWIFI_LEGACY_DEBUG
  892. &dev_attr_debug_level.attr,
  893. #endif
  894. NULL
  895. };
  896. static struct attribute_group iwl_attribute_group = {
  897. .name = NULL, /* put in device directory */
  898. .attrs = iwl_sysfs_entries,
  899. };
  900. /******************************************************************************
  901. *
  902. * uCode download functions
  903. *
  904. ******************************************************************************/
  905. static void iwl4965_dealloc_ucode_pci(struct iwl_priv *priv)
  906. {
  907. iwl_legacy_free_fw_desc(priv->pci_dev, &priv->ucode_code);
  908. iwl_legacy_free_fw_desc(priv->pci_dev, &priv->ucode_data);
  909. iwl_legacy_free_fw_desc(priv->pci_dev, &priv->ucode_data_backup);
  910. iwl_legacy_free_fw_desc(priv->pci_dev, &priv->ucode_init);
  911. iwl_legacy_free_fw_desc(priv->pci_dev, &priv->ucode_init_data);
  912. iwl_legacy_free_fw_desc(priv->pci_dev, &priv->ucode_boot);
  913. }
  914. static void iwl4965_nic_start(struct iwl_priv *priv)
  915. {
  916. /* Remove all resets to allow NIC to operate */
  917. iwl_write32(priv, CSR_RESET, 0);
  918. }
  919. static void iwl4965_ucode_callback(const struct firmware *ucode_raw,
  920. void *context);
  921. static int iwl4965_mac_setup_register(struct iwl_priv *priv,
  922. u32 max_probe_length);
  923. static int __must_check iwl4965_request_firmware(struct iwl_priv *priv, bool first)
  924. {
  925. const char *name_pre = priv->cfg->fw_name_pre;
  926. char tag[8];
  927. if (first) {
  928. priv->fw_index = priv->cfg->ucode_api_max;
  929. sprintf(tag, "%d", priv->fw_index);
  930. } else {
  931. priv->fw_index--;
  932. sprintf(tag, "%d", priv->fw_index);
  933. }
  934. if (priv->fw_index < priv->cfg->ucode_api_min) {
  935. IWL_ERR(priv, "no suitable firmware found!\n");
  936. return -ENOENT;
  937. }
  938. sprintf(priv->firmware_name, "%s%s%s", name_pre, tag, ".ucode");
  939. IWL_DEBUG_INFO(priv, "attempting to load firmware '%s'\n",
  940. priv->firmware_name);
  941. return request_firmware_nowait(THIS_MODULE, 1, priv->firmware_name,
  942. &priv->pci_dev->dev, GFP_KERNEL, priv,
  943. iwl4965_ucode_callback);
  944. }
  945. struct iwl4965_firmware_pieces {
  946. const void *inst, *data, *init, *init_data, *boot;
  947. size_t inst_size, data_size, init_size, init_data_size, boot_size;
  948. };
  949. static int iwl4965_load_firmware(struct iwl_priv *priv,
  950. const struct firmware *ucode_raw,
  951. struct iwl4965_firmware_pieces *pieces)
  952. {
  953. struct iwl_ucode_header *ucode = (void *)ucode_raw->data;
  954. u32 api_ver, hdr_size;
  955. const u8 *src;
  956. priv->ucode_ver = le32_to_cpu(ucode->ver);
  957. api_ver = IWL_UCODE_API(priv->ucode_ver);
  958. switch (api_ver) {
  959. default:
  960. case 0:
  961. case 1:
  962. case 2:
  963. hdr_size = 24;
  964. if (ucode_raw->size < hdr_size) {
  965. IWL_ERR(priv, "File size too small!\n");
  966. return -EINVAL;
  967. }
  968. pieces->inst_size = le32_to_cpu(ucode->v1.inst_size);
  969. pieces->data_size = le32_to_cpu(ucode->v1.data_size);
  970. pieces->init_size = le32_to_cpu(ucode->v1.init_size);
  971. pieces->init_data_size =
  972. le32_to_cpu(ucode->v1.init_data_size);
  973. pieces->boot_size = le32_to_cpu(ucode->v1.boot_size);
  974. src = ucode->v1.data;
  975. break;
  976. }
  977. /* Verify size of file vs. image size info in file's header */
  978. if (ucode_raw->size != hdr_size + pieces->inst_size +
  979. pieces->data_size + pieces->init_size +
  980. pieces->init_data_size + pieces->boot_size) {
  981. IWL_ERR(priv,
  982. "uCode file size %d does not match expected size\n",
  983. (int)ucode_raw->size);
  984. return -EINVAL;
  985. }
  986. pieces->inst = src;
  987. src += pieces->inst_size;
  988. pieces->data = src;
  989. src += pieces->data_size;
  990. pieces->init = src;
  991. src += pieces->init_size;
  992. pieces->init_data = src;
  993. src += pieces->init_data_size;
  994. pieces->boot = src;
  995. src += pieces->boot_size;
  996. return 0;
  997. }
  998. /**
  999. * iwl4965_ucode_callback - callback when firmware was loaded
  1000. *
  1001. * If loaded successfully, copies the firmware into buffers
  1002. * for the card to fetch (via DMA).
  1003. */
  1004. static void
  1005. iwl4965_ucode_callback(const struct firmware *ucode_raw, void *context)
  1006. {
  1007. struct iwl_priv *priv = context;
  1008. struct iwl_ucode_header *ucode;
  1009. int err;
  1010. struct iwl4965_firmware_pieces pieces;
  1011. const unsigned int api_max = priv->cfg->ucode_api_max;
  1012. const unsigned int api_min = priv->cfg->ucode_api_min;
  1013. u32 api_ver;
  1014. u32 max_probe_length = 200;
  1015. u32 standard_phy_calibration_size =
  1016. IWL_DEFAULT_STANDARD_PHY_CALIBRATE_TBL_SIZE;
  1017. memset(&pieces, 0, sizeof(pieces));
  1018. if (!ucode_raw) {
  1019. if (priv->fw_index <= priv->cfg->ucode_api_max)
  1020. IWL_ERR(priv,
  1021. "request for firmware file '%s' failed.\n",
  1022. priv->firmware_name);
  1023. goto try_again;
  1024. }
  1025. IWL_DEBUG_INFO(priv, "Loaded firmware file '%s' (%zd bytes).\n",
  1026. priv->firmware_name, ucode_raw->size);
  1027. /* Make sure that we got at least the API version number */
  1028. if (ucode_raw->size < 4) {
  1029. IWL_ERR(priv, "File size way too small!\n");
  1030. goto try_again;
  1031. }
  1032. /* Data from ucode file: header followed by uCode images */
  1033. ucode = (struct iwl_ucode_header *)ucode_raw->data;
  1034. err = iwl4965_load_firmware(priv, ucode_raw, &pieces);
  1035. if (err)
  1036. goto try_again;
  1037. api_ver = IWL_UCODE_API(priv->ucode_ver);
  1038. /*
  1039. * api_ver should match the api version forming part of the
  1040. * firmware filename ... but we don't check for that and only rely
  1041. * on the API version read from firmware header from here on forward
  1042. */
  1043. if (api_ver < api_min || api_ver > api_max) {
  1044. IWL_ERR(priv,
  1045. "Driver unable to support your firmware API. "
  1046. "Driver supports v%u, firmware is v%u.\n",
  1047. api_max, api_ver);
  1048. goto try_again;
  1049. }
  1050. if (api_ver != api_max)
  1051. IWL_ERR(priv,
  1052. "Firmware has old API version. Expected v%u, "
  1053. "got v%u. New firmware can be obtained "
  1054. "from http://www.intellinuxwireless.org.\n",
  1055. api_max, api_ver);
  1056. IWL_INFO(priv, "loaded firmware version %u.%u.%u.%u\n",
  1057. IWL_UCODE_MAJOR(priv->ucode_ver),
  1058. IWL_UCODE_MINOR(priv->ucode_ver),
  1059. IWL_UCODE_API(priv->ucode_ver),
  1060. IWL_UCODE_SERIAL(priv->ucode_ver));
  1061. snprintf(priv->hw->wiphy->fw_version,
  1062. sizeof(priv->hw->wiphy->fw_version),
  1063. "%u.%u.%u.%u",
  1064. IWL_UCODE_MAJOR(priv->ucode_ver),
  1065. IWL_UCODE_MINOR(priv->ucode_ver),
  1066. IWL_UCODE_API(priv->ucode_ver),
  1067. IWL_UCODE_SERIAL(priv->ucode_ver));
  1068. /*
  1069. * For any of the failures below (before allocating pci memory)
  1070. * we will try to load a version with a smaller API -- maybe the
  1071. * user just got a corrupted version of the latest API.
  1072. */
  1073. IWL_DEBUG_INFO(priv, "f/w package hdr ucode version raw = 0x%x\n",
  1074. priv->ucode_ver);
  1075. IWL_DEBUG_INFO(priv, "f/w package hdr runtime inst size = %Zd\n",
  1076. pieces.inst_size);
  1077. IWL_DEBUG_INFO(priv, "f/w package hdr runtime data size = %Zd\n",
  1078. pieces.data_size);
  1079. IWL_DEBUG_INFO(priv, "f/w package hdr init inst size = %Zd\n",
  1080. pieces.init_size);
  1081. IWL_DEBUG_INFO(priv, "f/w package hdr init data size = %Zd\n",
  1082. pieces.init_data_size);
  1083. IWL_DEBUG_INFO(priv, "f/w package hdr boot inst size = %Zd\n",
  1084. pieces.boot_size);
  1085. /* Verify that uCode images will fit in card's SRAM */
  1086. if (pieces.inst_size > priv->hw_params.max_inst_size) {
  1087. IWL_ERR(priv, "uCode instr len %Zd too large to fit in\n",
  1088. pieces.inst_size);
  1089. goto try_again;
  1090. }
  1091. if (pieces.data_size > priv->hw_params.max_data_size) {
  1092. IWL_ERR(priv, "uCode data len %Zd too large to fit in\n",
  1093. pieces.data_size);
  1094. goto try_again;
  1095. }
  1096. if (pieces.init_size > priv->hw_params.max_inst_size) {
  1097. IWL_ERR(priv, "uCode init instr len %Zd too large to fit in\n",
  1098. pieces.init_size);
  1099. goto try_again;
  1100. }
  1101. if (pieces.init_data_size > priv->hw_params.max_data_size) {
  1102. IWL_ERR(priv, "uCode init data len %Zd too large to fit in\n",
  1103. pieces.init_data_size);
  1104. goto try_again;
  1105. }
  1106. if (pieces.boot_size > priv->hw_params.max_bsm_size) {
  1107. IWL_ERR(priv, "uCode boot instr len %Zd too large to fit in\n",
  1108. pieces.boot_size);
  1109. goto try_again;
  1110. }
  1111. /* Allocate ucode buffers for card's bus-master loading ... */
  1112. /* Runtime instructions and 2 copies of data:
  1113. * 1) unmodified from disk
  1114. * 2) backup cache for save/restore during power-downs */
  1115. priv->ucode_code.len = pieces.inst_size;
  1116. iwl_legacy_alloc_fw_desc(priv->pci_dev, &priv->ucode_code);
  1117. priv->ucode_data.len = pieces.data_size;
  1118. iwl_legacy_alloc_fw_desc(priv->pci_dev, &priv->ucode_data);
  1119. priv->ucode_data_backup.len = pieces.data_size;
  1120. iwl_legacy_alloc_fw_desc(priv->pci_dev, &priv->ucode_data_backup);
  1121. if (!priv->ucode_code.v_addr || !priv->ucode_data.v_addr ||
  1122. !priv->ucode_data_backup.v_addr)
  1123. goto err_pci_alloc;
  1124. /* Initialization instructions and data */
  1125. if (pieces.init_size && pieces.init_data_size) {
  1126. priv->ucode_init.len = pieces.init_size;
  1127. iwl_legacy_alloc_fw_desc(priv->pci_dev, &priv->ucode_init);
  1128. priv->ucode_init_data.len = pieces.init_data_size;
  1129. iwl_legacy_alloc_fw_desc(priv->pci_dev, &priv->ucode_init_data);
  1130. if (!priv->ucode_init.v_addr || !priv->ucode_init_data.v_addr)
  1131. goto err_pci_alloc;
  1132. }
  1133. /* Bootstrap (instructions only, no data) */
  1134. if (pieces.boot_size) {
  1135. priv->ucode_boot.len = pieces.boot_size;
  1136. iwl_legacy_alloc_fw_desc(priv->pci_dev, &priv->ucode_boot);
  1137. if (!priv->ucode_boot.v_addr)
  1138. goto err_pci_alloc;
  1139. }
  1140. /* Now that we can no longer fail, copy information */
  1141. priv->sta_key_max_num = STA_KEY_MAX_NUM;
  1142. /* Copy images into buffers for card's bus-master reads ... */
  1143. /* Runtime instructions (first block of data in file) */
  1144. IWL_DEBUG_INFO(priv, "Copying (but not loading) uCode instr len %Zd\n",
  1145. pieces.inst_size);
  1146. memcpy(priv->ucode_code.v_addr, pieces.inst, pieces.inst_size);
  1147. IWL_DEBUG_INFO(priv, "uCode instr buf vaddr = 0x%p, paddr = 0x%08x\n",
  1148. priv->ucode_code.v_addr, (u32)priv->ucode_code.p_addr);
  1149. /*
  1150. * Runtime data
  1151. * NOTE: Copy into backup buffer will be done in iwl_up()
  1152. */
  1153. IWL_DEBUG_INFO(priv, "Copying (but not loading) uCode data len %Zd\n",
  1154. pieces.data_size);
  1155. memcpy(priv->ucode_data.v_addr, pieces.data, pieces.data_size);
  1156. memcpy(priv->ucode_data_backup.v_addr, pieces.data, pieces.data_size);
  1157. /* Initialization instructions */
  1158. if (pieces.init_size) {
  1159. IWL_DEBUG_INFO(priv,
  1160. "Copying (but not loading) init instr len %Zd\n",
  1161. pieces.init_size);
  1162. memcpy(priv->ucode_init.v_addr, pieces.init, pieces.init_size);
  1163. }
  1164. /* Initialization data */
  1165. if (pieces.init_data_size) {
  1166. IWL_DEBUG_INFO(priv,
  1167. "Copying (but not loading) init data len %Zd\n",
  1168. pieces.init_data_size);
  1169. memcpy(priv->ucode_init_data.v_addr, pieces.init_data,
  1170. pieces.init_data_size);
  1171. }
  1172. /* Bootstrap instructions */
  1173. IWL_DEBUG_INFO(priv, "Copying (but not loading) boot instr len %Zd\n",
  1174. pieces.boot_size);
  1175. memcpy(priv->ucode_boot.v_addr, pieces.boot, pieces.boot_size);
  1176. /*
  1177. * figure out the offset of chain noise reset and gain commands
  1178. * base on the size of standard phy calibration commands table size
  1179. */
  1180. priv->_4965.phy_calib_chain_noise_reset_cmd =
  1181. standard_phy_calibration_size;
  1182. priv->_4965.phy_calib_chain_noise_gain_cmd =
  1183. standard_phy_calibration_size + 1;
  1184. /**************************************************
  1185. * This is still part of probe() in a sense...
  1186. *
  1187. * 9. Setup and register with mac80211 and debugfs
  1188. **************************************************/
  1189. err = iwl4965_mac_setup_register(priv, max_probe_length);
  1190. if (err)
  1191. goto out_unbind;
  1192. err = iwl_legacy_dbgfs_register(priv, DRV_NAME);
  1193. if (err)
  1194. IWL_ERR(priv,
  1195. "failed to create debugfs files. Ignoring error: %d\n", err);
  1196. err = sysfs_create_group(&priv->pci_dev->dev.kobj,
  1197. &iwl_attribute_group);
  1198. if (err) {
  1199. IWL_ERR(priv, "failed to create sysfs device attributes\n");
  1200. goto out_unbind;
  1201. }
  1202. /* We have our copies now, allow OS release its copies */
  1203. release_firmware(ucode_raw);
  1204. complete(&priv->_4965.firmware_loading_complete);
  1205. return;
  1206. try_again:
  1207. /* try next, if any */
  1208. if (iwl4965_request_firmware(priv, false))
  1209. goto out_unbind;
  1210. release_firmware(ucode_raw);
  1211. return;
  1212. err_pci_alloc:
  1213. IWL_ERR(priv, "failed to allocate pci memory\n");
  1214. iwl4965_dealloc_ucode_pci(priv);
  1215. out_unbind:
  1216. complete(&priv->_4965.firmware_loading_complete);
  1217. device_release_driver(&priv->pci_dev->dev);
  1218. release_firmware(ucode_raw);
  1219. }
  1220. static const char * const desc_lookup_text[] = {
  1221. "OK",
  1222. "FAIL",
  1223. "BAD_PARAM",
  1224. "BAD_CHECKSUM",
  1225. "NMI_INTERRUPT_WDG",
  1226. "SYSASSERT",
  1227. "FATAL_ERROR",
  1228. "BAD_COMMAND",
  1229. "HW_ERROR_TUNE_LOCK",
  1230. "HW_ERROR_TEMPERATURE",
  1231. "ILLEGAL_CHAN_FREQ",
  1232. "VCC_NOT_STABLE",
  1233. "FH_ERROR",
  1234. "NMI_INTERRUPT_HOST",
  1235. "NMI_INTERRUPT_ACTION_PT",
  1236. "NMI_INTERRUPT_UNKNOWN",
  1237. "UCODE_VERSION_MISMATCH",
  1238. "HW_ERROR_ABS_LOCK",
  1239. "HW_ERROR_CAL_LOCK_FAIL",
  1240. "NMI_INTERRUPT_INST_ACTION_PT",
  1241. "NMI_INTERRUPT_DATA_ACTION_PT",
  1242. "NMI_TRM_HW_ER",
  1243. "NMI_INTERRUPT_TRM",
  1244. "NMI_INTERRUPT_BREAK_POINT",
  1245. "DEBUG_0",
  1246. "DEBUG_1",
  1247. "DEBUG_2",
  1248. "DEBUG_3",
  1249. };
  1250. static struct { char *name; u8 num; } advanced_lookup[] = {
  1251. { "NMI_INTERRUPT_WDG", 0x34 },
  1252. { "SYSASSERT", 0x35 },
  1253. { "UCODE_VERSION_MISMATCH", 0x37 },
  1254. { "BAD_COMMAND", 0x38 },
  1255. { "NMI_INTERRUPT_DATA_ACTION_PT", 0x3C },
  1256. { "FATAL_ERROR", 0x3D },
  1257. { "NMI_TRM_HW_ERR", 0x46 },
  1258. { "NMI_INTERRUPT_TRM", 0x4C },
  1259. { "NMI_INTERRUPT_BREAK_POINT", 0x54 },
  1260. { "NMI_INTERRUPT_WDG_RXF_FULL", 0x5C },
  1261. { "NMI_INTERRUPT_WDG_NO_RBD_RXF_FULL", 0x64 },
  1262. { "NMI_INTERRUPT_HOST", 0x66 },
  1263. { "NMI_INTERRUPT_ACTION_PT", 0x7C },
  1264. { "NMI_INTERRUPT_UNKNOWN", 0x84 },
  1265. { "NMI_INTERRUPT_INST_ACTION_PT", 0x86 },
  1266. { "ADVANCED_SYSASSERT", 0 },
  1267. };
  1268. static const char *iwl4965_desc_lookup(u32 num)
  1269. {
  1270. int i;
  1271. int max = ARRAY_SIZE(desc_lookup_text);
  1272. if (num < max)
  1273. return desc_lookup_text[num];
  1274. max = ARRAY_SIZE(advanced_lookup) - 1;
  1275. for (i = 0; i < max; i++) {
  1276. if (advanced_lookup[i].num == num)
  1277. break;
  1278. }
  1279. return advanced_lookup[i].name;
  1280. }
  1281. #define ERROR_START_OFFSET (1 * sizeof(u32))
  1282. #define ERROR_ELEM_SIZE (7 * sizeof(u32))
  1283. void iwl4965_dump_nic_error_log(struct iwl_priv *priv)
  1284. {
  1285. u32 data2, line;
  1286. u32 desc, time, count, base, data1;
  1287. u32 blink1, blink2, ilink1, ilink2;
  1288. u32 pc, hcmd;
  1289. if (priv->ucode_type == UCODE_INIT) {
  1290. base = le32_to_cpu(priv->card_alive_init.error_event_table_ptr);
  1291. } else {
  1292. base = le32_to_cpu(priv->card_alive.error_event_table_ptr);
  1293. }
  1294. if (!priv->cfg->ops->lib->is_valid_rtc_data_addr(base)) {
  1295. IWL_ERR(priv,
  1296. "Not valid error log pointer 0x%08X for %s uCode\n",
  1297. base, (priv->ucode_type == UCODE_INIT) ? "Init" : "RT");
  1298. return;
  1299. }
  1300. count = iwl_legacy_read_targ_mem(priv, base);
  1301. if (ERROR_START_OFFSET <= count * ERROR_ELEM_SIZE) {
  1302. IWL_ERR(priv, "Start IWL Error Log Dump:\n");
  1303. IWL_ERR(priv, "Status: 0x%08lX, count: %d\n",
  1304. priv->status, count);
  1305. }
  1306. desc = iwl_legacy_read_targ_mem(priv, base + 1 * sizeof(u32));
  1307. priv->isr_stats.err_code = desc;
  1308. pc = iwl_legacy_read_targ_mem(priv, base + 2 * sizeof(u32));
  1309. blink1 = iwl_legacy_read_targ_mem(priv, base + 3 * sizeof(u32));
  1310. blink2 = iwl_legacy_read_targ_mem(priv, base + 4 * sizeof(u32));
  1311. ilink1 = iwl_legacy_read_targ_mem(priv, base + 5 * sizeof(u32));
  1312. ilink2 = iwl_legacy_read_targ_mem(priv, base + 6 * sizeof(u32));
  1313. data1 = iwl_legacy_read_targ_mem(priv, base + 7 * sizeof(u32));
  1314. data2 = iwl_legacy_read_targ_mem(priv, base + 8 * sizeof(u32));
  1315. line = iwl_legacy_read_targ_mem(priv, base + 9 * sizeof(u32));
  1316. time = iwl_legacy_read_targ_mem(priv, base + 11 * sizeof(u32));
  1317. hcmd = iwl_legacy_read_targ_mem(priv, base + 22 * sizeof(u32));
  1318. trace_iwlwifi_legacy_dev_ucode_error(priv, desc,
  1319. time, data1, data2, line,
  1320. blink1, blink2, ilink1, ilink2);
  1321. IWL_ERR(priv, "Desc Time "
  1322. "data1 data2 line\n");
  1323. IWL_ERR(priv, "%-28s (0x%04X) %010u 0x%08X 0x%08X %u\n",
  1324. iwl4965_desc_lookup(desc), desc, time, data1, data2, line);
  1325. IWL_ERR(priv, "pc blink1 blink2 ilink1 ilink2 hcmd\n");
  1326. IWL_ERR(priv, "0x%05X 0x%05X 0x%05X 0x%05X 0x%05X 0x%05X\n",
  1327. pc, blink1, blink2, ilink1, ilink2, hcmd);
  1328. }
  1329. static void iwl4965_rf_kill_ct_config(struct iwl_priv *priv)
  1330. {
  1331. struct iwl_ct_kill_config cmd;
  1332. unsigned long flags;
  1333. int ret = 0;
  1334. spin_lock_irqsave(&priv->lock, flags);
  1335. iwl_write32(priv, CSR_UCODE_DRV_GP1_CLR,
  1336. CSR_UCODE_DRV_GP1_REG_BIT_CT_KILL_EXIT);
  1337. spin_unlock_irqrestore(&priv->lock, flags);
  1338. cmd.critical_temperature_R =
  1339. cpu_to_le32(priv->hw_params.ct_kill_threshold);
  1340. ret = iwl_legacy_send_cmd_pdu(priv, REPLY_CT_KILL_CONFIG_CMD,
  1341. sizeof(cmd), &cmd);
  1342. if (ret)
  1343. IWL_ERR(priv, "REPLY_CT_KILL_CONFIG_CMD failed\n");
  1344. else
  1345. IWL_DEBUG_INFO(priv, "REPLY_CT_KILL_CONFIG_CMD "
  1346. "succeeded, "
  1347. "critical temperature is %d\n",
  1348. priv->hw_params.ct_kill_threshold);
  1349. }
  1350. static const s8 default_queue_to_tx_fifo[] = {
  1351. IWL_TX_FIFO_VO,
  1352. IWL_TX_FIFO_VI,
  1353. IWL_TX_FIFO_BE,
  1354. IWL_TX_FIFO_BK,
  1355. IWL49_CMD_FIFO_NUM,
  1356. IWL_TX_FIFO_UNUSED,
  1357. IWL_TX_FIFO_UNUSED,
  1358. };
  1359. static int iwl4965_alive_notify(struct iwl_priv *priv)
  1360. {
  1361. u32 a;
  1362. unsigned long flags;
  1363. int i, chan;
  1364. u32 reg_val;
  1365. spin_lock_irqsave(&priv->lock, flags);
  1366. /* Clear 4965's internal Tx Scheduler data base */
  1367. priv->scd_base_addr = iwl_legacy_read_prph(priv,
  1368. IWL49_SCD_SRAM_BASE_ADDR);
  1369. a = priv->scd_base_addr + IWL49_SCD_CONTEXT_DATA_OFFSET;
  1370. for (; a < priv->scd_base_addr + IWL49_SCD_TX_STTS_BITMAP_OFFSET; a += 4)
  1371. iwl_legacy_write_targ_mem(priv, a, 0);
  1372. for (; a < priv->scd_base_addr + IWL49_SCD_TRANSLATE_TBL_OFFSET; a += 4)
  1373. iwl_legacy_write_targ_mem(priv, a, 0);
  1374. for (; a < priv->scd_base_addr +
  1375. IWL49_SCD_TRANSLATE_TBL_OFFSET_QUEUE(priv->hw_params.max_txq_num); a += 4)
  1376. iwl_legacy_write_targ_mem(priv, a, 0);
  1377. /* Tel 4965 where to find Tx byte count tables */
  1378. iwl_legacy_write_prph(priv, IWL49_SCD_DRAM_BASE_ADDR,
  1379. priv->scd_bc_tbls.dma >> 10);
  1380. /* Enable DMA channel */
  1381. for (chan = 0; chan < FH49_TCSR_CHNL_NUM ; chan++)
  1382. iwl_legacy_write_direct32(priv,
  1383. FH_TCSR_CHNL_TX_CONFIG_REG(chan),
  1384. FH_TCSR_TX_CONFIG_REG_VAL_DMA_CHNL_ENABLE |
  1385. FH_TCSR_TX_CONFIG_REG_VAL_DMA_CREDIT_ENABLE);
  1386. /* Update FH chicken bits */
  1387. reg_val = iwl_legacy_read_direct32(priv, FH_TX_CHICKEN_BITS_REG);
  1388. iwl_legacy_write_direct32(priv, FH_TX_CHICKEN_BITS_REG,
  1389. reg_val | FH_TX_CHICKEN_BITS_SCD_AUTO_RETRY_EN);
  1390. /* Disable chain mode for all queues */
  1391. iwl_legacy_write_prph(priv, IWL49_SCD_QUEUECHAIN_SEL, 0);
  1392. /* Initialize each Tx queue (including the command queue) */
  1393. for (i = 0; i < priv->hw_params.max_txq_num; i++) {
  1394. /* TFD circular buffer read/write indexes */
  1395. iwl_legacy_write_prph(priv, IWL49_SCD_QUEUE_RDPTR(i), 0);
  1396. iwl_legacy_write_direct32(priv, HBUS_TARG_WRPTR, 0 | (i << 8));
  1397. /* Max Tx Window size for Scheduler-ACK mode */
  1398. iwl_legacy_write_targ_mem(priv, priv->scd_base_addr +
  1399. IWL49_SCD_CONTEXT_QUEUE_OFFSET(i),
  1400. (SCD_WIN_SIZE <<
  1401. IWL49_SCD_QUEUE_CTX_REG1_WIN_SIZE_POS) &
  1402. IWL49_SCD_QUEUE_CTX_REG1_WIN_SIZE_MSK);
  1403. /* Frame limit */
  1404. iwl_legacy_write_targ_mem(priv, priv->scd_base_addr +
  1405. IWL49_SCD_CONTEXT_QUEUE_OFFSET(i) +
  1406. sizeof(u32),
  1407. (SCD_FRAME_LIMIT <<
  1408. IWL49_SCD_QUEUE_CTX_REG2_FRAME_LIMIT_POS) &
  1409. IWL49_SCD_QUEUE_CTX_REG2_FRAME_LIMIT_MSK);
  1410. }
  1411. iwl_legacy_write_prph(priv, IWL49_SCD_INTERRUPT_MASK,
  1412. (1 << priv->hw_params.max_txq_num) - 1);
  1413. /* Activate all Tx DMA/FIFO channels */
  1414. iwl4965_txq_set_sched(priv, IWL_MASK(0, 6));
  1415. iwl4965_set_wr_ptrs(priv, IWL_DEFAULT_CMD_QUEUE_NUM, 0);
  1416. /* make sure all queue are not stopped */
  1417. memset(&priv->queue_stopped[0], 0, sizeof(priv->queue_stopped));
  1418. for (i = 0; i < 4; i++)
  1419. atomic_set(&priv->queue_stop_count[i], 0);
  1420. /* reset to 0 to enable all the queue first */
  1421. priv->txq_ctx_active_msk = 0;
  1422. /* Map each Tx/cmd queue to its corresponding fifo */
  1423. BUILD_BUG_ON(ARRAY_SIZE(default_queue_to_tx_fifo) != 7);
  1424. for (i = 0; i < ARRAY_SIZE(default_queue_to_tx_fifo); i++) {
  1425. int ac = default_queue_to_tx_fifo[i];
  1426. iwl_txq_ctx_activate(priv, i);
  1427. if (ac == IWL_TX_FIFO_UNUSED)
  1428. continue;
  1429. iwl4965_tx_queue_set_status(priv, &priv->txq[i], ac, 0);
  1430. }
  1431. spin_unlock_irqrestore(&priv->lock, flags);
  1432. return 0;
  1433. }
  1434. /**
  1435. * iwl4965_alive_start - called after REPLY_ALIVE notification received
  1436. * from protocol/runtime uCode (initialization uCode's
  1437. * Alive gets handled by iwl_init_alive_start()).
  1438. */
  1439. static void iwl4965_alive_start(struct iwl_priv *priv)
  1440. {
  1441. int ret = 0;
  1442. struct iwl_rxon_context *ctx = &priv->contexts[IWL_RXON_CTX_BSS];
  1443. IWL_DEBUG_INFO(priv, "Runtime Alive received.\n");
  1444. if (priv->card_alive.is_valid != UCODE_VALID_OK) {
  1445. /* We had an error bringing up the hardware, so take it
  1446. * all the way back down so we can try again */
  1447. IWL_DEBUG_INFO(priv, "Alive failed.\n");
  1448. goto restart;
  1449. }
  1450. /* Initialize uCode has loaded Runtime uCode ... verify inst image.
  1451. * This is a paranoid check, because we would not have gotten the
  1452. * "runtime" alive if code weren't properly loaded. */
  1453. if (iwl4965_verify_ucode(priv)) {
  1454. /* Runtime instruction load was bad;
  1455. * take it all the way back down so we can try again */
  1456. IWL_DEBUG_INFO(priv, "Bad runtime uCode load.\n");
  1457. goto restart;
  1458. }
  1459. ret = iwl4965_alive_notify(priv);
  1460. if (ret) {
  1461. IWL_WARN(priv,
  1462. "Could not complete ALIVE transition [ntf]: %d\n", ret);
  1463. goto restart;
  1464. }
  1465. /* After the ALIVE response, we can send host commands to the uCode */
  1466. set_bit(STATUS_ALIVE, &priv->status);
  1467. /* Enable watchdog to monitor the driver tx queues */
  1468. iwl_legacy_setup_watchdog(priv);
  1469. if (iwl_legacy_is_rfkill(priv))
  1470. return;
  1471. ieee80211_wake_queues(priv->hw);
  1472. priv->active_rate = IWL_RATES_MASK;
  1473. if (iwl_legacy_is_associated_ctx(ctx)) {
  1474. struct iwl_legacy_rxon_cmd *active_rxon =
  1475. (struct iwl_legacy_rxon_cmd *)&ctx->active;
  1476. /* apply any changes in staging */
  1477. ctx->staging.filter_flags |= RXON_FILTER_ASSOC_MSK;
  1478. active_rxon->filter_flags &= ~RXON_FILTER_ASSOC_MSK;
  1479. } else {
  1480. struct iwl_rxon_context *tmp;
  1481. /* Initialize our rx_config data */
  1482. for_each_context(priv, tmp)
  1483. iwl_legacy_connection_init_rx_config(priv, tmp);
  1484. if (priv->cfg->ops->hcmd->set_rxon_chain)
  1485. priv->cfg->ops->hcmd->set_rxon_chain(priv, ctx);
  1486. }
  1487. /* Configure bluetooth coexistence if enabled */
  1488. iwl_legacy_send_bt_config(priv);
  1489. iwl4965_reset_run_time_calib(priv);
  1490. set_bit(STATUS_READY, &priv->status);
  1491. /* Configure the adapter for unassociated operation */
  1492. iwl_legacy_commit_rxon(priv, ctx);
  1493. /* At this point, the NIC is initialized and operational */
  1494. iwl4965_rf_kill_ct_config(priv);
  1495. IWL_DEBUG_INFO(priv, "ALIVE processing complete.\n");
  1496. wake_up(&priv->wait_command_queue);
  1497. iwl_legacy_power_update_mode(priv, true);
  1498. IWL_DEBUG_INFO(priv, "Updated power mode\n");
  1499. return;
  1500. restart:
  1501. queue_work(priv->workqueue, &priv->restart);
  1502. }
  1503. static void iwl4965_cancel_deferred_work(struct iwl_priv *priv);
  1504. static void __iwl4965_down(struct iwl_priv *priv)
  1505. {
  1506. unsigned long flags;
  1507. int exit_pending;
  1508. IWL_DEBUG_INFO(priv, DRV_NAME " is going down\n");
  1509. iwl_legacy_scan_cancel_timeout(priv, 200);
  1510. exit_pending = test_and_set_bit(STATUS_EXIT_PENDING, &priv->status);
  1511. /* Stop TX queues watchdog. We need to have STATUS_EXIT_PENDING bit set
  1512. * to prevent rearm timer */
  1513. del_timer_sync(&priv->watchdog);
  1514. iwl_legacy_clear_ucode_stations(priv, NULL);
  1515. iwl_legacy_dealloc_bcast_stations(priv);
  1516. iwl_legacy_clear_driver_stations(priv);
  1517. /* Unblock any waiting calls */
  1518. wake_up_all(&priv->wait_command_queue);
  1519. /* Wipe out the EXIT_PENDING status bit if we are not actually
  1520. * exiting the module */
  1521. if (!exit_pending)
  1522. clear_bit(STATUS_EXIT_PENDING, &priv->status);
  1523. /* stop and reset the on-board processor */
  1524. iwl_write32(priv, CSR_RESET, CSR_RESET_REG_FLAG_NEVO_RESET);
  1525. /* tell the device to stop sending interrupts */
  1526. spin_lock_irqsave(&priv->lock, flags);
  1527. iwl_legacy_disable_interrupts(priv);
  1528. spin_unlock_irqrestore(&priv->lock, flags);
  1529. iwl4965_synchronize_irq(priv);
  1530. if (priv->mac80211_registered)
  1531. ieee80211_stop_queues(priv->hw);
  1532. /* If we have not previously called iwl_init() then
  1533. * clear all bits but the RF Kill bit and return */
  1534. if (!iwl_legacy_is_init(priv)) {
  1535. priv->status = test_bit(STATUS_RF_KILL_HW, &priv->status) <<
  1536. STATUS_RF_KILL_HW |
  1537. test_bit(STATUS_GEO_CONFIGURED, &priv->status) <<
  1538. STATUS_GEO_CONFIGURED |
  1539. test_bit(STATUS_EXIT_PENDING, &priv->status) <<
  1540. STATUS_EXIT_PENDING;
  1541. goto exit;
  1542. }
  1543. /* ...otherwise clear out all the status bits but the RF Kill
  1544. * bit and continue taking the NIC down. */
  1545. priv->status &= test_bit(STATUS_RF_KILL_HW, &priv->status) <<
  1546. STATUS_RF_KILL_HW |
  1547. test_bit(STATUS_GEO_CONFIGURED, &priv->status) <<
  1548. STATUS_GEO_CONFIGURED |
  1549. test_bit(STATUS_FW_ERROR, &priv->status) <<
  1550. STATUS_FW_ERROR |
  1551. test_bit(STATUS_EXIT_PENDING, &priv->status) <<
  1552. STATUS_EXIT_PENDING;
  1553. iwl4965_txq_ctx_stop(priv);
  1554. iwl4965_rxq_stop(priv);
  1555. /* Power-down device's busmaster DMA clocks */
  1556. iwl_legacy_write_prph(priv, APMG_CLK_DIS_REG, APMG_CLK_VAL_DMA_CLK_RQT);
  1557. udelay(5);
  1558. /* Make sure (redundant) we've released our request to stay awake */
  1559. iwl_legacy_clear_bit(priv, CSR_GP_CNTRL,
  1560. CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ);
  1561. /* Stop the device, and put it in low power state */
  1562. iwl_legacy_apm_stop(priv);
  1563. exit:
  1564. memset(&priv->card_alive, 0, sizeof(struct iwl_alive_resp));
  1565. dev_kfree_skb(priv->beacon_skb);
  1566. priv->beacon_skb = NULL;
  1567. /* clear out any free frames */
  1568. iwl4965_clear_free_frames(priv);
  1569. }
  1570. static void iwl4965_down(struct iwl_priv *priv)
  1571. {
  1572. mutex_lock(&priv->mutex);
  1573. __iwl4965_down(priv);
  1574. mutex_unlock(&priv->mutex);
  1575. iwl4965_cancel_deferred_work(priv);
  1576. }
  1577. #define HW_READY_TIMEOUT (50)
  1578. static int iwl4965_set_hw_ready(struct iwl_priv *priv)
  1579. {
  1580. int ret = 0;
  1581. iwl_legacy_set_bit(priv, CSR_HW_IF_CONFIG_REG,
  1582. CSR_HW_IF_CONFIG_REG_BIT_NIC_READY);
  1583. /* See if we got it */
  1584. ret = iwl_poll_bit(priv, CSR_HW_IF_CONFIG_REG,
  1585. CSR_HW_IF_CONFIG_REG_BIT_NIC_READY,
  1586. CSR_HW_IF_CONFIG_REG_BIT_NIC_READY,
  1587. HW_READY_TIMEOUT);
  1588. if (ret != -ETIMEDOUT)
  1589. priv->hw_ready = true;
  1590. else
  1591. priv->hw_ready = false;
  1592. IWL_DEBUG_INFO(priv, "hardware %s\n",
  1593. (priv->hw_ready == 1) ? "ready" : "not ready");
  1594. return ret;
  1595. }
  1596. static int iwl4965_prepare_card_hw(struct iwl_priv *priv)
  1597. {
  1598. int ret = 0;
  1599. IWL_DEBUG_INFO(priv, "iwl4965_prepare_card_hw enter\n");
  1600. ret = iwl4965_set_hw_ready(priv);
  1601. if (priv->hw_ready)
  1602. return ret;
  1603. /* If HW is not ready, prepare the conditions to check again */
  1604. iwl_legacy_set_bit(priv, CSR_HW_IF_CONFIG_REG,
  1605. CSR_HW_IF_CONFIG_REG_PREPARE);
  1606. ret = iwl_poll_bit(priv, CSR_HW_IF_CONFIG_REG,
  1607. ~CSR_HW_IF_CONFIG_REG_BIT_NIC_PREPARE_DONE,
  1608. CSR_HW_IF_CONFIG_REG_BIT_NIC_PREPARE_DONE, 150000);
  1609. /* HW should be ready by now, check again. */
  1610. if (ret != -ETIMEDOUT)
  1611. iwl4965_set_hw_ready(priv);
  1612. return ret;
  1613. }
  1614. #define MAX_HW_RESTARTS 5
  1615. static int __iwl4965_up(struct iwl_priv *priv)
  1616. {
  1617. struct iwl_rxon_context *ctx;
  1618. int i;
  1619. int ret;
  1620. if (test_bit(STATUS_EXIT_PENDING, &priv->status)) {
  1621. IWL_WARN(priv, "Exit pending; will not bring the NIC up\n");
  1622. return -EIO;
  1623. }
  1624. if (!priv->ucode_data_backup.v_addr || !priv->ucode_data.v_addr) {
  1625. IWL_ERR(priv, "ucode not available for device bringup\n");
  1626. return -EIO;
  1627. }
  1628. for_each_context(priv, ctx) {
  1629. ret = iwl4965_alloc_bcast_station(priv, ctx);
  1630. if (ret) {
  1631. iwl_legacy_dealloc_bcast_stations(priv);
  1632. return ret;
  1633. }
  1634. }
  1635. iwl4965_prepare_card_hw(priv);
  1636. if (!priv->hw_ready) {
  1637. IWL_WARN(priv, "Exit HW not ready\n");
  1638. return -EIO;
  1639. }
  1640. /* If platform's RF_KILL switch is NOT set to KILL */
  1641. if (iwl_read32(priv,
  1642. CSR_GP_CNTRL) & CSR_GP_CNTRL_REG_FLAG_HW_RF_KILL_SW)
  1643. clear_bit(STATUS_RF_KILL_HW, &priv->status);
  1644. else
  1645. set_bit(STATUS_RF_KILL_HW, &priv->status);
  1646. if (iwl_legacy_is_rfkill(priv)) {
  1647. wiphy_rfkill_set_hw_state(priv->hw->wiphy, true);
  1648. iwl_legacy_enable_interrupts(priv);
  1649. IWL_WARN(priv, "Radio disabled by HW RF Kill switch\n");
  1650. return 0;
  1651. }
  1652. iwl_write32(priv, CSR_INT, 0xFFFFFFFF);
  1653. /* must be initialised before iwl_hw_nic_init */
  1654. priv->cmd_queue = IWL_DEFAULT_CMD_QUEUE_NUM;
  1655. ret = iwl4965_hw_nic_init(priv);
  1656. if (ret) {
  1657. IWL_ERR(priv, "Unable to init nic\n");
  1658. return ret;
  1659. }
  1660. /* make sure rfkill handshake bits are cleared */
  1661. iwl_write32(priv, CSR_UCODE_DRV_GP1_CLR, CSR_UCODE_SW_BIT_RFKILL);
  1662. iwl_write32(priv, CSR_UCODE_DRV_GP1_CLR,
  1663. CSR_UCODE_DRV_GP1_BIT_CMD_BLOCKED);
  1664. /* clear (again), then enable host interrupts */
  1665. iwl_write32(priv, CSR_INT, 0xFFFFFFFF);
  1666. iwl_legacy_enable_interrupts(priv);
  1667. /* really make sure rfkill handshake bits are cleared */
  1668. iwl_write32(priv, CSR_UCODE_DRV_GP1_CLR, CSR_UCODE_SW_BIT_RFKILL);
  1669. iwl_write32(priv, CSR_UCODE_DRV_GP1_CLR, CSR_UCODE_SW_BIT_RFKILL);
  1670. /* Copy original ucode data image from disk into backup cache.
  1671. * This will be used to initialize the on-board processor's
  1672. * data SRAM for a clean start when the runtime program first loads. */
  1673. memcpy(priv->ucode_data_backup.v_addr, priv->ucode_data.v_addr,
  1674. priv->ucode_data.len);
  1675. for (i = 0; i < MAX_HW_RESTARTS; i++) {
  1676. /* load bootstrap state machine,
  1677. * load bootstrap program into processor's memory,
  1678. * prepare to load the "initialize" uCode */
  1679. ret = priv->cfg->ops->lib->load_ucode(priv);
  1680. if (ret) {
  1681. IWL_ERR(priv, "Unable to set up bootstrap uCode: %d\n",
  1682. ret);
  1683. continue;
  1684. }
  1685. /* start card; "initialize" will load runtime ucode */
  1686. iwl4965_nic_start(priv);
  1687. IWL_DEBUG_INFO(priv, DRV_NAME " is coming up\n");
  1688. return 0;
  1689. }
  1690. set_bit(STATUS_EXIT_PENDING, &priv->status);
  1691. __iwl4965_down(priv);
  1692. clear_bit(STATUS_EXIT_PENDING, &priv->status);
  1693. /* tried to restart and config the device for as long as our
  1694. * patience could withstand */
  1695. IWL_ERR(priv, "Unable to initialize device after %d attempts.\n", i);
  1696. return -EIO;
  1697. }
  1698. /*****************************************************************************
  1699. *
  1700. * Workqueue callbacks
  1701. *
  1702. *****************************************************************************/
  1703. static void iwl4965_bg_init_alive_start(struct work_struct *data)
  1704. {
  1705. struct iwl_priv *priv =
  1706. container_of(data, struct iwl_priv, init_alive_start.work);
  1707. mutex_lock(&priv->mutex);
  1708. if (test_bit(STATUS_EXIT_PENDING, &priv->status))
  1709. goto out;
  1710. priv->cfg->ops->lib->init_alive_start(priv);
  1711. out:
  1712. mutex_unlock(&priv->mutex);
  1713. }
  1714. static void iwl4965_bg_alive_start(struct work_struct *data)
  1715. {
  1716. struct iwl_priv *priv =
  1717. container_of(data, struct iwl_priv, alive_start.work);
  1718. mutex_lock(&priv->mutex);
  1719. if (test_bit(STATUS_EXIT_PENDING, &priv->status))
  1720. goto out;
  1721. iwl4965_alive_start(priv);
  1722. out:
  1723. mutex_unlock(&priv->mutex);
  1724. }
  1725. static void iwl4965_bg_run_time_calib_work(struct work_struct *work)
  1726. {
  1727. struct iwl_priv *priv = container_of(work, struct iwl_priv,
  1728. run_time_calib_work);
  1729. mutex_lock(&priv->mutex);
  1730. if (test_bit(STATUS_EXIT_PENDING, &priv->status) ||
  1731. test_bit(STATUS_SCANNING, &priv->status)) {
  1732. mutex_unlock(&priv->mutex);
  1733. return;
  1734. }
  1735. if (priv->start_calib) {
  1736. iwl4965_chain_noise_calibration(priv,
  1737. (void *)&priv->_4965.statistics);
  1738. iwl4965_sensitivity_calibration(priv,
  1739. (void *)&priv->_4965.statistics);
  1740. }
  1741. mutex_unlock(&priv->mutex);
  1742. }
  1743. static void iwl4965_bg_restart(struct work_struct *data)
  1744. {
  1745. struct iwl_priv *priv = container_of(data, struct iwl_priv, restart);
  1746. if (test_bit(STATUS_EXIT_PENDING, &priv->status))
  1747. return;
  1748. if (test_and_clear_bit(STATUS_FW_ERROR, &priv->status)) {
  1749. struct iwl_rxon_context *ctx;
  1750. mutex_lock(&priv->mutex);
  1751. for_each_context(priv, ctx)
  1752. ctx->vif = NULL;
  1753. priv->is_open = 0;
  1754. __iwl4965_down(priv);
  1755. mutex_unlock(&priv->mutex);
  1756. iwl4965_cancel_deferred_work(priv);
  1757. ieee80211_restart_hw(priv->hw);
  1758. } else {
  1759. iwl4965_down(priv);
  1760. mutex_lock(&priv->mutex);
  1761. if (test_bit(STATUS_EXIT_PENDING, &priv->status)) {
  1762. mutex_unlock(&priv->mutex);
  1763. return;
  1764. }
  1765. __iwl4965_up(priv);
  1766. mutex_unlock(&priv->mutex);
  1767. }
  1768. }
  1769. static void iwl4965_bg_rx_replenish(struct work_struct *data)
  1770. {
  1771. struct iwl_priv *priv =
  1772. container_of(data, struct iwl_priv, rx_replenish);
  1773. if (test_bit(STATUS_EXIT_PENDING, &priv->status))
  1774. return;
  1775. mutex_lock(&priv->mutex);
  1776. iwl4965_rx_replenish(priv);
  1777. mutex_unlock(&priv->mutex);
  1778. }
  1779. /*****************************************************************************
  1780. *
  1781. * mac80211 entry point functions
  1782. *
  1783. *****************************************************************************/
  1784. #define UCODE_READY_TIMEOUT (4 * HZ)
  1785. /*
  1786. * Not a mac80211 entry point function, but it fits in with all the
  1787. * other mac80211 functions grouped here.
  1788. */
  1789. static int iwl4965_mac_setup_register(struct iwl_priv *priv,
  1790. u32 max_probe_length)
  1791. {
  1792. int ret;
  1793. struct ieee80211_hw *hw = priv->hw;
  1794. struct iwl_rxon_context *ctx;
  1795. hw->rate_control_algorithm = "iwl-4965-rs";
  1796. /* Tell mac80211 our characteristics */
  1797. hw->flags = IEEE80211_HW_SIGNAL_DBM |
  1798. IEEE80211_HW_AMPDU_AGGREGATION |
  1799. IEEE80211_HW_NEED_DTIM_PERIOD |
  1800. IEEE80211_HW_SPECTRUM_MGMT |
  1801. IEEE80211_HW_REPORTS_TX_ACK_STATUS;
  1802. if (priv->cfg->sku & IWL_SKU_N)
  1803. hw->flags |= IEEE80211_HW_SUPPORTS_DYNAMIC_SMPS |
  1804. IEEE80211_HW_SUPPORTS_STATIC_SMPS;
  1805. hw->sta_data_size = sizeof(struct iwl_station_priv);
  1806. hw->vif_data_size = sizeof(struct iwl_vif_priv);
  1807. for_each_context(priv, ctx) {
  1808. hw->wiphy->interface_modes |= ctx->interface_modes;
  1809. hw->wiphy->interface_modes |= ctx->exclusive_interface_modes;
  1810. }
  1811. hw->wiphy->flags |= WIPHY_FLAG_CUSTOM_REGULATORY |
  1812. WIPHY_FLAG_DISABLE_BEACON_HINTS;
  1813. /*
  1814. * For now, disable PS by default because it affects
  1815. * RX performance significantly.
  1816. */
  1817. hw->wiphy->flags &= ~WIPHY_FLAG_PS_ON_BY_DEFAULT;
  1818. hw->wiphy->max_scan_ssids = PROBE_OPTION_MAX;
  1819. /* we create the 802.11 header and a zero-length SSID element */
  1820. hw->wiphy->max_scan_ie_len = max_probe_length - 24 - 2;
  1821. /* Default value; 4 EDCA QOS priorities */
  1822. hw->queues = 4;
  1823. hw->max_listen_interval = IWL_CONN_MAX_LISTEN_INTERVAL;
  1824. if (priv->bands[IEEE80211_BAND_2GHZ].n_channels)
  1825. priv->hw->wiphy->bands[IEEE80211_BAND_2GHZ] =
  1826. &priv->bands[IEEE80211_BAND_2GHZ];
  1827. if (priv->bands[IEEE80211_BAND_5GHZ].n_channels)
  1828. priv->hw->wiphy->bands[IEEE80211_BAND_5GHZ] =
  1829. &priv->bands[IEEE80211_BAND_5GHZ];
  1830. iwl_legacy_leds_init(priv);
  1831. ret = ieee80211_register_hw(priv->hw);
  1832. if (ret) {
  1833. IWL_ERR(priv, "Failed to register hw (error %d)\n", ret);
  1834. return ret;
  1835. }
  1836. priv->mac80211_registered = 1;
  1837. return 0;
  1838. }
  1839. int iwl4965_mac_start(struct ieee80211_hw *hw)
  1840. {
  1841. struct iwl_priv *priv = hw->priv;
  1842. int ret;
  1843. IWL_DEBUG_MAC80211(priv, "enter\n");
  1844. /* we should be verifying the device is ready to be opened */
  1845. mutex_lock(&priv->mutex);
  1846. ret = __iwl4965_up(priv);
  1847. mutex_unlock(&priv->mutex);
  1848. if (ret)
  1849. return ret;
  1850. if (iwl_legacy_is_rfkill(priv))
  1851. goto out;
  1852. IWL_DEBUG_INFO(priv, "Start UP work done.\n");
  1853. /* Wait for START_ALIVE from Run Time ucode. Otherwise callbacks from
  1854. * mac80211 will not be run successfully. */
  1855. ret = wait_event_timeout(priv->wait_command_queue,
  1856. test_bit(STATUS_READY, &priv->status),
  1857. UCODE_READY_TIMEOUT);
  1858. if (!ret) {
  1859. if (!test_bit(STATUS_READY, &priv->status)) {
  1860. IWL_ERR(priv, "START_ALIVE timeout after %dms.\n",
  1861. jiffies_to_msecs(UCODE_READY_TIMEOUT));
  1862. return -ETIMEDOUT;
  1863. }
  1864. }
  1865. iwl4965_led_enable(priv);
  1866. out:
  1867. priv->is_open = 1;
  1868. IWL_DEBUG_MAC80211(priv, "leave\n");
  1869. return 0;
  1870. }
  1871. void iwl4965_mac_stop(struct ieee80211_hw *hw)
  1872. {
  1873. struct iwl_priv *priv = hw->priv;
  1874. IWL_DEBUG_MAC80211(priv, "enter\n");
  1875. if (!priv->is_open)
  1876. return;
  1877. priv->is_open = 0;
  1878. iwl4965_down(priv);
  1879. flush_workqueue(priv->workqueue);
  1880. /* User space software may expect getting rfkill changes
  1881. * even if interface is down */
  1882. iwl_write32(priv, CSR_INT, 0xFFFFFFFF);
  1883. iwl_legacy_enable_rfkill_int(priv);
  1884. IWL_DEBUG_MAC80211(priv, "leave\n");
  1885. }
  1886. void iwl4965_mac_tx(struct ieee80211_hw *hw, struct sk_buff *skb)
  1887. {
  1888. struct iwl_priv *priv = hw->priv;
  1889. IWL_DEBUG_MACDUMP(priv, "enter\n");
  1890. IWL_DEBUG_TX(priv, "dev->xmit(%d bytes) at rate 0x%02x\n", skb->len,
  1891. ieee80211_get_tx_rate(hw, IEEE80211_SKB_CB(skb))->bitrate);
  1892. if (iwl4965_tx_skb(priv, skb))
  1893. dev_kfree_skb_any(skb);
  1894. IWL_DEBUG_MACDUMP(priv, "leave\n");
  1895. }
  1896. void iwl4965_mac_update_tkip_key(struct ieee80211_hw *hw,
  1897. struct ieee80211_vif *vif,
  1898. struct ieee80211_key_conf *keyconf,
  1899. struct ieee80211_sta *sta,
  1900. u32 iv32, u16 *phase1key)
  1901. {
  1902. struct iwl_priv *priv = hw->priv;
  1903. struct iwl_vif_priv *vif_priv = (void *)vif->drv_priv;
  1904. IWL_DEBUG_MAC80211(priv, "enter\n");
  1905. iwl4965_update_tkip_key(priv, vif_priv->ctx, keyconf, sta,
  1906. iv32, phase1key);
  1907. IWL_DEBUG_MAC80211(priv, "leave\n");
  1908. }
  1909. int iwl4965_mac_set_key(struct ieee80211_hw *hw, enum set_key_cmd cmd,
  1910. struct ieee80211_vif *vif, struct ieee80211_sta *sta,
  1911. struct ieee80211_key_conf *key)
  1912. {
  1913. struct iwl_priv *priv = hw->priv;
  1914. struct iwl_vif_priv *vif_priv = (void *)vif->drv_priv;
  1915. struct iwl_rxon_context *ctx = vif_priv->ctx;
  1916. int ret;
  1917. u8 sta_id;
  1918. bool is_default_wep_key = false;
  1919. IWL_DEBUG_MAC80211(priv, "enter\n");
  1920. if (priv->cfg->mod_params->sw_crypto) {
  1921. IWL_DEBUG_MAC80211(priv, "leave - hwcrypto disabled\n");
  1922. return -EOPNOTSUPP;
  1923. }
  1924. sta_id = iwl_legacy_sta_id_or_broadcast(priv, vif_priv->ctx, sta);
  1925. if (sta_id == IWL_INVALID_STATION)
  1926. return -EINVAL;
  1927. mutex_lock(&priv->mutex);
  1928. iwl_legacy_scan_cancel_timeout(priv, 100);
  1929. /*
  1930. * If we are getting WEP group key and we didn't receive any key mapping
  1931. * so far, we are in legacy wep mode (group key only), otherwise we are
  1932. * in 1X mode.
  1933. * In legacy wep mode, we use another host command to the uCode.
  1934. */
  1935. if ((key->cipher == WLAN_CIPHER_SUITE_WEP40 ||
  1936. key->cipher == WLAN_CIPHER_SUITE_WEP104) &&
  1937. !sta) {
  1938. if (cmd == SET_KEY)
  1939. is_default_wep_key = !ctx->key_mapping_keys;
  1940. else
  1941. is_default_wep_key =
  1942. (key->hw_key_idx == HW_KEY_DEFAULT);
  1943. }
  1944. switch (cmd) {
  1945. case SET_KEY:
  1946. if (is_default_wep_key)
  1947. ret = iwl4965_set_default_wep_key(priv,
  1948. vif_priv->ctx, key);
  1949. else
  1950. ret = iwl4965_set_dynamic_key(priv, vif_priv->ctx,
  1951. key, sta_id);
  1952. IWL_DEBUG_MAC80211(priv, "enable hwcrypto key\n");
  1953. break;
  1954. case DISABLE_KEY:
  1955. if (is_default_wep_key)
  1956. ret = iwl4965_remove_default_wep_key(priv, ctx, key);
  1957. else
  1958. ret = iwl4965_remove_dynamic_key(priv, ctx,
  1959. key, sta_id);
  1960. IWL_DEBUG_MAC80211(priv, "disable hwcrypto key\n");
  1961. break;
  1962. default:
  1963. ret = -EINVAL;
  1964. }
  1965. mutex_unlock(&priv->mutex);
  1966. IWL_DEBUG_MAC80211(priv, "leave\n");
  1967. return ret;
  1968. }
  1969. int iwl4965_mac_ampdu_action(struct ieee80211_hw *hw,
  1970. struct ieee80211_vif *vif,
  1971. enum ieee80211_ampdu_mlme_action action,
  1972. struct ieee80211_sta *sta, u16 tid, u16 *ssn,
  1973. u8 buf_size)
  1974. {
  1975. struct iwl_priv *priv = hw->priv;
  1976. int ret = -EINVAL;
  1977. IWL_DEBUG_HT(priv, "A-MPDU action on addr %pM tid %d\n",
  1978. sta->addr, tid);
  1979. if (!(priv->cfg->sku & IWL_SKU_N))
  1980. return -EACCES;
  1981. mutex_lock(&priv->mutex);
  1982. switch (action) {
  1983. case IEEE80211_AMPDU_RX_START:
  1984. IWL_DEBUG_HT(priv, "start Rx\n");
  1985. ret = iwl4965_sta_rx_agg_start(priv, sta, tid, *ssn);
  1986. break;
  1987. case IEEE80211_AMPDU_RX_STOP:
  1988. IWL_DEBUG_HT(priv, "stop Rx\n");
  1989. ret = iwl4965_sta_rx_agg_stop(priv, sta, tid);
  1990. if (test_bit(STATUS_EXIT_PENDING, &priv->status))
  1991. ret = 0;
  1992. break;
  1993. case IEEE80211_AMPDU_TX_START:
  1994. IWL_DEBUG_HT(priv, "start Tx\n");
  1995. ret = iwl4965_tx_agg_start(priv, vif, sta, tid, ssn);
  1996. break;
  1997. case IEEE80211_AMPDU_TX_STOP:
  1998. IWL_DEBUG_HT(priv, "stop Tx\n");
  1999. ret = iwl4965_tx_agg_stop(priv, vif, sta, tid);
  2000. if (test_bit(STATUS_EXIT_PENDING, &priv->status))
  2001. ret = 0;
  2002. break;
  2003. case IEEE80211_AMPDU_TX_OPERATIONAL:
  2004. ret = 0;
  2005. break;
  2006. }
  2007. mutex_unlock(&priv->mutex);
  2008. return ret;
  2009. }
  2010. int iwl4965_mac_sta_add(struct ieee80211_hw *hw,
  2011. struct ieee80211_vif *vif,
  2012. struct ieee80211_sta *sta)
  2013. {
  2014. struct iwl_priv *priv = hw->priv;
  2015. struct iwl_station_priv *sta_priv = (void *)sta->drv_priv;
  2016. struct iwl_vif_priv *vif_priv = (void *)vif->drv_priv;
  2017. bool is_ap = vif->type == NL80211_IFTYPE_STATION;
  2018. int ret;
  2019. u8 sta_id;
  2020. IWL_DEBUG_INFO(priv, "received request to add station %pM\n",
  2021. sta->addr);
  2022. mutex_lock(&priv->mutex);
  2023. IWL_DEBUG_INFO(priv, "proceeding to add station %pM\n",
  2024. sta->addr);
  2025. sta_priv->common.sta_id = IWL_INVALID_STATION;
  2026. atomic_set(&sta_priv->pending_frames, 0);
  2027. ret = iwl_legacy_add_station_common(priv, vif_priv->ctx, sta->addr,
  2028. is_ap, sta, &sta_id);
  2029. if (ret) {
  2030. IWL_ERR(priv, "Unable to add station %pM (%d)\n",
  2031. sta->addr, ret);
  2032. /* Should we return success if return code is EEXIST ? */
  2033. mutex_unlock(&priv->mutex);
  2034. return ret;
  2035. }
  2036. sta_priv->common.sta_id = sta_id;
  2037. /* Initialize rate scaling */
  2038. IWL_DEBUG_INFO(priv, "Initializing rate scaling for station %pM\n",
  2039. sta->addr);
  2040. iwl4965_rs_rate_init(priv, sta, sta_id);
  2041. mutex_unlock(&priv->mutex);
  2042. return 0;
  2043. }
  2044. void iwl4965_mac_channel_switch(struct ieee80211_hw *hw,
  2045. struct ieee80211_channel_switch *ch_switch)
  2046. {
  2047. struct iwl_priv *priv = hw->priv;
  2048. const struct iwl_channel_info *ch_info;
  2049. struct ieee80211_conf *conf = &hw->conf;
  2050. struct ieee80211_channel *channel = ch_switch->channel;
  2051. struct iwl_ht_config *ht_conf = &priv->current_ht_config;
  2052. struct iwl_rxon_context *ctx = &priv->contexts[IWL_RXON_CTX_BSS];
  2053. u16 ch;
  2054. IWL_DEBUG_MAC80211(priv, "enter\n");
  2055. mutex_lock(&priv->mutex);
  2056. if (iwl_legacy_is_rfkill(priv))
  2057. goto out;
  2058. if (test_bit(STATUS_EXIT_PENDING, &priv->status) ||
  2059. test_bit(STATUS_SCANNING, &priv->status) ||
  2060. test_bit(STATUS_CHANNEL_SWITCH_PENDING, &priv->status))
  2061. goto out;
  2062. if (!iwl_legacy_is_associated_ctx(ctx))
  2063. goto out;
  2064. if (!priv->cfg->ops->lib->set_channel_switch)
  2065. goto out;
  2066. ch = channel->hw_value;
  2067. if (le16_to_cpu(ctx->active.channel) == ch)
  2068. goto out;
  2069. ch_info = iwl_legacy_get_channel_info(priv, channel->band, ch);
  2070. if (!iwl_legacy_is_channel_valid(ch_info)) {
  2071. IWL_DEBUG_MAC80211(priv, "invalid channel\n");
  2072. goto out;
  2073. }
  2074. spin_lock_irq(&priv->lock);
  2075. priv->current_ht_config.smps = conf->smps_mode;
  2076. /* Configure HT40 channels */
  2077. ctx->ht.enabled = conf_is_ht(conf);
  2078. if (ctx->ht.enabled) {
  2079. if (conf_is_ht40_minus(conf)) {
  2080. ctx->ht.extension_chan_offset =
  2081. IEEE80211_HT_PARAM_CHA_SEC_BELOW;
  2082. ctx->ht.is_40mhz = true;
  2083. } else if (conf_is_ht40_plus(conf)) {
  2084. ctx->ht.extension_chan_offset =
  2085. IEEE80211_HT_PARAM_CHA_SEC_ABOVE;
  2086. ctx->ht.is_40mhz = true;
  2087. } else {
  2088. ctx->ht.extension_chan_offset =
  2089. IEEE80211_HT_PARAM_CHA_SEC_NONE;
  2090. ctx->ht.is_40mhz = false;
  2091. }
  2092. } else
  2093. ctx->ht.is_40mhz = false;
  2094. if ((le16_to_cpu(ctx->staging.channel) != ch))
  2095. ctx->staging.flags = 0;
  2096. iwl_legacy_set_rxon_channel(priv, channel, ctx);
  2097. iwl_legacy_set_rxon_ht(priv, ht_conf);
  2098. iwl_legacy_set_flags_for_band(priv, ctx, channel->band, ctx->vif);
  2099. spin_unlock_irq(&priv->lock);
  2100. iwl_legacy_set_rate(priv);
  2101. /*
  2102. * at this point, staging_rxon has the
  2103. * configuration for channel switch
  2104. */
  2105. set_bit(STATUS_CHANNEL_SWITCH_PENDING, &priv->status);
  2106. priv->switch_channel = cpu_to_le16(ch);
  2107. if (priv->cfg->ops->lib->set_channel_switch(priv, ch_switch)) {
  2108. clear_bit(STATUS_CHANNEL_SWITCH_PENDING, &priv->status);
  2109. priv->switch_channel = 0;
  2110. ieee80211_chswitch_done(ctx->vif, false);
  2111. }
  2112. out:
  2113. mutex_unlock(&priv->mutex);
  2114. IWL_DEBUG_MAC80211(priv, "leave\n");
  2115. }
  2116. void iwl4965_configure_filter(struct ieee80211_hw *hw,
  2117. unsigned int changed_flags,
  2118. unsigned int *total_flags,
  2119. u64 multicast)
  2120. {
  2121. struct iwl_priv *priv = hw->priv;
  2122. __le32 filter_or = 0, filter_nand = 0;
  2123. struct iwl_rxon_context *ctx;
  2124. #define CHK(test, flag) do { \
  2125. if (*total_flags & (test)) \
  2126. filter_or |= (flag); \
  2127. else \
  2128. filter_nand |= (flag); \
  2129. } while (0)
  2130. IWL_DEBUG_MAC80211(priv, "Enter: changed: 0x%x, total: 0x%x\n",
  2131. changed_flags, *total_flags);
  2132. CHK(FIF_OTHER_BSS | FIF_PROMISC_IN_BSS, RXON_FILTER_PROMISC_MSK);
  2133. /* Setting _just_ RXON_FILTER_CTL2HOST_MSK causes FH errors */
  2134. CHK(FIF_CONTROL, RXON_FILTER_CTL2HOST_MSK | RXON_FILTER_PROMISC_MSK);
  2135. CHK(FIF_BCN_PRBRESP_PROMISC, RXON_FILTER_BCON_AWARE_MSK);
  2136. #undef CHK
  2137. mutex_lock(&priv->mutex);
  2138. for_each_context(priv, ctx) {
  2139. ctx->staging.filter_flags &= ~filter_nand;
  2140. ctx->staging.filter_flags |= filter_or;
  2141. /*
  2142. * Not committing directly because hardware can perform a scan,
  2143. * but we'll eventually commit the filter flags change anyway.
  2144. */
  2145. }
  2146. mutex_unlock(&priv->mutex);
  2147. /*
  2148. * Receiving all multicast frames is always enabled by the
  2149. * default flags setup in iwl_legacy_connection_init_rx_config()
  2150. * since we currently do not support programming multicast
  2151. * filters into the device.
  2152. */
  2153. *total_flags &= FIF_OTHER_BSS | FIF_ALLMULTI | FIF_PROMISC_IN_BSS |
  2154. FIF_BCN_PRBRESP_PROMISC | FIF_CONTROL;
  2155. }
  2156. /*****************************************************************************
  2157. *
  2158. * driver setup and teardown
  2159. *
  2160. *****************************************************************************/
  2161. static void iwl4965_bg_txpower_work(struct work_struct *work)
  2162. {
  2163. struct iwl_priv *priv = container_of(work, struct iwl_priv,
  2164. txpower_work);
  2165. mutex_lock(&priv->mutex);
  2166. /* If a scan happened to start before we got here
  2167. * then just return; the statistics notification will
  2168. * kick off another scheduled work to compensate for
  2169. * any temperature delta we missed here. */
  2170. if (test_bit(STATUS_EXIT_PENDING, &priv->status) ||
  2171. test_bit(STATUS_SCANNING, &priv->status))
  2172. goto out;
  2173. /* Regardless of if we are associated, we must reconfigure the
  2174. * TX power since frames can be sent on non-radar channels while
  2175. * not associated */
  2176. priv->cfg->ops->lib->send_tx_power(priv);
  2177. /* Update last_temperature to keep is_calib_needed from running
  2178. * when it isn't needed... */
  2179. priv->last_temperature = priv->temperature;
  2180. out:
  2181. mutex_unlock(&priv->mutex);
  2182. }
  2183. static void iwl4965_setup_deferred_work(struct iwl_priv *priv)
  2184. {
  2185. priv->workqueue = create_singlethread_workqueue(DRV_NAME);
  2186. init_waitqueue_head(&priv->wait_command_queue);
  2187. INIT_WORK(&priv->restart, iwl4965_bg_restart);
  2188. INIT_WORK(&priv->rx_replenish, iwl4965_bg_rx_replenish);
  2189. INIT_WORK(&priv->run_time_calib_work, iwl4965_bg_run_time_calib_work);
  2190. INIT_DELAYED_WORK(&priv->init_alive_start, iwl4965_bg_init_alive_start);
  2191. INIT_DELAYED_WORK(&priv->alive_start, iwl4965_bg_alive_start);
  2192. iwl_legacy_setup_scan_deferred_work(priv);
  2193. INIT_WORK(&priv->txpower_work, iwl4965_bg_txpower_work);
  2194. init_timer(&priv->statistics_periodic);
  2195. priv->statistics_periodic.data = (unsigned long)priv;
  2196. priv->statistics_periodic.function = iwl4965_bg_statistics_periodic;
  2197. init_timer(&priv->watchdog);
  2198. priv->watchdog.data = (unsigned long)priv;
  2199. priv->watchdog.function = iwl_legacy_bg_watchdog;
  2200. tasklet_init(&priv->irq_tasklet, (void (*)(unsigned long))
  2201. iwl4965_irq_tasklet, (unsigned long)priv);
  2202. }
  2203. static void iwl4965_cancel_deferred_work(struct iwl_priv *priv)
  2204. {
  2205. cancel_work_sync(&priv->txpower_work);
  2206. cancel_delayed_work_sync(&priv->init_alive_start);
  2207. cancel_delayed_work(&priv->alive_start);
  2208. cancel_work_sync(&priv->run_time_calib_work);
  2209. iwl_legacy_cancel_scan_deferred_work(priv);
  2210. del_timer_sync(&priv->statistics_periodic);
  2211. }
  2212. static void iwl4965_init_hw_rates(struct iwl_priv *priv,
  2213. struct ieee80211_rate *rates)
  2214. {
  2215. int i;
  2216. for (i = 0; i < IWL_RATE_COUNT_LEGACY; i++) {
  2217. rates[i].bitrate = iwlegacy_rates[i].ieee * 5;
  2218. rates[i].hw_value = i; /* Rate scaling will work on indexes */
  2219. rates[i].hw_value_short = i;
  2220. rates[i].flags = 0;
  2221. if ((i >= IWL_FIRST_CCK_RATE) && (i <= IWL_LAST_CCK_RATE)) {
  2222. /*
  2223. * If CCK != 1M then set short preamble rate flag.
  2224. */
  2225. rates[i].flags |=
  2226. (iwlegacy_rates[i].plcp == IWL_RATE_1M_PLCP) ?
  2227. 0 : IEEE80211_RATE_SHORT_PREAMBLE;
  2228. }
  2229. }
  2230. }
  2231. /*
  2232. * Acquire priv->lock before calling this function !
  2233. */
  2234. void iwl4965_set_wr_ptrs(struct iwl_priv *priv, int txq_id, u32 index)
  2235. {
  2236. iwl_legacy_write_direct32(priv, HBUS_TARG_WRPTR,
  2237. (index & 0xff) | (txq_id << 8));
  2238. iwl_legacy_write_prph(priv, IWL49_SCD_QUEUE_RDPTR(txq_id), index);
  2239. }
  2240. void iwl4965_tx_queue_set_status(struct iwl_priv *priv,
  2241. struct iwl_tx_queue *txq,
  2242. int tx_fifo_id, int scd_retry)
  2243. {
  2244. int txq_id = txq->q.id;
  2245. /* Find out whether to activate Tx queue */
  2246. int active = test_bit(txq_id, &priv->txq_ctx_active_msk) ? 1 : 0;
  2247. /* Set up and activate */
  2248. iwl_legacy_write_prph(priv, IWL49_SCD_QUEUE_STATUS_BITS(txq_id),
  2249. (active << IWL49_SCD_QUEUE_STTS_REG_POS_ACTIVE) |
  2250. (tx_fifo_id << IWL49_SCD_QUEUE_STTS_REG_POS_TXF) |
  2251. (scd_retry << IWL49_SCD_QUEUE_STTS_REG_POS_WSL) |
  2252. (scd_retry << IWL49_SCD_QUEUE_STTS_REG_POS_SCD_ACK) |
  2253. IWL49_SCD_QUEUE_STTS_REG_MSK);
  2254. txq->sched_retry = scd_retry;
  2255. IWL_DEBUG_INFO(priv, "%s %s Queue %d on AC %d\n",
  2256. active ? "Activate" : "Deactivate",
  2257. scd_retry ? "BA" : "AC", txq_id, tx_fifo_id);
  2258. }
  2259. static int iwl4965_init_drv(struct iwl_priv *priv)
  2260. {
  2261. int ret;
  2262. spin_lock_init(&priv->sta_lock);
  2263. spin_lock_init(&priv->hcmd_lock);
  2264. INIT_LIST_HEAD(&priv->free_frames);
  2265. mutex_init(&priv->mutex);
  2266. priv->ieee_channels = NULL;
  2267. priv->ieee_rates = NULL;
  2268. priv->band = IEEE80211_BAND_2GHZ;
  2269. priv->iw_mode = NL80211_IFTYPE_STATION;
  2270. priv->current_ht_config.smps = IEEE80211_SMPS_STATIC;
  2271. priv->missed_beacon_threshold = IWL_MISSED_BEACON_THRESHOLD_DEF;
  2272. /* initialize force reset */
  2273. priv->force_reset.reset_duration = IWL_DELAY_NEXT_FORCE_FW_RELOAD;
  2274. /* Choose which receivers/antennas to use */
  2275. if (priv->cfg->ops->hcmd->set_rxon_chain)
  2276. priv->cfg->ops->hcmd->set_rxon_chain(priv,
  2277. &priv->contexts[IWL_RXON_CTX_BSS]);
  2278. iwl_legacy_init_scan_params(priv);
  2279. ret = iwl_legacy_init_channel_map(priv);
  2280. if (ret) {
  2281. IWL_ERR(priv, "initializing regulatory failed: %d\n", ret);
  2282. goto err;
  2283. }
  2284. ret = iwl_legacy_init_geos(priv);
  2285. if (ret) {
  2286. IWL_ERR(priv, "initializing geos failed: %d\n", ret);
  2287. goto err_free_channel_map;
  2288. }
  2289. iwl4965_init_hw_rates(priv, priv->ieee_rates);
  2290. return 0;
  2291. err_free_channel_map:
  2292. iwl_legacy_free_channel_map(priv);
  2293. err:
  2294. return ret;
  2295. }
  2296. static void iwl4965_uninit_drv(struct iwl_priv *priv)
  2297. {
  2298. iwl4965_calib_free_results(priv);
  2299. iwl_legacy_free_geos(priv);
  2300. iwl_legacy_free_channel_map(priv);
  2301. kfree(priv->scan_cmd);
  2302. }
  2303. static void iwl4965_hw_detect(struct iwl_priv *priv)
  2304. {
  2305. priv->hw_rev = _iwl_legacy_read32(priv, CSR_HW_REV);
  2306. priv->hw_wa_rev = _iwl_legacy_read32(priv, CSR_HW_REV_WA_REG);
  2307. priv->rev_id = priv->pci_dev->revision;
  2308. IWL_DEBUG_INFO(priv, "HW Revision ID = 0x%X\n", priv->rev_id);
  2309. }
  2310. static int iwl4965_set_hw_params(struct iwl_priv *priv)
  2311. {
  2312. priv->hw_params.max_rxq_size = RX_QUEUE_SIZE;
  2313. priv->hw_params.max_rxq_log = RX_QUEUE_SIZE_LOG;
  2314. if (priv->cfg->mod_params->amsdu_size_8K)
  2315. priv->hw_params.rx_page_order = get_order(IWL_RX_BUF_SIZE_8K);
  2316. else
  2317. priv->hw_params.rx_page_order = get_order(IWL_RX_BUF_SIZE_4K);
  2318. priv->hw_params.max_beacon_itrvl = IWL_MAX_UCODE_BEACON_INTERVAL;
  2319. if (priv->cfg->mod_params->disable_11n)
  2320. priv->cfg->sku &= ~IWL_SKU_N;
  2321. /* Device-specific setup */
  2322. return priv->cfg->ops->lib->set_hw_params(priv);
  2323. }
  2324. static const u8 iwl4965_bss_ac_to_fifo[] = {
  2325. IWL_TX_FIFO_VO,
  2326. IWL_TX_FIFO_VI,
  2327. IWL_TX_FIFO_BE,
  2328. IWL_TX_FIFO_BK,
  2329. };
  2330. static const u8 iwl4965_bss_ac_to_queue[] = {
  2331. 0, 1, 2, 3,
  2332. };
  2333. static int
  2334. iwl4965_pci_probe(struct pci_dev *pdev, const struct pci_device_id *ent)
  2335. {
  2336. int err = 0, i;
  2337. struct iwl_priv *priv;
  2338. struct ieee80211_hw *hw;
  2339. struct iwl_cfg *cfg = (struct iwl_cfg *)(ent->driver_data);
  2340. unsigned long flags;
  2341. u16 pci_cmd;
  2342. /************************
  2343. * 1. Allocating HW data
  2344. ************************/
  2345. hw = iwl_legacy_alloc_all(cfg);
  2346. if (!hw) {
  2347. err = -ENOMEM;
  2348. goto out;
  2349. }
  2350. priv = hw->priv;
  2351. /* At this point both hw and priv are allocated. */
  2352. /*
  2353. * The default context is always valid,
  2354. * more may be discovered when firmware
  2355. * is loaded.
  2356. */
  2357. priv->valid_contexts = BIT(IWL_RXON_CTX_BSS);
  2358. for (i = 0; i < NUM_IWL_RXON_CTX; i++)
  2359. priv->contexts[i].ctxid = i;
  2360. priv->contexts[IWL_RXON_CTX_BSS].always_active = true;
  2361. priv->contexts[IWL_RXON_CTX_BSS].is_active = true;
  2362. priv->contexts[IWL_RXON_CTX_BSS].rxon_cmd = REPLY_RXON;
  2363. priv->contexts[IWL_RXON_CTX_BSS].rxon_timing_cmd = REPLY_RXON_TIMING;
  2364. priv->contexts[IWL_RXON_CTX_BSS].rxon_assoc_cmd = REPLY_RXON_ASSOC;
  2365. priv->contexts[IWL_RXON_CTX_BSS].qos_cmd = REPLY_QOS_PARAM;
  2366. priv->contexts[IWL_RXON_CTX_BSS].ap_sta_id = IWL_AP_ID;
  2367. priv->contexts[IWL_RXON_CTX_BSS].wep_key_cmd = REPLY_WEPKEY;
  2368. priv->contexts[IWL_RXON_CTX_BSS].ac_to_fifo = iwl4965_bss_ac_to_fifo;
  2369. priv->contexts[IWL_RXON_CTX_BSS].ac_to_queue = iwl4965_bss_ac_to_queue;
  2370. priv->contexts[IWL_RXON_CTX_BSS].exclusive_interface_modes =
  2371. BIT(NL80211_IFTYPE_ADHOC);
  2372. priv->contexts[IWL_RXON_CTX_BSS].interface_modes =
  2373. BIT(NL80211_IFTYPE_STATION);
  2374. priv->contexts[IWL_RXON_CTX_BSS].ap_devtype = RXON_DEV_TYPE_AP;
  2375. priv->contexts[IWL_RXON_CTX_BSS].ibss_devtype = RXON_DEV_TYPE_IBSS;
  2376. priv->contexts[IWL_RXON_CTX_BSS].station_devtype = RXON_DEV_TYPE_ESS;
  2377. priv->contexts[IWL_RXON_CTX_BSS].unused_devtype = RXON_DEV_TYPE_ESS;
  2378. BUILD_BUG_ON(NUM_IWL_RXON_CTX != 1);
  2379. SET_IEEE80211_DEV(hw, &pdev->dev);
  2380. IWL_DEBUG_INFO(priv, "*** LOAD DRIVER ***\n");
  2381. priv->cfg = cfg;
  2382. priv->pci_dev = pdev;
  2383. priv->inta_mask = CSR_INI_SET_MASK;
  2384. if (iwl_legacy_alloc_traffic_mem(priv))
  2385. IWL_ERR(priv, "Not enough memory to generate traffic log\n");
  2386. /**************************
  2387. * 2. Initializing PCI bus
  2388. **************************/
  2389. pci_disable_link_state(pdev, PCIE_LINK_STATE_L0S | PCIE_LINK_STATE_L1 |
  2390. PCIE_LINK_STATE_CLKPM);
  2391. if (pci_enable_device(pdev)) {
  2392. err = -ENODEV;
  2393. goto out_ieee80211_free_hw;
  2394. }
  2395. pci_set_master(pdev);
  2396. err = pci_set_dma_mask(pdev, DMA_BIT_MASK(36));
  2397. if (!err)
  2398. err = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(36));
  2399. if (err) {
  2400. err = pci_set_dma_mask(pdev, DMA_BIT_MASK(32));
  2401. if (!err)
  2402. err = pci_set_consistent_dma_mask(pdev,
  2403. DMA_BIT_MASK(32));
  2404. /* both attempts failed: */
  2405. if (err) {
  2406. IWL_WARN(priv, "No suitable DMA available.\n");
  2407. goto out_pci_disable_device;
  2408. }
  2409. }
  2410. err = pci_request_regions(pdev, DRV_NAME);
  2411. if (err)
  2412. goto out_pci_disable_device;
  2413. pci_set_drvdata(pdev, priv);
  2414. /***********************
  2415. * 3. Read REV register
  2416. ***********************/
  2417. priv->hw_base = pci_iomap(pdev, 0, 0);
  2418. if (!priv->hw_base) {
  2419. err = -ENODEV;
  2420. goto out_pci_release_regions;
  2421. }
  2422. IWL_DEBUG_INFO(priv, "pci_resource_len = 0x%08llx\n",
  2423. (unsigned long long) pci_resource_len(pdev, 0));
  2424. IWL_DEBUG_INFO(priv, "pci_resource_base = %p\n", priv->hw_base);
  2425. /* these spin locks will be used in apm_ops.init and EEPROM access
  2426. * we should init now
  2427. */
  2428. spin_lock_init(&priv->reg_lock);
  2429. spin_lock_init(&priv->lock);
  2430. /*
  2431. * stop and reset the on-board processor just in case it is in a
  2432. * strange state ... like being left stranded by a primary kernel
  2433. * and this is now the kdump kernel trying to start up
  2434. */
  2435. iwl_write32(priv, CSR_RESET, CSR_RESET_REG_FLAG_NEVO_RESET);
  2436. iwl4965_hw_detect(priv);
  2437. IWL_INFO(priv, "Detected %s, REV=0x%X\n",
  2438. priv->cfg->name, priv->hw_rev);
  2439. /* We disable the RETRY_TIMEOUT register (0x41) to keep
  2440. * PCI Tx retries from interfering with C3 CPU state */
  2441. pci_write_config_byte(pdev, PCI_CFG_RETRY_TIMEOUT, 0x00);
  2442. iwl4965_prepare_card_hw(priv);
  2443. if (!priv->hw_ready) {
  2444. IWL_WARN(priv, "Failed, HW not ready\n");
  2445. goto out_iounmap;
  2446. }
  2447. /*****************
  2448. * 4. Read EEPROM
  2449. *****************/
  2450. /* Read the EEPROM */
  2451. err = iwl_legacy_eeprom_init(priv);
  2452. if (err) {
  2453. IWL_ERR(priv, "Unable to init EEPROM\n");
  2454. goto out_iounmap;
  2455. }
  2456. err = iwl4965_eeprom_check_version(priv);
  2457. if (err)
  2458. goto out_free_eeprom;
  2459. if (err)
  2460. goto out_free_eeprom;
  2461. /* extract MAC Address */
  2462. iwl4965_eeprom_get_mac(priv, priv->addresses[0].addr);
  2463. IWL_DEBUG_INFO(priv, "MAC address: %pM\n", priv->addresses[0].addr);
  2464. priv->hw->wiphy->addresses = priv->addresses;
  2465. priv->hw->wiphy->n_addresses = 1;
  2466. /************************
  2467. * 5. Setup HW constants
  2468. ************************/
  2469. if (iwl4965_set_hw_params(priv)) {
  2470. IWL_ERR(priv, "failed to set hw parameters\n");
  2471. goto out_free_eeprom;
  2472. }
  2473. /*******************
  2474. * 6. Setup priv
  2475. *******************/
  2476. err = iwl4965_init_drv(priv);
  2477. if (err)
  2478. goto out_free_eeprom;
  2479. /* At this point both hw and priv are initialized. */
  2480. /********************
  2481. * 7. Setup services
  2482. ********************/
  2483. spin_lock_irqsave(&priv->lock, flags);
  2484. iwl_legacy_disable_interrupts(priv);
  2485. spin_unlock_irqrestore(&priv->lock, flags);
  2486. pci_enable_msi(priv->pci_dev);
  2487. err = request_irq(priv->pci_dev->irq, iwl_legacy_isr,
  2488. IRQF_SHARED, DRV_NAME, priv);
  2489. if (err) {
  2490. IWL_ERR(priv, "Error allocating IRQ %d\n", priv->pci_dev->irq);
  2491. goto out_disable_msi;
  2492. }
  2493. iwl4965_setup_deferred_work(priv);
  2494. iwl4965_setup_rx_handlers(priv);
  2495. /*********************************************
  2496. * 8. Enable interrupts and read RFKILL state
  2497. *********************************************/
  2498. /* enable rfkill interrupt: hw bug w/a */
  2499. pci_read_config_word(priv->pci_dev, PCI_COMMAND, &pci_cmd);
  2500. if (pci_cmd & PCI_COMMAND_INTX_DISABLE) {
  2501. pci_cmd &= ~PCI_COMMAND_INTX_DISABLE;
  2502. pci_write_config_word(priv->pci_dev, PCI_COMMAND, pci_cmd);
  2503. }
  2504. iwl_legacy_enable_rfkill_int(priv);
  2505. /* If platform's RF_KILL switch is NOT set to KILL */
  2506. if (iwl_read32(priv, CSR_GP_CNTRL) &
  2507. CSR_GP_CNTRL_REG_FLAG_HW_RF_KILL_SW)
  2508. clear_bit(STATUS_RF_KILL_HW, &priv->status);
  2509. else
  2510. set_bit(STATUS_RF_KILL_HW, &priv->status);
  2511. wiphy_rfkill_set_hw_state(priv->hw->wiphy,
  2512. test_bit(STATUS_RF_KILL_HW, &priv->status));
  2513. iwl_legacy_power_initialize(priv);
  2514. init_completion(&priv->_4965.firmware_loading_complete);
  2515. err = iwl4965_request_firmware(priv, true);
  2516. if (err)
  2517. goto out_destroy_workqueue;
  2518. return 0;
  2519. out_destroy_workqueue:
  2520. destroy_workqueue(priv->workqueue);
  2521. priv->workqueue = NULL;
  2522. free_irq(priv->pci_dev->irq, priv);
  2523. out_disable_msi:
  2524. pci_disable_msi(priv->pci_dev);
  2525. iwl4965_uninit_drv(priv);
  2526. out_free_eeprom:
  2527. iwl_legacy_eeprom_free(priv);
  2528. out_iounmap:
  2529. pci_iounmap(pdev, priv->hw_base);
  2530. out_pci_release_regions:
  2531. pci_set_drvdata(pdev, NULL);
  2532. pci_release_regions(pdev);
  2533. out_pci_disable_device:
  2534. pci_disable_device(pdev);
  2535. out_ieee80211_free_hw:
  2536. iwl_legacy_free_traffic_mem(priv);
  2537. ieee80211_free_hw(priv->hw);
  2538. out:
  2539. return err;
  2540. }
  2541. static void __devexit iwl4965_pci_remove(struct pci_dev *pdev)
  2542. {
  2543. struct iwl_priv *priv = pci_get_drvdata(pdev);
  2544. unsigned long flags;
  2545. if (!priv)
  2546. return;
  2547. wait_for_completion(&priv->_4965.firmware_loading_complete);
  2548. IWL_DEBUG_INFO(priv, "*** UNLOAD DRIVER ***\n");
  2549. iwl_legacy_dbgfs_unregister(priv);
  2550. sysfs_remove_group(&pdev->dev.kobj, &iwl_attribute_group);
  2551. /* ieee80211_unregister_hw call wil cause iwl_mac_stop to
  2552. * to be called and iwl4965_down since we are removing the device
  2553. * we need to set STATUS_EXIT_PENDING bit.
  2554. */
  2555. set_bit(STATUS_EXIT_PENDING, &priv->status);
  2556. iwl_legacy_leds_exit(priv);
  2557. if (priv->mac80211_registered) {
  2558. ieee80211_unregister_hw(priv->hw);
  2559. priv->mac80211_registered = 0;
  2560. } else {
  2561. iwl4965_down(priv);
  2562. }
  2563. /*
  2564. * Make sure device is reset to low power before unloading driver.
  2565. * This may be redundant with iwl4965_down(), but there are paths to
  2566. * run iwl4965_down() without calling apm_ops.stop(), and there are
  2567. * paths to avoid running iwl4965_down() at all before leaving driver.
  2568. * This (inexpensive) call *makes sure* device is reset.
  2569. */
  2570. iwl_legacy_apm_stop(priv);
  2571. /* make sure we flush any pending irq or
  2572. * tasklet for the driver
  2573. */
  2574. spin_lock_irqsave(&priv->lock, flags);
  2575. iwl_legacy_disable_interrupts(priv);
  2576. spin_unlock_irqrestore(&priv->lock, flags);
  2577. iwl4965_synchronize_irq(priv);
  2578. iwl4965_dealloc_ucode_pci(priv);
  2579. if (priv->rxq.bd)
  2580. iwl4965_rx_queue_free(priv, &priv->rxq);
  2581. iwl4965_hw_txq_ctx_free(priv);
  2582. iwl_legacy_eeprom_free(priv);
  2583. /*netif_stop_queue(dev); */
  2584. flush_workqueue(priv->workqueue);
  2585. /* ieee80211_unregister_hw calls iwl_mac_stop, which flushes
  2586. * priv->workqueue... so we can't take down the workqueue
  2587. * until now... */
  2588. destroy_workqueue(priv->workqueue);
  2589. priv->workqueue = NULL;
  2590. iwl_legacy_free_traffic_mem(priv);
  2591. free_irq(priv->pci_dev->irq, priv);
  2592. pci_disable_msi(priv->pci_dev);
  2593. pci_iounmap(pdev, priv->hw_base);
  2594. pci_release_regions(pdev);
  2595. pci_disable_device(pdev);
  2596. pci_set_drvdata(pdev, NULL);
  2597. iwl4965_uninit_drv(priv);
  2598. dev_kfree_skb(priv->beacon_skb);
  2599. ieee80211_free_hw(priv->hw);
  2600. }
  2601. /*
  2602. * Activate/Deactivate Tx DMA/FIFO channels according tx fifos mask
  2603. * must be called under priv->lock and mac access
  2604. */
  2605. void iwl4965_txq_set_sched(struct iwl_priv *priv, u32 mask)
  2606. {
  2607. iwl_legacy_write_prph(priv, IWL49_SCD_TXFACT, mask);
  2608. }
  2609. /*****************************************************************************
  2610. *
  2611. * driver and module entry point
  2612. *
  2613. *****************************************************************************/
  2614. /* Hardware specific file defines the PCI IDs table for that hardware module */
  2615. static DEFINE_PCI_DEVICE_TABLE(iwl4965_hw_card_ids) = {
  2616. #if defined(CONFIG_IWL4965_MODULE) || defined(CONFIG_IWL4965)
  2617. {IWL_PCI_DEVICE(0x4229, PCI_ANY_ID, iwl4965_cfg)},
  2618. {IWL_PCI_DEVICE(0x4230, PCI_ANY_ID, iwl4965_cfg)},
  2619. #endif /* CONFIG_IWL4965 */
  2620. {0}
  2621. };
  2622. MODULE_DEVICE_TABLE(pci, iwl4965_hw_card_ids);
  2623. static struct pci_driver iwl4965_driver = {
  2624. .name = DRV_NAME,
  2625. .id_table = iwl4965_hw_card_ids,
  2626. .probe = iwl4965_pci_probe,
  2627. .remove = __devexit_p(iwl4965_pci_remove),
  2628. .driver.pm = IWL_LEGACY_PM_OPS,
  2629. };
  2630. static int __init iwl4965_init(void)
  2631. {
  2632. int ret;
  2633. pr_info(DRV_DESCRIPTION ", " DRV_VERSION "\n");
  2634. pr_info(DRV_COPYRIGHT "\n");
  2635. ret = iwl4965_rate_control_register();
  2636. if (ret) {
  2637. pr_err("Unable to register rate control algorithm: %d\n", ret);
  2638. return ret;
  2639. }
  2640. ret = pci_register_driver(&iwl4965_driver);
  2641. if (ret) {
  2642. pr_err("Unable to initialize PCI module\n");
  2643. goto error_register;
  2644. }
  2645. return ret;
  2646. error_register:
  2647. iwl4965_rate_control_unregister();
  2648. return ret;
  2649. }
  2650. static void __exit iwl4965_exit(void)
  2651. {
  2652. pci_unregister_driver(&iwl4965_driver);
  2653. iwl4965_rate_control_unregister();
  2654. }
  2655. module_exit(iwl4965_exit);
  2656. module_init(iwl4965_init);
  2657. #ifdef CONFIG_IWLWIFI_LEGACY_DEBUG
  2658. module_param_named(debug, iwlegacy_debug_level, uint, S_IRUGO | S_IWUSR);
  2659. MODULE_PARM_DESC(debug, "debug output mask");
  2660. #endif
  2661. module_param_named(swcrypto, iwl4965_mod_params.sw_crypto, int, S_IRUGO);
  2662. MODULE_PARM_DESC(swcrypto, "using crypto in software (default 0 [hardware])");
  2663. module_param_named(queues_num, iwl4965_mod_params.num_of_queues, int, S_IRUGO);
  2664. MODULE_PARM_DESC(queues_num, "number of hw queues.");
  2665. module_param_named(11n_disable, iwl4965_mod_params.disable_11n, int, S_IRUGO);
  2666. MODULE_PARM_DESC(11n_disable, "disable 11n functionality");
  2667. module_param_named(amsdu_size_8K, iwl4965_mod_params.amsdu_size_8K,
  2668. int, S_IRUGO);
  2669. MODULE_PARM_DESC(amsdu_size_8K, "enable 8K amsdu size");
  2670. module_param_named(fw_restart, iwl4965_mod_params.restart_fw, int, S_IRUGO);
  2671. MODULE_PARM_DESC(fw_restart, "restart firmware in case of error");