iwl-tx.c 19 KB

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  1. /******************************************************************************
  2. *
  3. * Copyright(c) 2003 - 2011 Intel Corporation. All rights reserved.
  4. *
  5. * Portions of this file are derived from the ipw3945 project, as well
  6. * as portions of the ieee80211 subsystem header files.
  7. *
  8. * This program is free software; you can redistribute it and/or modify it
  9. * under the terms of version 2 of the GNU General Public License as
  10. * published by the Free Software Foundation.
  11. *
  12. * This program is distributed in the hope that it will be useful, but WITHOUT
  13. * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  14. * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
  15. * more details.
  16. *
  17. * You should have received a copy of the GNU General Public License along with
  18. * this program; if not, write to the Free Software Foundation, Inc.,
  19. * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
  20. *
  21. * The full GNU General Public License is included in this distribution in the
  22. * file called LICENSE.
  23. *
  24. * Contact Information:
  25. * Intel Linux Wireless <ilw@linux.intel.com>
  26. * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
  27. *
  28. *****************************************************************************/
  29. #include <linux/etherdevice.h>
  30. #include <linux/sched.h>
  31. #include <linux/slab.h>
  32. #include <linux/export.h>
  33. #include <net/mac80211.h>
  34. #include "iwl-eeprom.h"
  35. #include "iwl-dev.h"
  36. #include "iwl-core.h"
  37. #include "iwl-sta.h"
  38. #include "iwl-io.h"
  39. #include "iwl-helpers.h"
  40. /**
  41. * iwl_legacy_txq_update_write_ptr - Send new write index to hardware
  42. */
  43. void
  44. iwl_legacy_txq_update_write_ptr(struct iwl_priv *priv, struct iwl_tx_queue *txq)
  45. {
  46. u32 reg = 0;
  47. int txq_id = txq->q.id;
  48. if (txq->need_update == 0)
  49. return;
  50. /* if we're trying to save power */
  51. if (test_bit(STATUS_POWER_PMI, &priv->status)) {
  52. /* wake up nic if it's powered down ...
  53. * uCode will wake up, and interrupt us again, so next
  54. * time we'll skip this part. */
  55. reg = iwl_read32(priv, CSR_UCODE_DRV_GP1);
  56. if (reg & CSR_UCODE_DRV_GP1_BIT_MAC_SLEEP) {
  57. IWL_DEBUG_INFO(priv,
  58. "Tx queue %d requesting wakeup,"
  59. " GP1 = 0x%x\n", txq_id, reg);
  60. iwl_legacy_set_bit(priv, CSR_GP_CNTRL,
  61. CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ);
  62. return;
  63. }
  64. iwl_legacy_write_direct32(priv, HBUS_TARG_WRPTR,
  65. txq->q.write_ptr | (txq_id << 8));
  66. /*
  67. * else not in power-save mode,
  68. * uCode will never sleep when we're
  69. * trying to tx (during RFKILL, we're not trying to tx).
  70. */
  71. } else
  72. iwl_write32(priv, HBUS_TARG_WRPTR,
  73. txq->q.write_ptr | (txq_id << 8));
  74. txq->need_update = 0;
  75. }
  76. EXPORT_SYMBOL(iwl_legacy_txq_update_write_ptr);
  77. /**
  78. * iwl_legacy_tx_queue_unmap - Unmap any remaining DMA mappings and free skb's
  79. */
  80. void iwl_legacy_tx_queue_unmap(struct iwl_priv *priv, int txq_id)
  81. {
  82. struct iwl_tx_queue *txq = &priv->txq[txq_id];
  83. struct iwl_queue *q = &txq->q;
  84. if (q->n_bd == 0)
  85. return;
  86. while (q->write_ptr != q->read_ptr) {
  87. priv->cfg->ops->lib->txq_free_tfd(priv, txq);
  88. q->read_ptr = iwl_legacy_queue_inc_wrap(q->read_ptr, q->n_bd);
  89. }
  90. }
  91. EXPORT_SYMBOL(iwl_legacy_tx_queue_unmap);
  92. /**
  93. * iwl_legacy_tx_queue_free - Deallocate DMA queue.
  94. * @txq: Transmit queue to deallocate.
  95. *
  96. * Empty queue by removing and destroying all BD's.
  97. * Free all buffers.
  98. * 0-fill, but do not free "txq" descriptor structure.
  99. */
  100. void iwl_legacy_tx_queue_free(struct iwl_priv *priv, int txq_id)
  101. {
  102. struct iwl_tx_queue *txq = &priv->txq[txq_id];
  103. struct device *dev = &priv->pci_dev->dev;
  104. int i;
  105. iwl_legacy_tx_queue_unmap(priv, txq_id);
  106. /* De-alloc array of command/tx buffers */
  107. for (i = 0; i < TFD_TX_CMD_SLOTS; i++)
  108. kfree(txq->cmd[i]);
  109. /* De-alloc circular buffer of TFDs */
  110. if (txq->q.n_bd)
  111. dma_free_coherent(dev, priv->hw_params.tfd_size *
  112. txq->q.n_bd, txq->tfds, txq->q.dma_addr);
  113. /* De-alloc array of per-TFD driver data */
  114. kfree(txq->txb);
  115. txq->txb = NULL;
  116. /* deallocate arrays */
  117. kfree(txq->cmd);
  118. kfree(txq->meta);
  119. txq->cmd = NULL;
  120. txq->meta = NULL;
  121. /* 0-fill queue descriptor structure */
  122. memset(txq, 0, sizeof(*txq));
  123. }
  124. EXPORT_SYMBOL(iwl_legacy_tx_queue_free);
  125. /**
  126. * iwl_cmd_queue_unmap - Unmap any remaining DMA mappings from command queue
  127. */
  128. void iwl_legacy_cmd_queue_unmap(struct iwl_priv *priv)
  129. {
  130. struct iwl_tx_queue *txq = &priv->txq[priv->cmd_queue];
  131. struct iwl_queue *q = &txq->q;
  132. int i;
  133. if (q->n_bd == 0)
  134. return;
  135. while (q->read_ptr != q->write_ptr) {
  136. i = iwl_legacy_get_cmd_index(q, q->read_ptr, 0);
  137. if (txq->meta[i].flags & CMD_MAPPED) {
  138. pci_unmap_single(priv->pci_dev,
  139. dma_unmap_addr(&txq->meta[i], mapping),
  140. dma_unmap_len(&txq->meta[i], len),
  141. PCI_DMA_BIDIRECTIONAL);
  142. txq->meta[i].flags = 0;
  143. }
  144. q->read_ptr = iwl_legacy_queue_inc_wrap(q->read_ptr, q->n_bd);
  145. }
  146. i = q->n_window;
  147. if (txq->meta[i].flags & CMD_MAPPED) {
  148. pci_unmap_single(priv->pci_dev,
  149. dma_unmap_addr(&txq->meta[i], mapping),
  150. dma_unmap_len(&txq->meta[i], len),
  151. PCI_DMA_BIDIRECTIONAL);
  152. txq->meta[i].flags = 0;
  153. }
  154. }
  155. EXPORT_SYMBOL(iwl_legacy_cmd_queue_unmap);
  156. /**
  157. * iwl_legacy_cmd_queue_free - Deallocate DMA queue.
  158. * @txq: Transmit queue to deallocate.
  159. *
  160. * Empty queue by removing and destroying all BD's.
  161. * Free all buffers.
  162. * 0-fill, but do not free "txq" descriptor structure.
  163. */
  164. void iwl_legacy_cmd_queue_free(struct iwl_priv *priv)
  165. {
  166. struct iwl_tx_queue *txq = &priv->txq[priv->cmd_queue];
  167. struct device *dev = &priv->pci_dev->dev;
  168. int i;
  169. iwl_legacy_cmd_queue_unmap(priv);
  170. /* De-alloc array of command/tx buffers */
  171. for (i = 0; i <= TFD_CMD_SLOTS; i++)
  172. kfree(txq->cmd[i]);
  173. /* De-alloc circular buffer of TFDs */
  174. if (txq->q.n_bd)
  175. dma_free_coherent(dev, priv->hw_params.tfd_size * txq->q.n_bd,
  176. txq->tfds, txq->q.dma_addr);
  177. /* deallocate arrays */
  178. kfree(txq->cmd);
  179. kfree(txq->meta);
  180. txq->cmd = NULL;
  181. txq->meta = NULL;
  182. /* 0-fill queue descriptor structure */
  183. memset(txq, 0, sizeof(*txq));
  184. }
  185. EXPORT_SYMBOL(iwl_legacy_cmd_queue_free);
  186. /*************** DMA-QUEUE-GENERAL-FUNCTIONS *****
  187. * DMA services
  188. *
  189. * Theory of operation
  190. *
  191. * A Tx or Rx queue resides in host DRAM, and is comprised of a circular buffer
  192. * of buffer descriptors, each of which points to one or more data buffers for
  193. * the device to read from or fill. Driver and device exchange status of each
  194. * queue via "read" and "write" pointers. Driver keeps minimum of 2 empty
  195. * entries in each circular buffer, to protect against confusing empty and full
  196. * queue states.
  197. *
  198. * The device reads or writes the data in the queues via the device's several
  199. * DMA/FIFO channels. Each queue is mapped to a single DMA channel.
  200. *
  201. * For Tx queue, there are low mark and high mark limits. If, after queuing
  202. * the packet for Tx, free space become < low mark, Tx queue stopped. When
  203. * reclaiming packets (on 'tx done IRQ), if free space become > high mark,
  204. * Tx queue resumed.
  205. *
  206. * See more detailed info in iwl-4965-hw.h.
  207. ***************************************************/
  208. int iwl_legacy_queue_space(const struct iwl_queue *q)
  209. {
  210. int s = q->read_ptr - q->write_ptr;
  211. if (q->read_ptr > q->write_ptr)
  212. s -= q->n_bd;
  213. if (s <= 0)
  214. s += q->n_window;
  215. /* keep some reserve to not confuse empty and full situations */
  216. s -= 2;
  217. if (s < 0)
  218. s = 0;
  219. return s;
  220. }
  221. EXPORT_SYMBOL(iwl_legacy_queue_space);
  222. /**
  223. * iwl_legacy_queue_init - Initialize queue's high/low-water and read/write indexes
  224. */
  225. static int iwl_legacy_queue_init(struct iwl_priv *priv, struct iwl_queue *q,
  226. int count, int slots_num, u32 id)
  227. {
  228. q->n_bd = count;
  229. q->n_window = slots_num;
  230. q->id = id;
  231. /* count must be power-of-two size, otherwise iwl_legacy_queue_inc_wrap
  232. * and iwl_legacy_queue_dec_wrap are broken. */
  233. BUG_ON(!is_power_of_2(count));
  234. /* slots_num must be power-of-two size, otherwise
  235. * iwl_legacy_get_cmd_index is broken. */
  236. BUG_ON(!is_power_of_2(slots_num));
  237. q->low_mark = q->n_window / 4;
  238. if (q->low_mark < 4)
  239. q->low_mark = 4;
  240. q->high_mark = q->n_window / 8;
  241. if (q->high_mark < 2)
  242. q->high_mark = 2;
  243. q->write_ptr = q->read_ptr = 0;
  244. return 0;
  245. }
  246. /**
  247. * iwl_legacy_tx_queue_alloc - Alloc driver data and TFD CB for one Tx/cmd queue
  248. */
  249. static int iwl_legacy_tx_queue_alloc(struct iwl_priv *priv,
  250. struct iwl_tx_queue *txq, u32 id)
  251. {
  252. struct device *dev = &priv->pci_dev->dev;
  253. size_t tfd_sz = priv->hw_params.tfd_size * TFD_QUEUE_SIZE_MAX;
  254. /* Driver private data, only for Tx (not command) queues,
  255. * not shared with device. */
  256. if (id != priv->cmd_queue) {
  257. txq->txb = kzalloc(sizeof(txq->txb[0]) *
  258. TFD_QUEUE_SIZE_MAX, GFP_KERNEL);
  259. if (!txq->txb) {
  260. IWL_ERR(priv, "kmalloc for auxiliary BD "
  261. "structures failed\n");
  262. goto error;
  263. }
  264. } else {
  265. txq->txb = NULL;
  266. }
  267. /* Circular buffer of transmit frame descriptors (TFDs),
  268. * shared with device */
  269. txq->tfds = dma_alloc_coherent(dev, tfd_sz, &txq->q.dma_addr,
  270. GFP_KERNEL);
  271. if (!txq->tfds) {
  272. IWL_ERR(priv, "pci_alloc_consistent(%zd) failed\n", tfd_sz);
  273. goto error;
  274. }
  275. txq->q.id = id;
  276. return 0;
  277. error:
  278. kfree(txq->txb);
  279. txq->txb = NULL;
  280. return -ENOMEM;
  281. }
  282. /**
  283. * iwl_legacy_tx_queue_init - Allocate and initialize one tx/cmd queue
  284. */
  285. int iwl_legacy_tx_queue_init(struct iwl_priv *priv, struct iwl_tx_queue *txq,
  286. int slots_num, u32 txq_id)
  287. {
  288. int i, len;
  289. int ret;
  290. int actual_slots = slots_num;
  291. /*
  292. * Alloc buffer array for commands (Tx or other types of commands).
  293. * For the command queue (#4/#9), allocate command space + one big
  294. * command for scan, since scan command is very huge; the system will
  295. * not have two scans at the same time, so only one is needed.
  296. * For normal Tx queues (all other queues), no super-size command
  297. * space is needed.
  298. */
  299. if (txq_id == priv->cmd_queue)
  300. actual_slots++;
  301. txq->meta = kzalloc(sizeof(struct iwl_cmd_meta) * actual_slots,
  302. GFP_KERNEL);
  303. txq->cmd = kzalloc(sizeof(struct iwl_device_cmd *) * actual_slots,
  304. GFP_KERNEL);
  305. if (!txq->meta || !txq->cmd)
  306. goto out_free_arrays;
  307. len = sizeof(struct iwl_device_cmd);
  308. for (i = 0; i < actual_slots; i++) {
  309. /* only happens for cmd queue */
  310. if (i == slots_num)
  311. len = IWL_MAX_CMD_SIZE;
  312. txq->cmd[i] = kmalloc(len, GFP_KERNEL);
  313. if (!txq->cmd[i])
  314. goto err;
  315. }
  316. /* Alloc driver data array and TFD circular buffer */
  317. ret = iwl_legacy_tx_queue_alloc(priv, txq, txq_id);
  318. if (ret)
  319. goto err;
  320. txq->need_update = 0;
  321. /*
  322. * For the default queues 0-3, set up the swq_id
  323. * already -- all others need to get one later
  324. * (if they need one at all).
  325. */
  326. if (txq_id < 4)
  327. iwl_legacy_set_swq_id(txq, txq_id, txq_id);
  328. /* TFD_QUEUE_SIZE_MAX must be power-of-two size, otherwise
  329. * iwl_legacy_queue_inc_wrap and iwl_legacy_queue_dec_wrap are broken. */
  330. BUILD_BUG_ON(TFD_QUEUE_SIZE_MAX & (TFD_QUEUE_SIZE_MAX - 1));
  331. /* Initialize queue's high/low-water marks, and head/tail indexes */
  332. iwl_legacy_queue_init(priv, &txq->q,
  333. TFD_QUEUE_SIZE_MAX, slots_num, txq_id);
  334. /* Tell device where to find queue */
  335. priv->cfg->ops->lib->txq_init(priv, txq);
  336. return 0;
  337. err:
  338. for (i = 0; i < actual_slots; i++)
  339. kfree(txq->cmd[i]);
  340. out_free_arrays:
  341. kfree(txq->meta);
  342. kfree(txq->cmd);
  343. return -ENOMEM;
  344. }
  345. EXPORT_SYMBOL(iwl_legacy_tx_queue_init);
  346. void iwl_legacy_tx_queue_reset(struct iwl_priv *priv, struct iwl_tx_queue *txq,
  347. int slots_num, u32 txq_id)
  348. {
  349. int actual_slots = slots_num;
  350. if (txq_id == priv->cmd_queue)
  351. actual_slots++;
  352. memset(txq->meta, 0, sizeof(struct iwl_cmd_meta) * actual_slots);
  353. txq->need_update = 0;
  354. /* Initialize queue's high/low-water marks, and head/tail indexes */
  355. iwl_legacy_queue_init(priv, &txq->q,
  356. TFD_QUEUE_SIZE_MAX, slots_num, txq_id);
  357. /* Tell device where to find queue */
  358. priv->cfg->ops->lib->txq_init(priv, txq);
  359. }
  360. EXPORT_SYMBOL(iwl_legacy_tx_queue_reset);
  361. /*************** HOST COMMAND QUEUE FUNCTIONS *****/
  362. /**
  363. * iwl_legacy_enqueue_hcmd - enqueue a uCode command
  364. * @priv: device private data point
  365. * @cmd: a point to the ucode command structure
  366. *
  367. * The function returns < 0 values to indicate the operation is
  368. * failed. On success, it turns the index (> 0) of command in the
  369. * command queue.
  370. */
  371. int iwl_legacy_enqueue_hcmd(struct iwl_priv *priv, struct iwl_host_cmd *cmd)
  372. {
  373. struct iwl_tx_queue *txq = &priv->txq[priv->cmd_queue];
  374. struct iwl_queue *q = &txq->q;
  375. struct iwl_device_cmd *out_cmd;
  376. struct iwl_cmd_meta *out_meta;
  377. dma_addr_t phys_addr;
  378. unsigned long flags;
  379. int len;
  380. u32 idx;
  381. u16 fix_size;
  382. cmd->len = priv->cfg->ops->utils->get_hcmd_size(cmd->id, cmd->len);
  383. fix_size = (u16)(cmd->len + sizeof(out_cmd->hdr));
  384. /* If any of the command structures end up being larger than
  385. * the TFD_MAX_PAYLOAD_SIZE, and it sent as a 'small' command then
  386. * we will need to increase the size of the TFD entries
  387. * Also, check to see if command buffer should not exceed the size
  388. * of device_cmd and max_cmd_size. */
  389. BUG_ON((fix_size > TFD_MAX_PAYLOAD_SIZE) &&
  390. !(cmd->flags & CMD_SIZE_HUGE));
  391. BUG_ON(fix_size > IWL_MAX_CMD_SIZE);
  392. if (iwl_legacy_is_rfkill(priv) || iwl_legacy_is_ctkill(priv)) {
  393. IWL_WARN(priv, "Not sending command - %s KILL\n",
  394. iwl_legacy_is_rfkill(priv) ? "RF" : "CT");
  395. return -EIO;
  396. }
  397. spin_lock_irqsave(&priv->hcmd_lock, flags);
  398. if (iwl_legacy_queue_space(q) < ((cmd->flags & CMD_ASYNC) ? 2 : 1)) {
  399. spin_unlock_irqrestore(&priv->hcmd_lock, flags);
  400. IWL_ERR(priv, "Restarting adapter due to command queue full\n");
  401. queue_work(priv->workqueue, &priv->restart);
  402. return -ENOSPC;
  403. }
  404. idx = iwl_legacy_get_cmd_index(q, q->write_ptr, cmd->flags & CMD_SIZE_HUGE);
  405. out_cmd = txq->cmd[idx];
  406. out_meta = &txq->meta[idx];
  407. if (WARN_ON(out_meta->flags & CMD_MAPPED)) {
  408. spin_unlock_irqrestore(&priv->hcmd_lock, flags);
  409. return -ENOSPC;
  410. }
  411. memset(out_meta, 0, sizeof(*out_meta)); /* re-initialize to NULL */
  412. out_meta->flags = cmd->flags | CMD_MAPPED;
  413. if (cmd->flags & CMD_WANT_SKB)
  414. out_meta->source = cmd;
  415. if (cmd->flags & CMD_ASYNC)
  416. out_meta->callback = cmd->callback;
  417. out_cmd->hdr.cmd = cmd->id;
  418. memcpy(&out_cmd->cmd.payload, cmd->data, cmd->len);
  419. /* At this point, the out_cmd now has all of the incoming cmd
  420. * information */
  421. out_cmd->hdr.flags = 0;
  422. out_cmd->hdr.sequence = cpu_to_le16(QUEUE_TO_SEQ(priv->cmd_queue) |
  423. INDEX_TO_SEQ(q->write_ptr));
  424. if (cmd->flags & CMD_SIZE_HUGE)
  425. out_cmd->hdr.sequence |= SEQ_HUGE_FRAME;
  426. len = sizeof(struct iwl_device_cmd);
  427. if (idx == TFD_CMD_SLOTS)
  428. len = IWL_MAX_CMD_SIZE;
  429. #ifdef CONFIG_IWLWIFI_LEGACY_DEBUG
  430. switch (out_cmd->hdr.cmd) {
  431. case REPLY_TX_LINK_QUALITY_CMD:
  432. case SENSITIVITY_CMD:
  433. IWL_DEBUG_HC_DUMP(priv,
  434. "Sending command %s (#%x), seq: 0x%04X, "
  435. "%d bytes at %d[%d]:%d\n",
  436. iwl_legacy_get_cmd_string(out_cmd->hdr.cmd),
  437. out_cmd->hdr.cmd,
  438. le16_to_cpu(out_cmd->hdr.sequence), fix_size,
  439. q->write_ptr, idx, priv->cmd_queue);
  440. break;
  441. default:
  442. IWL_DEBUG_HC(priv, "Sending command %s (#%x), seq: 0x%04X, "
  443. "%d bytes at %d[%d]:%d\n",
  444. iwl_legacy_get_cmd_string(out_cmd->hdr.cmd),
  445. out_cmd->hdr.cmd,
  446. le16_to_cpu(out_cmd->hdr.sequence), fix_size,
  447. q->write_ptr, idx, priv->cmd_queue);
  448. }
  449. #endif
  450. txq->need_update = 1;
  451. if (priv->cfg->ops->lib->txq_update_byte_cnt_tbl)
  452. /* Set up entry in queue's byte count circular buffer */
  453. priv->cfg->ops->lib->txq_update_byte_cnt_tbl(priv, txq, 0);
  454. phys_addr = pci_map_single(priv->pci_dev, &out_cmd->hdr,
  455. fix_size, PCI_DMA_BIDIRECTIONAL);
  456. dma_unmap_addr_set(out_meta, mapping, phys_addr);
  457. dma_unmap_len_set(out_meta, len, fix_size);
  458. trace_iwlwifi_legacy_dev_hcmd(priv, &out_cmd->hdr,
  459. fix_size, cmd->flags);
  460. priv->cfg->ops->lib->txq_attach_buf_to_tfd(priv, txq,
  461. phys_addr, fix_size, 1,
  462. U32_PAD(cmd->len));
  463. /* Increment and update queue's write index */
  464. q->write_ptr = iwl_legacy_queue_inc_wrap(q->write_ptr, q->n_bd);
  465. iwl_legacy_txq_update_write_ptr(priv, txq);
  466. spin_unlock_irqrestore(&priv->hcmd_lock, flags);
  467. return idx;
  468. }
  469. /**
  470. * iwl_legacy_hcmd_queue_reclaim - Reclaim TX command queue entries already Tx'd
  471. *
  472. * When FW advances 'R' index, all entries between old and new 'R' index
  473. * need to be reclaimed. As result, some free space forms. If there is
  474. * enough free space (> low mark), wake the stack that feeds us.
  475. */
  476. static void iwl_legacy_hcmd_queue_reclaim(struct iwl_priv *priv, int txq_id,
  477. int idx, int cmd_idx)
  478. {
  479. struct iwl_tx_queue *txq = &priv->txq[txq_id];
  480. struct iwl_queue *q = &txq->q;
  481. int nfreed = 0;
  482. if ((idx >= q->n_bd) || (iwl_legacy_queue_used(q, idx) == 0)) {
  483. IWL_ERR(priv, "Read index for DMA queue txq id (%d), index %d, "
  484. "is out of range [0-%d] %d %d.\n", txq_id,
  485. idx, q->n_bd, q->write_ptr, q->read_ptr);
  486. return;
  487. }
  488. for (idx = iwl_legacy_queue_inc_wrap(idx, q->n_bd); q->read_ptr != idx;
  489. q->read_ptr = iwl_legacy_queue_inc_wrap(q->read_ptr, q->n_bd)) {
  490. if (nfreed++ > 0) {
  491. IWL_ERR(priv, "HCMD skipped: index (%d) %d %d\n", idx,
  492. q->write_ptr, q->read_ptr);
  493. queue_work(priv->workqueue, &priv->restart);
  494. }
  495. }
  496. }
  497. /**
  498. * iwl_legacy_tx_cmd_complete - Pull unused buffers off the queue and reclaim them
  499. * @rxb: Rx buffer to reclaim
  500. *
  501. * If an Rx buffer has an async callback associated with it the callback
  502. * will be executed. The attached skb (if present) will only be freed
  503. * if the callback returns 1
  504. */
  505. void
  506. iwl_legacy_tx_cmd_complete(struct iwl_priv *priv, struct iwl_rx_mem_buffer *rxb)
  507. {
  508. struct iwl_rx_packet *pkt = rxb_addr(rxb);
  509. u16 sequence = le16_to_cpu(pkt->hdr.sequence);
  510. int txq_id = SEQ_TO_QUEUE(sequence);
  511. int index = SEQ_TO_INDEX(sequence);
  512. int cmd_index;
  513. bool huge = !!(pkt->hdr.sequence & SEQ_HUGE_FRAME);
  514. struct iwl_device_cmd *cmd;
  515. struct iwl_cmd_meta *meta;
  516. struct iwl_tx_queue *txq = &priv->txq[priv->cmd_queue];
  517. unsigned long flags;
  518. /* If a Tx command is being handled and it isn't in the actual
  519. * command queue then there a command routing bug has been introduced
  520. * in the queue management code. */
  521. if (WARN(txq_id != priv->cmd_queue,
  522. "wrong command queue %d (should be %d), sequence 0x%X readp=%d writep=%d\n",
  523. txq_id, priv->cmd_queue, sequence,
  524. priv->txq[priv->cmd_queue].q.read_ptr,
  525. priv->txq[priv->cmd_queue].q.write_ptr)) {
  526. iwl_print_hex_error(priv, pkt, 32);
  527. return;
  528. }
  529. cmd_index = iwl_legacy_get_cmd_index(&txq->q, index, huge);
  530. cmd = txq->cmd[cmd_index];
  531. meta = &txq->meta[cmd_index];
  532. txq->time_stamp = jiffies;
  533. pci_unmap_single(priv->pci_dev,
  534. dma_unmap_addr(meta, mapping),
  535. dma_unmap_len(meta, len),
  536. PCI_DMA_BIDIRECTIONAL);
  537. /* Input error checking is done when commands are added to queue. */
  538. if (meta->flags & CMD_WANT_SKB) {
  539. meta->source->reply_page = (unsigned long)rxb_addr(rxb);
  540. rxb->page = NULL;
  541. } else if (meta->callback)
  542. meta->callback(priv, cmd, pkt);
  543. spin_lock_irqsave(&priv->hcmd_lock, flags);
  544. iwl_legacy_hcmd_queue_reclaim(priv, txq_id, index, cmd_index);
  545. if (!(meta->flags & CMD_ASYNC)) {
  546. clear_bit(STATUS_HCMD_ACTIVE, &priv->status);
  547. IWL_DEBUG_INFO(priv, "Clearing HCMD_ACTIVE for command %s\n",
  548. iwl_legacy_get_cmd_string(cmd->hdr.cmd));
  549. wake_up(&priv->wait_command_queue);
  550. }
  551. /* Mark as unmapped */
  552. meta->flags = 0;
  553. spin_unlock_irqrestore(&priv->hcmd_lock, flags);
  554. }
  555. EXPORT_SYMBOL(iwl_legacy_tx_cmd_complete);