recv.c 53 KB

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  1. /*
  2. * Copyright (c) 2008-2011 Atheros Communications Inc.
  3. *
  4. * Permission to use, copy, modify, and/or distribute this software for any
  5. * purpose with or without fee is hereby granted, provided that the above
  6. * copyright notice and this permission notice appear in all copies.
  7. *
  8. * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
  9. * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
  10. * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
  11. * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
  12. * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
  13. * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
  14. * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
  15. */
  16. #include <linux/dma-mapping.h>
  17. #include "ath9k.h"
  18. #include "ar9003_mac.h"
  19. #define SKB_CB_ATHBUF(__skb) (*((struct ath_buf **)__skb->cb))
  20. static inline bool ath_is_alt_ant_ratio_better(int alt_ratio, int maxdelta,
  21. int mindelta, int main_rssi_avg,
  22. int alt_rssi_avg, int pkt_count)
  23. {
  24. return (((alt_ratio >= ATH_ANT_DIV_COMB_ALT_ANT_RATIO2) &&
  25. (alt_rssi_avg > main_rssi_avg + maxdelta)) ||
  26. (alt_rssi_avg > main_rssi_avg + mindelta)) && (pkt_count > 50);
  27. }
  28. static inline bool ath_ant_div_comb_alt_check(u8 div_group, int alt_ratio,
  29. int curr_main_set, int curr_alt_set,
  30. int alt_rssi_avg, int main_rssi_avg)
  31. {
  32. bool result = false;
  33. switch (div_group) {
  34. case 0:
  35. if (alt_ratio > ATH_ANT_DIV_COMB_ALT_ANT_RATIO)
  36. result = true;
  37. break;
  38. case 1:
  39. case 2:
  40. if ((((curr_main_set == ATH_ANT_DIV_COMB_LNA2) &&
  41. (curr_alt_set == ATH_ANT_DIV_COMB_LNA1) &&
  42. (alt_rssi_avg >= (main_rssi_avg - 5))) ||
  43. ((curr_main_set == ATH_ANT_DIV_COMB_LNA1) &&
  44. (curr_alt_set == ATH_ANT_DIV_COMB_LNA2) &&
  45. (alt_rssi_avg >= (main_rssi_avg - 2)))) &&
  46. (alt_rssi_avg >= 4))
  47. result = true;
  48. else
  49. result = false;
  50. break;
  51. }
  52. return result;
  53. }
  54. static inline bool ath9k_check_auto_sleep(struct ath_softc *sc)
  55. {
  56. return sc->ps_enabled &&
  57. (sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_AUTOSLEEP);
  58. }
  59. /*
  60. * Setup and link descriptors.
  61. *
  62. * 11N: we can no longer afford to self link the last descriptor.
  63. * MAC acknowledges BA status as long as it copies frames to host
  64. * buffer (or rx fifo). This can incorrectly acknowledge packets
  65. * to a sender if last desc is self-linked.
  66. */
  67. static void ath_rx_buf_link(struct ath_softc *sc, struct ath_buf *bf)
  68. {
  69. struct ath_hw *ah = sc->sc_ah;
  70. struct ath_common *common = ath9k_hw_common(ah);
  71. struct ath_desc *ds;
  72. struct sk_buff *skb;
  73. ATH_RXBUF_RESET(bf);
  74. ds = bf->bf_desc;
  75. ds->ds_link = 0; /* link to null */
  76. ds->ds_data = bf->bf_buf_addr;
  77. /* virtual addr of the beginning of the buffer. */
  78. skb = bf->bf_mpdu;
  79. BUG_ON(skb == NULL);
  80. ds->ds_vdata = skb->data;
  81. /*
  82. * setup rx descriptors. The rx_bufsize here tells the hardware
  83. * how much data it can DMA to us and that we are prepared
  84. * to process
  85. */
  86. ath9k_hw_setuprxdesc(ah, ds,
  87. common->rx_bufsize,
  88. 0);
  89. if (sc->rx.rxlink == NULL)
  90. ath9k_hw_putrxbuf(ah, bf->bf_daddr);
  91. else
  92. *sc->rx.rxlink = bf->bf_daddr;
  93. sc->rx.rxlink = &ds->ds_link;
  94. }
  95. static void ath_setdefantenna(struct ath_softc *sc, u32 antenna)
  96. {
  97. /* XXX block beacon interrupts */
  98. ath9k_hw_setantenna(sc->sc_ah, antenna);
  99. sc->rx.defant = antenna;
  100. sc->rx.rxotherant = 0;
  101. }
  102. static void ath_opmode_init(struct ath_softc *sc)
  103. {
  104. struct ath_hw *ah = sc->sc_ah;
  105. struct ath_common *common = ath9k_hw_common(ah);
  106. u32 rfilt, mfilt[2];
  107. /* configure rx filter */
  108. rfilt = ath_calcrxfilter(sc);
  109. ath9k_hw_setrxfilter(ah, rfilt);
  110. /* configure bssid mask */
  111. ath_hw_setbssidmask(common);
  112. /* configure operational mode */
  113. ath9k_hw_setopmode(ah);
  114. /* calculate and install multicast filter */
  115. mfilt[0] = mfilt[1] = ~0;
  116. ath9k_hw_setmcastfilter(ah, mfilt[0], mfilt[1]);
  117. }
  118. static bool ath_rx_edma_buf_link(struct ath_softc *sc,
  119. enum ath9k_rx_qtype qtype)
  120. {
  121. struct ath_hw *ah = sc->sc_ah;
  122. struct ath_rx_edma *rx_edma;
  123. struct sk_buff *skb;
  124. struct ath_buf *bf;
  125. rx_edma = &sc->rx.rx_edma[qtype];
  126. if (skb_queue_len(&rx_edma->rx_fifo) >= rx_edma->rx_fifo_hwsize)
  127. return false;
  128. bf = list_first_entry(&sc->rx.rxbuf, struct ath_buf, list);
  129. list_del_init(&bf->list);
  130. skb = bf->bf_mpdu;
  131. ATH_RXBUF_RESET(bf);
  132. memset(skb->data, 0, ah->caps.rx_status_len);
  133. dma_sync_single_for_device(sc->dev, bf->bf_buf_addr,
  134. ah->caps.rx_status_len, DMA_TO_DEVICE);
  135. SKB_CB_ATHBUF(skb) = bf;
  136. ath9k_hw_addrxbuf_edma(ah, bf->bf_buf_addr, qtype);
  137. skb_queue_tail(&rx_edma->rx_fifo, skb);
  138. return true;
  139. }
  140. static void ath_rx_addbuffer_edma(struct ath_softc *sc,
  141. enum ath9k_rx_qtype qtype, int size)
  142. {
  143. struct ath_common *common = ath9k_hw_common(sc->sc_ah);
  144. u32 nbuf = 0;
  145. if (list_empty(&sc->rx.rxbuf)) {
  146. ath_dbg(common, ATH_DBG_QUEUE, "No free rx buf available\n");
  147. return;
  148. }
  149. while (!list_empty(&sc->rx.rxbuf)) {
  150. nbuf++;
  151. if (!ath_rx_edma_buf_link(sc, qtype))
  152. break;
  153. if (nbuf >= size)
  154. break;
  155. }
  156. }
  157. static void ath_rx_remove_buffer(struct ath_softc *sc,
  158. enum ath9k_rx_qtype qtype)
  159. {
  160. struct ath_buf *bf;
  161. struct ath_rx_edma *rx_edma;
  162. struct sk_buff *skb;
  163. rx_edma = &sc->rx.rx_edma[qtype];
  164. while ((skb = skb_dequeue(&rx_edma->rx_fifo)) != NULL) {
  165. bf = SKB_CB_ATHBUF(skb);
  166. BUG_ON(!bf);
  167. list_add_tail(&bf->list, &sc->rx.rxbuf);
  168. }
  169. }
  170. static void ath_rx_edma_cleanup(struct ath_softc *sc)
  171. {
  172. struct ath_hw *ah = sc->sc_ah;
  173. struct ath_common *common = ath9k_hw_common(ah);
  174. struct ath_buf *bf;
  175. ath_rx_remove_buffer(sc, ATH9K_RX_QUEUE_LP);
  176. ath_rx_remove_buffer(sc, ATH9K_RX_QUEUE_HP);
  177. list_for_each_entry(bf, &sc->rx.rxbuf, list) {
  178. if (bf->bf_mpdu) {
  179. dma_unmap_single(sc->dev, bf->bf_buf_addr,
  180. common->rx_bufsize,
  181. DMA_BIDIRECTIONAL);
  182. dev_kfree_skb_any(bf->bf_mpdu);
  183. bf->bf_buf_addr = 0;
  184. bf->bf_mpdu = NULL;
  185. }
  186. }
  187. INIT_LIST_HEAD(&sc->rx.rxbuf);
  188. kfree(sc->rx.rx_bufptr);
  189. sc->rx.rx_bufptr = NULL;
  190. }
  191. static void ath_rx_edma_init_queue(struct ath_rx_edma *rx_edma, int size)
  192. {
  193. skb_queue_head_init(&rx_edma->rx_fifo);
  194. skb_queue_head_init(&rx_edma->rx_buffers);
  195. rx_edma->rx_fifo_hwsize = size;
  196. }
  197. static int ath_rx_edma_init(struct ath_softc *sc, int nbufs)
  198. {
  199. struct ath_common *common = ath9k_hw_common(sc->sc_ah);
  200. struct ath_hw *ah = sc->sc_ah;
  201. struct sk_buff *skb;
  202. struct ath_buf *bf;
  203. int error = 0, i;
  204. u32 size;
  205. ath9k_hw_set_rx_bufsize(ah, common->rx_bufsize -
  206. ah->caps.rx_status_len);
  207. ath_rx_edma_init_queue(&sc->rx.rx_edma[ATH9K_RX_QUEUE_LP],
  208. ah->caps.rx_lp_qdepth);
  209. ath_rx_edma_init_queue(&sc->rx.rx_edma[ATH9K_RX_QUEUE_HP],
  210. ah->caps.rx_hp_qdepth);
  211. size = sizeof(struct ath_buf) * nbufs;
  212. bf = kzalloc(size, GFP_KERNEL);
  213. if (!bf)
  214. return -ENOMEM;
  215. INIT_LIST_HEAD(&sc->rx.rxbuf);
  216. sc->rx.rx_bufptr = bf;
  217. for (i = 0; i < nbufs; i++, bf++) {
  218. skb = ath_rxbuf_alloc(common, common->rx_bufsize, GFP_KERNEL);
  219. if (!skb) {
  220. error = -ENOMEM;
  221. goto rx_init_fail;
  222. }
  223. memset(skb->data, 0, common->rx_bufsize);
  224. bf->bf_mpdu = skb;
  225. bf->bf_buf_addr = dma_map_single(sc->dev, skb->data,
  226. common->rx_bufsize,
  227. DMA_BIDIRECTIONAL);
  228. if (unlikely(dma_mapping_error(sc->dev,
  229. bf->bf_buf_addr))) {
  230. dev_kfree_skb_any(skb);
  231. bf->bf_mpdu = NULL;
  232. bf->bf_buf_addr = 0;
  233. ath_err(common,
  234. "dma_mapping_error() on RX init\n");
  235. error = -ENOMEM;
  236. goto rx_init_fail;
  237. }
  238. list_add_tail(&bf->list, &sc->rx.rxbuf);
  239. }
  240. return 0;
  241. rx_init_fail:
  242. ath_rx_edma_cleanup(sc);
  243. return error;
  244. }
  245. static void ath_edma_start_recv(struct ath_softc *sc)
  246. {
  247. spin_lock_bh(&sc->rx.rxbuflock);
  248. ath9k_hw_rxena(sc->sc_ah);
  249. ath_rx_addbuffer_edma(sc, ATH9K_RX_QUEUE_HP,
  250. sc->rx.rx_edma[ATH9K_RX_QUEUE_HP].rx_fifo_hwsize);
  251. ath_rx_addbuffer_edma(sc, ATH9K_RX_QUEUE_LP,
  252. sc->rx.rx_edma[ATH9K_RX_QUEUE_LP].rx_fifo_hwsize);
  253. ath_opmode_init(sc);
  254. ath9k_hw_startpcureceive(sc->sc_ah, (sc->sc_flags & SC_OP_OFFCHANNEL));
  255. spin_unlock_bh(&sc->rx.rxbuflock);
  256. }
  257. static void ath_edma_stop_recv(struct ath_softc *sc)
  258. {
  259. ath_rx_remove_buffer(sc, ATH9K_RX_QUEUE_HP);
  260. ath_rx_remove_buffer(sc, ATH9K_RX_QUEUE_LP);
  261. }
  262. int ath_rx_init(struct ath_softc *sc, int nbufs)
  263. {
  264. struct ath_common *common = ath9k_hw_common(sc->sc_ah);
  265. struct sk_buff *skb;
  266. struct ath_buf *bf;
  267. int error = 0;
  268. spin_lock_init(&sc->sc_pcu_lock);
  269. sc->sc_flags &= ~SC_OP_RXFLUSH;
  270. spin_lock_init(&sc->rx.rxbuflock);
  271. common->rx_bufsize = IEEE80211_MAX_MPDU_LEN / 2 +
  272. sc->sc_ah->caps.rx_status_len;
  273. if (sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_EDMA) {
  274. return ath_rx_edma_init(sc, nbufs);
  275. } else {
  276. ath_dbg(common, ATH_DBG_CONFIG, "cachelsz %u rxbufsize %u\n",
  277. common->cachelsz, common->rx_bufsize);
  278. /* Initialize rx descriptors */
  279. error = ath_descdma_setup(sc, &sc->rx.rxdma, &sc->rx.rxbuf,
  280. "rx", nbufs, 1, 0);
  281. if (error != 0) {
  282. ath_err(common,
  283. "failed to allocate rx descriptors: %d\n",
  284. error);
  285. goto err;
  286. }
  287. list_for_each_entry(bf, &sc->rx.rxbuf, list) {
  288. skb = ath_rxbuf_alloc(common, common->rx_bufsize,
  289. GFP_KERNEL);
  290. if (skb == NULL) {
  291. error = -ENOMEM;
  292. goto err;
  293. }
  294. bf->bf_mpdu = skb;
  295. bf->bf_buf_addr = dma_map_single(sc->dev, skb->data,
  296. common->rx_bufsize,
  297. DMA_FROM_DEVICE);
  298. if (unlikely(dma_mapping_error(sc->dev,
  299. bf->bf_buf_addr))) {
  300. dev_kfree_skb_any(skb);
  301. bf->bf_mpdu = NULL;
  302. bf->bf_buf_addr = 0;
  303. ath_err(common,
  304. "dma_mapping_error() on RX init\n");
  305. error = -ENOMEM;
  306. goto err;
  307. }
  308. }
  309. sc->rx.rxlink = NULL;
  310. }
  311. err:
  312. if (error)
  313. ath_rx_cleanup(sc);
  314. return error;
  315. }
  316. void ath_rx_cleanup(struct ath_softc *sc)
  317. {
  318. struct ath_hw *ah = sc->sc_ah;
  319. struct ath_common *common = ath9k_hw_common(ah);
  320. struct sk_buff *skb;
  321. struct ath_buf *bf;
  322. if (sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_EDMA) {
  323. ath_rx_edma_cleanup(sc);
  324. return;
  325. } else {
  326. list_for_each_entry(bf, &sc->rx.rxbuf, list) {
  327. skb = bf->bf_mpdu;
  328. if (skb) {
  329. dma_unmap_single(sc->dev, bf->bf_buf_addr,
  330. common->rx_bufsize,
  331. DMA_FROM_DEVICE);
  332. dev_kfree_skb(skb);
  333. bf->bf_buf_addr = 0;
  334. bf->bf_mpdu = NULL;
  335. }
  336. }
  337. if (sc->rx.rxdma.dd_desc_len != 0)
  338. ath_descdma_cleanup(sc, &sc->rx.rxdma, &sc->rx.rxbuf);
  339. }
  340. }
  341. /*
  342. * Calculate the receive filter according to the
  343. * operating mode and state:
  344. *
  345. * o always accept unicast, broadcast, and multicast traffic
  346. * o maintain current state of phy error reception (the hal
  347. * may enable phy error frames for noise immunity work)
  348. * o probe request frames are accepted only when operating in
  349. * hostap, adhoc, or monitor modes
  350. * o enable promiscuous mode according to the interface state
  351. * o accept beacons:
  352. * - when operating in adhoc mode so the 802.11 layer creates
  353. * node table entries for peers,
  354. * - when operating in station mode for collecting rssi data when
  355. * the station is otherwise quiet, or
  356. * - when operating as a repeater so we see repeater-sta beacons
  357. * - when scanning
  358. */
  359. u32 ath_calcrxfilter(struct ath_softc *sc)
  360. {
  361. u32 rfilt;
  362. rfilt = ATH9K_RX_FILTER_UCAST | ATH9K_RX_FILTER_BCAST
  363. | ATH9K_RX_FILTER_MCAST;
  364. if (sc->rx.rxfilter & FIF_PROBE_REQ)
  365. rfilt |= ATH9K_RX_FILTER_PROBEREQ;
  366. /*
  367. * Set promiscuous mode when FIF_PROMISC_IN_BSS is enabled for station
  368. * mode interface or when in monitor mode. AP mode does not need this
  369. * since it receives all in-BSS frames anyway.
  370. */
  371. if (sc->sc_ah->is_monitoring)
  372. rfilt |= ATH9K_RX_FILTER_PROM;
  373. if (sc->rx.rxfilter & FIF_CONTROL)
  374. rfilt |= ATH9K_RX_FILTER_CONTROL;
  375. if ((sc->sc_ah->opmode == NL80211_IFTYPE_STATION) &&
  376. (sc->nvifs <= 1) &&
  377. !(sc->rx.rxfilter & FIF_BCN_PRBRESP_PROMISC))
  378. rfilt |= ATH9K_RX_FILTER_MYBEACON;
  379. else
  380. rfilt |= ATH9K_RX_FILTER_BEACON;
  381. if ((sc->sc_ah->opmode == NL80211_IFTYPE_AP) ||
  382. (sc->rx.rxfilter & FIF_PSPOLL))
  383. rfilt |= ATH9K_RX_FILTER_PSPOLL;
  384. if (conf_is_ht(&sc->hw->conf))
  385. rfilt |= ATH9K_RX_FILTER_COMP_BAR;
  386. if (sc->nvifs > 1 || (sc->rx.rxfilter & FIF_OTHER_BSS)) {
  387. /* The following may also be needed for other older chips */
  388. if (sc->sc_ah->hw_version.macVersion == AR_SREV_VERSION_9160)
  389. rfilt |= ATH9K_RX_FILTER_PROM;
  390. rfilt |= ATH9K_RX_FILTER_MCAST_BCAST_ALL;
  391. }
  392. return rfilt;
  393. #undef RX_FILTER_PRESERVE
  394. }
  395. int ath_startrecv(struct ath_softc *sc)
  396. {
  397. struct ath_hw *ah = sc->sc_ah;
  398. struct ath_buf *bf, *tbf;
  399. if (ah->caps.hw_caps & ATH9K_HW_CAP_EDMA) {
  400. ath_edma_start_recv(sc);
  401. return 0;
  402. }
  403. spin_lock_bh(&sc->rx.rxbuflock);
  404. if (list_empty(&sc->rx.rxbuf))
  405. goto start_recv;
  406. sc->rx.rxlink = NULL;
  407. list_for_each_entry_safe(bf, tbf, &sc->rx.rxbuf, list) {
  408. ath_rx_buf_link(sc, bf);
  409. }
  410. /* We could have deleted elements so the list may be empty now */
  411. if (list_empty(&sc->rx.rxbuf))
  412. goto start_recv;
  413. bf = list_first_entry(&sc->rx.rxbuf, struct ath_buf, list);
  414. ath9k_hw_putrxbuf(ah, bf->bf_daddr);
  415. ath9k_hw_rxena(ah);
  416. start_recv:
  417. ath_opmode_init(sc);
  418. ath9k_hw_startpcureceive(ah, (sc->sc_flags & SC_OP_OFFCHANNEL));
  419. spin_unlock_bh(&sc->rx.rxbuflock);
  420. return 0;
  421. }
  422. bool ath_stoprecv(struct ath_softc *sc)
  423. {
  424. struct ath_hw *ah = sc->sc_ah;
  425. bool stopped, reset = false;
  426. spin_lock_bh(&sc->rx.rxbuflock);
  427. ath9k_hw_abortpcurecv(ah);
  428. ath9k_hw_setrxfilter(ah, 0);
  429. stopped = ath9k_hw_stopdmarecv(ah, &reset);
  430. if (sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_EDMA)
  431. ath_edma_stop_recv(sc);
  432. else
  433. sc->rx.rxlink = NULL;
  434. spin_unlock_bh(&sc->rx.rxbuflock);
  435. if (!(ah->ah_flags & AH_UNPLUGGED) &&
  436. unlikely(!stopped)) {
  437. ath_err(ath9k_hw_common(sc->sc_ah),
  438. "Could not stop RX, we could be "
  439. "confusing the DMA engine when we start RX up\n");
  440. ATH_DBG_WARN_ON_ONCE(!stopped);
  441. }
  442. return stopped && !reset;
  443. }
  444. void ath_flushrecv(struct ath_softc *sc)
  445. {
  446. sc->sc_flags |= SC_OP_RXFLUSH;
  447. if (sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_EDMA)
  448. ath_rx_tasklet(sc, 1, true);
  449. ath_rx_tasklet(sc, 1, false);
  450. sc->sc_flags &= ~SC_OP_RXFLUSH;
  451. }
  452. static bool ath_beacon_dtim_pending_cab(struct sk_buff *skb)
  453. {
  454. /* Check whether the Beacon frame has DTIM indicating buffered bc/mc */
  455. struct ieee80211_mgmt *mgmt;
  456. u8 *pos, *end, id, elen;
  457. struct ieee80211_tim_ie *tim;
  458. mgmt = (struct ieee80211_mgmt *)skb->data;
  459. pos = mgmt->u.beacon.variable;
  460. end = skb->data + skb->len;
  461. while (pos + 2 < end) {
  462. id = *pos++;
  463. elen = *pos++;
  464. if (pos + elen > end)
  465. break;
  466. if (id == WLAN_EID_TIM) {
  467. if (elen < sizeof(*tim))
  468. break;
  469. tim = (struct ieee80211_tim_ie *) pos;
  470. if (tim->dtim_count != 0)
  471. break;
  472. return tim->bitmap_ctrl & 0x01;
  473. }
  474. pos += elen;
  475. }
  476. return false;
  477. }
  478. static void ath_rx_ps_beacon(struct ath_softc *sc, struct sk_buff *skb)
  479. {
  480. struct ath_common *common = ath9k_hw_common(sc->sc_ah);
  481. if (skb->len < 24 + 8 + 2 + 2)
  482. return;
  483. sc->ps_flags &= ~PS_WAIT_FOR_BEACON;
  484. if (sc->ps_flags & PS_BEACON_SYNC) {
  485. sc->ps_flags &= ~PS_BEACON_SYNC;
  486. ath_dbg(common, ATH_DBG_PS,
  487. "Reconfigure Beacon timers based on timestamp from the AP\n");
  488. ath_set_beacon(sc);
  489. }
  490. if (ath_beacon_dtim_pending_cab(skb)) {
  491. /*
  492. * Remain awake waiting for buffered broadcast/multicast
  493. * frames. If the last broadcast/multicast frame is not
  494. * received properly, the next beacon frame will work as
  495. * a backup trigger for returning into NETWORK SLEEP state,
  496. * so we are waiting for it as well.
  497. */
  498. ath_dbg(common, ATH_DBG_PS,
  499. "Received DTIM beacon indicating buffered broadcast/multicast frame(s)\n");
  500. sc->ps_flags |= PS_WAIT_FOR_CAB | PS_WAIT_FOR_BEACON;
  501. return;
  502. }
  503. if (sc->ps_flags & PS_WAIT_FOR_CAB) {
  504. /*
  505. * This can happen if a broadcast frame is dropped or the AP
  506. * fails to send a frame indicating that all CAB frames have
  507. * been delivered.
  508. */
  509. sc->ps_flags &= ~PS_WAIT_FOR_CAB;
  510. ath_dbg(common, ATH_DBG_PS,
  511. "PS wait for CAB frames timed out\n");
  512. }
  513. }
  514. static void ath_rx_ps(struct ath_softc *sc, struct sk_buff *skb, bool mybeacon)
  515. {
  516. struct ieee80211_hdr *hdr;
  517. struct ath_common *common = ath9k_hw_common(sc->sc_ah);
  518. hdr = (struct ieee80211_hdr *)skb->data;
  519. /* Process Beacon and CAB receive in PS state */
  520. if (((sc->ps_flags & PS_WAIT_FOR_BEACON) || ath9k_check_auto_sleep(sc))
  521. && mybeacon)
  522. ath_rx_ps_beacon(sc, skb);
  523. else if ((sc->ps_flags & PS_WAIT_FOR_CAB) &&
  524. (ieee80211_is_data(hdr->frame_control) ||
  525. ieee80211_is_action(hdr->frame_control)) &&
  526. is_multicast_ether_addr(hdr->addr1) &&
  527. !ieee80211_has_moredata(hdr->frame_control)) {
  528. /*
  529. * No more broadcast/multicast frames to be received at this
  530. * point.
  531. */
  532. sc->ps_flags &= ~(PS_WAIT_FOR_CAB | PS_WAIT_FOR_BEACON);
  533. ath_dbg(common, ATH_DBG_PS,
  534. "All PS CAB frames received, back to sleep\n");
  535. } else if ((sc->ps_flags & PS_WAIT_FOR_PSPOLL_DATA) &&
  536. !is_multicast_ether_addr(hdr->addr1) &&
  537. !ieee80211_has_morefrags(hdr->frame_control)) {
  538. sc->ps_flags &= ~PS_WAIT_FOR_PSPOLL_DATA;
  539. ath_dbg(common, ATH_DBG_PS,
  540. "Going back to sleep after having received PS-Poll data (0x%lx)\n",
  541. sc->ps_flags & (PS_WAIT_FOR_BEACON |
  542. PS_WAIT_FOR_CAB |
  543. PS_WAIT_FOR_PSPOLL_DATA |
  544. PS_WAIT_FOR_TX_ACK));
  545. }
  546. }
  547. static bool ath_edma_get_buffers(struct ath_softc *sc,
  548. enum ath9k_rx_qtype qtype)
  549. {
  550. struct ath_rx_edma *rx_edma = &sc->rx.rx_edma[qtype];
  551. struct ath_hw *ah = sc->sc_ah;
  552. struct ath_common *common = ath9k_hw_common(ah);
  553. struct sk_buff *skb;
  554. struct ath_buf *bf;
  555. int ret;
  556. skb = skb_peek(&rx_edma->rx_fifo);
  557. if (!skb)
  558. return false;
  559. bf = SKB_CB_ATHBUF(skb);
  560. BUG_ON(!bf);
  561. dma_sync_single_for_cpu(sc->dev, bf->bf_buf_addr,
  562. common->rx_bufsize, DMA_FROM_DEVICE);
  563. ret = ath9k_hw_process_rxdesc_edma(ah, NULL, skb->data);
  564. if (ret == -EINPROGRESS) {
  565. /*let device gain the buffer again*/
  566. dma_sync_single_for_device(sc->dev, bf->bf_buf_addr,
  567. common->rx_bufsize, DMA_FROM_DEVICE);
  568. return false;
  569. }
  570. __skb_unlink(skb, &rx_edma->rx_fifo);
  571. if (ret == -EINVAL) {
  572. /* corrupt descriptor, skip this one and the following one */
  573. list_add_tail(&bf->list, &sc->rx.rxbuf);
  574. ath_rx_edma_buf_link(sc, qtype);
  575. skb = skb_peek(&rx_edma->rx_fifo);
  576. if (!skb)
  577. return true;
  578. bf = SKB_CB_ATHBUF(skb);
  579. BUG_ON(!bf);
  580. __skb_unlink(skb, &rx_edma->rx_fifo);
  581. list_add_tail(&bf->list, &sc->rx.rxbuf);
  582. ath_rx_edma_buf_link(sc, qtype);
  583. return true;
  584. }
  585. skb_queue_tail(&rx_edma->rx_buffers, skb);
  586. return true;
  587. }
  588. static struct ath_buf *ath_edma_get_next_rx_buf(struct ath_softc *sc,
  589. struct ath_rx_status *rs,
  590. enum ath9k_rx_qtype qtype)
  591. {
  592. struct ath_rx_edma *rx_edma = &sc->rx.rx_edma[qtype];
  593. struct sk_buff *skb;
  594. struct ath_buf *bf;
  595. while (ath_edma_get_buffers(sc, qtype));
  596. skb = __skb_dequeue(&rx_edma->rx_buffers);
  597. if (!skb)
  598. return NULL;
  599. bf = SKB_CB_ATHBUF(skb);
  600. ath9k_hw_process_rxdesc_edma(sc->sc_ah, rs, skb->data);
  601. return bf;
  602. }
  603. static struct ath_buf *ath_get_next_rx_buf(struct ath_softc *sc,
  604. struct ath_rx_status *rs)
  605. {
  606. struct ath_hw *ah = sc->sc_ah;
  607. struct ath_common *common = ath9k_hw_common(ah);
  608. struct ath_desc *ds;
  609. struct ath_buf *bf;
  610. int ret;
  611. if (list_empty(&sc->rx.rxbuf)) {
  612. sc->rx.rxlink = NULL;
  613. return NULL;
  614. }
  615. bf = list_first_entry(&sc->rx.rxbuf, struct ath_buf, list);
  616. ds = bf->bf_desc;
  617. /*
  618. * Must provide the virtual address of the current
  619. * descriptor, the physical address, and the virtual
  620. * address of the next descriptor in the h/w chain.
  621. * This allows the HAL to look ahead to see if the
  622. * hardware is done with a descriptor by checking the
  623. * done bit in the following descriptor and the address
  624. * of the current descriptor the DMA engine is working
  625. * on. All this is necessary because of our use of
  626. * a self-linked list to avoid rx overruns.
  627. */
  628. ret = ath9k_hw_rxprocdesc(ah, ds, rs);
  629. if (ret == -EINPROGRESS) {
  630. struct ath_rx_status trs;
  631. struct ath_buf *tbf;
  632. struct ath_desc *tds;
  633. memset(&trs, 0, sizeof(trs));
  634. if (list_is_last(&bf->list, &sc->rx.rxbuf)) {
  635. sc->rx.rxlink = NULL;
  636. return NULL;
  637. }
  638. tbf = list_entry(bf->list.next, struct ath_buf, list);
  639. /*
  640. * On some hardware the descriptor status words could
  641. * get corrupted, including the done bit. Because of
  642. * this, check if the next descriptor's done bit is
  643. * set or not.
  644. *
  645. * If the next descriptor's done bit is set, the current
  646. * descriptor has been corrupted. Force s/w to discard
  647. * this descriptor and continue...
  648. */
  649. tds = tbf->bf_desc;
  650. ret = ath9k_hw_rxprocdesc(ah, tds, &trs);
  651. if (ret == -EINPROGRESS)
  652. return NULL;
  653. }
  654. if (!bf->bf_mpdu)
  655. return bf;
  656. /*
  657. * Synchronize the DMA transfer with CPU before
  658. * 1. accessing the frame
  659. * 2. requeueing the same buffer to h/w
  660. */
  661. dma_sync_single_for_cpu(sc->dev, bf->bf_buf_addr,
  662. common->rx_bufsize,
  663. DMA_FROM_DEVICE);
  664. return bf;
  665. }
  666. /* Assumes you've already done the endian to CPU conversion */
  667. static bool ath9k_rx_accept(struct ath_common *common,
  668. struct ieee80211_hdr *hdr,
  669. struct ieee80211_rx_status *rxs,
  670. struct ath_rx_status *rx_stats,
  671. bool *decrypt_error)
  672. {
  673. struct ath_softc *sc = (struct ath_softc *) common->priv;
  674. bool is_mc, is_valid_tkip, strip_mic, mic_error;
  675. struct ath_hw *ah = common->ah;
  676. __le16 fc;
  677. u8 rx_status_len = ah->caps.rx_status_len;
  678. fc = hdr->frame_control;
  679. is_mc = !!is_multicast_ether_addr(hdr->addr1);
  680. is_valid_tkip = rx_stats->rs_keyix != ATH9K_RXKEYIX_INVALID &&
  681. test_bit(rx_stats->rs_keyix, common->tkip_keymap);
  682. strip_mic = is_valid_tkip && ieee80211_is_data(fc) &&
  683. !(rx_stats->rs_status &
  684. (ATH9K_RXERR_DECRYPT | ATH9K_RXERR_CRC | ATH9K_RXERR_MIC |
  685. ATH9K_RXERR_KEYMISS));
  686. if (!rx_stats->rs_datalen)
  687. return false;
  688. /*
  689. * rs_status follows rs_datalen so if rs_datalen is too large
  690. * we can take a hint that hardware corrupted it, so ignore
  691. * those frames.
  692. */
  693. if (rx_stats->rs_datalen > (common->rx_bufsize - rx_status_len))
  694. return false;
  695. /* Only use error bits from the last fragment */
  696. if (rx_stats->rs_more)
  697. return true;
  698. mic_error = is_valid_tkip && !ieee80211_is_ctl(fc) &&
  699. !ieee80211_has_morefrags(fc) &&
  700. !(le16_to_cpu(hdr->seq_ctrl) & IEEE80211_SCTL_FRAG) &&
  701. (rx_stats->rs_status & ATH9K_RXERR_MIC);
  702. /*
  703. * The rx_stats->rs_status will not be set until the end of the
  704. * chained descriptors so it can be ignored if rs_more is set. The
  705. * rs_more will be false at the last element of the chained
  706. * descriptors.
  707. */
  708. if (rx_stats->rs_status != 0) {
  709. u8 status_mask;
  710. if (rx_stats->rs_status & ATH9K_RXERR_CRC) {
  711. rxs->flag |= RX_FLAG_FAILED_FCS_CRC;
  712. mic_error = false;
  713. }
  714. if (rx_stats->rs_status & ATH9K_RXERR_PHY)
  715. return false;
  716. if ((rx_stats->rs_status & ATH9K_RXERR_DECRYPT) ||
  717. (!is_mc && (rx_stats->rs_status & ATH9K_RXERR_KEYMISS))) {
  718. *decrypt_error = true;
  719. mic_error = false;
  720. }
  721. /*
  722. * Reject error frames with the exception of
  723. * decryption and MIC failures. For monitor mode,
  724. * we also ignore the CRC error.
  725. */
  726. status_mask = ATH9K_RXERR_DECRYPT | ATH9K_RXERR_MIC |
  727. ATH9K_RXERR_KEYMISS;
  728. if (ah->is_monitoring && (sc->rx.rxfilter & FIF_FCSFAIL))
  729. status_mask |= ATH9K_RXERR_CRC;
  730. if (rx_stats->rs_status & ~status_mask)
  731. return false;
  732. }
  733. /*
  734. * For unicast frames the MIC error bit can have false positives,
  735. * so all MIC error reports need to be validated in software.
  736. * False negatives are not common, so skip software verification
  737. * if the hardware considers the MIC valid.
  738. */
  739. if (strip_mic)
  740. rxs->flag |= RX_FLAG_MMIC_STRIPPED;
  741. else if (is_mc && mic_error)
  742. rxs->flag |= RX_FLAG_MMIC_ERROR;
  743. return true;
  744. }
  745. static int ath9k_process_rate(struct ath_common *common,
  746. struct ieee80211_hw *hw,
  747. struct ath_rx_status *rx_stats,
  748. struct ieee80211_rx_status *rxs)
  749. {
  750. struct ieee80211_supported_band *sband;
  751. enum ieee80211_band band;
  752. unsigned int i = 0;
  753. band = hw->conf.channel->band;
  754. sband = hw->wiphy->bands[band];
  755. if (rx_stats->rs_rate & 0x80) {
  756. /* HT rate */
  757. rxs->flag |= RX_FLAG_HT;
  758. if (rx_stats->rs_flags & ATH9K_RX_2040)
  759. rxs->flag |= RX_FLAG_40MHZ;
  760. if (rx_stats->rs_flags & ATH9K_RX_GI)
  761. rxs->flag |= RX_FLAG_SHORT_GI;
  762. rxs->rate_idx = rx_stats->rs_rate & 0x7f;
  763. return 0;
  764. }
  765. for (i = 0; i < sband->n_bitrates; i++) {
  766. if (sband->bitrates[i].hw_value == rx_stats->rs_rate) {
  767. rxs->rate_idx = i;
  768. return 0;
  769. }
  770. if (sband->bitrates[i].hw_value_short == rx_stats->rs_rate) {
  771. rxs->flag |= RX_FLAG_SHORTPRE;
  772. rxs->rate_idx = i;
  773. return 0;
  774. }
  775. }
  776. /*
  777. * No valid hardware bitrate found -- we should not get here
  778. * because hardware has already validated this frame as OK.
  779. */
  780. ath_dbg(common, ATH_DBG_ANY,
  781. "unsupported hw bitrate detected 0x%02x using 1 Mbit\n",
  782. rx_stats->rs_rate);
  783. return -EINVAL;
  784. }
  785. static void ath9k_process_rssi(struct ath_common *common,
  786. struct ieee80211_hw *hw,
  787. struct ieee80211_hdr *hdr,
  788. struct ath_rx_status *rx_stats)
  789. {
  790. struct ath_softc *sc = hw->priv;
  791. struct ath_hw *ah = common->ah;
  792. int last_rssi;
  793. if (!rx_stats->is_mybeacon ||
  794. ((ah->opmode != NL80211_IFTYPE_STATION) &&
  795. (ah->opmode != NL80211_IFTYPE_ADHOC)))
  796. return;
  797. if (rx_stats->rs_rssi != ATH9K_RSSI_BAD && !rx_stats->rs_moreaggr)
  798. ATH_RSSI_LPF(sc->last_rssi, rx_stats->rs_rssi);
  799. last_rssi = sc->last_rssi;
  800. if (likely(last_rssi != ATH_RSSI_DUMMY_MARKER))
  801. rx_stats->rs_rssi = ATH_EP_RND(last_rssi,
  802. ATH_RSSI_EP_MULTIPLIER);
  803. if (rx_stats->rs_rssi < 0)
  804. rx_stats->rs_rssi = 0;
  805. /* Update Beacon RSSI, this is used by ANI. */
  806. ah->stats.avgbrssi = rx_stats->rs_rssi;
  807. }
  808. /*
  809. * For Decrypt or Demic errors, we only mark packet status here and always push
  810. * up the frame up to let mac80211 handle the actual error case, be it no
  811. * decryption key or real decryption error. This let us keep statistics there.
  812. */
  813. static int ath9k_rx_skb_preprocess(struct ath_common *common,
  814. struct ieee80211_hw *hw,
  815. struct ieee80211_hdr *hdr,
  816. struct ath_rx_status *rx_stats,
  817. struct ieee80211_rx_status *rx_status,
  818. bool *decrypt_error)
  819. {
  820. struct ath_hw *ah = common->ah;
  821. memset(rx_status, 0, sizeof(struct ieee80211_rx_status));
  822. /*
  823. * everything but the rate is checked here, the rate check is done
  824. * separately to avoid doing two lookups for a rate for each frame.
  825. */
  826. if (!ath9k_rx_accept(common, hdr, rx_status, rx_stats, decrypt_error))
  827. return -EINVAL;
  828. /* Only use status info from the last fragment */
  829. if (rx_stats->rs_more)
  830. return 0;
  831. ath9k_process_rssi(common, hw, hdr, rx_stats);
  832. if (ath9k_process_rate(common, hw, rx_stats, rx_status))
  833. return -EINVAL;
  834. rx_status->band = hw->conf.channel->band;
  835. rx_status->freq = hw->conf.channel->center_freq;
  836. rx_status->signal = ah->noise + rx_stats->rs_rssi;
  837. rx_status->antenna = rx_stats->rs_antenna;
  838. rx_status->flag |= RX_FLAG_MACTIME_MPDU;
  839. return 0;
  840. }
  841. static void ath9k_rx_skb_postprocess(struct ath_common *common,
  842. struct sk_buff *skb,
  843. struct ath_rx_status *rx_stats,
  844. struct ieee80211_rx_status *rxs,
  845. bool decrypt_error)
  846. {
  847. struct ath_hw *ah = common->ah;
  848. struct ieee80211_hdr *hdr;
  849. int hdrlen, padpos, padsize;
  850. u8 keyix;
  851. __le16 fc;
  852. /* see if any padding is done by the hw and remove it */
  853. hdr = (struct ieee80211_hdr *) skb->data;
  854. hdrlen = ieee80211_get_hdrlen_from_skb(skb);
  855. fc = hdr->frame_control;
  856. padpos = ath9k_cmn_padpos(hdr->frame_control);
  857. /* The MAC header is padded to have 32-bit boundary if the
  858. * packet payload is non-zero. The general calculation for
  859. * padsize would take into account odd header lengths:
  860. * padsize = (4 - padpos % 4) % 4; However, since only
  861. * even-length headers are used, padding can only be 0 or 2
  862. * bytes and we can optimize this a bit. In addition, we must
  863. * not try to remove padding from short control frames that do
  864. * not have payload. */
  865. padsize = padpos & 3;
  866. if (padsize && skb->len>=padpos+padsize+FCS_LEN) {
  867. memmove(skb->data + padsize, skb->data, padpos);
  868. skb_pull(skb, padsize);
  869. }
  870. keyix = rx_stats->rs_keyix;
  871. if (!(keyix == ATH9K_RXKEYIX_INVALID) && !decrypt_error &&
  872. ieee80211_has_protected(fc)) {
  873. rxs->flag |= RX_FLAG_DECRYPTED;
  874. } else if (ieee80211_has_protected(fc)
  875. && !decrypt_error && skb->len >= hdrlen + 4) {
  876. keyix = skb->data[hdrlen + 3] >> 6;
  877. if (test_bit(keyix, common->keymap))
  878. rxs->flag |= RX_FLAG_DECRYPTED;
  879. }
  880. if (ah->sw_mgmt_crypto &&
  881. (rxs->flag & RX_FLAG_DECRYPTED) &&
  882. ieee80211_is_mgmt(fc))
  883. /* Use software decrypt for management frames. */
  884. rxs->flag &= ~RX_FLAG_DECRYPTED;
  885. }
  886. static void ath_lnaconf_alt_good_scan(struct ath_ant_comb *antcomb,
  887. struct ath_hw_antcomb_conf ant_conf,
  888. int main_rssi_avg)
  889. {
  890. antcomb->quick_scan_cnt = 0;
  891. if (ant_conf.main_lna_conf == ATH_ANT_DIV_COMB_LNA2)
  892. antcomb->rssi_lna2 = main_rssi_avg;
  893. else if (ant_conf.main_lna_conf == ATH_ANT_DIV_COMB_LNA1)
  894. antcomb->rssi_lna1 = main_rssi_avg;
  895. switch ((ant_conf.main_lna_conf << 4) | ant_conf.alt_lna_conf) {
  896. case 0x10: /* LNA2 A-B */
  897. antcomb->main_conf = ATH_ANT_DIV_COMB_LNA1_MINUS_LNA2;
  898. antcomb->first_quick_scan_conf =
  899. ATH_ANT_DIV_COMB_LNA1_PLUS_LNA2;
  900. antcomb->second_quick_scan_conf = ATH_ANT_DIV_COMB_LNA1;
  901. break;
  902. case 0x20: /* LNA1 A-B */
  903. antcomb->main_conf = ATH_ANT_DIV_COMB_LNA1_MINUS_LNA2;
  904. antcomb->first_quick_scan_conf =
  905. ATH_ANT_DIV_COMB_LNA1_PLUS_LNA2;
  906. antcomb->second_quick_scan_conf = ATH_ANT_DIV_COMB_LNA2;
  907. break;
  908. case 0x21: /* LNA1 LNA2 */
  909. antcomb->main_conf = ATH_ANT_DIV_COMB_LNA2;
  910. antcomb->first_quick_scan_conf =
  911. ATH_ANT_DIV_COMB_LNA1_MINUS_LNA2;
  912. antcomb->second_quick_scan_conf =
  913. ATH_ANT_DIV_COMB_LNA1_PLUS_LNA2;
  914. break;
  915. case 0x12: /* LNA2 LNA1 */
  916. antcomb->main_conf = ATH_ANT_DIV_COMB_LNA1;
  917. antcomb->first_quick_scan_conf =
  918. ATH_ANT_DIV_COMB_LNA1_MINUS_LNA2;
  919. antcomb->second_quick_scan_conf =
  920. ATH_ANT_DIV_COMB_LNA1_PLUS_LNA2;
  921. break;
  922. case 0x13: /* LNA2 A+B */
  923. antcomb->main_conf = ATH_ANT_DIV_COMB_LNA1_PLUS_LNA2;
  924. antcomb->first_quick_scan_conf =
  925. ATH_ANT_DIV_COMB_LNA1_MINUS_LNA2;
  926. antcomb->second_quick_scan_conf = ATH_ANT_DIV_COMB_LNA1;
  927. break;
  928. case 0x23: /* LNA1 A+B */
  929. antcomb->main_conf = ATH_ANT_DIV_COMB_LNA1_PLUS_LNA2;
  930. antcomb->first_quick_scan_conf =
  931. ATH_ANT_DIV_COMB_LNA1_MINUS_LNA2;
  932. antcomb->second_quick_scan_conf = ATH_ANT_DIV_COMB_LNA2;
  933. break;
  934. default:
  935. break;
  936. }
  937. }
  938. static void ath_select_ant_div_from_quick_scan(struct ath_ant_comb *antcomb,
  939. struct ath_hw_antcomb_conf *div_ant_conf,
  940. int main_rssi_avg, int alt_rssi_avg,
  941. int alt_ratio)
  942. {
  943. /* alt_good */
  944. switch (antcomb->quick_scan_cnt) {
  945. case 0:
  946. /* set alt to main, and alt to first conf */
  947. div_ant_conf->main_lna_conf = antcomb->main_conf;
  948. div_ant_conf->alt_lna_conf = antcomb->first_quick_scan_conf;
  949. break;
  950. case 1:
  951. /* set alt to main, and alt to first conf */
  952. div_ant_conf->main_lna_conf = antcomb->main_conf;
  953. div_ant_conf->alt_lna_conf = antcomb->second_quick_scan_conf;
  954. antcomb->rssi_first = main_rssi_avg;
  955. antcomb->rssi_second = alt_rssi_avg;
  956. if (antcomb->main_conf == ATH_ANT_DIV_COMB_LNA1) {
  957. /* main is LNA1 */
  958. if (ath_is_alt_ant_ratio_better(alt_ratio,
  959. ATH_ANT_DIV_COMB_LNA1_DELTA_HI,
  960. ATH_ANT_DIV_COMB_LNA1_DELTA_LOW,
  961. main_rssi_avg, alt_rssi_avg,
  962. antcomb->total_pkt_count))
  963. antcomb->first_ratio = true;
  964. else
  965. antcomb->first_ratio = false;
  966. } else if (antcomb->main_conf == ATH_ANT_DIV_COMB_LNA2) {
  967. if (ath_is_alt_ant_ratio_better(alt_ratio,
  968. ATH_ANT_DIV_COMB_LNA1_DELTA_MID,
  969. ATH_ANT_DIV_COMB_LNA1_DELTA_LOW,
  970. main_rssi_avg, alt_rssi_avg,
  971. antcomb->total_pkt_count))
  972. antcomb->first_ratio = true;
  973. else
  974. antcomb->first_ratio = false;
  975. } else {
  976. if ((((alt_ratio >= ATH_ANT_DIV_COMB_ALT_ANT_RATIO2) &&
  977. (alt_rssi_avg > main_rssi_avg +
  978. ATH_ANT_DIV_COMB_LNA1_DELTA_HI)) ||
  979. (alt_rssi_avg > main_rssi_avg)) &&
  980. (antcomb->total_pkt_count > 50))
  981. antcomb->first_ratio = true;
  982. else
  983. antcomb->first_ratio = false;
  984. }
  985. break;
  986. case 2:
  987. antcomb->alt_good = false;
  988. antcomb->scan_not_start = false;
  989. antcomb->scan = false;
  990. antcomb->rssi_first = main_rssi_avg;
  991. antcomb->rssi_third = alt_rssi_avg;
  992. if (antcomb->second_quick_scan_conf == ATH_ANT_DIV_COMB_LNA1)
  993. antcomb->rssi_lna1 = alt_rssi_avg;
  994. else if (antcomb->second_quick_scan_conf ==
  995. ATH_ANT_DIV_COMB_LNA2)
  996. antcomb->rssi_lna2 = alt_rssi_avg;
  997. else if (antcomb->second_quick_scan_conf ==
  998. ATH_ANT_DIV_COMB_LNA1_PLUS_LNA2) {
  999. if (antcomb->main_conf == ATH_ANT_DIV_COMB_LNA2)
  1000. antcomb->rssi_lna2 = main_rssi_avg;
  1001. else if (antcomb->main_conf == ATH_ANT_DIV_COMB_LNA1)
  1002. antcomb->rssi_lna1 = main_rssi_avg;
  1003. }
  1004. if (antcomb->rssi_lna2 > antcomb->rssi_lna1 +
  1005. ATH_ANT_DIV_COMB_LNA1_LNA2_SWITCH_DELTA)
  1006. div_ant_conf->main_lna_conf = ATH_ANT_DIV_COMB_LNA2;
  1007. else
  1008. div_ant_conf->main_lna_conf = ATH_ANT_DIV_COMB_LNA1;
  1009. if (antcomb->main_conf == ATH_ANT_DIV_COMB_LNA1) {
  1010. if (ath_is_alt_ant_ratio_better(alt_ratio,
  1011. ATH_ANT_DIV_COMB_LNA1_DELTA_HI,
  1012. ATH_ANT_DIV_COMB_LNA1_DELTA_LOW,
  1013. main_rssi_avg, alt_rssi_avg,
  1014. antcomb->total_pkt_count))
  1015. antcomb->second_ratio = true;
  1016. else
  1017. antcomb->second_ratio = false;
  1018. } else if (antcomb->main_conf == ATH_ANT_DIV_COMB_LNA2) {
  1019. if (ath_is_alt_ant_ratio_better(alt_ratio,
  1020. ATH_ANT_DIV_COMB_LNA1_DELTA_MID,
  1021. ATH_ANT_DIV_COMB_LNA1_DELTA_LOW,
  1022. main_rssi_avg, alt_rssi_avg,
  1023. antcomb->total_pkt_count))
  1024. antcomb->second_ratio = true;
  1025. else
  1026. antcomb->second_ratio = false;
  1027. } else {
  1028. if ((((alt_ratio >= ATH_ANT_DIV_COMB_ALT_ANT_RATIO2) &&
  1029. (alt_rssi_avg > main_rssi_avg +
  1030. ATH_ANT_DIV_COMB_LNA1_DELTA_HI)) ||
  1031. (alt_rssi_avg > main_rssi_avg)) &&
  1032. (antcomb->total_pkt_count > 50))
  1033. antcomb->second_ratio = true;
  1034. else
  1035. antcomb->second_ratio = false;
  1036. }
  1037. /* set alt to the conf with maximun ratio */
  1038. if (antcomb->first_ratio && antcomb->second_ratio) {
  1039. if (antcomb->rssi_second > antcomb->rssi_third) {
  1040. /* first alt*/
  1041. if ((antcomb->first_quick_scan_conf ==
  1042. ATH_ANT_DIV_COMB_LNA1) ||
  1043. (antcomb->first_quick_scan_conf ==
  1044. ATH_ANT_DIV_COMB_LNA2))
  1045. /* Set alt LNA1 or LNA2*/
  1046. if (div_ant_conf->main_lna_conf ==
  1047. ATH_ANT_DIV_COMB_LNA2)
  1048. div_ant_conf->alt_lna_conf =
  1049. ATH_ANT_DIV_COMB_LNA1;
  1050. else
  1051. div_ant_conf->alt_lna_conf =
  1052. ATH_ANT_DIV_COMB_LNA2;
  1053. else
  1054. /* Set alt to A+B or A-B */
  1055. div_ant_conf->alt_lna_conf =
  1056. antcomb->first_quick_scan_conf;
  1057. } else if ((antcomb->second_quick_scan_conf ==
  1058. ATH_ANT_DIV_COMB_LNA1) ||
  1059. (antcomb->second_quick_scan_conf ==
  1060. ATH_ANT_DIV_COMB_LNA2)) {
  1061. /* Set alt LNA1 or LNA2 */
  1062. if (div_ant_conf->main_lna_conf ==
  1063. ATH_ANT_DIV_COMB_LNA2)
  1064. div_ant_conf->alt_lna_conf =
  1065. ATH_ANT_DIV_COMB_LNA1;
  1066. else
  1067. div_ant_conf->alt_lna_conf =
  1068. ATH_ANT_DIV_COMB_LNA2;
  1069. } else {
  1070. /* Set alt to A+B or A-B */
  1071. div_ant_conf->alt_lna_conf =
  1072. antcomb->second_quick_scan_conf;
  1073. }
  1074. } else if (antcomb->first_ratio) {
  1075. /* first alt */
  1076. if ((antcomb->first_quick_scan_conf ==
  1077. ATH_ANT_DIV_COMB_LNA1) ||
  1078. (antcomb->first_quick_scan_conf ==
  1079. ATH_ANT_DIV_COMB_LNA2))
  1080. /* Set alt LNA1 or LNA2 */
  1081. if (div_ant_conf->main_lna_conf ==
  1082. ATH_ANT_DIV_COMB_LNA2)
  1083. div_ant_conf->alt_lna_conf =
  1084. ATH_ANT_DIV_COMB_LNA1;
  1085. else
  1086. div_ant_conf->alt_lna_conf =
  1087. ATH_ANT_DIV_COMB_LNA2;
  1088. else
  1089. /* Set alt to A+B or A-B */
  1090. div_ant_conf->alt_lna_conf =
  1091. antcomb->first_quick_scan_conf;
  1092. } else if (antcomb->second_ratio) {
  1093. /* second alt */
  1094. if ((antcomb->second_quick_scan_conf ==
  1095. ATH_ANT_DIV_COMB_LNA1) ||
  1096. (antcomb->second_quick_scan_conf ==
  1097. ATH_ANT_DIV_COMB_LNA2))
  1098. /* Set alt LNA1 or LNA2 */
  1099. if (div_ant_conf->main_lna_conf ==
  1100. ATH_ANT_DIV_COMB_LNA2)
  1101. div_ant_conf->alt_lna_conf =
  1102. ATH_ANT_DIV_COMB_LNA1;
  1103. else
  1104. div_ant_conf->alt_lna_conf =
  1105. ATH_ANT_DIV_COMB_LNA2;
  1106. else
  1107. /* Set alt to A+B or A-B */
  1108. div_ant_conf->alt_lna_conf =
  1109. antcomb->second_quick_scan_conf;
  1110. } else {
  1111. /* main is largest */
  1112. if ((antcomb->main_conf == ATH_ANT_DIV_COMB_LNA1) ||
  1113. (antcomb->main_conf == ATH_ANT_DIV_COMB_LNA2))
  1114. /* Set alt LNA1 or LNA2 */
  1115. if (div_ant_conf->main_lna_conf ==
  1116. ATH_ANT_DIV_COMB_LNA2)
  1117. div_ant_conf->alt_lna_conf =
  1118. ATH_ANT_DIV_COMB_LNA1;
  1119. else
  1120. div_ant_conf->alt_lna_conf =
  1121. ATH_ANT_DIV_COMB_LNA2;
  1122. else
  1123. /* Set alt to A+B or A-B */
  1124. div_ant_conf->alt_lna_conf = antcomb->main_conf;
  1125. }
  1126. break;
  1127. default:
  1128. break;
  1129. }
  1130. }
  1131. static void ath_ant_div_conf_fast_divbias(struct ath_hw_antcomb_conf *ant_conf,
  1132. struct ath_ant_comb *antcomb, int alt_ratio)
  1133. {
  1134. if (ant_conf->div_group == 0) {
  1135. /* Adjust the fast_div_bias based on main and alt lna conf */
  1136. switch ((ant_conf->main_lna_conf << 4) |
  1137. ant_conf->alt_lna_conf) {
  1138. case 0x01: /* A-B LNA2 */
  1139. ant_conf->fast_div_bias = 0x3b;
  1140. break;
  1141. case 0x02: /* A-B LNA1 */
  1142. ant_conf->fast_div_bias = 0x3d;
  1143. break;
  1144. case 0x03: /* A-B A+B */
  1145. ant_conf->fast_div_bias = 0x1;
  1146. break;
  1147. case 0x10: /* LNA2 A-B */
  1148. ant_conf->fast_div_bias = 0x7;
  1149. break;
  1150. case 0x12: /* LNA2 LNA1 */
  1151. ant_conf->fast_div_bias = 0x2;
  1152. break;
  1153. case 0x13: /* LNA2 A+B */
  1154. ant_conf->fast_div_bias = 0x7;
  1155. break;
  1156. case 0x20: /* LNA1 A-B */
  1157. ant_conf->fast_div_bias = 0x6;
  1158. break;
  1159. case 0x21: /* LNA1 LNA2 */
  1160. ant_conf->fast_div_bias = 0x0;
  1161. break;
  1162. case 0x23: /* LNA1 A+B */
  1163. ant_conf->fast_div_bias = 0x6;
  1164. break;
  1165. case 0x30: /* A+B A-B */
  1166. ant_conf->fast_div_bias = 0x1;
  1167. break;
  1168. case 0x31: /* A+B LNA2 */
  1169. ant_conf->fast_div_bias = 0x3b;
  1170. break;
  1171. case 0x32: /* A+B LNA1 */
  1172. ant_conf->fast_div_bias = 0x3d;
  1173. break;
  1174. default:
  1175. break;
  1176. }
  1177. } else if (ant_conf->div_group == 1) {
  1178. /* Adjust the fast_div_bias based on main and alt_lna_conf */
  1179. switch ((ant_conf->main_lna_conf << 4) |
  1180. ant_conf->alt_lna_conf) {
  1181. case 0x01: /* A-B LNA2 */
  1182. ant_conf->fast_div_bias = 0x1;
  1183. ant_conf->main_gaintb = 0;
  1184. ant_conf->alt_gaintb = 0;
  1185. break;
  1186. case 0x02: /* A-B LNA1 */
  1187. ant_conf->fast_div_bias = 0x1;
  1188. ant_conf->main_gaintb = 0;
  1189. ant_conf->alt_gaintb = 0;
  1190. break;
  1191. case 0x03: /* A-B A+B */
  1192. ant_conf->fast_div_bias = 0x1;
  1193. ant_conf->main_gaintb = 0;
  1194. ant_conf->alt_gaintb = 0;
  1195. break;
  1196. case 0x10: /* LNA2 A-B */
  1197. if (!(antcomb->scan) &&
  1198. (alt_ratio > ATH_ANT_DIV_COMB_ALT_ANT_RATIO))
  1199. ant_conf->fast_div_bias = 0x3f;
  1200. else
  1201. ant_conf->fast_div_bias = 0x1;
  1202. ant_conf->main_gaintb = 0;
  1203. ant_conf->alt_gaintb = 0;
  1204. break;
  1205. case 0x12: /* LNA2 LNA1 */
  1206. ant_conf->fast_div_bias = 0x1;
  1207. ant_conf->main_gaintb = 0;
  1208. ant_conf->alt_gaintb = 0;
  1209. break;
  1210. case 0x13: /* LNA2 A+B */
  1211. if (!(antcomb->scan) &&
  1212. (alt_ratio > ATH_ANT_DIV_COMB_ALT_ANT_RATIO))
  1213. ant_conf->fast_div_bias = 0x3f;
  1214. else
  1215. ant_conf->fast_div_bias = 0x1;
  1216. ant_conf->main_gaintb = 0;
  1217. ant_conf->alt_gaintb = 0;
  1218. break;
  1219. case 0x20: /* LNA1 A-B */
  1220. if (!(antcomb->scan) &&
  1221. (alt_ratio > ATH_ANT_DIV_COMB_ALT_ANT_RATIO))
  1222. ant_conf->fast_div_bias = 0x3f;
  1223. else
  1224. ant_conf->fast_div_bias = 0x1;
  1225. ant_conf->main_gaintb = 0;
  1226. ant_conf->alt_gaintb = 0;
  1227. break;
  1228. case 0x21: /* LNA1 LNA2 */
  1229. ant_conf->fast_div_bias = 0x1;
  1230. ant_conf->main_gaintb = 0;
  1231. ant_conf->alt_gaintb = 0;
  1232. break;
  1233. case 0x23: /* LNA1 A+B */
  1234. if (!(antcomb->scan) &&
  1235. (alt_ratio > ATH_ANT_DIV_COMB_ALT_ANT_RATIO))
  1236. ant_conf->fast_div_bias = 0x3f;
  1237. else
  1238. ant_conf->fast_div_bias = 0x1;
  1239. ant_conf->main_gaintb = 0;
  1240. ant_conf->alt_gaintb = 0;
  1241. break;
  1242. case 0x30: /* A+B A-B */
  1243. ant_conf->fast_div_bias = 0x1;
  1244. ant_conf->main_gaintb = 0;
  1245. ant_conf->alt_gaintb = 0;
  1246. break;
  1247. case 0x31: /* A+B LNA2 */
  1248. ant_conf->fast_div_bias = 0x1;
  1249. ant_conf->main_gaintb = 0;
  1250. ant_conf->alt_gaintb = 0;
  1251. break;
  1252. case 0x32: /* A+B LNA1 */
  1253. ant_conf->fast_div_bias = 0x1;
  1254. ant_conf->main_gaintb = 0;
  1255. ant_conf->alt_gaintb = 0;
  1256. break;
  1257. default:
  1258. break;
  1259. }
  1260. } else if (ant_conf->div_group == 2) {
  1261. /* Adjust the fast_div_bias based on main and alt_lna_conf */
  1262. switch ((ant_conf->main_lna_conf << 4) |
  1263. ant_conf->alt_lna_conf) {
  1264. case 0x01: /* A-B LNA2 */
  1265. ant_conf->fast_div_bias = 0x1;
  1266. ant_conf->main_gaintb = 0;
  1267. ant_conf->alt_gaintb = 0;
  1268. break;
  1269. case 0x02: /* A-B LNA1 */
  1270. ant_conf->fast_div_bias = 0x1;
  1271. ant_conf->main_gaintb = 0;
  1272. ant_conf->alt_gaintb = 0;
  1273. break;
  1274. case 0x03: /* A-B A+B */
  1275. ant_conf->fast_div_bias = 0x1;
  1276. ant_conf->main_gaintb = 0;
  1277. ant_conf->alt_gaintb = 0;
  1278. break;
  1279. case 0x10: /* LNA2 A-B */
  1280. if (!(antcomb->scan) &&
  1281. (alt_ratio > ATH_ANT_DIV_COMB_ALT_ANT_RATIO))
  1282. ant_conf->fast_div_bias = 0x1;
  1283. else
  1284. ant_conf->fast_div_bias = 0x2;
  1285. ant_conf->main_gaintb = 0;
  1286. ant_conf->alt_gaintb = 0;
  1287. break;
  1288. case 0x12: /* LNA2 LNA1 */
  1289. ant_conf->fast_div_bias = 0x1;
  1290. ant_conf->main_gaintb = 0;
  1291. ant_conf->alt_gaintb = 0;
  1292. break;
  1293. case 0x13: /* LNA2 A+B */
  1294. if (!(antcomb->scan) &&
  1295. (alt_ratio > ATH_ANT_DIV_COMB_ALT_ANT_RATIO))
  1296. ant_conf->fast_div_bias = 0x1;
  1297. else
  1298. ant_conf->fast_div_bias = 0x2;
  1299. ant_conf->main_gaintb = 0;
  1300. ant_conf->alt_gaintb = 0;
  1301. break;
  1302. case 0x20: /* LNA1 A-B */
  1303. if (!(antcomb->scan) &&
  1304. (alt_ratio > ATH_ANT_DIV_COMB_ALT_ANT_RATIO))
  1305. ant_conf->fast_div_bias = 0x1;
  1306. else
  1307. ant_conf->fast_div_bias = 0x2;
  1308. ant_conf->main_gaintb = 0;
  1309. ant_conf->alt_gaintb = 0;
  1310. break;
  1311. case 0x21: /* LNA1 LNA2 */
  1312. ant_conf->fast_div_bias = 0x1;
  1313. ant_conf->main_gaintb = 0;
  1314. ant_conf->alt_gaintb = 0;
  1315. break;
  1316. case 0x23: /* LNA1 A+B */
  1317. if (!(antcomb->scan) &&
  1318. (alt_ratio > ATH_ANT_DIV_COMB_ALT_ANT_RATIO))
  1319. ant_conf->fast_div_bias = 0x1;
  1320. else
  1321. ant_conf->fast_div_bias = 0x2;
  1322. ant_conf->main_gaintb = 0;
  1323. ant_conf->alt_gaintb = 0;
  1324. break;
  1325. case 0x30: /* A+B A-B */
  1326. ant_conf->fast_div_bias = 0x1;
  1327. ant_conf->main_gaintb = 0;
  1328. ant_conf->alt_gaintb = 0;
  1329. break;
  1330. case 0x31: /* A+B LNA2 */
  1331. ant_conf->fast_div_bias = 0x1;
  1332. ant_conf->main_gaintb = 0;
  1333. ant_conf->alt_gaintb = 0;
  1334. break;
  1335. case 0x32: /* A+B LNA1 */
  1336. ant_conf->fast_div_bias = 0x1;
  1337. ant_conf->main_gaintb = 0;
  1338. ant_conf->alt_gaintb = 0;
  1339. break;
  1340. default:
  1341. break;
  1342. }
  1343. }
  1344. }
  1345. /* Antenna diversity and combining */
  1346. static void ath_ant_comb_scan(struct ath_softc *sc, struct ath_rx_status *rs)
  1347. {
  1348. struct ath_hw_antcomb_conf div_ant_conf;
  1349. struct ath_ant_comb *antcomb = &sc->ant_comb;
  1350. int alt_ratio = 0, alt_rssi_avg = 0, main_rssi_avg = 0, curr_alt_set;
  1351. int curr_main_set;
  1352. int main_rssi = rs->rs_rssi_ctl0;
  1353. int alt_rssi = rs->rs_rssi_ctl1;
  1354. int rx_ant_conf, main_ant_conf;
  1355. bool short_scan = false;
  1356. rx_ant_conf = (rs->rs_rssi_ctl2 >> ATH_ANT_RX_CURRENT_SHIFT) &
  1357. ATH_ANT_RX_MASK;
  1358. main_ant_conf = (rs->rs_rssi_ctl2 >> ATH_ANT_RX_MAIN_SHIFT) &
  1359. ATH_ANT_RX_MASK;
  1360. /* Record packet only when both main_rssi and alt_rssi is positive */
  1361. if (main_rssi > 0 && alt_rssi > 0) {
  1362. antcomb->total_pkt_count++;
  1363. antcomb->main_total_rssi += main_rssi;
  1364. antcomb->alt_total_rssi += alt_rssi;
  1365. if (main_ant_conf == rx_ant_conf)
  1366. antcomb->main_recv_cnt++;
  1367. else
  1368. antcomb->alt_recv_cnt++;
  1369. }
  1370. /* Short scan check */
  1371. if (antcomb->scan && antcomb->alt_good) {
  1372. if (time_after(jiffies, antcomb->scan_start_time +
  1373. msecs_to_jiffies(ATH_ANT_DIV_COMB_SHORT_SCAN_INTR)))
  1374. short_scan = true;
  1375. else
  1376. if (antcomb->total_pkt_count ==
  1377. ATH_ANT_DIV_COMB_SHORT_SCAN_PKTCOUNT) {
  1378. alt_ratio = ((antcomb->alt_recv_cnt * 100) /
  1379. antcomb->total_pkt_count);
  1380. if (alt_ratio < ATH_ANT_DIV_COMB_ALT_ANT_RATIO)
  1381. short_scan = true;
  1382. }
  1383. }
  1384. if (((antcomb->total_pkt_count < ATH_ANT_DIV_COMB_MAX_PKTCOUNT) ||
  1385. rs->rs_moreaggr) && !short_scan)
  1386. return;
  1387. if (antcomb->total_pkt_count) {
  1388. alt_ratio = ((antcomb->alt_recv_cnt * 100) /
  1389. antcomb->total_pkt_count);
  1390. main_rssi_avg = (antcomb->main_total_rssi /
  1391. antcomb->total_pkt_count);
  1392. alt_rssi_avg = (antcomb->alt_total_rssi /
  1393. antcomb->total_pkt_count);
  1394. }
  1395. ath9k_hw_antdiv_comb_conf_get(sc->sc_ah, &div_ant_conf);
  1396. curr_alt_set = div_ant_conf.alt_lna_conf;
  1397. curr_main_set = div_ant_conf.main_lna_conf;
  1398. antcomb->count++;
  1399. if (antcomb->count == ATH_ANT_DIV_COMB_MAX_COUNT) {
  1400. if (alt_ratio > ATH_ANT_DIV_COMB_ALT_ANT_RATIO) {
  1401. ath_lnaconf_alt_good_scan(antcomb, div_ant_conf,
  1402. main_rssi_avg);
  1403. antcomb->alt_good = true;
  1404. } else {
  1405. antcomb->alt_good = false;
  1406. }
  1407. antcomb->count = 0;
  1408. antcomb->scan = true;
  1409. antcomb->scan_not_start = true;
  1410. }
  1411. if (!antcomb->scan) {
  1412. if (ath_ant_div_comb_alt_check(div_ant_conf.div_group,
  1413. alt_ratio, curr_main_set, curr_alt_set,
  1414. alt_rssi_avg, main_rssi_avg)) {
  1415. if (curr_alt_set == ATH_ANT_DIV_COMB_LNA2) {
  1416. /* Switch main and alt LNA */
  1417. div_ant_conf.main_lna_conf =
  1418. ATH_ANT_DIV_COMB_LNA2;
  1419. div_ant_conf.alt_lna_conf =
  1420. ATH_ANT_DIV_COMB_LNA1;
  1421. } else if (curr_alt_set == ATH_ANT_DIV_COMB_LNA1) {
  1422. div_ant_conf.main_lna_conf =
  1423. ATH_ANT_DIV_COMB_LNA1;
  1424. div_ant_conf.alt_lna_conf =
  1425. ATH_ANT_DIV_COMB_LNA2;
  1426. }
  1427. goto div_comb_done;
  1428. } else if ((curr_alt_set != ATH_ANT_DIV_COMB_LNA1) &&
  1429. (curr_alt_set != ATH_ANT_DIV_COMB_LNA2)) {
  1430. /* Set alt to another LNA */
  1431. if (curr_main_set == ATH_ANT_DIV_COMB_LNA2)
  1432. div_ant_conf.alt_lna_conf =
  1433. ATH_ANT_DIV_COMB_LNA1;
  1434. else if (curr_main_set == ATH_ANT_DIV_COMB_LNA1)
  1435. div_ant_conf.alt_lna_conf =
  1436. ATH_ANT_DIV_COMB_LNA2;
  1437. goto div_comb_done;
  1438. }
  1439. if ((alt_rssi_avg < (main_rssi_avg +
  1440. div_ant_conf.lna1_lna2_delta)))
  1441. goto div_comb_done;
  1442. }
  1443. if (!antcomb->scan_not_start) {
  1444. switch (curr_alt_set) {
  1445. case ATH_ANT_DIV_COMB_LNA2:
  1446. antcomb->rssi_lna2 = alt_rssi_avg;
  1447. antcomb->rssi_lna1 = main_rssi_avg;
  1448. antcomb->scan = true;
  1449. /* set to A+B */
  1450. div_ant_conf.main_lna_conf =
  1451. ATH_ANT_DIV_COMB_LNA1;
  1452. div_ant_conf.alt_lna_conf =
  1453. ATH_ANT_DIV_COMB_LNA1_PLUS_LNA2;
  1454. break;
  1455. case ATH_ANT_DIV_COMB_LNA1:
  1456. antcomb->rssi_lna1 = alt_rssi_avg;
  1457. antcomb->rssi_lna2 = main_rssi_avg;
  1458. antcomb->scan = true;
  1459. /* set to A+B */
  1460. div_ant_conf.main_lna_conf = ATH_ANT_DIV_COMB_LNA2;
  1461. div_ant_conf.alt_lna_conf =
  1462. ATH_ANT_DIV_COMB_LNA1_PLUS_LNA2;
  1463. break;
  1464. case ATH_ANT_DIV_COMB_LNA1_PLUS_LNA2:
  1465. antcomb->rssi_add = alt_rssi_avg;
  1466. antcomb->scan = true;
  1467. /* set to A-B */
  1468. div_ant_conf.alt_lna_conf =
  1469. ATH_ANT_DIV_COMB_LNA1_MINUS_LNA2;
  1470. break;
  1471. case ATH_ANT_DIV_COMB_LNA1_MINUS_LNA2:
  1472. antcomb->rssi_sub = alt_rssi_avg;
  1473. antcomb->scan = false;
  1474. if (antcomb->rssi_lna2 >
  1475. (antcomb->rssi_lna1 +
  1476. ATH_ANT_DIV_COMB_LNA1_LNA2_SWITCH_DELTA)) {
  1477. /* use LNA2 as main LNA */
  1478. if ((antcomb->rssi_add > antcomb->rssi_lna1) &&
  1479. (antcomb->rssi_add > antcomb->rssi_sub)) {
  1480. /* set to A+B */
  1481. div_ant_conf.main_lna_conf =
  1482. ATH_ANT_DIV_COMB_LNA2;
  1483. div_ant_conf.alt_lna_conf =
  1484. ATH_ANT_DIV_COMB_LNA1_PLUS_LNA2;
  1485. } else if (antcomb->rssi_sub >
  1486. antcomb->rssi_lna1) {
  1487. /* set to A-B */
  1488. div_ant_conf.main_lna_conf =
  1489. ATH_ANT_DIV_COMB_LNA2;
  1490. div_ant_conf.alt_lna_conf =
  1491. ATH_ANT_DIV_COMB_LNA1_MINUS_LNA2;
  1492. } else {
  1493. /* set to LNA1 */
  1494. div_ant_conf.main_lna_conf =
  1495. ATH_ANT_DIV_COMB_LNA2;
  1496. div_ant_conf.alt_lna_conf =
  1497. ATH_ANT_DIV_COMB_LNA1;
  1498. }
  1499. } else {
  1500. /* use LNA1 as main LNA */
  1501. if ((antcomb->rssi_add > antcomb->rssi_lna2) &&
  1502. (antcomb->rssi_add > antcomb->rssi_sub)) {
  1503. /* set to A+B */
  1504. div_ant_conf.main_lna_conf =
  1505. ATH_ANT_DIV_COMB_LNA1;
  1506. div_ant_conf.alt_lna_conf =
  1507. ATH_ANT_DIV_COMB_LNA1_PLUS_LNA2;
  1508. } else if (antcomb->rssi_sub >
  1509. antcomb->rssi_lna1) {
  1510. /* set to A-B */
  1511. div_ant_conf.main_lna_conf =
  1512. ATH_ANT_DIV_COMB_LNA1;
  1513. div_ant_conf.alt_lna_conf =
  1514. ATH_ANT_DIV_COMB_LNA1_MINUS_LNA2;
  1515. } else {
  1516. /* set to LNA2 */
  1517. div_ant_conf.main_lna_conf =
  1518. ATH_ANT_DIV_COMB_LNA1;
  1519. div_ant_conf.alt_lna_conf =
  1520. ATH_ANT_DIV_COMB_LNA2;
  1521. }
  1522. }
  1523. break;
  1524. default:
  1525. break;
  1526. }
  1527. } else {
  1528. if (!antcomb->alt_good) {
  1529. antcomb->scan_not_start = false;
  1530. /* Set alt to another LNA */
  1531. if (curr_main_set == ATH_ANT_DIV_COMB_LNA2) {
  1532. div_ant_conf.main_lna_conf =
  1533. ATH_ANT_DIV_COMB_LNA2;
  1534. div_ant_conf.alt_lna_conf =
  1535. ATH_ANT_DIV_COMB_LNA1;
  1536. } else if (curr_main_set == ATH_ANT_DIV_COMB_LNA1) {
  1537. div_ant_conf.main_lna_conf =
  1538. ATH_ANT_DIV_COMB_LNA1;
  1539. div_ant_conf.alt_lna_conf =
  1540. ATH_ANT_DIV_COMB_LNA2;
  1541. }
  1542. goto div_comb_done;
  1543. }
  1544. }
  1545. ath_select_ant_div_from_quick_scan(antcomb, &div_ant_conf,
  1546. main_rssi_avg, alt_rssi_avg,
  1547. alt_ratio);
  1548. antcomb->quick_scan_cnt++;
  1549. div_comb_done:
  1550. ath_ant_div_conf_fast_divbias(&div_ant_conf, antcomb, alt_ratio);
  1551. ath9k_hw_antdiv_comb_conf_set(sc->sc_ah, &div_ant_conf);
  1552. antcomb->scan_start_time = jiffies;
  1553. antcomb->total_pkt_count = 0;
  1554. antcomb->main_total_rssi = 0;
  1555. antcomb->alt_total_rssi = 0;
  1556. antcomb->main_recv_cnt = 0;
  1557. antcomb->alt_recv_cnt = 0;
  1558. }
  1559. int ath_rx_tasklet(struct ath_softc *sc, int flush, bool hp)
  1560. {
  1561. struct ath_buf *bf;
  1562. struct sk_buff *skb = NULL, *requeue_skb, *hdr_skb;
  1563. struct ieee80211_rx_status *rxs;
  1564. struct ath_hw *ah = sc->sc_ah;
  1565. struct ath_common *common = ath9k_hw_common(ah);
  1566. struct ieee80211_hw *hw = sc->hw;
  1567. struct ieee80211_hdr *hdr;
  1568. int retval;
  1569. bool decrypt_error = false;
  1570. struct ath_rx_status rs;
  1571. enum ath9k_rx_qtype qtype;
  1572. bool edma = !!(ah->caps.hw_caps & ATH9K_HW_CAP_EDMA);
  1573. int dma_type;
  1574. u8 rx_status_len = ah->caps.rx_status_len;
  1575. u64 tsf = 0;
  1576. u32 tsf_lower = 0;
  1577. unsigned long flags;
  1578. if (edma)
  1579. dma_type = DMA_BIDIRECTIONAL;
  1580. else
  1581. dma_type = DMA_FROM_DEVICE;
  1582. qtype = hp ? ATH9K_RX_QUEUE_HP : ATH9K_RX_QUEUE_LP;
  1583. spin_lock_bh(&sc->rx.rxbuflock);
  1584. tsf = ath9k_hw_gettsf64(ah);
  1585. tsf_lower = tsf & 0xffffffff;
  1586. do {
  1587. /* If handling rx interrupt and flush is in progress => exit */
  1588. if ((sc->sc_flags & SC_OP_RXFLUSH) && (flush == 0))
  1589. break;
  1590. memset(&rs, 0, sizeof(rs));
  1591. if (edma)
  1592. bf = ath_edma_get_next_rx_buf(sc, &rs, qtype);
  1593. else
  1594. bf = ath_get_next_rx_buf(sc, &rs);
  1595. if (!bf)
  1596. break;
  1597. skb = bf->bf_mpdu;
  1598. if (!skb)
  1599. continue;
  1600. /*
  1601. * Take frame header from the first fragment and RX status from
  1602. * the last one.
  1603. */
  1604. if (sc->rx.frag)
  1605. hdr_skb = sc->rx.frag;
  1606. else
  1607. hdr_skb = skb;
  1608. hdr = (struct ieee80211_hdr *) (hdr_skb->data + rx_status_len);
  1609. rxs = IEEE80211_SKB_RXCB(hdr_skb);
  1610. if (ieee80211_is_beacon(hdr->frame_control) &&
  1611. !compare_ether_addr(hdr->addr3, common->curbssid))
  1612. rs.is_mybeacon = true;
  1613. else
  1614. rs.is_mybeacon = false;
  1615. ath_debug_stat_rx(sc, &rs);
  1616. /*
  1617. * If we're asked to flush receive queue, directly
  1618. * chain it back at the queue without processing it.
  1619. */
  1620. if (sc->sc_flags & SC_OP_RXFLUSH)
  1621. goto requeue_drop_frag;
  1622. retval = ath9k_rx_skb_preprocess(common, hw, hdr, &rs,
  1623. rxs, &decrypt_error);
  1624. if (retval)
  1625. goto requeue_drop_frag;
  1626. rxs->mactime = (tsf & ~0xffffffffULL) | rs.rs_tstamp;
  1627. if (rs.rs_tstamp > tsf_lower &&
  1628. unlikely(rs.rs_tstamp - tsf_lower > 0x10000000))
  1629. rxs->mactime -= 0x100000000ULL;
  1630. if (rs.rs_tstamp < tsf_lower &&
  1631. unlikely(tsf_lower - rs.rs_tstamp > 0x10000000))
  1632. rxs->mactime += 0x100000000ULL;
  1633. /* Ensure we always have an skb to requeue once we are done
  1634. * processing the current buffer's skb */
  1635. requeue_skb = ath_rxbuf_alloc(common, common->rx_bufsize, GFP_ATOMIC);
  1636. /* If there is no memory we ignore the current RX'd frame,
  1637. * tell hardware it can give us a new frame using the old
  1638. * skb and put it at the tail of the sc->rx.rxbuf list for
  1639. * processing. */
  1640. if (!requeue_skb)
  1641. goto requeue_drop_frag;
  1642. /* Unmap the frame */
  1643. dma_unmap_single(sc->dev, bf->bf_buf_addr,
  1644. common->rx_bufsize,
  1645. dma_type);
  1646. skb_put(skb, rs.rs_datalen + ah->caps.rx_status_len);
  1647. if (ah->caps.rx_status_len)
  1648. skb_pull(skb, ah->caps.rx_status_len);
  1649. if (!rs.rs_more)
  1650. ath9k_rx_skb_postprocess(common, hdr_skb, &rs,
  1651. rxs, decrypt_error);
  1652. /* We will now give hardware our shiny new allocated skb */
  1653. bf->bf_mpdu = requeue_skb;
  1654. bf->bf_buf_addr = dma_map_single(sc->dev, requeue_skb->data,
  1655. common->rx_bufsize,
  1656. dma_type);
  1657. if (unlikely(dma_mapping_error(sc->dev,
  1658. bf->bf_buf_addr))) {
  1659. dev_kfree_skb_any(requeue_skb);
  1660. bf->bf_mpdu = NULL;
  1661. bf->bf_buf_addr = 0;
  1662. ath_err(common, "dma_mapping_error() on RX\n");
  1663. ieee80211_rx(hw, skb);
  1664. break;
  1665. }
  1666. if (rs.rs_more) {
  1667. /*
  1668. * rs_more indicates chained descriptors which can be
  1669. * used to link buffers together for a sort of
  1670. * scatter-gather operation.
  1671. */
  1672. if (sc->rx.frag) {
  1673. /* too many fragments - cannot handle frame */
  1674. dev_kfree_skb_any(sc->rx.frag);
  1675. dev_kfree_skb_any(skb);
  1676. skb = NULL;
  1677. }
  1678. sc->rx.frag = skb;
  1679. goto requeue;
  1680. }
  1681. if (sc->rx.frag) {
  1682. int space = skb->len - skb_tailroom(hdr_skb);
  1683. sc->rx.frag = NULL;
  1684. if (pskb_expand_head(hdr_skb, 0, space, GFP_ATOMIC) < 0) {
  1685. dev_kfree_skb(skb);
  1686. goto requeue_drop_frag;
  1687. }
  1688. skb_copy_from_linear_data(skb, skb_put(hdr_skb, skb->len),
  1689. skb->len);
  1690. dev_kfree_skb_any(skb);
  1691. skb = hdr_skb;
  1692. }
  1693. /*
  1694. * change the default rx antenna if rx diversity chooses the
  1695. * other antenna 3 times in a row.
  1696. */
  1697. if (sc->rx.defant != rs.rs_antenna) {
  1698. if (++sc->rx.rxotherant >= 3)
  1699. ath_setdefantenna(sc, rs.rs_antenna);
  1700. } else {
  1701. sc->rx.rxotherant = 0;
  1702. }
  1703. if (rxs->flag & RX_FLAG_MMIC_STRIPPED)
  1704. skb_trim(skb, skb->len - 8);
  1705. spin_lock_irqsave(&sc->sc_pm_lock, flags);
  1706. if ((sc->ps_flags & (PS_WAIT_FOR_BEACON |
  1707. PS_WAIT_FOR_CAB |
  1708. PS_WAIT_FOR_PSPOLL_DATA)) ||
  1709. ath9k_check_auto_sleep(sc))
  1710. ath_rx_ps(sc, skb, rs.is_mybeacon);
  1711. spin_unlock_irqrestore(&sc->sc_pm_lock, flags);
  1712. if ((ah->caps.hw_caps & ATH9K_HW_CAP_ANT_DIV_COMB) && sc->ant_rx == 3)
  1713. ath_ant_comb_scan(sc, &rs);
  1714. ieee80211_rx(hw, skb);
  1715. requeue_drop_frag:
  1716. if (sc->rx.frag) {
  1717. dev_kfree_skb_any(sc->rx.frag);
  1718. sc->rx.frag = NULL;
  1719. }
  1720. requeue:
  1721. if (edma) {
  1722. list_add_tail(&bf->list, &sc->rx.rxbuf);
  1723. ath_rx_edma_buf_link(sc, qtype);
  1724. } else {
  1725. list_move_tail(&bf->list, &sc->rx.rxbuf);
  1726. ath_rx_buf_link(sc, bf);
  1727. if (!flush)
  1728. ath9k_hw_rxena(ah);
  1729. }
  1730. } while (1);
  1731. spin_unlock_bh(&sc->rx.rxbuflock);
  1732. if (!(ah->imask & ATH9K_INT_RXEOL)) {
  1733. ah->imask |= (ATH9K_INT_RXEOL | ATH9K_INT_RXORN);
  1734. ath9k_hw_set_interrupts(ah);
  1735. }
  1736. return 0;
  1737. }