smsc911x.c 63 KB

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  1. /***************************************************************************
  2. *
  3. * Copyright (C) 2004-2008 SMSC
  4. * Copyright (C) 2005-2008 ARM
  5. *
  6. * This program is free software; you can redistribute it and/or
  7. * modify it under the terms of the GNU General Public License
  8. * as published by the Free Software Foundation; either version 2
  9. * of the License, or (at your option) any later version.
  10. *
  11. * This program is distributed in the hope that it will be useful,
  12. * but WITHOUT ANY WARRANTY; without even the implied warranty of
  13. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  14. * GNU General Public License for more details.
  15. *
  16. * You should have received a copy of the GNU General Public License
  17. * along with this program; if not, write to the Free Software
  18. * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
  19. *
  20. ***************************************************************************
  21. * Rewritten, heavily based on smsc911x simple driver by SMSC.
  22. * Partly uses io macros from smc91x.c by Nicolas Pitre
  23. *
  24. * Supported devices:
  25. * LAN9115, LAN9116, LAN9117, LAN9118
  26. * LAN9215, LAN9216, LAN9217, LAN9218
  27. * LAN9210, LAN9211
  28. * LAN9220, LAN9221
  29. * LAN89218
  30. *
  31. */
  32. #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
  33. #include <linux/crc32.h>
  34. #include <linux/delay.h>
  35. #include <linux/errno.h>
  36. #include <linux/etherdevice.h>
  37. #include <linux/ethtool.h>
  38. #include <linux/init.h>
  39. #include <linux/interrupt.h>
  40. #include <linux/ioport.h>
  41. #include <linux/kernel.h>
  42. #include <linux/module.h>
  43. #include <linux/netdevice.h>
  44. #include <linux/platform_device.h>
  45. #include <linux/sched.h>
  46. #include <linux/timer.h>
  47. #include <linux/bug.h>
  48. #include <linux/bitops.h>
  49. #include <linux/irq.h>
  50. #include <linux/io.h>
  51. #include <linux/swab.h>
  52. #include <linux/phy.h>
  53. #include <linux/smsc911x.h>
  54. #include <linux/device.h>
  55. #include <linux/of.h>
  56. #include <linux/of_device.h>
  57. #include <linux/of_gpio.h>
  58. #include <linux/of_net.h>
  59. #include "smsc911x.h"
  60. #define SMSC_CHIPNAME "smsc911x"
  61. #define SMSC_MDIONAME "smsc911x-mdio"
  62. #define SMSC_DRV_VERSION "2008-10-21"
  63. MODULE_LICENSE("GPL");
  64. MODULE_VERSION(SMSC_DRV_VERSION);
  65. MODULE_ALIAS("platform:smsc911x");
  66. #if USE_DEBUG > 0
  67. static int debug = 16;
  68. #else
  69. static int debug = 3;
  70. #endif
  71. module_param(debug, int, 0);
  72. MODULE_PARM_DESC(debug, "Debug level (0=none,...,16=all)");
  73. struct smsc911x_data;
  74. struct smsc911x_ops {
  75. u32 (*reg_read)(struct smsc911x_data *pdata, u32 reg);
  76. void (*reg_write)(struct smsc911x_data *pdata, u32 reg, u32 val);
  77. void (*rx_readfifo)(struct smsc911x_data *pdata,
  78. unsigned int *buf, unsigned int wordcount);
  79. void (*tx_writefifo)(struct smsc911x_data *pdata,
  80. unsigned int *buf, unsigned int wordcount);
  81. };
  82. struct smsc911x_data {
  83. void __iomem *ioaddr;
  84. unsigned int idrev;
  85. /* used to decide which workarounds apply */
  86. unsigned int generation;
  87. /* device configuration (copied from platform_data during probe) */
  88. struct smsc911x_platform_config config;
  89. /* This needs to be acquired before calling any of below:
  90. * smsc911x_mac_read(), smsc911x_mac_write()
  91. */
  92. spinlock_t mac_lock;
  93. /* spinlock to ensure register accesses are serialised */
  94. spinlock_t dev_lock;
  95. struct phy_device *phy_dev;
  96. struct mii_bus *mii_bus;
  97. int phy_irq[PHY_MAX_ADDR];
  98. unsigned int using_extphy;
  99. int last_duplex;
  100. int last_carrier;
  101. u32 msg_enable;
  102. unsigned int gpio_setting;
  103. unsigned int gpio_orig_setting;
  104. struct net_device *dev;
  105. struct napi_struct napi;
  106. unsigned int software_irq_signal;
  107. #ifdef USE_PHY_WORK_AROUND
  108. #define MIN_PACKET_SIZE (64)
  109. char loopback_tx_pkt[MIN_PACKET_SIZE];
  110. char loopback_rx_pkt[MIN_PACKET_SIZE];
  111. unsigned int resetcount;
  112. #endif
  113. /* Members for Multicast filter workaround */
  114. unsigned int multicast_update_pending;
  115. unsigned int set_bits_mask;
  116. unsigned int clear_bits_mask;
  117. unsigned int hashhi;
  118. unsigned int hashlo;
  119. /* register access functions */
  120. const struct smsc911x_ops *ops;
  121. };
  122. /* Easy access to information */
  123. #define __smsc_shift(pdata, reg) ((reg) << ((pdata)->config.shift))
  124. static inline u32 __smsc911x_reg_read(struct smsc911x_data *pdata, u32 reg)
  125. {
  126. if (pdata->config.flags & SMSC911X_USE_32BIT)
  127. return readl(pdata->ioaddr + reg);
  128. if (pdata->config.flags & SMSC911X_USE_16BIT)
  129. return ((readw(pdata->ioaddr + reg) & 0xFFFF) |
  130. ((readw(pdata->ioaddr + reg + 2) & 0xFFFF) << 16));
  131. BUG();
  132. return 0;
  133. }
  134. static inline u32
  135. __smsc911x_reg_read_shift(struct smsc911x_data *pdata, u32 reg)
  136. {
  137. if (pdata->config.flags & SMSC911X_USE_32BIT)
  138. return readl(pdata->ioaddr + __smsc_shift(pdata, reg));
  139. if (pdata->config.flags & SMSC911X_USE_16BIT)
  140. return (readw(pdata->ioaddr +
  141. __smsc_shift(pdata, reg)) & 0xFFFF) |
  142. ((readw(pdata->ioaddr +
  143. __smsc_shift(pdata, reg + 2)) & 0xFFFF) << 16);
  144. BUG();
  145. return 0;
  146. }
  147. static inline u32 smsc911x_reg_read(struct smsc911x_data *pdata, u32 reg)
  148. {
  149. u32 data;
  150. unsigned long flags;
  151. spin_lock_irqsave(&pdata->dev_lock, flags);
  152. data = pdata->ops->reg_read(pdata, reg);
  153. spin_unlock_irqrestore(&pdata->dev_lock, flags);
  154. return data;
  155. }
  156. static inline void __smsc911x_reg_write(struct smsc911x_data *pdata, u32 reg,
  157. u32 val)
  158. {
  159. if (pdata->config.flags & SMSC911X_USE_32BIT) {
  160. writel(val, pdata->ioaddr + reg);
  161. return;
  162. }
  163. if (pdata->config.flags & SMSC911X_USE_16BIT) {
  164. writew(val & 0xFFFF, pdata->ioaddr + reg);
  165. writew((val >> 16) & 0xFFFF, pdata->ioaddr + reg + 2);
  166. return;
  167. }
  168. BUG();
  169. }
  170. static inline void
  171. __smsc911x_reg_write_shift(struct smsc911x_data *pdata, u32 reg, u32 val)
  172. {
  173. if (pdata->config.flags & SMSC911X_USE_32BIT) {
  174. writel(val, pdata->ioaddr + __smsc_shift(pdata, reg));
  175. return;
  176. }
  177. if (pdata->config.flags & SMSC911X_USE_16BIT) {
  178. writew(val & 0xFFFF,
  179. pdata->ioaddr + __smsc_shift(pdata, reg));
  180. writew((val >> 16) & 0xFFFF,
  181. pdata->ioaddr + __smsc_shift(pdata, reg + 2));
  182. return;
  183. }
  184. BUG();
  185. }
  186. static inline void smsc911x_reg_write(struct smsc911x_data *pdata, u32 reg,
  187. u32 val)
  188. {
  189. unsigned long flags;
  190. spin_lock_irqsave(&pdata->dev_lock, flags);
  191. pdata->ops->reg_write(pdata, reg, val);
  192. spin_unlock_irqrestore(&pdata->dev_lock, flags);
  193. }
  194. /* Writes a packet to the TX_DATA_FIFO */
  195. static inline void
  196. smsc911x_tx_writefifo(struct smsc911x_data *pdata, unsigned int *buf,
  197. unsigned int wordcount)
  198. {
  199. unsigned long flags;
  200. spin_lock_irqsave(&pdata->dev_lock, flags);
  201. if (pdata->config.flags & SMSC911X_SWAP_FIFO) {
  202. while (wordcount--)
  203. __smsc911x_reg_write(pdata, TX_DATA_FIFO,
  204. swab32(*buf++));
  205. goto out;
  206. }
  207. if (pdata->config.flags & SMSC911X_USE_32BIT) {
  208. writesl(pdata->ioaddr + TX_DATA_FIFO, buf, wordcount);
  209. goto out;
  210. }
  211. if (pdata->config.flags & SMSC911X_USE_16BIT) {
  212. while (wordcount--)
  213. __smsc911x_reg_write(pdata, TX_DATA_FIFO, *buf++);
  214. goto out;
  215. }
  216. BUG();
  217. out:
  218. spin_unlock_irqrestore(&pdata->dev_lock, flags);
  219. }
  220. /* Writes a packet to the TX_DATA_FIFO - shifted version */
  221. static inline void
  222. smsc911x_tx_writefifo_shift(struct smsc911x_data *pdata, unsigned int *buf,
  223. unsigned int wordcount)
  224. {
  225. unsigned long flags;
  226. spin_lock_irqsave(&pdata->dev_lock, flags);
  227. if (pdata->config.flags & SMSC911X_SWAP_FIFO) {
  228. while (wordcount--)
  229. __smsc911x_reg_write_shift(pdata, TX_DATA_FIFO,
  230. swab32(*buf++));
  231. goto out;
  232. }
  233. if (pdata->config.flags & SMSC911X_USE_32BIT) {
  234. writesl(pdata->ioaddr + __smsc_shift(pdata,
  235. TX_DATA_FIFO), buf, wordcount);
  236. goto out;
  237. }
  238. if (pdata->config.flags & SMSC911X_USE_16BIT) {
  239. while (wordcount--)
  240. __smsc911x_reg_write_shift(pdata,
  241. TX_DATA_FIFO, *buf++);
  242. goto out;
  243. }
  244. BUG();
  245. out:
  246. spin_unlock_irqrestore(&pdata->dev_lock, flags);
  247. }
  248. /* Reads a packet out of the RX_DATA_FIFO */
  249. static inline void
  250. smsc911x_rx_readfifo(struct smsc911x_data *pdata, unsigned int *buf,
  251. unsigned int wordcount)
  252. {
  253. unsigned long flags;
  254. spin_lock_irqsave(&pdata->dev_lock, flags);
  255. if (pdata->config.flags & SMSC911X_SWAP_FIFO) {
  256. while (wordcount--)
  257. *buf++ = swab32(__smsc911x_reg_read(pdata,
  258. RX_DATA_FIFO));
  259. goto out;
  260. }
  261. if (pdata->config.flags & SMSC911X_USE_32BIT) {
  262. readsl(pdata->ioaddr + RX_DATA_FIFO, buf, wordcount);
  263. goto out;
  264. }
  265. if (pdata->config.flags & SMSC911X_USE_16BIT) {
  266. while (wordcount--)
  267. *buf++ = __smsc911x_reg_read(pdata, RX_DATA_FIFO);
  268. goto out;
  269. }
  270. BUG();
  271. out:
  272. spin_unlock_irqrestore(&pdata->dev_lock, flags);
  273. }
  274. /* Reads a packet out of the RX_DATA_FIFO - shifted version */
  275. static inline void
  276. smsc911x_rx_readfifo_shift(struct smsc911x_data *pdata, unsigned int *buf,
  277. unsigned int wordcount)
  278. {
  279. unsigned long flags;
  280. spin_lock_irqsave(&pdata->dev_lock, flags);
  281. if (pdata->config.flags & SMSC911X_SWAP_FIFO) {
  282. while (wordcount--)
  283. *buf++ = swab32(__smsc911x_reg_read_shift(pdata,
  284. RX_DATA_FIFO));
  285. goto out;
  286. }
  287. if (pdata->config.flags & SMSC911X_USE_32BIT) {
  288. readsl(pdata->ioaddr + __smsc_shift(pdata,
  289. RX_DATA_FIFO), buf, wordcount);
  290. goto out;
  291. }
  292. if (pdata->config.flags & SMSC911X_USE_16BIT) {
  293. while (wordcount--)
  294. *buf++ = __smsc911x_reg_read_shift(pdata,
  295. RX_DATA_FIFO);
  296. goto out;
  297. }
  298. BUG();
  299. out:
  300. spin_unlock_irqrestore(&pdata->dev_lock, flags);
  301. }
  302. /* waits for MAC not busy, with timeout. Only called by smsc911x_mac_read
  303. * and smsc911x_mac_write, so assumes mac_lock is held */
  304. static int smsc911x_mac_complete(struct smsc911x_data *pdata)
  305. {
  306. int i;
  307. u32 val;
  308. SMSC_ASSERT_MAC_LOCK(pdata);
  309. for (i = 0; i < 40; i++) {
  310. val = smsc911x_reg_read(pdata, MAC_CSR_CMD);
  311. if (!(val & MAC_CSR_CMD_CSR_BUSY_))
  312. return 0;
  313. }
  314. SMSC_WARN(pdata, hw, "Timed out waiting for MAC not BUSY. "
  315. "MAC_CSR_CMD: 0x%08X", val);
  316. return -EIO;
  317. }
  318. /* Fetches a MAC register value. Assumes mac_lock is acquired */
  319. static u32 smsc911x_mac_read(struct smsc911x_data *pdata, unsigned int offset)
  320. {
  321. unsigned int temp;
  322. SMSC_ASSERT_MAC_LOCK(pdata);
  323. temp = smsc911x_reg_read(pdata, MAC_CSR_CMD);
  324. if (unlikely(temp & MAC_CSR_CMD_CSR_BUSY_)) {
  325. SMSC_WARN(pdata, hw, "MAC busy at entry");
  326. return 0xFFFFFFFF;
  327. }
  328. /* Send the MAC cmd */
  329. smsc911x_reg_write(pdata, MAC_CSR_CMD, ((offset & 0xFF) |
  330. MAC_CSR_CMD_CSR_BUSY_ | MAC_CSR_CMD_R_NOT_W_));
  331. /* Workaround for hardware read-after-write restriction */
  332. temp = smsc911x_reg_read(pdata, BYTE_TEST);
  333. /* Wait for the read to complete */
  334. if (likely(smsc911x_mac_complete(pdata) == 0))
  335. return smsc911x_reg_read(pdata, MAC_CSR_DATA);
  336. SMSC_WARN(pdata, hw, "MAC busy after read");
  337. return 0xFFFFFFFF;
  338. }
  339. /* Set a mac register, mac_lock must be acquired before calling */
  340. static void smsc911x_mac_write(struct smsc911x_data *pdata,
  341. unsigned int offset, u32 val)
  342. {
  343. unsigned int temp;
  344. SMSC_ASSERT_MAC_LOCK(pdata);
  345. temp = smsc911x_reg_read(pdata, MAC_CSR_CMD);
  346. if (unlikely(temp & MAC_CSR_CMD_CSR_BUSY_)) {
  347. SMSC_WARN(pdata, hw,
  348. "smsc911x_mac_write failed, MAC busy at entry");
  349. return;
  350. }
  351. /* Send data to write */
  352. smsc911x_reg_write(pdata, MAC_CSR_DATA, val);
  353. /* Write the actual data */
  354. smsc911x_reg_write(pdata, MAC_CSR_CMD, ((offset & 0xFF) |
  355. MAC_CSR_CMD_CSR_BUSY_));
  356. /* Workaround for hardware read-after-write restriction */
  357. temp = smsc911x_reg_read(pdata, BYTE_TEST);
  358. /* Wait for the write to complete */
  359. if (likely(smsc911x_mac_complete(pdata) == 0))
  360. return;
  361. SMSC_WARN(pdata, hw, "smsc911x_mac_write failed, MAC busy after write");
  362. }
  363. /* Get a phy register */
  364. static int smsc911x_mii_read(struct mii_bus *bus, int phyaddr, int regidx)
  365. {
  366. struct smsc911x_data *pdata = (struct smsc911x_data *)bus->priv;
  367. unsigned long flags;
  368. unsigned int addr;
  369. int i, reg;
  370. spin_lock_irqsave(&pdata->mac_lock, flags);
  371. /* Confirm MII not busy */
  372. if (unlikely(smsc911x_mac_read(pdata, MII_ACC) & MII_ACC_MII_BUSY_)) {
  373. SMSC_WARN(pdata, hw, "MII is busy in smsc911x_mii_read???");
  374. reg = -EIO;
  375. goto out;
  376. }
  377. /* Set the address, index & direction (read from PHY) */
  378. addr = ((phyaddr & 0x1F) << 11) | ((regidx & 0x1F) << 6);
  379. smsc911x_mac_write(pdata, MII_ACC, addr);
  380. /* Wait for read to complete w/ timeout */
  381. for (i = 0; i < 100; i++)
  382. if (!(smsc911x_mac_read(pdata, MII_ACC) & MII_ACC_MII_BUSY_)) {
  383. reg = smsc911x_mac_read(pdata, MII_DATA);
  384. goto out;
  385. }
  386. SMSC_WARN(pdata, hw, "Timed out waiting for MII read to finish");
  387. reg = -EIO;
  388. out:
  389. spin_unlock_irqrestore(&pdata->mac_lock, flags);
  390. return reg;
  391. }
  392. /* Set a phy register */
  393. static int smsc911x_mii_write(struct mii_bus *bus, int phyaddr, int regidx,
  394. u16 val)
  395. {
  396. struct smsc911x_data *pdata = (struct smsc911x_data *)bus->priv;
  397. unsigned long flags;
  398. unsigned int addr;
  399. int i, reg;
  400. spin_lock_irqsave(&pdata->mac_lock, flags);
  401. /* Confirm MII not busy */
  402. if (unlikely(smsc911x_mac_read(pdata, MII_ACC) & MII_ACC_MII_BUSY_)) {
  403. SMSC_WARN(pdata, hw, "MII is busy in smsc911x_mii_write???");
  404. reg = -EIO;
  405. goto out;
  406. }
  407. /* Put the data to write in the MAC */
  408. smsc911x_mac_write(pdata, MII_DATA, val);
  409. /* Set the address, index & direction (write to PHY) */
  410. addr = ((phyaddr & 0x1F) << 11) | ((regidx & 0x1F) << 6) |
  411. MII_ACC_MII_WRITE_;
  412. smsc911x_mac_write(pdata, MII_ACC, addr);
  413. /* Wait for write to complete w/ timeout */
  414. for (i = 0; i < 100; i++)
  415. if (!(smsc911x_mac_read(pdata, MII_ACC) & MII_ACC_MII_BUSY_)) {
  416. reg = 0;
  417. goto out;
  418. }
  419. SMSC_WARN(pdata, hw, "Timed out waiting for MII write to finish");
  420. reg = -EIO;
  421. out:
  422. spin_unlock_irqrestore(&pdata->mac_lock, flags);
  423. return reg;
  424. }
  425. /* Switch to external phy. Assumes tx and rx are stopped. */
  426. static void smsc911x_phy_enable_external(struct smsc911x_data *pdata)
  427. {
  428. unsigned int hwcfg = smsc911x_reg_read(pdata, HW_CFG);
  429. /* Disable phy clocks to the MAC */
  430. hwcfg &= (~HW_CFG_PHY_CLK_SEL_);
  431. hwcfg |= HW_CFG_PHY_CLK_SEL_CLK_DIS_;
  432. smsc911x_reg_write(pdata, HW_CFG, hwcfg);
  433. udelay(10); /* Enough time for clocks to stop */
  434. /* Switch to external phy */
  435. hwcfg |= HW_CFG_EXT_PHY_EN_;
  436. smsc911x_reg_write(pdata, HW_CFG, hwcfg);
  437. /* Enable phy clocks to the MAC */
  438. hwcfg &= (~HW_CFG_PHY_CLK_SEL_);
  439. hwcfg |= HW_CFG_PHY_CLK_SEL_EXT_PHY_;
  440. smsc911x_reg_write(pdata, HW_CFG, hwcfg);
  441. udelay(10); /* Enough time for clocks to restart */
  442. hwcfg |= HW_CFG_SMI_SEL_;
  443. smsc911x_reg_write(pdata, HW_CFG, hwcfg);
  444. }
  445. /* Autodetects and enables external phy if present on supported chips.
  446. * autodetection can be overridden by specifying SMSC911X_FORCE_INTERNAL_PHY
  447. * or SMSC911X_FORCE_EXTERNAL_PHY in the platform_data flags. */
  448. static void smsc911x_phy_initialise_external(struct smsc911x_data *pdata)
  449. {
  450. unsigned int hwcfg = smsc911x_reg_read(pdata, HW_CFG);
  451. if (pdata->config.flags & SMSC911X_FORCE_INTERNAL_PHY) {
  452. SMSC_TRACE(pdata, hw, "Forcing internal PHY");
  453. pdata->using_extphy = 0;
  454. } else if (pdata->config.flags & SMSC911X_FORCE_EXTERNAL_PHY) {
  455. SMSC_TRACE(pdata, hw, "Forcing external PHY");
  456. smsc911x_phy_enable_external(pdata);
  457. pdata->using_extphy = 1;
  458. } else if (hwcfg & HW_CFG_EXT_PHY_DET_) {
  459. SMSC_TRACE(pdata, hw,
  460. "HW_CFG EXT_PHY_DET set, using external PHY");
  461. smsc911x_phy_enable_external(pdata);
  462. pdata->using_extphy = 1;
  463. } else {
  464. SMSC_TRACE(pdata, hw,
  465. "HW_CFG EXT_PHY_DET clear, using internal PHY");
  466. pdata->using_extphy = 0;
  467. }
  468. }
  469. /* Fetches a tx status out of the status fifo */
  470. static unsigned int smsc911x_tx_get_txstatus(struct smsc911x_data *pdata)
  471. {
  472. unsigned int result =
  473. smsc911x_reg_read(pdata, TX_FIFO_INF) & TX_FIFO_INF_TSUSED_;
  474. if (result != 0)
  475. result = smsc911x_reg_read(pdata, TX_STATUS_FIFO);
  476. return result;
  477. }
  478. /* Fetches the next rx status */
  479. static unsigned int smsc911x_rx_get_rxstatus(struct smsc911x_data *pdata)
  480. {
  481. unsigned int result =
  482. smsc911x_reg_read(pdata, RX_FIFO_INF) & RX_FIFO_INF_RXSUSED_;
  483. if (result != 0)
  484. result = smsc911x_reg_read(pdata, RX_STATUS_FIFO);
  485. return result;
  486. }
  487. #ifdef USE_PHY_WORK_AROUND
  488. static int smsc911x_phy_check_loopbackpkt(struct smsc911x_data *pdata)
  489. {
  490. unsigned int tries;
  491. u32 wrsz;
  492. u32 rdsz;
  493. ulong bufp;
  494. for (tries = 0; tries < 10; tries++) {
  495. unsigned int txcmd_a;
  496. unsigned int txcmd_b;
  497. unsigned int status;
  498. unsigned int pktlength;
  499. unsigned int i;
  500. /* Zero-out rx packet memory */
  501. memset(pdata->loopback_rx_pkt, 0, MIN_PACKET_SIZE);
  502. /* Write tx packet to 118 */
  503. txcmd_a = (u32)((ulong)pdata->loopback_tx_pkt & 0x03) << 16;
  504. txcmd_a |= TX_CMD_A_FIRST_SEG_ | TX_CMD_A_LAST_SEG_;
  505. txcmd_a |= MIN_PACKET_SIZE;
  506. txcmd_b = MIN_PACKET_SIZE << 16 | MIN_PACKET_SIZE;
  507. smsc911x_reg_write(pdata, TX_DATA_FIFO, txcmd_a);
  508. smsc911x_reg_write(pdata, TX_DATA_FIFO, txcmd_b);
  509. bufp = (ulong)pdata->loopback_tx_pkt & (~0x3);
  510. wrsz = MIN_PACKET_SIZE + 3;
  511. wrsz += (u32)((ulong)pdata->loopback_tx_pkt & 0x3);
  512. wrsz >>= 2;
  513. pdata->ops->tx_writefifo(pdata, (unsigned int *)bufp, wrsz);
  514. /* Wait till transmit is done */
  515. i = 60;
  516. do {
  517. udelay(5);
  518. status = smsc911x_tx_get_txstatus(pdata);
  519. } while ((i--) && (!status));
  520. if (!status) {
  521. SMSC_WARN(pdata, hw,
  522. "Failed to transmit during loopback test");
  523. continue;
  524. }
  525. if (status & TX_STS_ES_) {
  526. SMSC_WARN(pdata, hw,
  527. "Transmit encountered errors during loopback test");
  528. continue;
  529. }
  530. /* Wait till receive is done */
  531. i = 60;
  532. do {
  533. udelay(5);
  534. status = smsc911x_rx_get_rxstatus(pdata);
  535. } while ((i--) && (!status));
  536. if (!status) {
  537. SMSC_WARN(pdata, hw,
  538. "Failed to receive during loopback test");
  539. continue;
  540. }
  541. if (status & RX_STS_ES_) {
  542. SMSC_WARN(pdata, hw,
  543. "Receive encountered errors during loopback test");
  544. continue;
  545. }
  546. pktlength = ((status & 0x3FFF0000UL) >> 16);
  547. bufp = (ulong)pdata->loopback_rx_pkt;
  548. rdsz = pktlength + 3;
  549. rdsz += (u32)((ulong)pdata->loopback_rx_pkt & 0x3);
  550. rdsz >>= 2;
  551. pdata->ops->rx_readfifo(pdata, (unsigned int *)bufp, rdsz);
  552. if (pktlength != (MIN_PACKET_SIZE + 4)) {
  553. SMSC_WARN(pdata, hw, "Unexpected packet size "
  554. "during loop back test, size=%d, will retry",
  555. pktlength);
  556. } else {
  557. unsigned int j;
  558. int mismatch = 0;
  559. for (j = 0; j < MIN_PACKET_SIZE; j++) {
  560. if (pdata->loopback_tx_pkt[j]
  561. != pdata->loopback_rx_pkt[j]) {
  562. mismatch = 1;
  563. break;
  564. }
  565. }
  566. if (!mismatch) {
  567. SMSC_TRACE(pdata, hw, "Successfully verified "
  568. "loopback packet");
  569. return 0;
  570. } else {
  571. SMSC_WARN(pdata, hw, "Data mismatch "
  572. "during loop back test, will retry");
  573. }
  574. }
  575. }
  576. return -EIO;
  577. }
  578. static int smsc911x_phy_reset(struct smsc911x_data *pdata)
  579. {
  580. struct phy_device *phy_dev = pdata->phy_dev;
  581. unsigned int temp;
  582. unsigned int i = 100000;
  583. BUG_ON(!phy_dev);
  584. BUG_ON(!phy_dev->bus);
  585. SMSC_TRACE(pdata, hw, "Performing PHY BCR Reset");
  586. smsc911x_mii_write(phy_dev->bus, phy_dev->addr, MII_BMCR, BMCR_RESET);
  587. do {
  588. msleep(1);
  589. temp = smsc911x_mii_read(phy_dev->bus, phy_dev->addr,
  590. MII_BMCR);
  591. } while ((i--) && (temp & BMCR_RESET));
  592. if (temp & BMCR_RESET) {
  593. SMSC_WARN(pdata, hw, "PHY reset failed to complete");
  594. return -EIO;
  595. }
  596. /* Extra delay required because the phy may not be completed with
  597. * its reset when BMCR_RESET is cleared. Specs say 256 uS is
  598. * enough delay but using 1ms here to be safe */
  599. msleep(1);
  600. return 0;
  601. }
  602. static int smsc911x_phy_loopbacktest(struct net_device *dev)
  603. {
  604. struct smsc911x_data *pdata = netdev_priv(dev);
  605. struct phy_device *phy_dev = pdata->phy_dev;
  606. int result = -EIO;
  607. unsigned int i, val;
  608. unsigned long flags;
  609. /* Initialise tx packet using broadcast destination address */
  610. memset(pdata->loopback_tx_pkt, 0xff, ETH_ALEN);
  611. /* Use incrementing source address */
  612. for (i = 6; i < 12; i++)
  613. pdata->loopback_tx_pkt[i] = (char)i;
  614. /* Set length type field */
  615. pdata->loopback_tx_pkt[12] = 0x00;
  616. pdata->loopback_tx_pkt[13] = 0x00;
  617. for (i = 14; i < MIN_PACKET_SIZE; i++)
  618. pdata->loopback_tx_pkt[i] = (char)i;
  619. val = smsc911x_reg_read(pdata, HW_CFG);
  620. val &= HW_CFG_TX_FIF_SZ_;
  621. val |= HW_CFG_SF_;
  622. smsc911x_reg_write(pdata, HW_CFG, val);
  623. smsc911x_reg_write(pdata, TX_CFG, TX_CFG_TX_ON_);
  624. smsc911x_reg_write(pdata, RX_CFG,
  625. (u32)((ulong)pdata->loopback_rx_pkt & 0x03) << 8);
  626. for (i = 0; i < 10; i++) {
  627. /* Set PHY to 10/FD, no ANEG, and loopback mode */
  628. smsc911x_mii_write(phy_dev->bus, phy_dev->addr, MII_BMCR,
  629. BMCR_LOOPBACK | BMCR_FULLDPLX);
  630. /* Enable MAC tx/rx, FD */
  631. spin_lock_irqsave(&pdata->mac_lock, flags);
  632. smsc911x_mac_write(pdata, MAC_CR, MAC_CR_FDPX_
  633. | MAC_CR_TXEN_ | MAC_CR_RXEN_);
  634. spin_unlock_irqrestore(&pdata->mac_lock, flags);
  635. if (smsc911x_phy_check_loopbackpkt(pdata) == 0) {
  636. result = 0;
  637. break;
  638. }
  639. pdata->resetcount++;
  640. /* Disable MAC rx */
  641. spin_lock_irqsave(&pdata->mac_lock, flags);
  642. smsc911x_mac_write(pdata, MAC_CR, 0);
  643. spin_unlock_irqrestore(&pdata->mac_lock, flags);
  644. smsc911x_phy_reset(pdata);
  645. }
  646. /* Disable MAC */
  647. spin_lock_irqsave(&pdata->mac_lock, flags);
  648. smsc911x_mac_write(pdata, MAC_CR, 0);
  649. spin_unlock_irqrestore(&pdata->mac_lock, flags);
  650. /* Cancel PHY loopback mode */
  651. smsc911x_mii_write(phy_dev->bus, phy_dev->addr, MII_BMCR, 0);
  652. smsc911x_reg_write(pdata, TX_CFG, 0);
  653. smsc911x_reg_write(pdata, RX_CFG, 0);
  654. return result;
  655. }
  656. #endif /* USE_PHY_WORK_AROUND */
  657. static void smsc911x_phy_update_flowcontrol(struct smsc911x_data *pdata)
  658. {
  659. struct phy_device *phy_dev = pdata->phy_dev;
  660. u32 afc = smsc911x_reg_read(pdata, AFC_CFG);
  661. u32 flow;
  662. unsigned long flags;
  663. if (phy_dev->duplex == DUPLEX_FULL) {
  664. u16 lcladv = phy_read(phy_dev, MII_ADVERTISE);
  665. u16 rmtadv = phy_read(phy_dev, MII_LPA);
  666. u8 cap = mii_resolve_flowctrl_fdx(lcladv, rmtadv);
  667. if (cap & FLOW_CTRL_RX)
  668. flow = 0xFFFF0002;
  669. else
  670. flow = 0;
  671. if (cap & FLOW_CTRL_TX)
  672. afc |= 0xF;
  673. else
  674. afc &= ~0xF;
  675. SMSC_TRACE(pdata, hw, "rx pause %s, tx pause %s",
  676. (cap & FLOW_CTRL_RX ? "enabled" : "disabled"),
  677. (cap & FLOW_CTRL_TX ? "enabled" : "disabled"));
  678. } else {
  679. SMSC_TRACE(pdata, hw, "half duplex");
  680. flow = 0;
  681. afc |= 0xF;
  682. }
  683. spin_lock_irqsave(&pdata->mac_lock, flags);
  684. smsc911x_mac_write(pdata, FLOW, flow);
  685. spin_unlock_irqrestore(&pdata->mac_lock, flags);
  686. smsc911x_reg_write(pdata, AFC_CFG, afc);
  687. }
  688. /* Update link mode if anything has changed. Called periodically when the
  689. * PHY is in polling mode, even if nothing has changed. */
  690. static void smsc911x_phy_adjust_link(struct net_device *dev)
  691. {
  692. struct smsc911x_data *pdata = netdev_priv(dev);
  693. struct phy_device *phy_dev = pdata->phy_dev;
  694. unsigned long flags;
  695. int carrier;
  696. if (phy_dev->duplex != pdata->last_duplex) {
  697. unsigned int mac_cr;
  698. SMSC_TRACE(pdata, hw, "duplex state has changed");
  699. spin_lock_irqsave(&pdata->mac_lock, flags);
  700. mac_cr = smsc911x_mac_read(pdata, MAC_CR);
  701. if (phy_dev->duplex) {
  702. SMSC_TRACE(pdata, hw,
  703. "configuring for full duplex mode");
  704. mac_cr |= MAC_CR_FDPX_;
  705. } else {
  706. SMSC_TRACE(pdata, hw,
  707. "configuring for half duplex mode");
  708. mac_cr &= ~MAC_CR_FDPX_;
  709. }
  710. smsc911x_mac_write(pdata, MAC_CR, mac_cr);
  711. spin_unlock_irqrestore(&pdata->mac_lock, flags);
  712. smsc911x_phy_update_flowcontrol(pdata);
  713. pdata->last_duplex = phy_dev->duplex;
  714. }
  715. carrier = netif_carrier_ok(dev);
  716. if (carrier != pdata->last_carrier) {
  717. SMSC_TRACE(pdata, hw, "carrier state has changed");
  718. if (carrier) {
  719. SMSC_TRACE(pdata, hw, "configuring for carrier OK");
  720. if ((pdata->gpio_orig_setting & GPIO_CFG_LED1_EN_) &&
  721. (!pdata->using_extphy)) {
  722. /* Restore original GPIO configuration */
  723. pdata->gpio_setting = pdata->gpio_orig_setting;
  724. smsc911x_reg_write(pdata, GPIO_CFG,
  725. pdata->gpio_setting);
  726. }
  727. } else {
  728. SMSC_TRACE(pdata, hw, "configuring for no carrier");
  729. /* Check global setting that LED1
  730. * usage is 10/100 indicator */
  731. pdata->gpio_setting = smsc911x_reg_read(pdata,
  732. GPIO_CFG);
  733. if ((pdata->gpio_setting & GPIO_CFG_LED1_EN_) &&
  734. (!pdata->using_extphy)) {
  735. /* Force 10/100 LED off, after saving
  736. * original GPIO configuration */
  737. pdata->gpio_orig_setting = pdata->gpio_setting;
  738. pdata->gpio_setting &= ~GPIO_CFG_LED1_EN_;
  739. pdata->gpio_setting |= (GPIO_CFG_GPIOBUF0_
  740. | GPIO_CFG_GPIODIR0_
  741. | GPIO_CFG_GPIOD0_);
  742. smsc911x_reg_write(pdata, GPIO_CFG,
  743. pdata->gpio_setting);
  744. }
  745. }
  746. pdata->last_carrier = carrier;
  747. }
  748. }
  749. static int smsc911x_mii_probe(struct net_device *dev)
  750. {
  751. struct smsc911x_data *pdata = netdev_priv(dev);
  752. struct phy_device *phydev = NULL;
  753. int ret;
  754. /* find the first phy */
  755. phydev = phy_find_first(pdata->mii_bus);
  756. if (!phydev) {
  757. netdev_err(dev, "no PHY found\n");
  758. return -ENODEV;
  759. }
  760. SMSC_TRACE(pdata, probe, "PHY: addr %d, phy_id 0x%08X",
  761. phydev->addr, phydev->phy_id);
  762. ret = phy_connect_direct(dev, phydev,
  763. &smsc911x_phy_adjust_link, 0,
  764. pdata->config.phy_interface);
  765. if (ret) {
  766. netdev_err(dev, "Could not attach to PHY\n");
  767. return ret;
  768. }
  769. netdev_info(dev,
  770. "attached PHY driver [%s] (mii_bus:phy_addr=%s, irq=%d)\n",
  771. phydev->drv->name, dev_name(&phydev->dev), phydev->irq);
  772. /* mask with MAC supported features */
  773. phydev->supported &= (PHY_BASIC_FEATURES | SUPPORTED_Pause |
  774. SUPPORTED_Asym_Pause);
  775. phydev->advertising = phydev->supported;
  776. pdata->phy_dev = phydev;
  777. pdata->last_duplex = -1;
  778. pdata->last_carrier = -1;
  779. #ifdef USE_PHY_WORK_AROUND
  780. if (smsc911x_phy_loopbacktest(dev) < 0) {
  781. SMSC_WARN(pdata, hw, "Failed Loop Back Test");
  782. return -ENODEV;
  783. }
  784. SMSC_TRACE(pdata, hw, "Passed Loop Back Test");
  785. #endif /* USE_PHY_WORK_AROUND */
  786. SMSC_TRACE(pdata, hw, "phy initialised successfully");
  787. return 0;
  788. }
  789. static int __devinit smsc911x_mii_init(struct platform_device *pdev,
  790. struct net_device *dev)
  791. {
  792. struct smsc911x_data *pdata = netdev_priv(dev);
  793. int err = -ENXIO, i;
  794. pdata->mii_bus = mdiobus_alloc();
  795. if (!pdata->mii_bus) {
  796. err = -ENOMEM;
  797. goto err_out_1;
  798. }
  799. pdata->mii_bus->name = SMSC_MDIONAME;
  800. snprintf(pdata->mii_bus->id, MII_BUS_ID_SIZE, "%x", pdev->id);
  801. pdata->mii_bus->priv = pdata;
  802. pdata->mii_bus->read = smsc911x_mii_read;
  803. pdata->mii_bus->write = smsc911x_mii_write;
  804. pdata->mii_bus->irq = pdata->phy_irq;
  805. for (i = 0; i < PHY_MAX_ADDR; ++i)
  806. pdata->mii_bus->irq[i] = PHY_POLL;
  807. pdata->mii_bus->parent = &pdev->dev;
  808. switch (pdata->idrev & 0xFFFF0000) {
  809. case 0x01170000:
  810. case 0x01150000:
  811. case 0x117A0000:
  812. case 0x115A0000:
  813. /* External PHY supported, try to autodetect */
  814. smsc911x_phy_initialise_external(pdata);
  815. break;
  816. default:
  817. SMSC_TRACE(pdata, hw, "External PHY is not supported, "
  818. "using internal PHY");
  819. pdata->using_extphy = 0;
  820. break;
  821. }
  822. if (!pdata->using_extphy) {
  823. /* Mask all PHYs except ID 1 (internal) */
  824. pdata->mii_bus->phy_mask = ~(1 << 1);
  825. }
  826. if (mdiobus_register(pdata->mii_bus)) {
  827. SMSC_WARN(pdata, probe, "Error registering mii bus");
  828. goto err_out_free_bus_2;
  829. }
  830. if (smsc911x_mii_probe(dev) < 0) {
  831. SMSC_WARN(pdata, probe, "Error registering mii bus");
  832. goto err_out_unregister_bus_3;
  833. }
  834. return 0;
  835. err_out_unregister_bus_3:
  836. mdiobus_unregister(pdata->mii_bus);
  837. err_out_free_bus_2:
  838. mdiobus_free(pdata->mii_bus);
  839. err_out_1:
  840. return err;
  841. }
  842. /* Gets the number of tx statuses in the fifo */
  843. static unsigned int smsc911x_tx_get_txstatcount(struct smsc911x_data *pdata)
  844. {
  845. return (smsc911x_reg_read(pdata, TX_FIFO_INF)
  846. & TX_FIFO_INF_TSUSED_) >> 16;
  847. }
  848. /* Reads tx statuses and increments counters where necessary */
  849. static void smsc911x_tx_update_txcounters(struct net_device *dev)
  850. {
  851. struct smsc911x_data *pdata = netdev_priv(dev);
  852. unsigned int tx_stat;
  853. while ((tx_stat = smsc911x_tx_get_txstatus(pdata)) != 0) {
  854. if (unlikely(tx_stat & 0x80000000)) {
  855. /* In this driver the packet tag is used as the packet
  856. * length. Since a packet length can never reach the
  857. * size of 0x8000, this bit is reserved. It is worth
  858. * noting that the "reserved bit" in the warning above
  859. * does not reference a hardware defined reserved bit
  860. * but rather a driver defined one.
  861. */
  862. SMSC_WARN(pdata, hw, "Packet tag reserved bit is high");
  863. } else {
  864. if (unlikely(tx_stat & TX_STS_ES_)) {
  865. dev->stats.tx_errors++;
  866. } else {
  867. dev->stats.tx_packets++;
  868. dev->stats.tx_bytes += (tx_stat >> 16);
  869. }
  870. if (unlikely(tx_stat & TX_STS_EXCESS_COL_)) {
  871. dev->stats.collisions += 16;
  872. dev->stats.tx_aborted_errors += 1;
  873. } else {
  874. dev->stats.collisions +=
  875. ((tx_stat >> 3) & 0xF);
  876. }
  877. if (unlikely(tx_stat & TX_STS_LOST_CARRIER_))
  878. dev->stats.tx_carrier_errors += 1;
  879. if (unlikely(tx_stat & TX_STS_LATE_COL_)) {
  880. dev->stats.collisions++;
  881. dev->stats.tx_aborted_errors++;
  882. }
  883. }
  884. }
  885. }
  886. /* Increments the Rx error counters */
  887. static void
  888. smsc911x_rx_counterrors(struct net_device *dev, unsigned int rxstat)
  889. {
  890. int crc_err = 0;
  891. if (unlikely(rxstat & RX_STS_ES_)) {
  892. dev->stats.rx_errors++;
  893. if (unlikely(rxstat & RX_STS_CRC_ERR_)) {
  894. dev->stats.rx_crc_errors++;
  895. crc_err = 1;
  896. }
  897. }
  898. if (likely(!crc_err)) {
  899. if (unlikely((rxstat & RX_STS_FRAME_TYPE_) &&
  900. (rxstat & RX_STS_LENGTH_ERR_)))
  901. dev->stats.rx_length_errors++;
  902. if (rxstat & RX_STS_MCAST_)
  903. dev->stats.multicast++;
  904. }
  905. }
  906. /* Quickly dumps bad packets */
  907. static void
  908. smsc911x_rx_fastforward(struct smsc911x_data *pdata, unsigned int pktbytes)
  909. {
  910. unsigned int pktwords = (pktbytes + NET_IP_ALIGN + 3) >> 2;
  911. if (likely(pktwords >= 4)) {
  912. unsigned int timeout = 500;
  913. unsigned int val;
  914. smsc911x_reg_write(pdata, RX_DP_CTRL, RX_DP_CTRL_RX_FFWD_);
  915. do {
  916. udelay(1);
  917. val = smsc911x_reg_read(pdata, RX_DP_CTRL);
  918. } while ((val & RX_DP_CTRL_RX_FFWD_) && --timeout);
  919. if (unlikely(timeout == 0))
  920. SMSC_WARN(pdata, hw, "Timed out waiting for "
  921. "RX FFWD to finish, RX_DP_CTRL: 0x%08X", val);
  922. } else {
  923. unsigned int temp;
  924. while (pktwords--)
  925. temp = smsc911x_reg_read(pdata, RX_DATA_FIFO);
  926. }
  927. }
  928. /* NAPI poll function */
  929. static int smsc911x_poll(struct napi_struct *napi, int budget)
  930. {
  931. struct smsc911x_data *pdata =
  932. container_of(napi, struct smsc911x_data, napi);
  933. struct net_device *dev = pdata->dev;
  934. int npackets = 0;
  935. while (npackets < budget) {
  936. unsigned int pktlength;
  937. unsigned int pktwords;
  938. struct sk_buff *skb;
  939. unsigned int rxstat = smsc911x_rx_get_rxstatus(pdata);
  940. if (!rxstat) {
  941. unsigned int temp;
  942. /* We processed all packets available. Tell NAPI it can
  943. * stop polling then re-enable rx interrupts */
  944. smsc911x_reg_write(pdata, INT_STS, INT_STS_RSFL_);
  945. napi_complete(napi);
  946. temp = smsc911x_reg_read(pdata, INT_EN);
  947. temp |= INT_EN_RSFL_EN_;
  948. smsc911x_reg_write(pdata, INT_EN, temp);
  949. break;
  950. }
  951. /* Count packet for NAPI scheduling, even if it has an error.
  952. * Error packets still require cycles to discard */
  953. npackets++;
  954. pktlength = ((rxstat & 0x3FFF0000) >> 16);
  955. pktwords = (pktlength + NET_IP_ALIGN + 3) >> 2;
  956. smsc911x_rx_counterrors(dev, rxstat);
  957. if (unlikely(rxstat & RX_STS_ES_)) {
  958. SMSC_WARN(pdata, rx_err,
  959. "Discarding packet with error bit set");
  960. /* Packet has an error, discard it and continue with
  961. * the next */
  962. smsc911x_rx_fastforward(pdata, pktwords);
  963. dev->stats.rx_dropped++;
  964. continue;
  965. }
  966. skb = netdev_alloc_skb(dev, pktlength + NET_IP_ALIGN);
  967. if (unlikely(!skb)) {
  968. SMSC_WARN(pdata, rx_err,
  969. "Unable to allocate skb for rx packet");
  970. /* Drop the packet and stop this polling iteration */
  971. smsc911x_rx_fastforward(pdata, pktwords);
  972. dev->stats.rx_dropped++;
  973. break;
  974. }
  975. skb->data = skb->head;
  976. skb_reset_tail_pointer(skb);
  977. /* Align IP on 16B boundary */
  978. skb_reserve(skb, NET_IP_ALIGN);
  979. skb_put(skb, pktlength - 4);
  980. pdata->ops->rx_readfifo(pdata,
  981. (unsigned int *)skb->head, pktwords);
  982. skb->protocol = eth_type_trans(skb, dev);
  983. skb_checksum_none_assert(skb);
  984. netif_receive_skb(skb);
  985. /* Update counters */
  986. dev->stats.rx_packets++;
  987. dev->stats.rx_bytes += (pktlength - 4);
  988. }
  989. /* Return total received packets */
  990. return npackets;
  991. }
  992. /* Returns hash bit number for given MAC address
  993. * Example:
  994. * 01 00 5E 00 00 01 -> returns bit number 31 */
  995. static unsigned int smsc911x_hash(char addr[ETH_ALEN])
  996. {
  997. return (ether_crc(ETH_ALEN, addr) >> 26) & 0x3f;
  998. }
  999. static void smsc911x_rx_multicast_update(struct smsc911x_data *pdata)
  1000. {
  1001. /* Performs the multicast & mac_cr update. This is called when
  1002. * safe on the current hardware, and with the mac_lock held */
  1003. unsigned int mac_cr;
  1004. SMSC_ASSERT_MAC_LOCK(pdata);
  1005. mac_cr = smsc911x_mac_read(pdata, MAC_CR);
  1006. mac_cr |= pdata->set_bits_mask;
  1007. mac_cr &= ~(pdata->clear_bits_mask);
  1008. smsc911x_mac_write(pdata, MAC_CR, mac_cr);
  1009. smsc911x_mac_write(pdata, HASHH, pdata->hashhi);
  1010. smsc911x_mac_write(pdata, HASHL, pdata->hashlo);
  1011. SMSC_TRACE(pdata, hw, "maccr 0x%08X, HASHH 0x%08X, HASHL 0x%08X",
  1012. mac_cr, pdata->hashhi, pdata->hashlo);
  1013. }
  1014. static void smsc911x_rx_multicast_update_workaround(struct smsc911x_data *pdata)
  1015. {
  1016. unsigned int mac_cr;
  1017. /* This function is only called for older LAN911x devices
  1018. * (revA or revB), where MAC_CR, HASHH and HASHL should not
  1019. * be modified during Rx - newer devices immediately update the
  1020. * registers.
  1021. *
  1022. * This is called from interrupt context */
  1023. spin_lock(&pdata->mac_lock);
  1024. /* Check Rx has stopped */
  1025. if (smsc911x_mac_read(pdata, MAC_CR) & MAC_CR_RXEN_)
  1026. SMSC_WARN(pdata, drv, "Rx not stopped");
  1027. /* Perform the update - safe to do now Rx has stopped */
  1028. smsc911x_rx_multicast_update(pdata);
  1029. /* Re-enable Rx */
  1030. mac_cr = smsc911x_mac_read(pdata, MAC_CR);
  1031. mac_cr |= MAC_CR_RXEN_;
  1032. smsc911x_mac_write(pdata, MAC_CR, mac_cr);
  1033. pdata->multicast_update_pending = 0;
  1034. spin_unlock(&pdata->mac_lock);
  1035. }
  1036. static int smsc911x_soft_reset(struct smsc911x_data *pdata)
  1037. {
  1038. unsigned int timeout;
  1039. unsigned int temp;
  1040. /* Reset the LAN911x */
  1041. smsc911x_reg_write(pdata, HW_CFG, HW_CFG_SRST_);
  1042. timeout = 10;
  1043. do {
  1044. udelay(10);
  1045. temp = smsc911x_reg_read(pdata, HW_CFG);
  1046. } while ((--timeout) && (temp & HW_CFG_SRST_));
  1047. if (unlikely(temp & HW_CFG_SRST_)) {
  1048. SMSC_WARN(pdata, drv, "Failed to complete reset");
  1049. return -EIO;
  1050. }
  1051. return 0;
  1052. }
  1053. /* Sets the device MAC address to dev_addr, called with mac_lock held */
  1054. static void
  1055. smsc911x_set_hw_mac_address(struct smsc911x_data *pdata, u8 dev_addr[6])
  1056. {
  1057. u32 mac_high16 = (dev_addr[5] << 8) | dev_addr[4];
  1058. u32 mac_low32 = (dev_addr[3] << 24) | (dev_addr[2] << 16) |
  1059. (dev_addr[1] << 8) | dev_addr[0];
  1060. SMSC_ASSERT_MAC_LOCK(pdata);
  1061. smsc911x_mac_write(pdata, ADDRH, mac_high16);
  1062. smsc911x_mac_write(pdata, ADDRL, mac_low32);
  1063. }
  1064. static int smsc911x_open(struct net_device *dev)
  1065. {
  1066. struct smsc911x_data *pdata = netdev_priv(dev);
  1067. unsigned int timeout;
  1068. unsigned int temp;
  1069. unsigned int intcfg;
  1070. /* if the phy is not yet registered, retry later*/
  1071. if (!pdata->phy_dev) {
  1072. SMSC_WARN(pdata, hw, "phy_dev is NULL");
  1073. return -EAGAIN;
  1074. }
  1075. if (!is_valid_ether_addr(dev->dev_addr)) {
  1076. SMSC_WARN(pdata, hw, "dev_addr is not a valid MAC address");
  1077. return -EADDRNOTAVAIL;
  1078. }
  1079. /* Reset the LAN911x */
  1080. if (smsc911x_soft_reset(pdata)) {
  1081. SMSC_WARN(pdata, hw, "soft reset failed");
  1082. return -EIO;
  1083. }
  1084. smsc911x_reg_write(pdata, HW_CFG, 0x00050000);
  1085. smsc911x_reg_write(pdata, AFC_CFG, 0x006E3740);
  1086. /* Increase the legal frame size of VLAN tagged frames to 1522 bytes */
  1087. spin_lock_irq(&pdata->mac_lock);
  1088. smsc911x_mac_write(pdata, VLAN1, ETH_P_8021Q);
  1089. spin_unlock_irq(&pdata->mac_lock);
  1090. /* Make sure EEPROM has finished loading before setting GPIO_CFG */
  1091. timeout = 50;
  1092. while ((smsc911x_reg_read(pdata, E2P_CMD) & E2P_CMD_EPC_BUSY_) &&
  1093. --timeout) {
  1094. udelay(10);
  1095. }
  1096. if (unlikely(timeout == 0))
  1097. SMSC_WARN(pdata, ifup,
  1098. "Timed out waiting for EEPROM busy bit to clear");
  1099. smsc911x_reg_write(pdata, GPIO_CFG, 0x70070000);
  1100. /* The soft reset above cleared the device's MAC address,
  1101. * restore it from local copy (set in probe) */
  1102. spin_lock_irq(&pdata->mac_lock);
  1103. smsc911x_set_hw_mac_address(pdata, dev->dev_addr);
  1104. spin_unlock_irq(&pdata->mac_lock);
  1105. /* Initialise irqs, but leave all sources disabled */
  1106. smsc911x_reg_write(pdata, INT_EN, 0);
  1107. smsc911x_reg_write(pdata, INT_STS, 0xFFFFFFFF);
  1108. /* Set interrupt deassertion to 100uS */
  1109. intcfg = ((10 << 24) | INT_CFG_IRQ_EN_);
  1110. if (pdata->config.irq_polarity) {
  1111. SMSC_TRACE(pdata, ifup, "irq polarity: active high");
  1112. intcfg |= INT_CFG_IRQ_POL_;
  1113. } else {
  1114. SMSC_TRACE(pdata, ifup, "irq polarity: active low");
  1115. }
  1116. if (pdata->config.irq_type) {
  1117. SMSC_TRACE(pdata, ifup, "irq type: push-pull");
  1118. intcfg |= INT_CFG_IRQ_TYPE_;
  1119. } else {
  1120. SMSC_TRACE(pdata, ifup, "irq type: open drain");
  1121. }
  1122. smsc911x_reg_write(pdata, INT_CFG, intcfg);
  1123. SMSC_TRACE(pdata, ifup, "Testing irq handler using IRQ %d", dev->irq);
  1124. pdata->software_irq_signal = 0;
  1125. smp_wmb();
  1126. temp = smsc911x_reg_read(pdata, INT_EN);
  1127. temp |= INT_EN_SW_INT_EN_;
  1128. smsc911x_reg_write(pdata, INT_EN, temp);
  1129. timeout = 1000;
  1130. while (timeout--) {
  1131. if (pdata->software_irq_signal)
  1132. break;
  1133. msleep(1);
  1134. }
  1135. if (!pdata->software_irq_signal) {
  1136. netdev_warn(dev, "ISR failed signaling test (IRQ %d)\n",
  1137. dev->irq);
  1138. return -ENODEV;
  1139. }
  1140. SMSC_TRACE(pdata, ifup, "IRQ handler passed test using IRQ %d",
  1141. dev->irq);
  1142. netdev_info(dev, "SMSC911x/921x identified at %#08lx, IRQ: %d\n",
  1143. (unsigned long)pdata->ioaddr, dev->irq);
  1144. /* Reset the last known duplex and carrier */
  1145. pdata->last_duplex = -1;
  1146. pdata->last_carrier = -1;
  1147. /* Bring the PHY up */
  1148. phy_start(pdata->phy_dev);
  1149. temp = smsc911x_reg_read(pdata, HW_CFG);
  1150. /* Preserve TX FIFO size and external PHY configuration */
  1151. temp &= (HW_CFG_TX_FIF_SZ_|0x00000FFF);
  1152. temp |= HW_CFG_SF_;
  1153. smsc911x_reg_write(pdata, HW_CFG, temp);
  1154. temp = smsc911x_reg_read(pdata, FIFO_INT);
  1155. temp |= FIFO_INT_TX_AVAIL_LEVEL_;
  1156. temp &= ~(FIFO_INT_RX_STS_LEVEL_);
  1157. smsc911x_reg_write(pdata, FIFO_INT, temp);
  1158. /* set RX Data offset to 2 bytes for alignment */
  1159. smsc911x_reg_write(pdata, RX_CFG, (2 << 8));
  1160. /* enable NAPI polling before enabling RX interrupts */
  1161. napi_enable(&pdata->napi);
  1162. temp = smsc911x_reg_read(pdata, INT_EN);
  1163. temp |= (INT_EN_TDFA_EN_ | INT_EN_RSFL_EN_ | INT_EN_RXSTOP_INT_EN_);
  1164. smsc911x_reg_write(pdata, INT_EN, temp);
  1165. spin_lock_irq(&pdata->mac_lock);
  1166. temp = smsc911x_mac_read(pdata, MAC_CR);
  1167. temp |= (MAC_CR_TXEN_ | MAC_CR_RXEN_ | MAC_CR_HBDIS_);
  1168. smsc911x_mac_write(pdata, MAC_CR, temp);
  1169. spin_unlock_irq(&pdata->mac_lock);
  1170. smsc911x_reg_write(pdata, TX_CFG, TX_CFG_TX_ON_);
  1171. netif_start_queue(dev);
  1172. return 0;
  1173. }
  1174. /* Entry point for stopping the interface */
  1175. static int smsc911x_stop(struct net_device *dev)
  1176. {
  1177. struct smsc911x_data *pdata = netdev_priv(dev);
  1178. unsigned int temp;
  1179. /* Disable all device interrupts */
  1180. temp = smsc911x_reg_read(pdata, INT_CFG);
  1181. temp &= ~INT_CFG_IRQ_EN_;
  1182. smsc911x_reg_write(pdata, INT_CFG, temp);
  1183. /* Stop Tx and Rx polling */
  1184. netif_stop_queue(dev);
  1185. napi_disable(&pdata->napi);
  1186. /* At this point all Rx and Tx activity is stopped */
  1187. dev->stats.rx_dropped += smsc911x_reg_read(pdata, RX_DROP);
  1188. smsc911x_tx_update_txcounters(dev);
  1189. /* Bring the PHY down */
  1190. if (pdata->phy_dev)
  1191. phy_stop(pdata->phy_dev);
  1192. SMSC_TRACE(pdata, ifdown, "Interface stopped");
  1193. return 0;
  1194. }
  1195. /* Entry point for transmitting a packet */
  1196. static int smsc911x_hard_start_xmit(struct sk_buff *skb, struct net_device *dev)
  1197. {
  1198. struct smsc911x_data *pdata = netdev_priv(dev);
  1199. unsigned int freespace;
  1200. unsigned int tx_cmd_a;
  1201. unsigned int tx_cmd_b;
  1202. unsigned int temp;
  1203. u32 wrsz;
  1204. ulong bufp;
  1205. freespace = smsc911x_reg_read(pdata, TX_FIFO_INF) & TX_FIFO_INF_TDFREE_;
  1206. if (unlikely(freespace < TX_FIFO_LOW_THRESHOLD))
  1207. SMSC_WARN(pdata, tx_err,
  1208. "Tx data fifo low, space available: %d", freespace);
  1209. /* Word alignment adjustment */
  1210. tx_cmd_a = (u32)((ulong)skb->data & 0x03) << 16;
  1211. tx_cmd_a |= TX_CMD_A_FIRST_SEG_ | TX_CMD_A_LAST_SEG_;
  1212. tx_cmd_a |= (unsigned int)skb->len;
  1213. tx_cmd_b = ((unsigned int)skb->len) << 16;
  1214. tx_cmd_b |= (unsigned int)skb->len;
  1215. smsc911x_reg_write(pdata, TX_DATA_FIFO, tx_cmd_a);
  1216. smsc911x_reg_write(pdata, TX_DATA_FIFO, tx_cmd_b);
  1217. bufp = (ulong)skb->data & (~0x3);
  1218. wrsz = (u32)skb->len + 3;
  1219. wrsz += (u32)((ulong)skb->data & 0x3);
  1220. wrsz >>= 2;
  1221. pdata->ops->tx_writefifo(pdata, (unsigned int *)bufp, wrsz);
  1222. freespace -= (skb->len + 32);
  1223. skb_tx_timestamp(skb);
  1224. dev_kfree_skb(skb);
  1225. if (unlikely(smsc911x_tx_get_txstatcount(pdata) >= 30))
  1226. smsc911x_tx_update_txcounters(dev);
  1227. if (freespace < TX_FIFO_LOW_THRESHOLD) {
  1228. netif_stop_queue(dev);
  1229. temp = smsc911x_reg_read(pdata, FIFO_INT);
  1230. temp &= 0x00FFFFFF;
  1231. temp |= 0x32000000;
  1232. smsc911x_reg_write(pdata, FIFO_INT, temp);
  1233. }
  1234. return NETDEV_TX_OK;
  1235. }
  1236. /* Entry point for getting status counters */
  1237. static struct net_device_stats *smsc911x_get_stats(struct net_device *dev)
  1238. {
  1239. struct smsc911x_data *pdata = netdev_priv(dev);
  1240. smsc911x_tx_update_txcounters(dev);
  1241. dev->stats.rx_dropped += smsc911x_reg_read(pdata, RX_DROP);
  1242. return &dev->stats;
  1243. }
  1244. /* Entry point for setting addressing modes */
  1245. static void smsc911x_set_multicast_list(struct net_device *dev)
  1246. {
  1247. struct smsc911x_data *pdata = netdev_priv(dev);
  1248. unsigned long flags;
  1249. if (dev->flags & IFF_PROMISC) {
  1250. /* Enabling promiscuous mode */
  1251. pdata->set_bits_mask = MAC_CR_PRMS_;
  1252. pdata->clear_bits_mask = (MAC_CR_MCPAS_ | MAC_CR_HPFILT_);
  1253. pdata->hashhi = 0;
  1254. pdata->hashlo = 0;
  1255. } else if (dev->flags & IFF_ALLMULTI) {
  1256. /* Enabling all multicast mode */
  1257. pdata->set_bits_mask = MAC_CR_MCPAS_;
  1258. pdata->clear_bits_mask = (MAC_CR_PRMS_ | MAC_CR_HPFILT_);
  1259. pdata->hashhi = 0;
  1260. pdata->hashlo = 0;
  1261. } else if (!netdev_mc_empty(dev)) {
  1262. /* Enabling specific multicast addresses */
  1263. unsigned int hash_high = 0;
  1264. unsigned int hash_low = 0;
  1265. struct netdev_hw_addr *ha;
  1266. pdata->set_bits_mask = MAC_CR_HPFILT_;
  1267. pdata->clear_bits_mask = (MAC_CR_PRMS_ | MAC_CR_MCPAS_);
  1268. netdev_for_each_mc_addr(ha, dev) {
  1269. unsigned int bitnum = smsc911x_hash(ha->addr);
  1270. unsigned int mask = 0x01 << (bitnum & 0x1F);
  1271. if (bitnum & 0x20)
  1272. hash_high |= mask;
  1273. else
  1274. hash_low |= mask;
  1275. }
  1276. pdata->hashhi = hash_high;
  1277. pdata->hashlo = hash_low;
  1278. } else {
  1279. /* Enabling local MAC address only */
  1280. pdata->set_bits_mask = 0;
  1281. pdata->clear_bits_mask =
  1282. (MAC_CR_PRMS_ | MAC_CR_MCPAS_ | MAC_CR_HPFILT_);
  1283. pdata->hashhi = 0;
  1284. pdata->hashlo = 0;
  1285. }
  1286. spin_lock_irqsave(&pdata->mac_lock, flags);
  1287. if (pdata->generation <= 1) {
  1288. /* Older hardware revision - cannot change these flags while
  1289. * receiving data */
  1290. if (!pdata->multicast_update_pending) {
  1291. unsigned int temp;
  1292. SMSC_TRACE(pdata, hw, "scheduling mcast update");
  1293. pdata->multicast_update_pending = 1;
  1294. /* Request the hardware to stop, then perform the
  1295. * update when we get an RX_STOP interrupt */
  1296. temp = smsc911x_mac_read(pdata, MAC_CR);
  1297. temp &= ~(MAC_CR_RXEN_);
  1298. smsc911x_mac_write(pdata, MAC_CR, temp);
  1299. } else {
  1300. /* There is another update pending, this should now
  1301. * use the newer values */
  1302. }
  1303. } else {
  1304. /* Newer hardware revision - can write immediately */
  1305. smsc911x_rx_multicast_update(pdata);
  1306. }
  1307. spin_unlock_irqrestore(&pdata->mac_lock, flags);
  1308. }
  1309. static irqreturn_t smsc911x_irqhandler(int irq, void *dev_id)
  1310. {
  1311. struct net_device *dev = dev_id;
  1312. struct smsc911x_data *pdata = netdev_priv(dev);
  1313. u32 intsts = smsc911x_reg_read(pdata, INT_STS);
  1314. u32 inten = smsc911x_reg_read(pdata, INT_EN);
  1315. int serviced = IRQ_NONE;
  1316. u32 temp;
  1317. if (unlikely(intsts & inten & INT_STS_SW_INT_)) {
  1318. temp = smsc911x_reg_read(pdata, INT_EN);
  1319. temp &= (~INT_EN_SW_INT_EN_);
  1320. smsc911x_reg_write(pdata, INT_EN, temp);
  1321. smsc911x_reg_write(pdata, INT_STS, INT_STS_SW_INT_);
  1322. pdata->software_irq_signal = 1;
  1323. smp_wmb();
  1324. serviced = IRQ_HANDLED;
  1325. }
  1326. if (unlikely(intsts & inten & INT_STS_RXSTOP_INT_)) {
  1327. /* Called when there is a multicast update scheduled and
  1328. * it is now safe to complete the update */
  1329. SMSC_TRACE(pdata, intr, "RX Stop interrupt");
  1330. smsc911x_reg_write(pdata, INT_STS, INT_STS_RXSTOP_INT_);
  1331. if (pdata->multicast_update_pending)
  1332. smsc911x_rx_multicast_update_workaround(pdata);
  1333. serviced = IRQ_HANDLED;
  1334. }
  1335. if (intsts & inten & INT_STS_TDFA_) {
  1336. temp = smsc911x_reg_read(pdata, FIFO_INT);
  1337. temp |= FIFO_INT_TX_AVAIL_LEVEL_;
  1338. smsc911x_reg_write(pdata, FIFO_INT, temp);
  1339. smsc911x_reg_write(pdata, INT_STS, INT_STS_TDFA_);
  1340. netif_wake_queue(dev);
  1341. serviced = IRQ_HANDLED;
  1342. }
  1343. if (unlikely(intsts & inten & INT_STS_RXE_)) {
  1344. SMSC_TRACE(pdata, intr, "RX Error interrupt");
  1345. smsc911x_reg_write(pdata, INT_STS, INT_STS_RXE_);
  1346. serviced = IRQ_HANDLED;
  1347. }
  1348. if (likely(intsts & inten & INT_STS_RSFL_)) {
  1349. if (likely(napi_schedule_prep(&pdata->napi))) {
  1350. /* Disable Rx interrupts */
  1351. temp = smsc911x_reg_read(pdata, INT_EN);
  1352. temp &= (~INT_EN_RSFL_EN_);
  1353. smsc911x_reg_write(pdata, INT_EN, temp);
  1354. /* Schedule a NAPI poll */
  1355. __napi_schedule(&pdata->napi);
  1356. } else {
  1357. SMSC_WARN(pdata, rx_err, "napi_schedule_prep failed");
  1358. }
  1359. serviced = IRQ_HANDLED;
  1360. }
  1361. return serviced;
  1362. }
  1363. #ifdef CONFIG_NET_POLL_CONTROLLER
  1364. static void smsc911x_poll_controller(struct net_device *dev)
  1365. {
  1366. disable_irq(dev->irq);
  1367. smsc911x_irqhandler(0, dev);
  1368. enable_irq(dev->irq);
  1369. }
  1370. #endif /* CONFIG_NET_POLL_CONTROLLER */
  1371. static int smsc911x_set_mac_address(struct net_device *dev, void *p)
  1372. {
  1373. struct smsc911x_data *pdata = netdev_priv(dev);
  1374. struct sockaddr *addr = p;
  1375. /* On older hardware revisions we cannot change the mac address
  1376. * registers while receiving data. Newer devices can safely change
  1377. * this at any time. */
  1378. if (pdata->generation <= 1 && netif_running(dev))
  1379. return -EBUSY;
  1380. if (!is_valid_ether_addr(addr->sa_data))
  1381. return -EADDRNOTAVAIL;
  1382. memcpy(dev->dev_addr, addr->sa_data, ETH_ALEN);
  1383. spin_lock_irq(&pdata->mac_lock);
  1384. smsc911x_set_hw_mac_address(pdata, dev->dev_addr);
  1385. spin_unlock_irq(&pdata->mac_lock);
  1386. netdev_info(dev, "MAC Address: %pM\n", dev->dev_addr);
  1387. return 0;
  1388. }
  1389. /* Standard ioctls for mii-tool */
  1390. static int smsc911x_do_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
  1391. {
  1392. struct smsc911x_data *pdata = netdev_priv(dev);
  1393. if (!netif_running(dev) || !pdata->phy_dev)
  1394. return -EINVAL;
  1395. return phy_mii_ioctl(pdata->phy_dev, ifr, cmd);
  1396. }
  1397. static int
  1398. smsc911x_ethtool_getsettings(struct net_device *dev, struct ethtool_cmd *cmd)
  1399. {
  1400. struct smsc911x_data *pdata = netdev_priv(dev);
  1401. cmd->maxtxpkt = 1;
  1402. cmd->maxrxpkt = 1;
  1403. return phy_ethtool_gset(pdata->phy_dev, cmd);
  1404. }
  1405. static int
  1406. smsc911x_ethtool_setsettings(struct net_device *dev, struct ethtool_cmd *cmd)
  1407. {
  1408. struct smsc911x_data *pdata = netdev_priv(dev);
  1409. return phy_ethtool_sset(pdata->phy_dev, cmd);
  1410. }
  1411. static void smsc911x_ethtool_getdrvinfo(struct net_device *dev,
  1412. struct ethtool_drvinfo *info)
  1413. {
  1414. strlcpy(info->driver, SMSC_CHIPNAME, sizeof(info->driver));
  1415. strlcpy(info->version, SMSC_DRV_VERSION, sizeof(info->version));
  1416. strlcpy(info->bus_info, dev_name(dev->dev.parent),
  1417. sizeof(info->bus_info));
  1418. }
  1419. static int smsc911x_ethtool_nwayreset(struct net_device *dev)
  1420. {
  1421. struct smsc911x_data *pdata = netdev_priv(dev);
  1422. return phy_start_aneg(pdata->phy_dev);
  1423. }
  1424. static u32 smsc911x_ethtool_getmsglevel(struct net_device *dev)
  1425. {
  1426. struct smsc911x_data *pdata = netdev_priv(dev);
  1427. return pdata->msg_enable;
  1428. }
  1429. static void smsc911x_ethtool_setmsglevel(struct net_device *dev, u32 level)
  1430. {
  1431. struct smsc911x_data *pdata = netdev_priv(dev);
  1432. pdata->msg_enable = level;
  1433. }
  1434. static int smsc911x_ethtool_getregslen(struct net_device *dev)
  1435. {
  1436. return (((E2P_DATA - ID_REV) / 4 + 1) + (WUCSR - MAC_CR) + 1 + 32) *
  1437. sizeof(u32);
  1438. }
  1439. static void
  1440. smsc911x_ethtool_getregs(struct net_device *dev, struct ethtool_regs *regs,
  1441. void *buf)
  1442. {
  1443. struct smsc911x_data *pdata = netdev_priv(dev);
  1444. struct phy_device *phy_dev = pdata->phy_dev;
  1445. unsigned long flags;
  1446. unsigned int i;
  1447. unsigned int j = 0;
  1448. u32 *data = buf;
  1449. regs->version = pdata->idrev;
  1450. for (i = ID_REV; i <= E2P_DATA; i += (sizeof(u32)))
  1451. data[j++] = smsc911x_reg_read(pdata, i);
  1452. for (i = MAC_CR; i <= WUCSR; i++) {
  1453. spin_lock_irqsave(&pdata->mac_lock, flags);
  1454. data[j++] = smsc911x_mac_read(pdata, i);
  1455. spin_unlock_irqrestore(&pdata->mac_lock, flags);
  1456. }
  1457. for (i = 0; i <= 31; i++)
  1458. data[j++] = smsc911x_mii_read(phy_dev->bus, phy_dev->addr, i);
  1459. }
  1460. static void smsc911x_eeprom_enable_access(struct smsc911x_data *pdata)
  1461. {
  1462. unsigned int temp = smsc911x_reg_read(pdata, GPIO_CFG);
  1463. temp &= ~GPIO_CFG_EEPR_EN_;
  1464. smsc911x_reg_write(pdata, GPIO_CFG, temp);
  1465. msleep(1);
  1466. }
  1467. static int smsc911x_eeprom_send_cmd(struct smsc911x_data *pdata, u32 op)
  1468. {
  1469. int timeout = 100;
  1470. u32 e2cmd;
  1471. SMSC_TRACE(pdata, drv, "op 0x%08x", op);
  1472. if (smsc911x_reg_read(pdata, E2P_CMD) & E2P_CMD_EPC_BUSY_) {
  1473. SMSC_WARN(pdata, drv, "Busy at start");
  1474. return -EBUSY;
  1475. }
  1476. e2cmd = op | E2P_CMD_EPC_BUSY_;
  1477. smsc911x_reg_write(pdata, E2P_CMD, e2cmd);
  1478. do {
  1479. msleep(1);
  1480. e2cmd = smsc911x_reg_read(pdata, E2P_CMD);
  1481. } while ((e2cmd & E2P_CMD_EPC_BUSY_) && (--timeout));
  1482. if (!timeout) {
  1483. SMSC_TRACE(pdata, drv, "TIMED OUT");
  1484. return -EAGAIN;
  1485. }
  1486. if (e2cmd & E2P_CMD_EPC_TIMEOUT_) {
  1487. SMSC_TRACE(pdata, drv, "Error occurred during eeprom operation");
  1488. return -EINVAL;
  1489. }
  1490. return 0;
  1491. }
  1492. static int smsc911x_eeprom_read_location(struct smsc911x_data *pdata,
  1493. u8 address, u8 *data)
  1494. {
  1495. u32 op = E2P_CMD_EPC_CMD_READ_ | address;
  1496. int ret;
  1497. SMSC_TRACE(pdata, drv, "address 0x%x", address);
  1498. ret = smsc911x_eeprom_send_cmd(pdata, op);
  1499. if (!ret)
  1500. data[address] = smsc911x_reg_read(pdata, E2P_DATA);
  1501. return ret;
  1502. }
  1503. static int smsc911x_eeprom_write_location(struct smsc911x_data *pdata,
  1504. u8 address, u8 data)
  1505. {
  1506. u32 op = E2P_CMD_EPC_CMD_ERASE_ | address;
  1507. u32 temp;
  1508. int ret;
  1509. SMSC_TRACE(pdata, drv, "address 0x%x, data 0x%x", address, data);
  1510. ret = smsc911x_eeprom_send_cmd(pdata, op);
  1511. if (!ret) {
  1512. op = E2P_CMD_EPC_CMD_WRITE_ | address;
  1513. smsc911x_reg_write(pdata, E2P_DATA, (u32)data);
  1514. /* Workaround for hardware read-after-write restriction */
  1515. temp = smsc911x_reg_read(pdata, BYTE_TEST);
  1516. ret = smsc911x_eeprom_send_cmd(pdata, op);
  1517. }
  1518. return ret;
  1519. }
  1520. static int smsc911x_ethtool_get_eeprom_len(struct net_device *dev)
  1521. {
  1522. return SMSC911X_EEPROM_SIZE;
  1523. }
  1524. static int smsc911x_ethtool_get_eeprom(struct net_device *dev,
  1525. struct ethtool_eeprom *eeprom, u8 *data)
  1526. {
  1527. struct smsc911x_data *pdata = netdev_priv(dev);
  1528. u8 eeprom_data[SMSC911X_EEPROM_SIZE];
  1529. int len;
  1530. int i;
  1531. smsc911x_eeprom_enable_access(pdata);
  1532. len = min(eeprom->len, SMSC911X_EEPROM_SIZE);
  1533. for (i = 0; i < len; i++) {
  1534. int ret = smsc911x_eeprom_read_location(pdata, i, eeprom_data);
  1535. if (ret < 0) {
  1536. eeprom->len = 0;
  1537. return ret;
  1538. }
  1539. }
  1540. memcpy(data, &eeprom_data[eeprom->offset], len);
  1541. eeprom->len = len;
  1542. return 0;
  1543. }
  1544. static int smsc911x_ethtool_set_eeprom(struct net_device *dev,
  1545. struct ethtool_eeprom *eeprom, u8 *data)
  1546. {
  1547. int ret;
  1548. struct smsc911x_data *pdata = netdev_priv(dev);
  1549. smsc911x_eeprom_enable_access(pdata);
  1550. smsc911x_eeprom_send_cmd(pdata, E2P_CMD_EPC_CMD_EWEN_);
  1551. ret = smsc911x_eeprom_write_location(pdata, eeprom->offset, *data);
  1552. smsc911x_eeprom_send_cmd(pdata, E2P_CMD_EPC_CMD_EWDS_);
  1553. /* Single byte write, according to man page */
  1554. eeprom->len = 1;
  1555. return ret;
  1556. }
  1557. static const struct ethtool_ops smsc911x_ethtool_ops = {
  1558. .get_settings = smsc911x_ethtool_getsettings,
  1559. .set_settings = smsc911x_ethtool_setsettings,
  1560. .get_link = ethtool_op_get_link,
  1561. .get_drvinfo = smsc911x_ethtool_getdrvinfo,
  1562. .nway_reset = smsc911x_ethtool_nwayreset,
  1563. .get_msglevel = smsc911x_ethtool_getmsglevel,
  1564. .set_msglevel = smsc911x_ethtool_setmsglevel,
  1565. .get_regs_len = smsc911x_ethtool_getregslen,
  1566. .get_regs = smsc911x_ethtool_getregs,
  1567. .get_eeprom_len = smsc911x_ethtool_get_eeprom_len,
  1568. .get_eeprom = smsc911x_ethtool_get_eeprom,
  1569. .set_eeprom = smsc911x_ethtool_set_eeprom,
  1570. };
  1571. static const struct net_device_ops smsc911x_netdev_ops = {
  1572. .ndo_open = smsc911x_open,
  1573. .ndo_stop = smsc911x_stop,
  1574. .ndo_start_xmit = smsc911x_hard_start_xmit,
  1575. .ndo_get_stats = smsc911x_get_stats,
  1576. .ndo_set_rx_mode = smsc911x_set_multicast_list,
  1577. .ndo_do_ioctl = smsc911x_do_ioctl,
  1578. .ndo_change_mtu = eth_change_mtu,
  1579. .ndo_validate_addr = eth_validate_addr,
  1580. .ndo_set_mac_address = smsc911x_set_mac_address,
  1581. #ifdef CONFIG_NET_POLL_CONTROLLER
  1582. .ndo_poll_controller = smsc911x_poll_controller,
  1583. #endif
  1584. };
  1585. /* copies the current mac address from hardware to dev->dev_addr */
  1586. static void __devinit smsc911x_read_mac_address(struct net_device *dev)
  1587. {
  1588. struct smsc911x_data *pdata = netdev_priv(dev);
  1589. u32 mac_high16 = smsc911x_mac_read(pdata, ADDRH);
  1590. u32 mac_low32 = smsc911x_mac_read(pdata, ADDRL);
  1591. dev->dev_addr[0] = (u8)(mac_low32);
  1592. dev->dev_addr[1] = (u8)(mac_low32 >> 8);
  1593. dev->dev_addr[2] = (u8)(mac_low32 >> 16);
  1594. dev->dev_addr[3] = (u8)(mac_low32 >> 24);
  1595. dev->dev_addr[4] = (u8)(mac_high16);
  1596. dev->dev_addr[5] = (u8)(mac_high16 >> 8);
  1597. }
  1598. /* Initializing private device structures, only called from probe */
  1599. static int __devinit smsc911x_init(struct net_device *dev)
  1600. {
  1601. struct smsc911x_data *pdata = netdev_priv(dev);
  1602. unsigned int byte_test;
  1603. SMSC_TRACE(pdata, probe, "Driver Parameters:");
  1604. SMSC_TRACE(pdata, probe, "LAN base: 0x%08lX",
  1605. (unsigned long)pdata->ioaddr);
  1606. SMSC_TRACE(pdata, probe, "IRQ: %d", dev->irq);
  1607. SMSC_TRACE(pdata, probe, "PHY will be autodetected.");
  1608. spin_lock_init(&pdata->dev_lock);
  1609. spin_lock_init(&pdata->mac_lock);
  1610. if (pdata->ioaddr == 0) {
  1611. SMSC_WARN(pdata, probe, "pdata->ioaddr: 0x00000000");
  1612. return -ENODEV;
  1613. }
  1614. /* Check byte ordering */
  1615. byte_test = smsc911x_reg_read(pdata, BYTE_TEST);
  1616. SMSC_TRACE(pdata, probe, "BYTE_TEST: 0x%08X", byte_test);
  1617. if (byte_test == 0x43218765) {
  1618. SMSC_TRACE(pdata, probe, "BYTE_TEST looks swapped, "
  1619. "applying WORD_SWAP");
  1620. smsc911x_reg_write(pdata, WORD_SWAP, 0xffffffff);
  1621. /* 1 dummy read of BYTE_TEST is needed after a write to
  1622. * WORD_SWAP before its contents are valid */
  1623. byte_test = smsc911x_reg_read(pdata, BYTE_TEST);
  1624. byte_test = smsc911x_reg_read(pdata, BYTE_TEST);
  1625. }
  1626. if (byte_test != 0x87654321) {
  1627. SMSC_WARN(pdata, drv, "BYTE_TEST: 0x%08X", byte_test);
  1628. if (((byte_test >> 16) & 0xFFFF) == (byte_test & 0xFFFF)) {
  1629. SMSC_WARN(pdata, probe,
  1630. "top 16 bits equal to bottom 16 bits");
  1631. SMSC_TRACE(pdata, probe,
  1632. "This may mean the chip is set "
  1633. "for 32 bit while the bus is reading 16 bit");
  1634. }
  1635. return -ENODEV;
  1636. }
  1637. /* Default generation to zero (all workarounds apply) */
  1638. pdata->generation = 0;
  1639. pdata->idrev = smsc911x_reg_read(pdata, ID_REV);
  1640. switch (pdata->idrev & 0xFFFF0000) {
  1641. case 0x01180000:
  1642. case 0x01170000:
  1643. case 0x01160000:
  1644. case 0x01150000:
  1645. case 0x218A0000:
  1646. /* LAN911[5678] family */
  1647. pdata->generation = pdata->idrev & 0x0000FFFF;
  1648. break;
  1649. case 0x118A0000:
  1650. case 0x117A0000:
  1651. case 0x116A0000:
  1652. case 0x115A0000:
  1653. /* LAN921[5678] family */
  1654. pdata->generation = 3;
  1655. break;
  1656. case 0x92100000:
  1657. case 0x92110000:
  1658. case 0x92200000:
  1659. case 0x92210000:
  1660. /* LAN9210/LAN9211/LAN9220/LAN9221 */
  1661. pdata->generation = 4;
  1662. break;
  1663. default:
  1664. SMSC_WARN(pdata, probe, "LAN911x not identified, idrev: 0x%08X",
  1665. pdata->idrev);
  1666. return -ENODEV;
  1667. }
  1668. SMSC_TRACE(pdata, probe,
  1669. "LAN911x identified, idrev: 0x%08X, generation: %d",
  1670. pdata->idrev, pdata->generation);
  1671. if (pdata->generation == 0)
  1672. SMSC_WARN(pdata, probe,
  1673. "This driver is not intended for this chip revision");
  1674. /* workaround for platforms without an eeprom, where the mac address
  1675. * is stored elsewhere and set by the bootloader. This saves the
  1676. * mac address before resetting the device */
  1677. if (pdata->config.flags & SMSC911X_SAVE_MAC_ADDRESS) {
  1678. spin_lock_irq(&pdata->mac_lock);
  1679. smsc911x_read_mac_address(dev);
  1680. spin_unlock_irq(&pdata->mac_lock);
  1681. }
  1682. /* Reset the LAN911x */
  1683. if (smsc911x_soft_reset(pdata))
  1684. return -ENODEV;
  1685. /* Disable all interrupt sources until we bring the device up */
  1686. smsc911x_reg_write(pdata, INT_EN, 0);
  1687. ether_setup(dev);
  1688. dev->flags |= IFF_MULTICAST;
  1689. netif_napi_add(dev, &pdata->napi, smsc911x_poll, SMSC_NAPI_WEIGHT);
  1690. dev->netdev_ops = &smsc911x_netdev_ops;
  1691. dev->ethtool_ops = &smsc911x_ethtool_ops;
  1692. return 0;
  1693. }
  1694. static int __devexit smsc911x_drv_remove(struct platform_device *pdev)
  1695. {
  1696. struct net_device *dev;
  1697. struct smsc911x_data *pdata;
  1698. struct resource *res;
  1699. dev = platform_get_drvdata(pdev);
  1700. BUG_ON(!dev);
  1701. pdata = netdev_priv(dev);
  1702. BUG_ON(!pdata);
  1703. BUG_ON(!pdata->ioaddr);
  1704. BUG_ON(!pdata->phy_dev);
  1705. SMSC_TRACE(pdata, ifdown, "Stopping driver");
  1706. phy_disconnect(pdata->phy_dev);
  1707. pdata->phy_dev = NULL;
  1708. mdiobus_unregister(pdata->mii_bus);
  1709. mdiobus_free(pdata->mii_bus);
  1710. platform_set_drvdata(pdev, NULL);
  1711. unregister_netdev(dev);
  1712. free_irq(dev->irq, dev);
  1713. res = platform_get_resource_byname(pdev, IORESOURCE_MEM,
  1714. "smsc911x-memory");
  1715. if (!res)
  1716. res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
  1717. release_mem_region(res->start, resource_size(res));
  1718. iounmap(pdata->ioaddr);
  1719. free_netdev(dev);
  1720. return 0;
  1721. }
  1722. /* standard register acces */
  1723. static const struct smsc911x_ops standard_smsc911x_ops = {
  1724. .reg_read = __smsc911x_reg_read,
  1725. .reg_write = __smsc911x_reg_write,
  1726. .rx_readfifo = smsc911x_rx_readfifo,
  1727. .tx_writefifo = smsc911x_tx_writefifo,
  1728. };
  1729. /* shifted register access */
  1730. static const struct smsc911x_ops shifted_smsc911x_ops = {
  1731. .reg_read = __smsc911x_reg_read_shift,
  1732. .reg_write = __smsc911x_reg_write_shift,
  1733. .rx_readfifo = smsc911x_rx_readfifo_shift,
  1734. .tx_writefifo = smsc911x_tx_writefifo_shift,
  1735. };
  1736. #ifdef CONFIG_OF
  1737. static int __devinit smsc911x_probe_config_dt(
  1738. struct smsc911x_platform_config *config,
  1739. struct device_node *np)
  1740. {
  1741. const char *mac;
  1742. u32 width = 0;
  1743. if (!np)
  1744. return -ENODEV;
  1745. config->phy_interface = of_get_phy_mode(np);
  1746. mac = of_get_mac_address(np);
  1747. if (mac)
  1748. memcpy(config->mac, mac, ETH_ALEN);
  1749. of_property_read_u32(np, "reg-shift", &config->shift);
  1750. of_property_read_u32(np, "reg-io-width", &width);
  1751. if (width == 4)
  1752. config->flags |= SMSC911X_USE_32BIT;
  1753. else
  1754. config->flags |= SMSC911X_USE_16BIT;
  1755. if (of_get_property(np, "smsc,irq-active-high", NULL))
  1756. config->irq_polarity = SMSC911X_IRQ_POLARITY_ACTIVE_HIGH;
  1757. if (of_get_property(np, "smsc,irq-push-pull", NULL))
  1758. config->irq_type = SMSC911X_IRQ_TYPE_PUSH_PULL;
  1759. if (of_get_property(np, "smsc,force-internal-phy", NULL))
  1760. config->flags |= SMSC911X_FORCE_INTERNAL_PHY;
  1761. if (of_get_property(np, "smsc,force-external-phy", NULL))
  1762. config->flags |= SMSC911X_FORCE_EXTERNAL_PHY;
  1763. if (of_get_property(np, "smsc,save-mac-address", NULL))
  1764. config->flags |= SMSC911X_SAVE_MAC_ADDRESS;
  1765. return 0;
  1766. }
  1767. #else
  1768. static inline int smsc911x_probe_config_dt(
  1769. struct smsc911x_platform_config *config,
  1770. struct device_node *np)
  1771. {
  1772. return -ENODEV;
  1773. }
  1774. #endif /* CONFIG_OF */
  1775. static int __devinit smsc911x_drv_probe(struct platform_device *pdev)
  1776. {
  1777. struct device_node *np = pdev->dev.of_node;
  1778. struct net_device *dev;
  1779. struct smsc911x_data *pdata;
  1780. struct smsc911x_platform_config *config = pdev->dev.platform_data;
  1781. struct resource *res, *irq_res;
  1782. unsigned int intcfg = 0;
  1783. int res_size, irq_flags;
  1784. int retval;
  1785. pr_info("Driver version %s\n", SMSC_DRV_VERSION);
  1786. res = platform_get_resource_byname(pdev, IORESOURCE_MEM,
  1787. "smsc911x-memory");
  1788. if (!res)
  1789. res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
  1790. if (!res) {
  1791. pr_warn("Could not allocate resource\n");
  1792. retval = -ENODEV;
  1793. goto out_0;
  1794. }
  1795. res_size = resource_size(res);
  1796. irq_res = platform_get_resource(pdev, IORESOURCE_IRQ, 0);
  1797. if (!irq_res) {
  1798. pr_warn("Could not allocate irq resource\n");
  1799. retval = -ENODEV;
  1800. goto out_0;
  1801. }
  1802. if (!request_mem_region(res->start, res_size, SMSC_CHIPNAME)) {
  1803. retval = -EBUSY;
  1804. goto out_0;
  1805. }
  1806. dev = alloc_etherdev(sizeof(struct smsc911x_data));
  1807. if (!dev) {
  1808. pr_warn("Could not allocate device\n");
  1809. retval = -ENOMEM;
  1810. goto out_release_io_1;
  1811. }
  1812. SET_NETDEV_DEV(dev, &pdev->dev);
  1813. pdata = netdev_priv(dev);
  1814. dev->irq = irq_res->start;
  1815. irq_flags = irq_res->flags & IRQF_TRIGGER_MASK;
  1816. pdata->ioaddr = ioremap_nocache(res->start, res_size);
  1817. pdata->dev = dev;
  1818. pdata->msg_enable = ((1 << debug) - 1);
  1819. if (pdata->ioaddr == NULL) {
  1820. SMSC_WARN(pdata, probe, "Error smsc911x base address invalid");
  1821. retval = -ENOMEM;
  1822. goto out_free_netdev_2;
  1823. }
  1824. retval = smsc911x_probe_config_dt(&pdata->config, np);
  1825. if (retval && config) {
  1826. /* copy config parameters across to pdata */
  1827. memcpy(&pdata->config, config, sizeof(pdata->config));
  1828. retval = 0;
  1829. }
  1830. if (retval) {
  1831. SMSC_WARN(pdata, probe, "Error smsc911x config not found");
  1832. goto out_unmap_io_3;
  1833. }
  1834. /* assume standard, non-shifted, access to HW registers */
  1835. pdata->ops = &standard_smsc911x_ops;
  1836. /* apply the right access if shifting is needed */
  1837. if (pdata->config.shift)
  1838. pdata->ops = &shifted_smsc911x_ops;
  1839. retval = smsc911x_init(dev);
  1840. if (retval < 0)
  1841. goto out_unmap_io_3;
  1842. /* configure irq polarity and type before connecting isr */
  1843. if (pdata->config.irq_polarity == SMSC911X_IRQ_POLARITY_ACTIVE_HIGH)
  1844. intcfg |= INT_CFG_IRQ_POL_;
  1845. if (pdata->config.irq_type == SMSC911X_IRQ_TYPE_PUSH_PULL)
  1846. intcfg |= INT_CFG_IRQ_TYPE_;
  1847. smsc911x_reg_write(pdata, INT_CFG, intcfg);
  1848. /* Ensure interrupts are globally disabled before connecting ISR */
  1849. smsc911x_reg_write(pdata, INT_EN, 0);
  1850. smsc911x_reg_write(pdata, INT_STS, 0xFFFFFFFF);
  1851. retval = request_irq(dev->irq, smsc911x_irqhandler,
  1852. irq_flags | IRQF_SHARED, dev->name, dev);
  1853. if (retval) {
  1854. SMSC_WARN(pdata, probe,
  1855. "Unable to claim requested irq: %d", dev->irq);
  1856. goto out_unmap_io_3;
  1857. }
  1858. platform_set_drvdata(pdev, dev);
  1859. retval = register_netdev(dev);
  1860. if (retval) {
  1861. SMSC_WARN(pdata, probe, "Error %i registering device", retval);
  1862. goto out_unset_drvdata_4;
  1863. } else {
  1864. SMSC_TRACE(pdata, probe,
  1865. "Network interface: \"%s\"", dev->name);
  1866. }
  1867. retval = smsc911x_mii_init(pdev, dev);
  1868. if (retval) {
  1869. SMSC_WARN(pdata, probe, "Error %i initialising mii", retval);
  1870. goto out_unregister_netdev_5;
  1871. }
  1872. spin_lock_irq(&pdata->mac_lock);
  1873. /* Check if mac address has been specified when bringing interface up */
  1874. if (is_valid_ether_addr(dev->dev_addr)) {
  1875. smsc911x_set_hw_mac_address(pdata, dev->dev_addr);
  1876. SMSC_TRACE(pdata, probe,
  1877. "MAC Address is specified by configuration");
  1878. } else if (is_valid_ether_addr(pdata->config.mac)) {
  1879. memcpy(dev->dev_addr, pdata->config.mac, 6);
  1880. SMSC_TRACE(pdata, probe,
  1881. "MAC Address specified by platform data");
  1882. } else {
  1883. /* Try reading mac address from device. if EEPROM is present
  1884. * it will already have been set */
  1885. smsc_get_mac(dev);
  1886. if (is_valid_ether_addr(dev->dev_addr)) {
  1887. /* eeprom values are valid so use them */
  1888. SMSC_TRACE(pdata, probe,
  1889. "Mac Address is read from LAN911x EEPROM");
  1890. } else {
  1891. /* eeprom values are invalid, generate random MAC */
  1892. random_ether_addr(dev->dev_addr);
  1893. smsc911x_set_hw_mac_address(pdata, dev->dev_addr);
  1894. SMSC_TRACE(pdata, probe,
  1895. "MAC Address is set to random_ether_addr");
  1896. }
  1897. }
  1898. spin_unlock_irq(&pdata->mac_lock);
  1899. netdev_info(dev, "MAC Address: %pM\n", dev->dev_addr);
  1900. return 0;
  1901. out_unregister_netdev_5:
  1902. unregister_netdev(dev);
  1903. out_unset_drvdata_4:
  1904. platform_set_drvdata(pdev, NULL);
  1905. free_irq(dev->irq, dev);
  1906. out_unmap_io_3:
  1907. iounmap(pdata->ioaddr);
  1908. out_free_netdev_2:
  1909. free_netdev(dev);
  1910. out_release_io_1:
  1911. release_mem_region(res->start, resource_size(res));
  1912. out_0:
  1913. return retval;
  1914. }
  1915. #ifdef CONFIG_PM
  1916. /* This implementation assumes the devices remains powered on its VDDVARIO
  1917. * pins during suspend. */
  1918. /* TODO: implement freeze/thaw callbacks for hibernation.*/
  1919. static int smsc911x_suspend(struct device *dev)
  1920. {
  1921. struct net_device *ndev = dev_get_drvdata(dev);
  1922. struct smsc911x_data *pdata = netdev_priv(ndev);
  1923. /* enable wake on LAN, energy detection and the external PME
  1924. * signal. */
  1925. smsc911x_reg_write(pdata, PMT_CTRL,
  1926. PMT_CTRL_PM_MODE_D1_ | PMT_CTRL_WOL_EN_ |
  1927. PMT_CTRL_ED_EN_ | PMT_CTRL_PME_EN_);
  1928. return 0;
  1929. }
  1930. static int smsc911x_resume(struct device *dev)
  1931. {
  1932. struct net_device *ndev = dev_get_drvdata(dev);
  1933. struct smsc911x_data *pdata = netdev_priv(ndev);
  1934. unsigned int to = 100;
  1935. /* Note 3.11 from the datasheet:
  1936. * "When the LAN9220 is in a power saving state, a write of any
  1937. * data to the BYTE_TEST register will wake-up the device."
  1938. */
  1939. smsc911x_reg_write(pdata, BYTE_TEST, 0);
  1940. /* poll the READY bit in PMT_CTRL. Any other access to the device is
  1941. * forbidden while this bit isn't set. Try for 100ms and return -EIO
  1942. * if it failed. */
  1943. while (!(smsc911x_reg_read(pdata, PMT_CTRL) & PMT_CTRL_READY_) && --to)
  1944. udelay(1000);
  1945. return (to == 0) ? -EIO : 0;
  1946. }
  1947. static const struct dev_pm_ops smsc911x_pm_ops = {
  1948. .suspend = smsc911x_suspend,
  1949. .resume = smsc911x_resume,
  1950. };
  1951. #define SMSC911X_PM_OPS (&smsc911x_pm_ops)
  1952. #else
  1953. #define SMSC911X_PM_OPS NULL
  1954. #endif
  1955. static const struct of_device_id smsc911x_dt_ids[] = {
  1956. { .compatible = "smsc,lan9115", },
  1957. { /* sentinel */ }
  1958. };
  1959. MODULE_DEVICE_TABLE(of, smsc911x_dt_ids);
  1960. static struct platform_driver smsc911x_driver = {
  1961. .probe = smsc911x_drv_probe,
  1962. .remove = __devexit_p(smsc911x_drv_remove),
  1963. .driver = {
  1964. .name = SMSC_CHIPNAME,
  1965. .owner = THIS_MODULE,
  1966. .pm = SMSC911X_PM_OPS,
  1967. .of_match_table = smsc911x_dt_ids,
  1968. },
  1969. };
  1970. /* Entry point for loading the module */
  1971. static int __init smsc911x_init_module(void)
  1972. {
  1973. SMSC_INITIALIZE();
  1974. return platform_driver_register(&smsc911x_driver);
  1975. }
  1976. /* entry point for unloading the module */
  1977. static void __exit smsc911x_cleanup_module(void)
  1978. {
  1979. platform_driver_unregister(&smsc911x_driver);
  1980. }
  1981. module_init(smsc911x_init_module);
  1982. module_exit(smsc911x_cleanup_module);