sh_eth.c 48 KB

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  1. /*
  2. * SuperH Ethernet device driver
  3. *
  4. * Copyright (C) 2006-2008 Nobuhiro Iwamatsu
  5. * Copyright (C) 2008-2009 Renesas Solutions Corp.
  6. *
  7. * This program is free software; you can redistribute it and/or modify it
  8. * under the terms and conditions of the GNU General Public License,
  9. * version 2, as published by the Free Software Foundation.
  10. *
  11. * This program is distributed in the hope it will be useful, but WITHOUT
  12. * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  13. * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
  14. * more details.
  15. * You should have received a copy of the GNU General Public License along with
  16. * this program; if not, write to the Free Software Foundation, Inc.,
  17. * 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
  18. *
  19. * The full GNU General Public License is included in this distribution in
  20. * the file called "COPYING".
  21. */
  22. #include <linux/init.h>
  23. #include <linux/module.h>
  24. #include <linux/kernel.h>
  25. #include <linux/spinlock.h>
  26. #include <linux/interrupt.h>
  27. #include <linux/dma-mapping.h>
  28. #include <linux/etherdevice.h>
  29. #include <linux/delay.h>
  30. #include <linux/platform_device.h>
  31. #include <linux/mdio-bitbang.h>
  32. #include <linux/netdevice.h>
  33. #include <linux/phy.h>
  34. #include <linux/cache.h>
  35. #include <linux/io.h>
  36. #include <linux/interrupt.h>
  37. #include <linux/pm_runtime.h>
  38. #include <linux/slab.h>
  39. #include <linux/ethtool.h>
  40. #include <linux/sh_eth.h>
  41. #include "sh_eth.h"
  42. #define SH_ETH_DEF_MSG_ENABLE \
  43. (NETIF_MSG_LINK | \
  44. NETIF_MSG_TIMER | \
  45. NETIF_MSG_RX_ERR| \
  46. NETIF_MSG_TX_ERR)
  47. /* There is CPU dependent code */
  48. #if defined(CONFIG_CPU_SUBTYPE_SH7724)
  49. #define SH_ETH_RESET_DEFAULT 1
  50. static void sh_eth_set_duplex(struct net_device *ndev)
  51. {
  52. struct sh_eth_private *mdp = netdev_priv(ndev);
  53. if (mdp->duplex) /* Full */
  54. sh_eth_write(ndev, sh_eth_read(ndev, ECMR) | ECMR_DM, ECMR);
  55. else /* Half */
  56. sh_eth_write(ndev, sh_eth_read(ndev, ECMR) & ~ECMR_DM, ECMR);
  57. }
  58. static void sh_eth_set_rate(struct net_device *ndev)
  59. {
  60. struct sh_eth_private *mdp = netdev_priv(ndev);
  61. switch (mdp->speed) {
  62. case 10: /* 10BASE */
  63. sh_eth_write(ndev, sh_eth_read(ndev, ECMR) & ~ECMR_RTM, ECMR);
  64. break;
  65. case 100:/* 100BASE */
  66. sh_eth_write(ndev, sh_eth_read(ndev, ECMR) | ECMR_RTM, ECMR);
  67. break;
  68. default:
  69. break;
  70. }
  71. }
  72. /* SH7724 */
  73. static struct sh_eth_cpu_data sh_eth_my_cpu_data = {
  74. .set_duplex = sh_eth_set_duplex,
  75. .set_rate = sh_eth_set_rate,
  76. .ecsr_value = ECSR_PSRTO | ECSR_LCHNG | ECSR_ICD,
  77. .ecsipr_value = ECSIPR_PSRTOIP | ECSIPR_LCHNGIP | ECSIPR_ICDIP,
  78. .eesipr_value = DMAC_M_RFRMER | DMAC_M_ECI | 0x01ff009f,
  79. .tx_check = EESR_FTC | EESR_CND | EESR_DLC | EESR_CD | EESR_RTO,
  80. .eesr_err_check = EESR_TWB | EESR_TABT | EESR_RABT | EESR_RDE |
  81. EESR_RFRMER | EESR_TFE | EESR_TDE | EESR_ECI,
  82. .tx_error_check = EESR_TWB | EESR_TABT | EESR_TDE | EESR_TFE,
  83. .apr = 1,
  84. .mpr = 1,
  85. .tpauser = 1,
  86. .hw_swap = 1,
  87. .rpadir = 1,
  88. .rpadir_value = 0x00020000, /* NET_IP_ALIGN assumed to be 2 */
  89. };
  90. #elif defined(CONFIG_CPU_SUBTYPE_SH7757)
  91. #define SH_ETH_HAS_BOTH_MODULES 1
  92. #define SH_ETH_HAS_TSU 1
  93. static void sh_eth_set_duplex(struct net_device *ndev)
  94. {
  95. struct sh_eth_private *mdp = netdev_priv(ndev);
  96. if (mdp->duplex) /* Full */
  97. sh_eth_write(ndev, sh_eth_read(ndev, ECMR) | ECMR_DM, ECMR);
  98. else /* Half */
  99. sh_eth_write(ndev, sh_eth_read(ndev, ECMR) & ~ECMR_DM, ECMR);
  100. }
  101. static void sh_eth_set_rate(struct net_device *ndev)
  102. {
  103. struct sh_eth_private *mdp = netdev_priv(ndev);
  104. switch (mdp->speed) {
  105. case 10: /* 10BASE */
  106. sh_eth_write(ndev, 0, RTRATE);
  107. break;
  108. case 100:/* 100BASE */
  109. sh_eth_write(ndev, 1, RTRATE);
  110. break;
  111. default:
  112. break;
  113. }
  114. }
  115. /* SH7757 */
  116. static struct sh_eth_cpu_data sh_eth_my_cpu_data = {
  117. .set_duplex = sh_eth_set_duplex,
  118. .set_rate = sh_eth_set_rate,
  119. .eesipr_value = DMAC_M_RFRMER | DMAC_M_ECI | 0x003fffff,
  120. .rmcr_value = 0x00000001,
  121. .tx_check = EESR_FTC | EESR_CND | EESR_DLC | EESR_CD | EESR_RTO,
  122. .eesr_err_check = EESR_TWB | EESR_TABT | EESR_RABT | EESR_RDE |
  123. EESR_RFRMER | EESR_TFE | EESR_TDE | EESR_ECI,
  124. .tx_error_check = EESR_TWB | EESR_TABT | EESR_TDE | EESR_TFE,
  125. .apr = 1,
  126. .mpr = 1,
  127. .tpauser = 1,
  128. .hw_swap = 1,
  129. .no_ade = 1,
  130. .rpadir = 1,
  131. .rpadir_value = 2 << 16,
  132. };
  133. #define SH_GIGA_ETH_BASE 0xfee00000
  134. #define GIGA_MALR(port) (SH_GIGA_ETH_BASE + 0x800 * (port) + 0x05c8)
  135. #define GIGA_MAHR(port) (SH_GIGA_ETH_BASE + 0x800 * (port) + 0x05c0)
  136. static void sh_eth_chip_reset_giga(struct net_device *ndev)
  137. {
  138. int i;
  139. unsigned long mahr[2], malr[2];
  140. /* save MAHR and MALR */
  141. for (i = 0; i < 2; i++) {
  142. malr[i] = ioread32((void *)GIGA_MALR(i));
  143. mahr[i] = ioread32((void *)GIGA_MAHR(i));
  144. }
  145. /* reset device */
  146. iowrite32(ARSTR_ARSTR, (void *)(SH_GIGA_ETH_BASE + 0x1800));
  147. mdelay(1);
  148. /* restore MAHR and MALR */
  149. for (i = 0; i < 2; i++) {
  150. iowrite32(malr[i], (void *)GIGA_MALR(i));
  151. iowrite32(mahr[i], (void *)GIGA_MAHR(i));
  152. }
  153. }
  154. static int sh_eth_is_gether(struct sh_eth_private *mdp);
  155. static void sh_eth_reset(struct net_device *ndev)
  156. {
  157. struct sh_eth_private *mdp = netdev_priv(ndev);
  158. int cnt = 100;
  159. if (sh_eth_is_gether(mdp)) {
  160. sh_eth_write(ndev, 0x03, EDSR);
  161. sh_eth_write(ndev, sh_eth_read(ndev, EDMR) | EDMR_SRST_GETHER,
  162. EDMR);
  163. while (cnt > 0) {
  164. if (!(sh_eth_read(ndev, EDMR) & 0x3))
  165. break;
  166. mdelay(1);
  167. cnt--;
  168. }
  169. if (cnt < 0)
  170. printk(KERN_ERR "Device reset fail\n");
  171. /* Table Init */
  172. sh_eth_write(ndev, 0x0, TDLAR);
  173. sh_eth_write(ndev, 0x0, TDFAR);
  174. sh_eth_write(ndev, 0x0, TDFXR);
  175. sh_eth_write(ndev, 0x0, TDFFR);
  176. sh_eth_write(ndev, 0x0, RDLAR);
  177. sh_eth_write(ndev, 0x0, RDFAR);
  178. sh_eth_write(ndev, 0x0, RDFXR);
  179. sh_eth_write(ndev, 0x0, RDFFR);
  180. } else {
  181. sh_eth_write(ndev, sh_eth_read(ndev, EDMR) | EDMR_SRST_ETHER,
  182. EDMR);
  183. mdelay(3);
  184. sh_eth_write(ndev, sh_eth_read(ndev, EDMR) & ~EDMR_SRST_ETHER,
  185. EDMR);
  186. }
  187. }
  188. static void sh_eth_set_duplex_giga(struct net_device *ndev)
  189. {
  190. struct sh_eth_private *mdp = netdev_priv(ndev);
  191. if (mdp->duplex) /* Full */
  192. sh_eth_write(ndev, sh_eth_read(ndev, ECMR) | ECMR_DM, ECMR);
  193. else /* Half */
  194. sh_eth_write(ndev, sh_eth_read(ndev, ECMR) & ~ECMR_DM, ECMR);
  195. }
  196. static void sh_eth_set_rate_giga(struct net_device *ndev)
  197. {
  198. struct sh_eth_private *mdp = netdev_priv(ndev);
  199. switch (mdp->speed) {
  200. case 10: /* 10BASE */
  201. sh_eth_write(ndev, 0x00000000, GECMR);
  202. break;
  203. case 100:/* 100BASE */
  204. sh_eth_write(ndev, 0x00000010, GECMR);
  205. break;
  206. case 1000: /* 1000BASE */
  207. sh_eth_write(ndev, 0x00000020, GECMR);
  208. break;
  209. default:
  210. break;
  211. }
  212. }
  213. /* SH7757(GETHERC) */
  214. static struct sh_eth_cpu_data sh_eth_my_cpu_data_giga = {
  215. .chip_reset = sh_eth_chip_reset_giga,
  216. .set_duplex = sh_eth_set_duplex_giga,
  217. .set_rate = sh_eth_set_rate_giga,
  218. .ecsr_value = ECSR_ICD | ECSR_MPD,
  219. .ecsipr_value = ECSIPR_LCHNGIP | ECSIPR_ICDIP | ECSIPR_MPDIP,
  220. .eesipr_value = DMAC_M_RFRMER | DMAC_M_ECI | 0x003fffff,
  221. .tx_check = EESR_TC1 | EESR_FTC,
  222. .eesr_err_check = EESR_TWB1 | EESR_TWB | EESR_TABT | EESR_RABT | \
  223. EESR_RDE | EESR_RFRMER | EESR_TFE | EESR_TDE | \
  224. EESR_ECI,
  225. .tx_error_check = EESR_TWB1 | EESR_TWB | EESR_TABT | EESR_TDE | \
  226. EESR_TFE,
  227. .fdr_value = 0x0000072f,
  228. .rmcr_value = 0x00000001,
  229. .apr = 1,
  230. .mpr = 1,
  231. .tpauser = 1,
  232. .bculr = 1,
  233. .hw_swap = 1,
  234. .rpadir = 1,
  235. .rpadir_value = 2 << 16,
  236. .no_trimd = 1,
  237. .no_ade = 1,
  238. };
  239. static struct sh_eth_cpu_data *sh_eth_get_cpu_data(struct sh_eth_private *mdp)
  240. {
  241. if (sh_eth_is_gether(mdp))
  242. return &sh_eth_my_cpu_data_giga;
  243. else
  244. return &sh_eth_my_cpu_data;
  245. }
  246. #elif defined(CONFIG_CPU_SUBTYPE_SH7763)
  247. #define SH_ETH_HAS_TSU 1
  248. static void sh_eth_chip_reset(struct net_device *ndev)
  249. {
  250. struct sh_eth_private *mdp = netdev_priv(ndev);
  251. /* reset device */
  252. sh_eth_tsu_write(mdp, ARSTR_ARSTR, ARSTR);
  253. mdelay(1);
  254. }
  255. static void sh_eth_reset(struct net_device *ndev)
  256. {
  257. int cnt = 100;
  258. sh_eth_write(ndev, EDSR_ENALL, EDSR);
  259. sh_eth_write(ndev, sh_eth_read(ndev, EDMR) | EDMR_SRST_GETHER, EDMR);
  260. while (cnt > 0) {
  261. if (!(sh_eth_read(ndev, EDMR) & 0x3))
  262. break;
  263. mdelay(1);
  264. cnt--;
  265. }
  266. if (cnt == 0)
  267. printk(KERN_ERR "Device reset fail\n");
  268. /* Table Init */
  269. sh_eth_write(ndev, 0x0, TDLAR);
  270. sh_eth_write(ndev, 0x0, TDFAR);
  271. sh_eth_write(ndev, 0x0, TDFXR);
  272. sh_eth_write(ndev, 0x0, TDFFR);
  273. sh_eth_write(ndev, 0x0, RDLAR);
  274. sh_eth_write(ndev, 0x0, RDFAR);
  275. sh_eth_write(ndev, 0x0, RDFXR);
  276. sh_eth_write(ndev, 0x0, RDFFR);
  277. }
  278. static void sh_eth_set_duplex(struct net_device *ndev)
  279. {
  280. struct sh_eth_private *mdp = netdev_priv(ndev);
  281. if (mdp->duplex) /* Full */
  282. sh_eth_write(ndev, sh_eth_read(ndev, ECMR) | ECMR_DM, ECMR);
  283. else /* Half */
  284. sh_eth_write(ndev, sh_eth_read(ndev, ECMR) & ~ECMR_DM, ECMR);
  285. }
  286. static void sh_eth_set_rate(struct net_device *ndev)
  287. {
  288. struct sh_eth_private *mdp = netdev_priv(ndev);
  289. switch (mdp->speed) {
  290. case 10: /* 10BASE */
  291. sh_eth_write(ndev, GECMR_10, GECMR);
  292. break;
  293. case 100:/* 100BASE */
  294. sh_eth_write(ndev, GECMR_100, GECMR);
  295. break;
  296. case 1000: /* 1000BASE */
  297. sh_eth_write(ndev, GECMR_1000, GECMR);
  298. break;
  299. default:
  300. break;
  301. }
  302. }
  303. /* sh7763 */
  304. static struct sh_eth_cpu_data sh_eth_my_cpu_data = {
  305. .chip_reset = sh_eth_chip_reset,
  306. .set_duplex = sh_eth_set_duplex,
  307. .set_rate = sh_eth_set_rate,
  308. .ecsr_value = ECSR_ICD | ECSR_MPD,
  309. .ecsipr_value = ECSIPR_LCHNGIP | ECSIPR_ICDIP | ECSIPR_MPDIP,
  310. .eesipr_value = DMAC_M_RFRMER | DMAC_M_ECI | 0x003fffff,
  311. .tx_check = EESR_TC1 | EESR_FTC,
  312. .eesr_err_check = EESR_TWB1 | EESR_TWB | EESR_TABT | EESR_RABT | \
  313. EESR_RDE | EESR_RFRMER | EESR_TFE | EESR_TDE | \
  314. EESR_ECI,
  315. .tx_error_check = EESR_TWB1 | EESR_TWB | EESR_TABT | EESR_TDE | \
  316. EESR_TFE,
  317. .apr = 1,
  318. .mpr = 1,
  319. .tpauser = 1,
  320. .bculr = 1,
  321. .hw_swap = 1,
  322. .no_trimd = 1,
  323. .no_ade = 1,
  324. .tsu = 1,
  325. };
  326. #elif defined(CONFIG_CPU_SUBTYPE_SH7619)
  327. #define SH_ETH_RESET_DEFAULT 1
  328. static struct sh_eth_cpu_data sh_eth_my_cpu_data = {
  329. .eesipr_value = DMAC_M_RFRMER | DMAC_M_ECI | 0x003fffff,
  330. .apr = 1,
  331. .mpr = 1,
  332. .tpauser = 1,
  333. .hw_swap = 1,
  334. };
  335. #elif defined(CONFIG_CPU_SUBTYPE_SH7710) || defined(CONFIG_CPU_SUBTYPE_SH7712)
  336. #define SH_ETH_RESET_DEFAULT 1
  337. #define SH_ETH_HAS_TSU 1
  338. static struct sh_eth_cpu_data sh_eth_my_cpu_data = {
  339. .eesipr_value = DMAC_M_RFRMER | DMAC_M_ECI | 0x003fffff,
  340. .tsu = 1,
  341. };
  342. #endif
  343. static void sh_eth_set_default_cpu_data(struct sh_eth_cpu_data *cd)
  344. {
  345. if (!cd->ecsr_value)
  346. cd->ecsr_value = DEFAULT_ECSR_INIT;
  347. if (!cd->ecsipr_value)
  348. cd->ecsipr_value = DEFAULT_ECSIPR_INIT;
  349. if (!cd->fcftr_value)
  350. cd->fcftr_value = DEFAULT_FIFO_F_D_RFF | \
  351. DEFAULT_FIFO_F_D_RFD;
  352. if (!cd->fdr_value)
  353. cd->fdr_value = DEFAULT_FDR_INIT;
  354. if (!cd->rmcr_value)
  355. cd->rmcr_value = DEFAULT_RMCR_VALUE;
  356. if (!cd->tx_check)
  357. cd->tx_check = DEFAULT_TX_CHECK;
  358. if (!cd->eesr_err_check)
  359. cd->eesr_err_check = DEFAULT_EESR_ERR_CHECK;
  360. if (!cd->tx_error_check)
  361. cd->tx_error_check = DEFAULT_TX_ERROR_CHECK;
  362. }
  363. #if defined(SH_ETH_RESET_DEFAULT)
  364. /* Chip Reset */
  365. static void sh_eth_reset(struct net_device *ndev)
  366. {
  367. sh_eth_write(ndev, sh_eth_read(ndev, EDMR) | EDMR_SRST_ETHER, EDMR);
  368. mdelay(3);
  369. sh_eth_write(ndev, sh_eth_read(ndev, EDMR) & ~EDMR_SRST_ETHER, EDMR);
  370. }
  371. #endif
  372. #if defined(CONFIG_CPU_SH4)
  373. static void sh_eth_set_receive_align(struct sk_buff *skb)
  374. {
  375. int reserve;
  376. reserve = SH4_SKB_RX_ALIGN - ((u32)skb->data & (SH4_SKB_RX_ALIGN - 1));
  377. if (reserve)
  378. skb_reserve(skb, reserve);
  379. }
  380. #else
  381. static void sh_eth_set_receive_align(struct sk_buff *skb)
  382. {
  383. skb_reserve(skb, SH2_SH3_SKB_RX_ALIGN);
  384. }
  385. #endif
  386. /* CPU <-> EDMAC endian convert */
  387. static inline __u32 cpu_to_edmac(struct sh_eth_private *mdp, u32 x)
  388. {
  389. switch (mdp->edmac_endian) {
  390. case EDMAC_LITTLE_ENDIAN:
  391. return cpu_to_le32(x);
  392. case EDMAC_BIG_ENDIAN:
  393. return cpu_to_be32(x);
  394. }
  395. return x;
  396. }
  397. static inline __u32 edmac_to_cpu(struct sh_eth_private *mdp, u32 x)
  398. {
  399. switch (mdp->edmac_endian) {
  400. case EDMAC_LITTLE_ENDIAN:
  401. return le32_to_cpu(x);
  402. case EDMAC_BIG_ENDIAN:
  403. return be32_to_cpu(x);
  404. }
  405. return x;
  406. }
  407. /*
  408. * Program the hardware MAC address from dev->dev_addr.
  409. */
  410. static void update_mac_address(struct net_device *ndev)
  411. {
  412. sh_eth_write(ndev,
  413. (ndev->dev_addr[0] << 24) | (ndev->dev_addr[1] << 16) |
  414. (ndev->dev_addr[2] << 8) | (ndev->dev_addr[3]), MAHR);
  415. sh_eth_write(ndev,
  416. (ndev->dev_addr[4] << 8) | (ndev->dev_addr[5]), MALR);
  417. }
  418. /*
  419. * Get MAC address from SuperH MAC address register
  420. *
  421. * SuperH's Ethernet device doesn't have 'ROM' to MAC address.
  422. * This driver get MAC address that use by bootloader(U-boot or sh-ipl+g).
  423. * When you want use this device, you must set MAC address in bootloader.
  424. *
  425. */
  426. static void read_mac_address(struct net_device *ndev, unsigned char *mac)
  427. {
  428. if (mac[0] || mac[1] || mac[2] || mac[3] || mac[4] || mac[5]) {
  429. memcpy(ndev->dev_addr, mac, 6);
  430. } else {
  431. ndev->dev_addr[0] = (sh_eth_read(ndev, MAHR) >> 24);
  432. ndev->dev_addr[1] = (sh_eth_read(ndev, MAHR) >> 16) & 0xFF;
  433. ndev->dev_addr[2] = (sh_eth_read(ndev, MAHR) >> 8) & 0xFF;
  434. ndev->dev_addr[3] = (sh_eth_read(ndev, MAHR) & 0xFF);
  435. ndev->dev_addr[4] = (sh_eth_read(ndev, MALR) >> 8) & 0xFF;
  436. ndev->dev_addr[5] = (sh_eth_read(ndev, MALR) & 0xFF);
  437. }
  438. }
  439. static int sh_eth_is_gether(struct sh_eth_private *mdp)
  440. {
  441. if (mdp->reg_offset == sh_eth_offset_gigabit)
  442. return 1;
  443. else
  444. return 0;
  445. }
  446. static unsigned long sh_eth_get_edtrr_trns(struct sh_eth_private *mdp)
  447. {
  448. if (sh_eth_is_gether(mdp))
  449. return EDTRR_TRNS_GETHER;
  450. else
  451. return EDTRR_TRNS_ETHER;
  452. }
  453. struct bb_info {
  454. void (*set_gate)(void *addr);
  455. struct mdiobb_ctrl ctrl;
  456. void *addr;
  457. u32 mmd_msk;/* MMD */
  458. u32 mdo_msk;
  459. u32 mdi_msk;
  460. u32 mdc_msk;
  461. };
  462. /* PHY bit set */
  463. static void bb_set(void *addr, u32 msk)
  464. {
  465. iowrite32(ioread32(addr) | msk, addr);
  466. }
  467. /* PHY bit clear */
  468. static void bb_clr(void *addr, u32 msk)
  469. {
  470. iowrite32((ioread32(addr) & ~msk), addr);
  471. }
  472. /* PHY bit read */
  473. static int bb_read(void *addr, u32 msk)
  474. {
  475. return (ioread32(addr) & msk) != 0;
  476. }
  477. /* Data I/O pin control */
  478. static void sh_mmd_ctrl(struct mdiobb_ctrl *ctrl, int bit)
  479. {
  480. struct bb_info *bitbang = container_of(ctrl, struct bb_info, ctrl);
  481. if (bitbang->set_gate)
  482. bitbang->set_gate(bitbang->addr);
  483. if (bit)
  484. bb_set(bitbang->addr, bitbang->mmd_msk);
  485. else
  486. bb_clr(bitbang->addr, bitbang->mmd_msk);
  487. }
  488. /* Set bit data*/
  489. static void sh_set_mdio(struct mdiobb_ctrl *ctrl, int bit)
  490. {
  491. struct bb_info *bitbang = container_of(ctrl, struct bb_info, ctrl);
  492. if (bitbang->set_gate)
  493. bitbang->set_gate(bitbang->addr);
  494. if (bit)
  495. bb_set(bitbang->addr, bitbang->mdo_msk);
  496. else
  497. bb_clr(bitbang->addr, bitbang->mdo_msk);
  498. }
  499. /* Get bit data*/
  500. static int sh_get_mdio(struct mdiobb_ctrl *ctrl)
  501. {
  502. struct bb_info *bitbang = container_of(ctrl, struct bb_info, ctrl);
  503. if (bitbang->set_gate)
  504. bitbang->set_gate(bitbang->addr);
  505. return bb_read(bitbang->addr, bitbang->mdi_msk);
  506. }
  507. /* MDC pin control */
  508. static void sh_mdc_ctrl(struct mdiobb_ctrl *ctrl, int bit)
  509. {
  510. struct bb_info *bitbang = container_of(ctrl, struct bb_info, ctrl);
  511. if (bitbang->set_gate)
  512. bitbang->set_gate(bitbang->addr);
  513. if (bit)
  514. bb_set(bitbang->addr, bitbang->mdc_msk);
  515. else
  516. bb_clr(bitbang->addr, bitbang->mdc_msk);
  517. }
  518. /* mdio bus control struct */
  519. static struct mdiobb_ops bb_ops = {
  520. .owner = THIS_MODULE,
  521. .set_mdc = sh_mdc_ctrl,
  522. .set_mdio_dir = sh_mmd_ctrl,
  523. .set_mdio_data = sh_set_mdio,
  524. .get_mdio_data = sh_get_mdio,
  525. };
  526. /* free skb and descriptor buffer */
  527. static void sh_eth_ring_free(struct net_device *ndev)
  528. {
  529. struct sh_eth_private *mdp = netdev_priv(ndev);
  530. int i;
  531. /* Free Rx skb ringbuffer */
  532. if (mdp->rx_skbuff) {
  533. for (i = 0; i < RX_RING_SIZE; i++) {
  534. if (mdp->rx_skbuff[i])
  535. dev_kfree_skb(mdp->rx_skbuff[i]);
  536. }
  537. }
  538. kfree(mdp->rx_skbuff);
  539. /* Free Tx skb ringbuffer */
  540. if (mdp->tx_skbuff) {
  541. for (i = 0; i < TX_RING_SIZE; i++) {
  542. if (mdp->tx_skbuff[i])
  543. dev_kfree_skb(mdp->tx_skbuff[i]);
  544. }
  545. }
  546. kfree(mdp->tx_skbuff);
  547. }
  548. /* format skb and descriptor buffer */
  549. static void sh_eth_ring_format(struct net_device *ndev)
  550. {
  551. struct sh_eth_private *mdp = netdev_priv(ndev);
  552. int i;
  553. struct sk_buff *skb;
  554. struct sh_eth_rxdesc *rxdesc = NULL;
  555. struct sh_eth_txdesc *txdesc = NULL;
  556. int rx_ringsize = sizeof(*rxdesc) * RX_RING_SIZE;
  557. int tx_ringsize = sizeof(*txdesc) * TX_RING_SIZE;
  558. mdp->cur_rx = mdp->cur_tx = 0;
  559. mdp->dirty_rx = mdp->dirty_tx = 0;
  560. memset(mdp->rx_ring, 0, rx_ringsize);
  561. /* build Rx ring buffer */
  562. for (i = 0; i < RX_RING_SIZE; i++) {
  563. /* skb */
  564. mdp->rx_skbuff[i] = NULL;
  565. skb = dev_alloc_skb(mdp->rx_buf_sz);
  566. mdp->rx_skbuff[i] = skb;
  567. if (skb == NULL)
  568. break;
  569. dma_map_single(&ndev->dev, skb->tail, mdp->rx_buf_sz,
  570. DMA_FROM_DEVICE);
  571. skb->dev = ndev; /* Mark as being used by this device. */
  572. sh_eth_set_receive_align(skb);
  573. /* RX descriptor */
  574. rxdesc = &mdp->rx_ring[i];
  575. rxdesc->addr = virt_to_phys(PTR_ALIGN(skb->data, 4));
  576. rxdesc->status = cpu_to_edmac(mdp, RD_RACT | RD_RFP);
  577. /* The size of the buffer is 16 byte boundary. */
  578. rxdesc->buffer_length = ALIGN(mdp->rx_buf_sz, 16);
  579. /* Rx descriptor address set */
  580. if (i == 0) {
  581. sh_eth_write(ndev, mdp->rx_desc_dma, RDLAR);
  582. if (sh_eth_is_gether(mdp))
  583. sh_eth_write(ndev, mdp->rx_desc_dma, RDFAR);
  584. }
  585. }
  586. mdp->dirty_rx = (u32) (i - RX_RING_SIZE);
  587. /* Mark the last entry as wrapping the ring. */
  588. rxdesc->status |= cpu_to_edmac(mdp, RD_RDEL);
  589. memset(mdp->tx_ring, 0, tx_ringsize);
  590. /* build Tx ring buffer */
  591. for (i = 0; i < TX_RING_SIZE; i++) {
  592. mdp->tx_skbuff[i] = NULL;
  593. txdesc = &mdp->tx_ring[i];
  594. txdesc->status = cpu_to_edmac(mdp, TD_TFP);
  595. txdesc->buffer_length = 0;
  596. if (i == 0) {
  597. /* Tx descriptor address set */
  598. sh_eth_write(ndev, mdp->tx_desc_dma, TDLAR);
  599. if (sh_eth_is_gether(mdp))
  600. sh_eth_write(ndev, mdp->tx_desc_dma, TDFAR);
  601. }
  602. }
  603. txdesc->status |= cpu_to_edmac(mdp, TD_TDLE);
  604. }
  605. /* Get skb and descriptor buffer */
  606. static int sh_eth_ring_init(struct net_device *ndev)
  607. {
  608. struct sh_eth_private *mdp = netdev_priv(ndev);
  609. int rx_ringsize, tx_ringsize, ret = 0;
  610. /*
  611. * +26 gets the maximum ethernet encapsulation, +7 & ~7 because the
  612. * card needs room to do 8 byte alignment, +2 so we can reserve
  613. * the first 2 bytes, and +16 gets room for the status word from the
  614. * card.
  615. */
  616. mdp->rx_buf_sz = (ndev->mtu <= 1492 ? PKT_BUF_SZ :
  617. (((ndev->mtu + 26 + 7) & ~7) + 2 + 16));
  618. if (mdp->cd->rpadir)
  619. mdp->rx_buf_sz += NET_IP_ALIGN;
  620. /* Allocate RX and TX skb rings */
  621. mdp->rx_skbuff = kmalloc(sizeof(*mdp->rx_skbuff) * RX_RING_SIZE,
  622. GFP_KERNEL);
  623. if (!mdp->rx_skbuff) {
  624. dev_err(&ndev->dev, "Cannot allocate Rx skb\n");
  625. ret = -ENOMEM;
  626. return ret;
  627. }
  628. mdp->tx_skbuff = kmalloc(sizeof(*mdp->tx_skbuff) * TX_RING_SIZE,
  629. GFP_KERNEL);
  630. if (!mdp->tx_skbuff) {
  631. dev_err(&ndev->dev, "Cannot allocate Tx skb\n");
  632. ret = -ENOMEM;
  633. goto skb_ring_free;
  634. }
  635. /* Allocate all Rx descriptors. */
  636. rx_ringsize = sizeof(struct sh_eth_rxdesc) * RX_RING_SIZE;
  637. mdp->rx_ring = dma_alloc_coherent(NULL, rx_ringsize, &mdp->rx_desc_dma,
  638. GFP_KERNEL);
  639. if (!mdp->rx_ring) {
  640. dev_err(&ndev->dev, "Cannot allocate Rx Ring (size %d bytes)\n",
  641. rx_ringsize);
  642. ret = -ENOMEM;
  643. goto desc_ring_free;
  644. }
  645. mdp->dirty_rx = 0;
  646. /* Allocate all Tx descriptors. */
  647. tx_ringsize = sizeof(struct sh_eth_txdesc) * TX_RING_SIZE;
  648. mdp->tx_ring = dma_alloc_coherent(NULL, tx_ringsize, &mdp->tx_desc_dma,
  649. GFP_KERNEL);
  650. if (!mdp->tx_ring) {
  651. dev_err(&ndev->dev, "Cannot allocate Tx Ring (size %d bytes)\n",
  652. tx_ringsize);
  653. ret = -ENOMEM;
  654. goto desc_ring_free;
  655. }
  656. return ret;
  657. desc_ring_free:
  658. /* free DMA buffer */
  659. dma_free_coherent(NULL, rx_ringsize, mdp->rx_ring, mdp->rx_desc_dma);
  660. skb_ring_free:
  661. /* Free Rx and Tx skb ring buffer */
  662. sh_eth_ring_free(ndev);
  663. return ret;
  664. }
  665. static int sh_eth_dev_init(struct net_device *ndev)
  666. {
  667. int ret = 0;
  668. struct sh_eth_private *mdp = netdev_priv(ndev);
  669. u_int32_t rx_int_var, tx_int_var;
  670. u32 val;
  671. /* Soft Reset */
  672. sh_eth_reset(ndev);
  673. /* Descriptor format */
  674. sh_eth_ring_format(ndev);
  675. if (mdp->cd->rpadir)
  676. sh_eth_write(ndev, mdp->cd->rpadir_value, RPADIR);
  677. /* all sh_eth int mask */
  678. sh_eth_write(ndev, 0, EESIPR);
  679. #if defined(__LITTLE_ENDIAN__)
  680. if (mdp->cd->hw_swap)
  681. sh_eth_write(ndev, EDMR_EL, EDMR);
  682. else
  683. #endif
  684. sh_eth_write(ndev, 0, EDMR);
  685. /* FIFO size set */
  686. sh_eth_write(ndev, mdp->cd->fdr_value, FDR);
  687. sh_eth_write(ndev, 0, TFTR);
  688. /* Frame recv control */
  689. sh_eth_write(ndev, mdp->cd->rmcr_value, RMCR);
  690. rx_int_var = mdp->rx_int_var = DESC_I_RINT8 | DESC_I_RINT5;
  691. tx_int_var = mdp->tx_int_var = DESC_I_TINT2;
  692. sh_eth_write(ndev, rx_int_var | tx_int_var, TRSCER);
  693. if (mdp->cd->bculr)
  694. sh_eth_write(ndev, 0x800, BCULR); /* Burst sycle set */
  695. sh_eth_write(ndev, mdp->cd->fcftr_value, FCFTR);
  696. if (!mdp->cd->no_trimd)
  697. sh_eth_write(ndev, 0, TRIMD);
  698. /* Recv frame limit set register */
  699. sh_eth_write(ndev, RFLR_VALUE, RFLR);
  700. sh_eth_write(ndev, sh_eth_read(ndev, EESR), EESR);
  701. sh_eth_write(ndev, mdp->cd->eesipr_value, EESIPR);
  702. /* PAUSE Prohibition */
  703. val = (sh_eth_read(ndev, ECMR) & ECMR_DM) |
  704. ECMR_ZPF | (mdp->duplex ? ECMR_DM : 0) | ECMR_TE | ECMR_RE;
  705. sh_eth_write(ndev, val, ECMR);
  706. if (mdp->cd->set_rate)
  707. mdp->cd->set_rate(ndev);
  708. /* E-MAC Status Register clear */
  709. sh_eth_write(ndev, mdp->cd->ecsr_value, ECSR);
  710. /* E-MAC Interrupt Enable register */
  711. sh_eth_write(ndev, mdp->cd->ecsipr_value, ECSIPR);
  712. /* Set MAC address */
  713. update_mac_address(ndev);
  714. /* mask reset */
  715. if (mdp->cd->apr)
  716. sh_eth_write(ndev, APR_AP, APR);
  717. if (mdp->cd->mpr)
  718. sh_eth_write(ndev, MPR_MP, MPR);
  719. if (mdp->cd->tpauser)
  720. sh_eth_write(ndev, TPAUSER_UNLIMITED, TPAUSER);
  721. /* Setting the Rx mode will start the Rx process. */
  722. sh_eth_write(ndev, EDRRR_R, EDRRR);
  723. netif_start_queue(ndev);
  724. return ret;
  725. }
  726. /* free Tx skb function */
  727. static int sh_eth_txfree(struct net_device *ndev)
  728. {
  729. struct sh_eth_private *mdp = netdev_priv(ndev);
  730. struct sh_eth_txdesc *txdesc;
  731. int freeNum = 0;
  732. int entry = 0;
  733. for (; mdp->cur_tx - mdp->dirty_tx > 0; mdp->dirty_tx++) {
  734. entry = mdp->dirty_tx % TX_RING_SIZE;
  735. txdesc = &mdp->tx_ring[entry];
  736. if (txdesc->status & cpu_to_edmac(mdp, TD_TACT))
  737. break;
  738. /* Free the original skb. */
  739. if (mdp->tx_skbuff[entry]) {
  740. dma_unmap_single(&ndev->dev, txdesc->addr,
  741. txdesc->buffer_length, DMA_TO_DEVICE);
  742. dev_kfree_skb_irq(mdp->tx_skbuff[entry]);
  743. mdp->tx_skbuff[entry] = NULL;
  744. freeNum++;
  745. }
  746. txdesc->status = cpu_to_edmac(mdp, TD_TFP);
  747. if (entry >= TX_RING_SIZE - 1)
  748. txdesc->status |= cpu_to_edmac(mdp, TD_TDLE);
  749. mdp->stats.tx_packets++;
  750. mdp->stats.tx_bytes += txdesc->buffer_length;
  751. }
  752. return freeNum;
  753. }
  754. /* Packet receive function */
  755. static int sh_eth_rx(struct net_device *ndev)
  756. {
  757. struct sh_eth_private *mdp = netdev_priv(ndev);
  758. struct sh_eth_rxdesc *rxdesc;
  759. int entry = mdp->cur_rx % RX_RING_SIZE;
  760. int boguscnt = (mdp->dirty_rx + RX_RING_SIZE) - mdp->cur_rx;
  761. struct sk_buff *skb;
  762. u16 pkt_len = 0;
  763. u32 desc_status;
  764. rxdesc = &mdp->rx_ring[entry];
  765. while (!(rxdesc->status & cpu_to_edmac(mdp, RD_RACT))) {
  766. desc_status = edmac_to_cpu(mdp, rxdesc->status);
  767. pkt_len = rxdesc->frame_length;
  768. if (--boguscnt < 0)
  769. break;
  770. if (!(desc_status & RDFEND))
  771. mdp->stats.rx_length_errors++;
  772. if (desc_status & (RD_RFS1 | RD_RFS2 | RD_RFS3 | RD_RFS4 |
  773. RD_RFS5 | RD_RFS6 | RD_RFS10)) {
  774. mdp->stats.rx_errors++;
  775. if (desc_status & RD_RFS1)
  776. mdp->stats.rx_crc_errors++;
  777. if (desc_status & RD_RFS2)
  778. mdp->stats.rx_frame_errors++;
  779. if (desc_status & RD_RFS3)
  780. mdp->stats.rx_length_errors++;
  781. if (desc_status & RD_RFS4)
  782. mdp->stats.rx_length_errors++;
  783. if (desc_status & RD_RFS6)
  784. mdp->stats.rx_missed_errors++;
  785. if (desc_status & RD_RFS10)
  786. mdp->stats.rx_over_errors++;
  787. } else {
  788. if (!mdp->cd->hw_swap)
  789. sh_eth_soft_swap(
  790. phys_to_virt(ALIGN(rxdesc->addr, 4)),
  791. pkt_len + 2);
  792. skb = mdp->rx_skbuff[entry];
  793. mdp->rx_skbuff[entry] = NULL;
  794. if (mdp->cd->rpadir)
  795. skb_reserve(skb, NET_IP_ALIGN);
  796. skb_put(skb, pkt_len);
  797. skb->protocol = eth_type_trans(skb, ndev);
  798. netif_rx(skb);
  799. mdp->stats.rx_packets++;
  800. mdp->stats.rx_bytes += pkt_len;
  801. }
  802. rxdesc->status |= cpu_to_edmac(mdp, RD_RACT);
  803. entry = (++mdp->cur_rx) % RX_RING_SIZE;
  804. rxdesc = &mdp->rx_ring[entry];
  805. }
  806. /* Refill the Rx ring buffers. */
  807. for (; mdp->cur_rx - mdp->dirty_rx > 0; mdp->dirty_rx++) {
  808. entry = mdp->dirty_rx % RX_RING_SIZE;
  809. rxdesc = &mdp->rx_ring[entry];
  810. /* The size of the buffer is 16 byte boundary. */
  811. rxdesc->buffer_length = ALIGN(mdp->rx_buf_sz, 16);
  812. if (mdp->rx_skbuff[entry] == NULL) {
  813. skb = dev_alloc_skb(mdp->rx_buf_sz);
  814. mdp->rx_skbuff[entry] = skb;
  815. if (skb == NULL)
  816. break; /* Better luck next round. */
  817. dma_map_single(&ndev->dev, skb->tail, mdp->rx_buf_sz,
  818. DMA_FROM_DEVICE);
  819. skb->dev = ndev;
  820. sh_eth_set_receive_align(skb);
  821. skb_checksum_none_assert(skb);
  822. rxdesc->addr = virt_to_phys(PTR_ALIGN(skb->data, 4));
  823. }
  824. if (entry >= RX_RING_SIZE - 1)
  825. rxdesc->status |=
  826. cpu_to_edmac(mdp, RD_RACT | RD_RFP | RD_RDEL);
  827. else
  828. rxdesc->status |=
  829. cpu_to_edmac(mdp, RD_RACT | RD_RFP);
  830. }
  831. /* Restart Rx engine if stopped. */
  832. /* If we don't need to check status, don't. -KDU */
  833. if (!(sh_eth_read(ndev, EDRRR) & EDRRR_R))
  834. sh_eth_write(ndev, EDRRR_R, EDRRR);
  835. return 0;
  836. }
  837. static void sh_eth_rcv_snd_disable(struct net_device *ndev)
  838. {
  839. /* disable tx and rx */
  840. sh_eth_write(ndev, sh_eth_read(ndev, ECMR) &
  841. ~(ECMR_RE | ECMR_TE), ECMR);
  842. }
  843. static void sh_eth_rcv_snd_enable(struct net_device *ndev)
  844. {
  845. /* enable tx and rx */
  846. sh_eth_write(ndev, sh_eth_read(ndev, ECMR) |
  847. (ECMR_RE | ECMR_TE), ECMR);
  848. }
  849. /* error control function */
  850. static void sh_eth_error(struct net_device *ndev, int intr_status)
  851. {
  852. struct sh_eth_private *mdp = netdev_priv(ndev);
  853. u32 felic_stat;
  854. u32 link_stat;
  855. u32 mask;
  856. if (intr_status & EESR_ECI) {
  857. felic_stat = sh_eth_read(ndev, ECSR);
  858. sh_eth_write(ndev, felic_stat, ECSR); /* clear int */
  859. if (felic_stat & ECSR_ICD)
  860. mdp->stats.tx_carrier_errors++;
  861. if (felic_stat & ECSR_LCHNG) {
  862. /* Link Changed */
  863. if (mdp->cd->no_psr || mdp->no_ether_link) {
  864. if (mdp->link == PHY_DOWN)
  865. link_stat = 0;
  866. else
  867. link_stat = PHY_ST_LINK;
  868. } else {
  869. link_stat = (sh_eth_read(ndev, PSR));
  870. if (mdp->ether_link_active_low)
  871. link_stat = ~link_stat;
  872. }
  873. if (!(link_stat & PHY_ST_LINK))
  874. sh_eth_rcv_snd_disable(ndev);
  875. else {
  876. /* Link Up */
  877. sh_eth_write(ndev, sh_eth_read(ndev, EESIPR) &
  878. ~DMAC_M_ECI, EESIPR);
  879. /*clear int */
  880. sh_eth_write(ndev, sh_eth_read(ndev, ECSR),
  881. ECSR);
  882. sh_eth_write(ndev, sh_eth_read(ndev, EESIPR) |
  883. DMAC_M_ECI, EESIPR);
  884. /* enable tx and rx */
  885. sh_eth_rcv_snd_enable(ndev);
  886. }
  887. }
  888. }
  889. if (intr_status & EESR_TWB) {
  890. /* Write buck end. unused write back interrupt */
  891. if (intr_status & EESR_TABT) /* Transmit Abort int */
  892. mdp->stats.tx_aborted_errors++;
  893. if (netif_msg_tx_err(mdp))
  894. dev_err(&ndev->dev, "Transmit Abort\n");
  895. }
  896. if (intr_status & EESR_RABT) {
  897. /* Receive Abort int */
  898. if (intr_status & EESR_RFRMER) {
  899. /* Receive Frame Overflow int */
  900. mdp->stats.rx_frame_errors++;
  901. if (netif_msg_rx_err(mdp))
  902. dev_err(&ndev->dev, "Receive Abort\n");
  903. }
  904. }
  905. if (intr_status & EESR_TDE) {
  906. /* Transmit Descriptor Empty int */
  907. mdp->stats.tx_fifo_errors++;
  908. if (netif_msg_tx_err(mdp))
  909. dev_err(&ndev->dev, "Transmit Descriptor Empty\n");
  910. }
  911. if (intr_status & EESR_TFE) {
  912. /* FIFO under flow */
  913. mdp->stats.tx_fifo_errors++;
  914. if (netif_msg_tx_err(mdp))
  915. dev_err(&ndev->dev, "Transmit FIFO Under flow\n");
  916. }
  917. if (intr_status & EESR_RDE) {
  918. /* Receive Descriptor Empty int */
  919. mdp->stats.rx_over_errors++;
  920. if (sh_eth_read(ndev, EDRRR) ^ EDRRR_R)
  921. sh_eth_write(ndev, EDRRR_R, EDRRR);
  922. if (netif_msg_rx_err(mdp))
  923. dev_err(&ndev->dev, "Receive Descriptor Empty\n");
  924. }
  925. if (intr_status & EESR_RFE) {
  926. /* Receive FIFO Overflow int */
  927. mdp->stats.rx_fifo_errors++;
  928. if (netif_msg_rx_err(mdp))
  929. dev_err(&ndev->dev, "Receive FIFO Overflow\n");
  930. }
  931. if (!mdp->cd->no_ade && (intr_status & EESR_ADE)) {
  932. /* Address Error */
  933. mdp->stats.tx_fifo_errors++;
  934. if (netif_msg_tx_err(mdp))
  935. dev_err(&ndev->dev, "Address Error\n");
  936. }
  937. mask = EESR_TWB | EESR_TABT | EESR_ADE | EESR_TDE | EESR_TFE;
  938. if (mdp->cd->no_ade)
  939. mask &= ~EESR_ADE;
  940. if (intr_status & mask) {
  941. /* Tx error */
  942. u32 edtrr = sh_eth_read(ndev, EDTRR);
  943. /* dmesg */
  944. dev_err(&ndev->dev, "TX error. status=%8.8x cur_tx=%8.8x ",
  945. intr_status, mdp->cur_tx);
  946. dev_err(&ndev->dev, "dirty_tx=%8.8x state=%8.8x EDTRR=%8.8x.\n",
  947. mdp->dirty_tx, (u32) ndev->state, edtrr);
  948. /* dirty buffer free */
  949. sh_eth_txfree(ndev);
  950. /* SH7712 BUG */
  951. if (edtrr ^ sh_eth_get_edtrr_trns(mdp)) {
  952. /* tx dma start */
  953. sh_eth_write(ndev, sh_eth_get_edtrr_trns(mdp), EDTRR);
  954. }
  955. /* wakeup */
  956. netif_wake_queue(ndev);
  957. }
  958. }
  959. static irqreturn_t sh_eth_interrupt(int irq, void *netdev)
  960. {
  961. struct net_device *ndev = netdev;
  962. struct sh_eth_private *mdp = netdev_priv(ndev);
  963. struct sh_eth_cpu_data *cd = mdp->cd;
  964. irqreturn_t ret = IRQ_NONE;
  965. u32 intr_status = 0;
  966. spin_lock(&mdp->lock);
  967. /* Get interrpt stat */
  968. intr_status = sh_eth_read(ndev, EESR);
  969. /* Clear interrupt */
  970. if (intr_status & (EESR_FRC | EESR_RMAF | EESR_RRF |
  971. EESR_RTLF | EESR_RTSF | EESR_PRE | EESR_CERF |
  972. cd->tx_check | cd->eesr_err_check)) {
  973. sh_eth_write(ndev, intr_status, EESR);
  974. ret = IRQ_HANDLED;
  975. } else
  976. goto other_irq;
  977. if (intr_status & (EESR_FRC | /* Frame recv*/
  978. EESR_RMAF | /* Multi cast address recv*/
  979. EESR_RRF | /* Bit frame recv */
  980. EESR_RTLF | /* Long frame recv*/
  981. EESR_RTSF | /* short frame recv */
  982. EESR_PRE | /* PHY-LSI recv error */
  983. EESR_CERF)){ /* recv frame CRC error */
  984. sh_eth_rx(ndev);
  985. }
  986. /* Tx Check */
  987. if (intr_status & cd->tx_check) {
  988. sh_eth_txfree(ndev);
  989. netif_wake_queue(ndev);
  990. }
  991. if (intr_status & cd->eesr_err_check)
  992. sh_eth_error(ndev, intr_status);
  993. other_irq:
  994. spin_unlock(&mdp->lock);
  995. return ret;
  996. }
  997. static void sh_eth_timer(unsigned long data)
  998. {
  999. struct net_device *ndev = (struct net_device *)data;
  1000. struct sh_eth_private *mdp = netdev_priv(ndev);
  1001. mod_timer(&mdp->timer, jiffies + (10 * HZ));
  1002. }
  1003. /* PHY state control function */
  1004. static void sh_eth_adjust_link(struct net_device *ndev)
  1005. {
  1006. struct sh_eth_private *mdp = netdev_priv(ndev);
  1007. struct phy_device *phydev = mdp->phydev;
  1008. int new_state = 0;
  1009. if (phydev->link != PHY_DOWN) {
  1010. if (phydev->duplex != mdp->duplex) {
  1011. new_state = 1;
  1012. mdp->duplex = phydev->duplex;
  1013. if (mdp->cd->set_duplex)
  1014. mdp->cd->set_duplex(ndev);
  1015. }
  1016. if (phydev->speed != mdp->speed) {
  1017. new_state = 1;
  1018. mdp->speed = phydev->speed;
  1019. if (mdp->cd->set_rate)
  1020. mdp->cd->set_rate(ndev);
  1021. }
  1022. if (mdp->link == PHY_DOWN) {
  1023. sh_eth_write(ndev,
  1024. (sh_eth_read(ndev, ECMR) & ~ECMR_TXF), ECMR);
  1025. new_state = 1;
  1026. mdp->link = phydev->link;
  1027. }
  1028. } else if (mdp->link) {
  1029. new_state = 1;
  1030. mdp->link = PHY_DOWN;
  1031. mdp->speed = 0;
  1032. mdp->duplex = -1;
  1033. }
  1034. if (new_state && netif_msg_link(mdp))
  1035. phy_print_status(phydev);
  1036. }
  1037. /* PHY init function */
  1038. static int sh_eth_phy_init(struct net_device *ndev)
  1039. {
  1040. struct sh_eth_private *mdp = netdev_priv(ndev);
  1041. char phy_id[MII_BUS_ID_SIZE + 3];
  1042. struct phy_device *phydev = NULL;
  1043. snprintf(phy_id, sizeof(phy_id), PHY_ID_FMT,
  1044. mdp->mii_bus->id , mdp->phy_id);
  1045. mdp->link = PHY_DOWN;
  1046. mdp->speed = 0;
  1047. mdp->duplex = -1;
  1048. /* Try connect to PHY */
  1049. phydev = phy_connect(ndev, phy_id, sh_eth_adjust_link,
  1050. 0, mdp->phy_interface);
  1051. if (IS_ERR(phydev)) {
  1052. dev_err(&ndev->dev, "phy_connect failed\n");
  1053. return PTR_ERR(phydev);
  1054. }
  1055. dev_info(&ndev->dev, "attached phy %i to driver %s\n",
  1056. phydev->addr, phydev->drv->name);
  1057. mdp->phydev = phydev;
  1058. return 0;
  1059. }
  1060. /* PHY control start function */
  1061. static int sh_eth_phy_start(struct net_device *ndev)
  1062. {
  1063. struct sh_eth_private *mdp = netdev_priv(ndev);
  1064. int ret;
  1065. ret = sh_eth_phy_init(ndev);
  1066. if (ret)
  1067. return ret;
  1068. /* reset phy - this also wakes it from PDOWN */
  1069. phy_write(mdp->phydev, MII_BMCR, BMCR_RESET);
  1070. phy_start(mdp->phydev);
  1071. return 0;
  1072. }
  1073. static int sh_eth_get_settings(struct net_device *ndev,
  1074. struct ethtool_cmd *ecmd)
  1075. {
  1076. struct sh_eth_private *mdp = netdev_priv(ndev);
  1077. unsigned long flags;
  1078. int ret;
  1079. spin_lock_irqsave(&mdp->lock, flags);
  1080. ret = phy_ethtool_gset(mdp->phydev, ecmd);
  1081. spin_unlock_irqrestore(&mdp->lock, flags);
  1082. return ret;
  1083. }
  1084. static int sh_eth_set_settings(struct net_device *ndev,
  1085. struct ethtool_cmd *ecmd)
  1086. {
  1087. struct sh_eth_private *mdp = netdev_priv(ndev);
  1088. unsigned long flags;
  1089. int ret;
  1090. spin_lock_irqsave(&mdp->lock, flags);
  1091. /* disable tx and rx */
  1092. sh_eth_rcv_snd_disable(ndev);
  1093. ret = phy_ethtool_sset(mdp->phydev, ecmd);
  1094. if (ret)
  1095. goto error_exit;
  1096. if (ecmd->duplex == DUPLEX_FULL)
  1097. mdp->duplex = 1;
  1098. else
  1099. mdp->duplex = 0;
  1100. if (mdp->cd->set_duplex)
  1101. mdp->cd->set_duplex(ndev);
  1102. error_exit:
  1103. mdelay(1);
  1104. /* enable tx and rx */
  1105. sh_eth_rcv_snd_enable(ndev);
  1106. spin_unlock_irqrestore(&mdp->lock, flags);
  1107. return ret;
  1108. }
  1109. static int sh_eth_nway_reset(struct net_device *ndev)
  1110. {
  1111. struct sh_eth_private *mdp = netdev_priv(ndev);
  1112. unsigned long flags;
  1113. int ret;
  1114. spin_lock_irqsave(&mdp->lock, flags);
  1115. ret = phy_start_aneg(mdp->phydev);
  1116. spin_unlock_irqrestore(&mdp->lock, flags);
  1117. return ret;
  1118. }
  1119. static u32 sh_eth_get_msglevel(struct net_device *ndev)
  1120. {
  1121. struct sh_eth_private *mdp = netdev_priv(ndev);
  1122. return mdp->msg_enable;
  1123. }
  1124. static void sh_eth_set_msglevel(struct net_device *ndev, u32 value)
  1125. {
  1126. struct sh_eth_private *mdp = netdev_priv(ndev);
  1127. mdp->msg_enable = value;
  1128. }
  1129. static const char sh_eth_gstrings_stats[][ETH_GSTRING_LEN] = {
  1130. "rx_current", "tx_current",
  1131. "rx_dirty", "tx_dirty",
  1132. };
  1133. #define SH_ETH_STATS_LEN ARRAY_SIZE(sh_eth_gstrings_stats)
  1134. static int sh_eth_get_sset_count(struct net_device *netdev, int sset)
  1135. {
  1136. switch (sset) {
  1137. case ETH_SS_STATS:
  1138. return SH_ETH_STATS_LEN;
  1139. default:
  1140. return -EOPNOTSUPP;
  1141. }
  1142. }
  1143. static void sh_eth_get_ethtool_stats(struct net_device *ndev,
  1144. struct ethtool_stats *stats, u64 *data)
  1145. {
  1146. struct sh_eth_private *mdp = netdev_priv(ndev);
  1147. int i = 0;
  1148. /* device-specific stats */
  1149. data[i++] = mdp->cur_rx;
  1150. data[i++] = mdp->cur_tx;
  1151. data[i++] = mdp->dirty_rx;
  1152. data[i++] = mdp->dirty_tx;
  1153. }
  1154. static void sh_eth_get_strings(struct net_device *ndev, u32 stringset, u8 *data)
  1155. {
  1156. switch (stringset) {
  1157. case ETH_SS_STATS:
  1158. memcpy(data, *sh_eth_gstrings_stats,
  1159. sizeof(sh_eth_gstrings_stats));
  1160. break;
  1161. }
  1162. }
  1163. static struct ethtool_ops sh_eth_ethtool_ops = {
  1164. .get_settings = sh_eth_get_settings,
  1165. .set_settings = sh_eth_set_settings,
  1166. .nway_reset = sh_eth_nway_reset,
  1167. .get_msglevel = sh_eth_get_msglevel,
  1168. .set_msglevel = sh_eth_set_msglevel,
  1169. .get_link = ethtool_op_get_link,
  1170. .get_strings = sh_eth_get_strings,
  1171. .get_ethtool_stats = sh_eth_get_ethtool_stats,
  1172. .get_sset_count = sh_eth_get_sset_count,
  1173. };
  1174. /* network device open function */
  1175. static int sh_eth_open(struct net_device *ndev)
  1176. {
  1177. int ret = 0;
  1178. struct sh_eth_private *mdp = netdev_priv(ndev);
  1179. pm_runtime_get_sync(&mdp->pdev->dev);
  1180. ret = request_irq(ndev->irq, sh_eth_interrupt,
  1181. #if defined(CONFIG_CPU_SUBTYPE_SH7763) || \
  1182. defined(CONFIG_CPU_SUBTYPE_SH7764) || \
  1183. defined(CONFIG_CPU_SUBTYPE_SH7757)
  1184. IRQF_SHARED,
  1185. #else
  1186. 0,
  1187. #endif
  1188. ndev->name, ndev);
  1189. if (ret) {
  1190. dev_err(&ndev->dev, "Can not assign IRQ number\n");
  1191. return ret;
  1192. }
  1193. /* Descriptor set */
  1194. ret = sh_eth_ring_init(ndev);
  1195. if (ret)
  1196. goto out_free_irq;
  1197. /* device init */
  1198. ret = sh_eth_dev_init(ndev);
  1199. if (ret)
  1200. goto out_free_irq;
  1201. /* PHY control start*/
  1202. ret = sh_eth_phy_start(ndev);
  1203. if (ret)
  1204. goto out_free_irq;
  1205. /* Set the timer to check for link beat. */
  1206. init_timer(&mdp->timer);
  1207. mdp->timer.expires = (jiffies + (24 * HZ)) / 10;/* 2.4 sec. */
  1208. setup_timer(&mdp->timer, sh_eth_timer, (unsigned long)ndev);
  1209. return ret;
  1210. out_free_irq:
  1211. free_irq(ndev->irq, ndev);
  1212. pm_runtime_put_sync(&mdp->pdev->dev);
  1213. return ret;
  1214. }
  1215. /* Timeout function */
  1216. static void sh_eth_tx_timeout(struct net_device *ndev)
  1217. {
  1218. struct sh_eth_private *mdp = netdev_priv(ndev);
  1219. struct sh_eth_rxdesc *rxdesc;
  1220. int i;
  1221. netif_stop_queue(ndev);
  1222. if (netif_msg_timer(mdp))
  1223. dev_err(&ndev->dev, "%s: transmit timed out, status %8.8x,"
  1224. " resetting...\n", ndev->name, (int)sh_eth_read(ndev, EESR));
  1225. /* tx_errors count up */
  1226. mdp->stats.tx_errors++;
  1227. /* timer off */
  1228. del_timer_sync(&mdp->timer);
  1229. /* Free all the skbuffs in the Rx queue. */
  1230. for (i = 0; i < RX_RING_SIZE; i++) {
  1231. rxdesc = &mdp->rx_ring[i];
  1232. rxdesc->status = 0;
  1233. rxdesc->addr = 0xBADF00D0;
  1234. if (mdp->rx_skbuff[i])
  1235. dev_kfree_skb(mdp->rx_skbuff[i]);
  1236. mdp->rx_skbuff[i] = NULL;
  1237. }
  1238. for (i = 0; i < TX_RING_SIZE; i++) {
  1239. if (mdp->tx_skbuff[i])
  1240. dev_kfree_skb(mdp->tx_skbuff[i]);
  1241. mdp->tx_skbuff[i] = NULL;
  1242. }
  1243. /* device init */
  1244. sh_eth_dev_init(ndev);
  1245. /* timer on */
  1246. mdp->timer.expires = (jiffies + (24 * HZ)) / 10;/* 2.4 sec. */
  1247. add_timer(&mdp->timer);
  1248. }
  1249. /* Packet transmit function */
  1250. static int sh_eth_start_xmit(struct sk_buff *skb, struct net_device *ndev)
  1251. {
  1252. struct sh_eth_private *mdp = netdev_priv(ndev);
  1253. struct sh_eth_txdesc *txdesc;
  1254. u32 entry;
  1255. unsigned long flags;
  1256. spin_lock_irqsave(&mdp->lock, flags);
  1257. if ((mdp->cur_tx - mdp->dirty_tx) >= (TX_RING_SIZE - 4)) {
  1258. if (!sh_eth_txfree(ndev)) {
  1259. if (netif_msg_tx_queued(mdp))
  1260. dev_warn(&ndev->dev, "TxFD exhausted.\n");
  1261. netif_stop_queue(ndev);
  1262. spin_unlock_irqrestore(&mdp->lock, flags);
  1263. return NETDEV_TX_BUSY;
  1264. }
  1265. }
  1266. spin_unlock_irqrestore(&mdp->lock, flags);
  1267. entry = mdp->cur_tx % TX_RING_SIZE;
  1268. mdp->tx_skbuff[entry] = skb;
  1269. txdesc = &mdp->tx_ring[entry];
  1270. /* soft swap. */
  1271. if (!mdp->cd->hw_swap)
  1272. sh_eth_soft_swap(phys_to_virt(ALIGN(txdesc->addr, 4)),
  1273. skb->len + 2);
  1274. txdesc->addr = dma_map_single(&ndev->dev, skb->data, skb->len,
  1275. DMA_TO_DEVICE);
  1276. if (skb->len < ETHERSMALL)
  1277. txdesc->buffer_length = ETHERSMALL;
  1278. else
  1279. txdesc->buffer_length = skb->len;
  1280. if (entry >= TX_RING_SIZE - 1)
  1281. txdesc->status |= cpu_to_edmac(mdp, TD_TACT | TD_TDLE);
  1282. else
  1283. txdesc->status |= cpu_to_edmac(mdp, TD_TACT);
  1284. mdp->cur_tx++;
  1285. if (!(sh_eth_read(ndev, EDTRR) & sh_eth_get_edtrr_trns(mdp)))
  1286. sh_eth_write(ndev, sh_eth_get_edtrr_trns(mdp), EDTRR);
  1287. return NETDEV_TX_OK;
  1288. }
  1289. /* device close function */
  1290. static int sh_eth_close(struct net_device *ndev)
  1291. {
  1292. struct sh_eth_private *mdp = netdev_priv(ndev);
  1293. int ringsize;
  1294. netif_stop_queue(ndev);
  1295. /* Disable interrupts by clearing the interrupt mask. */
  1296. sh_eth_write(ndev, 0x0000, EESIPR);
  1297. /* Stop the chip's Tx and Rx processes. */
  1298. sh_eth_write(ndev, 0, EDTRR);
  1299. sh_eth_write(ndev, 0, EDRRR);
  1300. /* PHY Disconnect */
  1301. if (mdp->phydev) {
  1302. phy_stop(mdp->phydev);
  1303. phy_disconnect(mdp->phydev);
  1304. }
  1305. free_irq(ndev->irq, ndev);
  1306. del_timer_sync(&mdp->timer);
  1307. /* Free all the skbuffs in the Rx queue. */
  1308. sh_eth_ring_free(ndev);
  1309. /* free DMA buffer */
  1310. ringsize = sizeof(struct sh_eth_rxdesc) * RX_RING_SIZE;
  1311. dma_free_coherent(NULL, ringsize, mdp->rx_ring, mdp->rx_desc_dma);
  1312. /* free DMA buffer */
  1313. ringsize = sizeof(struct sh_eth_txdesc) * TX_RING_SIZE;
  1314. dma_free_coherent(NULL, ringsize, mdp->tx_ring, mdp->tx_desc_dma);
  1315. pm_runtime_put_sync(&mdp->pdev->dev);
  1316. return 0;
  1317. }
  1318. static struct net_device_stats *sh_eth_get_stats(struct net_device *ndev)
  1319. {
  1320. struct sh_eth_private *mdp = netdev_priv(ndev);
  1321. pm_runtime_get_sync(&mdp->pdev->dev);
  1322. mdp->stats.tx_dropped += sh_eth_read(ndev, TROCR);
  1323. sh_eth_write(ndev, 0, TROCR); /* (write clear) */
  1324. mdp->stats.collisions += sh_eth_read(ndev, CDCR);
  1325. sh_eth_write(ndev, 0, CDCR); /* (write clear) */
  1326. mdp->stats.tx_carrier_errors += sh_eth_read(ndev, LCCR);
  1327. sh_eth_write(ndev, 0, LCCR); /* (write clear) */
  1328. if (sh_eth_is_gether(mdp)) {
  1329. mdp->stats.tx_carrier_errors += sh_eth_read(ndev, CERCR);
  1330. sh_eth_write(ndev, 0, CERCR); /* (write clear) */
  1331. mdp->stats.tx_carrier_errors += sh_eth_read(ndev, CEECR);
  1332. sh_eth_write(ndev, 0, CEECR); /* (write clear) */
  1333. } else {
  1334. mdp->stats.tx_carrier_errors += sh_eth_read(ndev, CNDCR);
  1335. sh_eth_write(ndev, 0, CNDCR); /* (write clear) */
  1336. }
  1337. pm_runtime_put_sync(&mdp->pdev->dev);
  1338. return &mdp->stats;
  1339. }
  1340. /* ioctl to device funciotn*/
  1341. static int sh_eth_do_ioctl(struct net_device *ndev, struct ifreq *rq,
  1342. int cmd)
  1343. {
  1344. struct sh_eth_private *mdp = netdev_priv(ndev);
  1345. struct phy_device *phydev = mdp->phydev;
  1346. if (!netif_running(ndev))
  1347. return -EINVAL;
  1348. if (!phydev)
  1349. return -ENODEV;
  1350. return phy_mii_ioctl(phydev, rq, cmd);
  1351. }
  1352. #if defined(SH_ETH_HAS_TSU)
  1353. /* Multicast reception directions set */
  1354. static void sh_eth_set_multicast_list(struct net_device *ndev)
  1355. {
  1356. if (ndev->flags & IFF_PROMISC) {
  1357. /* Set promiscuous. */
  1358. sh_eth_write(ndev, (sh_eth_read(ndev, ECMR) & ~ECMR_MCT) |
  1359. ECMR_PRM, ECMR);
  1360. } else {
  1361. /* Normal, unicast/broadcast-only mode. */
  1362. sh_eth_write(ndev, (sh_eth_read(ndev, ECMR) & ~ECMR_PRM) |
  1363. ECMR_MCT, ECMR);
  1364. }
  1365. }
  1366. #endif /* SH_ETH_HAS_TSU */
  1367. /* SuperH's TSU register init function */
  1368. static void sh_eth_tsu_init(struct sh_eth_private *mdp)
  1369. {
  1370. sh_eth_tsu_write(mdp, 0, TSU_FWEN0); /* Disable forward(0->1) */
  1371. sh_eth_tsu_write(mdp, 0, TSU_FWEN1); /* Disable forward(1->0) */
  1372. sh_eth_tsu_write(mdp, 0, TSU_FCM); /* forward fifo 3k-3k */
  1373. sh_eth_tsu_write(mdp, 0xc, TSU_BSYSL0);
  1374. sh_eth_tsu_write(mdp, 0xc, TSU_BSYSL1);
  1375. sh_eth_tsu_write(mdp, 0, TSU_PRISL0);
  1376. sh_eth_tsu_write(mdp, 0, TSU_PRISL1);
  1377. sh_eth_tsu_write(mdp, 0, TSU_FWSL0);
  1378. sh_eth_tsu_write(mdp, 0, TSU_FWSL1);
  1379. sh_eth_tsu_write(mdp, TSU_FWSLC_POSTENU | TSU_FWSLC_POSTENL, TSU_FWSLC);
  1380. if (sh_eth_is_gether(mdp)) {
  1381. sh_eth_tsu_write(mdp, 0, TSU_QTAG0); /* Disable QTAG(0->1) */
  1382. sh_eth_tsu_write(mdp, 0, TSU_QTAG1); /* Disable QTAG(1->0) */
  1383. } else {
  1384. sh_eth_tsu_write(mdp, 0, TSU_QTAGM0); /* Disable QTAG(0->1) */
  1385. sh_eth_tsu_write(mdp, 0, TSU_QTAGM1); /* Disable QTAG(1->0) */
  1386. }
  1387. sh_eth_tsu_write(mdp, 0, TSU_FWSR); /* all interrupt status clear */
  1388. sh_eth_tsu_write(mdp, 0, TSU_FWINMK); /* Disable all interrupt */
  1389. sh_eth_tsu_write(mdp, 0, TSU_TEN); /* Disable all CAM entry */
  1390. sh_eth_tsu_write(mdp, 0, TSU_POST1); /* Disable CAM entry [ 0- 7] */
  1391. sh_eth_tsu_write(mdp, 0, TSU_POST2); /* Disable CAM entry [ 8-15] */
  1392. sh_eth_tsu_write(mdp, 0, TSU_POST3); /* Disable CAM entry [16-23] */
  1393. sh_eth_tsu_write(mdp, 0, TSU_POST4); /* Disable CAM entry [24-31] */
  1394. }
  1395. /* MDIO bus release function */
  1396. static int sh_mdio_release(struct net_device *ndev)
  1397. {
  1398. struct mii_bus *bus = dev_get_drvdata(&ndev->dev);
  1399. /* unregister mdio bus */
  1400. mdiobus_unregister(bus);
  1401. /* remove mdio bus info from net_device */
  1402. dev_set_drvdata(&ndev->dev, NULL);
  1403. /* free interrupts memory */
  1404. kfree(bus->irq);
  1405. /* free bitbang info */
  1406. free_mdio_bitbang(bus);
  1407. return 0;
  1408. }
  1409. /* MDIO bus init function */
  1410. static int sh_mdio_init(struct net_device *ndev, int id,
  1411. struct sh_eth_plat_data *pd)
  1412. {
  1413. int ret, i;
  1414. struct bb_info *bitbang;
  1415. struct sh_eth_private *mdp = netdev_priv(ndev);
  1416. /* create bit control struct for PHY */
  1417. bitbang = kzalloc(sizeof(struct bb_info), GFP_KERNEL);
  1418. if (!bitbang) {
  1419. ret = -ENOMEM;
  1420. goto out;
  1421. }
  1422. /* bitbang init */
  1423. bitbang->addr = mdp->addr + mdp->reg_offset[PIR];
  1424. bitbang->set_gate = pd->set_mdio_gate;
  1425. bitbang->mdi_msk = 0x08;
  1426. bitbang->mdo_msk = 0x04;
  1427. bitbang->mmd_msk = 0x02;/* MMD */
  1428. bitbang->mdc_msk = 0x01;
  1429. bitbang->ctrl.ops = &bb_ops;
  1430. /* MII controller setting */
  1431. mdp->mii_bus = alloc_mdio_bitbang(&bitbang->ctrl);
  1432. if (!mdp->mii_bus) {
  1433. ret = -ENOMEM;
  1434. goto out_free_bitbang;
  1435. }
  1436. /* Hook up MII support for ethtool */
  1437. mdp->mii_bus->name = "sh_mii";
  1438. mdp->mii_bus->parent = &ndev->dev;
  1439. snprintf(mdp->mii_bus->id, MII_BUS_ID_SIZE, "%x", id);
  1440. /* PHY IRQ */
  1441. mdp->mii_bus->irq = kmalloc(sizeof(int)*PHY_MAX_ADDR, GFP_KERNEL);
  1442. if (!mdp->mii_bus->irq) {
  1443. ret = -ENOMEM;
  1444. goto out_free_bus;
  1445. }
  1446. for (i = 0; i < PHY_MAX_ADDR; i++)
  1447. mdp->mii_bus->irq[i] = PHY_POLL;
  1448. /* regist mdio bus */
  1449. ret = mdiobus_register(mdp->mii_bus);
  1450. if (ret)
  1451. goto out_free_irq;
  1452. dev_set_drvdata(&ndev->dev, mdp->mii_bus);
  1453. return 0;
  1454. out_free_irq:
  1455. kfree(mdp->mii_bus->irq);
  1456. out_free_bus:
  1457. free_mdio_bitbang(mdp->mii_bus);
  1458. out_free_bitbang:
  1459. kfree(bitbang);
  1460. out:
  1461. return ret;
  1462. }
  1463. static const u16 *sh_eth_get_register_offset(int register_type)
  1464. {
  1465. const u16 *reg_offset = NULL;
  1466. switch (register_type) {
  1467. case SH_ETH_REG_GIGABIT:
  1468. reg_offset = sh_eth_offset_gigabit;
  1469. break;
  1470. case SH_ETH_REG_FAST_SH4:
  1471. reg_offset = sh_eth_offset_fast_sh4;
  1472. break;
  1473. case SH_ETH_REG_FAST_SH3_SH2:
  1474. reg_offset = sh_eth_offset_fast_sh3_sh2;
  1475. break;
  1476. default:
  1477. printk(KERN_ERR "Unknown register type (%d)\n", register_type);
  1478. break;
  1479. }
  1480. return reg_offset;
  1481. }
  1482. static const struct net_device_ops sh_eth_netdev_ops = {
  1483. .ndo_open = sh_eth_open,
  1484. .ndo_stop = sh_eth_close,
  1485. .ndo_start_xmit = sh_eth_start_xmit,
  1486. .ndo_get_stats = sh_eth_get_stats,
  1487. #if defined(SH_ETH_HAS_TSU)
  1488. .ndo_set_rx_mode = sh_eth_set_multicast_list,
  1489. #endif
  1490. .ndo_tx_timeout = sh_eth_tx_timeout,
  1491. .ndo_do_ioctl = sh_eth_do_ioctl,
  1492. .ndo_validate_addr = eth_validate_addr,
  1493. .ndo_set_mac_address = eth_mac_addr,
  1494. .ndo_change_mtu = eth_change_mtu,
  1495. };
  1496. static int sh_eth_drv_probe(struct platform_device *pdev)
  1497. {
  1498. int ret, devno = 0;
  1499. struct resource *res;
  1500. struct net_device *ndev = NULL;
  1501. struct sh_eth_private *mdp = NULL;
  1502. struct sh_eth_plat_data *pd;
  1503. /* get base addr */
  1504. res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
  1505. if (unlikely(res == NULL)) {
  1506. dev_err(&pdev->dev, "invalid resource\n");
  1507. ret = -EINVAL;
  1508. goto out;
  1509. }
  1510. ndev = alloc_etherdev(sizeof(struct sh_eth_private));
  1511. if (!ndev) {
  1512. dev_err(&pdev->dev, "Could not allocate device.\n");
  1513. ret = -ENOMEM;
  1514. goto out;
  1515. }
  1516. /* The sh Ether-specific entries in the device structure. */
  1517. ndev->base_addr = res->start;
  1518. devno = pdev->id;
  1519. if (devno < 0)
  1520. devno = 0;
  1521. ndev->dma = -1;
  1522. ret = platform_get_irq(pdev, 0);
  1523. if (ret < 0) {
  1524. ret = -ENODEV;
  1525. goto out_release;
  1526. }
  1527. ndev->irq = ret;
  1528. SET_NETDEV_DEV(ndev, &pdev->dev);
  1529. /* Fill in the fields of the device structure with ethernet values. */
  1530. ether_setup(ndev);
  1531. mdp = netdev_priv(ndev);
  1532. mdp->addr = ioremap(res->start, resource_size(res));
  1533. if (mdp->addr == NULL) {
  1534. ret = -ENOMEM;
  1535. dev_err(&pdev->dev, "ioremap failed.\n");
  1536. goto out_release;
  1537. }
  1538. spin_lock_init(&mdp->lock);
  1539. mdp->pdev = pdev;
  1540. pm_runtime_enable(&pdev->dev);
  1541. pm_runtime_resume(&pdev->dev);
  1542. pd = (struct sh_eth_plat_data *)(pdev->dev.platform_data);
  1543. /* get PHY ID */
  1544. mdp->phy_id = pd->phy;
  1545. mdp->phy_interface = pd->phy_interface;
  1546. /* EDMAC endian */
  1547. mdp->edmac_endian = pd->edmac_endian;
  1548. mdp->no_ether_link = pd->no_ether_link;
  1549. mdp->ether_link_active_low = pd->ether_link_active_low;
  1550. mdp->reg_offset = sh_eth_get_register_offset(pd->register_type);
  1551. /* set cpu data */
  1552. #if defined(SH_ETH_HAS_BOTH_MODULES)
  1553. mdp->cd = sh_eth_get_cpu_data(mdp);
  1554. #else
  1555. mdp->cd = &sh_eth_my_cpu_data;
  1556. #endif
  1557. sh_eth_set_default_cpu_data(mdp->cd);
  1558. /* set function */
  1559. ndev->netdev_ops = &sh_eth_netdev_ops;
  1560. SET_ETHTOOL_OPS(ndev, &sh_eth_ethtool_ops);
  1561. ndev->watchdog_timeo = TX_TIMEOUT;
  1562. /* debug message level */
  1563. mdp->msg_enable = SH_ETH_DEF_MSG_ENABLE;
  1564. mdp->post_rx = POST_RX >> (devno << 1);
  1565. mdp->post_fw = POST_FW >> (devno << 1);
  1566. /* read and set MAC address */
  1567. read_mac_address(ndev, pd->mac_addr);
  1568. /* First device only init */
  1569. if (!devno) {
  1570. if (mdp->cd->tsu) {
  1571. struct resource *rtsu;
  1572. rtsu = platform_get_resource(pdev, IORESOURCE_MEM, 1);
  1573. if (!rtsu) {
  1574. dev_err(&pdev->dev, "Not found TSU resource\n");
  1575. goto out_release;
  1576. }
  1577. mdp->tsu_addr = ioremap(rtsu->start,
  1578. resource_size(rtsu));
  1579. }
  1580. if (mdp->cd->chip_reset)
  1581. mdp->cd->chip_reset(ndev);
  1582. if (mdp->cd->tsu) {
  1583. /* TSU init (Init only)*/
  1584. sh_eth_tsu_init(mdp);
  1585. }
  1586. }
  1587. /* network device register */
  1588. ret = register_netdev(ndev);
  1589. if (ret)
  1590. goto out_release;
  1591. /* mdio bus init */
  1592. ret = sh_mdio_init(ndev, pdev->id, pd);
  1593. if (ret)
  1594. goto out_unregister;
  1595. /* print device information */
  1596. pr_info("Base address at 0x%x, %pM, IRQ %d.\n",
  1597. (u32)ndev->base_addr, ndev->dev_addr, ndev->irq);
  1598. platform_set_drvdata(pdev, ndev);
  1599. return ret;
  1600. out_unregister:
  1601. unregister_netdev(ndev);
  1602. out_release:
  1603. /* net_dev free */
  1604. if (mdp && mdp->addr)
  1605. iounmap(mdp->addr);
  1606. if (mdp && mdp->tsu_addr)
  1607. iounmap(mdp->tsu_addr);
  1608. if (ndev)
  1609. free_netdev(ndev);
  1610. out:
  1611. return ret;
  1612. }
  1613. static int sh_eth_drv_remove(struct platform_device *pdev)
  1614. {
  1615. struct net_device *ndev = platform_get_drvdata(pdev);
  1616. struct sh_eth_private *mdp = netdev_priv(ndev);
  1617. iounmap(mdp->tsu_addr);
  1618. sh_mdio_release(ndev);
  1619. unregister_netdev(ndev);
  1620. pm_runtime_disable(&pdev->dev);
  1621. iounmap(mdp->addr);
  1622. free_netdev(ndev);
  1623. platform_set_drvdata(pdev, NULL);
  1624. return 0;
  1625. }
  1626. static int sh_eth_runtime_nop(struct device *dev)
  1627. {
  1628. /*
  1629. * Runtime PM callback shared between ->runtime_suspend()
  1630. * and ->runtime_resume(). Simply returns success.
  1631. *
  1632. * This driver re-initializes all registers after
  1633. * pm_runtime_get_sync() anyway so there is no need
  1634. * to save and restore registers here.
  1635. */
  1636. return 0;
  1637. }
  1638. static struct dev_pm_ops sh_eth_dev_pm_ops = {
  1639. .runtime_suspend = sh_eth_runtime_nop,
  1640. .runtime_resume = sh_eth_runtime_nop,
  1641. };
  1642. static struct platform_driver sh_eth_driver = {
  1643. .probe = sh_eth_drv_probe,
  1644. .remove = sh_eth_drv_remove,
  1645. .driver = {
  1646. .name = CARDNAME,
  1647. .pm = &sh_eth_dev_pm_ops,
  1648. },
  1649. };
  1650. static int __init sh_eth_init(void)
  1651. {
  1652. return platform_driver_register(&sh_eth_driver);
  1653. }
  1654. static void __exit sh_eth_cleanup(void)
  1655. {
  1656. platform_driver_unregister(&sh_eth_driver);
  1657. }
  1658. module_init(sh_eth_init);
  1659. module_exit(sh_eth_cleanup);
  1660. MODULE_AUTHOR("Nobuhiro Iwamatsu, Yoshihiro Shimoda");
  1661. MODULE_DESCRIPTION("Renesas SuperH Ethernet driver");
  1662. MODULE_LICENSE("GPL v2");