cnic.c 140 KB

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  1. /* cnic.c: Broadcom CNIC core network driver.
  2. *
  3. * Copyright (c) 2006-2011 Broadcom Corporation
  4. *
  5. * This program is free software; you can redistribute it and/or modify
  6. * it under the terms of the GNU General Public License as published by
  7. * the Free Software Foundation.
  8. *
  9. * Original skeleton written by: John(Zongxi) Chen (zongxi@broadcom.com)
  10. * Modified and maintained by: Michael Chan <mchan@broadcom.com>
  11. */
  12. #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
  13. #include <linux/module.h>
  14. #include <linux/kernel.h>
  15. #include <linux/errno.h>
  16. #include <linux/list.h>
  17. #include <linux/slab.h>
  18. #include <linux/pci.h>
  19. #include <linux/init.h>
  20. #include <linux/netdevice.h>
  21. #include <linux/uio_driver.h>
  22. #include <linux/in.h>
  23. #include <linux/dma-mapping.h>
  24. #include <linux/delay.h>
  25. #include <linux/ethtool.h>
  26. #include <linux/if_vlan.h>
  27. #include <linux/prefetch.h>
  28. #include <linux/random.h>
  29. #if defined(CONFIG_VLAN_8021Q) || defined(CONFIG_VLAN_8021Q_MODULE)
  30. #define BCM_VLAN 1
  31. #endif
  32. #include <net/ip.h>
  33. #include <net/tcp.h>
  34. #include <net/route.h>
  35. #include <net/ipv6.h>
  36. #include <net/ip6_route.h>
  37. #include <net/ip6_checksum.h>
  38. #include <scsi/iscsi_if.h>
  39. #include "cnic_if.h"
  40. #include "bnx2.h"
  41. #include "bnx2x/bnx2x_reg.h"
  42. #include "bnx2x/bnx2x_fw_defs.h"
  43. #include "bnx2x/bnx2x_hsi.h"
  44. #include "../../../scsi/bnx2i/57xx_iscsi_constants.h"
  45. #include "../../../scsi/bnx2i/57xx_iscsi_hsi.h"
  46. #include "cnic.h"
  47. #include "cnic_defs.h"
  48. #define DRV_MODULE_NAME "cnic"
  49. static char version[] __devinitdata =
  50. "Broadcom NetXtreme II CNIC Driver " DRV_MODULE_NAME " v" CNIC_MODULE_VERSION " (" CNIC_MODULE_RELDATE ")\n";
  51. MODULE_AUTHOR("Michael Chan <mchan@broadcom.com> and John(Zongxi) "
  52. "Chen (zongxi@broadcom.com");
  53. MODULE_DESCRIPTION("Broadcom NetXtreme II CNIC Driver");
  54. MODULE_LICENSE("GPL");
  55. MODULE_VERSION(CNIC_MODULE_VERSION);
  56. /* cnic_dev_list modifications are protected by both rtnl and cnic_dev_lock */
  57. static LIST_HEAD(cnic_dev_list);
  58. static LIST_HEAD(cnic_udev_list);
  59. static DEFINE_RWLOCK(cnic_dev_lock);
  60. static DEFINE_MUTEX(cnic_lock);
  61. static struct cnic_ulp_ops __rcu *cnic_ulp_tbl[MAX_CNIC_ULP_TYPE];
  62. /* helper function, assuming cnic_lock is held */
  63. static inline struct cnic_ulp_ops *cnic_ulp_tbl_prot(int type)
  64. {
  65. return rcu_dereference_protected(cnic_ulp_tbl[type],
  66. lockdep_is_held(&cnic_lock));
  67. }
  68. static int cnic_service_bnx2(void *, void *);
  69. static int cnic_service_bnx2x(void *, void *);
  70. static int cnic_ctl(void *, struct cnic_ctl_info *);
  71. static struct cnic_ops cnic_bnx2_ops = {
  72. .cnic_owner = THIS_MODULE,
  73. .cnic_handler = cnic_service_bnx2,
  74. .cnic_ctl = cnic_ctl,
  75. };
  76. static struct cnic_ops cnic_bnx2x_ops = {
  77. .cnic_owner = THIS_MODULE,
  78. .cnic_handler = cnic_service_bnx2x,
  79. .cnic_ctl = cnic_ctl,
  80. };
  81. static struct workqueue_struct *cnic_wq;
  82. static void cnic_shutdown_rings(struct cnic_dev *);
  83. static void cnic_init_rings(struct cnic_dev *);
  84. static int cnic_cm_set_pg(struct cnic_sock *);
  85. static int cnic_uio_open(struct uio_info *uinfo, struct inode *inode)
  86. {
  87. struct cnic_uio_dev *udev = uinfo->priv;
  88. struct cnic_dev *dev;
  89. if (!capable(CAP_NET_ADMIN))
  90. return -EPERM;
  91. if (udev->uio_dev != -1)
  92. return -EBUSY;
  93. rtnl_lock();
  94. dev = udev->dev;
  95. if (!dev || !test_bit(CNIC_F_CNIC_UP, &dev->flags)) {
  96. rtnl_unlock();
  97. return -ENODEV;
  98. }
  99. udev->uio_dev = iminor(inode);
  100. cnic_shutdown_rings(dev);
  101. cnic_init_rings(dev);
  102. rtnl_unlock();
  103. return 0;
  104. }
  105. static int cnic_uio_close(struct uio_info *uinfo, struct inode *inode)
  106. {
  107. struct cnic_uio_dev *udev = uinfo->priv;
  108. udev->uio_dev = -1;
  109. return 0;
  110. }
  111. static inline void cnic_hold(struct cnic_dev *dev)
  112. {
  113. atomic_inc(&dev->ref_count);
  114. }
  115. static inline void cnic_put(struct cnic_dev *dev)
  116. {
  117. atomic_dec(&dev->ref_count);
  118. }
  119. static inline void csk_hold(struct cnic_sock *csk)
  120. {
  121. atomic_inc(&csk->ref_count);
  122. }
  123. static inline void csk_put(struct cnic_sock *csk)
  124. {
  125. atomic_dec(&csk->ref_count);
  126. }
  127. static struct cnic_dev *cnic_from_netdev(struct net_device *netdev)
  128. {
  129. struct cnic_dev *cdev;
  130. read_lock(&cnic_dev_lock);
  131. list_for_each_entry(cdev, &cnic_dev_list, list) {
  132. if (netdev == cdev->netdev) {
  133. cnic_hold(cdev);
  134. read_unlock(&cnic_dev_lock);
  135. return cdev;
  136. }
  137. }
  138. read_unlock(&cnic_dev_lock);
  139. return NULL;
  140. }
  141. static inline void ulp_get(struct cnic_ulp_ops *ulp_ops)
  142. {
  143. atomic_inc(&ulp_ops->ref_count);
  144. }
  145. static inline void ulp_put(struct cnic_ulp_ops *ulp_ops)
  146. {
  147. atomic_dec(&ulp_ops->ref_count);
  148. }
  149. static void cnic_ctx_wr(struct cnic_dev *dev, u32 cid_addr, u32 off, u32 val)
  150. {
  151. struct cnic_local *cp = dev->cnic_priv;
  152. struct cnic_eth_dev *ethdev = cp->ethdev;
  153. struct drv_ctl_info info;
  154. struct drv_ctl_io *io = &info.data.io;
  155. info.cmd = DRV_CTL_CTX_WR_CMD;
  156. io->cid_addr = cid_addr;
  157. io->offset = off;
  158. io->data = val;
  159. ethdev->drv_ctl(dev->netdev, &info);
  160. }
  161. static void cnic_ctx_tbl_wr(struct cnic_dev *dev, u32 off, dma_addr_t addr)
  162. {
  163. struct cnic_local *cp = dev->cnic_priv;
  164. struct cnic_eth_dev *ethdev = cp->ethdev;
  165. struct drv_ctl_info info;
  166. struct drv_ctl_io *io = &info.data.io;
  167. info.cmd = DRV_CTL_CTXTBL_WR_CMD;
  168. io->offset = off;
  169. io->dma_addr = addr;
  170. ethdev->drv_ctl(dev->netdev, &info);
  171. }
  172. static void cnic_ring_ctl(struct cnic_dev *dev, u32 cid, u32 cl_id, int start)
  173. {
  174. struct cnic_local *cp = dev->cnic_priv;
  175. struct cnic_eth_dev *ethdev = cp->ethdev;
  176. struct drv_ctl_info info;
  177. struct drv_ctl_l2_ring *ring = &info.data.ring;
  178. if (start)
  179. info.cmd = DRV_CTL_START_L2_CMD;
  180. else
  181. info.cmd = DRV_CTL_STOP_L2_CMD;
  182. ring->cid = cid;
  183. ring->client_id = cl_id;
  184. ethdev->drv_ctl(dev->netdev, &info);
  185. }
  186. static void cnic_reg_wr_ind(struct cnic_dev *dev, u32 off, u32 val)
  187. {
  188. struct cnic_local *cp = dev->cnic_priv;
  189. struct cnic_eth_dev *ethdev = cp->ethdev;
  190. struct drv_ctl_info info;
  191. struct drv_ctl_io *io = &info.data.io;
  192. info.cmd = DRV_CTL_IO_WR_CMD;
  193. io->offset = off;
  194. io->data = val;
  195. ethdev->drv_ctl(dev->netdev, &info);
  196. }
  197. static u32 cnic_reg_rd_ind(struct cnic_dev *dev, u32 off)
  198. {
  199. struct cnic_local *cp = dev->cnic_priv;
  200. struct cnic_eth_dev *ethdev = cp->ethdev;
  201. struct drv_ctl_info info;
  202. struct drv_ctl_io *io = &info.data.io;
  203. info.cmd = DRV_CTL_IO_RD_CMD;
  204. io->offset = off;
  205. ethdev->drv_ctl(dev->netdev, &info);
  206. return io->data;
  207. }
  208. static int cnic_in_use(struct cnic_sock *csk)
  209. {
  210. return test_bit(SK_F_INUSE, &csk->flags);
  211. }
  212. static void cnic_spq_completion(struct cnic_dev *dev, int cmd, u32 count)
  213. {
  214. struct cnic_local *cp = dev->cnic_priv;
  215. struct cnic_eth_dev *ethdev = cp->ethdev;
  216. struct drv_ctl_info info;
  217. info.cmd = cmd;
  218. info.data.credit.credit_count = count;
  219. ethdev->drv_ctl(dev->netdev, &info);
  220. }
  221. static int cnic_get_l5_cid(struct cnic_local *cp, u32 cid, u32 *l5_cid)
  222. {
  223. u32 i;
  224. for (i = 0; i < cp->max_cid_space; i++) {
  225. if (cp->ctx_tbl[i].cid == cid) {
  226. *l5_cid = i;
  227. return 0;
  228. }
  229. }
  230. return -EINVAL;
  231. }
  232. static int cnic_send_nlmsg(struct cnic_local *cp, u32 type,
  233. struct cnic_sock *csk)
  234. {
  235. struct iscsi_path path_req;
  236. char *buf = NULL;
  237. u16 len = 0;
  238. u32 msg_type = ISCSI_KEVENT_IF_DOWN;
  239. struct cnic_ulp_ops *ulp_ops;
  240. struct cnic_uio_dev *udev = cp->udev;
  241. int rc = 0, retry = 0;
  242. if (!udev || udev->uio_dev == -1)
  243. return -ENODEV;
  244. if (csk) {
  245. len = sizeof(path_req);
  246. buf = (char *) &path_req;
  247. memset(&path_req, 0, len);
  248. msg_type = ISCSI_KEVENT_PATH_REQ;
  249. path_req.handle = (u64) csk->l5_cid;
  250. if (test_bit(SK_F_IPV6, &csk->flags)) {
  251. memcpy(&path_req.dst.v6_addr, &csk->dst_ip[0],
  252. sizeof(struct in6_addr));
  253. path_req.ip_addr_len = 16;
  254. } else {
  255. memcpy(&path_req.dst.v4_addr, &csk->dst_ip[0],
  256. sizeof(struct in_addr));
  257. path_req.ip_addr_len = 4;
  258. }
  259. path_req.vlan_id = csk->vlan_id;
  260. path_req.pmtu = csk->mtu;
  261. }
  262. while (retry < 3) {
  263. rc = 0;
  264. rcu_read_lock();
  265. ulp_ops = rcu_dereference(cnic_ulp_tbl[CNIC_ULP_ISCSI]);
  266. if (ulp_ops)
  267. rc = ulp_ops->iscsi_nl_send_msg(
  268. cp->ulp_handle[CNIC_ULP_ISCSI],
  269. msg_type, buf, len);
  270. rcu_read_unlock();
  271. if (rc == 0 || msg_type != ISCSI_KEVENT_PATH_REQ)
  272. break;
  273. msleep(100);
  274. retry++;
  275. }
  276. return rc;
  277. }
  278. static void cnic_cm_upcall(struct cnic_local *, struct cnic_sock *, u8);
  279. static int cnic_iscsi_nl_msg_recv(struct cnic_dev *dev, u32 msg_type,
  280. char *buf, u16 len)
  281. {
  282. int rc = -EINVAL;
  283. switch (msg_type) {
  284. case ISCSI_UEVENT_PATH_UPDATE: {
  285. struct cnic_local *cp;
  286. u32 l5_cid;
  287. struct cnic_sock *csk;
  288. struct iscsi_path *path_resp;
  289. if (len < sizeof(*path_resp))
  290. break;
  291. path_resp = (struct iscsi_path *) buf;
  292. cp = dev->cnic_priv;
  293. l5_cid = (u32) path_resp->handle;
  294. if (l5_cid >= MAX_CM_SK_TBL_SZ)
  295. break;
  296. rcu_read_lock();
  297. if (!rcu_dereference(cp->ulp_ops[CNIC_ULP_L4])) {
  298. rc = -ENODEV;
  299. rcu_read_unlock();
  300. break;
  301. }
  302. csk = &cp->csk_tbl[l5_cid];
  303. csk_hold(csk);
  304. if (cnic_in_use(csk) &&
  305. test_bit(SK_F_CONNECT_START, &csk->flags)) {
  306. memcpy(csk->ha, path_resp->mac_addr, 6);
  307. if (test_bit(SK_F_IPV6, &csk->flags))
  308. memcpy(&csk->src_ip[0], &path_resp->src.v6_addr,
  309. sizeof(struct in6_addr));
  310. else
  311. memcpy(&csk->src_ip[0], &path_resp->src.v4_addr,
  312. sizeof(struct in_addr));
  313. if (is_valid_ether_addr(csk->ha)) {
  314. cnic_cm_set_pg(csk);
  315. } else if (!test_bit(SK_F_OFFLD_SCHED, &csk->flags) &&
  316. !test_bit(SK_F_OFFLD_COMPLETE, &csk->flags)) {
  317. cnic_cm_upcall(cp, csk,
  318. L4_KCQE_OPCODE_VALUE_CONNECT_COMPLETE);
  319. clear_bit(SK_F_CONNECT_START, &csk->flags);
  320. }
  321. }
  322. csk_put(csk);
  323. rcu_read_unlock();
  324. rc = 0;
  325. }
  326. }
  327. return rc;
  328. }
  329. static int cnic_offld_prep(struct cnic_sock *csk)
  330. {
  331. if (test_and_set_bit(SK_F_OFFLD_SCHED, &csk->flags))
  332. return 0;
  333. if (!test_bit(SK_F_CONNECT_START, &csk->flags)) {
  334. clear_bit(SK_F_OFFLD_SCHED, &csk->flags);
  335. return 0;
  336. }
  337. return 1;
  338. }
  339. static int cnic_close_prep(struct cnic_sock *csk)
  340. {
  341. clear_bit(SK_F_CONNECT_START, &csk->flags);
  342. smp_mb__after_clear_bit();
  343. if (test_and_clear_bit(SK_F_OFFLD_COMPLETE, &csk->flags)) {
  344. while (test_and_set_bit(SK_F_OFFLD_SCHED, &csk->flags))
  345. msleep(1);
  346. return 1;
  347. }
  348. return 0;
  349. }
  350. static int cnic_abort_prep(struct cnic_sock *csk)
  351. {
  352. clear_bit(SK_F_CONNECT_START, &csk->flags);
  353. smp_mb__after_clear_bit();
  354. while (test_and_set_bit(SK_F_OFFLD_SCHED, &csk->flags))
  355. msleep(1);
  356. if (test_and_clear_bit(SK_F_OFFLD_COMPLETE, &csk->flags)) {
  357. csk->state = L4_KCQE_OPCODE_VALUE_RESET_COMP;
  358. return 1;
  359. }
  360. return 0;
  361. }
  362. int cnic_register_driver(int ulp_type, struct cnic_ulp_ops *ulp_ops)
  363. {
  364. struct cnic_dev *dev;
  365. if (ulp_type < 0 || ulp_type >= MAX_CNIC_ULP_TYPE) {
  366. pr_err("%s: Bad type %d\n", __func__, ulp_type);
  367. return -EINVAL;
  368. }
  369. mutex_lock(&cnic_lock);
  370. if (cnic_ulp_tbl_prot(ulp_type)) {
  371. pr_err("%s: Type %d has already been registered\n",
  372. __func__, ulp_type);
  373. mutex_unlock(&cnic_lock);
  374. return -EBUSY;
  375. }
  376. read_lock(&cnic_dev_lock);
  377. list_for_each_entry(dev, &cnic_dev_list, list) {
  378. struct cnic_local *cp = dev->cnic_priv;
  379. clear_bit(ULP_F_INIT, &cp->ulp_flags[ulp_type]);
  380. }
  381. read_unlock(&cnic_dev_lock);
  382. atomic_set(&ulp_ops->ref_count, 0);
  383. rcu_assign_pointer(cnic_ulp_tbl[ulp_type], ulp_ops);
  384. mutex_unlock(&cnic_lock);
  385. /* Prevent race conditions with netdev_event */
  386. rtnl_lock();
  387. list_for_each_entry(dev, &cnic_dev_list, list) {
  388. struct cnic_local *cp = dev->cnic_priv;
  389. if (!test_and_set_bit(ULP_F_INIT, &cp->ulp_flags[ulp_type]))
  390. ulp_ops->cnic_init(dev);
  391. }
  392. rtnl_unlock();
  393. return 0;
  394. }
  395. int cnic_unregister_driver(int ulp_type)
  396. {
  397. struct cnic_dev *dev;
  398. struct cnic_ulp_ops *ulp_ops;
  399. int i = 0;
  400. if (ulp_type < 0 || ulp_type >= MAX_CNIC_ULP_TYPE) {
  401. pr_err("%s: Bad type %d\n", __func__, ulp_type);
  402. return -EINVAL;
  403. }
  404. mutex_lock(&cnic_lock);
  405. ulp_ops = cnic_ulp_tbl_prot(ulp_type);
  406. if (!ulp_ops) {
  407. pr_err("%s: Type %d has not been registered\n",
  408. __func__, ulp_type);
  409. goto out_unlock;
  410. }
  411. read_lock(&cnic_dev_lock);
  412. list_for_each_entry(dev, &cnic_dev_list, list) {
  413. struct cnic_local *cp = dev->cnic_priv;
  414. if (rcu_dereference(cp->ulp_ops[ulp_type])) {
  415. pr_err("%s: Type %d still has devices registered\n",
  416. __func__, ulp_type);
  417. read_unlock(&cnic_dev_lock);
  418. goto out_unlock;
  419. }
  420. }
  421. read_unlock(&cnic_dev_lock);
  422. rcu_assign_pointer(cnic_ulp_tbl[ulp_type], NULL);
  423. mutex_unlock(&cnic_lock);
  424. synchronize_rcu();
  425. while ((atomic_read(&ulp_ops->ref_count) != 0) && (i < 20)) {
  426. msleep(100);
  427. i++;
  428. }
  429. if (atomic_read(&ulp_ops->ref_count) != 0)
  430. netdev_warn(dev->netdev, "Failed waiting for ref count to go to zero\n");
  431. return 0;
  432. out_unlock:
  433. mutex_unlock(&cnic_lock);
  434. return -EINVAL;
  435. }
  436. static int cnic_start_hw(struct cnic_dev *);
  437. static void cnic_stop_hw(struct cnic_dev *);
  438. static int cnic_register_device(struct cnic_dev *dev, int ulp_type,
  439. void *ulp_ctx)
  440. {
  441. struct cnic_local *cp = dev->cnic_priv;
  442. struct cnic_ulp_ops *ulp_ops;
  443. if (ulp_type < 0 || ulp_type >= MAX_CNIC_ULP_TYPE) {
  444. pr_err("%s: Bad type %d\n", __func__, ulp_type);
  445. return -EINVAL;
  446. }
  447. mutex_lock(&cnic_lock);
  448. if (cnic_ulp_tbl_prot(ulp_type) == NULL) {
  449. pr_err("%s: Driver with type %d has not been registered\n",
  450. __func__, ulp_type);
  451. mutex_unlock(&cnic_lock);
  452. return -EAGAIN;
  453. }
  454. if (rcu_dereference(cp->ulp_ops[ulp_type])) {
  455. pr_err("%s: Type %d has already been registered to this device\n",
  456. __func__, ulp_type);
  457. mutex_unlock(&cnic_lock);
  458. return -EBUSY;
  459. }
  460. clear_bit(ULP_F_START, &cp->ulp_flags[ulp_type]);
  461. cp->ulp_handle[ulp_type] = ulp_ctx;
  462. ulp_ops = cnic_ulp_tbl_prot(ulp_type);
  463. rcu_assign_pointer(cp->ulp_ops[ulp_type], ulp_ops);
  464. cnic_hold(dev);
  465. if (test_bit(CNIC_F_CNIC_UP, &dev->flags))
  466. if (!test_and_set_bit(ULP_F_START, &cp->ulp_flags[ulp_type]))
  467. ulp_ops->cnic_start(cp->ulp_handle[ulp_type]);
  468. mutex_unlock(&cnic_lock);
  469. return 0;
  470. }
  471. EXPORT_SYMBOL(cnic_register_driver);
  472. static int cnic_unregister_device(struct cnic_dev *dev, int ulp_type)
  473. {
  474. struct cnic_local *cp = dev->cnic_priv;
  475. int i = 0;
  476. if (ulp_type < 0 || ulp_type >= MAX_CNIC_ULP_TYPE) {
  477. pr_err("%s: Bad type %d\n", __func__, ulp_type);
  478. return -EINVAL;
  479. }
  480. mutex_lock(&cnic_lock);
  481. if (rcu_dereference(cp->ulp_ops[ulp_type])) {
  482. rcu_assign_pointer(cp->ulp_ops[ulp_type], NULL);
  483. cnic_put(dev);
  484. } else {
  485. pr_err("%s: device not registered to this ulp type %d\n",
  486. __func__, ulp_type);
  487. mutex_unlock(&cnic_lock);
  488. return -EINVAL;
  489. }
  490. mutex_unlock(&cnic_lock);
  491. if (ulp_type == CNIC_ULP_ISCSI)
  492. cnic_send_nlmsg(cp, ISCSI_KEVENT_IF_DOWN, NULL);
  493. synchronize_rcu();
  494. while (test_bit(ULP_F_CALL_PENDING, &cp->ulp_flags[ulp_type]) &&
  495. i < 20) {
  496. msleep(100);
  497. i++;
  498. }
  499. if (test_bit(ULP_F_CALL_PENDING, &cp->ulp_flags[ulp_type]))
  500. netdev_warn(dev->netdev, "Failed waiting for ULP up call to complete\n");
  501. return 0;
  502. }
  503. EXPORT_SYMBOL(cnic_unregister_driver);
  504. static int cnic_init_id_tbl(struct cnic_id_tbl *id_tbl, u32 size, u32 start_id,
  505. u32 next)
  506. {
  507. id_tbl->start = start_id;
  508. id_tbl->max = size;
  509. id_tbl->next = next;
  510. spin_lock_init(&id_tbl->lock);
  511. id_tbl->table = kzalloc(DIV_ROUND_UP(size, 32) * 4, GFP_KERNEL);
  512. if (!id_tbl->table)
  513. return -ENOMEM;
  514. return 0;
  515. }
  516. static void cnic_free_id_tbl(struct cnic_id_tbl *id_tbl)
  517. {
  518. kfree(id_tbl->table);
  519. id_tbl->table = NULL;
  520. }
  521. static int cnic_alloc_id(struct cnic_id_tbl *id_tbl, u32 id)
  522. {
  523. int ret = -1;
  524. id -= id_tbl->start;
  525. if (id >= id_tbl->max)
  526. return ret;
  527. spin_lock(&id_tbl->lock);
  528. if (!test_bit(id, id_tbl->table)) {
  529. set_bit(id, id_tbl->table);
  530. ret = 0;
  531. }
  532. spin_unlock(&id_tbl->lock);
  533. return ret;
  534. }
  535. /* Returns -1 if not successful */
  536. static u32 cnic_alloc_new_id(struct cnic_id_tbl *id_tbl)
  537. {
  538. u32 id;
  539. spin_lock(&id_tbl->lock);
  540. id = find_next_zero_bit(id_tbl->table, id_tbl->max, id_tbl->next);
  541. if (id >= id_tbl->max) {
  542. id = -1;
  543. if (id_tbl->next != 0) {
  544. id = find_first_zero_bit(id_tbl->table, id_tbl->next);
  545. if (id >= id_tbl->next)
  546. id = -1;
  547. }
  548. }
  549. if (id < id_tbl->max) {
  550. set_bit(id, id_tbl->table);
  551. id_tbl->next = (id + 1) & (id_tbl->max - 1);
  552. id += id_tbl->start;
  553. }
  554. spin_unlock(&id_tbl->lock);
  555. return id;
  556. }
  557. static void cnic_free_id(struct cnic_id_tbl *id_tbl, u32 id)
  558. {
  559. if (id == -1)
  560. return;
  561. id -= id_tbl->start;
  562. if (id >= id_tbl->max)
  563. return;
  564. clear_bit(id, id_tbl->table);
  565. }
  566. static void cnic_free_dma(struct cnic_dev *dev, struct cnic_dma *dma)
  567. {
  568. int i;
  569. if (!dma->pg_arr)
  570. return;
  571. for (i = 0; i < dma->num_pages; i++) {
  572. if (dma->pg_arr[i]) {
  573. dma_free_coherent(&dev->pcidev->dev, BCM_PAGE_SIZE,
  574. dma->pg_arr[i], dma->pg_map_arr[i]);
  575. dma->pg_arr[i] = NULL;
  576. }
  577. }
  578. if (dma->pgtbl) {
  579. dma_free_coherent(&dev->pcidev->dev, dma->pgtbl_size,
  580. dma->pgtbl, dma->pgtbl_map);
  581. dma->pgtbl = NULL;
  582. }
  583. kfree(dma->pg_arr);
  584. dma->pg_arr = NULL;
  585. dma->num_pages = 0;
  586. }
  587. static void cnic_setup_page_tbl(struct cnic_dev *dev, struct cnic_dma *dma)
  588. {
  589. int i;
  590. __le32 *page_table = (__le32 *) dma->pgtbl;
  591. for (i = 0; i < dma->num_pages; i++) {
  592. /* Each entry needs to be in big endian format. */
  593. *page_table = cpu_to_le32((u64) dma->pg_map_arr[i] >> 32);
  594. page_table++;
  595. *page_table = cpu_to_le32(dma->pg_map_arr[i] & 0xffffffff);
  596. page_table++;
  597. }
  598. }
  599. static void cnic_setup_page_tbl_le(struct cnic_dev *dev, struct cnic_dma *dma)
  600. {
  601. int i;
  602. __le32 *page_table = (__le32 *) dma->pgtbl;
  603. for (i = 0; i < dma->num_pages; i++) {
  604. /* Each entry needs to be in little endian format. */
  605. *page_table = cpu_to_le32(dma->pg_map_arr[i] & 0xffffffff);
  606. page_table++;
  607. *page_table = cpu_to_le32((u64) dma->pg_map_arr[i] >> 32);
  608. page_table++;
  609. }
  610. }
  611. static int cnic_alloc_dma(struct cnic_dev *dev, struct cnic_dma *dma,
  612. int pages, int use_pg_tbl)
  613. {
  614. int i, size;
  615. struct cnic_local *cp = dev->cnic_priv;
  616. size = pages * (sizeof(void *) + sizeof(dma_addr_t));
  617. dma->pg_arr = kzalloc(size, GFP_ATOMIC);
  618. if (dma->pg_arr == NULL)
  619. return -ENOMEM;
  620. dma->pg_map_arr = (dma_addr_t *) (dma->pg_arr + pages);
  621. dma->num_pages = pages;
  622. for (i = 0; i < pages; i++) {
  623. dma->pg_arr[i] = dma_alloc_coherent(&dev->pcidev->dev,
  624. BCM_PAGE_SIZE,
  625. &dma->pg_map_arr[i],
  626. GFP_ATOMIC);
  627. if (dma->pg_arr[i] == NULL)
  628. goto error;
  629. }
  630. if (!use_pg_tbl)
  631. return 0;
  632. dma->pgtbl_size = ((pages * 8) + BCM_PAGE_SIZE - 1) &
  633. ~(BCM_PAGE_SIZE - 1);
  634. dma->pgtbl = dma_alloc_coherent(&dev->pcidev->dev, dma->pgtbl_size,
  635. &dma->pgtbl_map, GFP_ATOMIC);
  636. if (dma->pgtbl == NULL)
  637. goto error;
  638. cp->setup_pgtbl(dev, dma);
  639. return 0;
  640. error:
  641. cnic_free_dma(dev, dma);
  642. return -ENOMEM;
  643. }
  644. static void cnic_free_context(struct cnic_dev *dev)
  645. {
  646. struct cnic_local *cp = dev->cnic_priv;
  647. int i;
  648. for (i = 0; i < cp->ctx_blks; i++) {
  649. if (cp->ctx_arr[i].ctx) {
  650. dma_free_coherent(&dev->pcidev->dev, cp->ctx_blk_size,
  651. cp->ctx_arr[i].ctx,
  652. cp->ctx_arr[i].mapping);
  653. cp->ctx_arr[i].ctx = NULL;
  654. }
  655. }
  656. }
  657. static void __cnic_free_uio(struct cnic_uio_dev *udev)
  658. {
  659. uio_unregister_device(&udev->cnic_uinfo);
  660. if (udev->l2_buf) {
  661. dma_free_coherent(&udev->pdev->dev, udev->l2_buf_size,
  662. udev->l2_buf, udev->l2_buf_map);
  663. udev->l2_buf = NULL;
  664. }
  665. if (udev->l2_ring) {
  666. dma_free_coherent(&udev->pdev->dev, udev->l2_ring_size,
  667. udev->l2_ring, udev->l2_ring_map);
  668. udev->l2_ring = NULL;
  669. }
  670. pci_dev_put(udev->pdev);
  671. kfree(udev);
  672. }
  673. static void cnic_free_uio(struct cnic_uio_dev *udev)
  674. {
  675. if (!udev)
  676. return;
  677. write_lock(&cnic_dev_lock);
  678. list_del_init(&udev->list);
  679. write_unlock(&cnic_dev_lock);
  680. __cnic_free_uio(udev);
  681. }
  682. static void cnic_free_resc(struct cnic_dev *dev)
  683. {
  684. struct cnic_local *cp = dev->cnic_priv;
  685. struct cnic_uio_dev *udev = cp->udev;
  686. if (udev) {
  687. udev->dev = NULL;
  688. cp->udev = NULL;
  689. }
  690. cnic_free_context(dev);
  691. kfree(cp->ctx_arr);
  692. cp->ctx_arr = NULL;
  693. cp->ctx_blks = 0;
  694. cnic_free_dma(dev, &cp->gbl_buf_info);
  695. cnic_free_dma(dev, &cp->kwq_info);
  696. cnic_free_dma(dev, &cp->kwq_16_data_info);
  697. cnic_free_dma(dev, &cp->kcq2.dma);
  698. cnic_free_dma(dev, &cp->kcq1.dma);
  699. kfree(cp->iscsi_tbl);
  700. cp->iscsi_tbl = NULL;
  701. kfree(cp->ctx_tbl);
  702. cp->ctx_tbl = NULL;
  703. cnic_free_id_tbl(&cp->fcoe_cid_tbl);
  704. cnic_free_id_tbl(&cp->cid_tbl);
  705. }
  706. static int cnic_alloc_context(struct cnic_dev *dev)
  707. {
  708. struct cnic_local *cp = dev->cnic_priv;
  709. if (CHIP_NUM(cp) == CHIP_NUM_5709) {
  710. int i, k, arr_size;
  711. cp->ctx_blk_size = BCM_PAGE_SIZE;
  712. cp->cids_per_blk = BCM_PAGE_SIZE / 128;
  713. arr_size = BNX2_MAX_CID / cp->cids_per_blk *
  714. sizeof(struct cnic_ctx);
  715. cp->ctx_arr = kzalloc(arr_size, GFP_KERNEL);
  716. if (cp->ctx_arr == NULL)
  717. return -ENOMEM;
  718. k = 0;
  719. for (i = 0; i < 2; i++) {
  720. u32 j, reg, off, lo, hi;
  721. if (i == 0)
  722. off = BNX2_PG_CTX_MAP;
  723. else
  724. off = BNX2_ISCSI_CTX_MAP;
  725. reg = cnic_reg_rd_ind(dev, off);
  726. lo = reg >> 16;
  727. hi = reg & 0xffff;
  728. for (j = lo; j < hi; j += cp->cids_per_blk, k++)
  729. cp->ctx_arr[k].cid = j;
  730. }
  731. cp->ctx_blks = k;
  732. if (cp->ctx_blks >= (BNX2_MAX_CID / cp->cids_per_blk)) {
  733. cp->ctx_blks = 0;
  734. return -ENOMEM;
  735. }
  736. for (i = 0; i < cp->ctx_blks; i++) {
  737. cp->ctx_arr[i].ctx =
  738. dma_alloc_coherent(&dev->pcidev->dev,
  739. BCM_PAGE_SIZE,
  740. &cp->ctx_arr[i].mapping,
  741. GFP_KERNEL);
  742. if (cp->ctx_arr[i].ctx == NULL)
  743. return -ENOMEM;
  744. }
  745. }
  746. return 0;
  747. }
  748. static u16 cnic_bnx2_next_idx(u16 idx)
  749. {
  750. return idx + 1;
  751. }
  752. static u16 cnic_bnx2_hw_idx(u16 idx)
  753. {
  754. return idx;
  755. }
  756. static u16 cnic_bnx2x_next_idx(u16 idx)
  757. {
  758. idx++;
  759. if ((idx & MAX_KCQE_CNT) == MAX_KCQE_CNT)
  760. idx++;
  761. return idx;
  762. }
  763. static u16 cnic_bnx2x_hw_idx(u16 idx)
  764. {
  765. if ((idx & MAX_KCQE_CNT) == MAX_KCQE_CNT)
  766. idx++;
  767. return idx;
  768. }
  769. static int cnic_alloc_kcq(struct cnic_dev *dev, struct kcq_info *info,
  770. bool use_pg_tbl)
  771. {
  772. int err, i, use_page_tbl = 0;
  773. struct kcqe **kcq;
  774. if (use_pg_tbl)
  775. use_page_tbl = 1;
  776. err = cnic_alloc_dma(dev, &info->dma, KCQ_PAGE_CNT, use_page_tbl);
  777. if (err)
  778. return err;
  779. kcq = (struct kcqe **) info->dma.pg_arr;
  780. info->kcq = kcq;
  781. info->next_idx = cnic_bnx2_next_idx;
  782. info->hw_idx = cnic_bnx2_hw_idx;
  783. if (use_pg_tbl)
  784. return 0;
  785. info->next_idx = cnic_bnx2x_next_idx;
  786. info->hw_idx = cnic_bnx2x_hw_idx;
  787. for (i = 0; i < KCQ_PAGE_CNT; i++) {
  788. struct bnx2x_bd_chain_next *next =
  789. (struct bnx2x_bd_chain_next *) &kcq[i][MAX_KCQE_CNT];
  790. int j = i + 1;
  791. if (j >= KCQ_PAGE_CNT)
  792. j = 0;
  793. next->addr_hi = (u64) info->dma.pg_map_arr[j] >> 32;
  794. next->addr_lo = info->dma.pg_map_arr[j] & 0xffffffff;
  795. }
  796. return 0;
  797. }
  798. static int cnic_alloc_uio_rings(struct cnic_dev *dev, int pages)
  799. {
  800. struct cnic_local *cp = dev->cnic_priv;
  801. struct cnic_uio_dev *udev;
  802. read_lock(&cnic_dev_lock);
  803. list_for_each_entry(udev, &cnic_udev_list, list) {
  804. if (udev->pdev == dev->pcidev) {
  805. udev->dev = dev;
  806. cp->udev = udev;
  807. read_unlock(&cnic_dev_lock);
  808. return 0;
  809. }
  810. }
  811. read_unlock(&cnic_dev_lock);
  812. udev = kzalloc(sizeof(struct cnic_uio_dev), GFP_ATOMIC);
  813. if (!udev)
  814. return -ENOMEM;
  815. udev->uio_dev = -1;
  816. udev->dev = dev;
  817. udev->pdev = dev->pcidev;
  818. udev->l2_ring_size = pages * BCM_PAGE_SIZE;
  819. udev->l2_ring = dma_alloc_coherent(&udev->pdev->dev, udev->l2_ring_size,
  820. &udev->l2_ring_map,
  821. GFP_KERNEL | __GFP_COMP);
  822. if (!udev->l2_ring)
  823. goto err_udev;
  824. udev->l2_buf_size = (cp->l2_rx_ring_size + 1) * cp->l2_single_buf_size;
  825. udev->l2_buf_size = PAGE_ALIGN(udev->l2_buf_size);
  826. udev->l2_buf = dma_alloc_coherent(&udev->pdev->dev, udev->l2_buf_size,
  827. &udev->l2_buf_map,
  828. GFP_KERNEL | __GFP_COMP);
  829. if (!udev->l2_buf)
  830. goto err_dma;
  831. write_lock(&cnic_dev_lock);
  832. list_add(&udev->list, &cnic_udev_list);
  833. write_unlock(&cnic_dev_lock);
  834. pci_dev_get(udev->pdev);
  835. cp->udev = udev;
  836. return 0;
  837. err_dma:
  838. dma_free_coherent(&udev->pdev->dev, udev->l2_ring_size,
  839. udev->l2_ring, udev->l2_ring_map);
  840. err_udev:
  841. kfree(udev);
  842. return -ENOMEM;
  843. }
  844. static int cnic_init_uio(struct cnic_dev *dev)
  845. {
  846. struct cnic_local *cp = dev->cnic_priv;
  847. struct cnic_uio_dev *udev = cp->udev;
  848. struct uio_info *uinfo;
  849. int ret = 0;
  850. if (!udev)
  851. return -ENOMEM;
  852. uinfo = &udev->cnic_uinfo;
  853. uinfo->mem[0].addr = dev->netdev->base_addr;
  854. uinfo->mem[0].internal_addr = dev->regview;
  855. uinfo->mem[0].size = dev->netdev->mem_end - dev->netdev->mem_start;
  856. uinfo->mem[0].memtype = UIO_MEM_PHYS;
  857. if (test_bit(CNIC_F_BNX2_CLASS, &dev->flags)) {
  858. uinfo->mem[1].addr = (unsigned long) cp->status_blk.gen &
  859. PAGE_MASK;
  860. if (cp->ethdev->drv_state & CNIC_DRV_STATE_USING_MSIX)
  861. uinfo->mem[1].size = BNX2_SBLK_MSIX_ALIGN_SIZE * 9;
  862. else
  863. uinfo->mem[1].size = BNX2_SBLK_MSIX_ALIGN_SIZE;
  864. uinfo->name = "bnx2_cnic";
  865. } else if (test_bit(CNIC_F_BNX2X_CLASS, &dev->flags)) {
  866. uinfo->mem[1].addr = (unsigned long) cp->bnx2x_def_status_blk &
  867. PAGE_MASK;
  868. uinfo->mem[1].size = sizeof(*cp->bnx2x_def_status_blk);
  869. uinfo->name = "bnx2x_cnic";
  870. }
  871. uinfo->mem[1].memtype = UIO_MEM_LOGICAL;
  872. uinfo->mem[2].addr = (unsigned long) udev->l2_ring;
  873. uinfo->mem[2].size = udev->l2_ring_size;
  874. uinfo->mem[2].memtype = UIO_MEM_LOGICAL;
  875. uinfo->mem[3].addr = (unsigned long) udev->l2_buf;
  876. uinfo->mem[3].size = udev->l2_buf_size;
  877. uinfo->mem[3].memtype = UIO_MEM_LOGICAL;
  878. uinfo->version = CNIC_MODULE_VERSION;
  879. uinfo->irq = UIO_IRQ_CUSTOM;
  880. uinfo->open = cnic_uio_open;
  881. uinfo->release = cnic_uio_close;
  882. if (udev->uio_dev == -1) {
  883. if (!uinfo->priv) {
  884. uinfo->priv = udev;
  885. ret = uio_register_device(&udev->pdev->dev, uinfo);
  886. }
  887. } else {
  888. cnic_init_rings(dev);
  889. }
  890. return ret;
  891. }
  892. static int cnic_alloc_bnx2_resc(struct cnic_dev *dev)
  893. {
  894. struct cnic_local *cp = dev->cnic_priv;
  895. int ret;
  896. ret = cnic_alloc_dma(dev, &cp->kwq_info, KWQ_PAGE_CNT, 1);
  897. if (ret)
  898. goto error;
  899. cp->kwq = (struct kwqe **) cp->kwq_info.pg_arr;
  900. ret = cnic_alloc_kcq(dev, &cp->kcq1, true);
  901. if (ret)
  902. goto error;
  903. ret = cnic_alloc_context(dev);
  904. if (ret)
  905. goto error;
  906. ret = cnic_alloc_uio_rings(dev, 2);
  907. if (ret)
  908. goto error;
  909. ret = cnic_init_uio(dev);
  910. if (ret)
  911. goto error;
  912. return 0;
  913. error:
  914. cnic_free_resc(dev);
  915. return ret;
  916. }
  917. static int cnic_alloc_bnx2x_context(struct cnic_dev *dev)
  918. {
  919. struct cnic_local *cp = dev->cnic_priv;
  920. int ctx_blk_size = cp->ethdev->ctx_blk_size;
  921. int total_mem, blks, i;
  922. total_mem = BNX2X_CONTEXT_MEM_SIZE * cp->max_cid_space;
  923. blks = total_mem / ctx_blk_size;
  924. if (total_mem % ctx_blk_size)
  925. blks++;
  926. if (blks > cp->ethdev->ctx_tbl_len)
  927. return -ENOMEM;
  928. cp->ctx_arr = kcalloc(blks, sizeof(struct cnic_ctx), GFP_KERNEL);
  929. if (cp->ctx_arr == NULL)
  930. return -ENOMEM;
  931. cp->ctx_blks = blks;
  932. cp->ctx_blk_size = ctx_blk_size;
  933. if (!BNX2X_CHIP_IS_57710(cp->chip_id))
  934. cp->ctx_align = 0;
  935. else
  936. cp->ctx_align = ctx_blk_size;
  937. cp->cids_per_blk = ctx_blk_size / BNX2X_CONTEXT_MEM_SIZE;
  938. for (i = 0; i < blks; i++) {
  939. cp->ctx_arr[i].ctx =
  940. dma_alloc_coherent(&dev->pcidev->dev, cp->ctx_blk_size,
  941. &cp->ctx_arr[i].mapping,
  942. GFP_KERNEL);
  943. if (cp->ctx_arr[i].ctx == NULL)
  944. return -ENOMEM;
  945. if (cp->ctx_align && cp->ctx_blk_size == ctx_blk_size) {
  946. if (cp->ctx_arr[i].mapping & (cp->ctx_align - 1)) {
  947. cnic_free_context(dev);
  948. cp->ctx_blk_size += cp->ctx_align;
  949. i = -1;
  950. continue;
  951. }
  952. }
  953. }
  954. return 0;
  955. }
  956. static int cnic_alloc_bnx2x_resc(struct cnic_dev *dev)
  957. {
  958. struct cnic_local *cp = dev->cnic_priv;
  959. struct cnic_eth_dev *ethdev = cp->ethdev;
  960. u32 start_cid = ethdev->starting_cid;
  961. int i, j, n, ret, pages;
  962. struct cnic_dma *kwq_16_dma = &cp->kwq_16_data_info;
  963. cp->iro_arr = ethdev->iro_arr;
  964. cp->max_cid_space = MAX_ISCSI_TBL_SZ;
  965. cp->iscsi_start_cid = start_cid;
  966. cp->fcoe_start_cid = start_cid + MAX_ISCSI_TBL_SZ;
  967. if (BNX2X_CHIP_IS_E2_PLUS(cp->chip_id)) {
  968. cp->max_cid_space += dev->max_fcoe_conn;
  969. cp->fcoe_init_cid = ethdev->fcoe_init_cid;
  970. if (!cp->fcoe_init_cid)
  971. cp->fcoe_init_cid = 0x10;
  972. }
  973. cp->iscsi_tbl = kzalloc(sizeof(struct cnic_iscsi) * MAX_ISCSI_TBL_SZ,
  974. GFP_KERNEL);
  975. if (!cp->iscsi_tbl)
  976. goto error;
  977. cp->ctx_tbl = kzalloc(sizeof(struct cnic_context) *
  978. cp->max_cid_space, GFP_KERNEL);
  979. if (!cp->ctx_tbl)
  980. goto error;
  981. for (i = 0; i < MAX_ISCSI_TBL_SZ; i++) {
  982. cp->ctx_tbl[i].proto.iscsi = &cp->iscsi_tbl[i];
  983. cp->ctx_tbl[i].ulp_proto_id = CNIC_ULP_ISCSI;
  984. }
  985. for (i = MAX_ISCSI_TBL_SZ; i < cp->max_cid_space; i++)
  986. cp->ctx_tbl[i].ulp_proto_id = CNIC_ULP_FCOE;
  987. pages = PAGE_ALIGN(cp->max_cid_space * CNIC_KWQ16_DATA_SIZE) /
  988. PAGE_SIZE;
  989. ret = cnic_alloc_dma(dev, kwq_16_dma, pages, 0);
  990. if (ret)
  991. return -ENOMEM;
  992. n = PAGE_SIZE / CNIC_KWQ16_DATA_SIZE;
  993. for (i = 0, j = 0; i < cp->max_cid_space; i++) {
  994. long off = CNIC_KWQ16_DATA_SIZE * (i % n);
  995. cp->ctx_tbl[i].kwqe_data = kwq_16_dma->pg_arr[j] + off;
  996. cp->ctx_tbl[i].kwqe_data_mapping = kwq_16_dma->pg_map_arr[j] +
  997. off;
  998. if ((i % n) == (n - 1))
  999. j++;
  1000. }
  1001. ret = cnic_alloc_kcq(dev, &cp->kcq1, false);
  1002. if (ret)
  1003. goto error;
  1004. if (BNX2X_CHIP_IS_E2_PLUS(cp->chip_id)) {
  1005. ret = cnic_alloc_kcq(dev, &cp->kcq2, true);
  1006. if (ret)
  1007. goto error;
  1008. }
  1009. pages = PAGE_ALIGN(BNX2X_ISCSI_GLB_BUF_SIZE) / PAGE_SIZE;
  1010. ret = cnic_alloc_dma(dev, &cp->gbl_buf_info, pages, 0);
  1011. if (ret)
  1012. goto error;
  1013. ret = cnic_alloc_bnx2x_context(dev);
  1014. if (ret)
  1015. goto error;
  1016. cp->bnx2x_def_status_blk = cp->ethdev->irq_arr[1].status_blk;
  1017. cp->l2_rx_ring_size = 15;
  1018. ret = cnic_alloc_uio_rings(dev, 4);
  1019. if (ret)
  1020. goto error;
  1021. ret = cnic_init_uio(dev);
  1022. if (ret)
  1023. goto error;
  1024. return 0;
  1025. error:
  1026. cnic_free_resc(dev);
  1027. return -ENOMEM;
  1028. }
  1029. static inline u32 cnic_kwq_avail(struct cnic_local *cp)
  1030. {
  1031. return cp->max_kwq_idx -
  1032. ((cp->kwq_prod_idx - cp->kwq_con_idx) & cp->max_kwq_idx);
  1033. }
  1034. static int cnic_submit_bnx2_kwqes(struct cnic_dev *dev, struct kwqe *wqes[],
  1035. u32 num_wqes)
  1036. {
  1037. struct cnic_local *cp = dev->cnic_priv;
  1038. struct kwqe *prod_qe;
  1039. u16 prod, sw_prod, i;
  1040. if (!test_bit(CNIC_F_CNIC_UP, &dev->flags))
  1041. return -EAGAIN; /* bnx2 is down */
  1042. spin_lock_bh(&cp->cnic_ulp_lock);
  1043. if (num_wqes > cnic_kwq_avail(cp) &&
  1044. !test_bit(CNIC_LCL_FL_KWQ_INIT, &cp->cnic_local_flags)) {
  1045. spin_unlock_bh(&cp->cnic_ulp_lock);
  1046. return -EAGAIN;
  1047. }
  1048. clear_bit(CNIC_LCL_FL_KWQ_INIT, &cp->cnic_local_flags);
  1049. prod = cp->kwq_prod_idx;
  1050. sw_prod = prod & MAX_KWQ_IDX;
  1051. for (i = 0; i < num_wqes; i++) {
  1052. prod_qe = &cp->kwq[KWQ_PG(sw_prod)][KWQ_IDX(sw_prod)];
  1053. memcpy(prod_qe, wqes[i], sizeof(struct kwqe));
  1054. prod++;
  1055. sw_prod = prod & MAX_KWQ_IDX;
  1056. }
  1057. cp->kwq_prod_idx = prod;
  1058. CNIC_WR16(dev, cp->kwq_io_addr, cp->kwq_prod_idx);
  1059. spin_unlock_bh(&cp->cnic_ulp_lock);
  1060. return 0;
  1061. }
  1062. static void *cnic_get_kwqe_16_data(struct cnic_local *cp, u32 l5_cid,
  1063. union l5cm_specific_data *l5_data)
  1064. {
  1065. struct cnic_context *ctx = &cp->ctx_tbl[l5_cid];
  1066. dma_addr_t map;
  1067. map = ctx->kwqe_data_mapping;
  1068. l5_data->phy_address.lo = (u64) map & 0xffffffff;
  1069. l5_data->phy_address.hi = (u64) map >> 32;
  1070. return ctx->kwqe_data;
  1071. }
  1072. static int cnic_submit_kwqe_16(struct cnic_dev *dev, u32 cmd, u32 cid,
  1073. u32 type, union l5cm_specific_data *l5_data)
  1074. {
  1075. struct cnic_local *cp = dev->cnic_priv;
  1076. struct l5cm_spe kwqe;
  1077. struct kwqe_16 *kwq[1];
  1078. u16 type_16;
  1079. int ret;
  1080. kwqe.hdr.conn_and_cmd_data =
  1081. cpu_to_le32(((cmd << SPE_HDR_CMD_ID_SHIFT) |
  1082. BNX2X_HW_CID(cp, cid)));
  1083. type_16 = (type << SPE_HDR_CONN_TYPE_SHIFT) & SPE_HDR_CONN_TYPE;
  1084. type_16 |= (cp->pfid << SPE_HDR_FUNCTION_ID_SHIFT) &
  1085. SPE_HDR_FUNCTION_ID;
  1086. kwqe.hdr.type = cpu_to_le16(type_16);
  1087. kwqe.hdr.reserved1 = 0;
  1088. kwqe.data.phy_address.lo = cpu_to_le32(l5_data->phy_address.lo);
  1089. kwqe.data.phy_address.hi = cpu_to_le32(l5_data->phy_address.hi);
  1090. kwq[0] = (struct kwqe_16 *) &kwqe;
  1091. spin_lock_bh(&cp->cnic_ulp_lock);
  1092. ret = cp->ethdev->drv_submit_kwqes_16(dev->netdev, kwq, 1);
  1093. spin_unlock_bh(&cp->cnic_ulp_lock);
  1094. if (ret == 1)
  1095. return 0;
  1096. return -EBUSY;
  1097. }
  1098. static void cnic_reply_bnx2x_kcqes(struct cnic_dev *dev, int ulp_type,
  1099. struct kcqe *cqes[], u32 num_cqes)
  1100. {
  1101. struct cnic_local *cp = dev->cnic_priv;
  1102. struct cnic_ulp_ops *ulp_ops;
  1103. rcu_read_lock();
  1104. ulp_ops = rcu_dereference(cp->ulp_ops[ulp_type]);
  1105. if (likely(ulp_ops)) {
  1106. ulp_ops->indicate_kcqes(cp->ulp_handle[ulp_type],
  1107. cqes, num_cqes);
  1108. }
  1109. rcu_read_unlock();
  1110. }
  1111. static int cnic_bnx2x_iscsi_init1(struct cnic_dev *dev, struct kwqe *kwqe)
  1112. {
  1113. struct cnic_local *cp = dev->cnic_priv;
  1114. struct iscsi_kwqe_init1 *req1 = (struct iscsi_kwqe_init1 *) kwqe;
  1115. int hq_bds, pages;
  1116. u32 pfid = cp->pfid;
  1117. cp->num_iscsi_tasks = req1->num_tasks_per_conn;
  1118. cp->num_ccells = req1->num_ccells_per_conn;
  1119. cp->task_array_size = BNX2X_ISCSI_TASK_CONTEXT_SIZE *
  1120. cp->num_iscsi_tasks;
  1121. cp->r2tq_size = cp->num_iscsi_tasks * BNX2X_ISCSI_MAX_PENDING_R2TS *
  1122. BNX2X_ISCSI_R2TQE_SIZE;
  1123. cp->hq_size = cp->num_ccells * BNX2X_ISCSI_HQ_BD_SIZE;
  1124. pages = PAGE_ALIGN(cp->hq_size) / PAGE_SIZE;
  1125. hq_bds = pages * (PAGE_SIZE / BNX2X_ISCSI_HQ_BD_SIZE);
  1126. cp->num_cqs = req1->num_cqs;
  1127. if (!dev->max_iscsi_conn)
  1128. return 0;
  1129. /* init Tstorm RAM */
  1130. CNIC_WR16(dev, BAR_TSTRORM_INTMEM + TSTORM_ISCSI_RQ_SIZE_OFFSET(pfid),
  1131. req1->rq_num_wqes);
  1132. CNIC_WR16(dev, BAR_TSTRORM_INTMEM + TSTORM_ISCSI_PAGE_SIZE_OFFSET(pfid),
  1133. PAGE_SIZE);
  1134. CNIC_WR8(dev, BAR_TSTRORM_INTMEM +
  1135. TSTORM_ISCSI_PAGE_SIZE_LOG_OFFSET(pfid), PAGE_SHIFT);
  1136. CNIC_WR16(dev, BAR_TSTRORM_INTMEM +
  1137. TSTORM_ISCSI_NUM_OF_TASKS_OFFSET(pfid),
  1138. req1->num_tasks_per_conn);
  1139. /* init Ustorm RAM */
  1140. CNIC_WR16(dev, BAR_USTRORM_INTMEM +
  1141. USTORM_ISCSI_RQ_BUFFER_SIZE_OFFSET(pfid),
  1142. req1->rq_buffer_size);
  1143. CNIC_WR16(dev, BAR_USTRORM_INTMEM + USTORM_ISCSI_PAGE_SIZE_OFFSET(pfid),
  1144. PAGE_SIZE);
  1145. CNIC_WR8(dev, BAR_USTRORM_INTMEM +
  1146. USTORM_ISCSI_PAGE_SIZE_LOG_OFFSET(pfid), PAGE_SHIFT);
  1147. CNIC_WR16(dev, BAR_USTRORM_INTMEM +
  1148. USTORM_ISCSI_NUM_OF_TASKS_OFFSET(pfid),
  1149. req1->num_tasks_per_conn);
  1150. CNIC_WR16(dev, BAR_USTRORM_INTMEM + USTORM_ISCSI_RQ_SIZE_OFFSET(pfid),
  1151. req1->rq_num_wqes);
  1152. CNIC_WR16(dev, BAR_USTRORM_INTMEM + USTORM_ISCSI_CQ_SIZE_OFFSET(pfid),
  1153. req1->cq_num_wqes);
  1154. CNIC_WR16(dev, BAR_USTRORM_INTMEM + USTORM_ISCSI_R2TQ_SIZE_OFFSET(pfid),
  1155. cp->num_iscsi_tasks * BNX2X_ISCSI_MAX_PENDING_R2TS);
  1156. /* init Xstorm RAM */
  1157. CNIC_WR16(dev, BAR_XSTRORM_INTMEM + XSTORM_ISCSI_PAGE_SIZE_OFFSET(pfid),
  1158. PAGE_SIZE);
  1159. CNIC_WR8(dev, BAR_XSTRORM_INTMEM +
  1160. XSTORM_ISCSI_PAGE_SIZE_LOG_OFFSET(pfid), PAGE_SHIFT);
  1161. CNIC_WR16(dev, BAR_XSTRORM_INTMEM +
  1162. XSTORM_ISCSI_NUM_OF_TASKS_OFFSET(pfid),
  1163. req1->num_tasks_per_conn);
  1164. CNIC_WR16(dev, BAR_XSTRORM_INTMEM + XSTORM_ISCSI_HQ_SIZE_OFFSET(pfid),
  1165. hq_bds);
  1166. CNIC_WR16(dev, BAR_XSTRORM_INTMEM + XSTORM_ISCSI_SQ_SIZE_OFFSET(pfid),
  1167. req1->num_tasks_per_conn);
  1168. CNIC_WR16(dev, BAR_XSTRORM_INTMEM + XSTORM_ISCSI_R2TQ_SIZE_OFFSET(pfid),
  1169. cp->num_iscsi_tasks * BNX2X_ISCSI_MAX_PENDING_R2TS);
  1170. /* init Cstorm RAM */
  1171. CNIC_WR16(dev, BAR_CSTRORM_INTMEM + CSTORM_ISCSI_PAGE_SIZE_OFFSET(pfid),
  1172. PAGE_SIZE);
  1173. CNIC_WR8(dev, BAR_CSTRORM_INTMEM +
  1174. CSTORM_ISCSI_PAGE_SIZE_LOG_OFFSET(pfid), PAGE_SHIFT);
  1175. CNIC_WR16(dev, BAR_CSTRORM_INTMEM +
  1176. CSTORM_ISCSI_NUM_OF_TASKS_OFFSET(pfid),
  1177. req1->num_tasks_per_conn);
  1178. CNIC_WR16(dev, BAR_CSTRORM_INTMEM + CSTORM_ISCSI_CQ_SIZE_OFFSET(pfid),
  1179. req1->cq_num_wqes);
  1180. CNIC_WR16(dev, BAR_CSTRORM_INTMEM + CSTORM_ISCSI_HQ_SIZE_OFFSET(pfid),
  1181. hq_bds);
  1182. return 0;
  1183. }
  1184. static int cnic_bnx2x_iscsi_init2(struct cnic_dev *dev, struct kwqe *kwqe)
  1185. {
  1186. struct iscsi_kwqe_init2 *req2 = (struct iscsi_kwqe_init2 *) kwqe;
  1187. struct cnic_local *cp = dev->cnic_priv;
  1188. u32 pfid = cp->pfid;
  1189. struct iscsi_kcqe kcqe;
  1190. struct kcqe *cqes[1];
  1191. memset(&kcqe, 0, sizeof(kcqe));
  1192. if (!dev->max_iscsi_conn) {
  1193. kcqe.completion_status =
  1194. ISCSI_KCQE_COMPLETION_STATUS_ISCSI_NOT_SUPPORTED;
  1195. goto done;
  1196. }
  1197. CNIC_WR(dev, BAR_TSTRORM_INTMEM +
  1198. TSTORM_ISCSI_ERROR_BITMAP_OFFSET(pfid), req2->error_bit_map[0]);
  1199. CNIC_WR(dev, BAR_TSTRORM_INTMEM +
  1200. TSTORM_ISCSI_ERROR_BITMAP_OFFSET(pfid) + 4,
  1201. req2->error_bit_map[1]);
  1202. CNIC_WR16(dev, BAR_USTRORM_INTMEM +
  1203. USTORM_ISCSI_CQ_SQN_SIZE_OFFSET(pfid), req2->max_cq_sqn);
  1204. CNIC_WR(dev, BAR_USTRORM_INTMEM +
  1205. USTORM_ISCSI_ERROR_BITMAP_OFFSET(pfid), req2->error_bit_map[0]);
  1206. CNIC_WR(dev, BAR_USTRORM_INTMEM +
  1207. USTORM_ISCSI_ERROR_BITMAP_OFFSET(pfid) + 4,
  1208. req2->error_bit_map[1]);
  1209. CNIC_WR16(dev, BAR_CSTRORM_INTMEM +
  1210. CSTORM_ISCSI_CQ_SQN_SIZE_OFFSET(pfid), req2->max_cq_sqn);
  1211. kcqe.completion_status = ISCSI_KCQE_COMPLETION_STATUS_SUCCESS;
  1212. done:
  1213. kcqe.op_code = ISCSI_KCQE_OPCODE_INIT;
  1214. cqes[0] = (struct kcqe *) &kcqe;
  1215. cnic_reply_bnx2x_kcqes(dev, CNIC_ULP_ISCSI, cqes, 1);
  1216. return 0;
  1217. }
  1218. static void cnic_free_bnx2x_conn_resc(struct cnic_dev *dev, u32 l5_cid)
  1219. {
  1220. struct cnic_local *cp = dev->cnic_priv;
  1221. struct cnic_context *ctx = &cp->ctx_tbl[l5_cid];
  1222. if (ctx->ulp_proto_id == CNIC_ULP_ISCSI) {
  1223. struct cnic_iscsi *iscsi = ctx->proto.iscsi;
  1224. cnic_free_dma(dev, &iscsi->hq_info);
  1225. cnic_free_dma(dev, &iscsi->r2tq_info);
  1226. cnic_free_dma(dev, &iscsi->task_array_info);
  1227. cnic_free_id(&cp->cid_tbl, ctx->cid);
  1228. } else {
  1229. cnic_free_id(&cp->fcoe_cid_tbl, ctx->cid);
  1230. }
  1231. ctx->cid = 0;
  1232. }
  1233. static int cnic_alloc_bnx2x_conn_resc(struct cnic_dev *dev, u32 l5_cid)
  1234. {
  1235. u32 cid;
  1236. int ret, pages;
  1237. struct cnic_local *cp = dev->cnic_priv;
  1238. struct cnic_context *ctx = &cp->ctx_tbl[l5_cid];
  1239. struct cnic_iscsi *iscsi = ctx->proto.iscsi;
  1240. if (ctx->ulp_proto_id == CNIC_ULP_FCOE) {
  1241. cid = cnic_alloc_new_id(&cp->fcoe_cid_tbl);
  1242. if (cid == -1) {
  1243. ret = -ENOMEM;
  1244. goto error;
  1245. }
  1246. ctx->cid = cid;
  1247. return 0;
  1248. }
  1249. cid = cnic_alloc_new_id(&cp->cid_tbl);
  1250. if (cid == -1) {
  1251. ret = -ENOMEM;
  1252. goto error;
  1253. }
  1254. ctx->cid = cid;
  1255. pages = PAGE_ALIGN(cp->task_array_size) / PAGE_SIZE;
  1256. ret = cnic_alloc_dma(dev, &iscsi->task_array_info, pages, 1);
  1257. if (ret)
  1258. goto error;
  1259. pages = PAGE_ALIGN(cp->r2tq_size) / PAGE_SIZE;
  1260. ret = cnic_alloc_dma(dev, &iscsi->r2tq_info, pages, 1);
  1261. if (ret)
  1262. goto error;
  1263. pages = PAGE_ALIGN(cp->hq_size) / PAGE_SIZE;
  1264. ret = cnic_alloc_dma(dev, &iscsi->hq_info, pages, 1);
  1265. if (ret)
  1266. goto error;
  1267. return 0;
  1268. error:
  1269. cnic_free_bnx2x_conn_resc(dev, l5_cid);
  1270. return ret;
  1271. }
  1272. static void *cnic_get_bnx2x_ctx(struct cnic_dev *dev, u32 cid, int init,
  1273. struct regpair *ctx_addr)
  1274. {
  1275. struct cnic_local *cp = dev->cnic_priv;
  1276. struct cnic_eth_dev *ethdev = cp->ethdev;
  1277. int blk = (cid - ethdev->starting_cid) / cp->cids_per_blk;
  1278. int off = (cid - ethdev->starting_cid) % cp->cids_per_blk;
  1279. unsigned long align_off = 0;
  1280. dma_addr_t ctx_map;
  1281. void *ctx;
  1282. if (cp->ctx_align) {
  1283. unsigned long mask = cp->ctx_align - 1;
  1284. if (cp->ctx_arr[blk].mapping & mask)
  1285. align_off = cp->ctx_align -
  1286. (cp->ctx_arr[blk].mapping & mask);
  1287. }
  1288. ctx_map = cp->ctx_arr[blk].mapping + align_off +
  1289. (off * BNX2X_CONTEXT_MEM_SIZE);
  1290. ctx = cp->ctx_arr[blk].ctx + align_off +
  1291. (off * BNX2X_CONTEXT_MEM_SIZE);
  1292. if (init)
  1293. memset(ctx, 0, BNX2X_CONTEXT_MEM_SIZE);
  1294. ctx_addr->lo = ctx_map & 0xffffffff;
  1295. ctx_addr->hi = (u64) ctx_map >> 32;
  1296. return ctx;
  1297. }
  1298. static int cnic_setup_bnx2x_ctx(struct cnic_dev *dev, struct kwqe *wqes[],
  1299. u32 num)
  1300. {
  1301. struct cnic_local *cp = dev->cnic_priv;
  1302. struct iscsi_kwqe_conn_offload1 *req1 =
  1303. (struct iscsi_kwqe_conn_offload1 *) wqes[0];
  1304. struct iscsi_kwqe_conn_offload2 *req2 =
  1305. (struct iscsi_kwqe_conn_offload2 *) wqes[1];
  1306. struct iscsi_kwqe_conn_offload3 *req3;
  1307. struct cnic_context *ctx = &cp->ctx_tbl[req1->iscsi_conn_id];
  1308. struct cnic_iscsi *iscsi = ctx->proto.iscsi;
  1309. u32 cid = ctx->cid;
  1310. u32 hw_cid = BNX2X_HW_CID(cp, cid);
  1311. struct iscsi_context *ictx;
  1312. struct regpair context_addr;
  1313. int i, j, n = 2, n_max;
  1314. u8 port = CNIC_PORT(cp);
  1315. ctx->ctx_flags = 0;
  1316. if (!req2->num_additional_wqes)
  1317. return -EINVAL;
  1318. n_max = req2->num_additional_wqes + 2;
  1319. ictx = cnic_get_bnx2x_ctx(dev, cid, 1, &context_addr);
  1320. if (ictx == NULL)
  1321. return -ENOMEM;
  1322. req3 = (struct iscsi_kwqe_conn_offload3 *) wqes[n++];
  1323. ictx->xstorm_ag_context.hq_prod = 1;
  1324. ictx->xstorm_st_context.iscsi.first_burst_length =
  1325. ISCSI_DEF_FIRST_BURST_LEN;
  1326. ictx->xstorm_st_context.iscsi.max_send_pdu_length =
  1327. ISCSI_DEF_MAX_RECV_SEG_LEN;
  1328. ictx->xstorm_st_context.iscsi.sq_pbl_base.lo =
  1329. req1->sq_page_table_addr_lo;
  1330. ictx->xstorm_st_context.iscsi.sq_pbl_base.hi =
  1331. req1->sq_page_table_addr_hi;
  1332. ictx->xstorm_st_context.iscsi.sq_curr_pbe.lo = req2->sq_first_pte.hi;
  1333. ictx->xstorm_st_context.iscsi.sq_curr_pbe.hi = req2->sq_first_pte.lo;
  1334. ictx->xstorm_st_context.iscsi.hq_pbl_base.lo =
  1335. iscsi->hq_info.pgtbl_map & 0xffffffff;
  1336. ictx->xstorm_st_context.iscsi.hq_pbl_base.hi =
  1337. (u64) iscsi->hq_info.pgtbl_map >> 32;
  1338. ictx->xstorm_st_context.iscsi.hq_curr_pbe_base.lo =
  1339. iscsi->hq_info.pgtbl[0];
  1340. ictx->xstorm_st_context.iscsi.hq_curr_pbe_base.hi =
  1341. iscsi->hq_info.pgtbl[1];
  1342. ictx->xstorm_st_context.iscsi.r2tq_pbl_base.lo =
  1343. iscsi->r2tq_info.pgtbl_map & 0xffffffff;
  1344. ictx->xstorm_st_context.iscsi.r2tq_pbl_base.hi =
  1345. (u64) iscsi->r2tq_info.pgtbl_map >> 32;
  1346. ictx->xstorm_st_context.iscsi.r2tq_curr_pbe_base.lo =
  1347. iscsi->r2tq_info.pgtbl[0];
  1348. ictx->xstorm_st_context.iscsi.r2tq_curr_pbe_base.hi =
  1349. iscsi->r2tq_info.pgtbl[1];
  1350. ictx->xstorm_st_context.iscsi.task_pbl_base.lo =
  1351. iscsi->task_array_info.pgtbl_map & 0xffffffff;
  1352. ictx->xstorm_st_context.iscsi.task_pbl_base.hi =
  1353. (u64) iscsi->task_array_info.pgtbl_map >> 32;
  1354. ictx->xstorm_st_context.iscsi.task_pbl_cache_idx =
  1355. BNX2X_ISCSI_PBL_NOT_CACHED;
  1356. ictx->xstorm_st_context.iscsi.flags.flags |=
  1357. XSTORM_ISCSI_CONTEXT_FLAGS_B_IMMEDIATE_DATA;
  1358. ictx->xstorm_st_context.iscsi.flags.flags |=
  1359. XSTORM_ISCSI_CONTEXT_FLAGS_B_INITIAL_R2T;
  1360. ictx->xstorm_st_context.common.ethernet.reserved_vlan_type =
  1361. ETH_P_8021Q;
  1362. if (BNX2X_CHIP_IS_E2_PLUS(cp->chip_id) &&
  1363. cp->port_mode == CHIP_2_PORT_MODE) {
  1364. port = 0;
  1365. }
  1366. ictx->xstorm_st_context.common.flags =
  1367. 1 << XSTORM_COMMON_CONTEXT_SECTION_PHYSQ_INITIALIZED_SHIFT;
  1368. ictx->xstorm_st_context.common.flags =
  1369. port << XSTORM_COMMON_CONTEXT_SECTION_PBF_PORT_SHIFT;
  1370. ictx->tstorm_st_context.iscsi.hdr_bytes_2_fetch = ISCSI_HEADER_SIZE;
  1371. /* TSTORM requires the base address of RQ DB & not PTE */
  1372. ictx->tstorm_st_context.iscsi.rq_db_phy_addr.lo =
  1373. req2->rq_page_table_addr_lo & PAGE_MASK;
  1374. ictx->tstorm_st_context.iscsi.rq_db_phy_addr.hi =
  1375. req2->rq_page_table_addr_hi;
  1376. ictx->tstorm_st_context.iscsi.iscsi_conn_id = req1->iscsi_conn_id;
  1377. ictx->tstorm_st_context.tcp.cwnd = 0x5A8;
  1378. ictx->tstorm_st_context.tcp.flags2 |=
  1379. TSTORM_TCP_ST_CONTEXT_SECTION_DA_EN;
  1380. ictx->tstorm_st_context.tcp.ooo_support_mode =
  1381. TCP_TSTORM_OOO_DROP_AND_PROC_ACK;
  1382. ictx->timers_context.flags |= TIMERS_BLOCK_CONTEXT_CONN_VALID_FLG;
  1383. ictx->ustorm_st_context.ring.rq.pbl_base.lo =
  1384. req2->rq_page_table_addr_lo;
  1385. ictx->ustorm_st_context.ring.rq.pbl_base.hi =
  1386. req2->rq_page_table_addr_hi;
  1387. ictx->ustorm_st_context.ring.rq.curr_pbe.lo = req3->qp_first_pte[0].hi;
  1388. ictx->ustorm_st_context.ring.rq.curr_pbe.hi = req3->qp_first_pte[0].lo;
  1389. ictx->ustorm_st_context.ring.r2tq.pbl_base.lo =
  1390. iscsi->r2tq_info.pgtbl_map & 0xffffffff;
  1391. ictx->ustorm_st_context.ring.r2tq.pbl_base.hi =
  1392. (u64) iscsi->r2tq_info.pgtbl_map >> 32;
  1393. ictx->ustorm_st_context.ring.r2tq.curr_pbe.lo =
  1394. iscsi->r2tq_info.pgtbl[0];
  1395. ictx->ustorm_st_context.ring.r2tq.curr_pbe.hi =
  1396. iscsi->r2tq_info.pgtbl[1];
  1397. ictx->ustorm_st_context.ring.cq_pbl_base.lo =
  1398. req1->cq_page_table_addr_lo;
  1399. ictx->ustorm_st_context.ring.cq_pbl_base.hi =
  1400. req1->cq_page_table_addr_hi;
  1401. ictx->ustorm_st_context.ring.cq[0].cq_sn = ISCSI_INITIAL_SN;
  1402. ictx->ustorm_st_context.ring.cq[0].curr_pbe.lo = req2->cq_first_pte.hi;
  1403. ictx->ustorm_st_context.ring.cq[0].curr_pbe.hi = req2->cq_first_pte.lo;
  1404. ictx->ustorm_st_context.task_pbe_cache_index =
  1405. BNX2X_ISCSI_PBL_NOT_CACHED;
  1406. ictx->ustorm_st_context.task_pdu_cache_index =
  1407. BNX2X_ISCSI_PDU_HEADER_NOT_CACHED;
  1408. for (i = 1, j = 1; i < cp->num_cqs; i++, j++) {
  1409. if (j == 3) {
  1410. if (n >= n_max)
  1411. break;
  1412. req3 = (struct iscsi_kwqe_conn_offload3 *) wqes[n++];
  1413. j = 0;
  1414. }
  1415. ictx->ustorm_st_context.ring.cq[i].cq_sn = ISCSI_INITIAL_SN;
  1416. ictx->ustorm_st_context.ring.cq[i].curr_pbe.lo =
  1417. req3->qp_first_pte[j].hi;
  1418. ictx->ustorm_st_context.ring.cq[i].curr_pbe.hi =
  1419. req3->qp_first_pte[j].lo;
  1420. }
  1421. ictx->ustorm_st_context.task_pbl_base.lo =
  1422. iscsi->task_array_info.pgtbl_map & 0xffffffff;
  1423. ictx->ustorm_st_context.task_pbl_base.hi =
  1424. (u64) iscsi->task_array_info.pgtbl_map >> 32;
  1425. ictx->ustorm_st_context.tce_phy_addr.lo =
  1426. iscsi->task_array_info.pgtbl[0];
  1427. ictx->ustorm_st_context.tce_phy_addr.hi =
  1428. iscsi->task_array_info.pgtbl[1];
  1429. ictx->ustorm_st_context.iscsi_conn_id = req1->iscsi_conn_id;
  1430. ictx->ustorm_st_context.num_cqs = cp->num_cqs;
  1431. ictx->ustorm_st_context.negotiated_rx |= ISCSI_DEF_MAX_RECV_SEG_LEN;
  1432. ictx->ustorm_st_context.negotiated_rx_and_flags |=
  1433. ISCSI_DEF_MAX_BURST_LEN;
  1434. ictx->ustorm_st_context.negotiated_rx |=
  1435. ISCSI_DEFAULT_MAX_OUTSTANDING_R2T <<
  1436. USTORM_ISCSI_ST_CONTEXT_MAX_OUTSTANDING_R2TS_SHIFT;
  1437. ictx->cstorm_st_context.hq_pbl_base.lo =
  1438. iscsi->hq_info.pgtbl_map & 0xffffffff;
  1439. ictx->cstorm_st_context.hq_pbl_base.hi =
  1440. (u64) iscsi->hq_info.pgtbl_map >> 32;
  1441. ictx->cstorm_st_context.hq_curr_pbe.lo = iscsi->hq_info.pgtbl[0];
  1442. ictx->cstorm_st_context.hq_curr_pbe.hi = iscsi->hq_info.pgtbl[1];
  1443. ictx->cstorm_st_context.task_pbl_base.lo =
  1444. iscsi->task_array_info.pgtbl_map & 0xffffffff;
  1445. ictx->cstorm_st_context.task_pbl_base.hi =
  1446. (u64) iscsi->task_array_info.pgtbl_map >> 32;
  1447. /* CSTORM and USTORM initialization is different, CSTORM requires
  1448. * CQ DB base & not PTE addr */
  1449. ictx->cstorm_st_context.cq_db_base.lo =
  1450. req1->cq_page_table_addr_lo & PAGE_MASK;
  1451. ictx->cstorm_st_context.cq_db_base.hi = req1->cq_page_table_addr_hi;
  1452. ictx->cstorm_st_context.iscsi_conn_id = req1->iscsi_conn_id;
  1453. ictx->cstorm_st_context.cq_proc_en_bit_map = (1 << cp->num_cqs) - 1;
  1454. for (i = 0; i < cp->num_cqs; i++) {
  1455. ictx->cstorm_st_context.cq_c_prod_sqn_arr.sqn[i] =
  1456. ISCSI_INITIAL_SN;
  1457. ictx->cstorm_st_context.cq_c_sqn_2_notify_arr.sqn[i] =
  1458. ISCSI_INITIAL_SN;
  1459. }
  1460. ictx->xstorm_ag_context.cdu_reserved =
  1461. CDU_RSRVD_VALUE_TYPE_A(hw_cid, CDU_REGION_NUMBER_XCM_AG,
  1462. ISCSI_CONNECTION_TYPE);
  1463. ictx->ustorm_ag_context.cdu_usage =
  1464. CDU_RSRVD_VALUE_TYPE_A(hw_cid, CDU_REGION_NUMBER_UCM_AG,
  1465. ISCSI_CONNECTION_TYPE);
  1466. return 0;
  1467. }
  1468. static int cnic_bnx2x_iscsi_ofld1(struct cnic_dev *dev, struct kwqe *wqes[],
  1469. u32 num, int *work)
  1470. {
  1471. struct iscsi_kwqe_conn_offload1 *req1;
  1472. struct iscsi_kwqe_conn_offload2 *req2;
  1473. struct cnic_local *cp = dev->cnic_priv;
  1474. struct cnic_context *ctx;
  1475. struct iscsi_kcqe kcqe;
  1476. struct kcqe *cqes[1];
  1477. u32 l5_cid;
  1478. int ret = 0;
  1479. if (num < 2) {
  1480. *work = num;
  1481. return -EINVAL;
  1482. }
  1483. req1 = (struct iscsi_kwqe_conn_offload1 *) wqes[0];
  1484. req2 = (struct iscsi_kwqe_conn_offload2 *) wqes[1];
  1485. if ((num - 2) < req2->num_additional_wqes) {
  1486. *work = num;
  1487. return -EINVAL;
  1488. }
  1489. *work = 2 + req2->num_additional_wqes;
  1490. l5_cid = req1->iscsi_conn_id;
  1491. if (l5_cid >= MAX_ISCSI_TBL_SZ)
  1492. return -EINVAL;
  1493. memset(&kcqe, 0, sizeof(kcqe));
  1494. kcqe.op_code = ISCSI_KCQE_OPCODE_OFFLOAD_CONN;
  1495. kcqe.iscsi_conn_id = l5_cid;
  1496. kcqe.completion_status = ISCSI_KCQE_COMPLETION_STATUS_CTX_ALLOC_FAILURE;
  1497. ctx = &cp->ctx_tbl[l5_cid];
  1498. if (test_bit(CTX_FL_OFFLD_START, &ctx->ctx_flags)) {
  1499. kcqe.completion_status =
  1500. ISCSI_KCQE_COMPLETION_STATUS_CID_BUSY;
  1501. goto done;
  1502. }
  1503. if (atomic_inc_return(&cp->iscsi_conn) > dev->max_iscsi_conn) {
  1504. atomic_dec(&cp->iscsi_conn);
  1505. goto done;
  1506. }
  1507. ret = cnic_alloc_bnx2x_conn_resc(dev, l5_cid);
  1508. if (ret) {
  1509. atomic_dec(&cp->iscsi_conn);
  1510. ret = 0;
  1511. goto done;
  1512. }
  1513. ret = cnic_setup_bnx2x_ctx(dev, wqes, num);
  1514. if (ret < 0) {
  1515. cnic_free_bnx2x_conn_resc(dev, l5_cid);
  1516. atomic_dec(&cp->iscsi_conn);
  1517. goto done;
  1518. }
  1519. kcqe.completion_status = ISCSI_KCQE_COMPLETION_STATUS_SUCCESS;
  1520. kcqe.iscsi_conn_context_id = BNX2X_HW_CID(cp, cp->ctx_tbl[l5_cid].cid);
  1521. done:
  1522. cqes[0] = (struct kcqe *) &kcqe;
  1523. cnic_reply_bnx2x_kcqes(dev, CNIC_ULP_ISCSI, cqes, 1);
  1524. return ret;
  1525. }
  1526. static int cnic_bnx2x_iscsi_update(struct cnic_dev *dev, struct kwqe *kwqe)
  1527. {
  1528. struct cnic_local *cp = dev->cnic_priv;
  1529. struct iscsi_kwqe_conn_update *req =
  1530. (struct iscsi_kwqe_conn_update *) kwqe;
  1531. void *data;
  1532. union l5cm_specific_data l5_data;
  1533. u32 l5_cid, cid = BNX2X_SW_CID(req->context_id);
  1534. int ret;
  1535. if (cnic_get_l5_cid(cp, cid, &l5_cid) != 0)
  1536. return -EINVAL;
  1537. data = cnic_get_kwqe_16_data(cp, l5_cid, &l5_data);
  1538. if (!data)
  1539. return -ENOMEM;
  1540. memcpy(data, kwqe, sizeof(struct kwqe));
  1541. ret = cnic_submit_kwqe_16(dev, ISCSI_RAMROD_CMD_ID_UPDATE_CONN,
  1542. req->context_id, ISCSI_CONNECTION_TYPE, &l5_data);
  1543. return ret;
  1544. }
  1545. static int cnic_bnx2x_destroy_ramrod(struct cnic_dev *dev, u32 l5_cid)
  1546. {
  1547. struct cnic_local *cp = dev->cnic_priv;
  1548. struct cnic_context *ctx = &cp->ctx_tbl[l5_cid];
  1549. union l5cm_specific_data l5_data;
  1550. int ret;
  1551. u32 hw_cid;
  1552. init_waitqueue_head(&ctx->waitq);
  1553. ctx->wait_cond = 0;
  1554. memset(&l5_data, 0, sizeof(l5_data));
  1555. hw_cid = BNX2X_HW_CID(cp, ctx->cid);
  1556. ret = cnic_submit_kwqe_16(dev, RAMROD_CMD_ID_COMMON_CFC_DEL,
  1557. hw_cid, NONE_CONNECTION_TYPE, &l5_data);
  1558. if (ret == 0) {
  1559. wait_event_timeout(ctx->waitq, ctx->wait_cond, CNIC_RAMROD_TMO);
  1560. if (unlikely(test_bit(CTX_FL_CID_ERROR, &ctx->ctx_flags)))
  1561. return -EBUSY;
  1562. }
  1563. return 0;
  1564. }
  1565. static int cnic_bnx2x_iscsi_destroy(struct cnic_dev *dev, struct kwqe *kwqe)
  1566. {
  1567. struct cnic_local *cp = dev->cnic_priv;
  1568. struct iscsi_kwqe_conn_destroy *req =
  1569. (struct iscsi_kwqe_conn_destroy *) kwqe;
  1570. u32 l5_cid = req->reserved0;
  1571. struct cnic_context *ctx = &cp->ctx_tbl[l5_cid];
  1572. int ret = 0;
  1573. struct iscsi_kcqe kcqe;
  1574. struct kcqe *cqes[1];
  1575. if (!test_bit(CTX_FL_OFFLD_START, &ctx->ctx_flags))
  1576. goto skip_cfc_delete;
  1577. if (!time_after(jiffies, ctx->timestamp + (2 * HZ))) {
  1578. unsigned long delta = ctx->timestamp + (2 * HZ) - jiffies;
  1579. if (delta > (2 * HZ))
  1580. delta = 0;
  1581. set_bit(CTX_FL_DELETE_WAIT, &ctx->ctx_flags);
  1582. queue_delayed_work(cnic_wq, &cp->delete_task, delta);
  1583. goto destroy_reply;
  1584. }
  1585. ret = cnic_bnx2x_destroy_ramrod(dev, l5_cid);
  1586. skip_cfc_delete:
  1587. cnic_free_bnx2x_conn_resc(dev, l5_cid);
  1588. if (!ret) {
  1589. atomic_dec(&cp->iscsi_conn);
  1590. clear_bit(CTX_FL_OFFLD_START, &ctx->ctx_flags);
  1591. }
  1592. destroy_reply:
  1593. memset(&kcqe, 0, sizeof(kcqe));
  1594. kcqe.op_code = ISCSI_KCQE_OPCODE_DESTROY_CONN;
  1595. kcqe.iscsi_conn_id = l5_cid;
  1596. kcqe.completion_status = ISCSI_KCQE_COMPLETION_STATUS_SUCCESS;
  1597. kcqe.iscsi_conn_context_id = req->context_id;
  1598. cqes[0] = (struct kcqe *) &kcqe;
  1599. cnic_reply_bnx2x_kcqes(dev, CNIC_ULP_ISCSI, cqes, 1);
  1600. return ret;
  1601. }
  1602. static void cnic_init_storm_conn_bufs(struct cnic_dev *dev,
  1603. struct l4_kwq_connect_req1 *kwqe1,
  1604. struct l4_kwq_connect_req3 *kwqe3,
  1605. struct l5cm_active_conn_buffer *conn_buf)
  1606. {
  1607. struct l5cm_conn_addr_params *conn_addr = &conn_buf->conn_addr_buf;
  1608. struct l5cm_xstorm_conn_buffer *xstorm_buf =
  1609. &conn_buf->xstorm_conn_buffer;
  1610. struct l5cm_tstorm_conn_buffer *tstorm_buf =
  1611. &conn_buf->tstorm_conn_buffer;
  1612. struct regpair context_addr;
  1613. u32 cid = BNX2X_SW_CID(kwqe1->cid);
  1614. struct in6_addr src_ip, dst_ip;
  1615. int i;
  1616. u32 *addrp;
  1617. addrp = (u32 *) &conn_addr->local_ip_addr;
  1618. for (i = 0; i < 4; i++, addrp++)
  1619. src_ip.in6_u.u6_addr32[i] = cpu_to_be32(*addrp);
  1620. addrp = (u32 *) &conn_addr->remote_ip_addr;
  1621. for (i = 0; i < 4; i++, addrp++)
  1622. dst_ip.in6_u.u6_addr32[i] = cpu_to_be32(*addrp);
  1623. cnic_get_bnx2x_ctx(dev, cid, 0, &context_addr);
  1624. xstorm_buf->context_addr.hi = context_addr.hi;
  1625. xstorm_buf->context_addr.lo = context_addr.lo;
  1626. xstorm_buf->mss = 0xffff;
  1627. xstorm_buf->rcv_buf = kwqe3->rcv_buf;
  1628. if (kwqe1->tcp_flags & L4_KWQ_CONNECT_REQ1_NAGLE_ENABLE)
  1629. xstorm_buf->params |= L5CM_XSTORM_CONN_BUFFER_NAGLE_ENABLE;
  1630. xstorm_buf->pseudo_header_checksum =
  1631. swab16(~csum_ipv6_magic(&src_ip, &dst_ip, 0, IPPROTO_TCP, 0));
  1632. if (!(kwqe1->tcp_flags & L4_KWQ_CONNECT_REQ1_NO_DELAY_ACK))
  1633. tstorm_buf->params |=
  1634. L5CM_TSTORM_CONN_BUFFER_DELAYED_ACK_ENABLE;
  1635. if (kwqe3->ka_timeout) {
  1636. tstorm_buf->ka_enable = 1;
  1637. tstorm_buf->ka_timeout = kwqe3->ka_timeout;
  1638. tstorm_buf->ka_interval = kwqe3->ka_interval;
  1639. tstorm_buf->ka_max_probe_count = kwqe3->ka_max_probe_count;
  1640. }
  1641. tstorm_buf->max_rt_time = 0xffffffff;
  1642. }
  1643. static void cnic_init_bnx2x_mac(struct cnic_dev *dev)
  1644. {
  1645. struct cnic_local *cp = dev->cnic_priv;
  1646. u32 pfid = cp->pfid;
  1647. u8 *mac = dev->mac_addr;
  1648. CNIC_WR8(dev, BAR_XSTRORM_INTMEM +
  1649. XSTORM_ISCSI_LOCAL_MAC_ADDR0_OFFSET(pfid), mac[0]);
  1650. CNIC_WR8(dev, BAR_XSTRORM_INTMEM +
  1651. XSTORM_ISCSI_LOCAL_MAC_ADDR1_OFFSET(pfid), mac[1]);
  1652. CNIC_WR8(dev, BAR_XSTRORM_INTMEM +
  1653. XSTORM_ISCSI_LOCAL_MAC_ADDR2_OFFSET(pfid), mac[2]);
  1654. CNIC_WR8(dev, BAR_XSTRORM_INTMEM +
  1655. XSTORM_ISCSI_LOCAL_MAC_ADDR3_OFFSET(pfid), mac[3]);
  1656. CNIC_WR8(dev, BAR_XSTRORM_INTMEM +
  1657. XSTORM_ISCSI_LOCAL_MAC_ADDR4_OFFSET(pfid), mac[4]);
  1658. CNIC_WR8(dev, BAR_XSTRORM_INTMEM +
  1659. XSTORM_ISCSI_LOCAL_MAC_ADDR5_OFFSET(pfid), mac[5]);
  1660. CNIC_WR8(dev, BAR_TSTRORM_INTMEM +
  1661. TSTORM_ISCSI_TCP_VARS_LSB_LOCAL_MAC_ADDR_OFFSET(pfid), mac[5]);
  1662. CNIC_WR8(dev, BAR_TSTRORM_INTMEM +
  1663. TSTORM_ISCSI_TCP_VARS_LSB_LOCAL_MAC_ADDR_OFFSET(pfid) + 1,
  1664. mac[4]);
  1665. CNIC_WR8(dev, BAR_TSTRORM_INTMEM +
  1666. TSTORM_ISCSI_TCP_VARS_MID_LOCAL_MAC_ADDR_OFFSET(pfid), mac[3]);
  1667. CNIC_WR8(dev, BAR_TSTRORM_INTMEM +
  1668. TSTORM_ISCSI_TCP_VARS_MID_LOCAL_MAC_ADDR_OFFSET(pfid) + 1,
  1669. mac[2]);
  1670. CNIC_WR8(dev, BAR_TSTRORM_INTMEM +
  1671. TSTORM_ISCSI_TCP_VARS_MSB_LOCAL_MAC_ADDR_OFFSET(pfid), mac[1]);
  1672. CNIC_WR8(dev, BAR_TSTRORM_INTMEM +
  1673. TSTORM_ISCSI_TCP_VARS_MSB_LOCAL_MAC_ADDR_OFFSET(pfid) + 1,
  1674. mac[0]);
  1675. }
  1676. static void cnic_bnx2x_set_tcp_timestamp(struct cnic_dev *dev, int tcp_ts)
  1677. {
  1678. struct cnic_local *cp = dev->cnic_priv;
  1679. u8 xstorm_flags = XSTORM_L5CM_TCP_FLAGS_WND_SCL_EN;
  1680. u16 tstorm_flags = 0;
  1681. if (tcp_ts) {
  1682. xstorm_flags |= XSTORM_L5CM_TCP_FLAGS_TS_ENABLED;
  1683. tstorm_flags |= TSTORM_L5CM_TCP_FLAGS_TS_ENABLED;
  1684. }
  1685. CNIC_WR8(dev, BAR_XSTRORM_INTMEM +
  1686. XSTORM_ISCSI_TCP_VARS_FLAGS_OFFSET(cp->pfid), xstorm_flags);
  1687. CNIC_WR16(dev, BAR_TSTRORM_INTMEM +
  1688. TSTORM_ISCSI_TCP_VARS_FLAGS_OFFSET(cp->pfid), tstorm_flags);
  1689. }
  1690. static int cnic_bnx2x_connect(struct cnic_dev *dev, struct kwqe *wqes[],
  1691. u32 num, int *work)
  1692. {
  1693. struct cnic_local *cp = dev->cnic_priv;
  1694. struct l4_kwq_connect_req1 *kwqe1 =
  1695. (struct l4_kwq_connect_req1 *) wqes[0];
  1696. struct l4_kwq_connect_req3 *kwqe3;
  1697. struct l5cm_active_conn_buffer *conn_buf;
  1698. struct l5cm_conn_addr_params *conn_addr;
  1699. union l5cm_specific_data l5_data;
  1700. u32 l5_cid = kwqe1->pg_cid;
  1701. struct cnic_sock *csk = &cp->csk_tbl[l5_cid];
  1702. struct cnic_context *ctx = &cp->ctx_tbl[l5_cid];
  1703. int ret;
  1704. if (num < 2) {
  1705. *work = num;
  1706. return -EINVAL;
  1707. }
  1708. if (kwqe1->conn_flags & L4_KWQ_CONNECT_REQ1_IP_V6)
  1709. *work = 3;
  1710. else
  1711. *work = 2;
  1712. if (num < *work) {
  1713. *work = num;
  1714. return -EINVAL;
  1715. }
  1716. if (sizeof(*conn_buf) > CNIC_KWQ16_DATA_SIZE) {
  1717. netdev_err(dev->netdev, "conn_buf size too big\n");
  1718. return -ENOMEM;
  1719. }
  1720. conn_buf = cnic_get_kwqe_16_data(cp, l5_cid, &l5_data);
  1721. if (!conn_buf)
  1722. return -ENOMEM;
  1723. memset(conn_buf, 0, sizeof(*conn_buf));
  1724. conn_addr = &conn_buf->conn_addr_buf;
  1725. conn_addr->remote_addr_0 = csk->ha[0];
  1726. conn_addr->remote_addr_1 = csk->ha[1];
  1727. conn_addr->remote_addr_2 = csk->ha[2];
  1728. conn_addr->remote_addr_3 = csk->ha[3];
  1729. conn_addr->remote_addr_4 = csk->ha[4];
  1730. conn_addr->remote_addr_5 = csk->ha[5];
  1731. if (kwqe1->conn_flags & L4_KWQ_CONNECT_REQ1_IP_V6) {
  1732. struct l4_kwq_connect_req2 *kwqe2 =
  1733. (struct l4_kwq_connect_req2 *) wqes[1];
  1734. conn_addr->local_ip_addr.ip_addr_hi_hi = kwqe2->src_ip_v6_4;
  1735. conn_addr->local_ip_addr.ip_addr_hi_lo = kwqe2->src_ip_v6_3;
  1736. conn_addr->local_ip_addr.ip_addr_lo_hi = kwqe2->src_ip_v6_2;
  1737. conn_addr->remote_ip_addr.ip_addr_hi_hi = kwqe2->dst_ip_v6_4;
  1738. conn_addr->remote_ip_addr.ip_addr_hi_lo = kwqe2->dst_ip_v6_3;
  1739. conn_addr->remote_ip_addr.ip_addr_lo_hi = kwqe2->dst_ip_v6_2;
  1740. conn_addr->params |= L5CM_CONN_ADDR_PARAMS_IP_VERSION;
  1741. }
  1742. kwqe3 = (struct l4_kwq_connect_req3 *) wqes[*work - 1];
  1743. conn_addr->local_ip_addr.ip_addr_lo_lo = kwqe1->src_ip;
  1744. conn_addr->remote_ip_addr.ip_addr_lo_lo = kwqe1->dst_ip;
  1745. conn_addr->local_tcp_port = kwqe1->src_port;
  1746. conn_addr->remote_tcp_port = kwqe1->dst_port;
  1747. conn_addr->pmtu = kwqe3->pmtu;
  1748. cnic_init_storm_conn_bufs(dev, kwqe1, kwqe3, conn_buf);
  1749. CNIC_WR16(dev, BAR_XSTRORM_INTMEM +
  1750. XSTORM_ISCSI_LOCAL_VLAN_OFFSET(cp->pfid), csk->vlan_id);
  1751. cnic_bnx2x_set_tcp_timestamp(dev,
  1752. kwqe1->tcp_flags & L4_KWQ_CONNECT_REQ1_TIME_STAMP);
  1753. ret = cnic_submit_kwqe_16(dev, L5CM_RAMROD_CMD_ID_TCP_CONNECT,
  1754. kwqe1->cid, ISCSI_CONNECTION_TYPE, &l5_data);
  1755. if (!ret)
  1756. set_bit(CTX_FL_OFFLD_START, &ctx->ctx_flags);
  1757. return ret;
  1758. }
  1759. static int cnic_bnx2x_close(struct cnic_dev *dev, struct kwqe *kwqe)
  1760. {
  1761. struct l4_kwq_close_req *req = (struct l4_kwq_close_req *) kwqe;
  1762. union l5cm_specific_data l5_data;
  1763. int ret;
  1764. memset(&l5_data, 0, sizeof(l5_data));
  1765. ret = cnic_submit_kwqe_16(dev, L5CM_RAMROD_CMD_ID_CLOSE,
  1766. req->cid, ISCSI_CONNECTION_TYPE, &l5_data);
  1767. return ret;
  1768. }
  1769. static int cnic_bnx2x_reset(struct cnic_dev *dev, struct kwqe *kwqe)
  1770. {
  1771. struct l4_kwq_reset_req *req = (struct l4_kwq_reset_req *) kwqe;
  1772. union l5cm_specific_data l5_data;
  1773. int ret;
  1774. memset(&l5_data, 0, sizeof(l5_data));
  1775. ret = cnic_submit_kwqe_16(dev, L5CM_RAMROD_CMD_ID_ABORT,
  1776. req->cid, ISCSI_CONNECTION_TYPE, &l5_data);
  1777. return ret;
  1778. }
  1779. static int cnic_bnx2x_offload_pg(struct cnic_dev *dev, struct kwqe *kwqe)
  1780. {
  1781. struct l4_kwq_offload_pg *req = (struct l4_kwq_offload_pg *) kwqe;
  1782. struct l4_kcq kcqe;
  1783. struct kcqe *cqes[1];
  1784. memset(&kcqe, 0, sizeof(kcqe));
  1785. kcqe.pg_host_opaque = req->host_opaque;
  1786. kcqe.pg_cid = req->host_opaque;
  1787. kcqe.op_code = L4_KCQE_OPCODE_VALUE_OFFLOAD_PG;
  1788. cqes[0] = (struct kcqe *) &kcqe;
  1789. cnic_reply_bnx2x_kcqes(dev, CNIC_ULP_L4, cqes, 1);
  1790. return 0;
  1791. }
  1792. static int cnic_bnx2x_update_pg(struct cnic_dev *dev, struct kwqe *kwqe)
  1793. {
  1794. struct l4_kwq_update_pg *req = (struct l4_kwq_update_pg *) kwqe;
  1795. struct l4_kcq kcqe;
  1796. struct kcqe *cqes[1];
  1797. memset(&kcqe, 0, sizeof(kcqe));
  1798. kcqe.pg_host_opaque = req->pg_host_opaque;
  1799. kcqe.pg_cid = req->pg_cid;
  1800. kcqe.op_code = L4_KCQE_OPCODE_VALUE_UPDATE_PG;
  1801. cqes[0] = (struct kcqe *) &kcqe;
  1802. cnic_reply_bnx2x_kcqes(dev, CNIC_ULP_L4, cqes, 1);
  1803. return 0;
  1804. }
  1805. static int cnic_bnx2x_fcoe_stat(struct cnic_dev *dev, struct kwqe *kwqe)
  1806. {
  1807. struct fcoe_kwqe_stat *req;
  1808. struct fcoe_stat_ramrod_params *fcoe_stat;
  1809. union l5cm_specific_data l5_data;
  1810. struct cnic_local *cp = dev->cnic_priv;
  1811. int ret;
  1812. u32 cid;
  1813. req = (struct fcoe_kwqe_stat *) kwqe;
  1814. cid = BNX2X_HW_CID(cp, cp->fcoe_init_cid);
  1815. fcoe_stat = cnic_get_kwqe_16_data(cp, BNX2X_FCOE_L5_CID_BASE, &l5_data);
  1816. if (!fcoe_stat)
  1817. return -ENOMEM;
  1818. memset(fcoe_stat, 0, sizeof(*fcoe_stat));
  1819. memcpy(&fcoe_stat->stat_kwqe, req, sizeof(*req));
  1820. ret = cnic_submit_kwqe_16(dev, FCOE_RAMROD_CMD_ID_STAT_FUNC, cid,
  1821. FCOE_CONNECTION_TYPE, &l5_data);
  1822. return ret;
  1823. }
  1824. static int cnic_bnx2x_fcoe_init1(struct cnic_dev *dev, struct kwqe *wqes[],
  1825. u32 num, int *work)
  1826. {
  1827. int ret;
  1828. struct cnic_local *cp = dev->cnic_priv;
  1829. u32 cid;
  1830. struct fcoe_init_ramrod_params *fcoe_init;
  1831. struct fcoe_kwqe_init1 *req1;
  1832. struct fcoe_kwqe_init2 *req2;
  1833. struct fcoe_kwqe_init3 *req3;
  1834. union l5cm_specific_data l5_data;
  1835. if (num < 3) {
  1836. *work = num;
  1837. return -EINVAL;
  1838. }
  1839. req1 = (struct fcoe_kwqe_init1 *) wqes[0];
  1840. req2 = (struct fcoe_kwqe_init2 *) wqes[1];
  1841. req3 = (struct fcoe_kwqe_init3 *) wqes[2];
  1842. if (req2->hdr.op_code != FCOE_KWQE_OPCODE_INIT2) {
  1843. *work = 1;
  1844. return -EINVAL;
  1845. }
  1846. if (req3->hdr.op_code != FCOE_KWQE_OPCODE_INIT3) {
  1847. *work = 2;
  1848. return -EINVAL;
  1849. }
  1850. if (sizeof(*fcoe_init) > CNIC_KWQ16_DATA_SIZE) {
  1851. netdev_err(dev->netdev, "fcoe_init size too big\n");
  1852. return -ENOMEM;
  1853. }
  1854. fcoe_init = cnic_get_kwqe_16_data(cp, BNX2X_FCOE_L5_CID_BASE, &l5_data);
  1855. if (!fcoe_init)
  1856. return -ENOMEM;
  1857. memset(fcoe_init, 0, sizeof(*fcoe_init));
  1858. memcpy(&fcoe_init->init_kwqe1, req1, sizeof(*req1));
  1859. memcpy(&fcoe_init->init_kwqe2, req2, sizeof(*req2));
  1860. memcpy(&fcoe_init->init_kwqe3, req3, sizeof(*req3));
  1861. fcoe_init->eq_pbl_base.lo = cp->kcq2.dma.pgtbl_map & 0xffffffff;
  1862. fcoe_init->eq_pbl_base.hi = (u64) cp->kcq2.dma.pgtbl_map >> 32;
  1863. fcoe_init->eq_pbl_size = cp->kcq2.dma.num_pages;
  1864. fcoe_init->sb_num = cp->status_blk_num;
  1865. fcoe_init->eq_prod = MAX_KCQ_IDX;
  1866. fcoe_init->sb_id = HC_INDEX_FCOE_EQ_CONS;
  1867. cp->kcq2.sw_prod_idx = 0;
  1868. cid = BNX2X_HW_CID(cp, cp->fcoe_init_cid);
  1869. ret = cnic_submit_kwqe_16(dev, FCOE_RAMROD_CMD_ID_INIT_FUNC, cid,
  1870. FCOE_CONNECTION_TYPE, &l5_data);
  1871. *work = 3;
  1872. return ret;
  1873. }
  1874. static int cnic_bnx2x_fcoe_ofld1(struct cnic_dev *dev, struct kwqe *wqes[],
  1875. u32 num, int *work)
  1876. {
  1877. int ret = 0;
  1878. u32 cid = -1, l5_cid;
  1879. struct cnic_local *cp = dev->cnic_priv;
  1880. struct fcoe_kwqe_conn_offload1 *req1;
  1881. struct fcoe_kwqe_conn_offload2 *req2;
  1882. struct fcoe_kwqe_conn_offload3 *req3;
  1883. struct fcoe_kwqe_conn_offload4 *req4;
  1884. struct fcoe_conn_offload_ramrod_params *fcoe_offload;
  1885. struct cnic_context *ctx;
  1886. struct fcoe_context *fctx;
  1887. struct regpair ctx_addr;
  1888. union l5cm_specific_data l5_data;
  1889. struct fcoe_kcqe kcqe;
  1890. struct kcqe *cqes[1];
  1891. if (num < 4) {
  1892. *work = num;
  1893. return -EINVAL;
  1894. }
  1895. req1 = (struct fcoe_kwqe_conn_offload1 *) wqes[0];
  1896. req2 = (struct fcoe_kwqe_conn_offload2 *) wqes[1];
  1897. req3 = (struct fcoe_kwqe_conn_offload3 *) wqes[2];
  1898. req4 = (struct fcoe_kwqe_conn_offload4 *) wqes[3];
  1899. *work = 4;
  1900. l5_cid = req1->fcoe_conn_id;
  1901. if (l5_cid >= dev->max_fcoe_conn)
  1902. goto err_reply;
  1903. l5_cid += BNX2X_FCOE_L5_CID_BASE;
  1904. ctx = &cp->ctx_tbl[l5_cid];
  1905. if (test_bit(CTX_FL_OFFLD_START, &ctx->ctx_flags))
  1906. goto err_reply;
  1907. ret = cnic_alloc_bnx2x_conn_resc(dev, l5_cid);
  1908. if (ret) {
  1909. ret = 0;
  1910. goto err_reply;
  1911. }
  1912. cid = ctx->cid;
  1913. fctx = cnic_get_bnx2x_ctx(dev, cid, 1, &ctx_addr);
  1914. if (fctx) {
  1915. u32 hw_cid = BNX2X_HW_CID(cp, cid);
  1916. u32 val;
  1917. val = CDU_RSRVD_VALUE_TYPE_A(hw_cid, CDU_REGION_NUMBER_XCM_AG,
  1918. FCOE_CONNECTION_TYPE);
  1919. fctx->xstorm_ag_context.cdu_reserved = val;
  1920. val = CDU_RSRVD_VALUE_TYPE_A(hw_cid, CDU_REGION_NUMBER_UCM_AG,
  1921. FCOE_CONNECTION_TYPE);
  1922. fctx->ustorm_ag_context.cdu_usage = val;
  1923. }
  1924. if (sizeof(*fcoe_offload) > CNIC_KWQ16_DATA_SIZE) {
  1925. netdev_err(dev->netdev, "fcoe_offload size too big\n");
  1926. goto err_reply;
  1927. }
  1928. fcoe_offload = cnic_get_kwqe_16_data(cp, l5_cid, &l5_data);
  1929. if (!fcoe_offload)
  1930. goto err_reply;
  1931. memset(fcoe_offload, 0, sizeof(*fcoe_offload));
  1932. memcpy(&fcoe_offload->offload_kwqe1, req1, sizeof(*req1));
  1933. memcpy(&fcoe_offload->offload_kwqe2, req2, sizeof(*req2));
  1934. memcpy(&fcoe_offload->offload_kwqe3, req3, sizeof(*req3));
  1935. memcpy(&fcoe_offload->offload_kwqe4, req4, sizeof(*req4));
  1936. cid = BNX2X_HW_CID(cp, cid);
  1937. ret = cnic_submit_kwqe_16(dev, FCOE_RAMROD_CMD_ID_OFFLOAD_CONN, cid,
  1938. FCOE_CONNECTION_TYPE, &l5_data);
  1939. if (!ret)
  1940. set_bit(CTX_FL_OFFLD_START, &ctx->ctx_flags);
  1941. return ret;
  1942. err_reply:
  1943. if (cid != -1)
  1944. cnic_free_bnx2x_conn_resc(dev, l5_cid);
  1945. memset(&kcqe, 0, sizeof(kcqe));
  1946. kcqe.op_code = FCOE_KCQE_OPCODE_OFFLOAD_CONN;
  1947. kcqe.fcoe_conn_id = req1->fcoe_conn_id;
  1948. kcqe.completion_status = FCOE_KCQE_COMPLETION_STATUS_CTX_ALLOC_FAILURE;
  1949. cqes[0] = (struct kcqe *) &kcqe;
  1950. cnic_reply_bnx2x_kcqes(dev, CNIC_ULP_FCOE, cqes, 1);
  1951. return ret;
  1952. }
  1953. static int cnic_bnx2x_fcoe_enable(struct cnic_dev *dev, struct kwqe *kwqe)
  1954. {
  1955. struct fcoe_kwqe_conn_enable_disable *req;
  1956. struct fcoe_conn_enable_disable_ramrod_params *fcoe_enable;
  1957. union l5cm_specific_data l5_data;
  1958. int ret;
  1959. u32 cid, l5_cid;
  1960. struct cnic_local *cp = dev->cnic_priv;
  1961. req = (struct fcoe_kwqe_conn_enable_disable *) kwqe;
  1962. cid = req->context_id;
  1963. l5_cid = req->conn_id + BNX2X_FCOE_L5_CID_BASE;
  1964. if (sizeof(*fcoe_enable) > CNIC_KWQ16_DATA_SIZE) {
  1965. netdev_err(dev->netdev, "fcoe_enable size too big\n");
  1966. return -ENOMEM;
  1967. }
  1968. fcoe_enable = cnic_get_kwqe_16_data(cp, l5_cid, &l5_data);
  1969. if (!fcoe_enable)
  1970. return -ENOMEM;
  1971. memset(fcoe_enable, 0, sizeof(*fcoe_enable));
  1972. memcpy(&fcoe_enable->enable_disable_kwqe, req, sizeof(*req));
  1973. ret = cnic_submit_kwqe_16(dev, FCOE_RAMROD_CMD_ID_ENABLE_CONN, cid,
  1974. FCOE_CONNECTION_TYPE, &l5_data);
  1975. return ret;
  1976. }
  1977. static int cnic_bnx2x_fcoe_disable(struct cnic_dev *dev, struct kwqe *kwqe)
  1978. {
  1979. struct fcoe_kwqe_conn_enable_disable *req;
  1980. struct fcoe_conn_enable_disable_ramrod_params *fcoe_disable;
  1981. union l5cm_specific_data l5_data;
  1982. int ret;
  1983. u32 cid, l5_cid;
  1984. struct cnic_local *cp = dev->cnic_priv;
  1985. req = (struct fcoe_kwqe_conn_enable_disable *) kwqe;
  1986. cid = req->context_id;
  1987. l5_cid = req->conn_id;
  1988. if (l5_cid >= dev->max_fcoe_conn)
  1989. return -EINVAL;
  1990. l5_cid += BNX2X_FCOE_L5_CID_BASE;
  1991. if (sizeof(*fcoe_disable) > CNIC_KWQ16_DATA_SIZE) {
  1992. netdev_err(dev->netdev, "fcoe_disable size too big\n");
  1993. return -ENOMEM;
  1994. }
  1995. fcoe_disable = cnic_get_kwqe_16_data(cp, l5_cid, &l5_data);
  1996. if (!fcoe_disable)
  1997. return -ENOMEM;
  1998. memset(fcoe_disable, 0, sizeof(*fcoe_disable));
  1999. memcpy(&fcoe_disable->enable_disable_kwqe, req, sizeof(*req));
  2000. ret = cnic_submit_kwqe_16(dev, FCOE_RAMROD_CMD_ID_DISABLE_CONN, cid,
  2001. FCOE_CONNECTION_TYPE, &l5_data);
  2002. return ret;
  2003. }
  2004. static int cnic_bnx2x_fcoe_destroy(struct cnic_dev *dev, struct kwqe *kwqe)
  2005. {
  2006. struct fcoe_kwqe_conn_destroy *req;
  2007. union l5cm_specific_data l5_data;
  2008. int ret;
  2009. u32 cid, l5_cid;
  2010. struct cnic_local *cp = dev->cnic_priv;
  2011. struct cnic_context *ctx;
  2012. struct fcoe_kcqe kcqe;
  2013. struct kcqe *cqes[1];
  2014. req = (struct fcoe_kwqe_conn_destroy *) kwqe;
  2015. cid = req->context_id;
  2016. l5_cid = req->conn_id;
  2017. if (l5_cid >= dev->max_fcoe_conn)
  2018. return -EINVAL;
  2019. l5_cid += BNX2X_FCOE_L5_CID_BASE;
  2020. ctx = &cp->ctx_tbl[l5_cid];
  2021. init_waitqueue_head(&ctx->waitq);
  2022. ctx->wait_cond = 0;
  2023. memset(&kcqe, 0, sizeof(kcqe));
  2024. kcqe.completion_status = FCOE_KCQE_COMPLETION_STATUS_ERROR;
  2025. memset(&l5_data, 0, sizeof(l5_data));
  2026. ret = cnic_submit_kwqe_16(dev, FCOE_RAMROD_CMD_ID_TERMINATE_CONN, cid,
  2027. FCOE_CONNECTION_TYPE, &l5_data);
  2028. if (ret == 0) {
  2029. wait_event_timeout(ctx->waitq, ctx->wait_cond, CNIC_RAMROD_TMO);
  2030. if (ctx->wait_cond)
  2031. kcqe.completion_status = 0;
  2032. }
  2033. set_bit(CTX_FL_DELETE_WAIT, &ctx->ctx_flags);
  2034. queue_delayed_work(cnic_wq, &cp->delete_task, msecs_to_jiffies(2000));
  2035. kcqe.op_code = FCOE_KCQE_OPCODE_DESTROY_CONN;
  2036. kcqe.fcoe_conn_id = req->conn_id;
  2037. kcqe.fcoe_conn_context_id = cid;
  2038. cqes[0] = (struct kcqe *) &kcqe;
  2039. cnic_reply_bnx2x_kcqes(dev, CNIC_ULP_FCOE, cqes, 1);
  2040. return ret;
  2041. }
  2042. static void cnic_bnx2x_delete_wait(struct cnic_dev *dev, u32 start_cid)
  2043. {
  2044. struct cnic_local *cp = dev->cnic_priv;
  2045. u32 i;
  2046. for (i = start_cid; i < cp->max_cid_space; i++) {
  2047. struct cnic_context *ctx = &cp->ctx_tbl[i];
  2048. int j;
  2049. while (test_bit(CTX_FL_DELETE_WAIT, &ctx->ctx_flags))
  2050. msleep(10);
  2051. for (j = 0; j < 5; j++) {
  2052. if (!test_bit(CTX_FL_OFFLD_START, &ctx->ctx_flags))
  2053. break;
  2054. msleep(20);
  2055. }
  2056. if (test_bit(CTX_FL_OFFLD_START, &ctx->ctx_flags))
  2057. netdev_warn(dev->netdev, "CID %x not deleted\n",
  2058. ctx->cid);
  2059. }
  2060. }
  2061. static int cnic_bnx2x_fcoe_fw_destroy(struct cnic_dev *dev, struct kwqe *kwqe)
  2062. {
  2063. struct fcoe_kwqe_destroy *req;
  2064. union l5cm_specific_data l5_data;
  2065. struct cnic_local *cp = dev->cnic_priv;
  2066. int ret;
  2067. u32 cid;
  2068. cnic_bnx2x_delete_wait(dev, MAX_ISCSI_TBL_SZ);
  2069. req = (struct fcoe_kwqe_destroy *) kwqe;
  2070. cid = BNX2X_HW_CID(cp, cp->fcoe_init_cid);
  2071. memset(&l5_data, 0, sizeof(l5_data));
  2072. ret = cnic_submit_kwqe_16(dev, FCOE_RAMROD_CMD_ID_DESTROY_FUNC, cid,
  2073. FCOE_CONNECTION_TYPE, &l5_data);
  2074. return ret;
  2075. }
  2076. static int cnic_submit_bnx2x_iscsi_kwqes(struct cnic_dev *dev,
  2077. struct kwqe *wqes[], u32 num_wqes)
  2078. {
  2079. int i, work, ret;
  2080. u32 opcode;
  2081. struct kwqe *kwqe;
  2082. if (!test_bit(CNIC_F_CNIC_UP, &dev->flags))
  2083. return -EAGAIN; /* bnx2 is down */
  2084. for (i = 0; i < num_wqes; ) {
  2085. kwqe = wqes[i];
  2086. opcode = KWQE_OPCODE(kwqe->kwqe_op_flag);
  2087. work = 1;
  2088. switch (opcode) {
  2089. case ISCSI_KWQE_OPCODE_INIT1:
  2090. ret = cnic_bnx2x_iscsi_init1(dev, kwqe);
  2091. break;
  2092. case ISCSI_KWQE_OPCODE_INIT2:
  2093. ret = cnic_bnx2x_iscsi_init2(dev, kwqe);
  2094. break;
  2095. case ISCSI_KWQE_OPCODE_OFFLOAD_CONN1:
  2096. ret = cnic_bnx2x_iscsi_ofld1(dev, &wqes[i],
  2097. num_wqes - i, &work);
  2098. break;
  2099. case ISCSI_KWQE_OPCODE_UPDATE_CONN:
  2100. ret = cnic_bnx2x_iscsi_update(dev, kwqe);
  2101. break;
  2102. case ISCSI_KWQE_OPCODE_DESTROY_CONN:
  2103. ret = cnic_bnx2x_iscsi_destroy(dev, kwqe);
  2104. break;
  2105. case L4_KWQE_OPCODE_VALUE_CONNECT1:
  2106. ret = cnic_bnx2x_connect(dev, &wqes[i], num_wqes - i,
  2107. &work);
  2108. break;
  2109. case L4_KWQE_OPCODE_VALUE_CLOSE:
  2110. ret = cnic_bnx2x_close(dev, kwqe);
  2111. break;
  2112. case L4_KWQE_OPCODE_VALUE_RESET:
  2113. ret = cnic_bnx2x_reset(dev, kwqe);
  2114. break;
  2115. case L4_KWQE_OPCODE_VALUE_OFFLOAD_PG:
  2116. ret = cnic_bnx2x_offload_pg(dev, kwqe);
  2117. break;
  2118. case L4_KWQE_OPCODE_VALUE_UPDATE_PG:
  2119. ret = cnic_bnx2x_update_pg(dev, kwqe);
  2120. break;
  2121. case L4_KWQE_OPCODE_VALUE_UPLOAD_PG:
  2122. ret = 0;
  2123. break;
  2124. default:
  2125. ret = 0;
  2126. netdev_err(dev->netdev, "Unknown type of KWQE(0x%x)\n",
  2127. opcode);
  2128. break;
  2129. }
  2130. if (ret < 0)
  2131. netdev_err(dev->netdev, "KWQE(0x%x) failed\n",
  2132. opcode);
  2133. i += work;
  2134. }
  2135. return 0;
  2136. }
  2137. static int cnic_submit_bnx2x_fcoe_kwqes(struct cnic_dev *dev,
  2138. struct kwqe *wqes[], u32 num_wqes)
  2139. {
  2140. struct cnic_local *cp = dev->cnic_priv;
  2141. int i, work, ret;
  2142. u32 opcode;
  2143. struct kwqe *kwqe;
  2144. if (!test_bit(CNIC_F_CNIC_UP, &dev->flags))
  2145. return -EAGAIN; /* bnx2 is down */
  2146. if (!BNX2X_CHIP_IS_E2_PLUS(cp->chip_id))
  2147. return -EINVAL;
  2148. for (i = 0; i < num_wqes; ) {
  2149. kwqe = wqes[i];
  2150. opcode = KWQE_OPCODE(kwqe->kwqe_op_flag);
  2151. work = 1;
  2152. switch (opcode) {
  2153. case FCOE_KWQE_OPCODE_INIT1:
  2154. ret = cnic_bnx2x_fcoe_init1(dev, &wqes[i],
  2155. num_wqes - i, &work);
  2156. break;
  2157. case FCOE_KWQE_OPCODE_OFFLOAD_CONN1:
  2158. ret = cnic_bnx2x_fcoe_ofld1(dev, &wqes[i],
  2159. num_wqes - i, &work);
  2160. break;
  2161. case FCOE_KWQE_OPCODE_ENABLE_CONN:
  2162. ret = cnic_bnx2x_fcoe_enable(dev, kwqe);
  2163. break;
  2164. case FCOE_KWQE_OPCODE_DISABLE_CONN:
  2165. ret = cnic_bnx2x_fcoe_disable(dev, kwqe);
  2166. break;
  2167. case FCOE_KWQE_OPCODE_DESTROY_CONN:
  2168. ret = cnic_bnx2x_fcoe_destroy(dev, kwqe);
  2169. break;
  2170. case FCOE_KWQE_OPCODE_DESTROY:
  2171. ret = cnic_bnx2x_fcoe_fw_destroy(dev, kwqe);
  2172. break;
  2173. case FCOE_KWQE_OPCODE_STAT:
  2174. ret = cnic_bnx2x_fcoe_stat(dev, kwqe);
  2175. break;
  2176. default:
  2177. ret = 0;
  2178. netdev_err(dev->netdev, "Unknown type of KWQE(0x%x)\n",
  2179. opcode);
  2180. break;
  2181. }
  2182. if (ret < 0)
  2183. netdev_err(dev->netdev, "KWQE(0x%x) failed\n",
  2184. opcode);
  2185. i += work;
  2186. }
  2187. return 0;
  2188. }
  2189. static int cnic_submit_bnx2x_kwqes(struct cnic_dev *dev, struct kwqe *wqes[],
  2190. u32 num_wqes)
  2191. {
  2192. int ret = -EINVAL;
  2193. u32 layer_code;
  2194. if (!test_bit(CNIC_F_CNIC_UP, &dev->flags))
  2195. return -EAGAIN; /* bnx2x is down */
  2196. if (!num_wqes)
  2197. return 0;
  2198. layer_code = wqes[0]->kwqe_op_flag & KWQE_LAYER_MASK;
  2199. switch (layer_code) {
  2200. case KWQE_FLAGS_LAYER_MASK_L5_ISCSI:
  2201. case KWQE_FLAGS_LAYER_MASK_L4:
  2202. case KWQE_FLAGS_LAYER_MASK_L2:
  2203. ret = cnic_submit_bnx2x_iscsi_kwqes(dev, wqes, num_wqes);
  2204. break;
  2205. case KWQE_FLAGS_LAYER_MASK_L5_FCOE:
  2206. ret = cnic_submit_bnx2x_fcoe_kwqes(dev, wqes, num_wqes);
  2207. break;
  2208. }
  2209. return ret;
  2210. }
  2211. static inline u32 cnic_get_kcqe_layer_mask(u32 opflag)
  2212. {
  2213. if (unlikely(KCQE_OPCODE(opflag) == FCOE_RAMROD_CMD_ID_TERMINATE_CONN))
  2214. return KCQE_FLAGS_LAYER_MASK_L4;
  2215. return opflag & KCQE_FLAGS_LAYER_MASK;
  2216. }
  2217. static void service_kcqes(struct cnic_dev *dev, int num_cqes)
  2218. {
  2219. struct cnic_local *cp = dev->cnic_priv;
  2220. int i, j, comp = 0;
  2221. i = 0;
  2222. j = 1;
  2223. while (num_cqes) {
  2224. struct cnic_ulp_ops *ulp_ops;
  2225. int ulp_type;
  2226. u32 kcqe_op_flag = cp->completed_kcq[i]->kcqe_op_flag;
  2227. u32 kcqe_layer = cnic_get_kcqe_layer_mask(kcqe_op_flag);
  2228. if (unlikely(kcqe_op_flag & KCQE_RAMROD_COMPLETION))
  2229. comp++;
  2230. while (j < num_cqes) {
  2231. u32 next_op = cp->completed_kcq[i + j]->kcqe_op_flag;
  2232. if (cnic_get_kcqe_layer_mask(next_op) != kcqe_layer)
  2233. break;
  2234. if (unlikely(next_op & KCQE_RAMROD_COMPLETION))
  2235. comp++;
  2236. j++;
  2237. }
  2238. if (kcqe_layer == KCQE_FLAGS_LAYER_MASK_L5_RDMA)
  2239. ulp_type = CNIC_ULP_RDMA;
  2240. else if (kcqe_layer == KCQE_FLAGS_LAYER_MASK_L5_ISCSI)
  2241. ulp_type = CNIC_ULP_ISCSI;
  2242. else if (kcqe_layer == KCQE_FLAGS_LAYER_MASK_L5_FCOE)
  2243. ulp_type = CNIC_ULP_FCOE;
  2244. else if (kcqe_layer == KCQE_FLAGS_LAYER_MASK_L4)
  2245. ulp_type = CNIC_ULP_L4;
  2246. else if (kcqe_layer == KCQE_FLAGS_LAYER_MASK_L2)
  2247. goto end;
  2248. else {
  2249. netdev_err(dev->netdev, "Unknown type of KCQE(0x%x)\n",
  2250. kcqe_op_flag);
  2251. goto end;
  2252. }
  2253. rcu_read_lock();
  2254. ulp_ops = rcu_dereference(cp->ulp_ops[ulp_type]);
  2255. if (likely(ulp_ops)) {
  2256. ulp_ops->indicate_kcqes(cp->ulp_handle[ulp_type],
  2257. cp->completed_kcq + i, j);
  2258. }
  2259. rcu_read_unlock();
  2260. end:
  2261. num_cqes -= j;
  2262. i += j;
  2263. j = 1;
  2264. }
  2265. if (unlikely(comp))
  2266. cnic_spq_completion(dev, DRV_CTL_RET_L5_SPQ_CREDIT_CMD, comp);
  2267. }
  2268. static int cnic_get_kcqes(struct cnic_dev *dev, struct kcq_info *info)
  2269. {
  2270. struct cnic_local *cp = dev->cnic_priv;
  2271. u16 i, ri, hw_prod, last;
  2272. struct kcqe *kcqe;
  2273. int kcqe_cnt = 0, last_cnt = 0;
  2274. i = ri = last = info->sw_prod_idx;
  2275. ri &= MAX_KCQ_IDX;
  2276. hw_prod = *info->hw_prod_idx_ptr;
  2277. hw_prod = info->hw_idx(hw_prod);
  2278. while ((i != hw_prod) && (kcqe_cnt < MAX_COMPLETED_KCQE)) {
  2279. kcqe = &info->kcq[KCQ_PG(ri)][KCQ_IDX(ri)];
  2280. cp->completed_kcq[kcqe_cnt++] = kcqe;
  2281. i = info->next_idx(i);
  2282. ri = i & MAX_KCQ_IDX;
  2283. if (likely(!(kcqe->kcqe_op_flag & KCQE_FLAGS_NEXT))) {
  2284. last_cnt = kcqe_cnt;
  2285. last = i;
  2286. }
  2287. }
  2288. info->sw_prod_idx = last;
  2289. return last_cnt;
  2290. }
  2291. static int cnic_l2_completion(struct cnic_local *cp)
  2292. {
  2293. u16 hw_cons, sw_cons;
  2294. struct cnic_uio_dev *udev = cp->udev;
  2295. union eth_rx_cqe *cqe, *cqe_ring = (union eth_rx_cqe *)
  2296. (udev->l2_ring + (2 * BCM_PAGE_SIZE));
  2297. u32 cmd;
  2298. int comp = 0;
  2299. if (!test_bit(CNIC_F_BNX2X_CLASS, &cp->dev->flags))
  2300. return 0;
  2301. hw_cons = *cp->rx_cons_ptr;
  2302. if ((hw_cons & BNX2X_MAX_RCQ_DESC_CNT) == BNX2X_MAX_RCQ_DESC_CNT)
  2303. hw_cons++;
  2304. sw_cons = cp->rx_cons;
  2305. while (sw_cons != hw_cons) {
  2306. u8 cqe_fp_flags;
  2307. cqe = &cqe_ring[sw_cons & BNX2X_MAX_RCQ_DESC_CNT];
  2308. cqe_fp_flags = cqe->fast_path_cqe.type_error_flags;
  2309. if (cqe_fp_flags & ETH_FAST_PATH_RX_CQE_TYPE) {
  2310. cmd = le32_to_cpu(cqe->ramrod_cqe.conn_and_cmd_data);
  2311. cmd >>= COMMON_RAMROD_ETH_RX_CQE_CMD_ID_SHIFT;
  2312. if (cmd == RAMROD_CMD_ID_ETH_CLIENT_SETUP ||
  2313. cmd == RAMROD_CMD_ID_ETH_HALT)
  2314. comp++;
  2315. }
  2316. sw_cons = BNX2X_NEXT_RCQE(sw_cons);
  2317. }
  2318. return comp;
  2319. }
  2320. static void cnic_chk_pkt_rings(struct cnic_local *cp)
  2321. {
  2322. u16 rx_cons, tx_cons;
  2323. int comp = 0;
  2324. if (!test_bit(CNIC_LCL_FL_RINGS_INITED, &cp->cnic_local_flags))
  2325. return;
  2326. rx_cons = *cp->rx_cons_ptr;
  2327. tx_cons = *cp->tx_cons_ptr;
  2328. if (cp->tx_cons != tx_cons || cp->rx_cons != rx_cons) {
  2329. if (test_bit(CNIC_LCL_FL_L2_WAIT, &cp->cnic_local_flags))
  2330. comp = cnic_l2_completion(cp);
  2331. cp->tx_cons = tx_cons;
  2332. cp->rx_cons = rx_cons;
  2333. if (cp->udev)
  2334. uio_event_notify(&cp->udev->cnic_uinfo);
  2335. }
  2336. if (comp)
  2337. clear_bit(CNIC_LCL_FL_L2_WAIT, &cp->cnic_local_flags);
  2338. }
  2339. static u32 cnic_service_bnx2_queues(struct cnic_dev *dev)
  2340. {
  2341. struct cnic_local *cp = dev->cnic_priv;
  2342. u32 status_idx = (u16) *cp->kcq1.status_idx_ptr;
  2343. int kcqe_cnt;
  2344. /* status block index must be read before reading other fields */
  2345. rmb();
  2346. cp->kwq_con_idx = *cp->kwq_con_idx_ptr;
  2347. while ((kcqe_cnt = cnic_get_kcqes(dev, &cp->kcq1))) {
  2348. service_kcqes(dev, kcqe_cnt);
  2349. /* Tell compiler that status_blk fields can change. */
  2350. barrier();
  2351. status_idx = (u16) *cp->kcq1.status_idx_ptr;
  2352. /* status block index must be read first */
  2353. rmb();
  2354. cp->kwq_con_idx = *cp->kwq_con_idx_ptr;
  2355. }
  2356. CNIC_WR16(dev, cp->kcq1.io_addr, cp->kcq1.sw_prod_idx);
  2357. cnic_chk_pkt_rings(cp);
  2358. return status_idx;
  2359. }
  2360. static int cnic_service_bnx2(void *data, void *status_blk)
  2361. {
  2362. struct cnic_dev *dev = data;
  2363. if (unlikely(!test_bit(CNIC_F_CNIC_UP, &dev->flags))) {
  2364. struct status_block *sblk = status_blk;
  2365. return sblk->status_idx;
  2366. }
  2367. return cnic_service_bnx2_queues(dev);
  2368. }
  2369. static void cnic_service_bnx2_msix(unsigned long data)
  2370. {
  2371. struct cnic_dev *dev = (struct cnic_dev *) data;
  2372. struct cnic_local *cp = dev->cnic_priv;
  2373. cp->last_status_idx = cnic_service_bnx2_queues(dev);
  2374. CNIC_WR(dev, BNX2_PCICFG_INT_ACK_CMD, cp->int_num |
  2375. BNX2_PCICFG_INT_ACK_CMD_INDEX_VALID | cp->last_status_idx);
  2376. }
  2377. static void cnic_doirq(struct cnic_dev *dev)
  2378. {
  2379. struct cnic_local *cp = dev->cnic_priv;
  2380. if (likely(test_bit(CNIC_F_CNIC_UP, &dev->flags))) {
  2381. u16 prod = cp->kcq1.sw_prod_idx & MAX_KCQ_IDX;
  2382. prefetch(cp->status_blk.gen);
  2383. prefetch(&cp->kcq1.kcq[KCQ_PG(prod)][KCQ_IDX(prod)]);
  2384. tasklet_schedule(&cp->cnic_irq_task);
  2385. }
  2386. }
  2387. static irqreturn_t cnic_irq(int irq, void *dev_instance)
  2388. {
  2389. struct cnic_dev *dev = dev_instance;
  2390. struct cnic_local *cp = dev->cnic_priv;
  2391. if (cp->ack_int)
  2392. cp->ack_int(dev);
  2393. cnic_doirq(dev);
  2394. return IRQ_HANDLED;
  2395. }
  2396. static inline void cnic_ack_bnx2x_int(struct cnic_dev *dev, u8 id, u8 storm,
  2397. u16 index, u8 op, u8 update)
  2398. {
  2399. struct cnic_local *cp = dev->cnic_priv;
  2400. u32 hc_addr = (HC_REG_COMMAND_REG + CNIC_PORT(cp) * 32 +
  2401. COMMAND_REG_INT_ACK);
  2402. struct igu_ack_register igu_ack;
  2403. igu_ack.status_block_index = index;
  2404. igu_ack.sb_id_and_flags =
  2405. ((id << IGU_ACK_REGISTER_STATUS_BLOCK_ID_SHIFT) |
  2406. (storm << IGU_ACK_REGISTER_STORM_ID_SHIFT) |
  2407. (update << IGU_ACK_REGISTER_UPDATE_INDEX_SHIFT) |
  2408. (op << IGU_ACK_REGISTER_INTERRUPT_MODE_SHIFT));
  2409. CNIC_WR(dev, hc_addr, (*(u32 *)&igu_ack));
  2410. }
  2411. static void cnic_ack_igu_sb(struct cnic_dev *dev, u8 igu_sb_id, u8 segment,
  2412. u16 index, u8 op, u8 update)
  2413. {
  2414. struct igu_regular cmd_data;
  2415. u32 igu_addr = BAR_IGU_INTMEM + (IGU_CMD_INT_ACK_BASE + igu_sb_id) * 8;
  2416. cmd_data.sb_id_and_flags =
  2417. (index << IGU_REGULAR_SB_INDEX_SHIFT) |
  2418. (segment << IGU_REGULAR_SEGMENT_ACCESS_SHIFT) |
  2419. (update << IGU_REGULAR_BUPDATE_SHIFT) |
  2420. (op << IGU_REGULAR_ENABLE_INT_SHIFT);
  2421. CNIC_WR(dev, igu_addr, cmd_data.sb_id_and_flags);
  2422. }
  2423. static void cnic_ack_bnx2x_msix(struct cnic_dev *dev)
  2424. {
  2425. struct cnic_local *cp = dev->cnic_priv;
  2426. cnic_ack_bnx2x_int(dev, cp->bnx2x_igu_sb_id, CSTORM_ID, 0,
  2427. IGU_INT_DISABLE, 0);
  2428. }
  2429. static void cnic_ack_bnx2x_e2_msix(struct cnic_dev *dev)
  2430. {
  2431. struct cnic_local *cp = dev->cnic_priv;
  2432. cnic_ack_igu_sb(dev, cp->bnx2x_igu_sb_id, IGU_SEG_ACCESS_DEF, 0,
  2433. IGU_INT_DISABLE, 0);
  2434. }
  2435. static u32 cnic_service_bnx2x_kcq(struct cnic_dev *dev, struct kcq_info *info)
  2436. {
  2437. u32 last_status = *info->status_idx_ptr;
  2438. int kcqe_cnt;
  2439. /* status block index must be read before reading the KCQ */
  2440. rmb();
  2441. while ((kcqe_cnt = cnic_get_kcqes(dev, info))) {
  2442. service_kcqes(dev, kcqe_cnt);
  2443. /* Tell compiler that sblk fields can change. */
  2444. barrier();
  2445. last_status = *info->status_idx_ptr;
  2446. /* status block index must be read before reading the KCQ */
  2447. rmb();
  2448. }
  2449. return last_status;
  2450. }
  2451. static void cnic_service_bnx2x_bh(unsigned long data)
  2452. {
  2453. struct cnic_dev *dev = (struct cnic_dev *) data;
  2454. struct cnic_local *cp = dev->cnic_priv;
  2455. u32 status_idx, new_status_idx;
  2456. if (unlikely(!test_bit(CNIC_F_CNIC_UP, &dev->flags)))
  2457. return;
  2458. while (1) {
  2459. status_idx = cnic_service_bnx2x_kcq(dev, &cp->kcq1);
  2460. CNIC_WR16(dev, cp->kcq1.io_addr,
  2461. cp->kcq1.sw_prod_idx + MAX_KCQ_IDX);
  2462. if (!BNX2X_CHIP_IS_E2_PLUS(cp->chip_id)) {
  2463. cnic_ack_bnx2x_int(dev, cp->bnx2x_igu_sb_id, USTORM_ID,
  2464. status_idx, IGU_INT_ENABLE, 1);
  2465. break;
  2466. }
  2467. new_status_idx = cnic_service_bnx2x_kcq(dev, &cp->kcq2);
  2468. if (new_status_idx != status_idx)
  2469. continue;
  2470. CNIC_WR16(dev, cp->kcq2.io_addr, cp->kcq2.sw_prod_idx +
  2471. MAX_KCQ_IDX);
  2472. cnic_ack_igu_sb(dev, cp->bnx2x_igu_sb_id, IGU_SEG_ACCESS_DEF,
  2473. status_idx, IGU_INT_ENABLE, 1);
  2474. break;
  2475. }
  2476. }
  2477. static int cnic_service_bnx2x(void *data, void *status_blk)
  2478. {
  2479. struct cnic_dev *dev = data;
  2480. struct cnic_local *cp = dev->cnic_priv;
  2481. if (!(cp->ethdev->drv_state & CNIC_DRV_STATE_USING_MSIX))
  2482. cnic_doirq(dev);
  2483. cnic_chk_pkt_rings(cp);
  2484. return 0;
  2485. }
  2486. static void cnic_ulp_stop_one(struct cnic_local *cp, int if_type)
  2487. {
  2488. struct cnic_ulp_ops *ulp_ops;
  2489. if (if_type == CNIC_ULP_ISCSI)
  2490. cnic_send_nlmsg(cp, ISCSI_KEVENT_IF_DOWN, NULL);
  2491. mutex_lock(&cnic_lock);
  2492. ulp_ops = rcu_dereference_protected(cp->ulp_ops[if_type],
  2493. lockdep_is_held(&cnic_lock));
  2494. if (!ulp_ops) {
  2495. mutex_unlock(&cnic_lock);
  2496. return;
  2497. }
  2498. set_bit(ULP_F_CALL_PENDING, &cp->ulp_flags[if_type]);
  2499. mutex_unlock(&cnic_lock);
  2500. if (test_and_clear_bit(ULP_F_START, &cp->ulp_flags[if_type]))
  2501. ulp_ops->cnic_stop(cp->ulp_handle[if_type]);
  2502. clear_bit(ULP_F_CALL_PENDING, &cp->ulp_flags[if_type]);
  2503. }
  2504. static void cnic_ulp_stop(struct cnic_dev *dev)
  2505. {
  2506. struct cnic_local *cp = dev->cnic_priv;
  2507. int if_type;
  2508. for (if_type = 0; if_type < MAX_CNIC_ULP_TYPE; if_type++)
  2509. cnic_ulp_stop_one(cp, if_type);
  2510. }
  2511. static void cnic_ulp_start(struct cnic_dev *dev)
  2512. {
  2513. struct cnic_local *cp = dev->cnic_priv;
  2514. int if_type;
  2515. for (if_type = 0; if_type < MAX_CNIC_ULP_TYPE; if_type++) {
  2516. struct cnic_ulp_ops *ulp_ops;
  2517. mutex_lock(&cnic_lock);
  2518. ulp_ops = rcu_dereference_protected(cp->ulp_ops[if_type],
  2519. lockdep_is_held(&cnic_lock));
  2520. if (!ulp_ops || !ulp_ops->cnic_start) {
  2521. mutex_unlock(&cnic_lock);
  2522. continue;
  2523. }
  2524. set_bit(ULP_F_CALL_PENDING, &cp->ulp_flags[if_type]);
  2525. mutex_unlock(&cnic_lock);
  2526. if (!test_and_set_bit(ULP_F_START, &cp->ulp_flags[if_type]))
  2527. ulp_ops->cnic_start(cp->ulp_handle[if_type]);
  2528. clear_bit(ULP_F_CALL_PENDING, &cp->ulp_flags[if_type]);
  2529. }
  2530. }
  2531. static int cnic_ctl(void *data, struct cnic_ctl_info *info)
  2532. {
  2533. struct cnic_dev *dev = data;
  2534. switch (info->cmd) {
  2535. case CNIC_CTL_STOP_CMD:
  2536. cnic_hold(dev);
  2537. cnic_ulp_stop(dev);
  2538. cnic_stop_hw(dev);
  2539. cnic_put(dev);
  2540. break;
  2541. case CNIC_CTL_START_CMD:
  2542. cnic_hold(dev);
  2543. if (!cnic_start_hw(dev))
  2544. cnic_ulp_start(dev);
  2545. cnic_put(dev);
  2546. break;
  2547. case CNIC_CTL_STOP_ISCSI_CMD: {
  2548. struct cnic_local *cp = dev->cnic_priv;
  2549. set_bit(CNIC_LCL_FL_STOP_ISCSI, &cp->cnic_local_flags);
  2550. queue_delayed_work(cnic_wq, &cp->delete_task, 0);
  2551. break;
  2552. }
  2553. case CNIC_CTL_COMPLETION_CMD: {
  2554. struct cnic_ctl_completion *comp = &info->data.comp;
  2555. u32 cid = BNX2X_SW_CID(comp->cid);
  2556. u32 l5_cid;
  2557. struct cnic_local *cp = dev->cnic_priv;
  2558. if (cnic_get_l5_cid(cp, cid, &l5_cid) == 0) {
  2559. struct cnic_context *ctx = &cp->ctx_tbl[l5_cid];
  2560. if (unlikely(comp->error)) {
  2561. set_bit(CTX_FL_CID_ERROR, &ctx->ctx_flags);
  2562. netdev_err(dev->netdev,
  2563. "CID %x CFC delete comp error %x\n",
  2564. cid, comp->error);
  2565. }
  2566. ctx->wait_cond = 1;
  2567. wake_up(&ctx->waitq);
  2568. }
  2569. break;
  2570. }
  2571. default:
  2572. return -EINVAL;
  2573. }
  2574. return 0;
  2575. }
  2576. static void cnic_ulp_init(struct cnic_dev *dev)
  2577. {
  2578. int i;
  2579. struct cnic_local *cp = dev->cnic_priv;
  2580. for (i = 0; i < MAX_CNIC_ULP_TYPE_EXT; i++) {
  2581. struct cnic_ulp_ops *ulp_ops;
  2582. mutex_lock(&cnic_lock);
  2583. ulp_ops = cnic_ulp_tbl_prot(i);
  2584. if (!ulp_ops || !ulp_ops->cnic_init) {
  2585. mutex_unlock(&cnic_lock);
  2586. continue;
  2587. }
  2588. ulp_get(ulp_ops);
  2589. mutex_unlock(&cnic_lock);
  2590. if (!test_and_set_bit(ULP_F_INIT, &cp->ulp_flags[i]))
  2591. ulp_ops->cnic_init(dev);
  2592. ulp_put(ulp_ops);
  2593. }
  2594. }
  2595. static void cnic_ulp_exit(struct cnic_dev *dev)
  2596. {
  2597. int i;
  2598. struct cnic_local *cp = dev->cnic_priv;
  2599. for (i = 0; i < MAX_CNIC_ULP_TYPE_EXT; i++) {
  2600. struct cnic_ulp_ops *ulp_ops;
  2601. mutex_lock(&cnic_lock);
  2602. ulp_ops = cnic_ulp_tbl_prot(i);
  2603. if (!ulp_ops || !ulp_ops->cnic_exit) {
  2604. mutex_unlock(&cnic_lock);
  2605. continue;
  2606. }
  2607. ulp_get(ulp_ops);
  2608. mutex_unlock(&cnic_lock);
  2609. if (test_and_clear_bit(ULP_F_INIT, &cp->ulp_flags[i]))
  2610. ulp_ops->cnic_exit(dev);
  2611. ulp_put(ulp_ops);
  2612. }
  2613. }
  2614. static int cnic_cm_offload_pg(struct cnic_sock *csk)
  2615. {
  2616. struct cnic_dev *dev = csk->dev;
  2617. struct l4_kwq_offload_pg *l4kwqe;
  2618. struct kwqe *wqes[1];
  2619. l4kwqe = (struct l4_kwq_offload_pg *) &csk->kwqe1;
  2620. memset(l4kwqe, 0, sizeof(*l4kwqe));
  2621. wqes[0] = (struct kwqe *) l4kwqe;
  2622. l4kwqe->op_code = L4_KWQE_OPCODE_VALUE_OFFLOAD_PG;
  2623. l4kwqe->flags =
  2624. L4_LAYER_CODE << L4_KWQ_OFFLOAD_PG_LAYER_CODE_SHIFT;
  2625. l4kwqe->l2hdr_nbytes = ETH_HLEN;
  2626. l4kwqe->da0 = csk->ha[0];
  2627. l4kwqe->da1 = csk->ha[1];
  2628. l4kwqe->da2 = csk->ha[2];
  2629. l4kwqe->da3 = csk->ha[3];
  2630. l4kwqe->da4 = csk->ha[4];
  2631. l4kwqe->da5 = csk->ha[5];
  2632. l4kwqe->sa0 = dev->mac_addr[0];
  2633. l4kwqe->sa1 = dev->mac_addr[1];
  2634. l4kwqe->sa2 = dev->mac_addr[2];
  2635. l4kwqe->sa3 = dev->mac_addr[3];
  2636. l4kwqe->sa4 = dev->mac_addr[4];
  2637. l4kwqe->sa5 = dev->mac_addr[5];
  2638. l4kwqe->etype = ETH_P_IP;
  2639. l4kwqe->ipid_start = DEF_IPID_START;
  2640. l4kwqe->host_opaque = csk->l5_cid;
  2641. if (csk->vlan_id) {
  2642. l4kwqe->pg_flags |= L4_KWQ_OFFLOAD_PG_VLAN_TAGGING;
  2643. l4kwqe->vlan_tag = csk->vlan_id;
  2644. l4kwqe->l2hdr_nbytes += 4;
  2645. }
  2646. return dev->submit_kwqes(dev, wqes, 1);
  2647. }
  2648. static int cnic_cm_update_pg(struct cnic_sock *csk)
  2649. {
  2650. struct cnic_dev *dev = csk->dev;
  2651. struct l4_kwq_update_pg *l4kwqe;
  2652. struct kwqe *wqes[1];
  2653. l4kwqe = (struct l4_kwq_update_pg *) &csk->kwqe1;
  2654. memset(l4kwqe, 0, sizeof(*l4kwqe));
  2655. wqes[0] = (struct kwqe *) l4kwqe;
  2656. l4kwqe->opcode = L4_KWQE_OPCODE_VALUE_UPDATE_PG;
  2657. l4kwqe->flags =
  2658. L4_LAYER_CODE << L4_KWQ_UPDATE_PG_LAYER_CODE_SHIFT;
  2659. l4kwqe->pg_cid = csk->pg_cid;
  2660. l4kwqe->da0 = csk->ha[0];
  2661. l4kwqe->da1 = csk->ha[1];
  2662. l4kwqe->da2 = csk->ha[2];
  2663. l4kwqe->da3 = csk->ha[3];
  2664. l4kwqe->da4 = csk->ha[4];
  2665. l4kwqe->da5 = csk->ha[5];
  2666. l4kwqe->pg_host_opaque = csk->l5_cid;
  2667. l4kwqe->pg_valids = L4_KWQ_UPDATE_PG_VALIDS_DA;
  2668. return dev->submit_kwqes(dev, wqes, 1);
  2669. }
  2670. static int cnic_cm_upload_pg(struct cnic_sock *csk)
  2671. {
  2672. struct cnic_dev *dev = csk->dev;
  2673. struct l4_kwq_upload *l4kwqe;
  2674. struct kwqe *wqes[1];
  2675. l4kwqe = (struct l4_kwq_upload *) &csk->kwqe1;
  2676. memset(l4kwqe, 0, sizeof(*l4kwqe));
  2677. wqes[0] = (struct kwqe *) l4kwqe;
  2678. l4kwqe->opcode = L4_KWQE_OPCODE_VALUE_UPLOAD_PG;
  2679. l4kwqe->flags =
  2680. L4_LAYER_CODE << L4_KWQ_UPLOAD_LAYER_CODE_SHIFT;
  2681. l4kwqe->cid = csk->pg_cid;
  2682. return dev->submit_kwqes(dev, wqes, 1);
  2683. }
  2684. static int cnic_cm_conn_req(struct cnic_sock *csk)
  2685. {
  2686. struct cnic_dev *dev = csk->dev;
  2687. struct l4_kwq_connect_req1 *l4kwqe1;
  2688. struct l4_kwq_connect_req2 *l4kwqe2;
  2689. struct l4_kwq_connect_req3 *l4kwqe3;
  2690. struct kwqe *wqes[3];
  2691. u8 tcp_flags = 0;
  2692. int num_wqes = 2;
  2693. l4kwqe1 = (struct l4_kwq_connect_req1 *) &csk->kwqe1;
  2694. l4kwqe2 = (struct l4_kwq_connect_req2 *) &csk->kwqe2;
  2695. l4kwqe3 = (struct l4_kwq_connect_req3 *) &csk->kwqe3;
  2696. memset(l4kwqe1, 0, sizeof(*l4kwqe1));
  2697. memset(l4kwqe2, 0, sizeof(*l4kwqe2));
  2698. memset(l4kwqe3, 0, sizeof(*l4kwqe3));
  2699. l4kwqe3->op_code = L4_KWQE_OPCODE_VALUE_CONNECT3;
  2700. l4kwqe3->flags =
  2701. L4_LAYER_CODE << L4_KWQ_CONNECT_REQ3_LAYER_CODE_SHIFT;
  2702. l4kwqe3->ka_timeout = csk->ka_timeout;
  2703. l4kwqe3->ka_interval = csk->ka_interval;
  2704. l4kwqe3->ka_max_probe_count = csk->ka_max_probe_count;
  2705. l4kwqe3->tos = csk->tos;
  2706. l4kwqe3->ttl = csk->ttl;
  2707. l4kwqe3->snd_seq_scale = csk->snd_seq_scale;
  2708. l4kwqe3->pmtu = csk->mtu;
  2709. l4kwqe3->rcv_buf = csk->rcv_buf;
  2710. l4kwqe3->snd_buf = csk->snd_buf;
  2711. l4kwqe3->seed = csk->seed;
  2712. wqes[0] = (struct kwqe *) l4kwqe1;
  2713. if (test_bit(SK_F_IPV6, &csk->flags)) {
  2714. wqes[1] = (struct kwqe *) l4kwqe2;
  2715. wqes[2] = (struct kwqe *) l4kwqe3;
  2716. num_wqes = 3;
  2717. l4kwqe1->conn_flags = L4_KWQ_CONNECT_REQ1_IP_V6;
  2718. l4kwqe2->op_code = L4_KWQE_OPCODE_VALUE_CONNECT2;
  2719. l4kwqe2->flags =
  2720. L4_KWQ_CONNECT_REQ2_LINKED_WITH_NEXT |
  2721. L4_LAYER_CODE << L4_KWQ_CONNECT_REQ2_LAYER_CODE_SHIFT;
  2722. l4kwqe2->src_ip_v6_2 = be32_to_cpu(csk->src_ip[1]);
  2723. l4kwqe2->src_ip_v6_3 = be32_to_cpu(csk->src_ip[2]);
  2724. l4kwqe2->src_ip_v6_4 = be32_to_cpu(csk->src_ip[3]);
  2725. l4kwqe2->dst_ip_v6_2 = be32_to_cpu(csk->dst_ip[1]);
  2726. l4kwqe2->dst_ip_v6_3 = be32_to_cpu(csk->dst_ip[2]);
  2727. l4kwqe2->dst_ip_v6_4 = be32_to_cpu(csk->dst_ip[3]);
  2728. l4kwqe3->mss = l4kwqe3->pmtu - sizeof(struct ipv6hdr) -
  2729. sizeof(struct tcphdr);
  2730. } else {
  2731. wqes[1] = (struct kwqe *) l4kwqe3;
  2732. l4kwqe3->mss = l4kwqe3->pmtu - sizeof(struct iphdr) -
  2733. sizeof(struct tcphdr);
  2734. }
  2735. l4kwqe1->op_code = L4_KWQE_OPCODE_VALUE_CONNECT1;
  2736. l4kwqe1->flags =
  2737. (L4_LAYER_CODE << L4_KWQ_CONNECT_REQ1_LAYER_CODE_SHIFT) |
  2738. L4_KWQ_CONNECT_REQ3_LINKED_WITH_NEXT;
  2739. l4kwqe1->cid = csk->cid;
  2740. l4kwqe1->pg_cid = csk->pg_cid;
  2741. l4kwqe1->src_ip = be32_to_cpu(csk->src_ip[0]);
  2742. l4kwqe1->dst_ip = be32_to_cpu(csk->dst_ip[0]);
  2743. l4kwqe1->src_port = be16_to_cpu(csk->src_port);
  2744. l4kwqe1->dst_port = be16_to_cpu(csk->dst_port);
  2745. if (csk->tcp_flags & SK_TCP_NO_DELAY_ACK)
  2746. tcp_flags |= L4_KWQ_CONNECT_REQ1_NO_DELAY_ACK;
  2747. if (csk->tcp_flags & SK_TCP_KEEP_ALIVE)
  2748. tcp_flags |= L4_KWQ_CONNECT_REQ1_KEEP_ALIVE;
  2749. if (csk->tcp_flags & SK_TCP_NAGLE)
  2750. tcp_flags |= L4_KWQ_CONNECT_REQ1_NAGLE_ENABLE;
  2751. if (csk->tcp_flags & SK_TCP_TIMESTAMP)
  2752. tcp_flags |= L4_KWQ_CONNECT_REQ1_TIME_STAMP;
  2753. if (csk->tcp_flags & SK_TCP_SACK)
  2754. tcp_flags |= L4_KWQ_CONNECT_REQ1_SACK;
  2755. if (csk->tcp_flags & SK_TCP_SEG_SCALING)
  2756. tcp_flags |= L4_KWQ_CONNECT_REQ1_SEG_SCALING;
  2757. l4kwqe1->tcp_flags = tcp_flags;
  2758. return dev->submit_kwqes(dev, wqes, num_wqes);
  2759. }
  2760. static int cnic_cm_close_req(struct cnic_sock *csk)
  2761. {
  2762. struct cnic_dev *dev = csk->dev;
  2763. struct l4_kwq_close_req *l4kwqe;
  2764. struct kwqe *wqes[1];
  2765. l4kwqe = (struct l4_kwq_close_req *) &csk->kwqe2;
  2766. memset(l4kwqe, 0, sizeof(*l4kwqe));
  2767. wqes[0] = (struct kwqe *) l4kwqe;
  2768. l4kwqe->op_code = L4_KWQE_OPCODE_VALUE_CLOSE;
  2769. l4kwqe->flags = L4_LAYER_CODE << L4_KWQ_CLOSE_REQ_LAYER_CODE_SHIFT;
  2770. l4kwqe->cid = csk->cid;
  2771. return dev->submit_kwqes(dev, wqes, 1);
  2772. }
  2773. static int cnic_cm_abort_req(struct cnic_sock *csk)
  2774. {
  2775. struct cnic_dev *dev = csk->dev;
  2776. struct l4_kwq_reset_req *l4kwqe;
  2777. struct kwqe *wqes[1];
  2778. l4kwqe = (struct l4_kwq_reset_req *) &csk->kwqe2;
  2779. memset(l4kwqe, 0, sizeof(*l4kwqe));
  2780. wqes[0] = (struct kwqe *) l4kwqe;
  2781. l4kwqe->op_code = L4_KWQE_OPCODE_VALUE_RESET;
  2782. l4kwqe->flags = L4_LAYER_CODE << L4_KWQ_RESET_REQ_LAYER_CODE_SHIFT;
  2783. l4kwqe->cid = csk->cid;
  2784. return dev->submit_kwqes(dev, wqes, 1);
  2785. }
  2786. static int cnic_cm_create(struct cnic_dev *dev, int ulp_type, u32 cid,
  2787. u32 l5_cid, struct cnic_sock **csk, void *context)
  2788. {
  2789. struct cnic_local *cp = dev->cnic_priv;
  2790. struct cnic_sock *csk1;
  2791. if (l5_cid >= MAX_CM_SK_TBL_SZ)
  2792. return -EINVAL;
  2793. if (cp->ctx_tbl) {
  2794. struct cnic_context *ctx = &cp->ctx_tbl[l5_cid];
  2795. if (test_bit(CTX_FL_OFFLD_START, &ctx->ctx_flags))
  2796. return -EAGAIN;
  2797. }
  2798. csk1 = &cp->csk_tbl[l5_cid];
  2799. if (atomic_read(&csk1->ref_count))
  2800. return -EAGAIN;
  2801. if (test_and_set_bit(SK_F_INUSE, &csk1->flags))
  2802. return -EBUSY;
  2803. csk1->dev = dev;
  2804. csk1->cid = cid;
  2805. csk1->l5_cid = l5_cid;
  2806. csk1->ulp_type = ulp_type;
  2807. csk1->context = context;
  2808. csk1->ka_timeout = DEF_KA_TIMEOUT;
  2809. csk1->ka_interval = DEF_KA_INTERVAL;
  2810. csk1->ka_max_probe_count = DEF_KA_MAX_PROBE_COUNT;
  2811. csk1->tos = DEF_TOS;
  2812. csk1->ttl = DEF_TTL;
  2813. csk1->snd_seq_scale = DEF_SND_SEQ_SCALE;
  2814. csk1->rcv_buf = DEF_RCV_BUF;
  2815. csk1->snd_buf = DEF_SND_BUF;
  2816. csk1->seed = DEF_SEED;
  2817. *csk = csk1;
  2818. return 0;
  2819. }
  2820. static void cnic_cm_cleanup(struct cnic_sock *csk)
  2821. {
  2822. if (csk->src_port) {
  2823. struct cnic_dev *dev = csk->dev;
  2824. struct cnic_local *cp = dev->cnic_priv;
  2825. cnic_free_id(&cp->csk_port_tbl, be16_to_cpu(csk->src_port));
  2826. csk->src_port = 0;
  2827. }
  2828. }
  2829. static void cnic_close_conn(struct cnic_sock *csk)
  2830. {
  2831. if (test_bit(SK_F_PG_OFFLD_COMPLETE, &csk->flags)) {
  2832. cnic_cm_upload_pg(csk);
  2833. clear_bit(SK_F_PG_OFFLD_COMPLETE, &csk->flags);
  2834. }
  2835. cnic_cm_cleanup(csk);
  2836. }
  2837. static int cnic_cm_destroy(struct cnic_sock *csk)
  2838. {
  2839. if (!cnic_in_use(csk))
  2840. return -EINVAL;
  2841. csk_hold(csk);
  2842. clear_bit(SK_F_INUSE, &csk->flags);
  2843. smp_mb__after_clear_bit();
  2844. while (atomic_read(&csk->ref_count) != 1)
  2845. msleep(1);
  2846. cnic_cm_cleanup(csk);
  2847. csk->flags = 0;
  2848. csk_put(csk);
  2849. return 0;
  2850. }
  2851. static inline u16 cnic_get_vlan(struct net_device *dev,
  2852. struct net_device **vlan_dev)
  2853. {
  2854. if (dev->priv_flags & IFF_802_1Q_VLAN) {
  2855. *vlan_dev = vlan_dev_real_dev(dev);
  2856. return vlan_dev_vlan_id(dev);
  2857. }
  2858. *vlan_dev = dev;
  2859. return 0;
  2860. }
  2861. static int cnic_get_v4_route(struct sockaddr_in *dst_addr,
  2862. struct dst_entry **dst)
  2863. {
  2864. #if defined(CONFIG_INET)
  2865. struct rtable *rt;
  2866. rt = ip_route_output(&init_net, dst_addr->sin_addr.s_addr, 0, 0, 0);
  2867. if (!IS_ERR(rt)) {
  2868. *dst = &rt->dst;
  2869. return 0;
  2870. }
  2871. return PTR_ERR(rt);
  2872. #else
  2873. return -ENETUNREACH;
  2874. #endif
  2875. }
  2876. static int cnic_get_v6_route(struct sockaddr_in6 *dst_addr,
  2877. struct dst_entry **dst)
  2878. {
  2879. #if defined(CONFIG_IPV6) || (defined(CONFIG_IPV6_MODULE) && defined(MODULE))
  2880. struct flowi6 fl6;
  2881. memset(&fl6, 0, sizeof(fl6));
  2882. ipv6_addr_copy(&fl6.daddr, &dst_addr->sin6_addr);
  2883. if (ipv6_addr_type(&fl6.daddr) & IPV6_ADDR_LINKLOCAL)
  2884. fl6.flowi6_oif = dst_addr->sin6_scope_id;
  2885. *dst = ip6_route_output(&init_net, NULL, &fl6);
  2886. if (*dst)
  2887. return 0;
  2888. #endif
  2889. return -ENETUNREACH;
  2890. }
  2891. static struct cnic_dev *cnic_cm_select_dev(struct sockaddr_in *dst_addr,
  2892. int ulp_type)
  2893. {
  2894. struct cnic_dev *dev = NULL;
  2895. struct dst_entry *dst;
  2896. struct net_device *netdev = NULL;
  2897. int err = -ENETUNREACH;
  2898. if (dst_addr->sin_family == AF_INET)
  2899. err = cnic_get_v4_route(dst_addr, &dst);
  2900. else if (dst_addr->sin_family == AF_INET6) {
  2901. struct sockaddr_in6 *dst_addr6 =
  2902. (struct sockaddr_in6 *) dst_addr;
  2903. err = cnic_get_v6_route(dst_addr6, &dst);
  2904. } else
  2905. return NULL;
  2906. if (err)
  2907. return NULL;
  2908. if (!dst->dev)
  2909. goto done;
  2910. cnic_get_vlan(dst->dev, &netdev);
  2911. dev = cnic_from_netdev(netdev);
  2912. done:
  2913. dst_release(dst);
  2914. if (dev)
  2915. cnic_put(dev);
  2916. return dev;
  2917. }
  2918. static int cnic_resolve_addr(struct cnic_sock *csk, struct cnic_sockaddr *saddr)
  2919. {
  2920. struct cnic_dev *dev = csk->dev;
  2921. struct cnic_local *cp = dev->cnic_priv;
  2922. return cnic_send_nlmsg(cp, ISCSI_KEVENT_PATH_REQ, csk);
  2923. }
  2924. static int cnic_get_route(struct cnic_sock *csk, struct cnic_sockaddr *saddr)
  2925. {
  2926. struct cnic_dev *dev = csk->dev;
  2927. struct cnic_local *cp = dev->cnic_priv;
  2928. int is_v6, rc = 0;
  2929. struct dst_entry *dst = NULL;
  2930. struct net_device *realdev;
  2931. __be16 local_port;
  2932. u32 port_id;
  2933. if (saddr->local.v6.sin6_family == AF_INET6 &&
  2934. saddr->remote.v6.sin6_family == AF_INET6)
  2935. is_v6 = 1;
  2936. else if (saddr->local.v4.sin_family == AF_INET &&
  2937. saddr->remote.v4.sin_family == AF_INET)
  2938. is_v6 = 0;
  2939. else
  2940. return -EINVAL;
  2941. clear_bit(SK_F_IPV6, &csk->flags);
  2942. if (is_v6) {
  2943. set_bit(SK_F_IPV6, &csk->flags);
  2944. cnic_get_v6_route(&saddr->remote.v6, &dst);
  2945. memcpy(&csk->dst_ip[0], &saddr->remote.v6.sin6_addr,
  2946. sizeof(struct in6_addr));
  2947. csk->dst_port = saddr->remote.v6.sin6_port;
  2948. local_port = saddr->local.v6.sin6_port;
  2949. } else {
  2950. cnic_get_v4_route(&saddr->remote.v4, &dst);
  2951. csk->dst_ip[0] = saddr->remote.v4.sin_addr.s_addr;
  2952. csk->dst_port = saddr->remote.v4.sin_port;
  2953. local_port = saddr->local.v4.sin_port;
  2954. }
  2955. csk->vlan_id = 0;
  2956. csk->mtu = dev->netdev->mtu;
  2957. if (dst && dst->dev) {
  2958. u16 vlan = cnic_get_vlan(dst->dev, &realdev);
  2959. if (realdev == dev->netdev) {
  2960. csk->vlan_id = vlan;
  2961. csk->mtu = dst_mtu(dst);
  2962. }
  2963. }
  2964. port_id = be16_to_cpu(local_port);
  2965. if (port_id >= CNIC_LOCAL_PORT_MIN &&
  2966. port_id < CNIC_LOCAL_PORT_MAX) {
  2967. if (cnic_alloc_id(&cp->csk_port_tbl, port_id))
  2968. port_id = 0;
  2969. } else
  2970. port_id = 0;
  2971. if (!port_id) {
  2972. port_id = cnic_alloc_new_id(&cp->csk_port_tbl);
  2973. if (port_id == -1) {
  2974. rc = -ENOMEM;
  2975. goto err_out;
  2976. }
  2977. local_port = cpu_to_be16(port_id);
  2978. }
  2979. csk->src_port = local_port;
  2980. err_out:
  2981. dst_release(dst);
  2982. return rc;
  2983. }
  2984. static void cnic_init_csk_state(struct cnic_sock *csk)
  2985. {
  2986. csk->state = 0;
  2987. clear_bit(SK_F_OFFLD_SCHED, &csk->flags);
  2988. clear_bit(SK_F_CLOSING, &csk->flags);
  2989. }
  2990. static int cnic_cm_connect(struct cnic_sock *csk, struct cnic_sockaddr *saddr)
  2991. {
  2992. struct cnic_local *cp = csk->dev->cnic_priv;
  2993. int err = 0;
  2994. if (cp->ethdev->drv_state & CNIC_DRV_STATE_NO_ISCSI)
  2995. return -EOPNOTSUPP;
  2996. if (!cnic_in_use(csk))
  2997. return -EINVAL;
  2998. if (test_and_set_bit(SK_F_CONNECT_START, &csk->flags))
  2999. return -EINVAL;
  3000. cnic_init_csk_state(csk);
  3001. err = cnic_get_route(csk, saddr);
  3002. if (err)
  3003. goto err_out;
  3004. err = cnic_resolve_addr(csk, saddr);
  3005. if (!err)
  3006. return 0;
  3007. err_out:
  3008. clear_bit(SK_F_CONNECT_START, &csk->flags);
  3009. return err;
  3010. }
  3011. static int cnic_cm_abort(struct cnic_sock *csk)
  3012. {
  3013. struct cnic_local *cp = csk->dev->cnic_priv;
  3014. u32 opcode = L4_KCQE_OPCODE_VALUE_RESET_COMP;
  3015. if (!cnic_in_use(csk))
  3016. return -EINVAL;
  3017. if (cnic_abort_prep(csk))
  3018. return cnic_cm_abort_req(csk);
  3019. /* Getting here means that we haven't started connect, or
  3020. * connect was not successful.
  3021. */
  3022. cp->close_conn(csk, opcode);
  3023. if (csk->state != opcode)
  3024. return -EALREADY;
  3025. return 0;
  3026. }
  3027. static int cnic_cm_close(struct cnic_sock *csk)
  3028. {
  3029. if (!cnic_in_use(csk))
  3030. return -EINVAL;
  3031. if (cnic_close_prep(csk)) {
  3032. csk->state = L4_KCQE_OPCODE_VALUE_CLOSE_COMP;
  3033. return cnic_cm_close_req(csk);
  3034. } else {
  3035. return -EALREADY;
  3036. }
  3037. return 0;
  3038. }
  3039. static void cnic_cm_upcall(struct cnic_local *cp, struct cnic_sock *csk,
  3040. u8 opcode)
  3041. {
  3042. struct cnic_ulp_ops *ulp_ops;
  3043. int ulp_type = csk->ulp_type;
  3044. rcu_read_lock();
  3045. ulp_ops = rcu_dereference(cp->ulp_ops[ulp_type]);
  3046. if (ulp_ops) {
  3047. if (opcode == L4_KCQE_OPCODE_VALUE_CONNECT_COMPLETE)
  3048. ulp_ops->cm_connect_complete(csk);
  3049. else if (opcode == L4_KCQE_OPCODE_VALUE_CLOSE_COMP)
  3050. ulp_ops->cm_close_complete(csk);
  3051. else if (opcode == L4_KCQE_OPCODE_VALUE_RESET_RECEIVED)
  3052. ulp_ops->cm_remote_abort(csk);
  3053. else if (opcode == L4_KCQE_OPCODE_VALUE_RESET_COMP)
  3054. ulp_ops->cm_abort_complete(csk);
  3055. else if (opcode == L4_KCQE_OPCODE_VALUE_CLOSE_RECEIVED)
  3056. ulp_ops->cm_remote_close(csk);
  3057. }
  3058. rcu_read_unlock();
  3059. }
  3060. static int cnic_cm_set_pg(struct cnic_sock *csk)
  3061. {
  3062. if (cnic_offld_prep(csk)) {
  3063. if (test_bit(SK_F_PG_OFFLD_COMPLETE, &csk->flags))
  3064. cnic_cm_update_pg(csk);
  3065. else
  3066. cnic_cm_offload_pg(csk);
  3067. }
  3068. return 0;
  3069. }
  3070. static void cnic_cm_process_offld_pg(struct cnic_dev *dev, struct l4_kcq *kcqe)
  3071. {
  3072. struct cnic_local *cp = dev->cnic_priv;
  3073. u32 l5_cid = kcqe->pg_host_opaque;
  3074. u8 opcode = kcqe->op_code;
  3075. struct cnic_sock *csk = &cp->csk_tbl[l5_cid];
  3076. csk_hold(csk);
  3077. if (!cnic_in_use(csk))
  3078. goto done;
  3079. if (opcode == L4_KCQE_OPCODE_VALUE_UPDATE_PG) {
  3080. clear_bit(SK_F_OFFLD_SCHED, &csk->flags);
  3081. goto done;
  3082. }
  3083. /* Possible PG kcqe status: SUCCESS, OFFLOADED_PG, or CTX_ALLOC_FAIL */
  3084. if (kcqe->status == L4_KCQE_COMPLETION_STATUS_CTX_ALLOC_FAIL) {
  3085. clear_bit(SK_F_OFFLD_SCHED, &csk->flags);
  3086. cnic_cm_upcall(cp, csk,
  3087. L4_KCQE_OPCODE_VALUE_CONNECT_COMPLETE);
  3088. goto done;
  3089. }
  3090. csk->pg_cid = kcqe->pg_cid;
  3091. set_bit(SK_F_PG_OFFLD_COMPLETE, &csk->flags);
  3092. cnic_cm_conn_req(csk);
  3093. done:
  3094. csk_put(csk);
  3095. }
  3096. static void cnic_process_fcoe_term_conn(struct cnic_dev *dev, struct kcqe *kcqe)
  3097. {
  3098. struct cnic_local *cp = dev->cnic_priv;
  3099. struct fcoe_kcqe *fc_kcqe = (struct fcoe_kcqe *) kcqe;
  3100. u32 l5_cid = fc_kcqe->fcoe_conn_id + BNX2X_FCOE_L5_CID_BASE;
  3101. struct cnic_context *ctx = &cp->ctx_tbl[l5_cid];
  3102. ctx->timestamp = jiffies;
  3103. ctx->wait_cond = 1;
  3104. wake_up(&ctx->waitq);
  3105. }
  3106. static void cnic_cm_process_kcqe(struct cnic_dev *dev, struct kcqe *kcqe)
  3107. {
  3108. struct cnic_local *cp = dev->cnic_priv;
  3109. struct l4_kcq *l4kcqe = (struct l4_kcq *) kcqe;
  3110. u8 opcode = l4kcqe->op_code;
  3111. u32 l5_cid;
  3112. struct cnic_sock *csk;
  3113. if (opcode == FCOE_RAMROD_CMD_ID_TERMINATE_CONN) {
  3114. cnic_process_fcoe_term_conn(dev, kcqe);
  3115. return;
  3116. }
  3117. if (opcode == L4_KCQE_OPCODE_VALUE_OFFLOAD_PG ||
  3118. opcode == L4_KCQE_OPCODE_VALUE_UPDATE_PG) {
  3119. cnic_cm_process_offld_pg(dev, l4kcqe);
  3120. return;
  3121. }
  3122. l5_cid = l4kcqe->conn_id;
  3123. if (opcode & 0x80)
  3124. l5_cid = l4kcqe->cid;
  3125. if (l5_cid >= MAX_CM_SK_TBL_SZ)
  3126. return;
  3127. csk = &cp->csk_tbl[l5_cid];
  3128. csk_hold(csk);
  3129. if (!cnic_in_use(csk)) {
  3130. csk_put(csk);
  3131. return;
  3132. }
  3133. switch (opcode) {
  3134. case L5CM_RAMROD_CMD_ID_TCP_CONNECT:
  3135. if (l4kcqe->status != 0) {
  3136. clear_bit(SK_F_OFFLD_SCHED, &csk->flags);
  3137. cnic_cm_upcall(cp, csk,
  3138. L4_KCQE_OPCODE_VALUE_CONNECT_COMPLETE);
  3139. }
  3140. break;
  3141. case L4_KCQE_OPCODE_VALUE_CONNECT_COMPLETE:
  3142. if (l4kcqe->status == 0)
  3143. set_bit(SK_F_OFFLD_COMPLETE, &csk->flags);
  3144. smp_mb__before_clear_bit();
  3145. clear_bit(SK_F_OFFLD_SCHED, &csk->flags);
  3146. cnic_cm_upcall(cp, csk, opcode);
  3147. break;
  3148. case L4_KCQE_OPCODE_VALUE_RESET_RECEIVED:
  3149. case L4_KCQE_OPCODE_VALUE_CLOSE_COMP:
  3150. case L4_KCQE_OPCODE_VALUE_RESET_COMP:
  3151. case L5CM_RAMROD_CMD_ID_SEARCHER_DELETE:
  3152. case L5CM_RAMROD_CMD_ID_TERMINATE_OFFLOAD:
  3153. cp->close_conn(csk, opcode);
  3154. break;
  3155. case L4_KCQE_OPCODE_VALUE_CLOSE_RECEIVED:
  3156. /* after we already sent CLOSE_REQ */
  3157. if (test_bit(CNIC_F_BNX2X_CLASS, &dev->flags) &&
  3158. !test_bit(SK_F_OFFLD_COMPLETE, &csk->flags) &&
  3159. csk->state == L4_KCQE_OPCODE_VALUE_CLOSE_COMP)
  3160. cp->close_conn(csk, L4_KCQE_OPCODE_VALUE_RESET_COMP);
  3161. else
  3162. cnic_cm_upcall(cp, csk, opcode);
  3163. break;
  3164. }
  3165. csk_put(csk);
  3166. }
  3167. static void cnic_cm_indicate_kcqe(void *data, struct kcqe *kcqe[], u32 num)
  3168. {
  3169. struct cnic_dev *dev = data;
  3170. int i;
  3171. for (i = 0; i < num; i++)
  3172. cnic_cm_process_kcqe(dev, kcqe[i]);
  3173. }
  3174. static struct cnic_ulp_ops cm_ulp_ops = {
  3175. .indicate_kcqes = cnic_cm_indicate_kcqe,
  3176. };
  3177. static void cnic_cm_free_mem(struct cnic_dev *dev)
  3178. {
  3179. struct cnic_local *cp = dev->cnic_priv;
  3180. kfree(cp->csk_tbl);
  3181. cp->csk_tbl = NULL;
  3182. cnic_free_id_tbl(&cp->csk_port_tbl);
  3183. }
  3184. static int cnic_cm_alloc_mem(struct cnic_dev *dev)
  3185. {
  3186. struct cnic_local *cp = dev->cnic_priv;
  3187. u32 port_id;
  3188. cp->csk_tbl = kzalloc(sizeof(struct cnic_sock) * MAX_CM_SK_TBL_SZ,
  3189. GFP_KERNEL);
  3190. if (!cp->csk_tbl)
  3191. return -ENOMEM;
  3192. port_id = random32();
  3193. port_id %= CNIC_LOCAL_PORT_RANGE;
  3194. if (cnic_init_id_tbl(&cp->csk_port_tbl, CNIC_LOCAL_PORT_RANGE,
  3195. CNIC_LOCAL_PORT_MIN, port_id)) {
  3196. cnic_cm_free_mem(dev);
  3197. return -ENOMEM;
  3198. }
  3199. return 0;
  3200. }
  3201. static int cnic_ready_to_close(struct cnic_sock *csk, u32 opcode)
  3202. {
  3203. if (test_and_clear_bit(SK_F_OFFLD_COMPLETE, &csk->flags)) {
  3204. /* Unsolicited RESET_COMP or RESET_RECEIVED */
  3205. opcode = L4_KCQE_OPCODE_VALUE_RESET_RECEIVED;
  3206. csk->state = opcode;
  3207. }
  3208. /* 1. If event opcode matches the expected event in csk->state
  3209. * 2. If the expected event is CLOSE_COMP or RESET_COMP, we accept any
  3210. * event
  3211. * 3. If the expected event is 0, meaning the connection was never
  3212. * never established, we accept the opcode from cm_abort.
  3213. */
  3214. if (opcode == csk->state || csk->state == 0 ||
  3215. csk->state == L4_KCQE_OPCODE_VALUE_CLOSE_COMP ||
  3216. csk->state == L4_KCQE_OPCODE_VALUE_RESET_COMP) {
  3217. if (!test_and_set_bit(SK_F_CLOSING, &csk->flags)) {
  3218. if (csk->state == 0)
  3219. csk->state = opcode;
  3220. return 1;
  3221. }
  3222. }
  3223. return 0;
  3224. }
  3225. static void cnic_close_bnx2_conn(struct cnic_sock *csk, u32 opcode)
  3226. {
  3227. struct cnic_dev *dev = csk->dev;
  3228. struct cnic_local *cp = dev->cnic_priv;
  3229. if (opcode == L4_KCQE_OPCODE_VALUE_RESET_RECEIVED) {
  3230. cnic_cm_upcall(cp, csk, opcode);
  3231. return;
  3232. }
  3233. clear_bit(SK_F_CONNECT_START, &csk->flags);
  3234. cnic_close_conn(csk);
  3235. csk->state = opcode;
  3236. cnic_cm_upcall(cp, csk, opcode);
  3237. }
  3238. static void cnic_cm_stop_bnx2_hw(struct cnic_dev *dev)
  3239. {
  3240. }
  3241. static int cnic_cm_init_bnx2_hw(struct cnic_dev *dev)
  3242. {
  3243. u32 seed;
  3244. seed = random32();
  3245. cnic_ctx_wr(dev, 45, 0, seed);
  3246. return 0;
  3247. }
  3248. static void cnic_close_bnx2x_conn(struct cnic_sock *csk, u32 opcode)
  3249. {
  3250. struct cnic_dev *dev = csk->dev;
  3251. struct cnic_local *cp = dev->cnic_priv;
  3252. struct cnic_context *ctx = &cp->ctx_tbl[csk->l5_cid];
  3253. union l5cm_specific_data l5_data;
  3254. u32 cmd = 0;
  3255. int close_complete = 0;
  3256. switch (opcode) {
  3257. case L4_KCQE_OPCODE_VALUE_RESET_RECEIVED:
  3258. case L4_KCQE_OPCODE_VALUE_CLOSE_COMP:
  3259. case L4_KCQE_OPCODE_VALUE_RESET_COMP:
  3260. if (cnic_ready_to_close(csk, opcode)) {
  3261. if (test_bit(SK_F_PG_OFFLD_COMPLETE, &csk->flags))
  3262. cmd = L5CM_RAMROD_CMD_ID_SEARCHER_DELETE;
  3263. else
  3264. close_complete = 1;
  3265. }
  3266. break;
  3267. case L5CM_RAMROD_CMD_ID_SEARCHER_DELETE:
  3268. cmd = L5CM_RAMROD_CMD_ID_TERMINATE_OFFLOAD;
  3269. break;
  3270. case L5CM_RAMROD_CMD_ID_TERMINATE_OFFLOAD:
  3271. close_complete = 1;
  3272. break;
  3273. }
  3274. if (cmd) {
  3275. memset(&l5_data, 0, sizeof(l5_data));
  3276. cnic_submit_kwqe_16(dev, cmd, csk->cid, ISCSI_CONNECTION_TYPE,
  3277. &l5_data);
  3278. } else if (close_complete) {
  3279. ctx->timestamp = jiffies;
  3280. cnic_close_conn(csk);
  3281. cnic_cm_upcall(cp, csk, csk->state);
  3282. }
  3283. }
  3284. static void cnic_cm_stop_bnx2x_hw(struct cnic_dev *dev)
  3285. {
  3286. struct cnic_local *cp = dev->cnic_priv;
  3287. if (!cp->ctx_tbl)
  3288. return;
  3289. if (!netif_running(dev->netdev))
  3290. return;
  3291. cnic_bnx2x_delete_wait(dev, 0);
  3292. cancel_delayed_work(&cp->delete_task);
  3293. flush_workqueue(cnic_wq);
  3294. if (atomic_read(&cp->iscsi_conn) != 0)
  3295. netdev_warn(dev->netdev, "%d iSCSI connections not destroyed\n",
  3296. atomic_read(&cp->iscsi_conn));
  3297. }
  3298. static int cnic_cm_init_bnx2x_hw(struct cnic_dev *dev)
  3299. {
  3300. struct cnic_local *cp = dev->cnic_priv;
  3301. u32 pfid = cp->pfid;
  3302. u32 port = CNIC_PORT(cp);
  3303. cnic_init_bnx2x_mac(dev);
  3304. cnic_bnx2x_set_tcp_timestamp(dev, 1);
  3305. CNIC_WR16(dev, BAR_XSTRORM_INTMEM +
  3306. XSTORM_ISCSI_LOCAL_VLAN_OFFSET(pfid), 0);
  3307. CNIC_WR(dev, BAR_XSTRORM_INTMEM +
  3308. XSTORM_TCP_GLOBAL_DEL_ACK_COUNTER_ENABLED_OFFSET(port), 1);
  3309. CNIC_WR(dev, BAR_XSTRORM_INTMEM +
  3310. XSTORM_TCP_GLOBAL_DEL_ACK_COUNTER_MAX_COUNT_OFFSET(port),
  3311. DEF_MAX_DA_COUNT);
  3312. CNIC_WR8(dev, BAR_XSTRORM_INTMEM +
  3313. XSTORM_ISCSI_TCP_VARS_TTL_OFFSET(pfid), DEF_TTL);
  3314. CNIC_WR8(dev, BAR_XSTRORM_INTMEM +
  3315. XSTORM_ISCSI_TCP_VARS_TOS_OFFSET(pfid), DEF_TOS);
  3316. CNIC_WR8(dev, BAR_XSTRORM_INTMEM +
  3317. XSTORM_ISCSI_TCP_VARS_ADV_WND_SCL_OFFSET(pfid), 2);
  3318. CNIC_WR(dev, BAR_XSTRORM_INTMEM +
  3319. XSTORM_TCP_TX_SWS_TIMER_VAL_OFFSET(pfid), DEF_SWS_TIMER);
  3320. CNIC_WR(dev, BAR_TSTRORM_INTMEM + TSTORM_TCP_MAX_CWND_OFFSET(pfid),
  3321. DEF_MAX_CWND);
  3322. return 0;
  3323. }
  3324. static void cnic_delete_task(struct work_struct *work)
  3325. {
  3326. struct cnic_local *cp;
  3327. struct cnic_dev *dev;
  3328. u32 i;
  3329. int need_resched = 0;
  3330. cp = container_of(work, struct cnic_local, delete_task.work);
  3331. dev = cp->dev;
  3332. if (test_and_clear_bit(CNIC_LCL_FL_STOP_ISCSI, &cp->cnic_local_flags)) {
  3333. struct drv_ctl_info info;
  3334. cnic_ulp_stop_one(cp, CNIC_ULP_ISCSI);
  3335. info.cmd = DRV_CTL_ISCSI_STOPPED_CMD;
  3336. cp->ethdev->drv_ctl(dev->netdev, &info);
  3337. }
  3338. for (i = 0; i < cp->max_cid_space; i++) {
  3339. struct cnic_context *ctx = &cp->ctx_tbl[i];
  3340. int err;
  3341. if (!test_bit(CTX_FL_OFFLD_START, &ctx->ctx_flags) ||
  3342. !test_bit(CTX_FL_DELETE_WAIT, &ctx->ctx_flags))
  3343. continue;
  3344. if (!time_after(jiffies, ctx->timestamp + (2 * HZ))) {
  3345. need_resched = 1;
  3346. continue;
  3347. }
  3348. if (!test_and_clear_bit(CTX_FL_DELETE_WAIT, &ctx->ctx_flags))
  3349. continue;
  3350. err = cnic_bnx2x_destroy_ramrod(dev, i);
  3351. cnic_free_bnx2x_conn_resc(dev, i);
  3352. if (!err) {
  3353. if (ctx->ulp_proto_id == CNIC_ULP_ISCSI)
  3354. atomic_dec(&cp->iscsi_conn);
  3355. clear_bit(CTX_FL_OFFLD_START, &ctx->ctx_flags);
  3356. }
  3357. }
  3358. if (need_resched)
  3359. queue_delayed_work(cnic_wq, &cp->delete_task,
  3360. msecs_to_jiffies(10));
  3361. }
  3362. static int cnic_cm_open(struct cnic_dev *dev)
  3363. {
  3364. struct cnic_local *cp = dev->cnic_priv;
  3365. int err;
  3366. err = cnic_cm_alloc_mem(dev);
  3367. if (err)
  3368. return err;
  3369. err = cp->start_cm(dev);
  3370. if (err)
  3371. goto err_out;
  3372. INIT_DELAYED_WORK(&cp->delete_task, cnic_delete_task);
  3373. dev->cm_create = cnic_cm_create;
  3374. dev->cm_destroy = cnic_cm_destroy;
  3375. dev->cm_connect = cnic_cm_connect;
  3376. dev->cm_abort = cnic_cm_abort;
  3377. dev->cm_close = cnic_cm_close;
  3378. dev->cm_select_dev = cnic_cm_select_dev;
  3379. cp->ulp_handle[CNIC_ULP_L4] = dev;
  3380. rcu_assign_pointer(cp->ulp_ops[CNIC_ULP_L4], &cm_ulp_ops);
  3381. return 0;
  3382. err_out:
  3383. cnic_cm_free_mem(dev);
  3384. return err;
  3385. }
  3386. static int cnic_cm_shutdown(struct cnic_dev *dev)
  3387. {
  3388. struct cnic_local *cp = dev->cnic_priv;
  3389. int i;
  3390. cp->stop_cm(dev);
  3391. if (!cp->csk_tbl)
  3392. return 0;
  3393. for (i = 0; i < MAX_CM_SK_TBL_SZ; i++) {
  3394. struct cnic_sock *csk = &cp->csk_tbl[i];
  3395. clear_bit(SK_F_INUSE, &csk->flags);
  3396. cnic_cm_cleanup(csk);
  3397. }
  3398. cnic_cm_free_mem(dev);
  3399. return 0;
  3400. }
  3401. static void cnic_init_context(struct cnic_dev *dev, u32 cid)
  3402. {
  3403. u32 cid_addr;
  3404. int i;
  3405. cid_addr = GET_CID_ADDR(cid);
  3406. for (i = 0; i < CTX_SIZE; i += 4)
  3407. cnic_ctx_wr(dev, cid_addr, i, 0);
  3408. }
  3409. static int cnic_setup_5709_context(struct cnic_dev *dev, int valid)
  3410. {
  3411. struct cnic_local *cp = dev->cnic_priv;
  3412. int ret = 0, i;
  3413. u32 valid_bit = valid ? BNX2_CTX_HOST_PAGE_TBL_DATA0_VALID : 0;
  3414. if (CHIP_NUM(cp) != CHIP_NUM_5709)
  3415. return 0;
  3416. for (i = 0; i < cp->ctx_blks; i++) {
  3417. int j;
  3418. u32 idx = cp->ctx_arr[i].cid / cp->cids_per_blk;
  3419. u32 val;
  3420. memset(cp->ctx_arr[i].ctx, 0, BCM_PAGE_SIZE);
  3421. CNIC_WR(dev, BNX2_CTX_HOST_PAGE_TBL_DATA0,
  3422. (cp->ctx_arr[i].mapping & 0xffffffff) | valid_bit);
  3423. CNIC_WR(dev, BNX2_CTX_HOST_PAGE_TBL_DATA1,
  3424. (u64) cp->ctx_arr[i].mapping >> 32);
  3425. CNIC_WR(dev, BNX2_CTX_HOST_PAGE_TBL_CTRL, idx |
  3426. BNX2_CTX_HOST_PAGE_TBL_CTRL_WRITE_REQ);
  3427. for (j = 0; j < 10; j++) {
  3428. val = CNIC_RD(dev, BNX2_CTX_HOST_PAGE_TBL_CTRL);
  3429. if (!(val & BNX2_CTX_HOST_PAGE_TBL_CTRL_WRITE_REQ))
  3430. break;
  3431. udelay(5);
  3432. }
  3433. if (val & BNX2_CTX_HOST_PAGE_TBL_CTRL_WRITE_REQ) {
  3434. ret = -EBUSY;
  3435. break;
  3436. }
  3437. }
  3438. return ret;
  3439. }
  3440. static void cnic_free_irq(struct cnic_dev *dev)
  3441. {
  3442. struct cnic_local *cp = dev->cnic_priv;
  3443. struct cnic_eth_dev *ethdev = cp->ethdev;
  3444. if (ethdev->drv_state & CNIC_DRV_STATE_USING_MSIX) {
  3445. cp->disable_int_sync(dev);
  3446. tasklet_kill(&cp->cnic_irq_task);
  3447. free_irq(ethdev->irq_arr[0].vector, dev);
  3448. }
  3449. }
  3450. static int cnic_request_irq(struct cnic_dev *dev)
  3451. {
  3452. struct cnic_local *cp = dev->cnic_priv;
  3453. struct cnic_eth_dev *ethdev = cp->ethdev;
  3454. int err;
  3455. err = request_irq(ethdev->irq_arr[0].vector, cnic_irq, 0, "cnic", dev);
  3456. if (err)
  3457. tasklet_disable(&cp->cnic_irq_task);
  3458. return err;
  3459. }
  3460. static int cnic_init_bnx2_irq(struct cnic_dev *dev)
  3461. {
  3462. struct cnic_local *cp = dev->cnic_priv;
  3463. struct cnic_eth_dev *ethdev = cp->ethdev;
  3464. if (ethdev->drv_state & CNIC_DRV_STATE_USING_MSIX) {
  3465. int err, i = 0;
  3466. int sblk_num = cp->status_blk_num;
  3467. u32 base = ((sblk_num - 1) * BNX2_HC_SB_CONFIG_SIZE) +
  3468. BNX2_HC_SB_CONFIG_1;
  3469. CNIC_WR(dev, base, BNX2_HC_SB_CONFIG_1_ONE_SHOT);
  3470. CNIC_WR(dev, base + BNX2_HC_COMP_PROD_TRIP_OFF, (2 << 16) | 8);
  3471. CNIC_WR(dev, base + BNX2_HC_COM_TICKS_OFF, (64 << 16) | 220);
  3472. CNIC_WR(dev, base + BNX2_HC_CMD_TICKS_OFF, (64 << 16) | 220);
  3473. cp->last_status_idx = cp->status_blk.bnx2->status_idx;
  3474. tasklet_init(&cp->cnic_irq_task, cnic_service_bnx2_msix,
  3475. (unsigned long) dev);
  3476. err = cnic_request_irq(dev);
  3477. if (err)
  3478. return err;
  3479. while (cp->status_blk.bnx2->status_completion_producer_index &&
  3480. i < 10) {
  3481. CNIC_WR(dev, BNX2_HC_COALESCE_NOW,
  3482. 1 << (11 + sblk_num));
  3483. udelay(10);
  3484. i++;
  3485. barrier();
  3486. }
  3487. if (cp->status_blk.bnx2->status_completion_producer_index) {
  3488. cnic_free_irq(dev);
  3489. goto failed;
  3490. }
  3491. } else {
  3492. struct status_block *sblk = cp->status_blk.gen;
  3493. u32 hc_cmd = CNIC_RD(dev, BNX2_HC_COMMAND);
  3494. int i = 0;
  3495. while (sblk->status_completion_producer_index && i < 10) {
  3496. CNIC_WR(dev, BNX2_HC_COMMAND,
  3497. hc_cmd | BNX2_HC_COMMAND_COAL_NOW_WO_INT);
  3498. udelay(10);
  3499. i++;
  3500. barrier();
  3501. }
  3502. if (sblk->status_completion_producer_index)
  3503. goto failed;
  3504. }
  3505. return 0;
  3506. failed:
  3507. netdev_err(dev->netdev, "KCQ index not resetting to 0\n");
  3508. return -EBUSY;
  3509. }
  3510. static void cnic_enable_bnx2_int(struct cnic_dev *dev)
  3511. {
  3512. struct cnic_local *cp = dev->cnic_priv;
  3513. struct cnic_eth_dev *ethdev = cp->ethdev;
  3514. if (!(ethdev->drv_state & CNIC_DRV_STATE_USING_MSIX))
  3515. return;
  3516. CNIC_WR(dev, BNX2_PCICFG_INT_ACK_CMD, cp->int_num |
  3517. BNX2_PCICFG_INT_ACK_CMD_INDEX_VALID | cp->last_status_idx);
  3518. }
  3519. static void cnic_disable_bnx2_int_sync(struct cnic_dev *dev)
  3520. {
  3521. struct cnic_local *cp = dev->cnic_priv;
  3522. struct cnic_eth_dev *ethdev = cp->ethdev;
  3523. if (!(ethdev->drv_state & CNIC_DRV_STATE_USING_MSIX))
  3524. return;
  3525. CNIC_WR(dev, BNX2_PCICFG_INT_ACK_CMD, cp->int_num |
  3526. BNX2_PCICFG_INT_ACK_CMD_MASK_INT);
  3527. CNIC_RD(dev, BNX2_PCICFG_INT_ACK_CMD);
  3528. synchronize_irq(ethdev->irq_arr[0].vector);
  3529. }
  3530. static void cnic_init_bnx2_tx_ring(struct cnic_dev *dev)
  3531. {
  3532. struct cnic_local *cp = dev->cnic_priv;
  3533. struct cnic_eth_dev *ethdev = cp->ethdev;
  3534. struct cnic_uio_dev *udev = cp->udev;
  3535. u32 cid_addr, tx_cid, sb_id;
  3536. u32 val, offset0, offset1, offset2, offset3;
  3537. int i;
  3538. struct tx_bd *txbd;
  3539. dma_addr_t buf_map, ring_map = udev->l2_ring_map;
  3540. struct status_block *s_blk = cp->status_blk.gen;
  3541. sb_id = cp->status_blk_num;
  3542. tx_cid = 20;
  3543. cp->tx_cons_ptr = &s_blk->status_tx_quick_consumer_index2;
  3544. if (ethdev->drv_state & CNIC_DRV_STATE_USING_MSIX) {
  3545. struct status_block_msix *sblk = cp->status_blk.bnx2;
  3546. tx_cid = TX_TSS_CID + sb_id - 1;
  3547. CNIC_WR(dev, BNX2_TSCH_TSS_CFG, (sb_id << 24) |
  3548. (TX_TSS_CID << 7));
  3549. cp->tx_cons_ptr = &sblk->status_tx_quick_consumer_index;
  3550. }
  3551. cp->tx_cons = *cp->tx_cons_ptr;
  3552. cid_addr = GET_CID_ADDR(tx_cid);
  3553. if (CHIP_NUM(cp) == CHIP_NUM_5709) {
  3554. u32 cid_addr2 = GET_CID_ADDR(tx_cid + 4) + 0x40;
  3555. for (i = 0; i < PHY_CTX_SIZE; i += 4)
  3556. cnic_ctx_wr(dev, cid_addr2, i, 0);
  3557. offset0 = BNX2_L2CTX_TYPE_XI;
  3558. offset1 = BNX2_L2CTX_CMD_TYPE_XI;
  3559. offset2 = BNX2_L2CTX_TBDR_BHADDR_HI_XI;
  3560. offset3 = BNX2_L2CTX_TBDR_BHADDR_LO_XI;
  3561. } else {
  3562. cnic_init_context(dev, tx_cid);
  3563. cnic_init_context(dev, tx_cid + 1);
  3564. offset0 = BNX2_L2CTX_TYPE;
  3565. offset1 = BNX2_L2CTX_CMD_TYPE;
  3566. offset2 = BNX2_L2CTX_TBDR_BHADDR_HI;
  3567. offset3 = BNX2_L2CTX_TBDR_BHADDR_LO;
  3568. }
  3569. val = BNX2_L2CTX_TYPE_TYPE_L2 | BNX2_L2CTX_TYPE_SIZE_L2;
  3570. cnic_ctx_wr(dev, cid_addr, offset0, val);
  3571. val = BNX2_L2CTX_CMD_TYPE_TYPE_L2 | (8 << 16);
  3572. cnic_ctx_wr(dev, cid_addr, offset1, val);
  3573. txbd = udev->l2_ring;
  3574. buf_map = udev->l2_buf_map;
  3575. for (i = 0; i < MAX_TX_DESC_CNT; i++, txbd++) {
  3576. txbd->tx_bd_haddr_hi = (u64) buf_map >> 32;
  3577. txbd->tx_bd_haddr_lo = (u64) buf_map & 0xffffffff;
  3578. }
  3579. val = (u64) ring_map >> 32;
  3580. cnic_ctx_wr(dev, cid_addr, offset2, val);
  3581. txbd->tx_bd_haddr_hi = val;
  3582. val = (u64) ring_map & 0xffffffff;
  3583. cnic_ctx_wr(dev, cid_addr, offset3, val);
  3584. txbd->tx_bd_haddr_lo = val;
  3585. }
  3586. static void cnic_init_bnx2_rx_ring(struct cnic_dev *dev)
  3587. {
  3588. struct cnic_local *cp = dev->cnic_priv;
  3589. struct cnic_eth_dev *ethdev = cp->ethdev;
  3590. struct cnic_uio_dev *udev = cp->udev;
  3591. u32 cid_addr, sb_id, val, coal_reg, coal_val;
  3592. int i;
  3593. struct rx_bd *rxbd;
  3594. struct status_block *s_blk = cp->status_blk.gen;
  3595. dma_addr_t ring_map = udev->l2_ring_map;
  3596. sb_id = cp->status_blk_num;
  3597. cnic_init_context(dev, 2);
  3598. cp->rx_cons_ptr = &s_blk->status_rx_quick_consumer_index2;
  3599. coal_reg = BNX2_HC_COMMAND;
  3600. coal_val = CNIC_RD(dev, coal_reg);
  3601. if (ethdev->drv_state & CNIC_DRV_STATE_USING_MSIX) {
  3602. struct status_block_msix *sblk = cp->status_blk.bnx2;
  3603. cp->rx_cons_ptr = &sblk->status_rx_quick_consumer_index;
  3604. coal_reg = BNX2_HC_COALESCE_NOW;
  3605. coal_val = 1 << (11 + sb_id);
  3606. }
  3607. i = 0;
  3608. while (!(*cp->rx_cons_ptr != 0) && i < 10) {
  3609. CNIC_WR(dev, coal_reg, coal_val);
  3610. udelay(10);
  3611. i++;
  3612. barrier();
  3613. }
  3614. cp->rx_cons = *cp->rx_cons_ptr;
  3615. cid_addr = GET_CID_ADDR(2);
  3616. val = BNX2_L2CTX_CTX_TYPE_CTX_BD_CHN_TYPE_VALUE |
  3617. BNX2_L2CTX_CTX_TYPE_SIZE_L2 | (0x02 << 8);
  3618. cnic_ctx_wr(dev, cid_addr, BNX2_L2CTX_CTX_TYPE, val);
  3619. if (sb_id == 0)
  3620. val = 2 << BNX2_L2CTX_L2_STATUSB_NUM_SHIFT;
  3621. else
  3622. val = BNX2_L2CTX_L2_STATUSB_NUM(sb_id);
  3623. cnic_ctx_wr(dev, cid_addr, BNX2_L2CTX_HOST_BDIDX, val);
  3624. rxbd = udev->l2_ring + BCM_PAGE_SIZE;
  3625. for (i = 0; i < MAX_RX_DESC_CNT; i++, rxbd++) {
  3626. dma_addr_t buf_map;
  3627. int n = (i % cp->l2_rx_ring_size) + 1;
  3628. buf_map = udev->l2_buf_map + (n * cp->l2_single_buf_size);
  3629. rxbd->rx_bd_len = cp->l2_single_buf_size;
  3630. rxbd->rx_bd_flags = RX_BD_FLAGS_START | RX_BD_FLAGS_END;
  3631. rxbd->rx_bd_haddr_hi = (u64) buf_map >> 32;
  3632. rxbd->rx_bd_haddr_lo = (u64) buf_map & 0xffffffff;
  3633. }
  3634. val = (u64) (ring_map + BCM_PAGE_SIZE) >> 32;
  3635. cnic_ctx_wr(dev, cid_addr, BNX2_L2CTX_NX_BDHADDR_HI, val);
  3636. rxbd->rx_bd_haddr_hi = val;
  3637. val = (u64) (ring_map + BCM_PAGE_SIZE) & 0xffffffff;
  3638. cnic_ctx_wr(dev, cid_addr, BNX2_L2CTX_NX_BDHADDR_LO, val);
  3639. rxbd->rx_bd_haddr_lo = val;
  3640. val = cnic_reg_rd_ind(dev, BNX2_RXP_SCRATCH_RXP_FLOOD);
  3641. cnic_reg_wr_ind(dev, BNX2_RXP_SCRATCH_RXP_FLOOD, val | (1 << 2));
  3642. }
  3643. static void cnic_shutdown_bnx2_rx_ring(struct cnic_dev *dev)
  3644. {
  3645. struct kwqe *wqes[1], l2kwqe;
  3646. memset(&l2kwqe, 0, sizeof(l2kwqe));
  3647. wqes[0] = &l2kwqe;
  3648. l2kwqe.kwqe_op_flag = (L2_LAYER_CODE << KWQE_LAYER_SHIFT) |
  3649. (L2_KWQE_OPCODE_VALUE_FLUSH <<
  3650. KWQE_OPCODE_SHIFT) | 2;
  3651. dev->submit_kwqes(dev, wqes, 1);
  3652. }
  3653. static void cnic_set_bnx2_mac(struct cnic_dev *dev)
  3654. {
  3655. struct cnic_local *cp = dev->cnic_priv;
  3656. u32 val;
  3657. val = cp->func << 2;
  3658. cp->shmem_base = cnic_reg_rd_ind(dev, BNX2_SHM_HDR_ADDR_0 + val);
  3659. val = cnic_reg_rd_ind(dev, cp->shmem_base +
  3660. BNX2_PORT_HW_CFG_ISCSI_MAC_UPPER);
  3661. dev->mac_addr[0] = (u8) (val >> 8);
  3662. dev->mac_addr[1] = (u8) val;
  3663. CNIC_WR(dev, BNX2_EMAC_MAC_MATCH4, val);
  3664. val = cnic_reg_rd_ind(dev, cp->shmem_base +
  3665. BNX2_PORT_HW_CFG_ISCSI_MAC_LOWER);
  3666. dev->mac_addr[2] = (u8) (val >> 24);
  3667. dev->mac_addr[3] = (u8) (val >> 16);
  3668. dev->mac_addr[4] = (u8) (val >> 8);
  3669. dev->mac_addr[5] = (u8) val;
  3670. CNIC_WR(dev, BNX2_EMAC_MAC_MATCH5, val);
  3671. val = 4 | BNX2_RPM_SORT_USER2_BC_EN;
  3672. if (CHIP_NUM(cp) != CHIP_NUM_5709)
  3673. val |= BNX2_RPM_SORT_USER2_PROM_VLAN;
  3674. CNIC_WR(dev, BNX2_RPM_SORT_USER2, 0x0);
  3675. CNIC_WR(dev, BNX2_RPM_SORT_USER2, val);
  3676. CNIC_WR(dev, BNX2_RPM_SORT_USER2, val | BNX2_RPM_SORT_USER2_ENA);
  3677. }
  3678. static int cnic_start_bnx2_hw(struct cnic_dev *dev)
  3679. {
  3680. struct cnic_local *cp = dev->cnic_priv;
  3681. struct cnic_eth_dev *ethdev = cp->ethdev;
  3682. struct status_block *sblk = cp->status_blk.gen;
  3683. u32 val, kcq_cid_addr, kwq_cid_addr;
  3684. int err;
  3685. cnic_set_bnx2_mac(dev);
  3686. val = CNIC_RD(dev, BNX2_MQ_CONFIG);
  3687. val &= ~BNX2_MQ_CONFIG_KNL_BYP_BLK_SIZE;
  3688. if (BCM_PAGE_BITS > 12)
  3689. val |= (12 - 8) << 4;
  3690. else
  3691. val |= (BCM_PAGE_BITS - 8) << 4;
  3692. CNIC_WR(dev, BNX2_MQ_CONFIG, val);
  3693. CNIC_WR(dev, BNX2_HC_COMP_PROD_TRIP, (2 << 16) | 8);
  3694. CNIC_WR(dev, BNX2_HC_COM_TICKS, (64 << 16) | 220);
  3695. CNIC_WR(dev, BNX2_HC_CMD_TICKS, (64 << 16) | 220);
  3696. err = cnic_setup_5709_context(dev, 1);
  3697. if (err)
  3698. return err;
  3699. cnic_init_context(dev, KWQ_CID);
  3700. cnic_init_context(dev, KCQ_CID);
  3701. kwq_cid_addr = GET_CID_ADDR(KWQ_CID);
  3702. cp->kwq_io_addr = MB_GET_CID_ADDR(KWQ_CID) + L5_KRNLQ_HOST_QIDX;
  3703. cp->max_kwq_idx = MAX_KWQ_IDX;
  3704. cp->kwq_prod_idx = 0;
  3705. cp->kwq_con_idx = 0;
  3706. set_bit(CNIC_LCL_FL_KWQ_INIT, &cp->cnic_local_flags);
  3707. if (CHIP_NUM(cp) == CHIP_NUM_5706 || CHIP_NUM(cp) == CHIP_NUM_5708)
  3708. cp->kwq_con_idx_ptr = &sblk->status_rx_quick_consumer_index15;
  3709. else
  3710. cp->kwq_con_idx_ptr = &sblk->status_cmd_consumer_index;
  3711. /* Initialize the kernel work queue context. */
  3712. val = KRNLQ_TYPE_TYPE_KRNLQ | KRNLQ_SIZE_TYPE_SIZE |
  3713. (BCM_PAGE_BITS - 8) | KRNLQ_FLAGS_QE_SELF_SEQ;
  3714. cnic_ctx_wr(dev, kwq_cid_addr, L5_KRNLQ_TYPE, val);
  3715. val = (BCM_PAGE_SIZE / sizeof(struct kwqe) - 1) << 16;
  3716. cnic_ctx_wr(dev, kwq_cid_addr, L5_KRNLQ_QE_SELF_SEQ_MAX, val);
  3717. val = ((BCM_PAGE_SIZE / sizeof(struct kwqe)) << 16) | KWQ_PAGE_CNT;
  3718. cnic_ctx_wr(dev, kwq_cid_addr, L5_KRNLQ_PGTBL_NPAGES, val);
  3719. val = (u32) ((u64) cp->kwq_info.pgtbl_map >> 32);
  3720. cnic_ctx_wr(dev, kwq_cid_addr, L5_KRNLQ_PGTBL_HADDR_HI, val);
  3721. val = (u32) cp->kwq_info.pgtbl_map;
  3722. cnic_ctx_wr(dev, kwq_cid_addr, L5_KRNLQ_PGTBL_HADDR_LO, val);
  3723. kcq_cid_addr = GET_CID_ADDR(KCQ_CID);
  3724. cp->kcq1.io_addr = MB_GET_CID_ADDR(KCQ_CID) + L5_KRNLQ_HOST_QIDX;
  3725. cp->kcq1.sw_prod_idx = 0;
  3726. cp->kcq1.hw_prod_idx_ptr =
  3727. (u16 *) &sblk->status_completion_producer_index;
  3728. cp->kcq1.status_idx_ptr = (u16 *) &sblk->status_idx;
  3729. /* Initialize the kernel complete queue context. */
  3730. val = KRNLQ_TYPE_TYPE_KRNLQ | KRNLQ_SIZE_TYPE_SIZE |
  3731. (BCM_PAGE_BITS - 8) | KRNLQ_FLAGS_QE_SELF_SEQ;
  3732. cnic_ctx_wr(dev, kcq_cid_addr, L5_KRNLQ_TYPE, val);
  3733. val = (BCM_PAGE_SIZE / sizeof(struct kcqe) - 1) << 16;
  3734. cnic_ctx_wr(dev, kcq_cid_addr, L5_KRNLQ_QE_SELF_SEQ_MAX, val);
  3735. val = ((BCM_PAGE_SIZE / sizeof(struct kcqe)) << 16) | KCQ_PAGE_CNT;
  3736. cnic_ctx_wr(dev, kcq_cid_addr, L5_KRNLQ_PGTBL_NPAGES, val);
  3737. val = (u32) ((u64) cp->kcq1.dma.pgtbl_map >> 32);
  3738. cnic_ctx_wr(dev, kcq_cid_addr, L5_KRNLQ_PGTBL_HADDR_HI, val);
  3739. val = (u32) cp->kcq1.dma.pgtbl_map;
  3740. cnic_ctx_wr(dev, kcq_cid_addr, L5_KRNLQ_PGTBL_HADDR_LO, val);
  3741. cp->int_num = 0;
  3742. if (ethdev->drv_state & CNIC_DRV_STATE_USING_MSIX) {
  3743. struct status_block_msix *msblk = cp->status_blk.bnx2;
  3744. u32 sb_id = cp->status_blk_num;
  3745. u32 sb = BNX2_L2CTX_L5_STATUSB_NUM(sb_id);
  3746. cp->kcq1.hw_prod_idx_ptr =
  3747. (u16 *) &msblk->status_completion_producer_index;
  3748. cp->kcq1.status_idx_ptr = (u16 *) &msblk->status_idx;
  3749. cp->kwq_con_idx_ptr = (u16 *) &msblk->status_cmd_consumer_index;
  3750. cp->int_num = sb_id << BNX2_PCICFG_INT_ACK_CMD_INT_NUM_SHIFT;
  3751. cnic_ctx_wr(dev, kwq_cid_addr, L5_KRNLQ_HOST_QIDX, sb);
  3752. cnic_ctx_wr(dev, kcq_cid_addr, L5_KRNLQ_HOST_QIDX, sb);
  3753. }
  3754. /* Enable Commnad Scheduler notification when we write to the
  3755. * host producer index of the kernel contexts. */
  3756. CNIC_WR(dev, BNX2_MQ_KNL_CMD_MASK1, 2);
  3757. /* Enable Command Scheduler notification when we write to either
  3758. * the Send Queue or Receive Queue producer indexes of the kernel
  3759. * bypass contexts. */
  3760. CNIC_WR(dev, BNX2_MQ_KNL_BYP_CMD_MASK1, 7);
  3761. CNIC_WR(dev, BNX2_MQ_KNL_BYP_WRITE_MASK1, 7);
  3762. /* Notify COM when the driver post an application buffer. */
  3763. CNIC_WR(dev, BNX2_MQ_KNL_RX_V2P_MASK2, 0x2000);
  3764. /* Set the CP and COM doorbells. These two processors polls the
  3765. * doorbell for a non zero value before running. This must be done
  3766. * after setting up the kernel queue contexts. */
  3767. cnic_reg_wr_ind(dev, BNX2_CP_SCRATCH + 0x20, 1);
  3768. cnic_reg_wr_ind(dev, BNX2_COM_SCRATCH + 0x20, 1);
  3769. cnic_init_bnx2_tx_ring(dev);
  3770. cnic_init_bnx2_rx_ring(dev);
  3771. err = cnic_init_bnx2_irq(dev);
  3772. if (err) {
  3773. netdev_err(dev->netdev, "cnic_init_irq failed\n");
  3774. cnic_reg_wr_ind(dev, BNX2_CP_SCRATCH + 0x20, 0);
  3775. cnic_reg_wr_ind(dev, BNX2_COM_SCRATCH + 0x20, 0);
  3776. return err;
  3777. }
  3778. return 0;
  3779. }
  3780. static void cnic_setup_bnx2x_context(struct cnic_dev *dev)
  3781. {
  3782. struct cnic_local *cp = dev->cnic_priv;
  3783. struct cnic_eth_dev *ethdev = cp->ethdev;
  3784. u32 start_offset = ethdev->ctx_tbl_offset;
  3785. int i;
  3786. for (i = 0; i < cp->ctx_blks; i++) {
  3787. struct cnic_ctx *ctx = &cp->ctx_arr[i];
  3788. dma_addr_t map = ctx->mapping;
  3789. if (cp->ctx_align) {
  3790. unsigned long mask = cp->ctx_align - 1;
  3791. map = (map + mask) & ~mask;
  3792. }
  3793. cnic_ctx_tbl_wr(dev, start_offset + i, map);
  3794. }
  3795. }
  3796. static int cnic_init_bnx2x_irq(struct cnic_dev *dev)
  3797. {
  3798. struct cnic_local *cp = dev->cnic_priv;
  3799. struct cnic_eth_dev *ethdev = cp->ethdev;
  3800. int err = 0;
  3801. tasklet_init(&cp->cnic_irq_task, cnic_service_bnx2x_bh,
  3802. (unsigned long) dev);
  3803. if (ethdev->drv_state & CNIC_DRV_STATE_USING_MSIX)
  3804. err = cnic_request_irq(dev);
  3805. return err;
  3806. }
  3807. static inline void cnic_storm_memset_hc_disable(struct cnic_dev *dev,
  3808. u16 sb_id, u8 sb_index,
  3809. u8 disable)
  3810. {
  3811. u32 addr = BAR_CSTRORM_INTMEM +
  3812. CSTORM_STATUS_BLOCK_DATA_OFFSET(sb_id) +
  3813. offsetof(struct hc_status_block_data_e1x, index_data) +
  3814. sizeof(struct hc_index_data)*sb_index +
  3815. offsetof(struct hc_index_data, flags);
  3816. u16 flags = CNIC_RD16(dev, addr);
  3817. /* clear and set */
  3818. flags &= ~HC_INDEX_DATA_HC_ENABLED;
  3819. flags |= (((~disable) << HC_INDEX_DATA_HC_ENABLED_SHIFT) &
  3820. HC_INDEX_DATA_HC_ENABLED);
  3821. CNIC_WR16(dev, addr, flags);
  3822. }
  3823. static void cnic_enable_bnx2x_int(struct cnic_dev *dev)
  3824. {
  3825. struct cnic_local *cp = dev->cnic_priv;
  3826. u8 sb_id = cp->status_blk_num;
  3827. CNIC_WR8(dev, BAR_CSTRORM_INTMEM +
  3828. CSTORM_STATUS_BLOCK_DATA_OFFSET(sb_id) +
  3829. offsetof(struct hc_status_block_data_e1x, index_data) +
  3830. sizeof(struct hc_index_data)*HC_INDEX_ISCSI_EQ_CONS +
  3831. offsetof(struct hc_index_data, timeout), 64 / 4);
  3832. cnic_storm_memset_hc_disable(dev, sb_id, HC_INDEX_ISCSI_EQ_CONS, 0);
  3833. }
  3834. static void cnic_disable_bnx2x_int_sync(struct cnic_dev *dev)
  3835. {
  3836. }
  3837. static void cnic_init_bnx2x_tx_ring(struct cnic_dev *dev,
  3838. struct client_init_ramrod_data *data)
  3839. {
  3840. struct cnic_local *cp = dev->cnic_priv;
  3841. struct cnic_uio_dev *udev = cp->udev;
  3842. union eth_tx_bd_types *txbd = (union eth_tx_bd_types *) udev->l2_ring;
  3843. dma_addr_t buf_map, ring_map = udev->l2_ring_map;
  3844. struct host_sp_status_block *sb = cp->bnx2x_def_status_blk;
  3845. int i;
  3846. u32 cli = cp->ethdev->iscsi_l2_client_id;
  3847. u32 val;
  3848. memset(txbd, 0, BCM_PAGE_SIZE);
  3849. buf_map = udev->l2_buf_map;
  3850. for (i = 0; i < MAX_TX_DESC_CNT; i += 3, txbd += 3) {
  3851. struct eth_tx_start_bd *start_bd = &txbd->start_bd;
  3852. struct eth_tx_bd *reg_bd = &((txbd + 2)->reg_bd);
  3853. start_bd->addr_hi = cpu_to_le32((u64) buf_map >> 32);
  3854. start_bd->addr_lo = cpu_to_le32(buf_map & 0xffffffff);
  3855. reg_bd->addr_hi = start_bd->addr_hi;
  3856. reg_bd->addr_lo = start_bd->addr_lo + 0x10;
  3857. start_bd->nbytes = cpu_to_le16(0x10);
  3858. start_bd->nbd = cpu_to_le16(3);
  3859. start_bd->bd_flags.as_bitfield = ETH_TX_BD_FLAGS_START_BD;
  3860. start_bd->general_data = (UNICAST_ADDRESS <<
  3861. ETH_TX_START_BD_ETH_ADDR_TYPE_SHIFT);
  3862. start_bd->general_data |= (1 << ETH_TX_START_BD_HDR_NBDS_SHIFT);
  3863. }
  3864. val = (u64) ring_map >> 32;
  3865. txbd->next_bd.addr_hi = cpu_to_le32(val);
  3866. data->tx.tx_bd_page_base.hi = cpu_to_le32(val);
  3867. val = (u64) ring_map & 0xffffffff;
  3868. txbd->next_bd.addr_lo = cpu_to_le32(val);
  3869. data->tx.tx_bd_page_base.lo = cpu_to_le32(val);
  3870. /* Other ramrod params */
  3871. data->tx.tx_sb_index_number = HC_SP_INDEX_ETH_ISCSI_CQ_CONS;
  3872. data->tx.tx_status_block_id = BNX2X_DEF_SB_ID;
  3873. /* reset xstorm per client statistics */
  3874. if (cli < MAX_STAT_COUNTER_ID) {
  3875. data->general.statistics_zero_flg = 1;
  3876. data->general.statistics_en_flg = 1;
  3877. data->general.statistics_counter_id = cli;
  3878. }
  3879. cp->tx_cons_ptr =
  3880. &sb->sp_sb.index_values[HC_SP_INDEX_ETH_ISCSI_CQ_CONS];
  3881. }
  3882. static void cnic_init_bnx2x_rx_ring(struct cnic_dev *dev,
  3883. struct client_init_ramrod_data *data)
  3884. {
  3885. struct cnic_local *cp = dev->cnic_priv;
  3886. struct cnic_uio_dev *udev = cp->udev;
  3887. struct eth_rx_bd *rxbd = (struct eth_rx_bd *) (udev->l2_ring +
  3888. BCM_PAGE_SIZE);
  3889. struct eth_rx_cqe_next_page *rxcqe = (struct eth_rx_cqe_next_page *)
  3890. (udev->l2_ring + (2 * BCM_PAGE_SIZE));
  3891. struct host_sp_status_block *sb = cp->bnx2x_def_status_blk;
  3892. int i;
  3893. u32 cli = cp->ethdev->iscsi_l2_client_id;
  3894. int cl_qzone_id = BNX2X_CL_QZONE_ID(cp, cli);
  3895. u32 val;
  3896. dma_addr_t ring_map = udev->l2_ring_map;
  3897. /* General data */
  3898. data->general.client_id = cli;
  3899. data->general.activate_flg = 1;
  3900. data->general.sp_client_id = cli;
  3901. data->general.mtu = cpu_to_le16(cp->l2_single_buf_size - 14);
  3902. data->general.func_id = cp->pfid;
  3903. for (i = 0; i < BNX2X_MAX_RX_DESC_CNT; i++, rxbd++) {
  3904. dma_addr_t buf_map;
  3905. int n = (i % cp->l2_rx_ring_size) + 1;
  3906. buf_map = udev->l2_buf_map + (n * cp->l2_single_buf_size);
  3907. rxbd->addr_hi = cpu_to_le32((u64) buf_map >> 32);
  3908. rxbd->addr_lo = cpu_to_le32(buf_map & 0xffffffff);
  3909. }
  3910. val = (u64) (ring_map + BCM_PAGE_SIZE) >> 32;
  3911. rxbd->addr_hi = cpu_to_le32(val);
  3912. data->rx.bd_page_base.hi = cpu_to_le32(val);
  3913. val = (u64) (ring_map + BCM_PAGE_SIZE) & 0xffffffff;
  3914. rxbd->addr_lo = cpu_to_le32(val);
  3915. data->rx.bd_page_base.lo = cpu_to_le32(val);
  3916. rxcqe += BNX2X_MAX_RCQ_DESC_CNT;
  3917. val = (u64) (ring_map + (2 * BCM_PAGE_SIZE)) >> 32;
  3918. rxcqe->addr_hi = cpu_to_le32(val);
  3919. data->rx.cqe_page_base.hi = cpu_to_le32(val);
  3920. val = (u64) (ring_map + (2 * BCM_PAGE_SIZE)) & 0xffffffff;
  3921. rxcqe->addr_lo = cpu_to_le32(val);
  3922. data->rx.cqe_page_base.lo = cpu_to_le32(val);
  3923. /* Other ramrod params */
  3924. data->rx.client_qzone_id = cl_qzone_id;
  3925. data->rx.rx_sb_index_number = HC_SP_INDEX_ETH_ISCSI_RX_CQ_CONS;
  3926. data->rx.status_block_id = BNX2X_DEF_SB_ID;
  3927. data->rx.cache_line_alignment_log_size = L1_CACHE_SHIFT;
  3928. data->rx.max_bytes_on_bd = cpu_to_le16(cp->l2_single_buf_size);
  3929. data->rx.outer_vlan_removal_enable_flg = 1;
  3930. data->rx.silent_vlan_removal_flg = 1;
  3931. data->rx.silent_vlan_value = 0;
  3932. data->rx.silent_vlan_mask = 0xffff;
  3933. cp->rx_cons_ptr =
  3934. &sb->sp_sb.index_values[HC_SP_INDEX_ETH_ISCSI_RX_CQ_CONS];
  3935. cp->rx_cons = *cp->rx_cons_ptr;
  3936. }
  3937. static void cnic_init_bnx2x_kcq(struct cnic_dev *dev)
  3938. {
  3939. struct cnic_local *cp = dev->cnic_priv;
  3940. u32 pfid = cp->pfid;
  3941. cp->kcq1.io_addr = BAR_CSTRORM_INTMEM +
  3942. CSTORM_ISCSI_EQ_PROD_OFFSET(pfid, 0);
  3943. cp->kcq1.sw_prod_idx = 0;
  3944. if (BNX2X_CHIP_IS_E2_PLUS(cp->chip_id)) {
  3945. struct host_hc_status_block_e2 *sb = cp->status_blk.gen;
  3946. cp->kcq1.hw_prod_idx_ptr =
  3947. &sb->sb.index_values[HC_INDEX_ISCSI_EQ_CONS];
  3948. cp->kcq1.status_idx_ptr =
  3949. &sb->sb.running_index[SM_RX_ID];
  3950. } else {
  3951. struct host_hc_status_block_e1x *sb = cp->status_blk.gen;
  3952. cp->kcq1.hw_prod_idx_ptr =
  3953. &sb->sb.index_values[HC_INDEX_ISCSI_EQ_CONS];
  3954. cp->kcq1.status_idx_ptr =
  3955. &sb->sb.running_index[SM_RX_ID];
  3956. }
  3957. if (BNX2X_CHIP_IS_E2_PLUS(cp->chip_id)) {
  3958. struct host_hc_status_block_e2 *sb = cp->status_blk.gen;
  3959. cp->kcq2.io_addr = BAR_USTRORM_INTMEM +
  3960. USTORM_FCOE_EQ_PROD_OFFSET(pfid);
  3961. cp->kcq2.sw_prod_idx = 0;
  3962. cp->kcq2.hw_prod_idx_ptr =
  3963. &sb->sb.index_values[HC_INDEX_FCOE_EQ_CONS];
  3964. cp->kcq2.status_idx_ptr =
  3965. &sb->sb.running_index[SM_RX_ID];
  3966. }
  3967. }
  3968. static int cnic_start_bnx2x_hw(struct cnic_dev *dev)
  3969. {
  3970. struct cnic_local *cp = dev->cnic_priv;
  3971. struct cnic_eth_dev *ethdev = cp->ethdev;
  3972. int func = CNIC_FUNC(cp), ret;
  3973. u32 pfid;
  3974. cp->port_mode = CHIP_PORT_MODE_NONE;
  3975. if (BNX2X_CHIP_IS_E2_PLUS(cp->chip_id)) {
  3976. u32 val = CNIC_RD(dev, MISC_REG_PORT4MODE_EN_OVWR);
  3977. if (!(val & 1))
  3978. val = CNIC_RD(dev, MISC_REG_PORT4MODE_EN);
  3979. else
  3980. val = (val >> 1) & 1;
  3981. if (val) {
  3982. cp->port_mode = CHIP_4_PORT_MODE;
  3983. cp->pfid = func >> 1;
  3984. } else {
  3985. cp->port_mode = CHIP_2_PORT_MODE;
  3986. cp->pfid = func & 0x6;
  3987. }
  3988. } else {
  3989. cp->pfid = func;
  3990. }
  3991. pfid = cp->pfid;
  3992. ret = cnic_init_id_tbl(&cp->cid_tbl, MAX_ISCSI_TBL_SZ,
  3993. cp->iscsi_start_cid, 0);
  3994. if (ret)
  3995. return -ENOMEM;
  3996. if (BNX2X_CHIP_IS_E2_PLUS(cp->chip_id)) {
  3997. ret = cnic_init_id_tbl(&cp->fcoe_cid_tbl, dev->max_fcoe_conn,
  3998. cp->fcoe_start_cid, 0);
  3999. if (ret)
  4000. return -ENOMEM;
  4001. }
  4002. cp->bnx2x_igu_sb_id = ethdev->irq_arr[0].status_blk_num2;
  4003. cnic_init_bnx2x_kcq(dev);
  4004. /* Only 1 EQ */
  4005. CNIC_WR16(dev, cp->kcq1.io_addr, MAX_KCQ_IDX);
  4006. CNIC_WR(dev, BAR_CSTRORM_INTMEM +
  4007. CSTORM_ISCSI_EQ_CONS_OFFSET(pfid, 0), 0);
  4008. CNIC_WR(dev, BAR_CSTRORM_INTMEM +
  4009. CSTORM_ISCSI_EQ_NEXT_PAGE_ADDR_OFFSET(pfid, 0),
  4010. cp->kcq1.dma.pg_map_arr[1] & 0xffffffff);
  4011. CNIC_WR(dev, BAR_CSTRORM_INTMEM +
  4012. CSTORM_ISCSI_EQ_NEXT_PAGE_ADDR_OFFSET(pfid, 0) + 4,
  4013. (u64) cp->kcq1.dma.pg_map_arr[1] >> 32);
  4014. CNIC_WR(dev, BAR_CSTRORM_INTMEM +
  4015. CSTORM_ISCSI_EQ_NEXT_EQE_ADDR_OFFSET(pfid, 0),
  4016. cp->kcq1.dma.pg_map_arr[0] & 0xffffffff);
  4017. CNIC_WR(dev, BAR_CSTRORM_INTMEM +
  4018. CSTORM_ISCSI_EQ_NEXT_EQE_ADDR_OFFSET(pfid, 0) + 4,
  4019. (u64) cp->kcq1.dma.pg_map_arr[0] >> 32);
  4020. CNIC_WR8(dev, BAR_CSTRORM_INTMEM +
  4021. CSTORM_ISCSI_EQ_NEXT_PAGE_ADDR_VALID_OFFSET(pfid, 0), 1);
  4022. CNIC_WR16(dev, BAR_CSTRORM_INTMEM +
  4023. CSTORM_ISCSI_EQ_SB_NUM_OFFSET(pfid, 0), cp->status_blk_num);
  4024. CNIC_WR8(dev, BAR_CSTRORM_INTMEM +
  4025. CSTORM_ISCSI_EQ_SB_INDEX_OFFSET(pfid, 0),
  4026. HC_INDEX_ISCSI_EQ_CONS);
  4027. CNIC_WR(dev, BAR_USTRORM_INTMEM +
  4028. USTORM_ISCSI_GLOBAL_BUF_PHYS_ADDR_OFFSET(pfid),
  4029. cp->gbl_buf_info.pg_map_arr[0] & 0xffffffff);
  4030. CNIC_WR(dev, BAR_USTRORM_INTMEM +
  4031. USTORM_ISCSI_GLOBAL_BUF_PHYS_ADDR_OFFSET(pfid) + 4,
  4032. (u64) cp->gbl_buf_info.pg_map_arr[0] >> 32);
  4033. CNIC_WR(dev, BAR_TSTRORM_INTMEM +
  4034. TSTORM_ISCSI_TCP_LOCAL_ADV_WND_OFFSET(pfid), DEF_RCV_BUF);
  4035. cnic_setup_bnx2x_context(dev);
  4036. ret = cnic_init_bnx2x_irq(dev);
  4037. if (ret)
  4038. return ret;
  4039. return 0;
  4040. }
  4041. static void cnic_init_rings(struct cnic_dev *dev)
  4042. {
  4043. struct cnic_local *cp = dev->cnic_priv;
  4044. struct cnic_uio_dev *udev = cp->udev;
  4045. if (test_bit(CNIC_LCL_FL_RINGS_INITED, &cp->cnic_local_flags))
  4046. return;
  4047. if (test_bit(CNIC_F_BNX2_CLASS, &dev->flags)) {
  4048. cnic_init_bnx2_tx_ring(dev);
  4049. cnic_init_bnx2_rx_ring(dev);
  4050. set_bit(CNIC_LCL_FL_RINGS_INITED, &cp->cnic_local_flags);
  4051. } else if (test_bit(CNIC_F_BNX2X_CLASS, &dev->flags)) {
  4052. u32 cli = cp->ethdev->iscsi_l2_client_id;
  4053. u32 cid = cp->ethdev->iscsi_l2_cid;
  4054. u32 cl_qzone_id;
  4055. struct client_init_ramrod_data *data;
  4056. union l5cm_specific_data l5_data;
  4057. struct ustorm_eth_rx_producers rx_prods = {0};
  4058. u32 off, i, *cid_ptr;
  4059. rx_prods.bd_prod = 0;
  4060. rx_prods.cqe_prod = BNX2X_MAX_RCQ_DESC_CNT;
  4061. barrier();
  4062. cl_qzone_id = BNX2X_CL_QZONE_ID(cp, cli);
  4063. off = BAR_USTRORM_INTMEM +
  4064. (BNX2X_CHIP_IS_E2_PLUS(cp->chip_id) ?
  4065. USTORM_RX_PRODS_E2_OFFSET(cl_qzone_id) :
  4066. USTORM_RX_PRODS_E1X_OFFSET(CNIC_PORT(cp), cli));
  4067. for (i = 0; i < sizeof(struct ustorm_eth_rx_producers) / 4; i++)
  4068. CNIC_WR(dev, off + i * 4, ((u32 *) &rx_prods)[i]);
  4069. set_bit(CNIC_LCL_FL_L2_WAIT, &cp->cnic_local_flags);
  4070. data = udev->l2_buf;
  4071. cid_ptr = udev->l2_buf + 12;
  4072. memset(data, 0, sizeof(*data));
  4073. cnic_init_bnx2x_tx_ring(dev, data);
  4074. cnic_init_bnx2x_rx_ring(dev, data);
  4075. l5_data.phy_address.lo = udev->l2_buf_map & 0xffffffff;
  4076. l5_data.phy_address.hi = (u64) udev->l2_buf_map >> 32;
  4077. set_bit(CNIC_LCL_FL_RINGS_INITED, &cp->cnic_local_flags);
  4078. cnic_submit_kwqe_16(dev, RAMROD_CMD_ID_ETH_CLIENT_SETUP,
  4079. cid, ETH_CONNECTION_TYPE, &l5_data);
  4080. i = 0;
  4081. while (test_bit(CNIC_LCL_FL_L2_WAIT, &cp->cnic_local_flags) &&
  4082. ++i < 10)
  4083. msleep(1);
  4084. if (test_bit(CNIC_LCL_FL_L2_WAIT, &cp->cnic_local_flags))
  4085. netdev_err(dev->netdev,
  4086. "iSCSI CLIENT_SETUP did not complete\n");
  4087. cnic_spq_completion(dev, DRV_CTL_RET_L2_SPQ_CREDIT_CMD, 1);
  4088. cnic_ring_ctl(dev, cid, cli, 1);
  4089. *cid_ptr = cid;
  4090. }
  4091. }
  4092. static void cnic_shutdown_rings(struct cnic_dev *dev)
  4093. {
  4094. struct cnic_local *cp = dev->cnic_priv;
  4095. struct cnic_uio_dev *udev = cp->udev;
  4096. void *rx_ring;
  4097. if (!test_bit(CNIC_LCL_FL_RINGS_INITED, &cp->cnic_local_flags))
  4098. return;
  4099. if (test_bit(CNIC_F_BNX2_CLASS, &dev->flags)) {
  4100. cnic_shutdown_bnx2_rx_ring(dev);
  4101. } else if (test_bit(CNIC_F_BNX2X_CLASS, &dev->flags)) {
  4102. u32 cli = cp->ethdev->iscsi_l2_client_id;
  4103. u32 cid = cp->ethdev->iscsi_l2_cid;
  4104. union l5cm_specific_data l5_data;
  4105. int i;
  4106. cnic_ring_ctl(dev, cid, cli, 0);
  4107. set_bit(CNIC_LCL_FL_L2_WAIT, &cp->cnic_local_flags);
  4108. l5_data.phy_address.lo = cli;
  4109. l5_data.phy_address.hi = 0;
  4110. cnic_submit_kwqe_16(dev, RAMROD_CMD_ID_ETH_HALT,
  4111. cid, ETH_CONNECTION_TYPE, &l5_data);
  4112. i = 0;
  4113. while (test_bit(CNIC_LCL_FL_L2_WAIT, &cp->cnic_local_flags) &&
  4114. ++i < 10)
  4115. msleep(1);
  4116. if (test_bit(CNIC_LCL_FL_L2_WAIT, &cp->cnic_local_flags))
  4117. netdev_err(dev->netdev,
  4118. "iSCSI CLIENT_HALT did not complete\n");
  4119. cnic_spq_completion(dev, DRV_CTL_RET_L2_SPQ_CREDIT_CMD, 1);
  4120. memset(&l5_data, 0, sizeof(l5_data));
  4121. cnic_submit_kwqe_16(dev, RAMROD_CMD_ID_COMMON_CFC_DEL,
  4122. cid, NONE_CONNECTION_TYPE, &l5_data);
  4123. msleep(10);
  4124. }
  4125. clear_bit(CNIC_LCL_FL_RINGS_INITED, &cp->cnic_local_flags);
  4126. rx_ring = udev->l2_ring + BCM_PAGE_SIZE;
  4127. memset(rx_ring, 0, BCM_PAGE_SIZE);
  4128. }
  4129. static int cnic_register_netdev(struct cnic_dev *dev)
  4130. {
  4131. struct cnic_local *cp = dev->cnic_priv;
  4132. struct cnic_eth_dev *ethdev = cp->ethdev;
  4133. int err;
  4134. if (!ethdev)
  4135. return -ENODEV;
  4136. if (ethdev->drv_state & CNIC_DRV_STATE_REGD)
  4137. return 0;
  4138. err = ethdev->drv_register_cnic(dev->netdev, cp->cnic_ops, dev);
  4139. if (err)
  4140. netdev_err(dev->netdev, "register_cnic failed\n");
  4141. return err;
  4142. }
  4143. static void cnic_unregister_netdev(struct cnic_dev *dev)
  4144. {
  4145. struct cnic_local *cp = dev->cnic_priv;
  4146. struct cnic_eth_dev *ethdev = cp->ethdev;
  4147. if (!ethdev)
  4148. return;
  4149. ethdev->drv_unregister_cnic(dev->netdev);
  4150. }
  4151. static int cnic_start_hw(struct cnic_dev *dev)
  4152. {
  4153. struct cnic_local *cp = dev->cnic_priv;
  4154. struct cnic_eth_dev *ethdev = cp->ethdev;
  4155. int err;
  4156. if (test_bit(CNIC_F_CNIC_UP, &dev->flags))
  4157. return -EALREADY;
  4158. dev->regview = ethdev->io_base;
  4159. pci_dev_get(dev->pcidev);
  4160. cp->func = PCI_FUNC(dev->pcidev->devfn);
  4161. cp->status_blk.gen = ethdev->irq_arr[0].status_blk;
  4162. cp->status_blk_num = ethdev->irq_arr[0].status_blk_num;
  4163. err = cp->alloc_resc(dev);
  4164. if (err) {
  4165. netdev_err(dev->netdev, "allocate resource failure\n");
  4166. goto err1;
  4167. }
  4168. err = cp->start_hw(dev);
  4169. if (err)
  4170. goto err1;
  4171. err = cnic_cm_open(dev);
  4172. if (err)
  4173. goto err1;
  4174. set_bit(CNIC_F_CNIC_UP, &dev->flags);
  4175. cp->enable_int(dev);
  4176. return 0;
  4177. err1:
  4178. cp->free_resc(dev);
  4179. pci_dev_put(dev->pcidev);
  4180. return err;
  4181. }
  4182. static void cnic_stop_bnx2_hw(struct cnic_dev *dev)
  4183. {
  4184. cnic_disable_bnx2_int_sync(dev);
  4185. cnic_reg_wr_ind(dev, BNX2_CP_SCRATCH + 0x20, 0);
  4186. cnic_reg_wr_ind(dev, BNX2_COM_SCRATCH + 0x20, 0);
  4187. cnic_init_context(dev, KWQ_CID);
  4188. cnic_init_context(dev, KCQ_CID);
  4189. cnic_setup_5709_context(dev, 0);
  4190. cnic_free_irq(dev);
  4191. cnic_free_resc(dev);
  4192. }
  4193. static void cnic_stop_bnx2x_hw(struct cnic_dev *dev)
  4194. {
  4195. struct cnic_local *cp = dev->cnic_priv;
  4196. cnic_free_irq(dev);
  4197. *cp->kcq1.hw_prod_idx_ptr = 0;
  4198. CNIC_WR(dev, BAR_CSTRORM_INTMEM +
  4199. CSTORM_ISCSI_EQ_CONS_OFFSET(cp->pfid, 0), 0);
  4200. CNIC_WR16(dev, cp->kcq1.io_addr, 0);
  4201. cnic_free_resc(dev);
  4202. }
  4203. static void cnic_stop_hw(struct cnic_dev *dev)
  4204. {
  4205. if (test_bit(CNIC_F_CNIC_UP, &dev->flags)) {
  4206. struct cnic_local *cp = dev->cnic_priv;
  4207. int i = 0;
  4208. /* Need to wait for the ring shutdown event to complete
  4209. * before clearing the CNIC_UP flag.
  4210. */
  4211. while (cp->udev->uio_dev != -1 && i < 15) {
  4212. msleep(100);
  4213. i++;
  4214. }
  4215. cnic_shutdown_rings(dev);
  4216. clear_bit(CNIC_F_CNIC_UP, &dev->flags);
  4217. rcu_assign_pointer(cp->ulp_ops[CNIC_ULP_L4], NULL);
  4218. synchronize_rcu();
  4219. cnic_cm_shutdown(dev);
  4220. cp->stop_hw(dev);
  4221. pci_dev_put(dev->pcidev);
  4222. }
  4223. }
  4224. static void cnic_free_dev(struct cnic_dev *dev)
  4225. {
  4226. int i = 0;
  4227. while ((atomic_read(&dev->ref_count) != 0) && i < 10) {
  4228. msleep(100);
  4229. i++;
  4230. }
  4231. if (atomic_read(&dev->ref_count) != 0)
  4232. netdev_err(dev->netdev, "Failed waiting for ref count to go to zero\n");
  4233. netdev_info(dev->netdev, "Removed CNIC device\n");
  4234. dev_put(dev->netdev);
  4235. kfree(dev);
  4236. }
  4237. static struct cnic_dev *cnic_alloc_dev(struct net_device *dev,
  4238. struct pci_dev *pdev)
  4239. {
  4240. struct cnic_dev *cdev;
  4241. struct cnic_local *cp;
  4242. int alloc_size;
  4243. alloc_size = sizeof(struct cnic_dev) + sizeof(struct cnic_local);
  4244. cdev = kzalloc(alloc_size , GFP_KERNEL);
  4245. if (cdev == NULL) {
  4246. netdev_err(dev, "allocate dev struct failure\n");
  4247. return NULL;
  4248. }
  4249. cdev->netdev = dev;
  4250. cdev->cnic_priv = (char *)cdev + sizeof(struct cnic_dev);
  4251. cdev->register_device = cnic_register_device;
  4252. cdev->unregister_device = cnic_unregister_device;
  4253. cdev->iscsi_nl_msg_recv = cnic_iscsi_nl_msg_recv;
  4254. cp = cdev->cnic_priv;
  4255. cp->dev = cdev;
  4256. cp->l2_single_buf_size = 0x400;
  4257. cp->l2_rx_ring_size = 3;
  4258. spin_lock_init(&cp->cnic_ulp_lock);
  4259. netdev_info(dev, "Added CNIC device\n");
  4260. return cdev;
  4261. }
  4262. static struct cnic_dev *init_bnx2_cnic(struct net_device *dev)
  4263. {
  4264. struct pci_dev *pdev;
  4265. struct cnic_dev *cdev;
  4266. struct cnic_local *cp;
  4267. struct cnic_eth_dev *ethdev = NULL;
  4268. struct cnic_eth_dev *(*probe)(struct net_device *) = NULL;
  4269. probe = symbol_get(bnx2_cnic_probe);
  4270. if (probe) {
  4271. ethdev = (*probe)(dev);
  4272. symbol_put(bnx2_cnic_probe);
  4273. }
  4274. if (!ethdev)
  4275. return NULL;
  4276. pdev = ethdev->pdev;
  4277. if (!pdev)
  4278. return NULL;
  4279. dev_hold(dev);
  4280. pci_dev_get(pdev);
  4281. if ((pdev->device == PCI_DEVICE_ID_NX2_5709 ||
  4282. pdev->device == PCI_DEVICE_ID_NX2_5709S) &&
  4283. (pdev->revision < 0x10)) {
  4284. pci_dev_put(pdev);
  4285. goto cnic_err;
  4286. }
  4287. pci_dev_put(pdev);
  4288. cdev = cnic_alloc_dev(dev, pdev);
  4289. if (cdev == NULL)
  4290. goto cnic_err;
  4291. set_bit(CNIC_F_BNX2_CLASS, &cdev->flags);
  4292. cdev->submit_kwqes = cnic_submit_bnx2_kwqes;
  4293. cp = cdev->cnic_priv;
  4294. cp->ethdev = ethdev;
  4295. cdev->pcidev = pdev;
  4296. cp->chip_id = ethdev->chip_id;
  4297. cdev->max_iscsi_conn = ethdev->max_iscsi_conn;
  4298. cp->cnic_ops = &cnic_bnx2_ops;
  4299. cp->start_hw = cnic_start_bnx2_hw;
  4300. cp->stop_hw = cnic_stop_bnx2_hw;
  4301. cp->setup_pgtbl = cnic_setup_page_tbl;
  4302. cp->alloc_resc = cnic_alloc_bnx2_resc;
  4303. cp->free_resc = cnic_free_resc;
  4304. cp->start_cm = cnic_cm_init_bnx2_hw;
  4305. cp->stop_cm = cnic_cm_stop_bnx2_hw;
  4306. cp->enable_int = cnic_enable_bnx2_int;
  4307. cp->disable_int_sync = cnic_disable_bnx2_int_sync;
  4308. cp->close_conn = cnic_close_bnx2_conn;
  4309. return cdev;
  4310. cnic_err:
  4311. dev_put(dev);
  4312. return NULL;
  4313. }
  4314. static struct cnic_dev *init_bnx2x_cnic(struct net_device *dev)
  4315. {
  4316. struct pci_dev *pdev;
  4317. struct cnic_dev *cdev;
  4318. struct cnic_local *cp;
  4319. struct cnic_eth_dev *ethdev = NULL;
  4320. struct cnic_eth_dev *(*probe)(struct net_device *) = NULL;
  4321. probe = symbol_get(bnx2x_cnic_probe);
  4322. if (probe) {
  4323. ethdev = (*probe)(dev);
  4324. symbol_put(bnx2x_cnic_probe);
  4325. }
  4326. if (!ethdev)
  4327. return NULL;
  4328. pdev = ethdev->pdev;
  4329. if (!pdev)
  4330. return NULL;
  4331. dev_hold(dev);
  4332. cdev = cnic_alloc_dev(dev, pdev);
  4333. if (cdev == NULL) {
  4334. dev_put(dev);
  4335. return NULL;
  4336. }
  4337. set_bit(CNIC_F_BNX2X_CLASS, &cdev->flags);
  4338. cdev->submit_kwqes = cnic_submit_bnx2x_kwqes;
  4339. cp = cdev->cnic_priv;
  4340. cp->ethdev = ethdev;
  4341. cdev->pcidev = pdev;
  4342. cp->chip_id = ethdev->chip_id;
  4343. if (!(ethdev->drv_state & CNIC_DRV_STATE_NO_ISCSI))
  4344. cdev->max_iscsi_conn = ethdev->max_iscsi_conn;
  4345. if (BNX2X_CHIP_IS_E2_PLUS(cp->chip_id) &&
  4346. !(ethdev->drv_state & CNIC_DRV_STATE_NO_FCOE))
  4347. cdev->max_fcoe_conn = ethdev->max_fcoe_conn;
  4348. if (cdev->max_fcoe_conn > BNX2X_FCOE_NUM_CONNECTIONS)
  4349. cdev->max_fcoe_conn = BNX2X_FCOE_NUM_CONNECTIONS;
  4350. memcpy(cdev->mac_addr, ethdev->iscsi_mac, 6);
  4351. cp->cnic_ops = &cnic_bnx2x_ops;
  4352. cp->start_hw = cnic_start_bnx2x_hw;
  4353. cp->stop_hw = cnic_stop_bnx2x_hw;
  4354. cp->setup_pgtbl = cnic_setup_page_tbl_le;
  4355. cp->alloc_resc = cnic_alloc_bnx2x_resc;
  4356. cp->free_resc = cnic_free_resc;
  4357. cp->start_cm = cnic_cm_init_bnx2x_hw;
  4358. cp->stop_cm = cnic_cm_stop_bnx2x_hw;
  4359. cp->enable_int = cnic_enable_bnx2x_int;
  4360. cp->disable_int_sync = cnic_disable_bnx2x_int_sync;
  4361. if (BNX2X_CHIP_IS_E2_PLUS(cp->chip_id))
  4362. cp->ack_int = cnic_ack_bnx2x_e2_msix;
  4363. else
  4364. cp->ack_int = cnic_ack_bnx2x_msix;
  4365. cp->close_conn = cnic_close_bnx2x_conn;
  4366. return cdev;
  4367. }
  4368. static struct cnic_dev *is_cnic_dev(struct net_device *dev)
  4369. {
  4370. struct ethtool_drvinfo drvinfo;
  4371. struct cnic_dev *cdev = NULL;
  4372. if (dev->ethtool_ops && dev->ethtool_ops->get_drvinfo) {
  4373. memset(&drvinfo, 0, sizeof(drvinfo));
  4374. dev->ethtool_ops->get_drvinfo(dev, &drvinfo);
  4375. if (!strcmp(drvinfo.driver, "bnx2"))
  4376. cdev = init_bnx2_cnic(dev);
  4377. if (!strcmp(drvinfo.driver, "bnx2x"))
  4378. cdev = init_bnx2x_cnic(dev);
  4379. if (cdev) {
  4380. write_lock(&cnic_dev_lock);
  4381. list_add(&cdev->list, &cnic_dev_list);
  4382. write_unlock(&cnic_dev_lock);
  4383. }
  4384. }
  4385. return cdev;
  4386. }
  4387. static void cnic_rcv_netevent(struct cnic_local *cp, unsigned long event,
  4388. u16 vlan_id)
  4389. {
  4390. int if_type;
  4391. rcu_read_lock();
  4392. for (if_type = 0; if_type < MAX_CNIC_ULP_TYPE; if_type++) {
  4393. struct cnic_ulp_ops *ulp_ops;
  4394. void *ctx;
  4395. ulp_ops = rcu_dereference(cp->ulp_ops[if_type]);
  4396. if (!ulp_ops || !ulp_ops->indicate_netevent)
  4397. continue;
  4398. ctx = cp->ulp_handle[if_type];
  4399. ulp_ops->indicate_netevent(ctx, event, vlan_id);
  4400. }
  4401. rcu_read_unlock();
  4402. }
  4403. /**
  4404. * netdev event handler
  4405. */
  4406. static int cnic_netdev_event(struct notifier_block *this, unsigned long event,
  4407. void *ptr)
  4408. {
  4409. struct net_device *netdev = ptr;
  4410. struct cnic_dev *dev;
  4411. int new_dev = 0;
  4412. dev = cnic_from_netdev(netdev);
  4413. if (!dev && (event == NETDEV_REGISTER || netif_running(netdev))) {
  4414. /* Check for the hot-plug device */
  4415. dev = is_cnic_dev(netdev);
  4416. if (dev) {
  4417. new_dev = 1;
  4418. cnic_hold(dev);
  4419. }
  4420. }
  4421. if (dev) {
  4422. struct cnic_local *cp = dev->cnic_priv;
  4423. if (new_dev)
  4424. cnic_ulp_init(dev);
  4425. else if (event == NETDEV_UNREGISTER)
  4426. cnic_ulp_exit(dev);
  4427. if (event == NETDEV_UP || (new_dev && netif_running(netdev))) {
  4428. if (cnic_register_netdev(dev) != 0) {
  4429. cnic_put(dev);
  4430. goto done;
  4431. }
  4432. if (!cnic_start_hw(dev))
  4433. cnic_ulp_start(dev);
  4434. }
  4435. cnic_rcv_netevent(cp, event, 0);
  4436. if (event == NETDEV_GOING_DOWN) {
  4437. cnic_ulp_stop(dev);
  4438. cnic_stop_hw(dev);
  4439. cnic_unregister_netdev(dev);
  4440. } else if (event == NETDEV_UNREGISTER) {
  4441. write_lock(&cnic_dev_lock);
  4442. list_del_init(&dev->list);
  4443. write_unlock(&cnic_dev_lock);
  4444. cnic_put(dev);
  4445. cnic_free_dev(dev);
  4446. goto done;
  4447. }
  4448. cnic_put(dev);
  4449. } else {
  4450. struct net_device *realdev;
  4451. u16 vid;
  4452. vid = cnic_get_vlan(netdev, &realdev);
  4453. if (realdev) {
  4454. dev = cnic_from_netdev(realdev);
  4455. if (dev) {
  4456. vid |= VLAN_TAG_PRESENT;
  4457. cnic_rcv_netevent(dev->cnic_priv, event, vid);
  4458. cnic_put(dev);
  4459. }
  4460. }
  4461. }
  4462. done:
  4463. return NOTIFY_DONE;
  4464. }
  4465. static struct notifier_block cnic_netdev_notifier = {
  4466. .notifier_call = cnic_netdev_event
  4467. };
  4468. static void cnic_release(void)
  4469. {
  4470. struct cnic_dev *dev;
  4471. struct cnic_uio_dev *udev;
  4472. while (!list_empty(&cnic_dev_list)) {
  4473. dev = list_entry(cnic_dev_list.next, struct cnic_dev, list);
  4474. if (test_bit(CNIC_F_CNIC_UP, &dev->flags)) {
  4475. cnic_ulp_stop(dev);
  4476. cnic_stop_hw(dev);
  4477. }
  4478. cnic_ulp_exit(dev);
  4479. cnic_unregister_netdev(dev);
  4480. list_del_init(&dev->list);
  4481. cnic_free_dev(dev);
  4482. }
  4483. while (!list_empty(&cnic_udev_list)) {
  4484. udev = list_entry(cnic_udev_list.next, struct cnic_uio_dev,
  4485. list);
  4486. cnic_free_uio(udev);
  4487. }
  4488. }
  4489. static int __init cnic_init(void)
  4490. {
  4491. int rc = 0;
  4492. pr_info("%s", version);
  4493. rc = register_netdevice_notifier(&cnic_netdev_notifier);
  4494. if (rc) {
  4495. cnic_release();
  4496. return rc;
  4497. }
  4498. cnic_wq = create_singlethread_workqueue("cnic_wq");
  4499. if (!cnic_wq) {
  4500. cnic_release();
  4501. unregister_netdevice_notifier(&cnic_netdev_notifier);
  4502. return -ENOMEM;
  4503. }
  4504. return 0;
  4505. }
  4506. static void __exit cnic_exit(void)
  4507. {
  4508. unregister_netdevice_notifier(&cnic_netdev_notifier);
  4509. cnic_release();
  4510. destroy_workqueue(cnic_wq);
  4511. }
  4512. module_init(cnic_init);
  4513. module_exit(cnic_exit);