sdhci-tegra.c 8.3 KB

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  1. /*
  2. * Copyright (C) 2010 Google, Inc.
  3. *
  4. * This software is licensed under the terms of the GNU General Public
  5. * License version 2, as published by the Free Software Foundation, and
  6. * may be copied, distributed, and modified under those terms.
  7. *
  8. * This program is distributed in the hope that it will be useful,
  9. * but WITHOUT ANY WARRANTY; without even the implied warranty of
  10. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  11. * GNU General Public License for more details.
  12. *
  13. */
  14. #include <linux/err.h>
  15. #include <linux/module.h>
  16. #include <linux/init.h>
  17. #include <linux/platform_device.h>
  18. #include <linux/clk.h>
  19. #include <linux/io.h>
  20. #include <linux/of.h>
  21. #include <linux/of_gpio.h>
  22. #include <linux/gpio.h>
  23. #include <linux/mmc/card.h>
  24. #include <linux/mmc/host.h>
  25. #include <linux/module.h>
  26. #include <asm/gpio.h>
  27. #include <mach/gpio-tegra.h>
  28. #include <mach/sdhci.h>
  29. #include "sdhci-pltfm.h"
  30. static u32 tegra_sdhci_readl(struct sdhci_host *host, int reg)
  31. {
  32. u32 val;
  33. if (unlikely(reg == SDHCI_PRESENT_STATE)) {
  34. /* Use wp_gpio here instead? */
  35. val = readl(host->ioaddr + reg);
  36. return val | SDHCI_WRITE_PROTECT;
  37. }
  38. return readl(host->ioaddr + reg);
  39. }
  40. static u16 tegra_sdhci_readw(struct sdhci_host *host, int reg)
  41. {
  42. if (unlikely(reg == SDHCI_HOST_VERSION)) {
  43. /* Erratum: Version register is invalid in HW. */
  44. return SDHCI_SPEC_200;
  45. }
  46. return readw(host->ioaddr + reg);
  47. }
  48. static void tegra_sdhci_writel(struct sdhci_host *host, u32 val, int reg)
  49. {
  50. /* Seems like we're getting spurious timeout and crc errors, so
  51. * disable signalling of them. In case of real errors software
  52. * timers should take care of eventually detecting them.
  53. */
  54. if (unlikely(reg == SDHCI_SIGNAL_ENABLE))
  55. val &= ~(SDHCI_INT_TIMEOUT|SDHCI_INT_CRC);
  56. writel(val, host->ioaddr + reg);
  57. if (unlikely(reg == SDHCI_INT_ENABLE)) {
  58. /* Erratum: Must enable block gap interrupt detection */
  59. u8 gap_ctrl = readb(host->ioaddr + SDHCI_BLOCK_GAP_CONTROL);
  60. if (val & SDHCI_INT_CARD_INT)
  61. gap_ctrl |= 0x8;
  62. else
  63. gap_ctrl &= ~0x8;
  64. writeb(gap_ctrl, host->ioaddr + SDHCI_BLOCK_GAP_CONTROL);
  65. }
  66. }
  67. static unsigned int tegra_sdhci_get_ro(struct sdhci_host *sdhci)
  68. {
  69. struct sdhci_pltfm_host *pltfm_host = sdhci_priv(sdhci);
  70. struct tegra_sdhci_platform_data *plat = pltfm_host->priv;
  71. if (!gpio_is_valid(plat->wp_gpio))
  72. return -1;
  73. return gpio_get_value(plat->wp_gpio);
  74. }
  75. static irqreturn_t carddetect_irq(int irq, void *data)
  76. {
  77. struct sdhci_host *sdhost = (struct sdhci_host *)data;
  78. tasklet_schedule(&sdhost->card_tasklet);
  79. return IRQ_HANDLED;
  80. };
  81. static int tegra_sdhci_8bit(struct sdhci_host *host, int bus_width)
  82. {
  83. struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
  84. struct tegra_sdhci_platform_data *plat = pltfm_host->priv;
  85. u32 ctrl;
  86. ctrl = sdhci_readb(host, SDHCI_HOST_CONTROL);
  87. if (plat->is_8bit && bus_width == MMC_BUS_WIDTH_8) {
  88. ctrl &= ~SDHCI_CTRL_4BITBUS;
  89. ctrl |= SDHCI_CTRL_8BITBUS;
  90. } else {
  91. ctrl &= ~SDHCI_CTRL_8BITBUS;
  92. if (bus_width == MMC_BUS_WIDTH_4)
  93. ctrl |= SDHCI_CTRL_4BITBUS;
  94. else
  95. ctrl &= ~SDHCI_CTRL_4BITBUS;
  96. }
  97. sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL);
  98. return 0;
  99. }
  100. static struct sdhci_ops tegra_sdhci_ops = {
  101. .get_ro = tegra_sdhci_get_ro,
  102. .read_l = tegra_sdhci_readl,
  103. .read_w = tegra_sdhci_readw,
  104. .write_l = tegra_sdhci_writel,
  105. .platform_8bit_width = tegra_sdhci_8bit,
  106. };
  107. static struct sdhci_pltfm_data sdhci_tegra_pdata = {
  108. .quirks = SDHCI_QUIRK_BROKEN_TIMEOUT_VAL |
  109. SDHCI_QUIRK_SINGLE_POWER_WRITE |
  110. SDHCI_QUIRK_NO_HISPD_BIT |
  111. SDHCI_QUIRK_BROKEN_ADMA_ZEROLEN_DESC,
  112. .ops = &tegra_sdhci_ops,
  113. };
  114. static const struct of_device_id sdhci_tegra_dt_match[] __devinitdata = {
  115. { .compatible = "nvidia,tegra20-sdhci", },
  116. {}
  117. };
  118. MODULE_DEVICE_TABLE(of, sdhci_dt_ids);
  119. static struct tegra_sdhci_platform_data * __devinit sdhci_tegra_dt_parse_pdata(
  120. struct platform_device *pdev)
  121. {
  122. struct tegra_sdhci_platform_data *plat;
  123. struct device_node *np = pdev->dev.of_node;
  124. if (!np)
  125. return NULL;
  126. plat = devm_kzalloc(&pdev->dev, sizeof(*plat), GFP_KERNEL);
  127. if (!plat) {
  128. dev_err(&pdev->dev, "Can't allocate platform data\n");
  129. return NULL;
  130. }
  131. plat->cd_gpio = of_get_named_gpio(np, "cd-gpios", 0);
  132. plat->wp_gpio = of_get_named_gpio(np, "wp-gpios", 0);
  133. plat->power_gpio = of_get_named_gpio(np, "power-gpios", 0);
  134. if (of_find_property(np, "support-8bit", NULL))
  135. plat->is_8bit = 1;
  136. return plat;
  137. }
  138. static int __devinit sdhci_tegra_probe(struct platform_device *pdev)
  139. {
  140. struct sdhci_pltfm_host *pltfm_host;
  141. struct tegra_sdhci_platform_data *plat;
  142. struct sdhci_host *host;
  143. struct clk *clk;
  144. int rc;
  145. host = sdhci_pltfm_init(pdev, &sdhci_tegra_pdata);
  146. if (IS_ERR(host))
  147. return PTR_ERR(host);
  148. pltfm_host = sdhci_priv(host);
  149. plat = pdev->dev.platform_data;
  150. if (plat == NULL)
  151. plat = sdhci_tegra_dt_parse_pdata(pdev);
  152. if (plat == NULL) {
  153. dev_err(mmc_dev(host->mmc), "missing platform data\n");
  154. rc = -ENXIO;
  155. goto err_no_plat;
  156. }
  157. pltfm_host->priv = plat;
  158. if (gpio_is_valid(plat->power_gpio)) {
  159. rc = gpio_request(plat->power_gpio, "sdhci_power");
  160. if (rc) {
  161. dev_err(mmc_dev(host->mmc),
  162. "failed to allocate power gpio\n");
  163. goto err_power_req;
  164. }
  165. tegra_gpio_enable(plat->power_gpio);
  166. gpio_direction_output(plat->power_gpio, 1);
  167. }
  168. if (gpio_is_valid(plat->cd_gpio)) {
  169. rc = gpio_request(plat->cd_gpio, "sdhci_cd");
  170. if (rc) {
  171. dev_err(mmc_dev(host->mmc),
  172. "failed to allocate cd gpio\n");
  173. goto err_cd_req;
  174. }
  175. tegra_gpio_enable(plat->cd_gpio);
  176. gpio_direction_input(plat->cd_gpio);
  177. rc = request_irq(gpio_to_irq(plat->cd_gpio), carddetect_irq,
  178. IRQF_TRIGGER_FALLING | IRQF_TRIGGER_RISING,
  179. mmc_hostname(host->mmc), host);
  180. if (rc) {
  181. dev_err(mmc_dev(host->mmc), "request irq error\n");
  182. goto err_cd_irq_req;
  183. }
  184. }
  185. if (gpio_is_valid(plat->wp_gpio)) {
  186. rc = gpio_request(plat->wp_gpio, "sdhci_wp");
  187. if (rc) {
  188. dev_err(mmc_dev(host->mmc),
  189. "failed to allocate wp gpio\n");
  190. goto err_wp_req;
  191. }
  192. tegra_gpio_enable(plat->wp_gpio);
  193. gpio_direction_input(plat->wp_gpio);
  194. }
  195. clk = clk_get(mmc_dev(host->mmc), NULL);
  196. if (IS_ERR(clk)) {
  197. dev_err(mmc_dev(host->mmc), "clk err\n");
  198. rc = PTR_ERR(clk);
  199. goto err_clk_get;
  200. }
  201. clk_enable(clk);
  202. pltfm_host->clk = clk;
  203. host->mmc->pm_caps = plat->pm_flags;
  204. if (plat->is_8bit)
  205. host->mmc->caps |= MMC_CAP_8_BIT_DATA;
  206. rc = sdhci_add_host(host);
  207. if (rc)
  208. goto err_add_host;
  209. return 0;
  210. err_add_host:
  211. clk_disable(pltfm_host->clk);
  212. clk_put(pltfm_host->clk);
  213. err_clk_get:
  214. if (gpio_is_valid(plat->wp_gpio)) {
  215. tegra_gpio_disable(plat->wp_gpio);
  216. gpio_free(plat->wp_gpio);
  217. }
  218. err_wp_req:
  219. if (gpio_is_valid(plat->cd_gpio))
  220. free_irq(gpio_to_irq(plat->cd_gpio), host);
  221. err_cd_irq_req:
  222. if (gpio_is_valid(plat->cd_gpio)) {
  223. tegra_gpio_disable(plat->cd_gpio);
  224. gpio_free(plat->cd_gpio);
  225. }
  226. err_cd_req:
  227. if (gpio_is_valid(plat->power_gpio)) {
  228. tegra_gpio_disable(plat->power_gpio);
  229. gpio_free(plat->power_gpio);
  230. }
  231. err_power_req:
  232. err_no_plat:
  233. sdhci_pltfm_free(pdev);
  234. return rc;
  235. }
  236. static int __devexit sdhci_tegra_remove(struct platform_device *pdev)
  237. {
  238. struct sdhci_host *host = platform_get_drvdata(pdev);
  239. struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
  240. struct tegra_sdhci_platform_data *plat = pltfm_host->priv;
  241. int dead = (readl(host->ioaddr + SDHCI_INT_STATUS) == 0xffffffff);
  242. sdhci_remove_host(host, dead);
  243. if (gpio_is_valid(plat->wp_gpio)) {
  244. tegra_gpio_disable(plat->wp_gpio);
  245. gpio_free(plat->wp_gpio);
  246. }
  247. if (gpio_is_valid(plat->cd_gpio)) {
  248. free_irq(gpio_to_irq(plat->cd_gpio), host);
  249. tegra_gpio_disable(plat->cd_gpio);
  250. gpio_free(plat->cd_gpio);
  251. }
  252. if (gpio_is_valid(plat->power_gpio)) {
  253. tegra_gpio_disable(plat->power_gpio);
  254. gpio_free(plat->power_gpio);
  255. }
  256. clk_disable(pltfm_host->clk);
  257. clk_put(pltfm_host->clk);
  258. sdhci_pltfm_free(pdev);
  259. return 0;
  260. }
  261. static struct platform_driver sdhci_tegra_driver = {
  262. .driver = {
  263. .name = "sdhci-tegra",
  264. .owner = THIS_MODULE,
  265. .of_match_table = sdhci_tegra_dt_match,
  266. },
  267. .probe = sdhci_tegra_probe,
  268. .remove = __devexit_p(sdhci_tegra_remove),
  269. #ifdef CONFIG_PM
  270. .suspend = sdhci_pltfm_suspend,
  271. .resume = sdhci_pltfm_resume,
  272. #endif
  273. };
  274. static int __init sdhci_tegra_init(void)
  275. {
  276. return platform_driver_register(&sdhci_tegra_driver);
  277. }
  278. module_init(sdhci_tegra_init);
  279. static void __exit sdhci_tegra_exit(void)
  280. {
  281. platform_driver_unregister(&sdhci_tegra_driver);
  282. }
  283. module_exit(sdhci_tegra_exit);
  284. MODULE_DESCRIPTION("SDHCI driver for Tegra");
  285. MODULE_AUTHOR(" Google, Inc.");
  286. MODULE_LICENSE("GPL v2");